Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31205	1		T4	10		T5	10		T6	212
bark[1]	280	1		T2	14		T130	63		T45	21
bark[2]	680	1		T9	223		T101	21		T22	14
bark[3]	182	1		T103	21		T109	26		T120	85
bark[4]	343	1		T82	21		T130	21		T50	113
bark[5]	591	1		T180	14		T32	21		T41	21
bark[6]	173	1		T43	73		T133	30		T166	21
bark[7]	621	1		T3	14		T10	21		T13	21
bark[8]	308	1		T16	21		T103	21		T93	105
bark[9]	576	1		T10	66		T150	14		T94	5
bark[10]	266	1		T6	21		T7	38		T16	33
bark[11]	134	1		T1	14		T111	14		T50	21
bark[12]	448	1		T16	21		T29	14		T120	21
bark[13]	781	1		T14	14		T40	21		T44	288
bark[14]	742	1		T43	213		T22	30		T184	14
bark[15]	343	1		T8	156		T9	21		T16	30
bark[16]	371	1		T13	40		T32	26		T174	14
bark[17]	386	1		T142	78		T131	30		T28	21
bark[18]	431	1		T6	14		T8	26		T82	42
bark[19]	570	1		T6	38		T7	26		T9	179
bark[20]	1594	1		T42	235		T101	21		T131	14
bark[21]	414	1		T13	43		T16	5		T86	14
bark[22]	892	1		T9	30		T43	258		T135	55
bark[23]	545	1		T8	145		T42	183		T142	21
bark[24]	596	1		T7	21		T41	21		T82	30
bark[25]	159	1		T10	54		T15	14		T103	42
bark[26]	542	1		T147	26		T132	21		T25	125
bark[27]	409	1		T8	69		T40	52		T94	30
bark[28]	388	1		T6	42		T41	21		T83	14
bark[29]	447	1		T8	47		T13	40		T47	14
bark[30]	243	1		T88	26		T145	26		T168	14
bark[31]	218	1		T135	49		T140	35		T145	113
bark_0	4650	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	31554	1		T4	9		T5	9		T6	212
bite[1]	487	1		T40	51		T142	21		T131	13
bite[2]	581	1		T8	68		T13	21		T44	21
bite[3]	389	1		T41	21		T82	30		T130	39
bite[4]	373	1		T6	38		T32	47		T135	40
bite[5]	384	1		T42	234		T140	21		T28	21
bite[6]	898	1		T9	21		T47	13		T135	55
bite[7]	514	1		T14	13		T142	78		T101	21
bite[8]	466	1		T3	13		T8	155		T82	21
bite[9]	231	1		T15	13		T16	21		T43	35
bite[10]	320	1		T41	21		T119	13		T188	13
bite[11]	202	1		T7	47		T10	87		T25	21
bite[12]	679	1		T32	21		T40	21		T22	21
bite[13]	311	1		T22	30		T159	63		T124	13
bite[14]	215	1		T10	54		T131	30		T140	13
bite[15]	205	1		T27	21		T120	21		T50	21
bite[16]	564	1		T7	38		T8	21		T16	4
bite[17]	528	1		T6	42		T16	21		T41	21
bite[18]	654	1		T16	30		T101	21		T135	21
bite[19]	281	1		T6	21		T13	40		T83	13
bite[20]	266	1		T16	25		T43	30		T101	21
bite[21]	418	1		T86	39		T159	21		T145	26
bite[22]	647	1		T131	21		T132	30		T120	42
bite[23]	212	1		T16	6		T130	21		T28	21
bite[24]	337	1		T9	30		T183	13		T106	13
bite[25]	690	1		T6	13		T8	26		T86	44
bite[26]	745	1		T1	13		T9	178		T130	63
bite[27]	165	1		T13	43		T148	13		T121	21
bite[28]	142	1		T13	40		T180	13		T135	21
bite[29]	385	1		T8	25		T43	212		T45	21
bite[30]	719	1		T9	239		T86	13		T42	229
bite[31]	779	1		T2	13		T82	81		T42	30
bite_0	5187	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43719	1		T1	21		T2	21		T3	21
auto[1]	6809	1		T7	38		T8	83		T9	467

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	25	1		T82	23		T90	2		-	-
prescale[0]	1157	1		T6	51		T8	112		T9	19
prescale[1]	1190	1		T6	23		T10	19		T195	9
prescale[2]	808	1		T9	53		T13	40		T86	19
prescale[3]	829	1		T16	23		T42	19		T44	33
prescale[4]	1009	1		T40	36		T85	9		T135	9
prescale[5]	1064	1		T9	2		T16	9		T41	2
prescale[6]	586	1		T8	2		T41	28		T82	18
prescale[7]	489	1		T43	40		T130	19		T135	23
prescale[8]	609	1		T8	19		T9	49		T11	9
prescale[9]	1197	1		T16	161		T44	19		T150	23
prescale[10]	1392	1		T6	28		T32	19		T41	29
prescale[11]	680	1		T8	66		T13	19		T41	49
prescale[12]	645	1		T8	19		T9	24		T49	9
prescale[13]	871	1		T9	71		T32	23		T16	36
prescale[14]	1290	1		T7	57		T8	28		T10	32
prescale[15]	878	1		T7	28		T8	2		T16	21
prescale[16]	518	1		T6	19		T7	28		T8	4
prescale[17]	833	1		T16	66		T41	9		T142	36
prescale[18]	878	1		T7	40		T8	87		T86	45
prescale[19]	602	1		T8	19		T40	2		T41	2
prescale[20]	960	1		T6	19		T13	97		T16	45
prescale[21]	1194	1		T9	79		T16	206		T86	23
prescale[22]	1044	1		T8	71		T9	2		T32	19
prescale[23]	767	1		T8	28		T9	45		T13	19
prescale[24]	420	1		T8	30		T12	9		T40	2
prescale[25]	635	1		T48	9		T43	24		T130	19
prescale[26]	526	1		T10	19		T13	23		T32	37
prescale[27]	866	1		T9	9		T13	19		T82	28
prescale[28]	736	1		T8	28		T40	2		T142	52
prescale[29]	1005	1		T13	30		T40	4		T87	19
prescale[30]	828	1		T196	9		T16	43		T40	23
prescale[31]	1188	1		T10	18		T13	23		T41	61
prescale_0	22834	1		T1	21		T2	21		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37177	1		T1	9		T2	21		T3	9
auto[1]	13351	1		T1	12		T3	12		T6	88

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50528	1		T1	21		T2	21		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30911	1		T1	1		T2	1		T3	1
wkup[1]	193	1		T8	26		T42	21		T43	21
wkup[2]	356	1		T8	21		T13	21		T16	51
wkup[3]	206	1		T123	15		T27	24		T166	21
wkup[4]	189	1		T92	21		T120	21		T57	21
wkup[5]	433	1		T16	21		T43	51		T132	30
wkup[6]	162	1		T27	21		T134	21		T120	26
wkup[7]	183	1		T89	21		T58	40		T128	21
wkup[8]	128	1		T101	21		T27	21		T95	21
wkup[9]	212	1		T8	15		T42	21		T43	21
wkup[10]	199	1		T8	21		T13	21		T45	30
wkup[11]	287	1		T8	21		T40	42		T82	21
wkup[12]	363	1		T43	36		T150	30		T22	26
wkup[13]	211	1		T16	21		T43	21		T131	30
wkup[14]	169	1		T26	21		T88	8		T145	30
wkup[15]	188	1		T16	21		T43	21		T44	21
wkup[16]	207	1		T2	15		T16	26		T42	21
wkup[17]	239	1		T13	21		T16	21		T42	21
wkup[18]	355	1		T6	21		T7	47		T9	21
wkup[19]	334	1		T13	15		T47	15		T40	8
wkup[20]	281	1		T40	21		T42	42		T22	21
wkup[21]	272	1		T6	21		T8	21		T32	21
wkup[22]	335	1		T3	15		T8	21		T10	26
wkup[23]	360	1		T8	21		T16	8		T43	21
wkup[24]	129	1		T6	15		T9	21		T170	15
wkup[25]	281	1		T40	8		T130	21		T25	35
wkup[26]	391	1		T40	26		T130	21		T135	21
wkup[27]	343	1		T8	21		T40	31		T103	21
wkup[28]	249	1		T16	21		T25	21		T27	21
wkup[29]	315	1		T6	21		T81	15		T142	21
wkup[30]	292	1		T8	21		T40	8		T135	21
wkup[31]	240	1		T16	21		T44	15		T92	31
wkup[32]	147	1		T40	21		T135	21		T25	21
wkup[33]	215	1		T96	15		T45	21		T184	15
wkup[34]	183	1		T14	15		T16	21		T22	42
wkup[35]	231	1		T25	26		T151	30		T93	21
wkup[36]	317	1		T8	47		T40	21		T136	15
wkup[37]	275	1		T82	21		T103	30		T25	21
wkup[38]	281	1		T7	21		T82	30		T140	21
wkup[39]	284	1		T6	21		T7	21		T8	8
wkup[40]	227	1		T130	21		T44	21		T25	21
wkup[41]	278	1		T8	21		T22	15		T25	21
wkup[42]	240	1		T16	27		T43	21		T93	26
wkup[43]	151	1		T7	21		T43	26		T94	21
wkup[44]	181	1		T41	21		T45	21		T56	21
wkup[45]	190	1		T8	21		T22	30		T161	21
wkup[46]	233	1		T10	26		T180	15		T16	30
wkup[47]	130	1		T42	21		T29	15		T149	21
wkup[48]	298	1		T8	21		T103	21		T109	21
wkup[49]	308	1		T9	21		T42	21		T111	15
wkup[50]	201	1		T13	21		T41	21		T82	21
wkup[51]	471	1		T9	26		T15	15		T43	30
wkup[52]	269	1		T16	21		T43	35		T101	21
wkup[53]	194	1		T10	21		T25	8		T28	21
wkup[54]	421	1		T9	21		T86	44		T142	21
wkup[55]	205	1		T32	26		T135	21		T133	21
wkup[56]	250	1		T16	30		T25	21		T56	26
wkup[57]	173	1		T10	21		T42	21		T112	21
wkup[58]	273	1		T16	21		T43	26		T130	21
wkup[59]	248	1		T6	21		T16	21		T41	21
wkup[60]	234	1		T95	15		T120	52		T50	21
wkup[61]	349	1		T1	15		T10	26		T41	21
wkup[62]	135	1		T9	21		T42	21		T140	21
wkup[63]	226	1		T8	30		T13	21		T32	21
wkup_0	3697	1		T1	5		T2	5		T3	5