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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.79 99.33 93.67 100.00 98.40 99.51 47.82


Total test records in report: 421
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T39 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3134632743 Jul 26 06:38:16 PM PDT 24 Jul 26 06:38:17 PM PDT 24 292730460 ps
T283 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.64947782 Jul 26 06:37:58 PM PDT 24 Jul 26 06:37:59 PM PDT 24 451759028 ps
T284 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3459900834 Jul 26 06:38:48 PM PDT 24 Jul 26 06:38:49 PM PDT 24 360732018 ps
T285 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.807763061 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:45 PM PDT 24 979131805 ps
T34 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1663009724 Jul 26 06:38:31 PM PDT 24 Jul 26 06:38:32 PM PDT 24 532320128 ps
T35 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3169524629 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:54 PM PDT 24 4542799656 ps
T286 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1816262417 Jul 26 06:38:58 PM PDT 24 Jul 26 06:38:59 PM PDT 24 348776535 ps
T287 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1339689997 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:44 PM PDT 24 278789567 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2881756005 Jul 26 06:38:03 PM PDT 24 Jul 26 06:38:04 PM PDT 24 362352656 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3253317194 Jul 26 06:38:00 PM PDT 24 Jul 26 06:38:01 PM PDT 24 328641816 ps
T290 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3592228645 Jul 26 06:38:31 PM PDT 24 Jul 26 06:38:33 PM PDT 24 466092308 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.178395853 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:21 PM PDT 24 777918813 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1538263483 Jul 26 06:38:00 PM PDT 24 Jul 26 06:38:02 PM PDT 24 717155288 ps
T292 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4042375827 Jul 26 06:38:30 PM PDT 24 Jul 26 06:38:31 PM PDT 24 359568844 ps
T72 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3762855267 Jul 26 06:38:48 PM PDT 24 Jul 26 06:38:50 PM PDT 24 2662733284 ps
T36 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3511175238 Jul 26 06:38:18 PM PDT 24 Jul 26 06:38:22 PM PDT 24 8190499145 ps
T293 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.53384737 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 586513825 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.81078150 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:46 PM PDT 24 523697942 ps
T295 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1445498660 Jul 26 06:38:33 PM PDT 24 Jul 26 06:38:34 PM PDT 24 382305304 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1097944783 Jul 26 06:38:12 PM PDT 24 Jul 26 06:38:18 PM PDT 24 12656148258 ps
T296 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.203900045 Jul 26 06:39:01 PM PDT 24 Jul 26 06:39:01 PM PDT 24 441929163 ps
T297 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.10340099 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:45 PM PDT 24 426929156 ps
T298 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2696997 Jul 26 06:38:18 PM PDT 24 Jul 26 06:38:20 PM PDT 24 514682627 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2655163255 Jul 26 06:38:51 PM PDT 24 Jul 26 06:38:53 PM PDT 24 411027365 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2670459052 Jul 26 06:37:59 PM PDT 24 Jul 26 06:38:01 PM PDT 24 398271346 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2865252361 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:27 PM PDT 24 2240928701 ps
T75 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3643350682 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 2175690947 ps
T76 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1612243214 Jul 26 06:38:10 PM PDT 24 Jul 26 06:38:12 PM PDT 24 931850622 ps
T77 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2988823861 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 464479045 ps
T78 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1102981762 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:48 PM PDT 24 1037234078 ps
T300 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1062532386 Jul 26 06:38:23 PM PDT 24 Jul 26 06:38:23 PM PDT 24 465195279 ps
T79 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3813925056 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:46 PM PDT 24 2030064448 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2885306977 Jul 26 06:38:00 PM PDT 24 Jul 26 06:38:01 PM PDT 24 618155665 ps
T301 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3733425026 Jul 26 06:39:03 PM PDT 24 Jul 26 06:39:04 PM PDT 24 290049218 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3654158133 Jul 26 06:38:06 PM PDT 24 Jul 26 06:38:07 PM PDT 24 608110397 ps
T37 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3704638328 Jul 26 06:38:10 PM PDT 24 Jul 26 06:38:12 PM PDT 24 4136321728 ps
T302 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2928102344 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:58 PM PDT 24 443938020 ps
T80 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2857276223 Jul 26 06:38:32 PM PDT 24 Jul 26 06:38:34 PM PDT 24 1081935262 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3019095447 Jul 26 06:38:11 PM PDT 24 Jul 26 06:38:12 PM PDT 24 390139958 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3488173757 Jul 26 06:38:01 PM PDT 24 Jul 26 06:38:02 PM PDT 24 538574653 ps
T305 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3661506356 Jul 26 06:38:07 PM PDT 24 Jul 26 06:38:09 PM PDT 24 675397048 ps
T306 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.733497819 Jul 26 06:39:04 PM PDT 24 Jul 26 06:39:05 PM PDT 24 486624975 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.891830212 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:20 PM PDT 24 482815696 ps
T307 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2262142036 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:58 PM PDT 24 409556119 ps
T308 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.19575486 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:49 PM PDT 24 2410919994 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.803598041 Jul 26 06:38:45 PM PDT 24 Jul 26 06:38:52 PM PDT 24 4644810718 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3863014693 Jul 26 06:38:52 PM PDT 24 Jul 26 06:38:54 PM PDT 24 2351895499 ps
T311 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4034219451 Jul 26 06:38:05 PM PDT 24 Jul 26 06:38:06 PM PDT 24 367728951 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1636680566 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:41 PM PDT 24 14034346903 ps
T189 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2385289491 Jul 26 06:38:26 PM PDT 24 Jul 26 06:38:30 PM PDT 24 4517359131 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.449272440 Jul 26 06:38:04 PM PDT 24 Jul 26 06:38:05 PM PDT 24 398295660 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1184467570 Jul 26 06:38:11 PM PDT 24 Jul 26 06:38:12 PM PDT 24 424783000 ps
T67 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2683352930 Jul 26 06:38:32 PM PDT 24 Jul 26 06:38:33 PM PDT 24 324711654 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2333674996 Jul 26 06:38:04 PM PDT 24 Jul 26 06:38:08 PM PDT 24 8485478580 ps
T314 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2697511367 Jul 26 06:38:29 PM PDT 24 Jul 26 06:38:30 PM PDT 24 499839608 ps
T315 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1925599075 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:54 PM PDT 24 8430325060 ps
T316 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1231082513 Jul 26 06:38:31 PM PDT 24 Jul 26 06:38:33 PM PDT 24 424567464 ps
T317 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3366501688 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:27 PM PDT 24 562662264 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3968776775 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:45 PM PDT 24 369753776 ps
T319 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1931414072 Jul 26 06:38:05 PM PDT 24 Jul 26 06:38:06 PM PDT 24 1119984250 ps
T190 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1536062636 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:58 PM PDT 24 7676508067 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3718633700 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:45 PM PDT 24 362508790 ps
T321 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.433663232 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:58 PM PDT 24 510178569 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.542940 Jul 26 06:38:17 PM PDT 24 Jul 26 06:38:18 PM PDT 24 384392281 ps
T323 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.855807986 Jul 26 06:38:52 PM PDT 24 Jul 26 06:38:53 PM PDT 24 318561032 ps
T324 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.263822733 Jul 26 06:38:49 PM PDT 24 Jul 26 06:38:51 PM PDT 24 959107568 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2883157344 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:21 PM PDT 24 408145392 ps
T326 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3008196468 Jul 26 06:38:42 PM PDT 24 Jul 26 06:38:44 PM PDT 24 630846908 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4259926903 Jul 26 06:37:59 PM PDT 24 Jul 26 06:38:01 PM PDT 24 699369338 ps
T328 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.567068335 Jul 26 06:38:45 PM PDT 24 Jul 26 06:38:47 PM PDT 24 523552955 ps
T329 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2518073008 Jul 26 06:38:51 PM PDT 24 Jul 26 06:38:52 PM PDT 24 291022288 ps
T330 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2376676420 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:46 PM PDT 24 8511137234 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.393745798 Jul 26 06:38:12 PM PDT 24 Jul 26 06:38:13 PM PDT 24 383239131 ps
T331 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.862058110 Jul 26 06:38:03 PM PDT 24 Jul 26 06:38:04 PM PDT 24 289594833 ps
T332 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.508190304 Jul 26 06:38:59 PM PDT 24 Jul 26 06:39:00 PM PDT 24 349070311 ps
T333 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3257283607 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:48 PM PDT 24 4375828429 ps
T334 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2077029578 Jul 26 06:38:26 PM PDT 24 Jul 26 06:38:28 PM PDT 24 1258623388 ps
T335 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3659700415 Jul 26 06:38:02 PM PDT 24 Jul 26 06:38:03 PM PDT 24 628304880 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2238375399 Jul 26 06:38:06 PM PDT 24 Jul 26 06:38:09 PM PDT 24 8374179711 ps
T337 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.977980694 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:22 PM PDT 24 1014442170 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1076014999 Jul 26 06:38:04 PM PDT 24 Jul 26 06:38:07 PM PDT 24 1269804121 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1626349416 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:44 PM PDT 24 405152071 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.907353364 Jul 26 06:38:31 PM PDT 24 Jul 26 06:38:32 PM PDT 24 373611258 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3386288936 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:21 PM PDT 24 801901872 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3029607497 Jul 26 06:38:06 PM PDT 24 Jul 26 06:38:07 PM PDT 24 524886195 ps
T343 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1676531587 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:44 PM PDT 24 456830096 ps
T191 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2677993313 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:29 PM PDT 24 4155132878 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1337438430 Jul 26 06:38:17 PM PDT 24 Jul 26 06:38:19 PM PDT 24 330339615 ps
T345 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3590923472 Jul 26 06:38:17 PM PDT 24 Jul 26 06:38:19 PM PDT 24 859344754 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1177515403 Jul 26 06:38:51 PM PDT 24 Jul 26 06:38:52 PM PDT 24 488432938 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.826087764 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 1666280577 ps
T348 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.599973297 Jul 26 06:38:48 PM PDT 24 Jul 26 06:38:49 PM PDT 24 1385499467 ps
T349 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4218242321 Jul 26 06:39:01 PM PDT 24 Jul 26 06:39:02 PM PDT 24 428224676 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3235335916 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:20 PM PDT 24 310803410 ps
T351 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1792362612 Jul 26 06:39:01 PM PDT 24 Jul 26 06:39:03 PM PDT 24 506836344 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4042027206 Jul 26 06:38:49 PM PDT 24 Jul 26 06:38:50 PM PDT 24 543062296 ps
T353 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4071933539 Jul 26 06:38:49 PM PDT 24 Jul 26 06:38:50 PM PDT 24 330459466 ps
T354 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2727600767 Jul 26 06:38:45 PM PDT 24 Jul 26 06:38:53 PM PDT 24 4288059355 ps
T355 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1706991832 Jul 26 06:39:02 PM PDT 24 Jul 26 06:39:03 PM PDT 24 301993483 ps
T356 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1685997576 Jul 26 06:38:59 PM PDT 24 Jul 26 06:39:00 PM PDT 24 344529461 ps
T193 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1053118425 Jul 26 06:38:20 PM PDT 24 Jul 26 06:38:32 PM PDT 24 8218664057 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2192174704 Jul 26 06:37:58 PM PDT 24 Jul 26 06:37:59 PM PDT 24 731478785 ps
T358 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4191758262 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 504754845 ps
T359 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1069201489 Jul 26 06:38:17 PM PDT 24 Jul 26 06:38:18 PM PDT 24 514321307 ps
T360 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3731948973 Jul 26 06:38:59 PM PDT 24 Jul 26 06:39:00 PM PDT 24 397854304 ps
T361 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3722140002 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:58 PM PDT 24 341294274 ps
T362 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4121271408 Jul 26 06:38:31 PM PDT 24 Jul 26 06:38:35 PM PDT 24 8469694402 ps
T363 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3253980447 Jul 26 06:38:47 PM PDT 24 Jul 26 06:38:49 PM PDT 24 483781518 ps
T364 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4024353239 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:21 PM PDT 24 464833088 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.384419779 Jul 26 06:38:10 PM PDT 24 Jul 26 06:38:12 PM PDT 24 522819065 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3869097193 Jul 26 06:38:34 PM PDT 24 Jul 26 06:38:35 PM PDT 24 1641476613 ps
T366 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2129578475 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 337220124 ps
T367 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4267831754 Jul 26 06:38:55 PM PDT 24 Jul 26 06:38:56 PM PDT 24 464236229 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3492253118 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:22 PM PDT 24 2691048904 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3842509590 Jul 26 06:38:50 PM PDT 24 Jul 26 06:38:51 PM PDT 24 419558664 ps
T370 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3838395084 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:27 PM PDT 24 495394555 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.986482203 Jul 26 06:38:45 PM PDT 24 Jul 26 06:38:47 PM PDT 24 429923222 ps
T372 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3514963248 Jul 26 06:38:56 PM PDT 24 Jul 26 06:38:56 PM PDT 24 510787649 ps
T373 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4111067613 Jul 26 06:38:47 PM PDT 24 Jul 26 06:38:50 PM PDT 24 485639412 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.47200767 Jul 26 06:38:00 PM PDT 24 Jul 26 06:38:01 PM PDT 24 502339976 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1940168312 Jul 26 06:38:24 PM PDT 24 Jul 26 06:38:36 PM PDT 24 7566738072 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4082856637 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:49 PM PDT 24 430397568 ps
T377 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3499134337 Jul 26 06:38:47 PM PDT 24 Jul 26 06:38:48 PM PDT 24 441815118 ps
T378 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3230018910 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:59 PM PDT 24 506544122 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1986698834 Jul 26 06:38:51 PM PDT 24 Jul 26 06:38:53 PM PDT 24 1315472472 ps
T194 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1129963600 Jul 26 06:37:58 PM PDT 24 Jul 26 06:38:00 PM PDT 24 8098162067 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1086585620 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:45 PM PDT 24 486808214 ps
T381 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.284851497 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:26 PM PDT 24 498322210 ps
T382 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3124488565 Jul 26 06:38:51 PM PDT 24 Jul 26 06:38:52 PM PDT 24 464741141 ps
T383 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3196015254 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:59 PM PDT 24 474496056 ps
T384 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2333421905 Jul 26 06:39:02 PM PDT 24 Jul 26 06:39:04 PM PDT 24 328829894 ps
T385 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3466125898 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:47 PM PDT 24 344744146 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4199664998 Jul 26 06:38:29 PM PDT 24 Jul 26 06:38:30 PM PDT 24 440306822 ps
T387 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2474196018 Jul 26 06:38:32 PM PDT 24 Jul 26 06:38:33 PM PDT 24 363302502 ps
T388 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2784676200 Jul 26 06:38:54 PM PDT 24 Jul 26 06:38:54 PM PDT 24 347430372 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3422704444 Jul 26 06:38:06 PM PDT 24 Jul 26 06:38:07 PM PDT 24 487117674 ps
T390 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.261936303 Jul 26 06:38:22 PM PDT 24 Jul 26 06:38:24 PM PDT 24 513298170 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4294050987 Jul 26 06:38:43 PM PDT 24 Jul 26 06:38:45 PM PDT 24 522629591 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.957764484 Jul 26 06:38:22 PM PDT 24 Jul 26 06:38:23 PM PDT 24 407125364 ps
T393 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1416605627 Jul 26 06:38:44 PM PDT 24 Jul 26 06:38:51 PM PDT 24 4133763741 ps
T394 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.184246811 Jul 26 06:38:49 PM PDT 24 Jul 26 06:38:50 PM PDT 24 420190123 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1845628710 Jul 26 06:37:58 PM PDT 24 Jul 26 06:37:59 PM PDT 24 964162175 ps
T396 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.627391321 Jul 26 06:38:30 PM PDT 24 Jul 26 06:38:33 PM PDT 24 4214251166 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3920485581 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:48 PM PDT 24 501839999 ps
T398 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.452438944 Jul 26 06:38:56 PM PDT 24 Jul 26 06:38:58 PM PDT 24 425173111 ps
T399 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3539063798 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:47 PM PDT 24 540403019 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.766224012 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:23 PM PDT 24 2231707042 ps
T401 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1170296683 Jul 26 06:38:07 PM PDT 24 Jul 26 06:38:09 PM PDT 24 7964545985 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4201786350 Jul 26 06:38:10 PM PDT 24 Jul 26 06:38:12 PM PDT 24 348225211 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2490673584 Jul 26 06:38:18 PM PDT 24 Jul 26 06:38:20 PM PDT 24 411879905 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1467393777 Jul 26 06:38:07 PM PDT 24 Jul 26 06:38:08 PM PDT 24 456641689 ps
T404 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.143921351 Jul 26 06:38:58 PM PDT 24 Jul 26 06:38:59 PM PDT 24 350634172 ps
T405 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2125653667 Jul 26 06:38:46 PM PDT 24 Jul 26 06:38:49 PM PDT 24 669159042 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4033649256 Jul 26 06:38:32 PM PDT 24 Jul 26 06:38:34 PM PDT 24 333594776 ps
T71 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1996786635 Jul 26 06:38:30 PM PDT 24 Jul 26 06:38:31 PM PDT 24 493888201 ps
T407 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1293266588 Jul 26 06:38:23 PM PDT 24 Jul 26 06:38:24 PM PDT 24 319362935 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4024506008 Jul 26 06:38:12 PM PDT 24 Jul 26 06:38:14 PM PDT 24 549078035 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4221002039 Jul 26 06:37:58 PM PDT 24 Jul 26 06:37:59 PM PDT 24 531813585 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2057350456 Jul 26 06:38:04 PM PDT 24 Jul 26 06:38:05 PM PDT 24 464080156 ps
T192 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1326302761 Jul 26 06:38:18 PM PDT 24 Jul 26 06:38:22 PM PDT 24 8505825688 ps
T411 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.325612007 Jul 26 06:38:19 PM PDT 24 Jul 26 06:38:21 PM PDT 24 478403954 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.250674748 Jul 26 06:38:20 PM PDT 24 Jul 26 06:38:21 PM PDT 24 415860610 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.693932249 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:26 PM PDT 24 527835618 ps
T414 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.703561678 Jul 26 06:38:57 PM PDT 24 Jul 26 06:38:58 PM PDT 24 287231756 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.12005071 Jul 26 06:38:23 PM PDT 24 Jul 26 06:38:24 PM PDT 24 278987189 ps
T416 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1197974517 Jul 26 06:38:25 PM PDT 24 Jul 26 06:38:26 PM PDT 24 558073293 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1639666788 Jul 26 06:38:04 PM PDT 24 Jul 26 06:38:05 PM PDT 24 352613127 ps
T418 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.93515070 Jul 26 06:38:49 PM PDT 24 Jul 26 06:38:50 PM PDT 24 312905812 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.531721136 Jul 26 06:38:10 PM PDT 24 Jul 26 06:38:12 PM PDT 24 983674233 ps
T420 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.674555698 Jul 26 06:39:01 PM PDT 24 Jul 26 06:39:02 PM PDT 24 430892655 ps
T421 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1019645405 Jul 26 06:38:30 PM PDT 24 Jul 26 06:38:31 PM PDT 24 1676543549 ps

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.426484608
Short name T8
Test name
Test status
Simulation time 240424224232 ps
CPU time 869.16 seconds
Started Jul 26 06:37:23 PM PDT 24
Finished Jul 26 06:51:53 PM PDT 24
Peak memory 214800 kb
Host smart-5f812e4d-193f-46cf-aa1f-95a017124d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426484608 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.426484608
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2778913237
Short name T6
Test name
Test status
Simulation time 80359112313 ps
CPU time 103.81 seconds
Started Jul 26 06:37:20 PM PDT 24
Finished Jul 26 06:39:04 PM PDT 24
Peak memory 198204 kb
Host smart-dcbb2e2b-0f5a-47ec-ada3-a2eddcc46437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778913237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2778913237
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3169524629
Short name T35
Test name
Test status
Simulation time 4542799656 ps
CPU time 2.65 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:54 PM PDT 24
Peak memory 198464 kb
Host smart-a5b4eaf7-8080-494a-979b-db49799c2330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169524629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3169524629
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.390014421
Short name T50
Test name
Test status
Simulation time 119131032968 ps
CPU time 310.5 seconds
Started Jul 26 06:36:58 PM PDT 24
Finished Jul 26 06:42:09 PM PDT 24
Peak memory 201480 kb
Host smart-5cbbfd57-1085-46da-9ac7-30378e446338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390014421 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.390014421
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3181224358
Short name T120
Test name
Test status
Simulation time 299513305843 ps
CPU time 785.25 seconds
Started Jul 26 06:36:59 PM PDT 24
Finished Jul 26 06:50:04 PM PDT 24
Peak memory 207560 kb
Host smart-5eb8a2f0-5036-49f8-a54d-94100c92f0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181224358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3181224358
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3873484380
Short name T113
Test name
Test status
Simulation time 341286972910 ps
CPU time 358.3 seconds
Started Jul 26 06:36:44 PM PDT 24
Finished Jul 26 06:42:42 PM PDT 24
Peak memory 202188 kb
Host smart-8e82d27a-14cc-404e-a736-a4d0d612ac23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873484380 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3873484380
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4207696818
Short name T116
Test name
Test status
Simulation time 111685264926 ps
CPU time 385.43 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:44:10 PM PDT 24
Peak memory 213760 kb
Host smart-9e8156e9-95b0-4a6a-a77e-f731357616b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207696818 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4207696818
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.814427529
Short name T91
Test name
Test status
Simulation time 54096800927 ps
CPU time 297.48 seconds
Started Jul 26 06:36:54 PM PDT 24
Finished Jul 26 06:41:52 PM PDT 24
Peak memory 199408 kb
Host smart-2a6a9e68-2b1f-418c-b4c0-ef022cb67adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814427529 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.814427529
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3496051702
Short name T100
Test name
Test status
Simulation time 373091440405 ps
CPU time 452.02 seconds
Started Jul 26 06:37:13 PM PDT 24
Finished Jul 26 06:44:46 PM PDT 24
Peak memory 211620 kb
Host smart-11db5a1f-aab1-48ce-a144-368eec2970a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496051702 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3496051702
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3078585800
Short name T16
Test name
Test status
Simulation time 54189306925 ps
CPU time 542.32 seconds
Started Jul 26 06:37:14 PM PDT 24
Finished Jul 26 06:46:17 PM PDT 24
Peak memory 210212 kb
Host smart-3adb71f2-ef4b-43ae-9711-c29503635f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078585800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3078585800
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2578882296
Short name T58
Test name
Test status
Simulation time 28136945761 ps
CPU time 81.36 seconds
Started Jul 26 06:37:43 PM PDT 24
Finished Jul 26 06:39:04 PM PDT 24
Peak memory 198464 kb
Host smart-1da206cc-21c5-4249-9a6a-bb254dd6fd81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578882296 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2578882296
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.684932692
Short name T17
Test name
Test status
Simulation time 7619772250 ps
CPU time 3.64 seconds
Started Jul 26 06:36:43 PM PDT 24
Finished Jul 26 06:36:47 PM PDT 24
Peak memory 215804 kb
Host smart-a4d6658d-3c97-4346-aeaf-bdc5b2a4e4dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684932692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.684932692
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1474006117
Short name T56
Test name
Test status
Simulation time 277029530528 ps
CPU time 612.35 seconds
Started Jul 26 06:36:39 PM PDT 24
Finished Jul 26 06:46:52 PM PDT 24
Peak memory 214264 kb
Host smart-d0f10a9b-5227-48db-b2ae-da9c62a251bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474006117 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1474006117
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2250027046
Short name T94
Test name
Test status
Simulation time 61797190775 ps
CPU time 446.45 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:44:22 PM PDT 24
Peak memory 206624 kb
Host smart-ebb02b8d-e655-4219-908b-6d8eafab3663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250027046 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2250027046
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.549786116
Short name T133
Test name
Test status
Simulation time 97324674052 ps
CPU time 135.34 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:39:40 PM PDT 24
Peak memory 191832 kb
Host smart-e63d5092-b48e-4daf-8474-4d17a02ecec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549786116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.549786116
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3860540529
Short name T89
Test name
Test status
Simulation time 119695239798 ps
CPU time 661.16 seconds
Started Jul 26 06:37:38 PM PDT 24
Finished Jul 26 06:48:39 PM PDT 24
Peak memory 206624 kb
Host smart-dd682aa4-3e4f-4b97-91a8-a164f2f3b8fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860540529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3860540529
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.13473484
Short name T40
Test name
Test status
Simulation time 312561314926 ps
CPU time 286.18 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:42:38 PM PDT 24
Peak memory 214756 kb
Host smart-9174c227-efff-4633-b68d-573a865e534f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13473484 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.13473484
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1486206242
Short name T110
Test name
Test status
Simulation time 294987479973 ps
CPU time 260.07 seconds
Started Jul 26 06:37:59 PM PDT 24
Finished Jul 26 06:42:19 PM PDT 24
Peak memory 209148 kb
Host smart-1770f80e-f5cd-425a-a203-8685dfc9c1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486206242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1486206242
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4253269574
Short name T25
Test name
Test status
Simulation time 146888863379 ps
CPU time 413.23 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:43:44 PM PDT 24
Peak memory 206592 kb
Host smart-73170948-f8ca-4b2f-ac3f-4c518016d3a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253269574 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4253269574
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4138776269
Short name T90
Test name
Test status
Simulation time 100066163904 ps
CPU time 716.52 seconds
Started Jul 26 06:36:49 PM PDT 24
Finished Jul 26 06:48:46 PM PDT 24
Peak memory 203952 kb
Host smart-80762422-44b4-45cb-a017-9605020c1547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138776269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4138776269
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2835621923
Short name T27
Test name
Test status
Simulation time 290463698102 ps
CPU time 439.78 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:44:10 PM PDT 24
Peak memory 213800 kb
Host smart-04a0250a-b339-4b78-8509-a56d0dce07d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835621923 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2835621923
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3544562366
Short name T26
Test name
Test status
Simulation time 462527307048 ps
CPU time 706.52 seconds
Started Jul 26 06:37:21 PM PDT 24
Finished Jul 26 06:49:08 PM PDT 24
Peak memory 192932 kb
Host smart-78231cc6-240b-4525-9946-98da424062b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544562366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3544562366
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2102598471
Short name T128
Test name
Test status
Simulation time 30366711496 ps
CPU time 39.99 seconds
Started Jul 26 06:37:10 PM PDT 24
Finished Jul 26 06:37:50 PM PDT 24
Peak memory 192900 kb
Host smart-06092ea0-c6b1-4a51-8186-1ebb7008ec97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102598471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2102598471
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2270144573
Short name T28
Test name
Test status
Simulation time 92032647510 ps
CPU time 66.83 seconds
Started Jul 26 06:37:46 PM PDT 24
Finished Jul 26 06:38:53 PM PDT 24
Peak memory 198224 kb
Host smart-80eef266-bc36-491a-b88e-704e68bcc527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270144573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2270144573
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1209604418
Short name T92
Test name
Test status
Simulation time 472276632816 ps
CPU time 117.98 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:39:06 PM PDT 24
Peak memory 198588 kb
Host smart-3ce88edf-8179-4eed-90ea-de418865e02e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209604418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1209604418
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.741730480
Short name T43
Test name
Test status
Simulation time 30217347127 ps
CPU time 169.35 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:40:13 PM PDT 24
Peak memory 198596 kb
Host smart-14390a4b-0653-4845-a64e-6b2b5f3aaca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741730480 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.741730480
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2133655392
Short name T10
Test name
Test status
Simulation time 122217229987 ps
CPU time 87.94 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:38:36 PM PDT 24
Peak memory 191824 kb
Host smart-25fb34c5-e6aa-41e0-adce-ae3c0ca493eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133655392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2133655392
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.553583445
Short name T140
Test name
Test status
Simulation time 186806931035 ps
CPU time 235.86 seconds
Started Jul 26 06:37:07 PM PDT 24
Finished Jul 26 06:41:04 PM PDT 24
Peak memory 192668 kb
Host smart-e678de1d-bc23-4f60-8ac1-abb4e16e34a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553583445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.553583445
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2352324895
Short name T9
Test name
Test status
Simulation time 22390930846 ps
CPU time 123.81 seconds
Started Jul 26 06:36:59 PM PDT 24
Finished Jul 26 06:39:03 PM PDT 24
Peak memory 206612 kb
Host smart-81eddd66-2449-45c6-a487-ec7d85d46c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352324895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2352324895
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1009835303
Short name T138
Test name
Test status
Simulation time 102930863337 ps
CPU time 99.53 seconds
Started Jul 26 06:37:37 PM PDT 24
Finished Jul 26 06:39:16 PM PDT 24
Peak memory 192552 kb
Host smart-1125156a-721c-4084-a6d5-5e35c0d6a374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009835303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1009835303
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1096810135
Short name T101
Test name
Test status
Simulation time 124959007835 ps
CPU time 125.59 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:38:46 PM PDT 24
Peak memory 192012 kb
Host smart-b520162f-33e6-4733-a3d3-a015aa382600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096810135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1096810135
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4111990724
Short name T102
Test name
Test status
Simulation time 170822040155 ps
CPU time 14.31 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:56 PM PDT 24
Peak memory 192928 kb
Host smart-c4129a52-fed7-4e3f-b811-1db79c48c22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111990724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4111990724
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3787077613
Short name T22
Test name
Test status
Simulation time 84878278095 ps
CPU time 220.9 seconds
Started Jul 26 06:37:15 PM PDT 24
Finished Jul 26 06:40:56 PM PDT 24
Peak memory 200420 kb
Host smart-1d5540fd-c120-488a-8972-9a4e0208abe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787077613 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3787077613
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2994111891
Short name T145
Test name
Test status
Simulation time 65570945429 ps
CPU time 349.09 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:43:34 PM PDT 24
Peak memory 213948 kb
Host smart-63b29c03-e3eb-47b6-9072-2253f459e743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994111891 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2994111891
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4119722641
Short name T42
Test name
Test status
Simulation time 59189867616 ps
CPU time 111.74 seconds
Started Jul 26 06:37:23 PM PDT 24
Finished Jul 26 06:39:15 PM PDT 24
Peak memory 206644 kb
Host smart-ac451e0d-7fc0-4d64-b627-ba17284c4638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119722641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4119722641
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.392984167
Short name T130
Test name
Test status
Simulation time 88069415341 ps
CPU time 110.16 seconds
Started Jul 26 06:36:48 PM PDT 24
Finished Jul 26 06:38:38 PM PDT 24
Peak memory 192412 kb
Host smart-b249768a-9f44-4d62-bfae-f3b80f832a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392984167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.392984167
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1477889390
Short name T99
Test name
Test status
Simulation time 393787643387 ps
CPU time 42.01 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:38:06 PM PDT 24
Peak memory 191832 kb
Host smart-08d44c08-abed-4672-909d-d99a15e19bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477889390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1477889390
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2239228883
Short name T108
Test name
Test status
Simulation time 394876374684 ps
CPU time 134.98 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:40:00 PM PDT 24
Peak memory 192856 kb
Host smart-a2ff74c2-28e1-4783-a446-8afae7fb13b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239228883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2239228883
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3548181863
Short name T131
Test name
Test status
Simulation time 4358283662 ps
CPU time 6.21 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 191820 kb
Host smart-132c8b88-318a-430b-8c0c-449f52d62454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548181863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3548181863
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.996955308
Short name T135
Test name
Test status
Simulation time 134640824981 ps
CPU time 27.04 seconds
Started Jul 26 06:37:03 PM PDT 24
Finished Jul 26 06:37:30 PM PDT 24
Peak memory 198140 kb
Host smart-393759ad-235e-4c20-826c-c770d3a01a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996955308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.996955308
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3177202731
Short name T127
Test name
Test status
Simulation time 389485819127 ps
CPU time 273.76 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:41:42 PM PDT 24
Peak memory 191856 kb
Host smart-2b34689c-580c-4892-b4a8-c289e92b81d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177202731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3177202731
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3353617809
Short name T115
Test name
Test status
Simulation time 14088003105 ps
CPU time 57.89 seconds
Started Jul 26 06:37:22 PM PDT 24
Finished Jul 26 06:38:20 PM PDT 24
Peak memory 206564 kb
Host smart-f2f7d69e-c027-4184-b11b-7e58ede0fc6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353617809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3353617809
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.550927827
Short name T134
Test name
Test status
Simulation time 451664832128 ps
CPU time 720.59 seconds
Started Jul 26 06:37:51 PM PDT 24
Finished Jul 26 06:49:52 PM PDT 24
Peak memory 192876 kb
Host smart-f0210d93-5922-46d6-b74d-41e274546954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550927827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.550927827
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2806253496
Short name T150
Test name
Test status
Simulation time 316752292126 ps
CPU time 360.73 seconds
Started Jul 26 06:37:59 PM PDT 24
Finished Jul 26 06:44:00 PM PDT 24
Peak memory 192532 kb
Host smart-97e94837-e2bc-4ecd-8aa3-fd74ce75c3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806253496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2806253496
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1008949520
Short name T104
Test name
Test status
Simulation time 48115209729 ps
CPU time 29.87 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:31 PM PDT 24
Peak memory 191824 kb
Host smart-fc72422c-b23e-4e7b-9733-80da10540d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008949520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1008949520
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3586899578
Short name T98
Test name
Test status
Simulation time 115676258779 ps
CPU time 325.7 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:42:34 PM PDT 24
Peak memory 201752 kb
Host smart-41c6f3cc-5441-4ee9-b6a2-b9ef2a2575b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586899578 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3586899578
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1732867655
Short name T107
Test name
Test status
Simulation time 626172776387 ps
CPU time 208.08 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:40:18 PM PDT 24
Peak memory 192408 kb
Host smart-dc3d1127-e7fc-480e-94fa-50175d22ca7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732867655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1732867655
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3409801625
Short name T144
Test name
Test status
Simulation time 202961979120 ps
CPU time 395.3 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:43:44 PM PDT 24
Peak memory 206612 kb
Host smart-5ec66515-6f45-471b-a29e-10e745ed5a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409801625 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3409801625
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1854279230
Short name T86
Test name
Test status
Simulation time 184142711641 ps
CPU time 60.92 seconds
Started Jul 26 06:37:14 PM PDT 24
Finished Jul 26 06:38:15 PM PDT 24
Peak memory 191804 kb
Host smart-da0fadbc-d7f2-40ce-a82f-9ec05e48348e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854279230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1854279230
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3364997792
Short name T13
Test name
Test status
Simulation time 502557114052 ps
CPU time 383.48 seconds
Started Jul 26 06:37:44 PM PDT 24
Finished Jul 26 06:44:08 PM PDT 24
Peak memory 198192 kb
Host smart-1cc65be0-52c6-4a8e-9951-399e5a09e468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364997792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3364997792
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.426110995
Short name T132
Test name
Test status
Simulation time 373392967653 ps
CPU time 144.99 seconds
Started Jul 26 06:37:12 PM PDT 24
Finished Jul 26 06:39:37 PM PDT 24
Peak memory 191816 kb
Host smart-48ccc930-6d5d-4f0b-85ed-7edcaf824926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426110995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.426110995
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3599385878
Short name T32
Test name
Test status
Simulation time 158298014444 ps
CPU time 233.11 seconds
Started Jul 26 06:37:16 PM PDT 24
Finished Jul 26 06:41:09 PM PDT 24
Peak memory 198168 kb
Host smart-a285d159-f232-41f9-bfad-9d398dd5fc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599385878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3599385878
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2086008024
Short name T82
Test name
Test status
Simulation time 129382971273 ps
CPU time 47.75 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:38:40 PM PDT 24
Peak memory 192816 kb
Host smart-169129f1-98d6-492c-b023-6db7be4318fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086008024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2086008024
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1075314288
Short name T103
Test name
Test status
Simulation time 393688246378 ps
CPU time 286.34 seconds
Started Jul 26 06:37:02 PM PDT 24
Finished Jul 26 06:41:49 PM PDT 24
Peak memory 192864 kb
Host smart-d17f7bc8-3495-4baa-a65a-1a6c6244eef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075314288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1075314288
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3844715734
Short name T121
Test name
Test status
Simulation time 288367086609 ps
CPU time 187.43 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:39:58 PM PDT 24
Peak memory 192480 kb
Host smart-4b25ee0f-e97d-4703-ba18-891ba0db8870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844715734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3844715734
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2885306977
Short name T62
Test name
Test status
Simulation time 618155665 ps
CPU time 0.89 seconds
Started Jul 26 06:38:00 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 193604 kb
Host smart-fc8d114d-3e81-4ae2-bf15-bea0701a00ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885306977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2885306977
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1663009724
Short name T34
Test name
Test status
Simulation time 532320128 ps
CPU time 0.82 seconds
Started Jul 26 06:38:31 PM PDT 24
Finished Jul 26 06:38:32 PM PDT 24
Peak memory 193784 kb
Host smart-a1aced21-ed44-4fbd-ac05-09e47850fb0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663009724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1663009724
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1160131894
Short name T126
Test name
Test status
Simulation time 46048678747 ps
CPU time 33.28 seconds
Started Jul 26 06:37:51 PM PDT 24
Finished Jul 26 06:38:25 PM PDT 24
Peak memory 192860 kb
Host smart-26291cd1-09c9-477f-95c4-585e04cbb6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160131894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1160131894
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1139001183
Short name T112
Test name
Test status
Simulation time 105110953282 ps
CPU time 150.1 seconds
Started Jul 26 06:36:57 PM PDT 24
Finished Jul 26 06:39:27 PM PDT 24
Peak memory 192428 kb
Host smart-0df82b39-41ac-47cd-b398-c5921c63c695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139001183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1139001183
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3423471761
Short name T143
Test name
Test status
Simulation time 25148694415 ps
CPU time 10.54 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:20 PM PDT 24
Peak memory 191820 kb
Host smart-32e2cf3f-54f8-4e23-a7c8-3cd68d60cec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423471761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3423471761
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2667009248
Short name T142
Test name
Test status
Simulation time 190430005762 ps
CPU time 67.51 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:38:31 PM PDT 24
Peak memory 198120 kb
Host smart-ee1534f2-1719-4dc9-b44f-5f823f13f8d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667009248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2667009248
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.8961049
Short name T45
Test name
Test status
Simulation time 148170769634 ps
CPU time 388.79 seconds
Started Jul 26 06:37:32 PM PDT 24
Finished Jul 26 06:44:01 PM PDT 24
Peak memory 207152 kb
Host smart-09ccc202-4bde-4ceb-9947-301f8062a587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8961049 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.8961049
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3166351288
Short name T122
Test name
Test status
Simulation time 314483970383 ps
CPU time 60.98 seconds
Started Jul 26 06:37:46 PM PDT 24
Finished Jul 26 06:38:47 PM PDT 24
Peak memory 192388 kb
Host smart-0f289a64-70e4-410a-8da4-b7b811d72957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166351288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3166351288
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.95735744
Short name T152
Test name
Test status
Simulation time 421611262 ps
CPU time 1.17 seconds
Started Jul 26 06:36:57 PM PDT 24
Finished Jul 26 06:36:58 PM PDT 24
Peak memory 196612 kb
Host smart-aa8a4c4e-b7ce-4c03-8d19-9921b493303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95735744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.95735744
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4107535292
Short name T95
Test name
Test status
Simulation time 83404181446 ps
CPU time 681.59 seconds
Started Jul 26 06:37:05 PM PDT 24
Finished Jul 26 06:48:27 PM PDT 24
Peak memory 213996 kb
Host smart-ccec0c90-da48-4914-8610-06e14bac6dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107535292 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4107535292
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.302455968
Short name T111
Test name
Test status
Simulation time 547744756 ps
CPU time 0.78 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 196580 kb
Host smart-d480648d-6fad-4b15-ad7c-f43cee132459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302455968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.302455968
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.277973285
Short name T88
Test name
Test status
Simulation time 514055432469 ps
CPU time 411.33 seconds
Started Jul 26 06:37:07 PM PDT 24
Finished Jul 26 06:43:58 PM PDT 24
Peak memory 210716 kb
Host smart-c5751e98-748e-4314-996c-b7aadffcfe85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277973285 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.277973285
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.162859763
Short name T7
Test name
Test status
Simulation time 197755499021 ps
CPU time 76.73 seconds
Started Jul 26 06:37:31 PM PDT 24
Finished Jul 26 06:38:48 PM PDT 24
Peak memory 198064 kb
Host smart-66b57326-7650-4ad1-a764-a4db3e61a67f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162859763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.162859763
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.52788653
Short name T96
Test name
Test status
Simulation time 410175031 ps
CPU time 0.63 seconds
Started Jul 26 06:37:59 PM PDT 24
Finished Jul 26 06:38:00 PM PDT 24
Peak memory 196520 kb
Host smart-a29c6b96-a7c5-454a-827c-610a4813e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52788653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.52788653
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2897334684
Short name T159
Test name
Test status
Simulation time 132400275782 ps
CPU time 307.4 seconds
Started Jul 26 06:37:05 PM PDT 24
Finished Jul 26 06:42:13 PM PDT 24
Peak memory 209780 kb
Host smart-d44d8c60-62ba-4326-9c1a-1fe78686fbe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897334684 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2897334684
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.505012341
Short name T118
Test name
Test status
Simulation time 399045467 ps
CPU time 0.73 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 196540 kb
Host smart-42dcf1fc-d82e-4439-b072-149b550c99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505012341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.505012341
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2627662156
Short name T139
Test name
Test status
Simulation time 14963553331 ps
CPU time 121.35 seconds
Started Jul 26 06:37:05 PM PDT 24
Finished Jul 26 06:39:06 PM PDT 24
Peak memory 206696 kb
Host smart-8b9cf1fd-4d91-4c05-aaae-fca14e2a446e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627662156 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2627662156
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2068316444
Short name T125
Test name
Test status
Simulation time 503078766 ps
CPU time 0.95 seconds
Started Jul 26 06:37:25 PM PDT 24
Finished Jul 26 06:37:26 PM PDT 24
Peak memory 196744 kb
Host smart-9f9f1c35-eb8a-456b-81a4-212431204bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068316444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2068316444
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.409698592
Short name T105
Test name
Test status
Simulation time 467582419 ps
CPU time 1.2 seconds
Started Jul 26 06:37:30 PM PDT 24
Finished Jul 26 06:37:32 PM PDT 24
Peak memory 196512 kb
Host smart-010fd67a-1d6d-4592-a7ea-5f7febb1b01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409698592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.409698592
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2708008109
Short name T149
Test name
Test status
Simulation time 39677354071 ps
CPU time 13.58 seconds
Started Jul 26 06:37:37 PM PDT 24
Finished Jul 26 06:37:51 PM PDT 24
Peak memory 191792 kb
Host smart-9dc67df6-cd41-441c-8ae7-155e49653beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708008109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2708008109
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1133092188
Short name T160
Test name
Test status
Simulation time 119412901537 ps
CPU time 245.01 seconds
Started Jul 26 06:37:36 PM PDT 24
Finished Jul 26 06:41:41 PM PDT 24
Peak memory 213856 kb
Host smart-b225e434-d7cf-4908-8913-f639402d0eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133092188 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1133092188
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3824824529
Short name T117
Test name
Test status
Simulation time 34657496684 ps
CPU time 299.48 seconds
Started Jul 26 06:37:51 PM PDT 24
Finished Jul 26 06:42:51 PM PDT 24
Peak memory 206612 kb
Host smart-e813b9d8-400e-412e-93c3-0397c4a9d3d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824824529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3824824529
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.190932990
Short name T114
Test name
Test status
Simulation time 486282031 ps
CPU time 0.81 seconds
Started Jul 26 06:36:57 PM PDT 24
Finished Jul 26 06:36:58 PM PDT 24
Peak memory 196504 kb
Host smart-e4c90a06-ec1c-49fd-974a-c5fe5787a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190932990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.190932990
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.349466465
Short name T15
Test name
Test status
Simulation time 393838990 ps
CPU time 1.18 seconds
Started Jul 26 06:36:57 PM PDT 24
Finished Jul 26 06:36:58 PM PDT 24
Peak memory 196612 kb
Host smart-d84fa047-3339-45a6-b2fc-672d925127a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349466465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.349466465
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1290379679
Short name T162
Test name
Test status
Simulation time 175154245080 ps
CPU time 226.18 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:40:47 PM PDT 24
Peak memory 192848 kb
Host smart-8bf4bfcf-0198-4dbd-bad7-67d45a1a492c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290379679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1290379679
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.217321104
Short name T57
Test name
Test status
Simulation time 13896983310 ps
CPU time 100.81 seconds
Started Jul 26 06:37:03 PM PDT 24
Finished Jul 26 06:38:44 PM PDT 24
Peak memory 198436 kb
Host smart-ce9b1e9d-9280-4081-96c5-b102314b1491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217321104 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.217321104
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1865152346
Short name T109
Test name
Test status
Simulation time 139127932432 ps
CPU time 143.96 seconds
Started Jul 26 06:37:26 PM PDT 24
Finished Jul 26 06:39:50 PM PDT 24
Peak memory 214788 kb
Host smart-6b158a91-1ad5-4d76-9b9e-3201f049b587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865152346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1865152346
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2682319327
Short name T156
Test name
Test status
Simulation time 162410122280 ps
CPU time 250.62 seconds
Started Jul 26 06:37:37 PM PDT 24
Finished Jul 26 06:41:48 PM PDT 24
Peak memory 191816 kb
Host smart-20514505-5ce1-441b-a690-f1f3cc4b7f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682319327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2682319327
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1953501725
Short name T83
Test name
Test status
Simulation time 504340755 ps
CPU time 0.8 seconds
Started Jul 26 06:37:38 PM PDT 24
Finished Jul 26 06:37:38 PM PDT 24
Peak memory 196604 kb
Host smart-8431d87f-827a-480c-b73c-9a4b467b04dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953501725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1953501725
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1516107661
Short name T44
Test name
Test status
Simulation time 77303379087 ps
CPU time 112.23 seconds
Started Jul 26 06:36:48 PM PDT 24
Finished Jul 26 06:38:40 PM PDT 24
Peak memory 213876 kb
Host smart-309c2709-8a0d-4efe-85eb-91d31d6ff3af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516107661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1516107661
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1970942907
Short name T147
Test name
Test status
Simulation time 168340818390 ps
CPU time 50.14 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:37:46 PM PDT 24
Peak memory 198220 kb
Host smart-c502fc5a-8f53-4ef2-8142-3e195bf365ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970942907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1970942907
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3875137144
Short name T136
Test name
Test status
Simulation time 506200524 ps
CPU time 0.89 seconds
Started Jul 26 06:36:48 PM PDT 24
Finished Jul 26 06:36:49 PM PDT 24
Peak memory 196504 kb
Host smart-a518aea6-5258-4bb9-b24e-4d84edda2f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875137144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3875137144
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3581100436
Short name T165
Test name
Test status
Simulation time 80581561633 ps
CPU time 898.12 seconds
Started Jul 26 06:37:11 PM PDT 24
Finished Jul 26 06:52:09 PM PDT 24
Peak memory 214856 kb
Host smart-ad373fb2-b623-449c-b199-872f0e59272e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581100436 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3581100436
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3047298428
Short name T1
Test name
Test status
Simulation time 544497269 ps
CPU time 1.44 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 196580 kb
Host smart-623b6116-0ae8-49eb-887d-2b0a479d9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047298428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3047298428
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2590441059
Short name T106
Test name
Test status
Simulation time 408454136 ps
CPU time 0.91 seconds
Started Jul 26 06:37:29 PM PDT 24
Finished Jul 26 06:37:30 PM PDT 24
Peak memory 196588 kb
Host smart-625cc586-19ac-4744-9f72-baec364defef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590441059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2590441059
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4282885761
Short name T3
Test name
Test status
Simulation time 431510483 ps
CPU time 0.76 seconds
Started Jul 26 06:37:34 PM PDT 24
Finished Jul 26 06:37:35 PM PDT 24
Peak memory 196548 kb
Host smart-f617535c-c293-48ee-bd9b-0dad8337c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282885761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4282885761
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1969294960
Short name T148
Test name
Test status
Simulation time 479780132 ps
CPU time 1.25 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:37:47 PM PDT 24
Peak memory 196524 kb
Host smart-1a5ca2cd-b6c6-49b5-b1bf-7271f3f02698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969294960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1969294960
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3737427296
Short name T14
Test name
Test status
Simulation time 626287498 ps
CPU time 0.65 seconds
Started Jul 26 06:36:40 PM PDT 24
Finished Jul 26 06:36:41 PM PDT 24
Peak memory 196704 kb
Host smart-81353b58-eefd-4540-9a84-91a4da00bf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737427296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3737427296
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2326031539
Short name T29
Test name
Test status
Simulation time 558479469 ps
CPU time 1 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:36:56 PM PDT 24
Peak memory 196500 kb
Host smart-49481b5d-c287-49e3-aea9-01f1d94044ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326031539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2326031539
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.238334485
Short name T119
Test name
Test status
Simulation time 556612386 ps
CPU time 1.04 seconds
Started Jul 26 06:37:02 PM PDT 24
Finished Jul 26 06:37:03 PM PDT 24
Peak memory 196548 kb
Host smart-bf1dfe7b-acd8-467c-8b71-bd4e92c8b60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238334485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.238334485
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3778222394
Short name T129
Test name
Test status
Simulation time 70043931207 ps
CPU time 384.89 seconds
Started Jul 26 06:36:49 PM PDT 24
Finished Jul 26 06:43:14 PM PDT 24
Peak memory 209568 kb
Host smart-d544a3c5-8c6c-4f78-8a93-2e7d0744064d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778222394 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3778222394
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.303413668
Short name T166
Test name
Test status
Simulation time 537650626214 ps
CPU time 216.9 seconds
Started Jul 26 06:37:13 PM PDT 24
Finished Jul 26 06:40:50 PM PDT 24
Peak memory 198180 kb
Host smart-37e3ef8f-988a-4b1e-b554-2fec6b88cf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303413668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.303413668
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4216729197
Short name T93
Test name
Test status
Simulation time 179631280041 ps
CPU time 89.91 seconds
Started Jul 26 06:37:25 PM PDT 24
Finished Jul 26 06:38:55 PM PDT 24
Peak memory 198648 kb
Host smart-2c917834-26e4-4854-94e9-7c4f22a134ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216729197 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4216729197
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.836484241
Short name T137
Test name
Test status
Simulation time 508091342 ps
CPU time 1.32 seconds
Started Jul 26 06:37:19 PM PDT 24
Finished Jul 26 06:37:21 PM PDT 24
Peak memory 196540 kb
Host smart-341f579d-603a-457c-b96e-734d70abb0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836484241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.836484241
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.724999686
Short name T151
Test name
Test status
Simulation time 24813921269 ps
CPU time 38.09 seconds
Started Jul 26 06:37:30 PM PDT 24
Finished Jul 26 06:38:09 PM PDT 24
Peak memory 198184 kb
Host smart-34c0c542-075c-4b38-858a-9d34e64918c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724999686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.724999686
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3103581070
Short name T164
Test name
Test status
Simulation time 357373921742 ps
CPU time 29.47 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:37:26 PM PDT 24
Peak memory 192916 kb
Host smart-dbe2720b-50bf-4356-b9f9-273aa866c19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103581070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3103581070
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2976519801
Short name T46
Test name
Test status
Simulation time 308241637462 ps
CPU time 294.69 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:41:50 PM PDT 24
Peak memory 214256 kb
Host smart-31eee1fe-81a6-4e7a-8c99-8f55c2265f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976519801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2976519801
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3075616180
Short name T161
Test name
Test status
Simulation time 131241109097 ps
CPU time 370.18 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:43:06 PM PDT 24
Peak memory 210588 kb
Host smart-66fc88f5-456c-4ccc-b5ec-644d94c1a065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075616180 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3075616180
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2187883022
Short name T41
Test name
Test status
Simulation time 54727170317 ps
CPU time 167.81 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:39:52 PM PDT 24
Peak memory 206648 kb
Host smart-671af81a-64bc-48e7-8fc8-d4b8fd4c7295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187883022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2187883022
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2609165156
Short name T187
Test name
Test status
Simulation time 502057046 ps
CPU time 0.92 seconds
Started Jul 26 06:37:25 PM PDT 24
Finished Jul 26 06:37:26 PM PDT 24
Peak memory 196392 kb
Host smart-ab46a447-c57c-4764-b273-21eb3d432fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609165156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2609165156
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4235976413
Short name T155
Test name
Test status
Simulation time 496198395 ps
CPU time 0.97 seconds
Started Jul 26 06:37:36 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 196528 kb
Host smart-81c76c9b-6bd9-4fc9-bc30-95ea8f552ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235976413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4235976413
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3999446143
Short name T153
Test name
Test status
Simulation time 12679700221 ps
CPU time 102.63 seconds
Started Jul 26 06:37:44 PM PDT 24
Finished Jul 26 06:39:27 PM PDT 24
Peak memory 206624 kb
Host smart-05685bb4-c374-4279-b024-b625c98791d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999446143 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3999446143
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1906142719
Short name T168
Test name
Test status
Simulation time 426985297 ps
CPU time 0.73 seconds
Started Jul 26 06:37:55 PM PDT 24
Finished Jul 26 06:37:55 PM PDT 24
Peak memory 196488 kb
Host smart-d4fe561b-6ace-4b28-a557-5d90c373ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906142719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1906142719
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2678400305
Short name T51
Test name
Test status
Simulation time 80101887432 ps
CPU time 29.02 seconds
Started Jul 26 06:36:58 PM PDT 24
Finished Jul 26 06:37:27 PM PDT 24
Peak memory 198204 kb
Host smart-384422d0-3040-4013-a09d-d4498d9bd6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678400305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2678400305
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1536062636
Short name T190
Test name
Test status
Simulation time 7676508067 ps
CPU time 12.26 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 198844 kb
Host smart-7ad673ff-162b-476c-aef7-4f598c18840f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536062636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1536062636
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1542497762
Short name T170
Test name
Test status
Simulation time 388645360 ps
CPU time 1.19 seconds
Started Jul 26 06:36:42 PM PDT 24
Finished Jul 26 06:36:44 PM PDT 24
Peak memory 196576 kb
Host smart-2f966f22-8077-49d5-971a-bfc480c82264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542497762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1542497762
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1446708564
Short name T172
Test name
Test status
Simulation time 405975757 ps
CPU time 0.89 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:36:57 PM PDT 24
Peak memory 196620 kb
Host smart-22fdafce-8a3d-4f16-a2f1-d21ce27f7594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446708564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1446708564
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4089187252
Short name T171
Test name
Test status
Simulation time 378678801 ps
CPU time 0.97 seconds
Started Jul 26 06:37:02 PM PDT 24
Finished Jul 26 06:37:03 PM PDT 24
Peak memory 196488 kb
Host smart-2f2a8487-9ba7-4a1f-ad6e-1fba1a202930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089187252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4089187252
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3126139196
Short name T141
Test name
Test status
Simulation time 33431260342 ps
CPU time 45.66 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:49 PM PDT 24
Peak memory 191808 kb
Host smart-622ad088-08d8-43e8-a68b-82ce6aa75aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126139196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3126139196
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3758050349
Short name T154
Test name
Test status
Simulation time 512743538 ps
CPU time 1.25 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 196588 kb
Host smart-d497afe0-98f1-413b-8557-86a330339574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758050349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3758050349
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4193519496
Short name T167
Test name
Test status
Simulation time 58957899021 ps
CPU time 95.51 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:38:26 PM PDT 24
Peak memory 198240 kb
Host smart-3e1848c5-8696-4f3e-af1c-310d588617f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193519496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4193519496
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2305053074
Short name T184
Test name
Test status
Simulation time 551047967 ps
CPU time 0.98 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:10 PM PDT 24
Peak memory 196436 kb
Host smart-610389a5-b313-43e3-80df-d38235c0f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305053074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2305053074
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2192578784
Short name T124
Test name
Test status
Simulation time 527574909 ps
CPU time 0.67 seconds
Started Jul 26 06:37:10 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 196516 kb
Host smart-6c67655f-ef5e-4b25-8ccf-a312aaf2279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192578784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2192578784
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3344321534
Short name T173
Test name
Test status
Simulation time 497168521 ps
CPU time 0.77 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:17 PM PDT 24
Peak memory 196552 kb
Host smart-42a3a7e9-8d67-4471-b519-897a6859cdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344321534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3344321534
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.4196811431
Short name T182
Test name
Test status
Simulation time 444285037 ps
CPU time 0.71 seconds
Started Jul 26 06:37:15 PM PDT 24
Finished Jul 26 06:37:16 PM PDT 24
Peak memory 196488 kb
Host smart-a658484c-c601-467c-ade4-84e945fc4404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196811431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4196811431
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1783590934
Short name T123
Test name
Test status
Simulation time 491649431 ps
CPU time 0.74 seconds
Started Jul 26 06:37:26 PM PDT 24
Finished Jul 26 06:37:27 PM PDT 24
Peak memory 196812 kb
Host smart-b9b3a66b-849c-4d33-bbd0-e2927b0eab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783590934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1783590934
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.551386506
Short name T30
Test name
Test status
Simulation time 486923495 ps
CPU time 1.18 seconds
Started Jul 26 06:37:21 PM PDT 24
Finished Jul 26 06:37:22 PM PDT 24
Peak memory 196524 kb
Host smart-70c111b4-3b95-4bce-8ddb-874241d2054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551386506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.551386506
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2863560338
Short name T52
Test name
Test status
Simulation time 64910227844 ps
CPU time 21.95 seconds
Started Jul 26 06:37:29 PM PDT 24
Finished Jul 26 06:37:52 PM PDT 24
Peak memory 198160 kb
Host smart-1b6c18eb-2b05-438b-8e2c-96b8818c0d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863560338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2863560338
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4032446996
Short name T185
Test name
Test status
Simulation time 396455726 ps
CPU time 1.11 seconds
Started Jul 26 06:37:36 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 196464 kb
Host smart-08febef7-34e2-4509-8e8d-cd2677df850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032446996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4032446996
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1234802082
Short name T186
Test name
Test status
Simulation time 483666837 ps
CPU time 1.25 seconds
Started Jul 26 06:37:40 PM PDT 24
Finished Jul 26 06:37:41 PM PDT 24
Peak memory 196456 kb
Host smart-0942fb92-46ce-48de-8a3b-b374e96fbd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234802082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1234802082
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.559788416
Short name T179
Test name
Test status
Simulation time 544060235 ps
CPU time 1.26 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:37:53 PM PDT 24
Peak memory 196484 kb
Host smart-f7c87092-5075-4bd4-809f-1ca6b77ad241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559788416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.559788416
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2885077253
Short name T97
Test name
Test status
Simulation time 558502480 ps
CPU time 0.96 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:36:52 PM PDT 24
Peak memory 196520 kb
Host smart-97142643-3bd4-422b-8bca-8d9df721cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885077253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2885077253
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2074881964
Short name T146
Test name
Test status
Simulation time 167330217027 ps
CPU time 243.81 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:41:12 PM PDT 24
Peak memory 192244 kb
Host smart-9a31b812-ecfe-45c8-bf77-876cf2375c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074881964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2074881964
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2342138307
Short name T169
Test name
Test status
Simulation time 393029189 ps
CPU time 1.11 seconds
Started Jul 26 06:37:07 PM PDT 24
Finished Jul 26 06:37:08 PM PDT 24
Peak memory 196468 kb
Host smart-5f423fee-2057-4d73-bc57-5e3697bf8aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342138307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2342138307
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1419281631
Short name T81
Test name
Test status
Simulation time 548547040 ps
CPU time 1.44 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 196580 kb
Host smart-00bffebb-01a0-4677-8629-733bc8d2a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419281631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1419281631
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2635719412
Short name T158
Test name
Test status
Simulation time 500304973 ps
CPU time 1.37 seconds
Started Jul 26 06:37:15 PM PDT 24
Finished Jul 26 06:37:16 PM PDT 24
Peak memory 196468 kb
Host smart-cc7ade71-b872-4251-b815-1207bfff9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635719412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2635719412
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.463584658
Short name T177
Test name
Test status
Simulation time 453466995 ps
CPU time 1.29 seconds
Started Jul 26 06:36:48 PM PDT 24
Finished Jul 26 06:36:50 PM PDT 24
Peak memory 196508 kb
Host smart-2cfb618e-dfcf-453d-af0d-b66082d24768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463584658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.463584658
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3773777673
Short name T163
Test name
Test status
Simulation time 103755219900 ps
CPU time 32.63 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:37:23 PM PDT 24
Peak memory 191828 kb
Host smart-6a8912df-4c03-47d1-8cd2-0f25b03d58a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773777673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3773777673
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.351447848
Short name T59
Test name
Test status
Simulation time 612454768 ps
CPU time 0.88 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:37:25 PM PDT 24
Peak memory 196368 kb
Host smart-12e9f63c-6a1c-4f91-8daf-a87cf22c8ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351447848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.351447848
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1787833207
Short name T176
Test name
Test status
Simulation time 449233518 ps
CPU time 1.17 seconds
Started Jul 26 06:36:48 PM PDT 24
Finished Jul 26 06:36:50 PM PDT 24
Peak memory 196508 kb
Host smart-3b7ab610-78fc-4fc3-8504-1ac9cad1a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787833207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1787833207
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.842002772
Short name T178
Test name
Test status
Simulation time 369608261 ps
CPU time 0.77 seconds
Started Jul 26 06:37:46 PM PDT 24
Finished Jul 26 06:37:46 PM PDT 24
Peak memory 196488 kb
Host smart-4662ae7a-5f6a-418e-90e7-816be475d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842002772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.842002772
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1270231357
Short name T183
Test name
Test status
Simulation time 576292909 ps
CPU time 1.32 seconds
Started Jul 26 06:37:43 PM PDT 24
Finished Jul 26 06:37:45 PM PDT 24
Peak memory 196544 kb
Host smart-048a33d5-8649-4f4d-87ba-fdc6151ae548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270231357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1270231357
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1454799919
Short name T180
Test name
Test status
Simulation time 506514202 ps
CPU time 0.94 seconds
Started Jul 26 06:37:47 PM PDT 24
Finished Jul 26 06:37:48 PM PDT 24
Peak memory 196504 kb
Host smart-566cd070-0a77-481e-ae30-f8bb1b3558c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454799919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1454799919
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1590471921
Short name T2
Test name
Test status
Simulation time 566474026 ps
CPU time 0.98 seconds
Started Jul 26 06:37:53 PM PDT 24
Finished Jul 26 06:37:54 PM PDT 24
Peak memory 196572 kb
Host smart-34ec0cad-a5bc-4b3c-b2d4-fe8ad805d617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590471921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1590471921
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.16420614
Short name T157
Test name
Test status
Simulation time 48879861150 ps
CPU time 395.51 seconds
Started Jul 26 06:37:54 PM PDT 24
Finished Jul 26 06:44:29 PM PDT 24
Peak memory 199956 kb
Host smart-aa9fb87c-2634-4685-bdeb-a29027593ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420614 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.16420614
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.304304290
Short name T47
Test name
Test status
Simulation time 384351919 ps
CPU time 1.12 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:36:56 PM PDT 24
Peak memory 196496 kb
Host smart-1a88a159-8e21-4fbe-9544-ff4ef1f91cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304304290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.304304290
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1538263483
Short name T60
Test name
Test status
Simulation time 717155288 ps
CPU time 2.4 seconds
Started Jul 26 06:38:00 PM PDT 24
Finished Jul 26 06:38:02 PM PDT 24
Peak memory 192588 kb
Host smart-24c951e3-0f46-4213-9b81-48b974ccee48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538263483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1538263483
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2192174704
Short name T357
Test name
Test status
Simulation time 731478785 ps
CPU time 0.72 seconds
Started Jul 26 06:37:58 PM PDT 24
Finished Jul 26 06:37:59 PM PDT 24
Peak memory 184228 kb
Host smart-f5539f28-58ae-4226-baeb-f38407f02e2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192174704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2192174704
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3488173757
Short name T304
Test name
Test status
Simulation time 538574653 ps
CPU time 1.49 seconds
Started Jul 26 06:38:01 PM PDT 24
Finished Jul 26 06:38:02 PM PDT 24
Peak memory 196656 kb
Host smart-84a1a0f6-b775-4b18-9a78-3e3a54cf82d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488173757 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3488173757
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4221002039
Short name T409
Test name
Test status
Simulation time 531813585 ps
CPU time 0.8 seconds
Started Jul 26 06:37:58 PM PDT 24
Finished Jul 26 06:37:59 PM PDT 24
Peak memory 193532 kb
Host smart-6f79c9c0-390f-45a1-b175-61d1693d3d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221002039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4221002039
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3253317194
Short name T289
Test name
Test status
Simulation time 328641816 ps
CPU time 1.05 seconds
Started Jul 26 06:38:00 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 184184 kb
Host smart-e8c61cd6-e50c-4e97-ac9f-b5c988175d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253317194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3253317194
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.47200767
Short name T374
Test name
Test status
Simulation time 502339976 ps
CPU time 1.23 seconds
Started Jul 26 06:38:00 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 184120 kb
Host smart-48c11309-3ded-4a9c-8d64-3c9e3b49a73d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47200767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.47200767
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.64947782
Short name T283
Test name
Test status
Simulation time 451759028 ps
CPU time 0.88 seconds
Started Jul 26 06:37:58 PM PDT 24
Finished Jul 26 06:37:59 PM PDT 24
Peak memory 184044 kb
Host smart-7d38fd08-a081-4b5e-8c65-925a314a0e7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64947782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wal
k.64947782
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1845628710
Short name T395
Test name
Test status
Simulation time 964162175 ps
CPU time 1.13 seconds
Started Jul 26 06:37:58 PM PDT 24
Finished Jul 26 06:37:59 PM PDT 24
Peak memory 193984 kb
Host smart-d0a101eb-7357-41e5-abf1-4bb8c8f31245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845628710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1845628710
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2670459052
Short name T299
Test name
Test status
Simulation time 398271346 ps
CPU time 1.67 seconds
Started Jul 26 06:37:59 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 198984 kb
Host smart-68048fd4-ba19-4b7d-83c5-ca43578d09ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670459052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2670459052
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1129963600
Short name T194
Test name
Test status
Simulation time 8098162067 ps
CPU time 2.67 seconds
Started Jul 26 06:37:58 PM PDT 24
Finished Jul 26 06:38:00 PM PDT 24
Peak memory 198880 kb
Host smart-2188281c-488f-4298-a3cd-249c99097ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129963600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1129963600
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3654158133
Short name T63
Test name
Test status
Simulation time 608110397 ps
CPU time 0.8 seconds
Started Jul 26 06:38:06 PM PDT 24
Finished Jul 26 06:38:07 PM PDT 24
Peak memory 184160 kb
Host smart-30549891-eeff-442b-a36c-bc33640d1d50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654158133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3654158133
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1513502649
Short name T38
Test name
Test status
Simulation time 6397942941 ps
CPU time 3.75 seconds
Started Jul 26 06:38:03 PM PDT 24
Finished Jul 26 06:38:07 PM PDT 24
Peak memory 192712 kb
Host smart-ff0dd5ed-295a-42da-b076-c63fe17c6bb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513502649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1513502649
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3661506356
Short name T305
Test name
Test status
Simulation time 675397048 ps
CPU time 1.53 seconds
Started Jul 26 06:38:07 PM PDT 24
Finished Jul 26 06:38:09 PM PDT 24
Peak memory 193388 kb
Host smart-791b0e9b-c485-401f-9ae1-c3bbbc7d4187
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661506356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3661506356
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3029607497
Short name T342
Test name
Test status
Simulation time 524886195 ps
CPU time 0.83 seconds
Started Jul 26 06:38:06 PM PDT 24
Finished Jul 26 06:38:07 PM PDT 24
Peak memory 196620 kb
Host smart-2041080d-3583-4b18-8bf9-fd7b700624eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029607497 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3029607497
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3422704444
Short name T389
Test name
Test status
Simulation time 487117674 ps
CPU time 1.28 seconds
Started Jul 26 06:38:06 PM PDT 24
Finished Jul 26 06:38:07 PM PDT 24
Peak memory 193372 kb
Host smart-6b20eb4f-0cbe-4935-b18e-bfe76fe9cce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422704444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3422704444
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3659700415
Short name T335
Test name
Test status
Simulation time 628304880 ps
CPU time 0.57 seconds
Started Jul 26 06:38:02 PM PDT 24
Finished Jul 26 06:38:03 PM PDT 24
Peak memory 184212 kb
Host smart-43da09b4-d437-462d-b51c-f31eb288ea98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659700415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3659700415
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1467393777
Short name T403
Test name
Test status
Simulation time 456641689 ps
CPU time 1.21 seconds
Started Jul 26 06:38:07 PM PDT 24
Finished Jul 26 06:38:08 PM PDT 24
Peak memory 184080 kb
Host smart-eaf53e67-d684-43d4-aeac-d011a379d663
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467393777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1467393777
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2057350456
Short name T410
Test name
Test status
Simulation time 464080156 ps
CPU time 0.68 seconds
Started Jul 26 06:38:04 PM PDT 24
Finished Jul 26 06:38:05 PM PDT 24
Peak memory 184120 kb
Host smart-c290cbb3-4867-4c56-b201-3ba49ab43e34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057350456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2057350456
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1076014999
Short name T338
Test name
Test status
Simulation time 1269804121 ps
CPU time 3.74 seconds
Started Jul 26 06:38:04 PM PDT 24
Finished Jul 26 06:38:07 PM PDT 24
Peak memory 192332 kb
Host smart-334e1e94-f21a-496b-9827-4a181aed2c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076014999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1076014999
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4259926903
Short name T327
Test name
Test status
Simulation time 699369338 ps
CPU time 2.06 seconds
Started Jul 26 06:37:59 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 199036 kb
Host smart-bd9bdb95-950b-49c3-9f53-1335b3be2297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259926903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4259926903
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2238375399
Short name T336
Test name
Test status
Simulation time 8374179711 ps
CPU time 2.79 seconds
Started Jul 26 06:38:06 PM PDT 24
Finished Jul 26 06:38:09 PM PDT 24
Peak memory 198644 kb
Host smart-e4c7083b-7e1b-4840-9a5d-de4f99b940d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238375399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2238375399
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4033649256
Short name T406
Test name
Test status
Simulation time 333594776 ps
CPU time 1.11 seconds
Started Jul 26 06:38:32 PM PDT 24
Finished Jul 26 06:38:34 PM PDT 24
Peak memory 196536 kb
Host smart-b0f2c195-d38e-4c9d-bad3-96835c5763e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033649256 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4033649256
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1445498660
Short name T295
Test name
Test status
Simulation time 382305304 ps
CPU time 0.68 seconds
Started Jul 26 06:38:33 PM PDT 24
Finished Jul 26 06:38:34 PM PDT 24
Peak memory 184176 kb
Host smart-6841bd9e-b408-4e44-b4fd-eb23324a4a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445498660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1445498660
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3869097193
Short name T365
Test name
Test status
Simulation time 1641476613 ps
CPU time 1.17 seconds
Started Jul 26 06:38:34 PM PDT 24
Finished Jul 26 06:38:35 PM PDT 24
Peak memory 184420 kb
Host smart-ddfa4f99-36de-4a61-967c-1193d7d7c9dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869097193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3869097193
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1231082513
Short name T316
Test name
Test status
Simulation time 424567464 ps
CPU time 2.07 seconds
Started Jul 26 06:38:31 PM PDT 24
Finished Jul 26 06:38:33 PM PDT 24
Peak memory 199084 kb
Host smart-f955579d-af6c-42dc-b567-2605965d10c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231082513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1231082513
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.627391321
Short name T396
Test name
Test status
Simulation time 4214251166 ps
CPU time 2.12 seconds
Started Jul 26 06:38:30 PM PDT 24
Finished Jul 26 06:38:33 PM PDT 24
Peak memory 197212 kb
Host smart-ed4fb619-6338-43e9-8831-5fd23f4d75e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627391321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.627391321
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.248897931
Short name T33
Test name
Test status
Simulation time 394825202 ps
CPU time 0.85 seconds
Started Jul 26 06:38:45 PM PDT 24
Finished Jul 26 06:38:46 PM PDT 24
Peak memory 197028 kb
Host smart-295fa003-8051-4c1d-aa14-97df744c8c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248897931 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.248897931
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4294050987
Short name T391
Test name
Test status
Simulation time 522629591 ps
CPU time 1.33 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 193416 kb
Host smart-b3d7dbb6-f700-4bb2-a0c4-9fd59a0e32d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294050987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4294050987
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.907353364
Short name T340
Test name
Test status
Simulation time 373611258 ps
CPU time 0.68 seconds
Started Jul 26 06:38:31 PM PDT 24
Finished Jul 26 06:38:32 PM PDT 24
Peak memory 193404 kb
Host smart-68f5eafe-9ec8-42bb-852c-25a483b6e1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907353364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.907353364
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3813925056
Short name T79
Test name
Test status
Simulation time 2030064448 ps
CPU time 1.66 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:46 PM PDT 24
Peak memory 194392 kb
Host smart-1d82e067-6250-4f47-8c48-98e56c4b3d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813925056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3813925056
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3592228645
Short name T290
Test name
Test status
Simulation time 466092308 ps
CPU time 1.61 seconds
Started Jul 26 06:38:31 PM PDT 24
Finished Jul 26 06:38:33 PM PDT 24
Peak memory 199004 kb
Host smart-bf312e89-5e57-4d68-bbd1-f798a9f0671d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592228645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3592228645
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4121271408
Short name T362
Test name
Test status
Simulation time 8469694402 ps
CPU time 3.91 seconds
Started Jul 26 06:38:31 PM PDT 24
Finished Jul 26 06:38:35 PM PDT 24
Peak memory 198728 kb
Host smart-bda0d5bb-6b05-4496-ba27-0462da6cf7fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121271408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4121271408
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.986482203
Short name T371
Test name
Test status
Simulation time 429923222 ps
CPU time 1.25 seconds
Started Jul 26 06:38:45 PM PDT 24
Finished Jul 26 06:38:47 PM PDT 24
Peak memory 196656 kb
Host smart-535f989c-7998-40cb-b2ac-29c3526c91a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986482203 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.986482203
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1676531587
Short name T343
Test name
Test status
Simulation time 456830096 ps
CPU time 0.95 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:44 PM PDT 24
Peak memory 193576 kb
Host smart-9825d837-9168-4584-9711-9901c5b31586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676531587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1676531587
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.10340099
Short name T297
Test name
Test status
Simulation time 426929156 ps
CPU time 1.09 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 184220 kb
Host smart-d3e584c2-6ee9-4333-9577-df4ba8734f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.10340099
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.19575486
Short name T308
Test name
Test status
Simulation time 2410919994 ps
CPU time 4.85 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 194556 kb
Host smart-1e987d2f-1f76-4889-a3b2-3662c6022870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_
timer_same_csr_outstanding.19575486
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3968776775
Short name T318
Test name
Test status
Simulation time 369753776 ps
CPU time 2.04 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 199032 kb
Host smart-e0f23c04-59f4-47cb-93e0-8b2e77a765bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968776775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3968776775
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1416605627
Short name T393
Test name
Test status
Simulation time 4133763741 ps
CPU time 6.6 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 198324 kb
Host smart-2db8a625-0949-44fd-add2-f8e400760732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416605627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1416605627
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3718633700
Short name T320
Test name
Test status
Simulation time 362508790 ps
CPU time 1.07 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 196456 kb
Host smart-ea9bbcd0-44e1-438c-b67d-4c02886f5bb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718633700 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3718633700
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1626349416
Short name T339
Test name
Test status
Simulation time 405152071 ps
CPU time 1.12 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:44 PM PDT 24
Peak memory 193708 kb
Host smart-3454d90f-1b48-4cc5-ba5e-ff42662774b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626349416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1626349416
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1339689997
Short name T287
Test name
Test status
Simulation time 278789567 ps
CPU time 0.92 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:44 PM PDT 24
Peak memory 193376 kb
Host smart-e3376c39-9d1b-472e-a01d-81f33f8995da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339689997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1339689997
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1102981762
Short name T78
Test name
Test status
Simulation time 1037234078 ps
CPU time 3.68 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:48 PM PDT 24
Peak memory 194436 kb
Host smart-92c85f80-5869-4e66-9eb1-c6525f5a5758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102981762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1102981762
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.807763061
Short name T285
Test name
Test status
Simulation time 979131805 ps
CPU time 1.88 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 199084 kb
Host smart-12788050-e418-4fb7-9b4b-c0b33af0ae89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807763061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.807763061
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2376676420
Short name T330
Test name
Test status
Simulation time 8511137234 ps
CPU time 2.36 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:46 PM PDT 24
Peak memory 198672 kb
Host smart-0b8a64a0-e58b-4ad4-b9a5-2a9b42480819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376676420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2376676420
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.567068335
Short name T328
Test name
Test status
Simulation time 523552955 ps
CPU time 1.53 seconds
Started Jul 26 06:38:45 PM PDT 24
Finished Jul 26 06:38:47 PM PDT 24
Peak memory 196728 kb
Host smart-3080e02e-f73e-4730-98e2-5d07027bb802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567068335 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.567068335
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4042027206
Short name T352
Test name
Test status
Simulation time 543062296 ps
CPU time 0.76 seconds
Started Jul 26 06:38:49 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 193444 kb
Host smart-0086f67e-f744-489a-9e2c-5dd0fe21a438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042027206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4042027206
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1086585620
Short name T380
Test name
Test status
Simulation time 486808214 ps
CPU time 1.29 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:45 PM PDT 24
Peak memory 184140 kb
Host smart-788e497e-fbcf-4be9-8bb4-ba0a13789759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086585620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1086585620
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3762855267
Short name T72
Test name
Test status
Simulation time 2662733284 ps
CPU time 1.57 seconds
Started Jul 26 06:38:48 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 194544 kb
Host smart-d9e8aa41-c36b-4ab2-838d-b2815a753ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762855267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3762855267
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3008196468
Short name T326
Test name
Test status
Simulation time 630846908 ps
CPU time 1.78 seconds
Started Jul 26 06:38:42 PM PDT 24
Finished Jul 26 06:38:44 PM PDT 24
Peak memory 199016 kb
Host smart-fabdecea-bd77-4749-ba38-e8f80fd49b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008196468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3008196468
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3257283607
Short name T333
Test name
Test status
Simulation time 4375828429 ps
CPU time 4.97 seconds
Started Jul 26 06:38:43 PM PDT 24
Finished Jul 26 06:38:48 PM PDT 24
Peak memory 198588 kb
Host smart-2e950dee-2349-47b4-a8cf-8f0a51034458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257283607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3257283607
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4191758262
Short name T358
Test name
Test status
Simulation time 504754845 ps
CPU time 0.9 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 197932 kb
Host smart-6da1afe9-5410-4f47-90dd-c07ef9b9b9c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191758262 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4191758262
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2988823861
Short name T77
Test name
Test status
Simulation time 464479045 ps
CPU time 0.89 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 193392 kb
Host smart-871956aa-4dc8-4a0d-82bc-3eda471bcb09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988823861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2988823861
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3459900834
Short name T284
Test name
Test status
Simulation time 360732018 ps
CPU time 0.67 seconds
Started Jul 26 06:38:48 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 184168 kb
Host smart-635204c9-a544-4efe-9e69-28188edb2095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459900834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3459900834
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3643350682
Short name T75
Test name
Test status
Simulation time 2175690947 ps
CPU time 1.73 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 194404 kb
Host smart-6e6dadb1-1a17-465e-8c83-fe10b94ae0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643350682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3643350682
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4111067613
Short name T373
Test name
Test status
Simulation time 485639412 ps
CPU time 2.98 seconds
Started Jul 26 06:38:47 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 199060 kb
Host smart-5f16555f-4f5e-45d5-b52b-74a02072d051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111067613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4111067613
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.81078150
Short name T294
Test name
Test status
Simulation time 523697942 ps
CPU time 1.01 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:46 PM PDT 24
Peak memory 197172 kb
Host smart-cf866638-ca3e-484f-b773-1e25362cc4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81078150 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.81078150
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3539063798
Short name T399
Test name
Test status
Simulation time 540403019 ps
CPU time 0.72 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:47 PM PDT 24
Peak memory 193532 kb
Host smart-c4ac19cc-2beb-496f-a710-bffd5e94acc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539063798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3539063798
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.184246811
Short name T394
Test name
Test status
Simulation time 420190123 ps
CPU time 0.72 seconds
Started Jul 26 06:38:49 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 184208 kb
Host smart-21e9bcb8-b869-44fd-877a-41f03eda9134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184246811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.184246811
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.263822733
Short name T324
Test name
Test status
Simulation time 959107568 ps
CPU time 1.48 seconds
Started Jul 26 06:38:49 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 193964 kb
Host smart-e499beba-85ee-4c2f-ad4f-a82f8ce3465f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263822733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.263822733
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2125653667
Short name T405
Test name
Test status
Simulation time 669159042 ps
CPU time 2.56 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 198992 kb
Host smart-10a3dcc0-c097-49be-a6fd-4f915bc1d2f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125653667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2125653667
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1925599075
Short name T315
Test name
Test status
Simulation time 8430325060 ps
CPU time 9.19 seconds
Started Jul 26 06:38:44 PM PDT 24
Finished Jul 26 06:38:54 PM PDT 24
Peak memory 198664 kb
Host smart-eb8ca2fc-8dc7-47e5-b3b6-e1cc3f2b2b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925599075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1925599075
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3499134337
Short name T377
Test name
Test status
Simulation time 441815118 ps
CPU time 0.87 seconds
Started Jul 26 06:38:47 PM PDT 24
Finished Jul 26 06:38:48 PM PDT 24
Peak memory 196376 kb
Host smart-a77fa08b-c3b5-4d22-9ab4-c5ccc40af943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499134337 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3499134337
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3466125898
Short name T385
Test name
Test status
Simulation time 344744146 ps
CPU time 0.66 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:47 PM PDT 24
Peak memory 193396 kb
Host smart-345c371a-3034-44c3-9ce9-e66f3c06944a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466125898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3466125898
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.93515070
Short name T418
Test name
Test status
Simulation time 312905812 ps
CPU time 0.63 seconds
Started Jul 26 06:38:49 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 193452 kb
Host smart-da0fa5e7-440c-4ce3-952c-1858bec34ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93515070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.93515070
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.826087764
Short name T347
Test name
Test status
Simulation time 1666280577 ps
CPU time 1.24 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 192348 kb
Host smart-46948e4e-cc4e-4204-96a3-1d595f211bbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826087764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.826087764
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3253980447
Short name T363
Test name
Test status
Simulation time 483781518 ps
CPU time 1.98 seconds
Started Jul 26 06:38:47 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 199008 kb
Host smart-bf7d66df-43d3-44e7-b427-d4219028dd44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253980447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3253980447
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.803598041
Short name T309
Test name
Test status
Simulation time 4644810718 ps
CPU time 6.99 seconds
Started Jul 26 06:38:45 PM PDT 24
Finished Jul 26 06:38:52 PM PDT 24
Peak memory 198296 kb
Host smart-2c52d56f-ca9a-49d9-9d71-2b7db4625995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803598041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.803598041
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4071933539
Short name T353
Test name
Test status
Simulation time 330459466 ps
CPU time 0.77 seconds
Started Jul 26 06:38:49 PM PDT 24
Finished Jul 26 06:38:50 PM PDT 24
Peak memory 196528 kb
Host smart-b2c0b160-d3c4-43f9-97b6-d3de1fdc6ec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071933539 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4071933539
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3920485581
Short name T397
Test name
Test status
Simulation time 501839999 ps
CPU time 1.38 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:48 PM PDT 24
Peak memory 193808 kb
Host smart-bb257204-e70b-44e1-bdaa-af00ddce729a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920485581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3920485581
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3842509590
Short name T369
Test name
Test status
Simulation time 419558664 ps
CPU time 1.13 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 184172 kb
Host smart-4dd92420-f481-4050-b35e-a4c2699466e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842509590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3842509590
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.599973297
Short name T348
Test name
Test status
Simulation time 1385499467 ps
CPU time 1.1 seconds
Started Jul 26 06:38:48 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 194000 kb
Host smart-7232dc4d-5e69-4336-9229-dab2fc42a6ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599973297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.599973297
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4082856637
Short name T376
Test name
Test status
Simulation time 430397568 ps
CPU time 2.63 seconds
Started Jul 26 06:38:46 PM PDT 24
Finished Jul 26 06:38:49 PM PDT 24
Peak memory 198964 kb
Host smart-add564e9-c9e8-4f84-84dc-f33dc2336e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082856637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.4082856637
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2727600767
Short name T354
Test name
Test status
Simulation time 4288059355 ps
CPU time 7.49 seconds
Started Jul 26 06:38:45 PM PDT 24
Finished Jul 26 06:38:53 PM PDT 24
Peak memory 198084 kb
Host smart-264d51eb-13c5-4362-9873-e46c7154b8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727600767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2727600767
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1177515403
Short name T346
Test name
Test status
Simulation time 488432938 ps
CPU time 0.86 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:52 PM PDT 24
Peak memory 197236 kb
Host smart-3fde254b-4674-46e6-baf4-2d26dc83d0c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177515403 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1177515403
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2655163255
Short name T73
Test name
Test status
Simulation time 411027365 ps
CPU time 1.15 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:53 PM PDT 24
Peak memory 193704 kb
Host smart-eb85ffbe-6088-4159-aa55-8d1ba20b4751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655163255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2655163255
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2784676200
Short name T388
Test name
Test status
Simulation time 347430372 ps
CPU time 0.76 seconds
Started Jul 26 06:38:54 PM PDT 24
Finished Jul 26 06:38:54 PM PDT 24
Peak memory 193360 kb
Host smart-6e56268d-17f8-4c84-a617-352e08cd528c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784676200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2784676200
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3863014693
Short name T310
Test name
Test status
Simulation time 2351895499 ps
CPU time 2.21 seconds
Started Jul 26 06:38:52 PM PDT 24
Finished Jul 26 06:38:54 PM PDT 24
Peak memory 195592 kb
Host smart-020ffc1b-f0b2-4dd8-99b4-82f24fb4ca68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863014693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3863014693
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1986698834
Short name T379
Test name
Test status
Simulation time 1315472472 ps
CPU time 2.21 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:53 PM PDT 24
Peak memory 198876 kb
Host smart-6e4c4c5f-89a6-4c00-8ae6-619e91560981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986698834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1986698834
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.891830212
Short name T64
Test name
Test status
Simulation time 482815696 ps
CPU time 1 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:20 PM PDT 24
Peak memory 193688 kb
Host smart-b7e1cae7-2b35-482a-a6ef-a60522a7554b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891830212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.891830212
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1170296683
Short name T401
Test name
Test status
Simulation time 7964545985 ps
CPU time 2.3 seconds
Started Jul 26 06:38:07 PM PDT 24
Finished Jul 26 06:38:09 PM PDT 24
Peak memory 192720 kb
Host smart-fb9eeb49-f71e-491a-bc95-1298823b3e06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170296683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1170296683
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1931414072
Short name T319
Test name
Test status
Simulation time 1119984250 ps
CPU time 1.33 seconds
Started Jul 26 06:38:05 PM PDT 24
Finished Jul 26 06:38:06 PM PDT 24
Peak memory 184096 kb
Host smart-eec0aec8-c51b-404e-9296-044f5eff2b81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931414072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1931414072
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4024506008
Short name T408
Test name
Test status
Simulation time 549078035 ps
CPU time 1.58 seconds
Started Jul 26 06:38:12 PM PDT 24
Finished Jul 26 06:38:14 PM PDT 24
Peak memory 196920 kb
Host smart-530d1a38-7307-415f-a0dd-6cbcf88613ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024506008 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4024506008
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.449272440
Short name T66
Test name
Test status
Simulation time 398295660 ps
CPU time 0.9 seconds
Started Jul 26 06:38:04 PM PDT 24
Finished Jul 26 06:38:05 PM PDT 24
Peak memory 193912 kb
Host smart-a7a49b7d-8949-42e0-a7e6-99b85fac145f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449272440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.449272440
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1639666788
Short name T417
Test name
Test status
Simulation time 352613127 ps
CPU time 1.07 seconds
Started Jul 26 06:38:04 PM PDT 24
Finished Jul 26 06:38:05 PM PDT 24
Peak memory 193428 kb
Host smart-fc406c09-ce3a-41d1-a9e0-490d86558dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639666788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1639666788
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.862058110
Short name T331
Test name
Test status
Simulation time 289594833 ps
CPU time 0.63 seconds
Started Jul 26 06:38:03 PM PDT 24
Finished Jul 26 06:38:04 PM PDT 24
Peak memory 184144 kb
Host smart-fdd9bdba-dde4-492e-88d0-a738b02bdd79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862058110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.862058110
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4034219451
Short name T311
Test name
Test status
Simulation time 367728951 ps
CPU time 0.6 seconds
Started Jul 26 06:38:05 PM PDT 24
Finished Jul 26 06:38:06 PM PDT 24
Peak memory 184096 kb
Host smart-0afa132f-9d94-426f-8cd6-6f2ea077b1a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034219451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4034219451
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1612243214
Short name T76
Test name
Test status
Simulation time 931850622 ps
CPU time 1.07 seconds
Started Jul 26 06:38:10 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 193384 kb
Host smart-4af8b2d4-dcb9-4710-8219-103e38285d65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612243214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1612243214
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2881756005
Short name T288
Test name
Test status
Simulation time 362352656 ps
CPU time 1.5 seconds
Started Jul 26 06:38:03 PM PDT 24
Finished Jul 26 06:38:04 PM PDT 24
Peak memory 198860 kb
Host smart-53a69a72-0965-4a7a-b201-c4b085e44c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881756005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2881756005
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2333674996
Short name T313
Test name
Test status
Simulation time 8485478580 ps
CPU time 3.71 seconds
Started Jul 26 06:38:04 PM PDT 24
Finished Jul 26 06:38:08 PM PDT 24
Peak memory 198796 kb
Host smart-d1b19811-e746-4ed8-bdeb-901db2b5c497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333674996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2333674996
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2129578475
Short name T366
Test name
Test status
Simulation time 337220124 ps
CPU time 1 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 184144 kb
Host smart-14128506-4e6f-44b1-9763-fab882ab926f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129578475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2129578475
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.855807986
Short name T323
Test name
Test status
Simulation time 318561032 ps
CPU time 0.76 seconds
Started Jul 26 06:38:52 PM PDT 24
Finished Jul 26 06:38:53 PM PDT 24
Peak memory 184188 kb
Host smart-e387bebd-513a-4c18-8036-7af7244a2a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855807986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.855807986
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.53384737
Short name T293
Test name
Test status
Simulation time 586513825 ps
CPU time 0.62 seconds
Started Jul 26 06:38:50 PM PDT 24
Finished Jul 26 06:38:51 PM PDT 24
Peak memory 193444 kb
Host smart-ef39b3b7-c15a-4b88-abd5-8b1c8b8240fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53384737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.53384737
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1413385457
Short name T282
Test name
Test status
Simulation time 461201041 ps
CPU time 0.68 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:52 PM PDT 24
Peak memory 184172 kb
Host smart-c7ebdc83-4af6-4043-b494-de40e5a9298e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413385457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1413385457
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2518073008
Short name T329
Test name
Test status
Simulation time 291022288 ps
CPU time 0.97 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:52 PM PDT 24
Peak memory 184216 kb
Host smart-7d84f3be-3de3-4e38-9b3f-d16c9db9de7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518073008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2518073008
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3124488565
Short name T382
Test name
Test status
Simulation time 464741141 ps
CPU time 0.61 seconds
Started Jul 26 06:38:51 PM PDT 24
Finished Jul 26 06:38:52 PM PDT 24
Peak memory 184216 kb
Host smart-34706f30-a9b4-4612-99a7-4ab9d0c88a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124488565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3124488565
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1816262417
Short name T286
Test name
Test status
Simulation time 348776535 ps
CPU time 0.66 seconds
Started Jul 26 06:38:58 PM PDT 24
Finished Jul 26 06:38:59 PM PDT 24
Peak memory 184192 kb
Host smart-2f953742-f147-4752-a072-044862c4657f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816262417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1816262417
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.143921351
Short name T404
Test name
Test status
Simulation time 350634172 ps
CPU time 0.78 seconds
Started Jul 26 06:38:58 PM PDT 24
Finished Jul 26 06:38:59 PM PDT 24
Peak memory 184200 kb
Host smart-2ea7c1dc-e62e-4c68-9bc6-28144d1a6efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143921351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.143921351
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2333421905
Short name T384
Test name
Test status
Simulation time 328829894 ps
CPU time 1.05 seconds
Started Jul 26 06:39:02 PM PDT 24
Finished Jul 26 06:39:04 PM PDT 24
Peak memory 184448 kb
Host smart-87f47363-f416-435c-a58e-cfc9d38a9add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333421905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2333421905
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.733497819
Short name T306
Test name
Test status
Simulation time 486624975 ps
CPU time 0.72 seconds
Started Jul 26 06:39:04 PM PDT 24
Finished Jul 26 06:39:05 PM PDT 24
Peak memory 184448 kb
Host smart-cd48e37e-57ea-45b2-a100-a85224d68e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733497819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.733497819
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.384419779
Short name T69
Test name
Test status
Simulation time 522819065 ps
CPU time 1.61 seconds
Started Jul 26 06:38:10 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 195052 kb
Host smart-512aad16-712b-47f7-b717-a8c0fed0c3bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384419779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.384419779
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1097944783
Short name T61
Test name
Test status
Simulation time 12656148258 ps
CPU time 6.29 seconds
Started Jul 26 06:38:12 PM PDT 24
Finished Jul 26 06:38:18 PM PDT 24
Peak memory 192676 kb
Host smart-4c147905-851f-4fdd-9526-1785f25c1a54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097944783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1097944783
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.531721136
Short name T419
Test name
Test status
Simulation time 983674233 ps
CPU time 1.31 seconds
Started Jul 26 06:38:10 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 193524 kb
Host smart-f0db60ef-5d07-4d34-8bd5-9da40e4501e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531721136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.531721136
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2696997
Short name T298
Test name
Test status
Simulation time 514682627 ps
CPU time 1.35 seconds
Started Jul 26 06:38:18 PM PDT 24
Finished Jul 26 06:38:20 PM PDT 24
Peak memory 196208 kb
Host smart-0b8bc9eb-08b8-4282-a29f-8f3f10e021e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696997 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2696997
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.393745798
Short name T68
Test name
Test status
Simulation time 383239131 ps
CPU time 0.73 seconds
Started Jul 26 06:38:12 PM PDT 24
Finished Jul 26 06:38:13 PM PDT 24
Peak memory 193776 kb
Host smart-467433ae-c08c-4eef-bd89-9464b9918739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393745798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.393745798
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1184467570
Short name T312
Test name
Test status
Simulation time 424783000 ps
CPU time 0.75 seconds
Started Jul 26 06:38:11 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 184192 kb
Host smart-1830d879-8d60-4f7d-b1f5-c8afdd61c28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184467570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1184467570
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3019095447
Short name T303
Test name
Test status
Simulation time 390139958 ps
CPU time 0.67 seconds
Started Jul 26 06:38:11 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 184132 kb
Host smart-8a13d7f5-61c6-4910-b399-9277a0770c47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019095447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3019095447
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4201786350
Short name T402
Test name
Test status
Simulation time 348225211 ps
CPU time 1.05 seconds
Started Jul 26 06:38:10 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 183972 kb
Host smart-73473718-2d3f-489b-ae9f-b438d02b08c9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201786350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4201786350
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3386288936
Short name T341
Test name
Test status
Simulation time 801901872 ps
CPU time 1.92 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 193392 kb
Host smart-274823ef-927c-4768-8065-4748ffea7a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386288936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3386288936
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.977980694
Short name T337
Test name
Test status
Simulation time 1014442170 ps
CPU time 2.07 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:22 PM PDT 24
Peak memory 198936 kb
Host smart-73f007a9-47b8-4b49-8ebf-6c4eb915ac6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977980694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.977980694
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3704638328
Short name T37
Test name
Test status
Simulation time 4136321728 ps
CPU time 2.14 seconds
Started Jul 26 06:38:10 PM PDT 24
Finished Jul 26 06:38:12 PM PDT 24
Peak memory 198012 kb
Host smart-8aa9da9e-174a-46fd-9730-49576b96cc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704638328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3704638328
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1706991832
Short name T355
Test name
Test status
Simulation time 301993483 ps
CPU time 0.99 seconds
Started Jul 26 06:39:02 PM PDT 24
Finished Jul 26 06:39:03 PM PDT 24
Peak memory 184148 kb
Host smart-313a5632-2bc3-4710-8790-4075fdc90e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706991832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1706991832
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.508190304
Short name T332
Test name
Test status
Simulation time 349070311 ps
CPU time 0.66 seconds
Started Jul 26 06:38:59 PM PDT 24
Finished Jul 26 06:39:00 PM PDT 24
Peak memory 184180 kb
Host smart-804fd6e0-4e20-4480-a292-25cef94214b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508190304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.508190304
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3230018910
Short name T378
Test name
Test status
Simulation time 506544122 ps
CPU time 1.35 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:59 PM PDT 24
Peak memory 184164 kb
Host smart-9234aede-ed98-4cd3-9805-70f5146af60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230018910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3230018910
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.433663232
Short name T321
Test name
Test status
Simulation time 510178569 ps
CPU time 0.92 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 184180 kb
Host smart-8db5578c-c164-4499-aad2-18562c006fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433663232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.433663232
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4218242321
Short name T349
Test name
Test status
Simulation time 428224676 ps
CPU time 1.19 seconds
Started Jul 26 06:39:01 PM PDT 24
Finished Jul 26 06:39:02 PM PDT 24
Peak memory 184148 kb
Host smart-3ea0c581-6551-4cd2-8a2e-a83929f54cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218242321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4218242321
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.452438944
Short name T398
Test name
Test status
Simulation time 425173111 ps
CPU time 1.16 seconds
Started Jul 26 06:38:56 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 184164 kb
Host smart-a0be4cf8-7d83-4af7-bac6-620e81be4397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452438944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.452438944
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1685997576
Short name T356
Test name
Test status
Simulation time 344529461 ps
CPU time 1.04 seconds
Started Jul 26 06:38:59 PM PDT 24
Finished Jul 26 06:39:00 PM PDT 24
Peak memory 193412 kb
Host smart-172784cf-b38d-4339-b58b-e742b2514589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685997576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1685997576
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3722140002
Short name T361
Test name
Test status
Simulation time 341294274 ps
CPU time 1.04 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 184192 kb
Host smart-ad832764-a661-460a-a1e1-8924ec420586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722140002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3722140002
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2928102344
Short name T302
Test name
Test status
Simulation time 443938020 ps
CPU time 0.72 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 184140 kb
Host smart-d59db252-98aa-4143-ab0c-9c2d89acff32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928102344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2928102344
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4267831754
Short name T367
Test name
Test status
Simulation time 464236229 ps
CPU time 0.9 seconds
Started Jul 26 06:38:55 PM PDT 24
Finished Jul 26 06:38:56 PM PDT 24
Peak memory 184200 kb
Host smart-f248677b-6c1f-4590-8cdf-64a0259009dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267831754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4267831754
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2490673584
Short name T70
Test name
Test status
Simulation time 411879905 ps
CPU time 1.23 seconds
Started Jul 26 06:38:18 PM PDT 24
Finished Jul 26 06:38:20 PM PDT 24
Peak memory 193664 kb
Host smart-883ae330-ed3d-46db-9c51-3717805f6068
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490673584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2490673584
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1636680566
Short name T65
Test name
Test status
Simulation time 14034346903 ps
CPU time 21.14 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:41 PM PDT 24
Peak memory 192676 kb
Host smart-4014d0ba-8833-4b5c-9c77-b13a6e0bfa8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636680566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1636680566
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.178395853
Short name T291
Test name
Test status
Simulation time 777918813 ps
CPU time 0.93 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 192596 kb
Host smart-4fda1b87-84f7-47f2-8234-14a96e43b165
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178395853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.178395853
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.250674748
Short name T412
Test name
Test status
Simulation time 415860610 ps
CPU time 1.04 seconds
Started Jul 26 06:38:20 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 199084 kb
Host smart-3cab22a5-ffbf-45c0-840d-230066b5cb12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250674748 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.250674748
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3134632743
Short name T39
Test name
Test status
Simulation time 292730460 ps
CPU time 0.67 seconds
Started Jul 26 06:38:16 PM PDT 24
Finished Jul 26 06:38:17 PM PDT 24
Peak memory 192456 kb
Host smart-1deb2a4e-c4ca-401d-9f02-a7af8475d682
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134632743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3134632743
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.542940
Short name T322
Test name
Test status
Simulation time 384392281 ps
CPU time 0.68 seconds
Started Jul 26 06:38:17 PM PDT 24
Finished Jul 26 06:38:18 PM PDT 24
Peak memory 184208 kb
Host smart-2a1998ff-e9b9-4e2e-a6f9-955419e4b4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.542940
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.957764484
Short name T392
Test name
Test status
Simulation time 407125364 ps
CPU time 0.65 seconds
Started Jul 26 06:38:22 PM PDT 24
Finished Jul 26 06:38:23 PM PDT 24
Peak memory 184080 kb
Host smart-e8b29b3b-d1f7-4e49-bbf6-bfb025d8bea0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957764484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.957764484
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3235335916
Short name T350
Test name
Test status
Simulation time 310803410 ps
CPU time 0.97 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:20 PM PDT 24
Peak memory 184128 kb
Host smart-32a90e27-45c8-4598-bb08-db4d09390d77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235335916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3235335916
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.766224012
Short name T400
Test name
Test status
Simulation time 2231707042 ps
CPU time 4.03 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:23 PM PDT 24
Peak memory 194596 kb
Host smart-f3e77c16-a21a-4a6e-bedd-71a95827e757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766224012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.766224012
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3590923472
Short name T345
Test name
Test status
Simulation time 859344754 ps
CPU time 2.17 seconds
Started Jul 26 06:38:17 PM PDT 24
Finished Jul 26 06:38:19 PM PDT 24
Peak memory 199000 kb
Host smart-b53c7917-6861-486d-956e-14508861b0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590923472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3590923472
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1326302761
Short name T192
Test name
Test status
Simulation time 8505825688 ps
CPU time 4.13 seconds
Started Jul 26 06:38:18 PM PDT 24
Finished Jul 26 06:38:22 PM PDT 24
Peak memory 198748 kb
Host smart-1f037d6f-4649-4dd6-b6a8-e1d350946930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326302761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1326302761
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.703561678
Short name T414
Test name
Test status
Simulation time 287231756 ps
CPU time 0.64 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 193384 kb
Host smart-01e57455-ab1e-4c5b-9162-446a946801b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703561678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.703561678
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1792362612
Short name T351
Test name
Test status
Simulation time 506836344 ps
CPU time 1.27 seconds
Started Jul 26 06:39:01 PM PDT 24
Finished Jul 26 06:39:03 PM PDT 24
Peak memory 193392 kb
Host smart-e03cfee2-f4e1-4199-be5b-dc24eb60bd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792362612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1792362612
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.534816194
Short name T281
Test name
Test status
Simulation time 321521633 ps
CPU time 1.02 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 193436 kb
Host smart-1b282fd8-3766-4b71-9e9f-d9726deb5a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534816194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.534816194
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3731948973
Short name T360
Test name
Test status
Simulation time 397854304 ps
CPU time 0.76 seconds
Started Jul 26 06:38:59 PM PDT 24
Finished Jul 26 06:39:00 PM PDT 24
Peak memory 193360 kb
Host smart-2e1ad195-b731-4c79-980f-86362c3c0e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731948973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3731948973
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3514963248
Short name T372
Test name
Test status
Simulation time 510787649 ps
CPU time 0.63 seconds
Started Jul 26 06:38:56 PM PDT 24
Finished Jul 26 06:38:56 PM PDT 24
Peak memory 184136 kb
Host smart-f9ce6e9a-7731-4398-abd9-574f7346c8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514963248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3514963248
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.203900045
Short name T296
Test name
Test status
Simulation time 441929163 ps
CPU time 0.81 seconds
Started Jul 26 06:39:01 PM PDT 24
Finished Jul 26 06:39:01 PM PDT 24
Peak memory 184448 kb
Host smart-8786a538-be60-48d3-a520-1fec80ab8c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203900045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.203900045
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2262142036
Short name T307
Test name
Test status
Simulation time 409556119 ps
CPU time 1.03 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:58 PM PDT 24
Peak memory 184204 kb
Host smart-310a68af-cbde-41f9-8c4a-82f38e4c62ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262142036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2262142036
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.674555698
Short name T420
Test name
Test status
Simulation time 430892655 ps
CPU time 0.7 seconds
Started Jul 26 06:39:01 PM PDT 24
Finished Jul 26 06:39:02 PM PDT 24
Peak memory 193384 kb
Host smart-a570a92d-cdc9-458e-a980-b4a3e30fcc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674555698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.674555698
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3196015254
Short name T383
Test name
Test status
Simulation time 474496056 ps
CPU time 1.21 seconds
Started Jul 26 06:38:57 PM PDT 24
Finished Jul 26 06:38:59 PM PDT 24
Peak memory 193408 kb
Host smart-e77e670f-309d-46f3-8a4a-8ddb25074d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196015254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3196015254
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3733425026
Short name T301
Test name
Test status
Simulation time 290049218 ps
CPU time 1.05 seconds
Started Jul 26 06:39:03 PM PDT 24
Finished Jul 26 06:39:04 PM PDT 24
Peak memory 193376 kb
Host smart-3bdc052b-1002-411a-a2c1-1247b355e19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733425026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3733425026
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1069201489
Short name T359
Test name
Test status
Simulation time 514321307 ps
CPU time 1.36 seconds
Started Jul 26 06:38:17 PM PDT 24
Finished Jul 26 06:38:18 PM PDT 24
Peak memory 196304 kb
Host smart-2c4256fe-1f60-4a53-9601-1b8074970d05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069201489 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1069201489
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1337438430
Short name T344
Test name
Test status
Simulation time 330339615 ps
CPU time 1.13 seconds
Started Jul 26 06:38:17 PM PDT 24
Finished Jul 26 06:38:19 PM PDT 24
Peak memory 192480 kb
Host smart-f4facffb-5cbb-4bff-83eb-0e646227d376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337438430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1337438430
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1062532386
Short name T300
Test name
Test status
Simulation time 465195279 ps
CPU time 0.72 seconds
Started Jul 26 06:38:23 PM PDT 24
Finished Jul 26 06:38:23 PM PDT 24
Peak memory 184172 kb
Host smart-d88d55cb-5f50-49b9-b600-daf853951f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062532386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1062532386
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3492253118
Short name T368
Test name
Test status
Simulation time 2691048904 ps
CPU time 2.45 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:22 PM PDT 24
Peak memory 195636 kb
Host smart-a4ee906e-6619-40bd-9de7-cafa761b5fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492253118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3492253118
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2883157344
Short name T325
Test name
Test status
Simulation time 408145392 ps
CPU time 1.86 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 198928 kb
Host smart-7f1c8070-902b-4b3c-8968-974f9a1c5e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883157344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2883157344
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3511175238
Short name T36
Test name
Test status
Simulation time 8190499145 ps
CPU time 3.69 seconds
Started Jul 26 06:38:18 PM PDT 24
Finished Jul 26 06:38:22 PM PDT 24
Peak memory 198728 kb
Host smart-9f3f825b-f97d-427c-960d-ea8ffb5d8598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511175238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3511175238
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.693932249
Short name T413
Test name
Test status
Simulation time 527835618 ps
CPU time 0.85 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:26 PM PDT 24
Peak memory 197976 kb
Host smart-3411d06a-87b7-43e2-84c9-7abf7ad17d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693932249 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.693932249
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4024353239
Short name T364
Test name
Test status
Simulation time 464833088 ps
CPU time 1.19 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 193420 kb
Host smart-4e764da2-a53a-43dd-ae23-ae16e28527c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024353239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4024353239
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.261936303
Short name T390
Test name
Test status
Simulation time 513298170 ps
CPU time 1.37 seconds
Started Jul 26 06:38:22 PM PDT 24
Finished Jul 26 06:38:24 PM PDT 24
Peak memory 184176 kb
Host smart-67f2353e-e139-40ee-b9b6-756a7013cb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261936303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.261936303
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2077029578
Short name T334
Test name
Test status
Simulation time 1258623388 ps
CPU time 2.29 seconds
Started Jul 26 06:38:26 PM PDT 24
Finished Jul 26 06:38:28 PM PDT 24
Peak memory 193380 kb
Host smart-e506e5b0-3d42-4d42-8ed0-fcea6b138b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077029578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2077029578
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.325612007
Short name T411
Test name
Test status
Simulation time 478403954 ps
CPU time 1.93 seconds
Started Jul 26 06:38:19 PM PDT 24
Finished Jul 26 06:38:21 PM PDT 24
Peak memory 199028 kb
Host smart-7c373fc6-fc96-46fa-872f-1ba84dbc7859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325612007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.325612007
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1053118425
Short name T193
Test name
Test status
Simulation time 8218664057 ps
CPU time 12.01 seconds
Started Jul 26 06:38:20 PM PDT 24
Finished Jul 26 06:38:32 PM PDT 24
Peak memory 198768 kb
Host smart-1e83a040-18a4-4b3b-8507-9fc7a3a77497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053118425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1053118425
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2697511367
Short name T314
Test name
Test status
Simulation time 499839608 ps
CPU time 1.44 seconds
Started Jul 26 06:38:29 PM PDT 24
Finished Jul 26 06:38:30 PM PDT 24
Peak memory 196564 kb
Host smart-38a69189-7757-4ca7-9c4e-fff03736c90e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697511367 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2697511367
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.284851497
Short name T381
Test name
Test status
Simulation time 498322210 ps
CPU time 1.37 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:26 PM PDT 24
Peak memory 193404 kb
Host smart-5de093a0-343c-4751-a429-370b55759ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284851497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.284851497
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4042375827
Short name T292
Test name
Test status
Simulation time 359568844 ps
CPU time 0.8 seconds
Started Jul 26 06:38:30 PM PDT 24
Finished Jul 26 06:38:31 PM PDT 24
Peak memory 184208 kb
Host smart-ec3d1307-3d1c-45de-9e2c-e46719182137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042375827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4042375827
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2865252361
Short name T74
Test name
Test status
Simulation time 2240928701 ps
CPU time 1.97 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:27 PM PDT 24
Peak memory 184452 kb
Host smart-8db43bc5-fcf2-469c-8ccf-f3352d446a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865252361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2865252361
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1197974517
Short name T416
Test name
Test status
Simulation time 558073293 ps
CPU time 1.43 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:26 PM PDT 24
Peak memory 199052 kb
Host smart-e2ce4c89-5db3-42b9-a97b-94a9907a6e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197974517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1197974517
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1940168312
Short name T375
Test name
Test status
Simulation time 7566738072 ps
CPU time 11.73 seconds
Started Jul 26 06:38:24 PM PDT 24
Finished Jul 26 06:38:36 PM PDT 24
Peak memory 198656 kb
Host smart-ddb9cccf-05ba-4396-8d25-f8a54fc96def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940168312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1940168312
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4199664998
Short name T386
Test name
Test status
Simulation time 440306822 ps
CPU time 0.82 seconds
Started Jul 26 06:38:29 PM PDT 24
Finished Jul 26 06:38:30 PM PDT 24
Peak memory 197372 kb
Host smart-9c937db7-10b9-4e98-8ba9-1c72d7610968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199664998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.4199664998
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1996786635
Short name T71
Test name
Test status
Simulation time 493888201 ps
CPU time 0.97 seconds
Started Jul 26 06:38:30 PM PDT 24
Finished Jul 26 06:38:31 PM PDT 24
Peak memory 193728 kb
Host smart-526cc2e3-0a25-4476-8036-a887ec328ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996786635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1996786635
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.12005071
Short name T415
Test name
Test status
Simulation time 278987189 ps
CPU time 0.89 seconds
Started Jul 26 06:38:23 PM PDT 24
Finished Jul 26 06:38:24 PM PDT 24
Peak memory 193444 kb
Host smart-ab5a0e83-26e7-4072-9f46-0c93e521d797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.12005071
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1019645405
Short name T421
Test name
Test status
Simulation time 1676543549 ps
CPU time 1.12 seconds
Started Jul 26 06:38:30 PM PDT 24
Finished Jul 26 06:38:31 PM PDT 24
Peak memory 192404 kb
Host smart-abf53e29-1fc3-431e-9634-3f6d414c9914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019645405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1019645405
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3838395084
Short name T370
Test name
Test status
Simulation time 495394555 ps
CPU time 1.93 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:27 PM PDT 24
Peak memory 198964 kb
Host smart-84a30517-17d3-4acb-a4cf-bdd3630d90c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838395084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3838395084
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2385289491
Short name T189
Test name
Test status
Simulation time 4517359131 ps
CPU time 4.34 seconds
Started Jul 26 06:38:26 PM PDT 24
Finished Jul 26 06:38:30 PM PDT 24
Peak memory 198088 kb
Host smart-91cbc4a4-7342-4865-9993-28e74945c54f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385289491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2385289491
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2474196018
Short name T387
Test name
Test status
Simulation time 363302502 ps
CPU time 0.88 seconds
Started Jul 26 06:38:32 PM PDT 24
Finished Jul 26 06:38:33 PM PDT 24
Peak memory 198780 kb
Host smart-b2b63e37-09d1-4ba8-8ba4-15f129a09948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474196018 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2474196018
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2683352930
Short name T67
Test name
Test status
Simulation time 324711654 ps
CPU time 0.66 seconds
Started Jul 26 06:38:32 PM PDT 24
Finished Jul 26 06:38:33 PM PDT 24
Peak memory 192464 kb
Host smart-7766583c-a03a-4ff7-909a-cc55bd0a46d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683352930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2683352930
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1293266588
Short name T407
Test name
Test status
Simulation time 319362935 ps
CPU time 0.61 seconds
Started Jul 26 06:38:23 PM PDT 24
Finished Jul 26 06:38:24 PM PDT 24
Peak memory 184156 kb
Host smart-4acae763-53f3-4bd7-9db4-f9188deac448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293266588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1293266588
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2857276223
Short name T80
Test name
Test status
Simulation time 1081935262 ps
CPU time 2.05 seconds
Started Jul 26 06:38:32 PM PDT 24
Finished Jul 26 06:38:34 PM PDT 24
Peak memory 193428 kb
Host smart-e7baf7b3-49ff-4e94-a26a-f1159c8eb4d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857276223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2857276223
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3366501688
Short name T317
Test name
Test status
Simulation time 562662264 ps
CPU time 1.22 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:27 PM PDT 24
Peak memory 198812 kb
Host smart-efd81c17-9c11-44ea-8653-c5715a0b0022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366501688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3366501688
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2677993313
Short name T191
Test name
Test status
Simulation time 4155132878 ps
CPU time 3.98 seconds
Started Jul 26 06:38:25 PM PDT 24
Finished Jul 26 06:38:29 PM PDT 24
Peak memory 198516 kb
Host smart-a061fb44-2c84-43e8-9c24-acc61de7bdb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677993313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2677993313
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1672913970
Short name T214
Test name
Test status
Simulation time 21806556127 ps
CPU time 9.18 seconds
Started Jul 26 06:36:43 PM PDT 24
Finished Jul 26 06:36:52 PM PDT 24
Peak memory 191824 kb
Host smart-f7546af6-f767-4c1f-b678-c4543c644bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672913970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1672913970
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3782995424
Short name T274
Test name
Test status
Simulation time 575276587 ps
CPU time 0.74 seconds
Started Jul 26 06:36:43 PM PDT 24
Finished Jul 26 06:36:44 PM PDT 24
Peak memory 191600 kb
Host smart-1a5975b6-5bef-4188-b9f2-2fab6c771a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782995424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3782995424
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3475034657
Short name T85
Test name
Test status
Simulation time 6420874737 ps
CPU time 9.34 seconds
Started Jul 26 06:36:41 PM PDT 24
Finished Jul 26 06:36:50 PM PDT 24
Peak memory 196852 kb
Host smart-4cd858d9-dc88-4c0d-80d9-3c911ea042b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475034657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3475034657
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2395213131
Short name T20
Test name
Test status
Simulation time 8575714017 ps
CPU time 12.03 seconds
Started Jul 26 06:36:52 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 215860 kb
Host smart-5678cefc-24c5-4e31-85c8-e244c59f4a02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395213131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2395213131
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1061094004
Short name T278
Test name
Test status
Simulation time 474161979 ps
CPU time 1.3 seconds
Started Jul 26 06:36:44 PM PDT 24
Finished Jul 26 06:36:45 PM PDT 24
Peak memory 191708 kb
Host smart-6bcf2adb-8dea-4c9e-b2a3-608b72ed32c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061094004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1061094004
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3756703581
Short name T212
Test name
Test status
Simulation time 37182202716 ps
CPU time 11.31 seconds
Started Jul 26 06:36:54 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 191828 kb
Host smart-6437c064-0e98-4d05-94c9-8207544cfa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756703581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3756703581
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2536516986
Short name T215
Test name
Test status
Simulation time 397663935 ps
CPU time 0.92 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:36:56 PM PDT 24
Peak memory 191708 kb
Host smart-378cfd1a-4649-4881-8205-c73944a316fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536516986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2536516986
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.139009078
Short name T260
Test name
Test status
Simulation time 3963047452 ps
CPU time 2.22 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:36:58 PM PDT 24
Peak memory 191616 kb
Host smart-e455e640-df1a-4139-8b21-d4eb315f8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139009078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.139009078
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.411688826
Short name T197
Test name
Test status
Simulation time 514213326 ps
CPU time 1.39 seconds
Started Jul 26 06:36:59 PM PDT 24
Finished Jul 26 06:37:01 PM PDT 24
Peak memory 191592 kb
Host smart-9fd3d0a3-e5c1-43e9-bfc3-09cd1ad126c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411688826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.411688826
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4024353949
Short name T53
Test name
Test status
Simulation time 8297783026 ps
CPU time 2.08 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:36:58 PM PDT 24
Peak memory 196780 kb
Host smart-87cbf5e6-5456-4997-9bc4-ba90e5356d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024353949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4024353949
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1499091384
Short name T249
Test name
Test status
Simulation time 420008362 ps
CPU time 0.73 seconds
Started Jul 26 06:37:05 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 191676 kb
Host smart-df9e9abe-4823-4d38-8108-12ee0af3e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499091384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1499091384
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3658385139
Short name T23
Test name
Test status
Simulation time 16936871677 ps
CPU time 6.68 seconds
Started Jul 26 06:36:53 PM PDT 24
Finished Jul 26 06:37:00 PM PDT 24
Peak memory 191828 kb
Host smart-9b9e5cf9-e218-4c41-98fe-39a2c62a4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658385139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3658385139
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.339711460
Short name T228
Test name
Test status
Simulation time 471584888 ps
CPU time 0.64 seconds
Started Jul 26 06:36:53 PM PDT 24
Finished Jul 26 06:36:54 PM PDT 24
Peak memory 191696 kb
Host smart-01315ee1-8133-4350-9c87-4a56738ae0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339711460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.339711460
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1673951212
Short name T195
Test name
Test status
Simulation time 2167657493 ps
CPU time 1.32 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:05 PM PDT 24
Peak memory 191748 kb
Host smart-2085c1af-9ac6-4893-b574-e2c93a42eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673951212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1673951212
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1136121316
Short name T244
Test name
Test status
Simulation time 553079643 ps
CPU time 1.26 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 191652 kb
Host smart-dc27f487-212f-49b5-b3f7-9f266d74b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136121316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1136121316
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3436307225
Short name T255
Test name
Test status
Simulation time 26469918279 ps
CPU time 38.52 seconds
Started Jul 26 06:37:06 PM PDT 24
Finished Jul 26 06:37:44 PM PDT 24
Peak memory 191804 kb
Host smart-648cb8fc-3b1b-4611-ae50-64cf7c10bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436307225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3436307225
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2929981056
Short name T273
Test name
Test status
Simulation time 590586337 ps
CPU time 0.95 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 191648 kb
Host smart-f6df7380-f530-4b8e-a62c-2619aad002e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929981056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2929981056
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1258535820
Short name T188
Test name
Test status
Simulation time 497081079 ps
CPU time 0.69 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 196516 kb
Host smart-1079279c-7306-4049-af5e-ff05e77c674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258535820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1258535820
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3549410501
Short name T269
Test name
Test status
Simulation time 36455176287 ps
CPU time 15.66 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:20 PM PDT 24
Peak memory 191820 kb
Host smart-be448900-eb62-4371-9a09-a05ce7cb3028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549410501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3549410501
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3025048165
Short name T84
Test name
Test status
Simulation time 500387096 ps
CPU time 1.26 seconds
Started Jul 26 06:37:00 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 191704 kb
Host smart-5e9a84f0-91a0-4b13-b6e4-db7220282b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025048165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3025048165
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1367516819
Short name T256
Test name
Test status
Simulation time 13994695511 ps
CPU time 19.28 seconds
Started Jul 26 06:37:03 PM PDT 24
Finished Jul 26 06:37:23 PM PDT 24
Peak memory 191828 kb
Host smart-1d229697-6d63-460c-ab25-61bd7fdfd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367516819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1367516819
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3897877672
Short name T268
Test name
Test status
Simulation time 540186841 ps
CPU time 0.77 seconds
Started Jul 26 06:37:01 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 191696 kb
Host smart-83f6f71b-6281-45b5-ba4a-4f5f87cedef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897877672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3897877672
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.277406859
Short name T217
Test name
Test status
Simulation time 31686930758 ps
CPU time 43.25 seconds
Started Jul 26 06:37:02 PM PDT 24
Finished Jul 26 06:37:45 PM PDT 24
Peak memory 191824 kb
Host smart-26d4b551-1ccb-494a-9ced-839aaea5ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277406859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.277406859
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2056684492
Short name T265
Test name
Test status
Simulation time 520125012 ps
CPU time 0.65 seconds
Started Jul 26 06:37:03 PM PDT 24
Finished Jul 26 06:37:04 PM PDT 24
Peak memory 191700 kb
Host smart-717cf7dc-5ae2-4657-bf99-7a82719e18a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056684492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2056684492
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.775506307
Short name T181
Test name
Test status
Simulation time 526976884 ps
CPU time 0.77 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:37:09 PM PDT 24
Peak memory 196488 kb
Host smart-b1e02c06-e77b-4559-a1f4-e9686fc53864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775506307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.775506307
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1757064844
Short name T251
Test name
Test status
Simulation time 18799808368 ps
CPU time 4.08 seconds
Started Jul 26 06:37:11 PM PDT 24
Finished Jul 26 06:37:15 PM PDT 24
Peak memory 191848 kb
Host smart-dd8d0334-9001-4874-a458-5f7c6f69fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757064844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1757064844
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3437177250
Short name T257
Test name
Test status
Simulation time 525073563 ps
CPU time 0.77 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:37:09 PM PDT 24
Peak memory 191680 kb
Host smart-f2f620a2-1ec3-41a7-8725-07a5d22bb196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437177250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3437177250
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2977004844
Short name T24
Test name
Test status
Simulation time 20669538991 ps
CPU time 5.51 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:36:55 PM PDT 24
Peak memory 191868 kb
Host smart-52825a65-52e7-4374-acae-4fb9648f8b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977004844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2977004844
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.205579883
Short name T19
Test name
Test status
Simulation time 3573822244 ps
CPU time 5.88 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:36:56 PM PDT 24
Peak memory 215404 kb
Host smart-10c83f05-8f11-4ab1-a0ca-29ae8ec176d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205579883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.205579883
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.353461033
Short name T271
Test name
Test status
Simulation time 579329247 ps
CPU time 1.38 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:36:52 PM PDT 24
Peak memory 196548 kb
Host smart-e4966915-1f21-4d40-89a9-f60acb384eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353461033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.353461033
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1193150174
Short name T201
Test name
Test status
Simulation time 32304183958 ps
CPU time 3.12 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:37:12 PM PDT 24
Peak memory 196832 kb
Host smart-493cf4d7-1b87-411a-8b85-1a251601547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193150174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1193150174
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2909185551
Short name T55
Test name
Test status
Simulation time 514754620 ps
CPU time 1.27 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 196588 kb
Host smart-4fd5b010-37fe-4cb0-8c10-62b58cebdba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909185551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2909185551
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1176664463
Short name T204
Test name
Test status
Simulation time 16607271736 ps
CPU time 7.24 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:37:15 PM PDT 24
Peak memory 191728 kb
Host smart-b00bd05e-f24a-43d2-b7d9-49008e465196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176664463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1176664463
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.308838161
Short name T238
Test name
Test status
Simulation time 452108472 ps
CPU time 1.18 seconds
Started Jul 26 06:37:10 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 196456 kb
Host smart-660dc061-e6da-43a5-9569-1f94ba093c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308838161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.308838161
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3772086037
Short name T239
Test name
Test status
Simulation time 29740686482 ps
CPU time 31.96 seconds
Started Jul 26 06:37:08 PM PDT 24
Finished Jul 26 06:37:41 PM PDT 24
Peak memory 196808 kb
Host smart-7bb74ef4-1d12-48cc-b799-3d783d9de6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772086037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3772086037
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1667383185
Short name T248
Test name
Test status
Simulation time 608789966 ps
CPU time 0.73 seconds
Started Jul 26 06:37:06 PM PDT 24
Finished Jul 26 06:37:07 PM PDT 24
Peak memory 191688 kb
Host smart-9ec91d5e-e968-40f6-b353-20150f248aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667383185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1667383185
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4095134389
Short name T230
Test name
Test status
Simulation time 53044447399 ps
CPU time 36.76 seconds
Started Jul 26 06:37:10 PM PDT 24
Finished Jul 26 06:37:47 PM PDT 24
Peak memory 191820 kb
Host smart-57ca8ae6-2640-455f-a988-96732681d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095134389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4095134389
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1536513636
Short name T240
Test name
Test status
Simulation time 490206584 ps
CPU time 1.39 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:11 PM PDT 24
Peak memory 191708 kb
Host smart-72533986-913c-4332-a0d8-b42b22c21a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536513636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1536513636
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.605355170
Short name T11
Test name
Test status
Simulation time 11183769759 ps
CPU time 4.45 seconds
Started Jul 26 06:37:12 PM PDT 24
Finished Jul 26 06:37:16 PM PDT 24
Peak memory 191824 kb
Host smart-7cad5513-10fb-4682-9601-f078719bf786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605355170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.605355170
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.631341153
Short name T235
Test name
Test status
Simulation time 547650465 ps
CPU time 0.73 seconds
Started Jul 26 06:37:09 PM PDT 24
Finished Jul 26 06:37:10 PM PDT 24
Peak memory 191676 kb
Host smart-d1bac4d4-074f-4082-ad75-aefcdf93c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631341153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.631341153
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4111208631
Short name T49
Test name
Test status
Simulation time 16527554585 ps
CPU time 24.09 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:41 PM PDT 24
Peak memory 196848 kb
Host smart-0360910f-6fb9-4f04-9b49-cf41abb450c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111208631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4111208631
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1725940693
Short name T222
Test name
Test status
Simulation time 610029173 ps
CPU time 0.8 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:18 PM PDT 24
Peak memory 196544 kb
Host smart-25f41f64-004f-47a1-a254-ea58f4507a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725940693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1725940693
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2408617271
Short name T280
Test name
Test status
Simulation time 9138731109 ps
CPU time 6.51 seconds
Started Jul 26 06:37:15 PM PDT 24
Finished Jul 26 06:37:22 PM PDT 24
Peak memory 191816 kb
Host smart-904d780d-722b-4a0c-ae96-875d5bfe9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408617271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2408617271
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2382762565
Short name T241
Test name
Test status
Simulation time 436529096 ps
CPU time 0.75 seconds
Started Jul 26 06:37:15 PM PDT 24
Finished Jul 26 06:37:16 PM PDT 24
Peak memory 196500 kb
Host smart-04e2df83-0a06-44da-bfde-589ffaf1bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382762565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2382762565
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1614215151
Short name T237
Test name
Test status
Simulation time 30374477124 ps
CPU time 19.55 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 196800 kb
Host smart-536b0046-607e-4692-bac6-2c15c9e86b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614215151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1614215151
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2303852404
Short name T216
Test name
Test status
Simulation time 517244998 ps
CPU time 0.78 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:18 PM PDT 24
Peak memory 191696 kb
Host smart-cab2d2c2-b0d7-4bf6-aa50-0812ab4bcf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303852404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2303852404
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1167461172
Short name T207
Test name
Test status
Simulation time 39756759262 ps
CPU time 14.98 seconds
Started Jul 26 06:37:23 PM PDT 24
Finished Jul 26 06:37:38 PM PDT 24
Peak memory 191796 kb
Host smart-7aeef121-949f-484d-be75-9ba49a9ebf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167461172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1167461172
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1590175514
Short name T218
Test name
Test status
Simulation time 377648687 ps
CPU time 0.88 seconds
Started Jul 26 06:37:17 PM PDT 24
Finished Jul 26 06:37:18 PM PDT 24
Peak memory 191692 kb
Host smart-03f18fc0-a923-4ba5-95c7-fc35c2c1bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590175514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1590175514
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2975047076
Short name T247
Test name
Test status
Simulation time 39291327460 ps
CPU time 6.81 seconds
Started Jul 26 06:37:21 PM PDT 24
Finished Jul 26 06:37:28 PM PDT 24
Peak memory 191832 kb
Host smart-4d3e6a2b-62dc-45cb-a29e-01295491a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975047076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2975047076
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3168448684
Short name T262
Test name
Test status
Simulation time 388765560 ps
CPU time 0.73 seconds
Started Jul 26 06:37:23 PM PDT 24
Finished Jul 26 06:37:24 PM PDT 24
Peak memory 196464 kb
Host smart-f806e659-4830-482a-a3f0-e606fdd736aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168448684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3168448684
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.804580814
Short name T227
Test name
Test status
Simulation time 23802162127 ps
CPU time 33.62 seconds
Started Jul 26 06:36:52 PM PDT 24
Finished Jul 26 06:37:25 PM PDT 24
Peak memory 196832 kb
Host smart-894591ba-d086-44ba-b887-f32ac9bed168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804580814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.804580814
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3536179719
Short name T18
Test name
Test status
Simulation time 7741417688 ps
CPU time 10.83 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:37:02 PM PDT 24
Peak memory 215744 kb
Host smart-c2d3ddb6-ec5f-4c50-9afc-19113094467b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536179719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3536179719
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2703755576
Short name T266
Test name
Test status
Simulation time 400970298 ps
CPU time 1.17 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:36:51 PM PDT 24
Peak memory 191708 kb
Host smart-521bf69a-0d92-4a60-af37-4a374025fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703755576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2703755576
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1252324168
Short name T234
Test name
Test status
Simulation time 32036545932 ps
CPU time 13.27 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:37:38 PM PDT 24
Peak memory 192068 kb
Host smart-1bb392b6-1bc1-4242-8b08-5ebbac4ed392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252324168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1252324168
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2481792472
Short name T277
Test name
Test status
Simulation time 443694761 ps
CPU time 0.76 seconds
Started Jul 26 06:37:25 PM PDT 24
Finished Jul 26 06:37:25 PM PDT 24
Peak memory 196784 kb
Host smart-b99d914b-0708-4243-bb46-998261d748ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481792472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2481792472
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1231009295
Short name T202
Test name
Test status
Simulation time 24032969737 ps
CPU time 14.99 seconds
Started Jul 26 06:37:22 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 191780 kb
Host smart-8b350124-83d2-47e5-aa52-e801e62897e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231009295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1231009295
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3078938014
Short name T4
Test name
Test status
Simulation time 390759243 ps
CPU time 1.13 seconds
Started Jul 26 06:37:25 PM PDT 24
Finished Jul 26 06:37:26 PM PDT 24
Peak memory 191732 kb
Host smart-1c045044-5f99-473c-a4dc-23feeca7aba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078938014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3078938014
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.537458704
Short name T12
Test name
Test status
Simulation time 47762801530 ps
CPU time 65.83 seconds
Started Jul 26 06:37:22 PM PDT 24
Finished Jul 26 06:38:28 PM PDT 24
Peak memory 191828 kb
Host smart-cc7337b9-5e2f-4801-9266-cb54c1ccfb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537458704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.537458704
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3686300867
Short name T54
Test name
Test status
Simulation time 498920628 ps
CPU time 0.97 seconds
Started Jul 26 06:37:24 PM PDT 24
Finished Jul 26 06:37:25 PM PDT 24
Peak memory 191712 kb
Host smart-475c8e41-d294-42b4-9f8e-fcfd168b1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686300867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3686300867
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1219044428
Short name T220
Test name
Test status
Simulation time 43136361453 ps
CPU time 13.35 seconds
Started Jul 26 06:37:23 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 196808 kb
Host smart-bf936ab2-a8a0-433e-93ea-f43b7a032541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219044428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1219044428
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1262201239
Short name T232
Test name
Test status
Simulation time 505210183 ps
CPU time 0.92 seconds
Started Jul 26 06:37:21 PM PDT 24
Finished Jul 26 06:37:23 PM PDT 24
Peak memory 191732 kb
Host smart-92223498-d271-42da-8d04-517b9ad007b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262201239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1262201239
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1558643430
Short name T242
Test name
Test status
Simulation time 22317367823 ps
CPU time 9.11 seconds
Started Jul 26 06:37:30 PM PDT 24
Finished Jul 26 06:37:40 PM PDT 24
Peak memory 196820 kb
Host smart-9d2ddcdb-278d-44e3-99f6-eaaf4bc7aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558643430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1558643430
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.814099969
Short name T246
Test name
Test status
Simulation time 502468041 ps
CPU time 1.24 seconds
Started Jul 26 06:37:29 PM PDT 24
Finished Jul 26 06:37:31 PM PDT 24
Peak memory 191696 kb
Host smart-46ce5fe8-fcea-405a-bae1-978ea224fea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814099969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.814099969
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1140714221
Short name T253
Test name
Test status
Simulation time 1341536682 ps
CPU time 2.21 seconds
Started Jul 26 06:37:33 PM PDT 24
Finished Jul 26 06:37:35 PM PDT 24
Peak memory 191700 kb
Host smart-83dd03df-8646-4412-90da-11cc24e4dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140714221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1140714221
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4061042396
Short name T31
Test name
Test status
Simulation time 563896412 ps
CPU time 1.42 seconds
Started Jul 26 06:37:31 PM PDT 24
Finished Jul 26 06:37:32 PM PDT 24
Peak memory 191708 kb
Host smart-aadb984b-c6a3-4375-a3bf-d34d215c7f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061042396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4061042396
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1349526082
Short name T250
Test name
Test status
Simulation time 7134682895 ps
CPU time 11.87 seconds
Started Jul 26 06:37:31 PM PDT 24
Finished Jul 26 06:37:43 PM PDT 24
Peak memory 191848 kb
Host smart-f5876536-12b6-45c2-9671-4cafa00dc95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349526082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1349526082
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1377962082
Short name T259
Test name
Test status
Simulation time 395543871 ps
CPU time 1.13 seconds
Started Jul 26 06:37:29 PM PDT 24
Finished Jul 26 06:37:30 PM PDT 24
Peak memory 191708 kb
Host smart-2f9e3a16-d9d1-4d43-91a6-d3c12a851225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377962082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1377962082
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2698947531
Short name T264
Test name
Test status
Simulation time 12205221551 ps
CPU time 16.17 seconds
Started Jul 26 06:37:34 PM PDT 24
Finished Jul 26 06:37:50 PM PDT 24
Peak memory 196836 kb
Host smart-7bd0aedc-bf3a-49fd-952a-94bd0d50a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698947531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2698947531
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.393707346
Short name T229
Test name
Test status
Simulation time 335847007 ps
CPU time 1.09 seconds
Started Jul 26 06:37:32 PM PDT 24
Finished Jul 26 06:37:33 PM PDT 24
Peak memory 191712 kb
Host smart-e0d82c32-b02a-419b-ac70-dfa54784dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393707346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.393707346
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1599895732
Short name T252
Test name
Test status
Simulation time 19464583100 ps
CPU time 7.94 seconds
Started Jul 26 06:37:40 PM PDT 24
Finished Jul 26 06:37:48 PM PDT 24
Peak memory 191804 kb
Host smart-3da1d1cb-3c70-4762-8ffa-5dace14e5bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599895732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1599895732
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2200876293
Short name T199
Test name
Test status
Simulation time 353968491 ps
CPU time 0.99 seconds
Started Jul 26 06:37:36 PM PDT 24
Finished Jul 26 06:37:37 PM PDT 24
Peak memory 191688 kb
Host smart-6ffc9ad8-d721-4305-ac6b-72889e4ac888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200876293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2200876293
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2778508846
Short name T226
Test name
Test status
Simulation time 23553198961 ps
CPU time 2.77 seconds
Started Jul 26 06:37:38 PM PDT 24
Finished Jul 26 06:37:41 PM PDT 24
Peak memory 196804 kb
Host smart-097b041f-0a2c-406f-a77a-07d056c11afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778508846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2778508846
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3721557879
Short name T270
Test name
Test status
Simulation time 480074139 ps
CPU time 0.96 seconds
Started Jul 26 06:37:40 PM PDT 24
Finished Jul 26 06:37:41 PM PDT 24
Peak memory 196332 kb
Host smart-36fe609b-02a5-450d-b69d-79c551ea77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721557879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3721557879
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2294318133
Short name T213
Test name
Test status
Simulation time 19960284807 ps
CPU time 3.52 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:36:55 PM PDT 24
Peak memory 196772 kb
Host smart-8c059b16-cf86-49ad-9645-32e8eed28f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294318133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2294318133
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.916301990
Short name T21
Test name
Test status
Simulation time 8174657991 ps
CPU time 6.32 seconds
Started Jul 26 06:36:51 PM PDT 24
Finished Jul 26 06:36:57 PM PDT 24
Peak memory 215852 kb
Host smart-7cfec98e-0fe1-4bf1-9220-3a9088cfe767
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916301990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.916301990
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2706041365
Short name T245
Test name
Test status
Simulation time 372118007 ps
CPU time 0.73 seconds
Started Jul 26 06:36:47 PM PDT 24
Finished Jul 26 06:36:48 PM PDT 24
Peak memory 191720 kb
Host smart-1d9082e1-501f-47c7-8797-872b125183b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706041365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2706041365
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3544761701
Short name T267
Test name
Test status
Simulation time 4413028150 ps
CPU time 2.31 seconds
Started Jul 26 06:37:40 PM PDT 24
Finished Jul 26 06:37:43 PM PDT 24
Peak memory 196804 kb
Host smart-b48f1744-f1bb-490a-96d6-fccd6498a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544761701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3544761701
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.754121754
Short name T219
Test name
Test status
Simulation time 359924106 ps
CPU time 0.72 seconds
Started Jul 26 06:37:35 PM PDT 24
Finished Jul 26 06:37:36 PM PDT 24
Peak memory 196588 kb
Host smart-dd908ad6-cf38-4d84-8bb8-e7d1ba2a182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754121754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.754121754
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.30092899
Short name T175
Test name
Test status
Simulation time 545527868 ps
CPU time 0.99 seconds
Started Jul 26 06:37:35 PM PDT 24
Finished Jul 26 06:37:36 PM PDT 24
Peak memory 196600 kb
Host smart-e53e532e-7757-4f17-bd5a-489462af73ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30092899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.30092899
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2956191981
Short name T196
Test name
Test status
Simulation time 39763319696 ps
CPU time 15.14 seconds
Started Jul 26 06:37:36 PM PDT 24
Finished Jul 26 06:37:51 PM PDT 24
Peak memory 196824 kb
Host smart-0da21a1e-e1e9-4057-b28d-66b7a8f09cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956191981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2956191981
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2195212648
Short name T208
Test name
Test status
Simulation time 444804039 ps
CPU time 1.16 seconds
Started Jul 26 06:37:38 PM PDT 24
Finished Jul 26 06:37:39 PM PDT 24
Peak memory 196564 kb
Host smart-b17dc24b-878a-495a-8fcd-06ba6f613342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195212648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2195212648
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1727351328
Short name T236
Test name
Test status
Simulation time 4144636853 ps
CPU time 6.08 seconds
Started Jul 26 06:37:43 PM PDT 24
Finished Jul 26 06:37:49 PM PDT 24
Peak memory 196584 kb
Host smart-f75385d1-cca1-4c2f-b393-f3b0842d5294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727351328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1727351328
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3522461927
Short name T231
Test name
Test status
Simulation time 430194810 ps
CPU time 1.1 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:37:46 PM PDT 24
Peak memory 191736 kb
Host smart-7b5656b1-d9d3-4c4b-bbb5-61ab59ab5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522461927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3522461927
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3325849199
Short name T198
Test name
Test status
Simulation time 2017467510 ps
CPU time 1.37 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:37:46 PM PDT 24
Peak memory 196412 kb
Host smart-25939834-221e-41ee-9995-7c0c8cda5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325849199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3325849199
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.977977771
Short name T210
Test name
Test status
Simulation time 352923739 ps
CPU time 1.05 seconds
Started Jul 26 06:37:45 PM PDT 24
Finished Jul 26 06:37:46 PM PDT 24
Peak memory 191704 kb
Host smart-516387c2-9fd5-4e67-a48c-a9286d58a8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977977771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.977977771
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.874137870
Short name T225
Test name
Test status
Simulation time 26274971469 ps
CPU time 7.37 seconds
Started Jul 26 06:37:44 PM PDT 24
Finished Jul 26 06:37:51 PM PDT 24
Peak memory 196820 kb
Host smart-7666a101-df18-4a3c-9354-afc7f1ccd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874137870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.874137870
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.962906438
Short name T254
Test name
Test status
Simulation time 422867251 ps
CPU time 0.79 seconds
Started Jul 26 06:37:42 PM PDT 24
Finished Jul 26 06:37:43 PM PDT 24
Peak memory 191700 kb
Host smart-35e9085f-b540-4728-ad8a-d27bce8e92d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962906438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.962906438
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3931532516
Short name T223
Test name
Test status
Simulation time 10072870870 ps
CPU time 16.09 seconds
Started Jul 26 06:37:44 PM PDT 24
Finished Jul 26 06:38:00 PM PDT 24
Peak memory 191820 kb
Host smart-d33c1844-374e-4bf5-afa0-372ac16b3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931532516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3931532516
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4201995401
Short name T279
Test name
Test status
Simulation time 551517023 ps
CPU time 0.75 seconds
Started Jul 26 06:37:44 PM PDT 24
Finished Jul 26 06:37:45 PM PDT 24
Peak memory 191684 kb
Host smart-e694d9c6-0873-4df3-be66-551eb076e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201995401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4201995401
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1722745564
Short name T87
Test name
Test status
Simulation time 187414809594 ps
CPU time 244.7 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:41:57 PM PDT 24
Peak memory 183624 kb
Host smart-7dd2b01e-79e5-4926-a701-514955c202f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722745564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1722745564
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.292697141
Short name T205
Test name
Test status
Simulation time 6373152268 ps
CPU time 10.05 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:38:02 PM PDT 24
Peak memory 191812 kb
Host smart-a3324dea-34cb-4f56-b687-4d30f036fcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292697141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.292697141
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1025630681
Short name T272
Test name
Test status
Simulation time 529926596 ps
CPU time 0.94 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:37:53 PM PDT 24
Peak memory 191736 kb
Host smart-8cf0fc68-4a34-4643-bd6c-5ba2f144be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025630681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1025630681
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.800949641
Short name T48
Test name
Test status
Simulation time 48668643143 ps
CPU time 37.79 seconds
Started Jul 26 06:37:53 PM PDT 24
Finished Jul 26 06:38:31 PM PDT 24
Peak memory 191808 kb
Host smart-8ec49292-20b3-41c9-a344-c3601173fa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800949641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.800949641
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4143178004
Short name T203
Test name
Test status
Simulation time 528899864 ps
CPU time 1.21 seconds
Started Jul 26 06:37:52 PM PDT 24
Finished Jul 26 06:37:53 PM PDT 24
Peak memory 196500 kb
Host smart-757e1e5c-4bec-4aad-aae5-8c3033c86fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143178004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4143178004
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.196872945
Short name T275
Test name
Test status
Simulation time 25478880942 ps
CPU time 19.75 seconds
Started Jul 26 06:37:49 PM PDT 24
Finished Jul 26 06:38:09 PM PDT 24
Peak memory 191792 kb
Host smart-6be4bb49-64be-44f9-aced-cdb6ac752cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196872945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.196872945
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.412196363
Short name T276
Test name
Test status
Simulation time 610441463 ps
CPU time 0.81 seconds
Started Jul 26 06:37:50 PM PDT 24
Finished Jul 26 06:37:51 PM PDT 24
Peak memory 196456 kb
Host smart-a0deccc3-3d91-4b52-a383-4080ad7b3932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412196363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.412196363
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3835481213
Short name T263
Test name
Test status
Simulation time 20018970613 ps
CPU time 7.8 seconds
Started Jul 26 06:38:02 PM PDT 24
Finished Jul 26 06:38:10 PM PDT 24
Peak memory 196836 kb
Host smart-e82889a4-054e-4935-b17d-8264f7225a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835481213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3835481213
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2306135839
Short name T209
Test name
Test status
Simulation time 561347303 ps
CPU time 0.79 seconds
Started Jul 26 06:38:00 PM PDT 24
Finished Jul 26 06:38:01 PM PDT 24
Peak memory 196520 kb
Host smart-f5b4b359-86de-4d1f-a843-bd8497668f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306135839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2306135839
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3082918869
Short name T174
Test name
Test status
Simulation time 487956601 ps
CPU time 1.27 seconds
Started Jul 26 06:36:49 PM PDT 24
Finished Jul 26 06:36:50 PM PDT 24
Peak memory 196576 kb
Host smart-5820e368-0e6a-42d7-a60f-c73fbde4e34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082918869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3082918869
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.690079834
Short name T224
Test name
Test status
Simulation time 2540597068 ps
CPU time 2.93 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:36:53 PM PDT 24
Peak memory 191812 kb
Host smart-4a26824d-79c1-4098-8292-3ee9b2454b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690079834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.690079834
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2062774960
Short name T211
Test name
Test status
Simulation time 541128734 ps
CPU time 1.23 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:36:51 PM PDT 24
Peak memory 196504 kb
Host smart-ada62466-b347-4f75-9499-1e8e80b74d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062774960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2062774960
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.289217087
Short name T206
Test name
Test status
Simulation time 37185255372 ps
CPU time 27.2 seconds
Started Jul 26 06:36:50 PM PDT 24
Finished Jul 26 06:37:18 PM PDT 24
Peak memory 191824 kb
Host smart-fb19a416-a07f-437c-a55c-04c251e65309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289217087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.289217087
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3456938274
Short name T200
Test name
Test status
Simulation time 471594534 ps
CPU time 0.77 seconds
Started Jul 26 06:36:52 PM PDT 24
Finished Jul 26 06:36:53 PM PDT 24
Peak memory 196496 kb
Host smart-25d30110-1390-4dbf-aa18-452f7837b8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456938274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3456938274
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.875917533
Short name T261
Test name
Test status
Simulation time 25198049733 ps
CPU time 17.26 seconds
Started Jul 26 06:37:04 PM PDT 24
Finished Jul 26 06:37:21 PM PDT 24
Peak memory 191808 kb
Host smart-c691724b-1a61-4990-9dfe-39885a3d1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875917533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.875917533
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.473609105
Short name T5
Test name
Test status
Simulation time 532743856 ps
CPU time 0.76 seconds
Started Jul 26 06:36:58 PM PDT 24
Finished Jul 26 06:36:59 PM PDT 24
Peak memory 196416 kb
Host smart-41e8ce58-99fd-4590-94b3-969dbaa25b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473609105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.473609105
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.281372909
Short name T221
Test name
Test status
Simulation time 27320137536 ps
CPU time 11.13 seconds
Started Jul 26 06:36:58 PM PDT 24
Finished Jul 26 06:37:09 PM PDT 24
Peak memory 191824 kb
Host smart-40155020-7ae1-4674-92fc-15485a95074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281372909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.281372909
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3246890995
Short name T243
Test name
Test status
Simulation time 475876481 ps
CPU time 0.74 seconds
Started Jul 26 06:36:54 PM PDT 24
Finished Jul 26 06:36:55 PM PDT 24
Peak memory 191656 kb
Host smart-8d4601a8-c48d-4bdc-b45f-4a7bcd531a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246890995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3246890995
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3199394680
Short name T258
Test name
Test status
Simulation time 33834235294 ps
CPU time 5.61 seconds
Started Jul 26 06:36:55 PM PDT 24
Finished Jul 26 06:37:00 PM PDT 24
Peak memory 191856 kb
Host smart-5c681e9d-ae04-4bf4-882a-15463d5ed70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199394680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3199394680
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.874403243
Short name T233
Test name
Test status
Simulation time 504405213 ps
CPU time 1.2 seconds
Started Jul 26 06:36:56 PM PDT 24
Finished Jul 26 06:36:57 PM PDT 24
Peak memory 191708 kb
Host smart-5d441317-f2cb-4af0-b2c8-c88789ac4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874403243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.874403243
Directory /workspace/9.aon_timer_smoke/latest
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