Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	34434	1		T1	783		T2	233		T3	205
bark[1]	545	1		T39	244		T48	96		T81	30
bark[2]	809	1		T2	21		T3	203		T39	21
bark[3]	945	1		T7	26		T13	61		T44	21
bark[4]	349	1		T14	21		T41	204		T125	40
bark[5]	244	1		T14	21		T38	102		T114	21
bark[6]	299	1		T7	14		T81	73		T108	30
bark[7]	723	1		T18	21		T31	21		T32	21
bark[8]	448	1		T31	45		T45	14		T96	287
bark[9]	667	1		T3	73		T13	26		T41	112
bark[10]	1139	1		T3	224		T13	236		T14	21
bark[11]	864	1		T32	47		T42	21		T83	14
bark[12]	438	1		T14	69		T40	21		T132	21
bark[13]	259	1		T31	95		T47	14		T119	21
bark[14]	686	1		T4	14		T32	21		T127	14
bark[15]	382	1		T2	14		T40	47		T187	14
bark[16]	357	1		T41	111		T137	21		T139	47
bark[17]	273	1		T132	21		T98	21		T169	21
bark[18]	325	1		T130	14		T39	21		T158	70
bark[19]	756	1		T1	262		T7	52		T44	14
bark[20]	282	1		T3	26		T18	54		T31	21
bark[21]	499	1		T32	35		T40	21		T131	21
bark[22]	356	1		T1	26		T13	7		T31	31
bark[23]	347	1		T14	56		T96	43		T81	26
bark[24]	871	1		T14	26		T97	184		T98	248
bark[25]	364	1		T31	107		T131	21		T139	21
bark[26]	1052	1		T42	69		T114	35		T145	30
bark[27]	932	1		T7	21		T132	38		T97	99
bark[28]	241	1		T39	26		T152	21		T129	21
bark[29]	567	1		T79	14		T126	88		T139	21
bark[30]	907	1		T3	96		T13	21		T32	21
bark[31]	296	1		T1	114		T39	7		T40	14
bark_0	4684	1		T1	88		T2	7		T3	79

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	33895	1		T1	777		T2	207		T3	200
bite[1]	546	1		T39	243		T97	21		T92	21
bite[2]	173	1		T41	21		T96	25		T129	21
bite[3]	1171	1		T41	110		T96	286		T48	95
bite[4]	647	1		T158	70		T40	13		T80	13
bite[5]	669	1		T38	101		T42	21		T127	13
bite[6]	900	1		T14	21		T18	21		T31	106
bite[7]	604	1		T3	223		T152	47		T49	13
bite[8]	875	1		T7	21		T13	235		T31	94
bite[9]	635	1		T1	119		T14	26		T32	34
bite[10]	501	1		T4	13		T98	21		T108	30
bite[11]	812	1		T1	171		T2	21		T32	21
bite[12]	275	1		T3	25		T14	21		T40	55
bite[13]	387	1		T1	25		T101	21		T117	21
bite[14]	251	1		T7	26		T130	13		T181	13
bite[15]	705	1		T7	52		T79	13		T97	230
bite[16]	507	1		T13	60		T45	13		T39	13
bite[17]	711	1		T97	21		T160	116		T108	283
bite[18]	255	1		T2	13		T32	21		T39	21
bite[19]	228	1		T7	13		T40	46		T98	21
bite[20]	773	1		T3	95		T157	275		T23	13
bite[21]	356	1		T40	21		T102	25		T119	30
bite[22]	691	1		T14	21		T18	54		T39	21
bite[23]	740	1		T1	83		T3	202		T14	68
bite[24]	438	1		T31	30		T42	110		T98	21
bite[25]	292	1		T7	56		T13	6		T31	44
bite[26]	629	1		T13	21		T114	21		T137	40
bite[27]	261	1		T47	13		T158	13		T152	21
bite[28]	512	1		T2	26		T13	25		T39	6
bite[29]	530	1		T14	55		T85	13		T129	21
bite[30]	544	1		T3	72		T32	21		T158	104
bite[31]	615	1		T44	21		T114	21		T97	21
bite_0	5212	1		T1	98		T2	8		T3	89

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45457	1		T1	941		T2	218		T3	906
auto[1]	10883	1		T1	332		T2	57		T8	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1613	1		T2	24		T14	36		T38	72
prescale[1]	1134	1		T1	19		T3	117		T41	47
prescale[2]	881	1		T2	30		T18	67		T39	195
prescale[3]	1123	1		T3	83		T9	9		T14	71
prescale[4]	725	1		T3	19		T7	49		T18	19
prescale[5]	558	1		T1	2		T158	40		T41	61
prescale[6]	986	1		T1	19		T31	19		T32	19
prescale[7]	1174	1		T1	28		T3	19		T5	9
prescale[8]	550	1		T1	21		T3	2		T40	33
prescale[9]	1097	1		T1	36		T3	45		T14	2
prescale[10]	1526	1		T1	119		T13	2		T31	214
prescale[11]	994	1		T13	66		T14	42		T44	19
prescale[12]	1182	1		T1	40		T31	2		T158	19
prescale[13]	1329	1		T1	73		T3	2		T13	26
prescale[14]	1201	1		T1	45		T7	19		T39	26
prescale[15]	597	1		T6	9		T39	23		T81	2
prescale[16]	941	1		T11	9		T13	41		T31	2
prescale[17]	1024	1		T31	18		T158	49		T42	2
prescale[18]	1064	1		T3	2		T14	26		T39	2
prescale[19]	889	1		T1	47		T3	67		T31	40
prescale[20]	814	1		T3	2		T13	2		T39	2
prescale[21]	1139	1		T44	28		T38	59		T39	57
prescale[22]	836	1		T44	57		T40	30		T41	118
prescale[23]	706	1		T1	57		T2	19		T7	28
prescale[24]	500	1		T13	2		T14	2		T31	49
prescale[25]	904	1		T1	19		T12	9		T41	2
prescale[26]	807	1		T14	71		T31	19		T40	23
prescale[27]	1243	1		T43	9		T32	19		T39	2
prescale[28]	633	1		T1	4		T39	44		T158	19
prescale[29]	409	1		T2	19		T3	2		T13	79
prescale[30]	920	1		T3	2		T7	19		T14	6
prescale[31]	856	1		T18	19		T31	42		T40	56
prescale_0	25985	1		T1	744		T2	183		T3	544

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42836	1		T1	1123		T2	66		T3	769
auto[1]	13504	1		T1	150		T2	209		T3	137

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	56340	1		T1	1273		T2	275		T3	906

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	33858	1		T1	852		T2	208		T3	516
wkup[1]	331	1		T3	21		T13	21		T41	30
wkup[2]	275	1		T39	51		T42	21		T127	15
wkup[3]	292	1		T1	30		T31	51		T114	35
wkup[4]	364	1		T39	24		T40	30		T41	15
wkup[5]	243	1		T129	30		T97	21		T98	21
wkup[6]	342	1		T1	26		T3	26		T31	21
wkup[7]	240	1		T125	21		T160	21		T126	21
wkup[8]	254	1		T14	21		T92	21		T135	30
wkup[9]	241	1		T1	21		T181	15		T96	21
wkup[10]	426	1		T32	21		T152	21		T81	21
wkup[11]	324	1		T1	21		T32	21		T40	21
wkup[12]	174	1		T97	8		T92	21		T186	21
wkup[13]	263	1		T1	30		T184	15		T96	21
wkup[14]	216	1		T3	21		T13	21		T98	21
wkup[15]	265	1		T1	21		T39	21		T41	47
wkup[16]	183	1		T3	21		T81	21		T157	24
wkup[17]	188	1		T3	21		T31	21		T83	15
wkup[18]	361	1		T32	21		T132	21		T97	26
wkup[19]	240	1		T158	15		T41	21		T102	21
wkup[20]	532	1		T1	21		T14	21		T31	42
wkup[21]	299	1		T7	30		T13	8		T42	21
wkup[22]	259	1		T129	21		T110	35		T160	21
wkup[23]	363	1		T2	26		T14	21		T39	21
wkup[24]	288	1		T13	21		T31	30		T39	21
wkup[25]	269	1		T1	26		T31	21		T38	21
wkup[26]	259	1		T3	30		T7	21		T13	21
wkup[27]	557	1		T158	21		T40	21		T41	21
wkup[28]	277	1		T14	21		T32	21		T39	21
wkup[29]	162	1		T14	21		T41	15		T96	21
wkup[30]	351	1		T14	26		T44	15		T38	21
wkup[31]	256	1		T38	26		T39	26		T81	21
wkup[32]	283	1		T1	30		T97	21		T157	21
wkup[33]	394	1		T1	21		T2	21		T38	21
wkup[34]	485	1		T1	21		T31	26		T39	21
wkup[35]	222	1		T41	21		T42	21		T97	21
wkup[36]	299	1		T41	21		T119	21		T139	51
wkup[37]	412	1		T3	21		T31	51		T40	23
wkup[38]	227	1		T7	15		T98	21		T186	30
wkup[39]	165	1		T44	21		T97	15		T101	21
wkup[40]	207	1		T41	21		T98	21		T125	21
wkup[41]	428	1		T1	15		T7	21		T31	21
wkup[42]	294	1		T3	21		T14	49		T41	21
wkup[43]	152	1		T42	21		T143	21		T98	21
wkup[44]	309	1		T3	30		T13	21		T31	21
wkup[45]	328	1		T14	30		T31	21		T38	15
wkup[46]	317	1		T3	8		T18	21		T44	21
wkup[47]	341	1		T32	15		T38	21		T41	21
wkup[48]	290	1		T1	21		T7	31		T38	35
wkup[49]	419	1		T4	15		T38	21		T40	21
wkup[50]	495	1		T3	21		T38	41		T41	21
wkup[51]	290	1		T3	21		T160	21		T108	21
wkup[52]	252	1		T1	21		T31	21		T158	21
wkup[53]	407	1		T2	15		T40	21		T114	21
wkup[54]	321	1		T1	21		T31	29		T129	21
wkup[55]	309	1		T45	15		T41	21		T96	21
wkup[56]	264	1		T3	30		T97	63		T160	30
wkup[57]	261	1		T40	21		T129	21		T157	51
wkup[58]	204	1		T1	21		T3	39		T18	21
wkup[59]	149	1		T31	21		T187	15		T126	26
wkup[60]	331	1		T13	26		T39	21		T78	15
wkup[61]	337	1		T7	26		T130	15		T97	45
wkup[62]	188	1		T14	26		T157	21		T98	21
wkup[63]	335	1		T18	35		T40	21		T97	26
wkup_0	3673	1		T1	54		T2	5		T3	59