Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.06 99.33 93.67 100.00 98.40 99.51 49.48


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T288 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1698581788 Jul 27 06:22:50 PM PDT 24 Jul 27 06:22:51 PM PDT 24 442534051 ps
T33 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2909825225 Jul 27 06:22:15 PM PDT 24 Jul 27 06:22:16 PM PDT 24 552562183 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1263795071 Jul 27 06:22:07 PM PDT 24 Jul 27 06:22:08 PM PDT 24 384523478 ps
T34 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.744941691 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:36 PM PDT 24 533077480 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3966459461 Jul 27 06:21:40 PM PDT 24 Jul 27 06:21:40 PM PDT 24 429124457 ps
T291 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1073650673 Jul 27 06:22:38 PM PDT 24 Jul 27 06:22:41 PM PDT 24 418560122 ps
T292 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2398386940 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:49 PM PDT 24 397081981 ps
T35 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3343739579 Jul 27 06:22:14 PM PDT 24 Jul 27 06:22:22 PM PDT 24 4289807164 ps
T86 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2824971789 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:28 PM PDT 24 1427723785 ps
T202 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1983698689 Jul 27 06:22:36 PM PDT 24 Jul 27 06:22:37 PM PDT 24 384726288 ps
T87 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1744343920 Jul 27 06:22:24 PM PDT 24 Jul 27 06:22:25 PM PDT 24 1580294727 ps
T52 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.509897441 Jul 27 06:22:39 PM PDT 24 Jul 27 06:22:41 PM PDT 24 388850874 ps
T293 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.967957728 Jul 27 06:22:14 PM PDT 24 Jul 27 06:22:15 PM PDT 24 371321223 ps
T36 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3607557571 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:55 PM PDT 24 4524473526 ps
T53 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4280800974 Jul 27 06:22:14 PM PDT 24 Jul 27 06:22:14 PM PDT 24 452976868 ps
T294 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3957379317 Jul 27 06:22:46 PM PDT 24 Jul 27 06:22:48 PM PDT 24 460144798 ps
T88 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3868397352 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:28 PM PDT 24 865692014 ps
T37 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3586768083 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:30 PM PDT 24 8534185170 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.171248838 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:50 PM PDT 24 312012214 ps
T194 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3278460406 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:32 PM PDT 24 4326981636 ps
T89 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3053115655 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:35 PM PDT 24 2426896806 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3967525518 Jul 27 06:22:08 PM PDT 24 Jul 27 06:22:09 PM PDT 24 457870248 ps
T296 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3072421201 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:50 PM PDT 24 435154477 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1091137775 Jul 27 06:21:59 PM PDT 24 Jul 27 06:22:01 PM PDT 24 435331768 ps
T298 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2200131423 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:28 PM PDT 24 335658110 ps
T299 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2626517324 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:49 PM PDT 24 491974086 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.589950797 Jul 27 06:21:39 PM PDT 24 Jul 27 06:21:40 PM PDT 24 414386351 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1284826018 Jul 27 06:21:56 PM PDT 24 Jul 27 06:21:58 PM PDT 24 611681379 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1051367103 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:35 PM PDT 24 521151468 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3380972695 Jul 27 06:21:59 PM PDT 24 Jul 27 06:22:09 PM PDT 24 11871710803 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.276050830 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:50 PM PDT 24 655713547 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4119322264 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:49 PM PDT 24 403687864 ps
T305 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.179301463 Jul 27 06:22:24 PM PDT 24 Jul 27 06:22:25 PM PDT 24 347426215 ps
T195 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4249807304 Jul 27 06:22:35 PM PDT 24 Jul 27 06:22:39 PM PDT 24 4137728955 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1821974431 Jul 27 06:21:41 PM PDT 24 Jul 27 06:21:42 PM PDT 24 1292897857 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.373125145 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:07 PM PDT 24 762685735 ps
T196 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.827511893 Jul 27 06:22:35 PM PDT 24 Jul 27 06:22:38 PM PDT 24 4912676143 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3703426095 Jul 27 06:21:56 PM PDT 24 Jul 27 06:21:57 PM PDT 24 519142567 ps
T90 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.599335907 Jul 27 06:22:39 PM PDT 24 Jul 27 06:22:42 PM PDT 24 2893683886 ps
T307 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2485926260 Jul 27 06:22:54 PM PDT 24 Jul 27 06:22:55 PM PDT 24 431545345 ps
T58 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1269392740 Jul 27 06:22:35 PM PDT 24 Jul 27 06:22:36 PM PDT 24 366024228 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3801589147 Jul 27 06:22:09 PM PDT 24 Jul 27 06:22:11 PM PDT 24 541529941 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1541972593 Jul 27 06:22:36 PM PDT 24 Jul 27 06:22:38 PM PDT 24 362220011 ps
T91 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1207261104 Jul 27 06:22:29 PM PDT 24 Jul 27 06:22:30 PM PDT 24 1127609124 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2499858732 Jul 27 06:22:50 PM PDT 24 Jul 27 06:22:52 PM PDT 24 603237018 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2230754227 Jul 27 06:21:56 PM PDT 24 Jul 27 06:21:57 PM PDT 24 455145459 ps
T312 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.154185514 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:49 PM PDT 24 446171549 ps
T63 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.913027050 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:26 PM PDT 24 341308901 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3721784298 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:27 PM PDT 24 548163699 ps
T314 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2466115367 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:28 PM PDT 24 525469461 ps
T315 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1956083133 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:34 PM PDT 24 370987453 ps
T316 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.786858650 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:29 PM PDT 24 8296617132 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3030455661 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:27 PM PDT 24 389731945 ps
T318 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4078558825 Jul 27 06:22:54 PM PDT 24 Jul 27 06:22:56 PM PDT 24 358273833 ps
T319 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1669053946 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:07 PM PDT 24 511459860 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3684445857 Jul 27 06:22:20 PM PDT 24 Jul 27 06:22:23 PM PDT 24 578506737 ps
T321 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.368095289 Jul 27 06:22:24 PM PDT 24 Jul 27 06:22:25 PM PDT 24 393614641 ps
T322 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.127454184 Jul 27 06:22:17 PM PDT 24 Jul 27 06:22:17 PM PDT 24 438858398 ps
T77 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1655679073 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:26 PM PDT 24 350668702 ps
T323 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1999293722 Jul 27 06:22:16 PM PDT 24 Jul 27 06:22:17 PM PDT 24 462749441 ps
T324 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3405893067 Jul 27 06:22:46 PM PDT 24 Jul 27 06:22:47 PM PDT 24 466311454 ps
T200 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2655971032 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:47 PM PDT 24 7837895902 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1198397499 Jul 27 06:21:49 PM PDT 24 Jul 27 06:21:50 PM PDT 24 422345993 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.19913822 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:08 PM PDT 24 494812374 ps
T327 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1884295544 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:49 PM PDT 24 459652882 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1376251626 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:07 PM PDT 24 340841973 ps
T329 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.693053724 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:37 PM PDT 24 2061736114 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3105730990 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:28 PM PDT 24 1128090686 ps
T331 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3884328084 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:34 PM PDT 24 435737106 ps
T332 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2324862545 Jul 27 06:21:47 PM PDT 24 Jul 27 06:21:47 PM PDT 24 360921525 ps
T333 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.975623733 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:39 PM PDT 24 2325536214 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3458976744 Jul 27 06:22:49 PM PDT 24 Jul 27 06:22:51 PM PDT 24 435832525 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1196219747 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:19 PM PDT 24 8770534739 ps
T335 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1158565967 Jul 27 06:22:54 PM PDT 24 Jul 27 06:22:55 PM PDT 24 625783653 ps
T197 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2120227256 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:36 PM PDT 24 4289778876 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3679977310 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:49 PM PDT 24 624389440 ps
T336 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2219509635 Jul 27 06:22:53 PM PDT 24 Jul 27 06:22:54 PM PDT 24 480812099 ps
T337 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.191757615 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:28 PM PDT 24 520635341 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1385446739 Jul 27 06:21:49 PM PDT 24 Jul 27 06:21:53 PM PDT 24 12838685548 ps
T338 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3335755927 Jul 27 06:21:38 PM PDT 24 Jul 27 06:21:40 PM PDT 24 422311874 ps
T339 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2067880801 Jul 27 06:22:54 PM PDT 24 Jul 27 06:22:54 PM PDT 24 556180666 ps
T201 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1691810100 Jul 27 06:22:17 PM PDT 24 Jul 27 06:22:21 PM PDT 24 8666530548 ps
T340 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.710402184 Jul 27 06:22:16 PM PDT 24 Jul 27 06:22:18 PM PDT 24 570221320 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2597587631 Jul 27 06:22:09 PM PDT 24 Jul 27 06:22:10 PM PDT 24 404618769 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4113703941 Jul 27 06:22:49 PM PDT 24 Jul 27 06:22:49 PM PDT 24 549799621 ps
T198 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3956341126 Jul 27 06:22:18 PM PDT 24 Jul 27 06:22:23 PM PDT 24 8181449316 ps
T343 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2297160431 Jul 27 06:22:49 PM PDT 24 Jul 27 06:22:51 PM PDT 24 1362277071 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.416048381 Jul 27 06:22:15 PM PDT 24 Jul 27 06:22:19 PM PDT 24 1108957692 ps
T345 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1507596821 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:36 PM PDT 24 455839958 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.931867418 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:52 PM PDT 24 396256179 ps
T347 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.398881426 Jul 27 06:22:35 PM PDT 24 Jul 27 06:22:36 PM PDT 24 491697772 ps
T348 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2175140530 Jul 27 06:22:53 PM PDT 24 Jul 27 06:22:55 PM PDT 24 497738671 ps
T349 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4199095160 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:27 PM PDT 24 397155548 ps
T350 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1339220547 Jul 27 06:22:17 PM PDT 24 Jul 27 06:22:18 PM PDT 24 469991457 ps
T351 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3510017066 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:29 PM PDT 24 476299477 ps
T352 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2130672322 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:35 PM PDT 24 465959733 ps
T353 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3912834764 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:49 PM PDT 24 490026185 ps
T354 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3972520089 Jul 27 06:21:43 PM PDT 24 Jul 27 06:21:54 PM PDT 24 7909041911 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1986041889 Jul 27 06:21:59 PM PDT 24 Jul 27 06:21:59 PM PDT 24 520143389 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1243739256 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:27 PM PDT 24 579518441 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2925533172 Jul 27 06:21:59 PM PDT 24 Jul 27 06:22:01 PM PDT 24 1178844582 ps
T357 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.276337514 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:26 PM PDT 24 426939278 ps
T199 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4241157511 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:40 PM PDT 24 8566042090 ps
T358 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3346939774 Jul 27 06:22:51 PM PDT 24 Jul 27 06:22:52 PM PDT 24 393013648 ps
T359 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2541456944 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:35 PM PDT 24 356996468 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3821864816 Jul 27 06:22:04 PM PDT 24 Jul 27 06:22:09 PM PDT 24 4476295515 ps
T361 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1946623679 Jul 27 06:22:18 PM PDT 24 Jul 27 06:22:19 PM PDT 24 781149566 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3158004437 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:49 PM PDT 24 650887861 ps
T363 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2473165992 Jul 27 06:21:56 PM PDT 24 Jul 27 06:21:57 PM PDT 24 401840599 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.964423076 Jul 27 06:21:46 PM PDT 24 Jul 27 06:21:48 PM PDT 24 646216401 ps
T364 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2419511873 Jul 27 06:22:53 PM PDT 24 Jul 27 06:22:54 PM PDT 24 436263880 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.592865584 Jul 27 06:21:59 PM PDT 24 Jul 27 06:22:00 PM PDT 24 490703443 ps
T365 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1944468737 Jul 27 06:22:32 PM PDT 24 Jul 27 06:22:32 PM PDT 24 420481074 ps
T366 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2994424737 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:26 PM PDT 24 488761029 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2019510767 Jul 27 06:22:24 PM PDT 24 Jul 27 06:22:28 PM PDT 24 2712878494 ps
T368 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1153987863 Jul 27 06:22:14 PM PDT 24 Jul 27 06:22:16 PM PDT 24 2068177367 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2596394301 Jul 27 06:22:39 PM PDT 24 Jul 27 06:22:41 PM PDT 24 375076667 ps
T370 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.84803034 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:37 PM PDT 24 429980664 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2543791200 Jul 27 06:21:43 PM PDT 24 Jul 27 06:21:44 PM PDT 24 506488890 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2755411982 Jul 27 06:22:17 PM PDT 24 Jul 27 06:22:20 PM PDT 24 1708835499 ps
T373 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4290855308 Jul 27 06:22:50 PM PDT 24 Jul 27 06:22:51 PM PDT 24 305408023 ps
T374 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3669369908 Jul 27 06:22:46 PM PDT 24 Jul 27 06:22:47 PM PDT 24 457555478 ps
T375 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1547962945 Jul 27 06:22:51 PM PDT 24 Jul 27 06:22:53 PM PDT 24 507648437 ps
T376 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.622830863 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:50 PM PDT 24 461440625 ps
T377 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3525337857 Jul 27 06:22:46 PM PDT 24 Jul 27 06:22:46 PM PDT 24 481976317 ps
T378 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3085921578 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:47 PM PDT 24 591643621 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2566659728 Jul 27 06:21:57 PM PDT 24 Jul 27 06:22:00 PM PDT 24 1657762000 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2290708970 Jul 27 06:22:26 PM PDT 24 Jul 27 06:22:26 PM PDT 24 419285921 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.854178769 Jul 27 06:21:58 PM PDT 24 Jul 27 06:21:59 PM PDT 24 1492933525 ps
T382 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.104196827 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:31 PM PDT 24 8319491081 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3127241851 Jul 27 06:22:32 PM PDT 24 Jul 27 06:22:35 PM PDT 24 4550434790 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1356743556 Jul 27 06:21:47 PM PDT 24 Jul 27 06:21:48 PM PDT 24 423608161 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3362853238 Jul 27 06:22:19 PM PDT 24 Jul 27 06:22:20 PM PDT 24 484501734 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4003274745 Jul 27 06:22:08 PM PDT 24 Jul 27 06:22:10 PM PDT 24 1515005866 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2627461220 Jul 27 06:21:56 PM PDT 24 Jul 27 06:22:02 PM PDT 24 1699884384 ps
T388 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.649417474 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:30 PM PDT 24 437066018 ps
T389 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2361409250 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:49 PM PDT 24 518689692 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3682724276 Jul 27 06:21:58 PM PDT 24 Jul 27 06:22:00 PM PDT 24 4960446379 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.706322247 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:50 PM PDT 24 2427584615 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2298909459 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:52 PM PDT 24 333383804 ps
T393 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.41592603 Jul 27 06:22:52 PM PDT 24 Jul 27 06:22:53 PM PDT 24 512663455 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.114894883 Jul 27 06:22:07 PM PDT 24 Jul 27 06:22:15 PM PDT 24 8337670658 ps
T395 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1845905830 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:54 PM PDT 24 4339426068 ps
T396 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2975061861 Jul 27 06:22:50 PM PDT 24 Jul 27 06:22:52 PM PDT 24 442494022 ps
T397 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1936536098 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:49 PM PDT 24 482992104 ps
T398 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2699042001 Jul 27 06:22:53 PM PDT 24 Jul 27 06:22:54 PM PDT 24 377062967 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2473861260 Jul 27 06:22:10 PM PDT 24 Jul 27 06:22:11 PM PDT 24 342094588 ps
T399 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2399648484 Jul 27 06:22:34 PM PDT 24 Jul 27 06:22:36 PM PDT 24 522105788 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3960221988 Jul 27 06:22:29 PM PDT 24 Jul 27 06:22:31 PM PDT 24 932904302 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3118736046 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:51 PM PDT 24 667422401 ps
T402 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2097504406 Jul 27 06:22:10 PM PDT 24 Jul 27 06:22:11 PM PDT 24 472667634 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2098536359 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:51 PM PDT 24 298800520 ps
T404 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2359579290 Jul 27 06:22:48 PM PDT 24 Jul 27 06:22:49 PM PDT 24 365123412 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2563660755 Jul 27 06:21:58 PM PDT 24 Jul 27 06:22:00 PM PDT 24 1159029933 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2777154941 Jul 27 06:21:48 PM PDT 24 Jul 27 06:21:49 PM PDT 24 441800118 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1130874560 Jul 27 06:21:58 PM PDT 24 Jul 27 06:21:59 PM PDT 24 308343384 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4102862568 Jul 27 06:22:33 PM PDT 24 Jul 27 06:22:35 PM PDT 24 422325031 ps
T409 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1535801417 Jul 27 06:22:40 PM PDT 24 Jul 27 06:22:41 PM PDT 24 524971596 ps
T410 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.632247298 Jul 27 06:22:16 PM PDT 24 Jul 27 06:22:17 PM PDT 24 473794099 ps
T411 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4119684305 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:48 PM PDT 24 426796622 ps
T412 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1258935470 Jul 27 06:21:49 PM PDT 24 Jul 27 06:22:03 PM PDT 24 8239208021 ps
T413 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1963783504 Jul 27 06:22:49 PM PDT 24 Jul 27 06:22:50 PM PDT 24 322375505 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2904774613 Jul 27 06:21:50 PM PDT 24 Jul 27 06:21:52 PM PDT 24 2551451117 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2914919009 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:28 PM PDT 24 371827174 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1500239519 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:08 PM PDT 24 519734240 ps
T417 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3598618626 Jul 27 06:22:51 PM PDT 24 Jul 27 06:22:52 PM PDT 24 483944694 ps
T418 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4018732450 Jul 27 06:22:25 PM PDT 24 Jul 27 06:22:28 PM PDT 24 1188678636 ps
T419 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3215094949 Jul 27 06:22:32 PM PDT 24 Jul 27 06:22:33 PM PDT 24 1634366305 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3313369162 Jul 27 06:21:57 PM PDT 24 Jul 27 06:21:58 PM PDT 24 456858580 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1826545541 Jul 27 06:21:49 PM PDT 24 Jul 27 06:21:52 PM PDT 24 7727986556 ps
T421 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3325921256 Jul 27 06:22:27 PM PDT 24 Jul 27 06:22:28 PM PDT 24 506380514 ps
T422 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3201587157 Jul 27 06:22:47 PM PDT 24 Jul 27 06:22:49 PM PDT 24 410441540 ps
T423 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1604013682 Jul 27 06:22:06 PM PDT 24 Jul 27 06:22:07 PM PDT 24 421535280 ps

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.593040598
Short name T1
Test name
Test status
Simulation time 326880544406 ps
CPU time 485.47 seconds
Started Jul 27 06:20:37 PM PDT 24
Finished Jul 27 06:28:42 PM PDT 24
Peak memory 202964 kb
Host smart-f472c315-2009-448f-9327-acedea23f113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593040598 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.593040598
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.713111663
Short name T40
Test name
Test status
Simulation time 26558468720 ps
CPU time 141.92 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:23:19 PM PDT 24
Peak memory 206736 kb
Host smart-bc4e0cd2-e135-4153-bb6b-d37ddb9efa09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713111663 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.713111663
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3343739579
Short name T35
Test name
Test status
Simulation time 4289807164 ps
CPU time 7.58 seconds
Started Jul 27 06:22:14 PM PDT 24
Finished Jul 27 06:22:22 PM PDT 24
Peak memory 198164 kb
Host smart-a1ef4090-6e62-4f44-b001-e4d804d7482c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343739579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3343739579
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.435996324
Short name T7
Test name
Test status
Simulation time 157649587418 ps
CPU time 223.85 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:25:13 PM PDT 24
Peak memory 192460 kb
Host smart-ba617217-3811-4cf2-9700-14c1f100463d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435996324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.435996324
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3153503410
Short name T98
Test name
Test status
Simulation time 125798151215 ps
CPU time 213.58 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:24:29 PM PDT 24
Peak memory 206636 kb
Host smart-5004639c-15eb-421c-833d-83145dbb370e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153503410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3153503410
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2874991527
Short name T95
Test name
Test status
Simulation time 402483532444 ps
CPU time 831.21 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:34:36 PM PDT 24
Peak memory 214868 kb
Host smart-b1a2d06e-3662-4e57-83ce-4bc74530e1a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874991527 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2874991527
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.821626611
Short name T97
Test name
Test status
Simulation time 946587707698 ps
CPU time 703.32 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:32:39 PM PDT 24
Peak memory 205776 kb
Host smart-6b3c7c88-ba6e-4117-b1c0-b16c662e662c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821626611 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.821626611
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1845591248
Short name T122
Test name
Test status
Simulation time 107308046624 ps
CPU time 374.64 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:27:11 PM PDT 24
Peak memory 202324 kb
Host smart-b645f74b-63bb-4c18-a518-327367a5d87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845591248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1845591248
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.792979546
Short name T104
Test name
Test status
Simulation time 35375784970 ps
CPU time 268.97 seconds
Started Jul 27 06:21:23 PM PDT 24
Finished Jul 27 06:25:52 PM PDT 24
Peak memory 198552 kb
Host smart-63e1001e-52f1-4341-938d-dba45695dfd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792979546 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.792979546
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3591994179
Short name T120
Test name
Test status
Simulation time 428888765020 ps
CPU time 153.6 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:23:10 PM PDT 24
Peak memory 192668 kb
Host smart-01dc158f-6fe4-437d-8056-6580f641b303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591994179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3591994179
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2894781058
Short name T31
Test name
Test status
Simulation time 520298271083 ps
CPU time 849.88 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:35:39 PM PDT 24
Peak memory 214844 kb
Host smart-0f1d42d3-e9ed-4b2f-98d7-4694369c62cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894781058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2894781058
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.411100810
Short name T16
Test name
Test status
Simulation time 7513225144 ps
CPU time 5.98 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:32 PM PDT 24
Peak memory 215892 kb
Host smart-7460e2c3-fd90-43d2-a318-2040ac110c63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411100810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.411100810
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3220503206
Short name T109
Test name
Test status
Simulation time 29585542492 ps
CPU time 306.25 seconds
Started Jul 27 06:21:06 PM PDT 24
Finished Jul 27 06:26:12 PM PDT 24
Peak memory 214156 kb
Host smart-d5500ebb-7c3f-4dc2-b80d-7ed9d32317e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220503206 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3220503206
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1269392740
Short name T58
Test name
Test status
Simulation time 366024228 ps
CPU time 0.85 seconds
Started Jul 27 06:22:35 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 193712 kb
Host smart-35dfa215-4832-405f-8626-4261fddfb932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269392740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1269392740
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1003223997
Short name T3
Test name
Test status
Simulation time 64709495696 ps
CPU time 292.61 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:25:41 PM PDT 24
Peak memory 214416 kb
Host smart-9f455e64-2be3-45b8-8635-f07eedad7fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003223997 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1003223997
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1434246485
Short name T108
Test name
Test status
Simulation time 301874821380 ps
CPU time 193.66 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:24:01 PM PDT 24
Peak memory 214048 kb
Host smart-c1397da9-80b2-40d8-b8ff-eff565eb5687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434246485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1434246485
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3438692966
Short name T101
Test name
Test status
Simulation time 171696370593 ps
CPU time 62.49 seconds
Started Jul 27 06:20:38 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 192532 kb
Host smart-75ec6948-a74e-4384-9050-853d500db966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438692966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3438692966
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3152106202
Short name T119
Test name
Test status
Simulation time 91334440406 ps
CPU time 37.73 seconds
Started Jul 27 06:21:11 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 198240 kb
Host smart-1f7ea8e4-caa6-4087-b12e-620c81877480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152106202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3152106202
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3469245049
Short name T26
Test name
Test status
Simulation time 267403392255 ps
CPU time 41.5 seconds
Started Jul 27 06:21:09 PM PDT 24
Finished Jul 27 06:21:51 PM PDT 24
Peak memory 198256 kb
Host smart-3f1be55d-3576-44a8-beb1-76d9619c855d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469245049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3469245049
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2774250038
Short name T71
Test name
Test status
Simulation time 97562362754 ps
CPU time 213.03 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:24:18 PM PDT 24
Peak memory 200196 kb
Host smart-646dddd6-0445-4d3f-993b-15dc6289da3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774250038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2774250038
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1929060711
Short name T14
Test name
Test status
Simulation time 24745331709 ps
CPU time 197.61 seconds
Started Jul 27 06:21:41 PM PDT 24
Finished Jul 27 06:24:59 PM PDT 24
Peak memory 198532 kb
Host smart-6473b301-2994-4c6b-98d8-ec235b9f7d8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929060711 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1929060711
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2738943560
Short name T139
Test name
Test status
Simulation time 140616406563 ps
CPU time 379.85 seconds
Started Jul 27 06:20:31 PM PDT 24
Finished Jul 27 06:26:51 PM PDT 24
Peak memory 202532 kb
Host smart-09c4c7a8-1389-40a0-8fed-87bbeb0ee2e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738943560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2738943560
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1063761449
Short name T72
Test name
Test status
Simulation time 151940772497 ps
CPU time 218.59 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:24:39 PM PDT 24
Peak memory 191900 kb
Host smart-36173875-9cbc-4267-a1e6-4314d756d2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063761449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1063761449
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2177022358
Short name T39
Test name
Test status
Simulation time 107412331195 ps
CPU time 235.29 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:24:51 PM PDT 24
Peak memory 214832 kb
Host smart-4c441abd-eac2-4f4b-a1ee-8b14b2dae1de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177022358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2177022358
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3431575001
Short name T69
Test name
Test status
Simulation time 341860740578 ps
CPU time 515.32 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:30:05 PM PDT 24
Peak memory 192988 kb
Host smart-c9a1a0ec-2264-42ba-b86d-f54bb381383c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431575001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3431575001
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2926642304
Short name T117
Test name
Test status
Simulation time 290672675672 ps
CPU time 112.9 seconds
Started Jul 27 06:21:25 PM PDT 24
Finished Jul 27 06:23:18 PM PDT 24
Peak memory 192916 kb
Host smart-6fe93b67-77ca-4340-aad2-219b4f69e465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926642304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2926642304
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1441394607
Short name T105
Test name
Test status
Simulation time 296743321490 ps
CPU time 326.64 seconds
Started Jul 27 06:20:37 PM PDT 24
Finished Jul 27 06:26:04 PM PDT 24
Peak memory 192468 kb
Host smart-2f081020-8eab-455e-9747-73e368bc8425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441394607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1441394607
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3487832882
Short name T110
Test name
Test status
Simulation time 59600934990 ps
CPU time 10.16 seconds
Started Jul 27 06:20:51 PM PDT 24
Finished Jul 27 06:21:02 PM PDT 24
Peak memory 193024 kb
Host smart-c32ca5ff-e052-4d6b-8399-c5daff6577b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487832882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3487832882
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1612604117
Short name T131
Test name
Test status
Simulation time 4172813577 ps
CPU time 6.67 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:21:04 PM PDT 24
Peak memory 198200 kb
Host smart-a33dfcf1-ffde-4186-8907-84d85bbb6dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612604117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1612604117
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2558225391
Short name T114
Test name
Test status
Simulation time 98077046059 ps
CPU time 94.66 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:22:03 PM PDT 24
Peak memory 192916 kb
Host smart-b3abd546-be0e-48fd-8b2e-c1cf768697bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558225391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2558225391
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3260620347
Short name T126
Test name
Test status
Simulation time 181369533050 ps
CPU time 1060.17 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:38:27 PM PDT 24
Peak memory 214884 kb
Host smart-ee57ac5e-0ca3-40f5-8270-6ddf90ba0565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260620347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3260620347
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2891422523
Short name T99
Test name
Test status
Simulation time 267849129370 ps
CPU time 185.87 seconds
Started Jul 27 06:21:44 PM PDT 24
Finished Jul 27 06:24:50 PM PDT 24
Peak memory 199968 kb
Host smart-9d5b7baa-992e-4cdf-98f0-70f616c38054
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891422523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2891422523
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3530145598
Short name T94
Test name
Test status
Simulation time 27724884681 ps
CPU time 287.06 seconds
Started Jul 27 06:21:12 PM PDT 24
Finished Jul 27 06:25:59 PM PDT 24
Peak memory 206664 kb
Host smart-83fba7c1-8bbf-48bf-90b4-ab13016f0e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530145598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3530145598
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1363258502
Short name T132
Test name
Test status
Simulation time 204388639397 ps
CPU time 79.75 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:22:06 PM PDT 24
Peak memory 192912 kb
Host smart-a4a57df7-20d2-431a-857c-b772eb4a7f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363258502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1363258502
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.776707868
Short name T129
Test name
Test status
Simulation time 87366247240 ps
CPU time 236.44 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:25:27 PM PDT 24
Peak memory 209112 kb
Host smart-9c9b504c-8d39-4efb-9e06-7212cb0b6fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776707868 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.776707868
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2751058382
Short name T157
Test name
Test status
Simulation time 65493478012 ps
CPU time 513.42 seconds
Started Jul 27 06:20:25 PM PDT 24
Finished Jul 27 06:28:59 PM PDT 24
Peak memory 202176 kb
Host smart-70c65d9f-e400-4bb0-9aeb-56cbe3cac8fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751058382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2751058382
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.591153605
Short name T41
Test name
Test status
Simulation time 253511987555 ps
CPU time 480.95 seconds
Started Jul 27 06:20:51 PM PDT 24
Finished Jul 27 06:28:52 PM PDT 24
Peak memory 211856 kb
Host smart-275859d5-239a-4cc2-95e0-93acf7f17f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591153605 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.591153605
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1858632795
Short name T102
Test name
Test status
Simulation time 152257022248 ps
CPU time 254.18 seconds
Started Jul 27 06:21:18 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 201084 kb
Host smart-a3b06d76-fa4f-456f-be41-bf9820d06c75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858632795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1858632795
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1121793181
Short name T50
Test name
Test status
Simulation time 84320686229 ps
CPU time 382.19 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:27:18 PM PDT 24
Peak memory 207552 kb
Host smart-91c6e891-750d-4e09-93e0-1c11bcc758f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121793181 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1121793181
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3043943376
Short name T32
Test name
Test status
Simulation time 91320481647 ps
CPU time 117.77 seconds
Started Jul 27 06:21:38 PM PDT 24
Finished Jul 27 06:23:36 PM PDT 24
Peak memory 191904 kb
Host smart-d1e38a70-88d2-4bf2-97ff-2ea99a487b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043943376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3043943376
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1874326206
Short name T42
Test name
Test status
Simulation time 52302624638 ps
CPU time 132.86 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:22:58 PM PDT 24
Peak memory 198464 kb
Host smart-7d3ba724-8228-42a2-9e5a-0b281cfc416e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874326206 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1874326206
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1393481045
Short name T106
Test name
Test status
Simulation time 247589537911 ps
CPU time 57.77 seconds
Started Jul 27 06:20:42 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 198292 kb
Host smart-d5ea9a53-8c57-4c81-b30d-32fac1f59441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393481045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1393481045
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1775518698
Short name T92
Test name
Test status
Simulation time 49645231602 ps
CPU time 434.05 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:27:59 PM PDT 24
Peak memory 208980 kb
Host smart-74cc4171-111c-4c7b-a2c6-d79c72a4821d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775518698 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1775518698
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1162359374
Short name T27
Test name
Test status
Simulation time 306678815582 ps
CPU time 42.81 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:21:31 PM PDT 24
Peak memory 192912 kb
Host smart-a26a481b-fae4-4eb4-b2fd-0c19f35c54df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162359374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1162359374
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2196594877
Short name T112
Test name
Test status
Simulation time 69340570389 ps
CPU time 522.36 seconds
Started Jul 27 06:21:01 PM PDT 24
Finished Jul 27 06:29:44 PM PDT 24
Peak memory 206624 kb
Host smart-ce156e19-795c-48cb-8364-b8367f829033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196594877 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2196594877
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2422362774
Short name T164
Test name
Test status
Simulation time 145997819141 ps
CPU time 195.76 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:24:44 PM PDT 24
Peak memory 192404 kb
Host smart-3a6f27bb-76c7-4b90-bce4-bfaa75744a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422362774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2422362774
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2420527930
Short name T138
Test name
Test status
Simulation time 166790313461 ps
CPU time 165.3 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:24:25 PM PDT 24
Peak memory 199668 kb
Host smart-ca998bfe-4de6-4090-952e-7d120f20d714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420527930 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2420527930
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.10724587
Short name T121
Test name
Test status
Simulation time 68209696584 ps
CPU time 720.08 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:32:35 PM PDT 24
Peak memory 206004 kb
Host smart-78cfbae3-b5d1-4f4a-aade-1751fc3da3c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724587 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.10724587
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1205903329
Short name T81
Test name
Test status
Simulation time 47730336531 ps
CPU time 468.31 seconds
Started Jul 27 06:21:31 PM PDT 24
Finished Jul 27 06:29:20 PM PDT 24
Peak memory 201608 kb
Host smart-95825ced-d187-4d55-baf6-dc29219607bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205903329 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1205903329
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1772852130
Short name T155
Test name
Test status
Simulation time 147198895579 ps
CPU time 380.68 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:26:49 PM PDT 24
Peak memory 206644 kb
Host smart-ab3e5cd4-7916-419c-8559-6a2216a939c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772852130 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1772852130
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2659540400
Short name T96
Test name
Test status
Simulation time 61569265196 ps
CPU time 457.57 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:28:06 PM PDT 24
Peak memory 206908 kb
Host smart-8804000c-e9f3-4ca4-b390-fc66029fbfe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659540400 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2659540400
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.873264065
Short name T111
Test name
Test status
Simulation time 327923327582 ps
CPU time 451.18 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:29:11 PM PDT 24
Peak memory 198232 kb
Host smart-a8778dfc-a40d-47d5-a02a-3de389feec28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873264065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.873264065
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2019528374
Short name T125
Test name
Test status
Simulation time 473791900266 ps
CPU time 200.1 seconds
Started Jul 27 06:20:44 PM PDT 24
Finished Jul 27 06:24:05 PM PDT 24
Peak memory 198188 kb
Host smart-493f52f9-5320-4125-9af9-1ee432018a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019528374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2019528374
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2166178233
Short name T128
Test name
Test status
Simulation time 117689731469 ps
CPU time 164.89 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:23:32 PM PDT 24
Peak memory 191912 kb
Host smart-93b92dec-c4c6-4f16-a43d-47dd6c26106f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166178233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2166178233
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1504350753
Short name T51
Test name
Test status
Simulation time 35175326968 ps
CPU time 249.02 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:24:54 PM PDT 24
Peak memory 206684 kb
Host smart-374d9213-0253-44a0-8510-2a7df2dbdad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504350753 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1504350753
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2695580074
Short name T134
Test name
Test status
Simulation time 72526496699 ps
CPU time 19.71 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:28 PM PDT 24
Peak memory 191880 kb
Host smart-bdf91a62-373a-4048-adf2-da797cb4fe31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695580074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2695580074
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1945071132
Short name T137
Test name
Test status
Simulation time 210707661851 ps
CPU time 85.98 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:22:34 PM PDT 24
Peak memory 192980 kb
Host smart-05fbc1c2-a091-4828-a3d2-7e66bbdc9c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945071132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1945071132
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1485895653
Short name T147
Test name
Test status
Simulation time 179705195304 ps
CPU time 71.58 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:22:52 PM PDT 24
Peak memory 192864 kb
Host smart-68e26b2d-332f-4e99-ac96-bc46881a59fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485895653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1485895653
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2616071620
Short name T143
Test name
Test status
Simulation time 191586900730 ps
CPU time 76.98 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:22:04 PM PDT 24
Peak memory 198280 kb
Host smart-d7fc3258-8e60-4642-8f1c-54c4357aa573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616071620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2616071620
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3442658585
Short name T145
Test name
Test status
Simulation time 144805256480 ps
CPU time 129.41 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:22:57 PM PDT 24
Peak memory 191864 kb
Host smart-4506a94e-ced8-41bc-83c8-c48c304b8753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442658585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3442658585
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1258070311
Short name T103
Test name
Test status
Simulation time 26641370604 ps
CPU time 9.38 seconds
Started Jul 27 06:21:01 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 192792 kb
Host smart-fcab64f4-7938-4895-b540-26e9885e9683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258070311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1258070311
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.867372589
Short name T13
Test name
Test status
Simulation time 45615372298 ps
CPU time 506.45 seconds
Started Jul 27 06:21:10 PM PDT 24
Finished Jul 27 06:29:36 PM PDT 24
Peak memory 209352 kb
Host smart-90406f22-4df8-4a55-bdbb-259f74f9a0b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867372589 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.867372589
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1984192086
Short name T124
Test name
Test status
Simulation time 353448143474 ps
CPU time 80.01 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:22:50 PM PDT 24
Peak memory 198212 kb
Host smart-9aaba246-3eb6-47a3-a380-e8be25ac80b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984192086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1984192086
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4007461432
Short name T93
Test name
Test status
Simulation time 170606901392 ps
CPU time 160.51 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:23:19 PM PDT 24
Peak memory 207996 kb
Host smart-22277c38-d29e-44f0-a8ab-cddc98f25198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007461432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4007461432
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1658929742
Short name T44
Test name
Test status
Simulation time 365333895585 ps
CPU time 111.12 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:22:20 PM PDT 24
Peak memory 191852 kb
Host smart-a9776509-3e26-49a9-816c-8bd5e74e50e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658929742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1658929742
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2515888127
Short name T115
Test name
Test status
Simulation time 415209666943 ps
CPU time 104.78 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 192876 kb
Host smart-50d43645-3505-42db-aa65-bc470e8f9d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515888127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2515888127
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1595864870
Short name T18
Test name
Test status
Simulation time 101596490720 ps
CPU time 9.63 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:21:05 PM PDT 24
Peak memory 191892 kb
Host smart-04d769f1-a8d2-4124-a2b6-4b760c355f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595864870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1595864870
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2825320638
Short name T73
Test name
Test status
Simulation time 21183951731 ps
CPU time 108.99 seconds
Started Jul 27 06:21:24 PM PDT 24
Finished Jul 27 06:23:13 PM PDT 24
Peak memory 206704 kb
Host smart-b93fb789-695a-4491-bd3a-6282c0c29468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825320638 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2825320638
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3495248356
Short name T186
Test name
Test status
Simulation time 515936235584 ps
CPU time 796.78 seconds
Started Jul 27 06:21:31 PM PDT 24
Finished Jul 27 06:34:48 PM PDT 24
Peak memory 191884 kb
Host smart-64a23743-0683-4260-96c2-d4bb68bb4fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495248356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3495248356
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1180915148
Short name T153
Test name
Test status
Simulation time 483513339 ps
CPU time 0.8 seconds
Started Jul 27 06:21:32 PM PDT 24
Finished Jul 27 06:21:33 PM PDT 24
Peak memory 196636 kb
Host smart-ac69aae3-1055-401f-8048-c0858371f8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180915148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1180915148
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3219334239
Short name T148
Test name
Test status
Simulation time 607193245 ps
CPU time 0.69 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:21:31 PM PDT 24
Peak memory 196576 kb
Host smart-e3cd5cf6-71aa-4a98-8c67-a65bbc2fc564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219334239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3219334239
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1658023878
Short name T144
Test name
Test status
Simulation time 453791973 ps
CPU time 1.29 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:20:49 PM PDT 24
Peak memory 196592 kb
Host smart-052b9f44-6ffb-49e4-b4b9-39c2f7c69f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658023878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1658023878
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3260305660
Short name T158
Test name
Test status
Simulation time 184949816230 ps
CPU time 19.07 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 191832 kb
Host smart-49f7cc35-bc16-4afd-b00f-201ef503464b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260305660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3260305660
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4090315466
Short name T152
Test name
Test status
Simulation time 47796071023 ps
CPU time 69.33 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:22:38 PM PDT 24
Peak memory 191884 kb
Host smart-d5d93f45-6cbd-4f9e-b5ac-a849a00f12ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090315466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4090315466
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4117709704
Short name T82
Test name
Test status
Simulation time 496773881 ps
CPU time 1.45 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:30 PM PDT 24
Peak memory 195680 kb
Host smart-f8ed7e7a-753f-4430-b06a-327bddebea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117709704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4117709704
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3230159550
Short name T160
Test name
Test status
Simulation time 311164400468 ps
CPU time 586.86 seconds
Started Jul 27 06:21:43 PM PDT 24
Finished Jul 27 06:31:30 PM PDT 24
Peak memory 206644 kb
Host smart-41d33c09-0bd0-4942-b149-5c3253cc674a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230159550 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3230159550
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.953746943
Short name T107
Test name
Test status
Simulation time 341424016 ps
CPU time 1.08 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:20:47 PM PDT 24
Peak memory 196696 kb
Host smart-ef85a396-c334-4b2d-8f6e-6ef62325f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953746943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.953746943
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.879664840
Short name T38
Test name
Test status
Simulation time 138732140033 ps
CPU time 268.89 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:25:16 PM PDT 24
Peak memory 209316 kb
Host smart-2a895534-41d9-4cb9-928f-edbbb1064f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879664840 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.879664840
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.284830414
Short name T4
Test name
Test status
Simulation time 384640648 ps
CPU time 0.9 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:20:47 PM PDT 24
Peak memory 196592 kb
Host smart-ba28ea69-889f-4929-825e-8f263b7681af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284830414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.284830414
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1326290018
Short name T150
Test name
Test status
Simulation time 384134122 ps
CPU time 1.16 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 196632 kb
Host smart-ac09b723-efea-4c9a-b7d7-de787730c03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326290018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1326290018
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3466663545
Short name T136
Test name
Test status
Simulation time 133345473041 ps
CPU time 50.75 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:21:51 PM PDT 24
Peak memory 192944 kb
Host smart-6dbd38bc-8b55-440d-9b25-c1719fc6b5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466663545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3466663545
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1283919019
Short name T127
Test name
Test status
Simulation time 475201845 ps
CPU time 1.22 seconds
Started Jul 27 06:21:41 PM PDT 24
Finished Jul 27 06:21:42 PM PDT 24
Peak memory 196720 kb
Host smart-d14a3cbd-a51f-4b8d-b9f1-e67d5f49c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283919019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1283919019
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.568019459
Short name T80
Test name
Test status
Simulation time 541876880 ps
CPU time 0.78 seconds
Started Jul 27 06:21:43 PM PDT 24
Finished Jul 27 06:21:44 PM PDT 24
Peak memory 196548 kb
Host smart-5bd5e5e0-5f5b-49bc-8c2d-d5e6b18de580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568019459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.568019459
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1185136442
Short name T2
Test name
Test status
Simulation time 91661567686 ps
CPU time 34.63 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:21:01 PM PDT 24
Peak memory 191836 kb
Host smart-aef6d85c-0807-4740-afb0-662196cbb678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185136442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1185136442
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.206184106
Short name T135
Test name
Test status
Simulation time 108060945337 ps
CPU time 38.03 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:21:26 PM PDT 24
Peak memory 198200 kb
Host smart-08ed35ed-5d4f-4bef-ae66-ba581e8d8231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206184106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.206184106
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2854051622
Short name T78
Test name
Test status
Simulation time 425816226 ps
CPU time 1.16 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:58 PM PDT 24
Peak memory 196660 kb
Host smart-3e7f27f1-48a5-4e43-a011-131b3c98e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854051622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2854051622
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1741542694
Short name T149
Test name
Test status
Simulation time 207632367447 ps
CPU time 68.59 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 192012 kb
Host smart-3aeaa609-5c4b-4525-a82f-c53c86f16130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741542694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1741542694
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2289114619
Short name T28
Test name
Test status
Simulation time 474135410 ps
CPU time 1.2 seconds
Started Jul 27 06:21:09 PM PDT 24
Finished Jul 27 06:21:11 PM PDT 24
Peak memory 196588 kb
Host smart-21c7c6a2-80f8-4731-89dd-428ee5a9c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289114619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2289114619
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3852685523
Short name T146
Test name
Test status
Simulation time 76914655155 ps
CPU time 15.44 seconds
Started Jul 27 06:21:07 PM PDT 24
Finished Jul 27 06:21:23 PM PDT 24
Peak memory 192052 kb
Host smart-4686d0a0-affe-4f1f-8ad1-9b8c34225145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852685523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3852685523
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1541440705
Short name T113
Test name
Test status
Simulation time 581221141558 ps
CPU time 451.4 seconds
Started Jul 27 06:21:19 PM PDT 24
Finished Jul 27 06:28:51 PM PDT 24
Peak memory 191832 kb
Host smart-a91d4a27-ea11-4c6b-b378-c6e863e4f0c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541440705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1541440705
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4046043432
Short name T169
Test name
Test status
Simulation time 104510202658 ps
CPU time 159.1 seconds
Started Jul 27 06:21:23 PM PDT 24
Finished Jul 27 06:24:03 PM PDT 24
Peak memory 192984 kb
Host smart-57fb872b-6895-4edf-a6be-0bf697137186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046043432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4046043432
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.916278997
Short name T166
Test name
Test status
Simulation time 51647727976 ps
CPU time 4.93 seconds
Started Jul 27 06:21:38 PM PDT 24
Finished Jul 27 06:21:43 PM PDT 24
Peak memory 198236 kb
Host smart-5c60ae23-6768-4079-801f-35045acd5a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916278997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.916278997
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2440428850
Short name T156
Test name
Test status
Simulation time 76127780813 ps
CPU time 122.04 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:23:41 PM PDT 24
Peak memory 191840 kb
Host smart-bd739ab9-915b-456b-8d4e-43917ac279ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440428850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2440428850
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1218023681
Short name T133
Test name
Test status
Simulation time 371011249 ps
CPU time 0.7 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 196540 kb
Host smart-1ae2dba8-ff55-40a7-aa22-7baa2bed5857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218023681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1218023681
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2725413733
Short name T47
Test name
Test status
Simulation time 478624121 ps
CPU time 1 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:20:46 PM PDT 24
Peak memory 196500 kb
Host smart-95f20cd6-86c4-40bf-93a4-34090fa25a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725413733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2725413733
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.775582289
Short name T168
Test name
Test status
Simulation time 69748080557 ps
CPU time 67.7 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:21:54 PM PDT 24
Peak memory 198232 kb
Host smart-c22e27b8-8271-4249-8f8b-652eabe84686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775582289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.775582289
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.35779446
Short name T83
Test name
Test status
Simulation time 590402086 ps
CPU time 0.95 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 196648 kb
Host smart-23b72fc0-26a2-463c-87dc-03b550386c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35779446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.35779446
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.703747928
Short name T123
Test name
Test status
Simulation time 565399199 ps
CPU time 0.75 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 196676 kb
Host smart-378899a5-f7d3-4a52-bbf2-2963885e51ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703747928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.703747928
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3069780101
Short name T130
Test name
Test status
Simulation time 393689771 ps
CPU time 0.9 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:20:29 PM PDT 24
Peak memory 196588 kb
Host smart-37c748c9-120a-4d0c-aabd-a1265bb24980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069780101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3069780101
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.764782439
Short name T154
Test name
Test status
Simulation time 51532355269 ps
CPU time 295.93 seconds
Started Jul 27 06:20:37 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 198812 kb
Host smart-1f4c2f3e-6c07-4fa4-8eb2-0d930d6f1eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764782439 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.764782439
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2120227256
Short name T197
Test name
Test status
Simulation time 4289778876 ps
CPU time 2.13 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 198432 kb
Host smart-0aa8edcf-2ad3-43d1-ac33-ea0f5a913fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120227256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2120227256
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3376734054
Short name T49
Test name
Test status
Simulation time 433125538 ps
CPU time 0.7 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 196572 kb
Host smart-b7910f61-6f64-40bf-adcb-3231ce515343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376734054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3376734054
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3875894804
Short name T171
Test name
Test status
Simulation time 203232486849 ps
CPU time 66.59 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:22:05 PM PDT 24
Peak memory 198276 kb
Host smart-a4e6a202-75a3-42df-8139-bf689f576bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875894804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3875894804
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.981829101
Short name T159
Test name
Test status
Simulation time 99293301845 ps
CPU time 530.11 seconds
Started Jul 27 06:20:54 PM PDT 24
Finished Jul 27 06:29:44 PM PDT 24
Peak memory 214796 kb
Host smart-8ab550a7-307b-45b2-a42c-3f9172fe9bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981829101 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.981829101
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1147293935
Short name T165
Test name
Test status
Simulation time 52734473644 ps
CPU time 18.28 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:21:18 PM PDT 24
Peak memory 191820 kb
Host smart-cf682282-f76e-4a50-a8b9-4c467e1ac4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147293935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1147293935
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3526667183
Short name T116
Test name
Test status
Simulation time 494912385 ps
CPU time 0.74 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:21:01 PM PDT 24
Peak memory 196620 kb
Host smart-c09ee4da-7afc-4155-93c2-baf189198f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526667183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3526667183
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3317766385
Short name T142
Test name
Test status
Simulation time 399558923 ps
CPU time 1.09 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:49 PM PDT 24
Peak memory 196500 kb
Host smart-34f4540b-5a41-47c7-b95b-8665fd1b8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317766385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3317766385
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2916218566
Short name T162
Test name
Test status
Simulation time 256626735856 ps
CPU time 482.69 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:28:57 PM PDT 24
Peak memory 203708 kb
Host smart-5ecc7ab9-e659-4267-bcee-3f8a6f28dbe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916218566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2916218566
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3655409772
Short name T21
Test name
Test status
Simulation time 538036524 ps
CPU time 1.39 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:20:56 PM PDT 24
Peak memory 196536 kb
Host smart-92c427ac-e176-4381-9f66-be5de8605948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655409772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3655409772
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1839502638
Short name T179
Test name
Test status
Simulation time 156944092820 ps
CPU time 111.67 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:22:46 PM PDT 24
Peak memory 193000 kb
Host smart-9bfdc625-b122-409f-970d-f94b3e3c4a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839502638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1839502638
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1450411440
Short name T184
Test name
Test status
Simulation time 538594584 ps
CPU time 1.35 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:29 PM PDT 24
Peak memory 196640 kb
Host smart-923b8e4a-97ce-420c-b8bb-119c835fd836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450411440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1450411440
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2925172163
Short name T176
Test name
Test status
Simulation time 569820838 ps
CPU time 1.43 seconds
Started Jul 27 06:21:32 PM PDT 24
Finished Jul 27 06:21:34 PM PDT 24
Peak memory 196540 kb
Host smart-c1d25e7b-b433-480a-b3e2-928dc0891be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925172163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2925172163
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.740863720
Short name T151
Test name
Test status
Simulation time 499487242 ps
CPU time 1.35 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:21:32 PM PDT 24
Peak memory 196588 kb
Host smart-2ed02c45-8801-4c36-a5bd-8fbf942b25c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740863720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.740863720
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.995538214
Short name T140
Test name
Test status
Simulation time 356606582753 ps
CPU time 96.28 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:23:15 PM PDT 24
Peak memory 198160 kb
Host smart-5128459f-6ddf-4e7e-8125-3438a9e8b60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995538214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.995538214
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4243419907
Short name T141
Test name
Test status
Simulation time 374982228 ps
CPU time 0.95 seconds
Started Jul 27 06:20:44 PM PDT 24
Finished Jul 27 06:20:46 PM PDT 24
Peak memory 196144 kb
Host smart-ddf2ddd6-920a-465c-a0cc-f885f6ef3356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243419907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4243419907
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3851105594
Short name T174
Test name
Test status
Simulation time 490162852 ps
CPU time 0.94 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 196636 kb
Host smart-62c57ee1-d380-4193-8716-785072583464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851105594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3851105594
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2279210269
Short name T79
Test name
Test status
Simulation time 403017862 ps
CPU time 0.97 seconds
Started Jul 27 06:20:44 PM PDT 24
Finished Jul 27 06:20:45 PM PDT 24
Peak memory 196584 kb
Host smart-d7221bdf-0313-4c72-95a4-a51587addc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279210269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2279210269
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.39692864
Short name T173
Test name
Test status
Simulation time 605052637 ps
CPU time 1.39 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:58 PM PDT 24
Peak memory 196540 kb
Host smart-d2f65676-be30-4fe5-83f2-8a797faec89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39692864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.39692864
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.959895311
Short name T118
Test name
Test status
Simulation time 566143008 ps
CPU time 1.01 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:21:00 PM PDT 24
Peak memory 196532 kb
Host smart-5967f256-956f-4299-b0d8-8658e550c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959895311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.959895311
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.4135592399
Short name T182
Test name
Test status
Simulation time 407253381 ps
CPU time 0.87 seconds
Started Jul 27 06:21:11 PM PDT 24
Finished Jul 27 06:21:12 PM PDT 24
Peak memory 196524 kb
Host smart-c0435b2b-3cb5-45d0-a9c5-8b929283f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135592399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.4135592399
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.514056403
Short name T178
Test name
Test status
Simulation time 3729426609 ps
CPU time 35.39 seconds
Started Jul 27 06:21:11 PM PDT 24
Finished Jul 27 06:21:46 PM PDT 24
Peak memory 198464 kb
Host smart-aa3347a9-1549-4315-8a3f-2d49de076003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514056403 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.514056403
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2944518242
Short name T180
Test name
Test status
Simulation time 551889857 ps
CPU time 1.48 seconds
Started Jul 27 06:21:25 PM PDT 24
Finished Jul 27 06:21:26 PM PDT 24
Peak memory 196544 kb
Host smart-e27eef5d-15e9-40a6-bcf3-b96cf71f95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944518242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2944518242
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1492342456
Short name T48
Test name
Test status
Simulation time 13370636923 ps
CPU time 76.6 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:22:46 PM PDT 24
Peak memory 198544 kb
Host smart-d7df0353-baa0-4e17-927f-027c6d0968b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492342456 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1492342456
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2236514259
Short name T187
Test name
Test status
Simulation time 610996161 ps
CPU time 0.78 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 196560 kb
Host smart-e2a24790-8e17-4d1a-9a76-87ef17da1728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236514259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2236514259
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1374951105
Short name T192
Test name
Test status
Simulation time 499588616 ps
CPU time 1.38 seconds
Started Jul 27 06:21:44 PM PDT 24
Finished Jul 27 06:21:45 PM PDT 24
Peak memory 196588 kb
Host smart-80fca7b1-a1a5-4f5a-bf9a-61eb7e849955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374951105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1374951105
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3474026700
Short name T163
Test name
Test status
Simulation time 395515353 ps
CPU time 0.73 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:20:39 PM PDT 24
Peak memory 196516 kb
Host smart-63139b86-c847-4222-bdc6-5e7be3dfd97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474026700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3474026700
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1028727673
Short name T161
Test name
Test status
Simulation time 542902785 ps
CPU time 1.51 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:59 PM PDT 24
Peak memory 196632 kb
Host smart-e15aaf13-c0f6-4d5c-a437-6f98c0a03403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028727673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1028727673
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3377787018
Short name T188
Test name
Test status
Simulation time 415422458 ps
CPU time 1.1 seconds
Started Jul 27 06:20:54 PM PDT 24
Finished Jul 27 06:20:55 PM PDT 24
Peak memory 196492 kb
Host smart-be59c139-3f0e-47f2-bb55-a704c61df40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377787018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3377787018
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1321739530
Short name T175
Test name
Test status
Simulation time 556892590 ps
CPU time 0.77 seconds
Started Jul 27 06:20:54 PM PDT 24
Finished Jul 27 06:20:55 PM PDT 24
Peak memory 196572 kb
Host smart-5495dfac-91bf-4ab3-bec4-e5e2bcc4d03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321739530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1321739530
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2755198096
Short name T45
Test name
Test status
Simulation time 526486214 ps
CPU time 0.76 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:58 PM PDT 24
Peak memory 196548 kb
Host smart-1053ce4b-3a96-4641-92c3-9f58f55f5b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755198096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2755198096
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3460885879
Short name T85
Test name
Test status
Simulation time 515972368 ps
CPU time 1.3 seconds
Started Jul 27 06:21:19 PM PDT 24
Finished Jul 27 06:21:21 PM PDT 24
Peak memory 196544 kb
Host smart-fd1662c5-3e9e-4479-ba20-7e70b3730d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460885879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3460885879
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.873685260
Short name T190
Test name
Test status
Simulation time 529396918 ps
CPU time 0.71 seconds
Started Jul 27 06:21:19 PM PDT 24
Finished Jul 27 06:21:20 PM PDT 24
Peak memory 196572 kb
Host smart-9ba07aa2-a0c1-4af9-adcd-71b0352caaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873685260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.873685260
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1754110740
Short name T185
Test name
Test status
Simulation time 402941628 ps
CPU time 1.18 seconds
Started Jul 27 06:21:24 PM PDT 24
Finished Jul 27 06:21:26 PM PDT 24
Peak memory 196576 kb
Host smart-402692bf-9ec1-4bac-b5cd-4abdb26d8a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754110740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1754110740
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3874841885
Short name T167
Test name
Test status
Simulation time 74222830155 ps
CPU time 304.69 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:26:33 PM PDT 24
Peak memory 206724 kb
Host smart-441d2269-e061-4776-9664-e3b028a24db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874841885 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3874841885
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4138199429
Short name T189
Test name
Test status
Simulation time 233270411201 ps
CPU time 300.17 seconds
Started Jul 27 06:21:31 PM PDT 24
Finished Jul 27 06:26:31 PM PDT 24
Peak memory 198248 kb
Host smart-6372e9a2-7cbc-4b79-8524-10ac04fd26fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138199429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4138199429
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.564524188
Short name T193
Test name
Test status
Simulation time 512090014 ps
CPU time 0.74 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:21:41 PM PDT 24
Peak memory 196568 kb
Host smart-d372383c-77a2-4914-8a5b-f605678dbe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564524188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.564524188
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.760576480
Short name T75
Test name
Test status
Simulation time 362523673 ps
CPU time 0.86 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 196568 kb
Host smart-ba78eca1-3777-4574-a58f-268a28ef2113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760576480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.760576480
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.842921197
Short name T181
Test name
Test status
Simulation time 620968618 ps
CPU time 1.08 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:20:36 PM PDT 24
Peak memory 196496 kb
Host smart-55cc625b-a26d-480e-ae10-cbe49f4bf9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842921197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.842921197
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.767663998
Short name T172
Test name
Test status
Simulation time 528609395 ps
CPU time 1.32 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:20:38 PM PDT 24
Peak memory 196540 kb
Host smart-00a17523-936a-43bf-80be-a523d237648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767663998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.767663998
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3679977310
Short name T59
Test name
Test status
Simulation time 624389440 ps
CPU time 1.01 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 195196 kb
Host smart-bfb8bd69-a957-404c-8335-a0c0988c453a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679977310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3679977310
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1826545541
Short name T420
Test name
Test status
Simulation time 7727986556 ps
CPU time 2.78 seconds
Started Jul 27 06:21:49 PM PDT 24
Finished Jul 27 06:21:52 PM PDT 24
Peak memory 192704 kb
Host smart-fffbc78d-4e33-422b-a419-bb6e6e08d3ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826545541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1826545541
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1821974431
Short name T56
Test name
Test status
Simulation time 1292897857 ps
CPU time 1.01 seconds
Started Jul 27 06:21:41 PM PDT 24
Finished Jul 27 06:21:42 PM PDT 24
Peak memory 193444 kb
Host smart-e47fbdd0-a290-41ab-985c-75f0f86a8a92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821974431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1821974431
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.931867418
Short name T346
Test name
Test status
Simulation time 396256179 ps
CPU time 0.88 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:52 PM PDT 24
Peak memory 196732 kb
Host smart-254683e1-795c-426b-9820-ed9573d4886a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931867418 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.931867418
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2777154941
Short name T406
Test name
Test status
Simulation time 441800118 ps
CPU time 1.15 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 192524 kb
Host smart-1d666a64-b271-40f1-ba73-12082ee43dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777154941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2777154941
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2543791200
Short name T371
Test name
Test status
Simulation time 506488890 ps
CPU time 0.69 seconds
Started Jul 27 06:21:43 PM PDT 24
Finished Jul 27 06:21:44 PM PDT 24
Peak memory 193420 kb
Host smart-a8409b1f-04bd-4d74-8c35-44333f1057af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543791200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2543791200
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3966459461
Short name T290
Test name
Test status
Simulation time 429124457 ps
CPU time 0.58 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 184144 kb
Host smart-63f0a726-a350-4f7b-81a1-e03c9a12a2ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966459461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3966459461
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.589950797
Short name T300
Test name
Test status
Simulation time 414386351 ps
CPU time 1.1 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 184140 kb
Host smart-df1efdfb-b35c-4a73-863f-bc075a70581f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589950797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.589950797
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.706322247
Short name T391
Test name
Test status
Simulation time 2427584615 ps
CPU time 1.98 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 192536 kb
Host smart-3e6c4ccc-0c01-45f0-8c5d-75abdc1c7ffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706322247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.706322247
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3335755927
Short name T338
Test name
Test status
Simulation time 422311874 ps
CPU time 2.25 seconds
Started Jul 27 06:21:38 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 199024 kb
Host smart-a7f8f37e-238d-497c-9453-05f3285ebbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335755927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3335755927
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3972520089
Short name T354
Test name
Test status
Simulation time 7909041911 ps
CPU time 11.46 seconds
Started Jul 27 06:21:43 PM PDT 24
Finished Jul 27 06:21:54 PM PDT 24
Peak memory 198688 kb
Host smart-fe35f63e-6823-43d6-b0d9-95bc47452c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972520089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3972520089
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3118736046
Short name T401
Test name
Test status
Simulation time 667422401 ps
CPU time 0.92 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:51 PM PDT 24
Peak memory 193636 kb
Host smart-c63b7f91-bf77-48c2-a694-4ddba6949b07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118736046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3118736046
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1385446739
Short name T65
Test name
Test status
Simulation time 12838685548 ps
CPU time 3.81 seconds
Started Jul 27 06:21:49 PM PDT 24
Finished Jul 27 06:21:53 PM PDT 24
Peak memory 192708 kb
Host smart-4c086a46-60de-4887-ad25-22d803a72215
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385446739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1385446739
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.964423076
Short name T67
Test name
Test status
Simulation time 646216401 ps
CPU time 1.4 seconds
Started Jul 27 06:21:46 PM PDT 24
Finished Jul 27 06:21:48 PM PDT 24
Peak memory 193440 kb
Host smart-3b98274f-d7f4-4383-82ad-94b2a3b68d86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964423076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.964423076
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2298909459
Short name T392
Test name
Test status
Simulation time 333383804 ps
CPU time 1.11 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:52 PM PDT 24
Peak memory 196092 kb
Host smart-a58ccd74-84ca-4541-bae4-d02691e2becd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298909459 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2298909459
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.171248838
Short name T54
Test name
Test status
Simulation time 312012214 ps
CPU time 1.02 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 193608 kb
Host smart-0ee73996-db00-449f-85ef-f20c5356b2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171248838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.171248838
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1356743556
Short name T384
Test name
Test status
Simulation time 423608161 ps
CPU time 1.04 seconds
Started Jul 27 06:21:47 PM PDT 24
Finished Jul 27 06:21:48 PM PDT 24
Peak memory 184252 kb
Host smart-b70acea7-25fd-4cfc-b0c2-e66b7af414a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356743556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1356743556
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2098536359
Short name T403
Test name
Test status
Simulation time 298800520 ps
CPU time 0.94 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:51 PM PDT 24
Peak memory 184128 kb
Host smart-2506bf57-07a7-48b7-8854-805de034529d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098536359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2098536359
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4119322264
Short name T304
Test name
Test status
Simulation time 403687864 ps
CPU time 0.62 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 184172 kb
Host smart-2f31b9e1-4da9-42f3-abe5-9b833b2bdbc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119322264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4119322264
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2904774613
Short name T414
Test name
Test status
Simulation time 2551451117 ps
CPU time 2 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:52 PM PDT 24
Peak memory 192524 kb
Host smart-b259a047-477b-4971-9062-6cd883bcf19d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904774613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2904774613
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.276050830
Short name T303
Test name
Test status
Simulation time 655713547 ps
CPU time 1.66 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 199068 kb
Host smart-6bdf3015-1618-4233-92a2-90581c759d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276050830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.276050830
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1258935470
Short name T412
Test name
Test status
Simulation time 8239208021 ps
CPU time 14.37 seconds
Started Jul 27 06:21:49 PM PDT 24
Finished Jul 27 06:22:03 PM PDT 24
Peak memory 198776 kb
Host smart-8822a20b-fa8b-45b0-815a-2783646b8d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258935470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1258935470
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2200131423
Short name T298
Test name
Test status
Simulation time 335658110 ps
CPU time 0.77 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 196632 kb
Host smart-23bdb5db-af70-4e89-a793-6838e49cfc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200131423 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2200131423
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1655679073
Short name T77
Test name
Test status
Simulation time 350668702 ps
CPU time 0.87 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:26 PM PDT 24
Peak memory 193476 kb
Host smart-861e8c8c-1afa-46f3-8122-fb46f8f3e47f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655679073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1655679073
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2994424737
Short name T366
Test name
Test status
Simulation time 488761029 ps
CPU time 0.69 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:26 PM PDT 24
Peak memory 184424 kb
Host smart-d6a52b8e-ee84-4800-9e91-34bbea7185d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994424737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2994424737
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1744343920
Short name T87
Test name
Test status
Simulation time 1580294727 ps
CPU time 1.48 seconds
Started Jul 27 06:22:24 PM PDT 24
Finished Jul 27 06:22:25 PM PDT 24
Peak memory 194376 kb
Host smart-7597079c-5862-4642-a768-97ba2c5a5f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744343920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1744343920
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.649417474
Short name T388
Test name
Test status
Simulation time 437066018 ps
CPU time 3.23 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:30 PM PDT 24
Peak memory 199060 kb
Host smart-4433c05b-db9e-48f5-baae-ec8f0873ff66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649417474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.649417474
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3586768083
Short name T37
Test name
Test status
Simulation time 8534185170 ps
CPU time 4.35 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:30 PM PDT 24
Peak memory 198680 kb
Host smart-fd16d94f-4618-4f03-a76c-4b5149f3e9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586768083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3586768083
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.368095289
Short name T321
Test name
Test status
Simulation time 393614641 ps
CPU time 1.13 seconds
Started Jul 27 06:22:24 PM PDT 24
Finished Jul 27 06:22:25 PM PDT 24
Peak memory 195832 kb
Host smart-1a3752b0-028d-4689-b161-82f7e333e4c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368095289 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.368095289
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.179301463
Short name T305
Test name
Test status
Simulation time 347426215 ps
CPU time 0.69 seconds
Started Jul 27 06:22:24 PM PDT 24
Finished Jul 27 06:22:25 PM PDT 24
Peak memory 193464 kb
Host smart-abdc637a-f5d9-4eea-878b-847c3a9d44d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179301463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.179301463
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2914919009
Short name T415
Test name
Test status
Simulation time 371827174 ps
CPU time 0.61 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 184240 kb
Host smart-2b5ca48e-04af-4718-8581-525ef4f7d6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914919009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2914919009
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1207261104
Short name T91
Test name
Test status
Simulation time 1127609124 ps
CPU time 1.35 seconds
Started Jul 27 06:22:29 PM PDT 24
Finished Jul 27 06:22:30 PM PDT 24
Peak memory 193432 kb
Host smart-a26aeca3-286d-49f7-a58f-91e6c486be93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207261104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1207261104
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3105730990
Short name T330
Test name
Test status
Simulation time 1128090686 ps
CPU time 1.77 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 199060 kb
Host smart-0193ad9a-88f4-43ef-bfb4-2a3baf5d5039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105730990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3105730990
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.786858650
Short name T316
Test name
Test status
Simulation time 8296617132 ps
CPU time 3.54 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:29 PM PDT 24
Peak memory 198820 kb
Host smart-9a5d41b6-4cdb-4d30-b4a9-c3170c9c3f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786858650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.786858650
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4199095160
Short name T349
Test name
Test status
Simulation time 397155548 ps
CPU time 0.78 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:27 PM PDT 24
Peak memory 196944 kb
Host smart-f8aa8008-a71a-4098-b5c9-055cb6636972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199095160 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4199095160
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.913027050
Short name T63
Test name
Test status
Simulation time 341308901 ps
CPU time 1.1 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:26 PM PDT 24
Peak memory 193668 kb
Host smart-e07d20b9-14c8-429c-98ec-cddb795b9873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913027050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.913027050
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3030455661
Short name T317
Test name
Test status
Simulation time 389731945 ps
CPU time 0.84 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:27 PM PDT 24
Peak memory 184232 kb
Host smart-dd3a6800-c683-4f12-881a-a0f0428e8e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030455661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3030455661
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2824971789
Short name T86
Test name
Test status
Simulation time 1427723785 ps
CPU time 2.41 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 184196 kb
Host smart-c0872833-ac9e-4182-b62e-28db1ba23144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824971789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2824971789
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.191757615
Short name T337
Test name
Test status
Simulation time 520635341 ps
CPU time 2.26 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 199000 kb
Host smart-02ca18f0-29b0-41c8-a30b-abdb64f5f0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191757615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.191757615
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3278460406
Short name T194
Test name
Test status
Simulation time 4326981636 ps
CPU time 5.32 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:32 PM PDT 24
Peak memory 198260 kb
Host smart-f40430ec-c483-42e4-a8bd-13bd7d4f9b09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278460406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3278460406
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.276337514
Short name T357
Test name
Test status
Simulation time 426939278 ps
CPU time 1.07 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:26 PM PDT 24
Peak memory 197336 kb
Host smart-13f2bcc8-218d-4856-9f51-48dc5f88b8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276337514 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.276337514
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1243739256
Short name T356
Test name
Test status
Simulation time 579518441 ps
CPU time 0.63 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:27 PM PDT 24
Peak memory 192504 kb
Host smart-755d8225-e525-4f25-acab-5e0b23bf7d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243739256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1243739256
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.676054711
Short name T287
Test name
Test status
Simulation time 471488457 ps
CPU time 0.75 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 184216 kb
Host smart-dda6efdd-8850-48d1-8e6d-750e33a10a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676054711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.676054711
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3868397352
Short name T88
Test name
Test status
Simulation time 865692014 ps
CPU time 0.96 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 193828 kb
Host smart-3550988a-1bc4-4fcf-9edd-465aa4d0799a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868397352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3868397352
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3510017066
Short name T351
Test name
Test status
Simulation time 476299477 ps
CPU time 1.12 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:29 PM PDT 24
Peak memory 197276 kb
Host smart-d72377f1-feaf-4a23-aea1-0ade48bc5d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510017066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3510017066
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.104196827
Short name T382
Test name
Test status
Simulation time 8319491081 ps
CPU time 4.13 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:31 PM PDT 24
Peak memory 198892 kb
Host smart-3e1c20c1-8293-4e31-977a-cf0919144899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104196827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.104196827
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1507596821
Short name T345
Test name
Test status
Simulation time 455839958 ps
CPU time 1.3 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 196668 kb
Host smart-9d6539ab-13bd-43e8-abf1-d4eb449b670c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507596821 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1507596821
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1956083133
Short name T315
Test name
Test status
Simulation time 370987453 ps
CPU time 0.57 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:34 PM PDT 24
Peak memory 184284 kb
Host smart-fb7b553f-1980-47e4-8848-bc54265e2f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956083133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1956083133
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.599335907
Short name T90
Test name
Test status
Simulation time 2893683886 ps
CPU time 2.41 seconds
Started Jul 27 06:22:39 PM PDT 24
Finished Jul 27 06:22:42 PM PDT 24
Peak memory 194496 kb
Host smart-0b907b47-59a7-4d49-8efc-293839b066b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599335907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.599335907
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.84803034
Short name T370
Test name
Test status
Simulation time 429980664 ps
CPU time 2.01 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:37 PM PDT 24
Peak memory 198944 kb
Host smart-9d764e5f-5019-431d-9363-3884ae484711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84803034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.84803034
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4249807304
Short name T195
Test name
Test status
Simulation time 4137728955 ps
CPU time 3.66 seconds
Started Jul 27 06:22:35 PM PDT 24
Finished Jul 27 06:22:39 PM PDT 24
Peak memory 198380 kb
Host smart-e8300c94-7dc3-4880-acca-83462b93a830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249807304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4249807304
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1983698689
Short name T202
Test name
Test status
Simulation time 384726288 ps
CPU time 0.89 seconds
Started Jul 27 06:22:36 PM PDT 24
Finished Jul 27 06:22:37 PM PDT 24
Peak memory 196004 kb
Host smart-e7085c51-8af7-481d-9e33-9cc5fea0cfe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983698689 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1983698689
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.744941691
Short name T34
Test name
Test status
Simulation time 533077480 ps
CPU time 1.38 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 193732 kb
Host smart-59eaceeb-f430-4f21-9ad6-bfeb6f5b3be2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744941691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.744941691
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1535801417
Short name T409
Test name
Test status
Simulation time 524971596 ps
CPU time 0.95 seconds
Started Jul 27 06:22:40 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 193456 kb
Host smart-60a7eb33-b7ce-48f4-9b88-b1cfbfdf2015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535801417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1535801417
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3053115655
Short name T89
Test name
Test status
Simulation time 2426896806 ps
CPU time 1.98 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 194568 kb
Host smart-3155541f-62d4-428d-9470-12a86073bea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053115655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3053115655
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2399648484
Short name T399
Test name
Test status
Simulation time 522105788 ps
CPU time 2.05 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 199076 kb
Host smart-c86b42ea-977a-4be1-81ac-a3a70bda0006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399648484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2399648484
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2130672322
Short name T352
Test name
Test status
Simulation time 465959733 ps
CPU time 0.96 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 198420 kb
Host smart-dd830646-d5b1-4e04-bb15-33b3894570e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130672322 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2130672322
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.509897441
Short name T52
Test name
Test status
Simulation time 388850874 ps
CPU time 0.94 seconds
Started Jul 27 06:22:39 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 193848 kb
Host smart-74dd8db0-cad2-4453-91df-a6ba854672af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509897441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.509897441
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2596394301
Short name T369
Test name
Test status
Simulation time 375076667 ps
CPU time 1.03 seconds
Started Jul 27 06:22:39 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 193416 kb
Host smart-d5f66c6b-2cec-44b5-81ec-4c5485623609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596394301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2596394301
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.975623733
Short name T333
Test name
Test status
Simulation time 2325536214 ps
CPU time 4.16 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:39 PM PDT 24
Peak memory 195564 kb
Host smart-e7c6a542-2100-46e7-8072-b089a6a552ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975623733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.975623733
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3884328084
Short name T331
Test name
Test status
Simulation time 435737106 ps
CPU time 1.11 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:34 PM PDT 24
Peak memory 198840 kb
Host smart-447c38b3-59d4-40a0-a1ef-f60d530eb6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884328084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3884328084
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2655971032
Short name T200
Test name
Test status
Simulation time 7837895902 ps
CPU time 12.97 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:47 PM PDT 24
Peak memory 198676 kb
Host smart-5ae374e7-4511-4fef-aff9-30ff96e922e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655971032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2655971032
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1541972593
Short name T309
Test name
Test status
Simulation time 362220011 ps
CPU time 1.21 seconds
Started Jul 27 06:22:36 PM PDT 24
Finished Jul 27 06:22:38 PM PDT 24
Peak memory 196560 kb
Host smart-c5661e35-7af8-4dd4-a307-1407f4b831f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541972593 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1541972593
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2541456944
Short name T359
Test name
Test status
Simulation time 356996468 ps
CPU time 0.69 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 192704 kb
Host smart-7d5b980e-97ad-468f-8220-d4d24f11dbad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541456944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2541456944
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1051367103
Short name T302
Test name
Test status
Simulation time 521151468 ps
CPU time 0.76 seconds
Started Jul 27 06:22:34 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 193372 kb
Host smart-9fa09192-a9b9-4184-86bd-a5cf478f32bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051367103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1051367103
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.693053724
Short name T329
Test name
Test status
Simulation time 2061736114 ps
CPU time 3.56 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:37 PM PDT 24
Peak memory 194364 kb
Host smart-876b65a8-444e-41f1-aa29-a8c1394816c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693053724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.693053724
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1073650673
Short name T291
Test name
Test status
Simulation time 418560122 ps
CPU time 2.41 seconds
Started Jul 27 06:22:38 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 199068 kb
Host smart-23bffae8-28fc-4a08-bee9-abc84822df4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073650673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1073650673
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3127241851
Short name T383
Test name
Test status
Simulation time 4550434790 ps
CPU time 2.63 seconds
Started Jul 27 06:22:32 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 197412 kb
Host smart-2a19b7c4-87ab-4888-a0a8-f4d94f60bce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127241851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3127241851
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3458976744
Short name T334
Test name
Test status
Simulation time 435832525 ps
CPU time 1.28 seconds
Started Jul 27 06:22:49 PM PDT 24
Finished Jul 27 06:22:51 PM PDT 24
Peak memory 196356 kb
Host smart-fb0441af-b582-424c-a423-cb6aeefab278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458976744 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3458976744
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4102862568
Short name T408
Test name
Test status
Simulation time 422325031 ps
CPU time 1.11 seconds
Started Jul 27 06:22:33 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 193524 kb
Host smart-15365a44-c8a4-4aed-af71-9024c19ec144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102862568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4102862568
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1944468737
Short name T365
Test name
Test status
Simulation time 420481074 ps
CPU time 0.68 seconds
Started Jul 27 06:22:32 PM PDT 24
Finished Jul 27 06:22:32 PM PDT 24
Peak memory 193404 kb
Host smart-5cae7583-1cdd-4a7d-bdbc-a97f365e0b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944468737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1944468737
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3215094949
Short name T419
Test name
Test status
Simulation time 1634366305 ps
CPU time 0.99 seconds
Started Jul 27 06:22:32 PM PDT 24
Finished Jul 27 06:22:33 PM PDT 24
Peak memory 192396 kb
Host smart-4971ae7c-602a-4713-8a77-ce205393f1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215094949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3215094949
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.398881426
Short name T347
Test name
Test status
Simulation time 491697772 ps
CPU time 1.45 seconds
Started Jul 27 06:22:35 PM PDT 24
Finished Jul 27 06:22:36 PM PDT 24
Peak memory 199052 kb
Host smart-b3b1ac22-00a3-40ff-b88e-bd6fd34bfd46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398881426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.398881426
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.827511893
Short name T196
Test name
Test status
Simulation time 4912676143 ps
CPU time 2.7 seconds
Started Jul 27 06:22:35 PM PDT 24
Finished Jul 27 06:22:38 PM PDT 24
Peak memory 197292 kb
Host smart-db812d7f-bfc4-4a7e-b991-1e90afeb76e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827511893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.827511893
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4113703941
Short name T342
Test name
Test status
Simulation time 549799621 ps
CPU time 0.89 seconds
Started Jul 27 06:22:49 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 196836 kb
Host smart-ef35d9a0-d13a-454c-9e1a-b86fc459ea82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113703941 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4113703941
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4119684305
Short name T411
Test name
Test status
Simulation time 426796622 ps
CPU time 0.89 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:48 PM PDT 24
Peak memory 194420 kb
Host smart-bb524b11-9eff-4cf3-a831-d8d68aacfcff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119684305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4119684305
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3912834764
Short name T353
Test name
Test status
Simulation time 490026185 ps
CPU time 0.7 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184200 kb
Host smart-ac9dac98-1f4d-410b-bd6c-9cecd742e516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912834764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3912834764
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2297160431
Short name T343
Test name
Test status
Simulation time 1362277071 ps
CPU time 2.27 seconds
Started Jul 27 06:22:49 PM PDT 24
Finished Jul 27 06:22:51 PM PDT 24
Peak memory 194324 kb
Host smart-14b22c95-2f2e-4910-8070-3c2ba3578b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297160431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2297160431
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2499858732
Short name T310
Test name
Test status
Simulation time 603237018 ps
CPU time 1.93 seconds
Started Jul 27 06:22:50 PM PDT 24
Finished Jul 27 06:22:52 PM PDT 24
Peak memory 199052 kb
Host smart-07314255-93b8-4077-8e53-61c44ca09308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499858732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2499858732
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1845905830
Short name T395
Test name
Test status
Simulation time 4339426068 ps
CPU time 6.77 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:54 PM PDT 24
Peak memory 198508 kb
Host smart-a8f6f8e9-3c18-47b1-9c7d-a84539446bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845905830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1845905830
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3703426095
Short name T306
Test name
Test status
Simulation time 519142567 ps
CPU time 1.09 seconds
Started Jul 27 06:21:56 PM PDT 24
Finished Jul 27 06:21:57 PM PDT 24
Peak memory 184280 kb
Host smart-0a1af297-cef0-441c-8023-c0cc94dd6815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703426095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3703426095
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3380972695
Short name T55
Test name
Test status
Simulation time 11871710803 ps
CPU time 9.2 seconds
Started Jul 27 06:21:59 PM PDT 24
Finished Jul 27 06:22:09 PM PDT 24
Peak memory 196548 kb
Host smart-5816478b-0598-428c-bfe5-cf2cae91f895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380972695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3380972695
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2563660755
Short name T405
Test name
Test status
Simulation time 1159029933 ps
CPU time 2.28 seconds
Started Jul 27 06:21:58 PM PDT 24
Finished Jul 27 06:22:00 PM PDT 24
Peak memory 184216 kb
Host smart-f7041cc2-3d38-4703-a3f7-1e36803f5e89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563660755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2563660755
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2473165992
Short name T363
Test name
Test status
Simulation time 401840599 ps
CPU time 0.88 seconds
Started Jul 27 06:21:56 PM PDT 24
Finished Jul 27 06:21:57 PM PDT 24
Peak memory 196772 kb
Host smart-267040af-d907-457f-8d67-4c29bcd9d25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473165992 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2473165992
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3313369162
Short name T62
Test name
Test status
Simulation time 456858580 ps
CPU time 0.75 seconds
Started Jul 27 06:21:57 PM PDT 24
Finished Jul 27 06:21:58 PM PDT 24
Peak memory 194464 kb
Host smart-2c901124-4a41-4984-8e94-0dc842023703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313369162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3313369162
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2324862545
Short name T332
Test name
Test status
Simulation time 360921525 ps
CPU time 0.8 seconds
Started Jul 27 06:21:47 PM PDT 24
Finished Jul 27 06:21:47 PM PDT 24
Peak memory 184244 kb
Host smart-ef0d74d0-5eab-4c20-8479-4f1048463c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324862545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2324862545
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1198397499
Short name T325
Test name
Test status
Simulation time 422345993 ps
CPU time 1.06 seconds
Started Jul 27 06:21:49 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 184064 kb
Host smart-89ada440-5810-4f00-a849-3c28e501d1db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198397499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1198397499
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.154185514
Short name T312
Test name
Test status
Simulation time 446171549 ps
CPU time 0.9 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 184144 kb
Host smart-3d4867f2-dc58-411c-a03f-95bebbb0efc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154185514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.154185514
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2627461220
Short name T387
Test name
Test status
Simulation time 1699884384 ps
CPU time 5.79 seconds
Started Jul 27 06:21:56 PM PDT 24
Finished Jul 27 06:22:02 PM PDT 24
Peak memory 194092 kb
Host smart-a4fb85c9-0f30-41a6-b9eb-ba9ef4448885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627461220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2627461220
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3158004437
Short name T362
Test name
Test status
Simulation time 650887861 ps
CPU time 1.37 seconds
Started Jul 27 06:21:48 PM PDT 24
Finished Jul 27 06:21:49 PM PDT 24
Peak memory 198996 kb
Host smart-cf183d0f-6250-4fcd-beed-f4f1125d5488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158004437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3158004437
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3607557571
Short name T36
Test name
Test status
Simulation time 4524473526 ps
CPU time 3.97 seconds
Started Jul 27 06:21:50 PM PDT 24
Finished Jul 27 06:21:55 PM PDT 24
Peak memory 198312 kb
Host smart-0d9d6d44-0fea-4c7f-94df-efd991179de9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607557571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3607557571
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1963783504
Short name T413
Test name
Test status
Simulation time 322375505 ps
CPU time 1.03 seconds
Started Jul 27 06:22:49 PM PDT 24
Finished Jul 27 06:22:50 PM PDT 24
Peak memory 184224 kb
Host smart-667806ef-55d4-4706-8d71-855c0e810dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963783504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1963783504
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2067880801
Short name T339
Test name
Test status
Simulation time 556180666 ps
CPU time 0.62 seconds
Started Jul 27 06:22:54 PM PDT 24
Finished Jul 27 06:22:54 PM PDT 24
Peak memory 184192 kb
Host smart-09ee01d9-14c2-4dfb-9627-32bc603331cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067880801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2067880801
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3405893067
Short name T324
Test name
Test status
Simulation time 466311454 ps
CPU time 0.7 seconds
Started Jul 27 06:22:46 PM PDT 24
Finished Jul 27 06:22:47 PM PDT 24
Peak memory 193436 kb
Host smart-5045693e-d5be-44a7-a0e6-1d5df7acea21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405893067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3405893067
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2359579290
Short name T404
Test name
Test status
Simulation time 365123412 ps
CPU time 1.04 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184212 kb
Host smart-c331a818-88de-41ae-8f74-c44d7fd305f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359579290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2359579290
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2398386940
Short name T292
Test name
Test status
Simulation time 397081981 ps
CPU time 0.89 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184128 kb
Host smart-6270a9e0-ed5c-435f-98d1-bf72739d4057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398386940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2398386940
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1698581788
Short name T288
Test name
Test status
Simulation time 442534051 ps
CPU time 0.91 seconds
Started Jul 27 06:22:50 PM PDT 24
Finished Jul 27 06:22:51 PM PDT 24
Peak memory 184216 kb
Host smart-f29dc3be-629b-49ab-b33f-bbfb4304cb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698581788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1698581788
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4290855308
Short name T373
Test name
Test status
Simulation time 305408023 ps
CPU time 0.99 seconds
Started Jul 27 06:22:50 PM PDT 24
Finished Jul 27 06:22:51 PM PDT 24
Peak memory 193436 kb
Host smart-72ffbd8e-4a16-4124-ae11-f307d2841dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290855308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4290855308
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3072421201
Short name T296
Test name
Test status
Simulation time 435154477 ps
CPU time 1.24 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:50 PM PDT 24
Peak memory 184152 kb
Host smart-0d82daca-a3cf-42ec-a132-d9cf4e964e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072421201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3072421201
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2361409250
Short name T389
Test name
Test status
Simulation time 518689692 ps
CPU time 1.27 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184216 kb
Host smart-45531e07-5fa2-4085-9745-a399f33ec3af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361409250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2361409250
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2175140530
Short name T348
Test name
Test status
Simulation time 497738671 ps
CPU time 1.19 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:55 PM PDT 24
Peak memory 184236 kb
Host smart-3db17eca-a96c-4958-bae0-fc3cb586c310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175140530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2175140530
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1091137775
Short name T297
Test name
Test status
Simulation time 435331768 ps
CPU time 1.41 seconds
Started Jul 27 06:21:59 PM PDT 24
Finished Jul 27 06:22:01 PM PDT 24
Peak memory 194404 kb
Host smart-54f65baa-a965-4633-aebc-f4547ba2a81d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091137775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1091137775
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.854178769
Short name T381
Test name
Test status
Simulation time 1492933525 ps
CPU time 1.52 seconds
Started Jul 27 06:21:58 PM PDT 24
Finished Jul 27 06:21:59 PM PDT 24
Peak memory 196792 kb
Host smart-87ea535d-fa1c-4576-ac14-86845c0dfe33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854178769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.854178769
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2925533172
Short name T66
Test name
Test status
Simulation time 1178844582 ps
CPU time 2.43 seconds
Started Jul 27 06:21:59 PM PDT 24
Finished Jul 27 06:22:01 PM PDT 24
Peak memory 193424 kb
Host smart-ddc049f8-e595-44ab-a4e3-32165cf00bee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925533172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2925533172
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2597587631
Short name T341
Test name
Test status
Simulation time 404618769 ps
CPU time 1.22 seconds
Started Jul 27 06:22:09 PM PDT 24
Finished Jul 27 06:22:10 PM PDT 24
Peak memory 196508 kb
Host smart-4b9a69f8-3be8-448b-a912-84907cc9321f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597587631 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2597587631
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.592865584
Short name T60
Test name
Test status
Simulation time 490703443 ps
CPU time 0.92 seconds
Started Jul 27 06:21:59 PM PDT 24
Finished Jul 27 06:22:00 PM PDT 24
Peak memory 192520 kb
Host smart-844575b2-5ad8-4818-b0bf-d15a939549db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592865584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.592865584
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2230754227
Short name T311
Test name
Test status
Simulation time 455145459 ps
CPU time 0.63 seconds
Started Jul 27 06:21:56 PM PDT 24
Finished Jul 27 06:21:57 PM PDT 24
Peak memory 184260 kb
Host smart-62755e4c-b40e-42ad-bdd7-383f22ee98ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230754227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2230754227
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1986041889
Short name T355
Test name
Test status
Simulation time 520143389 ps
CPU time 0.7 seconds
Started Jul 27 06:21:59 PM PDT 24
Finished Jul 27 06:21:59 PM PDT 24
Peak memory 184132 kb
Host smart-e1499eff-5808-426a-9d07-2b106d1849b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986041889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1986041889
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1130874560
Short name T407
Test name
Test status
Simulation time 308343384 ps
CPU time 0.76 seconds
Started Jul 27 06:21:58 PM PDT 24
Finished Jul 27 06:21:59 PM PDT 24
Peak memory 184076 kb
Host smart-3cfac959-f98c-41c8-86da-1fc3d7ec32f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130874560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1130874560
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2566659728
Short name T379
Test name
Test status
Simulation time 1657762000 ps
CPU time 3 seconds
Started Jul 27 06:21:57 PM PDT 24
Finished Jul 27 06:22:00 PM PDT 24
Peak memory 184556 kb
Host smart-f599dfd1-8b2e-46dc-9b96-7dd1c48d87d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566659728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2566659728
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1284826018
Short name T301
Test name
Test status
Simulation time 611681379 ps
CPU time 1.35 seconds
Started Jul 27 06:21:56 PM PDT 24
Finished Jul 27 06:21:58 PM PDT 24
Peak memory 199016 kb
Host smart-ac28d6da-981b-4bc4-8e21-4a5177602876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284826018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1284826018
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3682724276
Short name T390
Test name
Test status
Simulation time 4960446379 ps
CPU time 2.57 seconds
Started Jul 27 06:21:58 PM PDT 24
Finished Jul 27 06:22:00 PM PDT 24
Peak memory 198128 kb
Host smart-e06a392f-c95e-4a40-ad1a-717899e49c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682724276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3682724276
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3525337857
Short name T377
Test name
Test status
Simulation time 481976317 ps
CPU time 0.71 seconds
Started Jul 27 06:22:46 PM PDT 24
Finished Jul 27 06:22:46 PM PDT 24
Peak memory 184168 kb
Host smart-0236f089-5dcd-4bd4-920c-ef0d2353091b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525337857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3525337857
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1884295544
Short name T327
Test name
Test status
Simulation time 459652882 ps
CPU time 1.16 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184132 kb
Host smart-75568313-0324-4ed9-81be-2a724c380083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884295544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1884295544
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3085921578
Short name T378
Test name
Test status
Simulation time 591643621 ps
CPU time 0.6 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:47 PM PDT 24
Peak memory 184188 kb
Host smart-4c5ee294-dd7a-43d0-aadb-b393e972845d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085921578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3085921578
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3669369908
Short name T374
Test name
Test status
Simulation time 457555478 ps
CPU time 0.89 seconds
Started Jul 27 06:22:46 PM PDT 24
Finished Jul 27 06:22:47 PM PDT 24
Peak memory 184188 kb
Host smart-a2c95ee4-b0b5-42fb-8f9f-5ccf9d959943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669369908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3669369908
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1936536098
Short name T397
Test name
Test status
Simulation time 482992104 ps
CPU time 1.31 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 184284 kb
Host smart-1265b39e-cb82-422c-b688-fe3bd1a42463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936536098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1936536098
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.622830863
Short name T376
Test name
Test status
Simulation time 461440625 ps
CPU time 1.21 seconds
Started Jul 27 06:22:48 PM PDT 24
Finished Jul 27 06:22:50 PM PDT 24
Peak memory 193420 kb
Host smart-b9524a0f-2861-4638-aa6c-5ed4fbaef1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622830863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.622830863
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3957379317
Short name T294
Test name
Test status
Simulation time 460144798 ps
CPU time 1.23 seconds
Started Jul 27 06:22:46 PM PDT 24
Finished Jul 27 06:22:48 PM PDT 24
Peak memory 184208 kb
Host smart-072c0965-97ee-40d0-bda0-0a48050a8f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957379317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3957379317
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2419511873
Short name T364
Test name
Test status
Simulation time 436263880 ps
CPU time 0.81 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:54 PM PDT 24
Peak memory 184236 kb
Host smart-96545779-b5be-45f4-b029-12a9b92441cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419511873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2419511873
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2626517324
Short name T299
Test name
Test status
Simulation time 491974086 ps
CPU time 1.26 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 193428 kb
Host smart-9fa88c9e-7d83-4b7c-99b2-0b64eb28976f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626517324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2626517324
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3201587157
Short name T422
Test name
Test status
Simulation time 410441540 ps
CPU time 1.28 seconds
Started Jul 27 06:22:47 PM PDT 24
Finished Jul 27 06:22:49 PM PDT 24
Peak memory 193436 kb
Host smart-15ea3731-dc3c-4b41-8c1a-318b2ccfa5cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201587157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3201587157
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2097504406
Short name T402
Test name
Test status
Simulation time 472667634 ps
CPU time 1.32 seconds
Started Jul 27 06:22:10 PM PDT 24
Finished Jul 27 06:22:11 PM PDT 24
Peak memory 193708 kb
Host smart-a2229bd3-f23d-4e92-bba8-6001f41e107a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097504406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2097504406
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1196219747
Short name T64
Test name
Test status
Simulation time 8770534739 ps
CPU time 12.85 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:19 PM PDT 24
Peak memory 192732 kb
Host smart-1e356194-cdb0-4652-90d0-8ccb75047ca3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196219747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1196219747
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.373125145
Short name T57
Test name
Test status
Simulation time 762685735 ps
CPU time 1.06 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 184212 kb
Host smart-13fbd8c6-12e9-4cd3-ae70-6c7c1239db97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373125145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.373125145
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3967525518
Short name T295
Test name
Test status
Simulation time 457870248 ps
CPU time 0.85 seconds
Started Jul 27 06:22:08 PM PDT 24
Finished Jul 27 06:22:09 PM PDT 24
Peak memory 197884 kb
Host smart-5f9c5108-37c5-4080-b178-7f1ed746a92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967525518 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3967525518
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2473861260
Short name T61
Test name
Test status
Simulation time 342094588 ps
CPU time 0.69 seconds
Started Jul 27 06:22:10 PM PDT 24
Finished Jul 27 06:22:11 PM PDT 24
Peak memory 193412 kb
Host smart-69c08a06-2728-4ede-b1f0-59330d602cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473861260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2473861260
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1604013682
Short name T423
Test name
Test status
Simulation time 421535280 ps
CPU time 0.69 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 184224 kb
Host smart-ee60f679-d19b-4c59-8ebe-0a980484491c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604013682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1604013682
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1500239519
Short name T416
Test name
Test status
Simulation time 519734240 ps
CPU time 1.31 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:08 PM PDT 24
Peak memory 184120 kb
Host smart-72a8aa70-1963-4098-883e-804132ba87c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500239519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1500239519
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1263795071
Short name T289
Test name
Test status
Simulation time 384523478 ps
CPU time 0.78 seconds
Started Jul 27 06:22:07 PM PDT 24
Finished Jul 27 06:22:08 PM PDT 24
Peak memory 184104 kb
Host smart-81ede0fb-b5e7-430a-b039-c260404ec2ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263795071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1263795071
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4003274745
Short name T386
Test name
Test status
Simulation time 1515005866 ps
CPU time 1.48 seconds
Started Jul 27 06:22:08 PM PDT 24
Finished Jul 27 06:22:10 PM PDT 24
Peak memory 193408 kb
Host smart-9f03a6ff-4753-4be7-a7c0-bbc9b0f6fce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003274745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4003274745
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3801589147
Short name T308
Test name
Test status
Simulation time 541529941 ps
CPU time 1.78 seconds
Started Jul 27 06:22:09 PM PDT 24
Finished Jul 27 06:22:11 PM PDT 24
Peak memory 198012 kb
Host smart-d9b53b11-7368-419d-bb22-66eaa951007f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801589147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3801589147
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3821864816
Short name T360
Test name
Test status
Simulation time 4476295515 ps
CPU time 4.44 seconds
Started Jul 27 06:22:04 PM PDT 24
Finished Jul 27 06:22:09 PM PDT 24
Peak memory 198184 kb
Host smart-91271e03-3d78-4bc2-ac9f-7971c6ad294f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821864816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3821864816
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1158565967
Short name T335
Test name
Test status
Simulation time 625783653 ps
CPU time 0.62 seconds
Started Jul 27 06:22:54 PM PDT 24
Finished Jul 27 06:22:55 PM PDT 24
Peak memory 193456 kb
Host smart-f4ef18d1-516a-4639-a22a-de9580cc7184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158565967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1158565967
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2219509635
Short name T336
Test name
Test status
Simulation time 480812099 ps
CPU time 0.98 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:54 PM PDT 24
Peak memory 184228 kb
Host smart-82698c39-2f53-4c04-83d0-68d3239ce616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219509635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2219509635
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3598618626
Short name T417
Test name
Test status
Simulation time 483944694 ps
CPU time 0.61 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:22:52 PM PDT 24
Peak memory 193452 kb
Host smart-400a1015-2670-4fbe-b447-dd93aba9d22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598618626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3598618626
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1547962945
Short name T375
Test name
Test status
Simulation time 507648437 ps
CPU time 1.29 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:22:53 PM PDT 24
Peak memory 184236 kb
Host smart-570c8597-c609-4f74-ac2d-281d1384855f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547962945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1547962945
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4078558825
Short name T318
Test name
Test status
Simulation time 358273833 ps
CPU time 1.08 seconds
Started Jul 27 06:22:54 PM PDT 24
Finished Jul 27 06:22:56 PM PDT 24
Peak memory 184228 kb
Host smart-67858fef-316d-4c40-8a77-d9d0e5df9d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078558825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4078558825
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2975061861
Short name T396
Test name
Test status
Simulation time 442494022 ps
CPU time 1.21 seconds
Started Jul 27 06:22:50 PM PDT 24
Finished Jul 27 06:22:52 PM PDT 24
Peak memory 184244 kb
Host smart-e2261168-04c7-42da-b88c-ab0e963df6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975061861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2975061861
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2485926260
Short name T307
Test name
Test status
Simulation time 431545345 ps
CPU time 1.17 seconds
Started Jul 27 06:22:54 PM PDT 24
Finished Jul 27 06:22:55 PM PDT 24
Peak memory 184228 kb
Host smart-598a3e8d-e25f-4b3f-b0fc-77fe64a88631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485926260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2485926260
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3346939774
Short name T358
Test name
Test status
Simulation time 393013648 ps
CPU time 0.8 seconds
Started Jul 27 06:22:51 PM PDT 24
Finished Jul 27 06:22:52 PM PDT 24
Peak memory 193412 kb
Host smart-991ed83f-638c-4a4a-9ba6-4731abf6653d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346939774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3346939774
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2699042001
Short name T398
Test name
Test status
Simulation time 377062967 ps
CPU time 1.06 seconds
Started Jul 27 06:22:53 PM PDT 24
Finished Jul 27 06:22:54 PM PDT 24
Peak memory 184228 kb
Host smart-8934363a-86ae-42ac-ad96-126f0deea9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699042001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2699042001
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.41592603
Short name T393
Test name
Test status
Simulation time 512663455 ps
CPU time 0.92 seconds
Started Jul 27 06:22:52 PM PDT 24
Finished Jul 27 06:22:53 PM PDT 24
Peak memory 184236 kb
Host smart-4abb705e-d446-4eed-b665-0b04d486bb0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.41592603
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1999293722
Short name T323
Test name
Test status
Simulation time 462749441 ps
CPU time 0.96 seconds
Started Jul 27 06:22:16 PM PDT 24
Finished Jul 27 06:22:17 PM PDT 24
Peak memory 195980 kb
Host smart-d738ff07-1b18-4922-8dfa-c11614de62bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999293722 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1999293722
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1669053946
Short name T319
Test name
Test status
Simulation time 511459860 ps
CPU time 1.11 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 193556 kb
Host smart-06ba3b19-57fb-428f-a32d-413502b6f33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669053946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1669053946
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1376251626
Short name T328
Test name
Test status
Simulation time 340841973 ps
CPU time 0.58 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 184224 kb
Host smart-07da9069-a5b7-43d6-b267-f7e9fe0a40cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376251626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1376251626
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2755411982
Short name T372
Test name
Test status
Simulation time 1708835499 ps
CPU time 2.85 seconds
Started Jul 27 06:22:17 PM PDT 24
Finished Jul 27 06:22:20 PM PDT 24
Peak memory 194132 kb
Host smart-0abba5bb-c945-4842-a1f8-a2b739b02797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755411982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2755411982
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.19913822
Short name T326
Test name
Test status
Simulation time 494812374 ps
CPU time 1.56 seconds
Started Jul 27 06:22:06 PM PDT 24
Finished Jul 27 06:22:08 PM PDT 24
Peak memory 199056 kb
Host smart-00b1ae8a-6177-41d7-a587-cafee5a74661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.19913822
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.114894883
Short name T394
Test name
Test status
Simulation time 8337670658 ps
CPU time 7.67 seconds
Started Jul 27 06:22:07 PM PDT 24
Finished Jul 27 06:22:15 PM PDT 24
Peak memory 198848 kb
Host smart-8d852f8f-8471-48bc-98a7-b0301032ad5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114894883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.114894883
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1339220547
Short name T350
Test name
Test status
Simulation time 469991457 ps
CPU time 0.95 seconds
Started Jul 27 06:22:17 PM PDT 24
Finished Jul 27 06:22:18 PM PDT 24
Peak memory 196240 kb
Host smart-2d04c5a6-afe8-4d71-9cea-7f8dd530c3d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339220547 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1339220547
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4280800974
Short name T53
Test name
Test status
Simulation time 452976868 ps
CPU time 0.73 seconds
Started Jul 27 06:22:14 PM PDT 24
Finished Jul 27 06:22:14 PM PDT 24
Peak memory 193916 kb
Host smart-008ccb88-860e-4dfa-95f8-496ba0aa5458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280800974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4280800974
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.967957728
Short name T293
Test name
Test status
Simulation time 371321223 ps
CPU time 0.79 seconds
Started Jul 27 06:22:14 PM PDT 24
Finished Jul 27 06:22:15 PM PDT 24
Peak memory 184256 kb
Host smart-d675b46d-969f-4624-9fe3-6e76866e1a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967957728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.967957728
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.416048381
Short name T344
Test name
Test status
Simulation time 1108957692 ps
CPU time 3.7 seconds
Started Jul 27 06:22:15 PM PDT 24
Finished Jul 27 06:22:19 PM PDT 24
Peak memory 194416 kb
Host smart-350c1399-49f2-475c-ad15-824185448579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416048381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.416048381
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.710402184
Short name T340
Test name
Test status
Simulation time 570221320 ps
CPU time 1.62 seconds
Started Jul 27 06:22:16 PM PDT 24
Finished Jul 27 06:22:18 PM PDT 24
Peak memory 199036 kb
Host smart-bd10f21d-886c-4d4b-9d41-f588ee2676f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710402184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.710402184
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1691810100
Short name T201
Test name
Test status
Simulation time 8666530548 ps
CPU time 3.28 seconds
Started Jul 27 06:22:17 PM PDT 24
Finished Jul 27 06:22:21 PM PDT 24
Peak memory 198672 kb
Host smart-737e4108-f948-4d54-a109-f4fddd06829f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691810100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1691810100
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2909825225
Short name T33
Test name
Test status
Simulation time 552562183 ps
CPU time 0.91 seconds
Started Jul 27 06:22:15 PM PDT 24
Finished Jul 27 06:22:16 PM PDT 24
Peak memory 198024 kb
Host smart-baac1261-d0a4-4cbf-80d2-d17111b6db99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909825225 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2909825225
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.127454184
Short name T322
Test name
Test status
Simulation time 438858398 ps
CPU time 0.67 seconds
Started Jul 27 06:22:17 PM PDT 24
Finished Jul 27 06:22:17 PM PDT 24
Peak memory 193804 kb
Host smart-515d8b69-e630-49ff-9546-acf79de4313f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127454184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.127454184
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3404211711
Short name T286
Test name
Test status
Simulation time 338651020 ps
CPU time 1.02 seconds
Started Jul 27 06:22:14 PM PDT 24
Finished Jul 27 06:22:16 PM PDT 24
Peak memory 184264 kb
Host smart-5b2da065-f0a4-4ba5-830c-51fed69ba6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404211711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3404211711
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1153987863
Short name T368
Test name
Test status
Simulation time 2068177367 ps
CPU time 1.25 seconds
Started Jul 27 06:22:14 PM PDT 24
Finished Jul 27 06:22:16 PM PDT 24
Peak memory 195436 kb
Host smart-980e28f9-14df-43b6-9969-c33a78c1a8cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153987863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1153987863
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3684445857
Short name T320
Test name
Test status
Simulation time 578506737 ps
CPU time 2.4 seconds
Started Jul 27 06:22:20 PM PDT 24
Finished Jul 27 06:22:23 PM PDT 24
Peak memory 199084 kb
Host smart-f6ea026c-430f-498c-87ad-8cb42453af0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684445857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3684445857
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3956341126
Short name T198
Test name
Test status
Simulation time 8181449316 ps
CPU time 4.48 seconds
Started Jul 27 06:22:18 PM PDT 24
Finished Jul 27 06:22:23 PM PDT 24
Peak memory 198768 kb
Host smart-56db2d6c-430a-475a-a65b-05558c64319e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956341126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3956341126
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3325921256
Short name T421
Test name
Test status
Simulation time 506380514 ps
CPU time 0.82 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 195888 kb
Host smart-eee2569b-b168-4ab7-a8ce-ed56f7cd7d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325921256 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3325921256
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.632247298
Short name T410
Test name
Test status
Simulation time 473794099 ps
CPU time 0.69 seconds
Started Jul 27 06:22:16 PM PDT 24
Finished Jul 27 06:22:17 PM PDT 24
Peak memory 193916 kb
Host smart-272744d6-f437-49a9-be32-96b98e66ae50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632247298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.632247298
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3362853238
Short name T385
Test name
Test status
Simulation time 484501734 ps
CPU time 1.22 seconds
Started Jul 27 06:22:19 PM PDT 24
Finished Jul 27 06:22:20 PM PDT 24
Peak memory 193424 kb
Host smart-c49df975-f5a1-4db1-8510-d6a7c9ce7159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362853238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3362853238
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4018732450
Short name T418
Test name
Test status
Simulation time 1188678636 ps
CPU time 3.41 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 194024 kb
Host smart-7e48116a-27c3-4a56-9dfe-95bb3bd7edf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018732450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4018732450
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1946623679
Short name T361
Test name
Test status
Simulation time 781149566 ps
CPU time 1.02 seconds
Started Jul 27 06:22:18 PM PDT 24
Finished Jul 27 06:22:19 PM PDT 24
Peak memory 198332 kb
Host smart-4a5f81e8-d450-4a64-9fd6-8819062bc43a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946623679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1946623679
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3721784298
Short name T313
Test name
Test status
Simulation time 548163699 ps
CPU time 1.47 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:27 PM PDT 24
Peak memory 196580 kb
Host smart-8c32ad4a-007b-46e2-9524-4cec8971247c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721784298 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3721784298
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2290708970
Short name T380
Test name
Test status
Simulation time 419285921 ps
CPU time 0.62 seconds
Started Jul 27 06:22:26 PM PDT 24
Finished Jul 27 06:22:26 PM PDT 24
Peak memory 193804 kb
Host smart-0590f07f-bfd8-4837-9b91-1791a7bf2f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290708970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2290708970
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2466115367
Short name T314
Test name
Test status
Simulation time 525469461 ps
CPU time 0.67 seconds
Started Jul 27 06:22:27 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 193404 kb
Host smart-3faac9fe-6ae8-4297-b661-f21482277893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466115367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2466115367
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2019510767
Short name T367
Test name
Test status
Simulation time 2712878494 ps
CPU time 3.74 seconds
Started Jul 27 06:22:24 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 194484 kb
Host smart-0b80147a-c58b-4fc0-9a38-e1fd0a4afd84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019510767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2019510767
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3960221988
Short name T400
Test name
Test status
Simulation time 932904302 ps
CPU time 1.81 seconds
Started Jul 27 06:22:29 PM PDT 24
Finished Jul 27 06:22:31 PM PDT 24
Peak memory 199072 kb
Host smart-e984dc15-49b7-4dec-b0a2-deee971982d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960221988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3960221988
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4241157511
Short name T199
Test name
Test status
Simulation time 8566042090 ps
CPU time 14.54 seconds
Started Jul 27 06:22:25 PM PDT 24
Finished Jul 27 06:22:40 PM PDT 24
Peak memory 198848 kb
Host smart-f7a61484-c0c9-4f94-bd70-ab86fc8eb692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241157511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4241157511
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3143828994
Short name T43
Test name
Test status
Simulation time 52865429965 ps
CPU time 80.24 seconds
Started Jul 27 06:20:25 PM PDT 24
Finished Jul 27 06:21:45 PM PDT 24
Peak memory 191856 kb
Host smart-730545a3-997b-407d-a02f-25f919e0cd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143828994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3143828994
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.231543966
Short name T267
Test name
Test status
Simulation time 550753449 ps
CPU time 0.66 seconds
Started Jul 27 06:20:26 PM PDT 24
Finished Jul 27 06:20:27 PM PDT 24
Peak memory 191764 kb
Host smart-5e01f5a9-043c-42ce-af07-c128092518cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231543966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.231543966
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1532649631
Short name T6
Test name
Test status
Simulation time 30639344138 ps
CPU time 47.28 seconds
Started Jul 27 06:20:28 PM PDT 24
Finished Jul 27 06:21:16 PM PDT 24
Peak memory 191852 kb
Host smart-3907c40a-cee1-47bf-9701-ebcb5bc6a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532649631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1532649631
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1169115710
Short name T19
Test name
Test status
Simulation time 4201977097 ps
CPU time 6.14 seconds
Started Jul 27 06:20:31 PM PDT 24
Finished Jul 27 06:20:37 PM PDT 24
Peak memory 215564 kb
Host smart-aea76398-42de-4002-b841-8248a27839ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169115710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1169115710
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4247734814
Short name T210
Test name
Test status
Simulation time 397427634 ps
CPU time 0.75 seconds
Started Jul 27 06:20:30 PM PDT 24
Finished Jul 27 06:20:31 PM PDT 24
Peak memory 196620 kb
Host smart-09378591-db2a-4b8f-837c-6256e16940bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247734814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4247734814
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4173018078
Short name T259
Test name
Test status
Simulation time 6425322005 ps
CPU time 1.44 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:20:47 PM PDT 24
Peak memory 196876 kb
Host smart-847f493d-f9c8-4fc5-b637-a4afd1aae93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173018078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4173018078
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3020788967
Short name T221
Test name
Test status
Simulation time 504408178 ps
CPU time 0.76 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:20:36 PM PDT 24
Peak memory 196516 kb
Host smart-78a8f667-93e6-4d73-b2e3-aca516296004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020788967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3020788967
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3629058211
Short name T228
Test name
Test status
Simulation time 14496773828 ps
CPU time 20.72 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:21:08 PM PDT 24
Peak memory 191900 kb
Host smart-99d8fbfc-1a2c-4297-ab99-76c67af005ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629058211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3629058211
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3144894752
Short name T272
Test name
Test status
Simulation time 508378007 ps
CPU time 0.74 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:20:46 PM PDT 24
Peak memory 196520 kb
Host smart-be2e3ed7-bc01-47f7-b112-db36fc7fab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144894752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3144894752
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2739167603
Short name T273
Test name
Test status
Simulation time 37140799877 ps
CPU time 14 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:21:01 PM PDT 24
Peak memory 191880 kb
Host smart-ad228ef7-996e-4ec9-ac0e-d5874a1eb42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739167603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2739167603
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.167970276
Short name T216
Test name
Test status
Simulation time 476768331 ps
CPU time 1.19 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 196584 kb
Host smart-edc28721-f0d3-49f1-b65c-d27f16a8320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167970276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.167970276
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4063270759
Short name T211
Test name
Test status
Simulation time 20176488637 ps
CPU time 2.41 seconds
Started Jul 27 06:20:49 PM PDT 24
Finished Jul 27 06:20:52 PM PDT 24
Peak memory 196736 kb
Host smart-2c7f8be6-42c1-4663-8cdd-2b415d1e7b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063270759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4063270759
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2953639751
Short name T240
Test name
Test status
Simulation time 567600091 ps
CPU time 0.78 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 191748 kb
Host smart-5066a3f2-d6a3-43b0-a32d-511e3bf2448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953639751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2953639751
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3060499514
Short name T264
Test name
Test status
Simulation time 15495921309 ps
CPU time 24.12 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:21:12 PM PDT 24
Peak memory 191884 kb
Host smart-4104e5f3-6ce9-4ae5-821c-e9d649886e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060499514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3060499514
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2203237835
Short name T208
Test name
Test status
Simulation time 484121191 ps
CPU time 0.73 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:20:46 PM PDT 24
Peak memory 191768 kb
Host smart-2fb291f5-dcfb-4c0e-984f-7cf3d8e6eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203237835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2203237835
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1586238665
Short name T170
Test name
Test status
Simulation time 605793641 ps
CPU time 0.88 seconds
Started Jul 27 06:20:46 PM PDT 24
Finished Jul 27 06:20:47 PM PDT 24
Peak memory 196548 kb
Host smart-b359ccb4-dbc1-4dcb-85dc-e9ebe26cc4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586238665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1586238665
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2512036797
Short name T12
Test name
Test status
Simulation time 32667072104 ps
CPU time 43.43 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:21:30 PM PDT 24
Peak memory 191836 kb
Host smart-1d5ab657-2d87-4196-bc38-b52cfce3f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512036797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2512036797
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3786076414
Short name T220
Test name
Test status
Simulation time 463633367 ps
CPU time 1.23 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:49 PM PDT 24
Peak memory 191664 kb
Host smart-61c75757-1c45-4aae-90f0-4ffffe12e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786076414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3786076414
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2936265390
Short name T74
Test name
Test status
Simulation time 60378025121 ps
CPU time 87.78 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:22:16 PM PDT 24
Peak memory 196788 kb
Host smart-3646cbbd-44aa-46b8-a586-898a715c79dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936265390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2936265390
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2236655444
Short name T229
Test name
Test status
Simulation time 480641325 ps
CPU time 1.17 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:49 PM PDT 24
Peak memory 191740 kb
Host smart-f174fbc1-4b9b-430e-a4f0-2cdf13f1c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236655444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2236655444
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2249306575
Short name T219
Test name
Test status
Simulation time 17610772191 ps
CPU time 26.81 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:21:12 PM PDT 24
Peak memory 191900 kb
Host smart-2edb079e-17da-4e39-a8c3-7ba5460b4021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249306575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2249306575
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.524789028
Short name T237
Test name
Test status
Simulation time 487238602 ps
CPU time 0.77 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 191752 kb
Host smart-1fc0378f-9b97-46e8-a922-f023fb852964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524789028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.524789028
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1822778148
Short name T265
Test name
Test status
Simulation time 5602194826 ps
CPU time 8 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:56 PM PDT 24
Peak memory 191896 kb
Host smart-35a8d63f-236f-4181-ae24-e728d1b56dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822778148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1822778148
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1791284213
Short name T227
Test name
Test status
Simulation time 352429967 ps
CPU time 1.03 seconds
Started Jul 27 06:20:48 PM PDT 24
Finished Jul 27 06:20:49 PM PDT 24
Peak memory 191768 kb
Host smart-ddb39ea4-5a03-4a29-ad79-c010e498d692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791284213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1791284213
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2159979501
Short name T9
Test name
Test status
Simulation time 6287519645 ps
CPU time 2.67 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:21:00 PM PDT 24
Peak memory 191860 kb
Host smart-c62d2833-a89f-494f-8482-d8c1b4608beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159979501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2159979501
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3776360827
Short name T222
Test name
Test status
Simulation time 530030615 ps
CPU time 0.74 seconds
Started Jul 27 06:20:47 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 191764 kb
Host smart-9a97e52d-09a7-4eac-a025-3775f888c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776360827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3776360827
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1434496914
Short name T214
Test name
Test status
Simulation time 51199427638 ps
CPU time 18.19 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:47 PM PDT 24
Peak memory 191872 kb
Host smart-c5bba48d-2ca0-4bb3-86d1-0022071136af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434496914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1434496914
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1092043175
Short name T15
Test name
Test status
Simulation time 8335985817 ps
CPU time 13.36 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:42 PM PDT 24
Peak memory 215872 kb
Host smart-f313ef33-90b2-4a1a-bc4e-24e7e1458308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092043175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1092043175
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3608358483
Short name T279
Test name
Test status
Simulation time 391416089 ps
CPU time 1.12 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:29 PM PDT 24
Peak memory 191772 kb
Host smart-c1797900-80fc-4e26-abd0-3aa04096709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608358483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3608358483
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.585578835
Short name T217
Test name
Test status
Simulation time 4544749240 ps
CPU time 7.07 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:21:03 PM PDT 24
Peak memory 196892 kb
Host smart-4e09c88b-15ba-44f4-8dfd-74ab6bf3f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585578835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.585578835
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3126665444
Short name T248
Test name
Test status
Simulation time 484396591 ps
CPU time 0.75 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:56 PM PDT 24
Peak memory 191748 kb
Host smart-f994be10-2031-42ae-ad8c-ff69493a856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126665444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3126665444
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4090084563
Short name T275
Test name
Test status
Simulation time 47740240537 ps
CPU time 74.46 seconds
Started Jul 27 06:20:54 PM PDT 24
Finished Jul 27 06:22:09 PM PDT 24
Peak memory 191824 kb
Host smart-ca48d459-637d-4659-91f5-d475d94f164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090084563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4090084563
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.12612683
Short name T29
Test name
Test status
Simulation time 752052361 ps
CPU time 0.62 seconds
Started Jul 27 06:20:55 PM PDT 24
Finished Jul 27 06:20:56 PM PDT 24
Peak memory 191768 kb
Host smart-f1ecd4f0-1924-4759-9905-229fef679363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12612683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.12612683
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3382895866
Short name T251
Test name
Test status
Simulation time 39147619168 ps
CPU time 52.89 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:21:51 PM PDT 24
Peak memory 191804 kb
Host smart-3a029594-d974-48c8-9ab9-c75fb40c4448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382895866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3382895866
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2130213598
Short name T205
Test name
Test status
Simulation time 596205173 ps
CPU time 1.38 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:20:59 PM PDT 24
Peak memory 191828 kb
Host smart-f1936372-a6ba-4ad4-95af-13ac28dc2dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130213598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2130213598
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2658646781
Short name T236
Test name
Test status
Simulation time 14705023196 ps
CPU time 16.93 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:21:14 PM PDT 24
Peak memory 196856 kb
Host smart-93606429-ced5-4ba1-bfb1-0c2b86ed0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658646781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2658646781
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4251249796
Short name T281
Test name
Test status
Simulation time 530222278 ps
CPU time 0.68 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 191752 kb
Host smart-7c96e804-3721-4c8a-85d4-413a36234f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251249796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4251249796
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1895831089
Short name T207
Test name
Test status
Simulation time 22542902743 ps
CPU time 34.39 seconds
Started Jul 27 06:21:01 PM PDT 24
Finished Jul 27 06:21:35 PM PDT 24
Peak memory 191840 kb
Host smart-606ac6de-84ed-4de8-852f-0395b6a8896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895831089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1895831089
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1265907776
Short name T209
Test name
Test status
Simulation time 596440151 ps
CPU time 0.67 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 191772 kb
Host smart-a538abfb-2775-4223-88c4-3fd2bbbed630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265907776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1265907776
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3948178011
Short name T11
Test name
Test status
Simulation time 32052648192 ps
CPU time 11.91 seconds
Started Jul 27 06:20:58 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 196932 kb
Host smart-3e6755ca-49ed-4c67-b3d7-e193d3da376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948178011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3948178011
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.951379360
Short name T8
Test name
Test status
Simulation time 339454328 ps
CPU time 0.71 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 196552 kb
Host smart-42eb23d6-35c4-4c3e-906d-e228df3e770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951379360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.951379360
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.463494495
Short name T261
Test name
Test status
Simulation time 21824642918 ps
CPU time 31.6 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:21:32 PM PDT 24
Peak memory 191836 kb
Host smart-175d1242-5b44-4c5b-914a-551364c24de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463494495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.463494495
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1806397574
Short name T245
Test name
Test status
Simulation time 511182478 ps
CPU time 1.34 seconds
Started Jul 27 06:20:59 PM PDT 24
Finished Jul 27 06:21:00 PM PDT 24
Peak memory 196684 kb
Host smart-29a65b60-2f06-460e-900f-806117aa44b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806397574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1806397574
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4079626456
Short name T241
Test name
Test status
Simulation time 38502328940 ps
CPU time 50.57 seconds
Started Jul 27 06:21:00 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 191840 kb
Host smart-b03d71a9-6826-496f-b873-f80bc3cdd1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079626456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4079626456
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2010953646
Short name T204
Test name
Test status
Simulation time 504103329 ps
CPU time 0.66 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 196568 kb
Host smart-0f001637-b20f-47aa-962c-962a65c4b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010953646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2010953646
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.308579378
Short name T212
Test name
Test status
Simulation time 58039883719 ps
CPU time 39.81 seconds
Started Jul 27 06:20:56 PM PDT 24
Finished Jul 27 06:21:36 PM PDT 24
Peak memory 196856 kb
Host smart-bc2dbd46-bba8-4a42-87b5-fc72c671e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308579378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.308579378
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4001074127
Short name T225
Test name
Test status
Simulation time 468861797 ps
CPU time 1.26 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:58 PM PDT 24
Peak memory 196564 kb
Host smart-7d645910-327c-45e2-baa9-6faa04d4fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001074127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4001074127
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1108614413
Short name T183
Test name
Test status
Simulation time 474165793 ps
CPU time 0.81 seconds
Started Jul 27 06:21:09 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 196660 kb
Host smart-fe9578ce-d1de-4566-85a5-7d78df3d2549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108614413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1108614413
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2062895749
Short name T76
Test name
Test status
Simulation time 653490249 ps
CPU time 0.84 seconds
Started Jul 27 06:21:07 PM PDT 24
Finished Jul 27 06:21:08 PM PDT 24
Peak memory 191752 kb
Host smart-92651969-4980-4701-9aa0-114ebde0a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062895749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2062895749
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4125497981
Short name T285
Test name
Test status
Simulation time 553219349 ps
CPU time 0.72 seconds
Started Jul 27 06:20:57 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 196644 kb
Host smart-f54a819c-d31f-4a15-ae9b-6828fce60300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125497981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4125497981
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.748068586
Short name T254
Test name
Test status
Simulation time 27354062082 ps
CPU time 11.43 seconds
Started Jul 27 06:20:29 PM PDT 24
Finished Jul 27 06:20:40 PM PDT 24
Peak memory 191888 kb
Host smart-f1d6b060-a7da-4161-ae16-dc2f3d560a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748068586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.748068586
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3305366853
Short name T20
Test name
Test status
Simulation time 8018495707 ps
CPU time 11.79 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:39 PM PDT 24
Peak memory 215860 kb
Host smart-c983bb5b-3601-4963-a303-51eb143f2cf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305366853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3305366853
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2481577034
Short name T226
Test name
Test status
Simulation time 514225495 ps
CPU time 0.75 seconds
Started Jul 27 06:20:27 PM PDT 24
Finished Jul 27 06:20:28 PM PDT 24
Peak memory 191768 kb
Host smart-fdd10341-c86e-42ec-809d-88b537855166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481577034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2481577034
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2026639555
Short name T24
Test name
Test status
Simulation time 38989206821 ps
CPU time 54.71 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:22:03 PM PDT 24
Peak memory 191844 kb
Host smart-17f93785-1fab-4a51-8ebd-c2098380462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026639555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2026639555
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3683798488
Short name T274
Test name
Test status
Simulation time 495673468 ps
CPU time 0.74 seconds
Started Jul 27 06:21:09 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 191792 kb
Host smart-d449bc10-c1b1-4c8d-966f-947586ff7b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683798488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3683798488
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.583842386
Short name T253
Test name
Test status
Simulation time 5277236704 ps
CPU time 1.52 seconds
Started Jul 27 06:21:09 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 191812 kb
Host smart-d13bec97-9248-44b6-a71f-6d9ab775b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583842386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.583842386
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.632087236
Short name T247
Test name
Test status
Simulation time 508339944 ps
CPU time 0.91 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:09 PM PDT 24
Peak memory 191760 kb
Host smart-aa56f314-b8a2-4885-acb7-b6fc0abae3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632087236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.632087236
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3625882322
Short name T70
Test name
Test status
Simulation time 388937522 ps
CPU time 0.99 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:09 PM PDT 24
Peak memory 196552 kb
Host smart-6003123d-f842-4e18-bd85-c597fbbbb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625882322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3625882322
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2048539897
Short name T256
Test name
Test status
Simulation time 33401743529 ps
CPU time 12.15 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:20 PM PDT 24
Peak memory 191868 kb
Host smart-58a78492-8736-4770-83f0-55b27b58a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048539897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2048539897
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3699606612
Short name T246
Test name
Test status
Simulation time 548699391 ps
CPU time 1.35 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:10 PM PDT 24
Peak memory 196612 kb
Host smart-d64a5665-f1c5-4f81-84c1-8b85c3d56a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699606612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3699606612
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1816365539
Short name T25
Test name
Test status
Simulation time 466321020 ps
CPU time 1.28 seconds
Started Jul 27 06:21:07 PM PDT 24
Finished Jul 27 06:21:08 PM PDT 24
Peak memory 196540 kb
Host smart-eb16f9cf-2c12-40ee-addf-0cff9fa1cb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816365539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1816365539
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3089948141
Short name T213
Test name
Test status
Simulation time 36950249519 ps
CPU time 39.35 seconds
Started Jul 27 06:21:07 PM PDT 24
Finished Jul 27 06:21:46 PM PDT 24
Peak memory 191888 kb
Host smart-4c797215-fe24-41cb-b7e3-1b9fd4e538d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089948141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3089948141
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4028819842
Short name T278
Test name
Test status
Simulation time 565286862 ps
CPU time 0.87 seconds
Started Jul 27 06:21:08 PM PDT 24
Finished Jul 27 06:21:09 PM PDT 24
Peak memory 191752 kb
Host smart-318d423a-d408-422c-abd0-a09da5713734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028819842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4028819842
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4136235475
Short name T249
Test name
Test status
Simulation time 31336860850 ps
CPU time 12.72 seconds
Started Jul 27 06:21:20 PM PDT 24
Finished Jul 27 06:21:33 PM PDT 24
Peak memory 191876 kb
Host smart-264dbb58-5c32-4948-9912-02fc797d77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136235475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4136235475
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4008918170
Short name T280
Test name
Test status
Simulation time 374034180 ps
CPU time 1.07 seconds
Started Jul 27 06:21:20 PM PDT 24
Finished Jul 27 06:21:22 PM PDT 24
Peak memory 196572 kb
Host smart-394234c4-420a-41a7-ba80-84d17c41ea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008918170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4008918170
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2769274278
Short name T252
Test name
Test status
Simulation time 25233467306 ps
CPU time 15.17 seconds
Started Jul 27 06:21:19 PM PDT 24
Finished Jul 27 06:21:34 PM PDT 24
Peak memory 191872 kb
Host smart-51b5d5d6-b5ce-48d7-af37-858fe5291ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769274278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2769274278
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.162536888
Short name T263
Test name
Test status
Simulation time 531504368 ps
CPU time 0.68 seconds
Started Jul 27 06:21:19 PM PDT 24
Finished Jul 27 06:21:20 PM PDT 24
Peak memory 191736 kb
Host smart-8a298035-1d25-4656-8d29-6c2c945ba5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162536888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.162536888
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1026473
Short name T269
Test name
Test status
Simulation time 4032797818 ps
CPU time 3.03 seconds
Started Jul 27 06:21:24 PM PDT 24
Finished Jul 27 06:21:27 PM PDT 24
Peak memory 191836 kb
Host smart-8add082f-c291-44b2-9106-27797c21a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1026473
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1065350517
Short name T231
Test name
Test status
Simulation time 443615033 ps
CPU time 1.19 seconds
Started Jul 27 06:21:18 PM PDT 24
Finished Jul 27 06:21:20 PM PDT 24
Peak memory 196656 kb
Host smart-9c2f7dd5-c271-42c3-9529-a11fed962424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065350517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1065350517
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2415116823
Short name T270
Test name
Test status
Simulation time 13117167662 ps
CPU time 20.6 seconds
Started Jul 27 06:21:18 PM PDT 24
Finished Jul 27 06:21:39 PM PDT 24
Peak memory 196824 kb
Host smart-6c5715b2-c897-4436-8f3a-17137943d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415116823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2415116823
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.424897998
Short name T244
Test name
Test status
Simulation time 411786835 ps
CPU time 1.03 seconds
Started Jul 27 06:21:20 PM PDT 24
Finished Jul 27 06:21:21 PM PDT 24
Peak memory 191768 kb
Host smart-4ba8fc53-bbe7-4848-a5f6-e1dc1c0a99c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424897998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.424897998
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3763042101
Short name T5
Test name
Test status
Simulation time 15649651910 ps
CPU time 11.25 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:39 PM PDT 24
Peak memory 190984 kb
Host smart-2cce8c5b-6a9a-4ee3-b681-afecc19c0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763042101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3763042101
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.242347656
Short name T266
Test name
Test status
Simulation time 375291267 ps
CPU time 0.81 seconds
Started Jul 27 06:21:18 PM PDT 24
Finished Jul 27 06:21:19 PM PDT 24
Peak memory 191668 kb
Host smart-81b3f7cb-d030-4187-8e0f-6953d2935d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242347656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.242347656
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3045335066
Short name T230
Test name
Test status
Simulation time 23000577479 ps
CPU time 36.81 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:22:06 PM PDT 24
Peak memory 191792 kb
Host smart-dcde7792-8807-4efa-b958-989e10481e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045335066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3045335066
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2202973621
Short name T224
Test name
Test status
Simulation time 569100406 ps
CPU time 0.77 seconds
Started Jul 27 06:21:31 PM PDT 24
Finished Jul 27 06:21:32 PM PDT 24
Peak memory 196504 kb
Host smart-467784cd-5957-4e15-ae76-835828031452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202973621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2202973621
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_jump.715902639
Short name T191
Test name
Test status
Simulation time 596270916 ps
CPU time 1.1 seconds
Started Jul 27 06:20:42 PM PDT 24
Finished Jul 27 06:20:44 PM PDT 24
Peak memory 196668 kb
Host smart-da82fc79-a723-4e16-8ce4-e15b697f159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715902639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.715902639
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2360441678
Short name T206
Test name
Test status
Simulation time 6385995652 ps
CPU time 9.36 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:20:48 PM PDT 24
Peak memory 191884 kb
Host smart-097f9da5-b145-4dc8-bef4-ef1b4a13c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360441678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2360441678
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3300391268
Short name T17
Test name
Test status
Simulation time 4381698144 ps
CPU time 6.78 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:20:42 PM PDT 24
Peak memory 215928 kb
Host smart-43346ec9-2f6e-4b0b-ba82-a0fc729015f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300391268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3300391268
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.392792342
Short name T22
Test name
Test status
Simulation time 347487353 ps
CPU time 1.14 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:20:40 PM PDT 24
Peak memory 196616 kb
Host smart-12584c3f-a98a-40bc-8f8e-7eb7ade2d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392792342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.392792342
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3983408492
Short name T68
Test name
Test status
Simulation time 764937597 ps
CPU time 1.09 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:21:30 PM PDT 24
Peak memory 196456 kb
Host smart-6663c826-cb76-48d6-8f63-93b9f17fcb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983408492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3983408492
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.755810359
Short name T223
Test name
Test status
Simulation time 593862913 ps
CPU time 0.62 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:29 PM PDT 24
Peak memory 191760 kb
Host smart-db95829b-4ff6-492e-a4bc-7b56d86e3b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755810359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.755810359
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.503966322
Short name T84
Test name
Test status
Simulation time 39769877784 ps
CPU time 6.22 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:34 PM PDT 24
Peak memory 196896 kb
Host smart-addc6351-5b4c-4f2f-803e-82aba811171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503966322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.503966322
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1598434035
Short name T282
Test name
Test status
Simulation time 356409754 ps
CPU time 1.11 seconds
Started Jul 27 06:21:30 PM PDT 24
Finished Jul 27 06:21:31 PM PDT 24
Peak memory 191740 kb
Host smart-7236a3ef-b5e3-4da0-b190-a1e01e3bff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598434035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1598434035
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2990056378
Short name T257
Test name
Test status
Simulation time 23210142560 ps
CPU time 34.11 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:22:03 PM PDT 24
Peak memory 191872 kb
Host smart-5539c483-2e1a-44ce-af64-8ec75bd5a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990056378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2990056378
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3409378514
Short name T239
Test name
Test status
Simulation time 468318971 ps
CPU time 1.2 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:29 PM PDT 24
Peak memory 196548 kb
Host smart-cea79dcc-8c3a-4ba5-bbcb-093b216c79c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409378514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3409378514
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1788931630
Short name T268
Test name
Test status
Simulation time 32709531769 ps
CPU time 26.97 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:55 PM PDT 24
Peak memory 191856 kb
Host smart-f5702f3a-92e1-481f-92b9-fb141d63eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788931630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1788931630
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1693510040
Short name T276
Test name
Test status
Simulation time 626307927 ps
CPU time 0.69 seconds
Started Jul 27 06:21:27 PM PDT 24
Finished Jul 27 06:21:28 PM PDT 24
Peak memory 196548 kb
Host smart-561276d6-5fb1-416b-904c-d107c5bcebae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693510040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1693510040
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4084703734
Short name T271
Test name
Test status
Simulation time 59097914221 ps
CPU time 37.33 seconds
Started Jul 27 06:21:29 PM PDT 24
Finished Jul 27 06:22:07 PM PDT 24
Peak memory 191880 kb
Host smart-79a6affc-3181-4a86-a735-c87ec8426d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084703734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4084703734
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1477966850
Short name T238
Test name
Test status
Simulation time 378759665 ps
CPU time 0.8 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:21:29 PM PDT 24
Peak memory 191724 kb
Host smart-d49dcaac-64b6-401c-b410-aa2fa3cf78bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477966850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1477966850
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1718945476
Short name T250
Test name
Test status
Simulation time 29224351552 ps
CPU time 42.31 seconds
Started Jul 27 06:21:28 PM PDT 24
Finished Jul 27 06:22:11 PM PDT 24
Peak memory 196840 kb
Host smart-7666f1eb-4abb-4313-82fb-2cdf8582b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718945476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1718945476
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2383897294
Short name T203
Test name
Test status
Simulation time 360548581 ps
CPU time 0.7 seconds
Started Jul 27 06:21:32 PM PDT 24
Finished Jul 27 06:21:33 PM PDT 24
Peak memory 191752 kb
Host smart-e26cf26a-fe31-47b3-b17e-ee6c65c962d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383897294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2383897294
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1677431948
Short name T46
Test name
Test status
Simulation time 18988008173 ps
CPU time 2.13 seconds
Started Jul 27 06:21:44 PM PDT 24
Finished Jul 27 06:21:46 PM PDT 24
Peak memory 191844 kb
Host smart-bd68b4f6-b8f5-4d6b-9ef4-57afbb464395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677431948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1677431948
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1320916922
Short name T10
Test name
Test status
Simulation time 426720066 ps
CPU time 0.73 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:21:40 PM PDT 24
Peak memory 191792 kb
Host smart-62f127f7-1773-4d7f-9957-e0694bafbad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320916922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1320916922
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.391130571
Short name T232
Test name
Test status
Simulation time 35792070339 ps
CPU time 56.33 seconds
Started Jul 27 06:21:39 PM PDT 24
Finished Jul 27 06:22:35 PM PDT 24
Peak memory 196860 kb
Host smart-37431f0e-8c54-47d1-be1b-a4e5c2ab3b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391130571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.391130571
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1537792519
Short name T260
Test name
Test status
Simulation time 473050994 ps
CPU time 0.63 seconds
Started Jul 27 06:21:42 PM PDT 24
Finished Jul 27 06:21:42 PM PDT 24
Peak memory 191772 kb
Host smart-d6b08140-ef97-4566-b5ef-6f16e5c5e9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537792519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1537792519
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2641063830
Short name T177
Test name
Test status
Simulation time 64378796547 ps
CPU time 505.92 seconds
Started Jul 27 06:21:38 PM PDT 24
Finished Jul 27 06:30:05 PM PDT 24
Peak memory 213876 kb
Host smart-f3102c6d-f98f-4376-90f7-47b7c5ec7042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641063830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2641063830
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.963445704
Short name T233
Test name
Test status
Simulation time 32626963687 ps
CPU time 9.95 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:21:50 PM PDT 24
Peak memory 191900 kb
Host smart-4d5735d0-9614-4836-9093-f78561861db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963445704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.963445704
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2007201927
Short name T258
Test name
Test status
Simulation time 394083923 ps
CPU time 1.12 seconds
Started Jul 27 06:21:38 PM PDT 24
Finished Jul 27 06:21:39 PM PDT 24
Peak memory 191720 kb
Host smart-c7f7b4eb-9bba-44cc-b50b-e4d8cc3b24aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007201927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2007201927
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2886754114
Short name T242
Test name
Test status
Simulation time 11097727976 ps
CPU time 7.68 seconds
Started Jul 27 06:21:37 PM PDT 24
Finished Jul 27 06:21:45 PM PDT 24
Peak memory 191876 kb
Host smart-14ce4da6-456a-4597-a462-f4b7698c41c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886754114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2886754114
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.976671012
Short name T235
Test name
Test status
Simulation time 401480501 ps
CPU time 0.74 seconds
Started Jul 27 06:21:40 PM PDT 24
Finished Jul 27 06:21:41 PM PDT 24
Peak memory 191768 kb
Host smart-d2017bdc-2e6d-491c-9885-9fa34191f76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976671012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.976671012
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3121155233
Short name T23
Test name
Test status
Simulation time 639531590 ps
CPU time 0.74 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:20:39 PM PDT 24
Peak memory 196596 kb
Host smart-4eec5493-99e6-421a-8eae-0009173fe098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121155233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3121155233
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3099515482
Short name T215
Test name
Test status
Simulation time 5052223754 ps
CPU time 8.13 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:20:44 PM PDT 24
Peak memory 196800 kb
Host smart-a67102fb-cd10-4b61-ae4f-585f94e6b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099515482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3099515482
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3405408754
Short name T243
Test name
Test status
Simulation time 539527805 ps
CPU time 0.62 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:20:37 PM PDT 24
Peak memory 196556 kb
Host smart-24e79db9-cf72-4894-84f1-3e3821449900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405408754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3405408754
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1165823220
Short name T100
Test name
Test status
Simulation time 14998592054 ps
CPU time 111.32 seconds
Started Jul 27 06:20:37 PM PDT 24
Finished Jul 27 06:22:28 PM PDT 24
Peak memory 206624 kb
Host smart-c4835762-312c-4c41-ba39-64535e942eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165823220 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1165823220
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3938177460
Short name T277
Test name
Test status
Simulation time 55116976995 ps
CPU time 20.01 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:20:55 PM PDT 24
Peak memory 191804 kb
Host smart-09a93006-e01e-403c-83b2-bffce5a464cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938177460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3938177460
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2582988100
Short name T218
Test name
Test status
Simulation time 398851646 ps
CPU time 1.18 seconds
Started Jul 27 06:20:34 PM PDT 24
Finished Jul 27 06:20:35 PM PDT 24
Peak memory 191776 kb
Host smart-3d922428-2f8e-4e23-8765-e36ca3b9ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582988100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2582988100
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.576106681
Short name T283
Test name
Test status
Simulation time 28624521441 ps
CPU time 37.09 seconds
Started Jul 27 06:20:45 PM PDT 24
Finished Jul 27 06:21:22 PM PDT 24
Peak memory 191828 kb
Host smart-7763c58e-88cd-42b6-9d52-702382a014cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576106681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.576106681
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.812982884
Short name T234
Test name
Test status
Simulation time 486532670 ps
CPU time 0.73 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:20:37 PM PDT 24
Peak memory 191732 kb
Host smart-7fade687-1925-4bea-8ccc-8b4adcdfb2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812982884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.812982884
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2782451274
Short name T284
Test name
Test status
Simulation time 10433334585 ps
CPU time 1.41 seconds
Started Jul 27 06:20:35 PM PDT 24
Finished Jul 27 06:20:37 PM PDT 24
Peak memory 191872 kb
Host smart-efa9d105-fafe-4947-9c66-4e253ccd3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782451274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2782451274
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2898506167
Short name T255
Test name
Test status
Simulation time 371328441 ps
CPU time 0.74 seconds
Started Jul 27 06:20:44 PM PDT 24
Finished Jul 27 06:20:45 PM PDT 24
Peak memory 196492 kb
Host smart-7dd8a447-a04f-4ff4-ab67-44ccbd8e9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898506167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2898506167
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1360123769
Short name T262
Test name
Test status
Simulation time 12701128309 ps
CPU time 18.55 seconds
Started Jul 27 06:20:39 PM PDT 24
Finished Jul 27 06:20:57 PM PDT 24
Peak memory 191848 kb
Host smart-354d633f-8b5b-4e7a-9a14-bf25a405f99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360123769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1360123769
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2324082227
Short name T30
Test name
Test status
Simulation time 386350233 ps
CPU time 0.7 seconds
Started Jul 27 06:20:36 PM PDT 24
Finished Jul 27 06:20:37 PM PDT 24
Peak memory 191756 kb
Host smart-eecce3ea-0335-4825-be5b-9dc33650ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324082227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2324082227
Directory /workspace/9.aon_timer_smoke/latest
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