Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26486	1		T2	10		T3	12		T4	12
bark[1]	506	1		T48	21		T123	21		T110	21
bark[2]	336	1		T9	14		T19	120		T142	21
bark[3]	791	1		T46	111		T116	14		T51	114
bark[4]	520	1		T1	14		T17	83		T46	21
bark[5]	509	1		T14	21		T123	21		T142	100
bark[6]	733	1		T12	14		T14	21		T36	14
bark[7]	493	1		T11	14		T176	14		T200	21
bark[8]	625	1		T93	26		T47	56		T104	150
bark[9]	619	1		T17	21		T47	275		T160	14
bark[10]	926	1		T49	21		T51	21		T173	14
bark[11]	627	1		T17	35		T97	21		T171	50
bark[12]	172	1		T19	5		T130	21		T105	21
bark[13]	572	1		T37	21		T169	21		T163	58
bark[14]	233	1		T14	21		T95	14		T142	35
bark[15]	1113	1		T14	21		T38	281		T47	304
bark[16]	487	1		T14	38		T37	21		T18	26
bark[17]	460	1		T149	14		T49	71		T148	72
bark[18]	261	1		T14	21		T35	14		T49	21
bark[19]	811	1		T7	21		T37	21		T19	21
bark[20]	446	1		T49	26		T104	21		T145	21
bark[21]	198	1		T171	30		T202	14		T49	35
bark[22]	438	1		T7	21		T51	279		T111	21
bark[23]	303	1		T97	30		T156	14		T38	21
bark[24]	520	1		T19	26		T49	21		T51	5
bark[25]	573	1		T8	21		T17	26		T97	21
bark[26]	460	1		T7	21		T55	14		T169	72
bark[27]	404	1		T46	21		T142	240		T203	14
bark[28]	330	1		T19	14		T51	26		T169	26
bark[29]	897	1		T97	21		T51	83		T113	14
bark[30]	509	1		T52	14		T47	21		T123	157
bark[31]	117	1		T5	14		T14	40		T93	21
bark_0	4583	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26586	1		T2	9		T3	11		T4	11
bite[1]	173	1		T52	13		T111	21		T161	21
bite[2]	134	1		T156	13		T113	13		T161	21
bite[3]	737	1		T5	13		T14	21		T37	21
bite[4]	136	1		T14	21		T17	21		T38	26
bite[5]	303	1		T19	26		T110	21		T104	21
bite[6]	414	1		T14	21		T35	13		T46	21
bite[7]	511	1		T17	25		T93	21		T176	13
bite[8]	647	1		T47	309		T49	21		T190	13
bite[9]	512	1		T97	21		T149	13		T116	13
bite[10]	903	1		T38	341		T50	6		T123	21
bite[11]	890	1		T14	38		T110	22		T155	13
bite[12]	357	1		T17	35		T49	21		T57	21
bite[13]	607	1		T36	13		T19	119		T104	6
bite[14]	683	1		T142	21		T110	13		T130	42
bite[15]	955	1		T14	21		T123	94		T104	42
bite[16]	394	1		T47	21		T51	113		T110	100
bite[17]	532	1		T104	149		T141	30		T118	42
bite[18]	326	1		T1	13		T9	13		T18	26
bite[19]	504	1		T17	82		T123	42		T101	21
bite[20]	680	1		T7	21		T37	21		T48	42
bite[21]	596	1		T38	280		T171	49		T123	21
bite[22]	460	1		T7	21		T46	21		T203	13
bite[23]	505	1		T12	13		T19	21		T97	21
bite[24]	544	1		T11	13		T14	40		T93	21
bite[25]	291	1		T7	21		T37	21		T55	13
bite[26]	141	1		T8	21		T97	30		T171	30
bite[27]	517	1		T14	21		T49	21		T157	26
bite[28]	588	1		T46	257		T202	13		T169	127
bite[29]	735	1		T93	26		T126	39		T47	21
bite[30]	204	1		T47	21		T169	21		T170	13
bite[31]	535	1		T95	13		T46	110		T200	21
bite_0	4958	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40803	1		T1	21		T2	17		T3	19
auto[1]	6255	1		T7	46		T8	59		T14	41

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1345	1		T19	19		T200	42		T171	23
prescale[1]	899	1		T8	28		T37	28		T54	9
prescale[2]	1359	1		T19	23		T46	19		T38	19
prescale[3]	1009	1		T17	2		T19	19		T38	19
prescale[4]	747	1		T16	9		T17	2		T53	9
prescale[5]	458	1		T46	61		T126	19		T51	24
prescale[6]	745	1		T8	19		T37	40		T38	23
prescale[7]	718	1		T17	71		T94	9		T46	33
prescale[8]	797	1		T18	2		T19	2		T38	78
prescale[9]	721	1		T4	9		T38	19		T47	161
prescale[10]	416	1		T7	40		T47	50		T49	4
prescale[11]	329	1		T38	74		T171	28		T49	2
prescale[12]	592	1		T47	132		T209	9		T169	70
prescale[13]	636	1		T7	19		T14	47		T38	78
prescale[14]	957	1		T7	49		T14	47		T17	2
prescale[15]	987	1		T7	28		T19	2		T47	24
prescale[16]	787	1		T13	9		T100	9		T46	4
prescale[17]	447	1		T19	2		T47	19		T48	4
prescale[18]	461	1		T3	9		T126	23		T47	92
prescale[19]	578	1		T17	19		T19	2		T38	40
prescale[20]	674	1		T8	19		T19	2		T38	24
prescale[21]	357	1		T8	24		T18	2		T200	50
prescale[22]	408	1		T46	2		T47	9		T50	36
prescale[23]	611	1		T17	21		T98	9		T48	21
prescale[24]	799	1		T126	28		T47	11		T123	85
prescale[25]	500	1		T17	19		T38	122		T47	83
prescale[26]	532	1		T18	19		T93	18		T38	40
prescale[27]	1319	1		T97	23		T46	24		T200	19
prescale[28]	945	1		T18	2		T49	30		T50	66
prescale[29]	921	1		T97	9		T38	35		T49	4
prescale[30]	765	1		T7	19		T46	48		T210	9
prescale[31]	834	1		T8	38		T46	2		T126	61
prescale_0	23405	1		T1	21		T2	17		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34221	1		T1	9		T2	17		T3	9
auto[1]	12837	1		T1	12		T3	10		T6	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	47058	1		T1	21		T2	17		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27308	1		T1	1		T2	12		T3	14
wkup[1]	200	1		T8	21		T49	21		T101	21
wkup[2]	138	1		T17	21		T46	21		T27	21
wkup[3]	238	1		T7	30		T156	15		T38	29
wkup[4]	457	1		T14	21		T97	21		T51	21
wkup[5]	191	1		T93	21		T51	21		T123	21
wkup[6]	272	1		T48	21		T123	30		T30	21
wkup[7]	193	1		T123	47		T110	21		T30	36
wkup[8]	350	1		T37	21		T19	30		T38	21
wkup[9]	274	1		T51	42		T123	21		T124	30
wkup[10]	213	1		T142	21		T173	15		T104	21
wkup[11]	327	1		T47	21		T110	21		T104	19
wkup[12]	270	1		T47	21		T142	21		T110	30
wkup[13]	243	1		T14	21		T19	21		T46	45
wkup[14]	246	1		T93	21		T101	21		T110	21
wkup[15]	314	1		T7	21		T47	21		T142	51
wkup[16]	257	1		T19	21		T47	21		T101	21
wkup[17]	192	1		T51	21		T101	21		T169	26
wkup[18]	152	1		T38	21		T110	21		T111	21
wkup[19]	126	1		T113	15		T142	21		T179	42
wkup[20]	308	1		T37	21		T123	21		T151	15
wkup[21]	314	1		T19	26		T126	21		T123	21
wkup[22]	346	1		T14	21		T17	35		T38	21
wkup[23]	167	1		T142	42		T163	26		T33	21
wkup[24]	285	1		T97	21		T51	26		T123	44
wkup[25]	213	1		T17	21		T19	21		T97	21
wkup[26]	207	1		T11	15		T38	21		T51	6
wkup[27]	321	1		T47	26		T101	21		T169	21
wkup[28]	312	1		T46	21		T126	21		T194	15
wkup[29]	272	1		T123	21		T101	21		T110	60
wkup[30]	278	1		T37	21		T18	26		T47	21
wkup[31]	344	1		T19	6		T47	21		T51	21
wkup[32]	180	1		T12	15		T37	21		T144	15
wkup[33]	231	1		T50	21		T51	21		T142	21
wkup[34]	272	1		T47	21		T202	21		T123	21
wkup[35]	253	1		T48	21		T51	26		T123	21
wkup[36]	281	1		T36	15		T38	21		T51	21
wkup[37]	213	1		T200	21		T202	15		T110	53
wkup[38]	314	1		T19	15		T171	21		T105	21
wkup[39]	171	1		T5	15		T14	21		T52	15
wkup[40]	265	1		T37	26		T46	21		T49	21
wkup[41]	385	1		T14	21		T47	21		T190	15
wkup[42]	385	1		T17	40		T19	21		T46	21
wkup[43]	331	1		T17	15		T48	21		T110	91
wkup[44]	317	1		T7	21		T93	21		T47	35
wkup[45]	184	1		T46	21		T47	21		T123	21
wkup[46]	224	1		T46	21		T47	21		T169	21
wkup[47]	340	1		T46	21		T47	21		T51	21
wkup[48]	201	1		T101	21		T169	21		T142	26
wkup[49]	188	1		T163	26		T161	21		T158	21
wkup[50]	268	1		T49	21		T51	31		T169	21
wkup[51]	340	1		T17	21		T55	15		T38	44
wkup[52]	221	1		T17	21		T47	21		T51	21
wkup[53]	204	1		T19	21		T149	15		T51	21
wkup[54]	167	1		T1	15		T14	21		T47	21
wkup[55]	198	1		T14	21		T35	15		T38	21
wkup[56]	332	1		T7	21		T38	51		T47	21
wkup[57]	256	1		T19	8		T97	30		T176	15
wkup[58]	450	1		T14	21		T46	51		T48	21
wkup[59]	193	1		T9	15		T38	21		T51	21
wkup[60]	183	1		T51	21		T157	15		T105	21
wkup[61]	80	1		T49	26		T110	24		T160	15
wkup[62]	254	1		T95	15		T126	21		T49	21
wkup[63]	249	1		T47	26		T142	30		T130	21
wkup_0	3600	1		T1	5		T2	5		T3	5