Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.93 99.33 93.67 100.00 98.40 99.51 48.66


Total test records in report: 421
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T285 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2715220460 Jul 28 06:20:38 PM PDT 24 Jul 28 06:20:40 PM PDT 24 502398397 ps
T286 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1105014594 Jul 28 06:19:55 PM PDT 24 Jul 28 06:19:57 PM PDT 24 649606842 ps
T287 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.504764136 Jul 28 06:21:31 PM PDT 24 Jul 28 06:21:32 PM PDT 24 461294167 ps
T288 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2289981087 Jul 28 06:21:29 PM PDT 24 Jul 28 06:21:32 PM PDT 24 583683339 ps
T289 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.451854945 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:45 PM PDT 24 398210997 ps
T290 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4181966914 Jul 28 06:20:10 PM PDT 24 Jul 28 06:20:11 PM PDT 24 379838399 ps
T67 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2454689048 Jul 28 06:21:27 PM PDT 24 Jul 28 06:21:28 PM PDT 24 279550539 ps
T291 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1637862395 Jul 28 06:21:56 PM PDT 24 Jul 28 06:21:57 PM PDT 24 297016451 ps
T292 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3166615091 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:44 PM PDT 24 588233371 ps
T45 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1495363467 Jul 28 06:20:20 PM PDT 24 Jul 28 06:20:21 PM PDT 24 456858114 ps
T293 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2595661331 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:02 PM PDT 24 536006237 ps
T41 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3434514319 Jul 28 06:20:20 PM PDT 24 Jul 28 06:20:21 PM PDT 24 356840702 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.965491849 Jul 28 06:20:07 PM PDT 24 Jul 28 06:20:16 PM PDT 24 11613504236 ps
T294 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2232642119 Jul 28 06:20:45 PM PDT 24 Jul 28 06:20:46 PM PDT 24 569557884 ps
T42 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3063220815 Jul 28 06:21:26 PM PDT 24 Jul 28 06:21:34 PM PDT 24 4707384628 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4288434642 Jul 28 06:20:04 PM PDT 24 Jul 28 06:20:05 PM PDT 24 523992573 ps
T70 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2782369801 Jul 28 06:21:20 PM PDT 24 Jul 28 06:21:21 PM PDT 24 461928394 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.545464114 Jul 28 06:19:47 PM PDT 24 Jul 28 06:19:47 PM PDT 24 517668730 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1853460730 Jul 28 06:20:31 PM PDT 24 Jul 28 06:20:32 PM PDT 24 528969868 ps
T87 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1442937083 Jul 28 06:20:56 PM PDT 24 Jul 28 06:20:58 PM PDT 24 492913431 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2466191867 Jul 28 06:21:12 PM PDT 24 Jul 28 06:21:13 PM PDT 24 362998740 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1137270477 Jul 28 06:20:16 PM PDT 24 Jul 28 06:20:17 PM PDT 24 337606383 ps
T297 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3944248836 Jul 28 06:20:52 PM PDT 24 Jul 28 06:20:53 PM PDT 24 438308323 ps
T211 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3632875436 Jul 28 06:21:39 PM PDT 24 Jul 28 06:21:40 PM PDT 24 321235600 ps
T298 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2283524194 Jul 28 06:21:58 PM PDT 24 Jul 28 06:21:59 PM PDT 24 493667947 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1631905316 Jul 28 06:20:41 PM PDT 24 Jul 28 06:20:42 PM PDT 24 522010911 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3467800301 Jul 28 06:20:22 PM PDT 24 Jul 28 06:20:23 PM PDT 24 640724440 ps
T88 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1165534070 Jul 28 06:20:51 PM PDT 24 Jul 28 06:20:53 PM PDT 24 1003792000 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2196605746 Jul 28 06:21:31 PM PDT 24 Jul 28 06:21:32 PM PDT 24 460204894 ps
T301 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2368314673 Jul 28 06:20:46 PM PDT 24 Jul 28 06:20:47 PM PDT 24 358504478 ps
T302 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.842568351 Jul 28 06:21:22 PM PDT 24 Jul 28 06:21:23 PM PDT 24 366989024 ps
T212 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1261403814 Jul 28 06:20:48 PM PDT 24 Jul 28 06:20:49 PM PDT 24 415714785 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3666433886 Jul 28 06:21:11 PM PDT 24 Jul 28 06:21:12 PM PDT 24 348138852 ps
T89 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4072382119 Jul 28 06:21:22 PM PDT 24 Jul 28 06:21:23 PM PDT 24 2345669201 ps
T304 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1906939545 Jul 28 06:21:59 PM PDT 24 Jul 28 06:22:00 PM PDT 24 407969875 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2924944522 Jul 28 06:20:30 PM PDT 24 Jul 28 06:20:35 PM PDT 24 6200942691 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.939132195 Jul 28 06:21:33 PM PDT 24 Jul 28 06:21:36 PM PDT 24 534055021 ps
T43 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.559141717 Jul 28 06:19:42 PM PDT 24 Jul 28 06:19:48 PM PDT 24 8068471921 ps
T44 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1217968815 Jul 28 06:21:19 PM PDT 24 Jul 28 06:21:26 PM PDT 24 8395795304 ps
T306 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2365717956 Jul 28 06:21:05 PM PDT 24 Jul 28 06:21:06 PM PDT 24 359459620 ps
T307 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2182903734 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:01 PM PDT 24 577773074 ps
T308 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1576756891 Jul 28 06:21:54 PM PDT 24 Jul 28 06:21:54 PM PDT 24 623258247 ps
T90 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.978943027 Jul 28 06:21:36 PM PDT 24 Jul 28 06:21:38 PM PDT 24 2683919567 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.919065353 Jul 28 06:21:34 PM PDT 24 Jul 28 06:21:35 PM PDT 24 483429540 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2769878824 Jul 28 06:20:26 PM PDT 24 Jul 28 06:20:29 PM PDT 24 9051067606 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3082640294 Jul 28 06:20:26 PM PDT 24 Jul 28 06:20:28 PM PDT 24 447248589 ps
T312 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3722445434 Jul 28 06:21:45 PM PDT 24 Jul 28 06:21:45 PM PDT 24 469439872 ps
T313 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1228517746 Jul 28 06:21:10 PM PDT 24 Jul 28 06:21:11 PM PDT 24 530863542 ps
T314 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3098339831 Jul 28 06:21:36 PM PDT 24 Jul 28 06:21:37 PM PDT 24 474965324 ps
T315 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2044129011 Jul 28 06:22:02 PM PDT 24 Jul 28 06:22:03 PM PDT 24 313668372 ps
T316 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2708837207 Jul 28 06:21:38 PM PDT 24 Jul 28 06:21:40 PM PDT 24 493443913 ps
T91 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.241645555 Jul 28 06:21:25 PM PDT 24 Jul 28 06:21:26 PM PDT 24 1174638730 ps
T92 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3727503776 Jul 28 06:20:24 PM PDT 24 Jul 28 06:20:27 PM PDT 24 2779423153 ps
T317 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4097104365 Jul 28 06:21:39 PM PDT 24 Jul 28 06:21:41 PM PDT 24 471174273 ps
T318 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.670009419 Jul 28 06:21:43 PM PDT 24 Jul 28 06:21:44 PM PDT 24 299572884 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2798718339 Jul 28 06:21:35 PM PDT 24 Jul 28 06:21:36 PM PDT 24 338977160 ps
T320 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1751741876 Jul 28 06:19:55 PM PDT 24 Jul 28 06:19:56 PM PDT 24 354368728 ps
T321 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1899840181 Jul 28 06:20:45 PM PDT 24 Jul 28 06:20:46 PM PDT 24 1247956263 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1633310022 Jul 28 06:20:56 PM PDT 24 Jul 28 06:20:57 PM PDT 24 420979507 ps
T323 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2104006723 Jul 28 06:21:48 PM PDT 24 Jul 28 06:21:49 PM PDT 24 302075940 ps
T204 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.890801266 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:08 PM PDT 24 4432633495 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3835866405 Jul 28 06:21:26 PM PDT 24 Jul 28 06:21:27 PM PDT 24 371690720 ps
T205 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2083538154 Jul 28 06:20:57 PM PDT 24 Jul 28 06:21:03 PM PDT 24 7988480615 ps
T325 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1846678750 Jul 28 06:21:26 PM PDT 24 Jul 28 06:21:27 PM PDT 24 317766245 ps
T326 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2698250787 Jul 28 06:21:58 PM PDT 24 Jul 28 06:21:59 PM PDT 24 381250528 ps
T327 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4146794134 Jul 28 06:19:42 PM PDT 24 Jul 28 06:19:43 PM PDT 24 376261821 ps
T328 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1517544756 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:45 PM PDT 24 419626116 ps
T206 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1225072864 Jul 28 06:21:41 PM PDT 24 Jul 28 06:21:54 PM PDT 24 7950739771 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.346670296 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:02 PM PDT 24 505893355 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.747412897 Jul 28 06:21:13 PM PDT 24 Jul 28 06:21:15 PM PDT 24 3906758297 ps
T331 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2996154111 Jul 28 06:21:47 PM PDT 24 Jul 28 06:21:48 PM PDT 24 295936963 ps
T332 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.349802226 Jul 28 06:20:26 PM PDT 24 Jul 28 06:20:27 PM PDT 24 287530440 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3037414800 Jul 28 06:20:06 PM PDT 24 Jul 28 06:20:07 PM PDT 24 505998888 ps
T334 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2546290341 Jul 28 06:21:58 PM PDT 24 Jul 28 06:21:58 PM PDT 24 451716413 ps
T207 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1608853952 Jul 28 06:20:55 PM PDT 24 Jul 28 06:20:58 PM PDT 24 8121561583 ps
T335 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2901273962 Jul 28 06:21:47 PM PDT 24 Jul 28 06:21:49 PM PDT 24 334944399 ps
T336 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2462711507 Jul 28 06:20:42 PM PDT 24 Jul 28 06:20:45 PM PDT 24 1105812091 ps
T337 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1226803067 Jul 28 06:21:29 PM PDT 24 Jul 28 06:21:33 PM PDT 24 2394323080 ps
T338 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1507799609 Jul 28 06:21:26 PM PDT 24 Jul 28 06:21:27 PM PDT 24 478545926 ps
T339 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3993868876 Jul 28 06:21:56 PM PDT 24 Jul 28 06:21:57 PM PDT 24 491143973 ps
T340 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1063778480 Jul 28 06:20:51 PM PDT 24 Jul 28 06:20:52 PM PDT 24 554506661 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4229543531 Jul 28 06:21:38 PM PDT 24 Jul 28 06:21:40 PM PDT 24 421592949 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2504587811 Jul 28 06:21:41 PM PDT 24 Jul 28 06:21:42 PM PDT 24 294738686 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2980240569 Jul 28 06:19:39 PM PDT 24 Jul 28 06:19:41 PM PDT 24 705770428 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3422644564 Jul 28 06:20:22 PM PDT 24 Jul 28 06:20:29 PM PDT 24 14257810687 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.322603558 Jul 28 06:20:57 PM PDT 24 Jul 28 06:20:58 PM PDT 24 1244139294 ps
T346 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.356457852 Jul 28 06:21:41 PM PDT 24 Jul 28 06:21:42 PM PDT 24 395008277 ps
T80 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2965959496 Jul 28 06:21:40 PM PDT 24 Jul 28 06:21:41 PM PDT 24 349347604 ps
T347 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1888772230 Jul 28 06:21:10 PM PDT 24 Jul 28 06:21:15 PM PDT 24 3014600404 ps
T75 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3490715107 Jul 28 06:21:34 PM PDT 24 Jul 28 06:21:35 PM PDT 24 423830677 ps
T348 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1417518630 Jul 28 06:21:07 PM PDT 24 Jul 28 06:21:09 PM PDT 24 3999098225 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3979877000 Jul 28 06:21:30 PM PDT 24 Jul 28 06:21:31 PM PDT 24 504789636 ps
T81 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1723839924 Jul 28 06:19:47 PM PDT 24 Jul 28 06:19:49 PM PDT 24 632066352 ps
T350 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2033861122 Jul 28 06:21:35 PM PDT 24 Jul 28 06:21:39 PM PDT 24 2086554044 ps
T351 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3893410290 Jul 28 06:19:52 PM PDT 24 Jul 28 06:19:59 PM PDT 24 2742216600 ps
T352 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3774364764 Jul 28 06:20:15 PM PDT 24 Jul 28 06:20:21 PM PDT 24 3631459311 ps
T353 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2051975929 Jul 28 06:21:14 PM PDT 24 Jul 28 06:21:16 PM PDT 24 682351290 ps
T82 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3385817168 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:02 PM PDT 24 463143331 ps
T354 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2513141076 Jul 28 06:21:31 PM PDT 24 Jul 28 06:21:32 PM PDT 24 457639497 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.211304063 Jul 28 06:20:17 PM PDT 24 Jul 28 06:20:18 PM PDT 24 455307185 ps
T356 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.434199010 Jul 28 06:21:51 PM PDT 24 Jul 28 06:21:52 PM PDT 24 493701306 ps
T357 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.196937337 Jul 28 06:21:47 PM PDT 24 Jul 28 06:21:48 PM PDT 24 414465407 ps
T208 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2494915614 Jul 28 06:20:38 PM PDT 24 Jul 28 06:20:41 PM PDT 24 8617624515 ps
T358 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3977118250 Jul 28 06:21:03 PM PDT 24 Jul 28 06:21:04 PM PDT 24 401000017 ps
T359 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1605483842 Jul 28 06:20:56 PM PDT 24 Jul 28 06:20:58 PM PDT 24 447591075 ps
T360 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2060441986 Jul 28 06:20:59 PM PDT 24 Jul 28 06:21:00 PM PDT 24 472205693 ps
T361 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.634776885 Jul 28 06:21:24 PM PDT 24 Jul 28 06:21:25 PM PDT 24 285429357 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3899948380 Jul 28 06:21:25 PM PDT 24 Jul 28 06:21:26 PM PDT 24 298229415 ps
T363 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.395843740 Jul 28 06:21:47 PM PDT 24 Jul 28 06:21:48 PM PDT 24 338108437 ps
T364 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2196757330 Jul 28 06:21:54 PM PDT 24 Jul 28 06:21:55 PM PDT 24 289162007 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.32326396 Jul 28 06:20:41 PM PDT 24 Jul 28 06:20:43 PM PDT 24 515094344 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2116097617 Jul 28 06:20:40 PM PDT 24 Jul 28 06:20:41 PM PDT 24 736174859 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3814364612 Jul 28 06:21:06 PM PDT 24 Jul 28 06:21:07 PM PDT 24 482692213 ps
T368 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3241543819 Jul 28 06:21:34 PM PDT 24 Jul 28 06:21:35 PM PDT 24 508138656 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3630503830 Jul 28 06:20:10 PM PDT 24 Jul 28 06:20:11 PM PDT 24 1146746442 ps
T370 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3217517081 Jul 28 06:21:25 PM PDT 24 Jul 28 06:21:27 PM PDT 24 4155773073 ps
T371 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4051660710 Jul 28 06:20:39 PM PDT 24 Jul 28 06:20:40 PM PDT 24 265686775 ps
T372 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1647057768 Jul 28 06:20:57 PM PDT 24 Jul 28 06:20:58 PM PDT 24 541201997 ps
T373 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1469839359 Jul 28 06:21:47 PM PDT 24 Jul 28 06:21:48 PM PDT 24 329726590 ps
T374 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3250029135 Jul 28 06:21:22 PM PDT 24 Jul 28 06:21:24 PM PDT 24 679917222 ps
T76 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3340006567 Jul 28 06:19:47 PM PDT 24 Jul 28 06:19:52 PM PDT 24 8060248333 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3005633446 Jul 28 06:20:00 PM PDT 24 Jul 28 06:20:01 PM PDT 24 510016755 ps
T376 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2839610437 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:09 PM PDT 24 2348705255 ps
T377 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3371830114 Jul 28 06:20:58 PM PDT 24 Jul 28 06:21:00 PM PDT 24 1422664089 ps
T378 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.536167594 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:45 PM PDT 24 389483784 ps
T379 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.987852708 Jul 28 06:21:58 PM PDT 24 Jul 28 06:21:59 PM PDT 24 425662745 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2004115961 Jul 28 06:19:39 PM PDT 24 Jul 28 06:19:40 PM PDT 24 508563477 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3200294739 Jul 28 06:21:32 PM PDT 24 Jul 28 06:21:36 PM PDT 24 2302789759 ps
T382 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3004052791 Jul 28 06:21:29 PM PDT 24 Jul 28 06:21:31 PM PDT 24 507738129 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3644464773 Jul 28 06:20:05 PM PDT 24 Jul 28 06:20:06 PM PDT 24 749064871 ps
T384 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1884138536 Jul 28 06:19:50 PM PDT 24 Jul 28 06:19:51 PM PDT 24 820471463 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1433767558 Jul 28 06:21:35 PM PDT 24 Jul 28 06:21:36 PM PDT 24 383753412 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1348095826 Jul 28 06:20:29 PM PDT 24 Jul 28 06:20:30 PM PDT 24 491331282 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2988763932 Jul 28 06:20:34 PM PDT 24 Jul 28 06:20:37 PM PDT 24 1846161985 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.101346346 Jul 28 06:21:20 PM PDT 24 Jul 28 06:21:21 PM PDT 24 2502464421 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1027606101 Jul 28 06:20:29 PM PDT 24 Jul 28 06:20:30 PM PDT 24 388385423 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4029909345 Jul 28 06:20:21 PM PDT 24 Jul 28 06:20:22 PM PDT 24 844426418 ps
T391 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3957556499 Jul 28 06:21:56 PM PDT 24 Jul 28 06:21:57 PM PDT 24 389058686 ps
T392 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.850655929 Jul 28 06:21:00 PM PDT 24 Jul 28 06:21:02 PM PDT 24 452926690 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3961458953 Jul 28 06:21:14 PM PDT 24 Jul 28 06:21:15 PM PDT 24 436431331 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1411436883 Jul 28 06:20:01 PM PDT 24 Jul 28 06:20:08 PM PDT 24 4219776036 ps
T395 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.334946430 Jul 28 06:20:15 PM PDT 24 Jul 28 06:20:16 PM PDT 24 401676889 ps
T396 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2563309926 Jul 28 06:21:06 PM PDT 24 Jul 28 06:21:06 PM PDT 24 392686175 ps
T397 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1450531057 Jul 28 06:21:26 PM PDT 24 Jul 28 06:21:27 PM PDT 24 443331939 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2767902997 Jul 28 06:21:42 PM PDT 24 Jul 28 06:21:46 PM PDT 24 1576089947 ps
T399 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.735055806 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:45 PM PDT 24 281584692 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2424688199 Jul 28 06:21:06 PM PDT 24 Jul 28 06:21:07 PM PDT 24 565374645 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2592687118 Jul 28 06:21:30 PM PDT 24 Jul 28 06:21:32 PM PDT 24 4539028727 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1471202059 Jul 28 06:20:26 PM PDT 24 Jul 28 06:20:26 PM PDT 24 356269944 ps
T403 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1433436918 Jul 28 06:21:31 PM PDT 24 Jul 28 06:21:38 PM PDT 24 4024756243 ps
T404 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1438582890 Jul 28 06:21:21 PM PDT 24 Jul 28 06:21:23 PM PDT 24 442580971 ps
T405 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.951119303 Jul 28 06:20:47 PM PDT 24 Jul 28 06:20:48 PM PDT 24 373074336 ps
T77 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2963760075 Jul 28 06:19:47 PM PDT 24 Jul 28 06:19:48 PM PDT 24 402690764 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3698999979 Jul 28 06:21:10 PM PDT 24 Jul 28 06:21:11 PM PDT 24 1066782926 ps
T407 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3408535182 Jul 28 06:21:44 PM PDT 24 Jul 28 06:21:45 PM PDT 24 460962717 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2142113060 Jul 28 06:21:35 PM PDT 24 Jul 28 06:21:39 PM PDT 24 8458820969 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3658339111 Jul 28 06:20:46 PM PDT 24 Jul 28 06:20:54 PM PDT 24 4293148340 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2371500315 Jul 28 06:20:26 PM PDT 24 Jul 28 06:20:28 PM PDT 24 596352543 ps
T78 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4195621845 Jul 28 06:20:45 PM PDT 24 Jul 28 06:20:47 PM PDT 24 1163407236 ps
T411 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2113929629 Jul 28 06:21:22 PM PDT 24 Jul 28 06:21:23 PM PDT 24 428986193 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2513014968 Jul 28 06:20:30 PM PDT 24 Jul 28 06:20:31 PM PDT 24 485490668 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1827140421 Jul 28 06:21:34 PM PDT 24 Jul 28 06:21:36 PM PDT 24 480706637 ps
T414 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.896602350 Jul 28 06:20:52 PM PDT 24 Jul 28 06:20:54 PM PDT 24 463014059 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3532581335 Jul 28 06:20:09 PM PDT 24 Jul 28 06:20:10 PM PDT 24 596683739 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.976658225 Jul 28 06:21:35 PM PDT 24 Jul 28 06:21:36 PM PDT 24 4759086192 ps
T416 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2826197104 Jul 28 06:21:12 PM PDT 24 Jul 28 06:21:14 PM PDT 24 401640554 ps
T417 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1963874991 Jul 28 06:21:58 PM PDT 24 Jul 28 06:21:59 PM PDT 24 284015154 ps
T418 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2252238561 Jul 28 06:21:01 PM PDT 24 Jul 28 06:21:03 PM PDT 24 4244414769 ps
T419 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2403709614 Jul 28 06:21:54 PM PDT 24 Jul 28 06:21:55 PM PDT 24 432808835 ps
T420 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1505899607 Jul 28 06:21:33 PM PDT 24 Jul 28 06:21:34 PM PDT 24 457672545 ps
T421 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3570429266 Jul 28 06:20:36 PM PDT 24 Jul 28 06:20:37 PM PDT 24 426945302 ps

Test location /workspace/coverage/default/3.aon_timer_stress_all.3401370193
Short name T7
Test name
Test status
Simulation time 222835540935 ps
CPU time 83.51 seconds
Started Jul 28 06:22:10 PM PDT 24
Finished Jul 28 06:23:34 PM PDT 24
Peak memory 198160 kb
Host smart-3110f6cb-bdd7-4a1a-abec-3c92277362c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401370193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3401370193
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1987679320
Short name T47
Test name
Test status
Simulation time 393354251841 ps
CPU time 665.07 seconds
Started Jul 28 06:23:32 PM PDT 24
Finished Jul 28 06:34:37 PM PDT 24
Peak memory 214304 kb
Host smart-823db0c5-ba31-407b-a83f-8562f24bef15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987679320 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1987679320
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3063220815
Short name T42
Test name
Test status
Simulation time 4707384628 ps
CPU time 8.13 seconds
Started Jul 28 06:21:26 PM PDT 24
Finished Jul 28 06:21:34 PM PDT 24
Peak memory 198560 kb
Host smart-d5b9cb52-ba0b-408d-bcf1-bfa34fbb34b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063220815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3063220815
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3640802180
Short name T19
Test name
Test status
Simulation time 33555587757 ps
CPU time 214.66 seconds
Started Jul 28 06:23:48 PM PDT 24
Finished Jul 28 06:27:22 PM PDT 24
Peak memory 198388 kb
Host smart-624d85df-a533-4600-b33c-353661ee6df8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640802180 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3640802180
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2303715379
Short name T66
Test name
Test status
Simulation time 795405460085 ps
CPU time 582.86 seconds
Started Jul 28 06:24:14 PM PDT 24
Finished Jul 28 06:33:57 PM PDT 24
Peak memory 204564 kb
Host smart-cab45da1-0f8f-441b-b798-6f9c47d8839c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303715379 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2303715379
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.284540309
Short name T110
Test name
Test status
Simulation time 332387928454 ps
CPU time 233.71 seconds
Started Jul 28 06:23:22 PM PDT 24
Finished Jul 28 06:27:16 PM PDT 24
Peak memory 213844 kb
Host smart-6e93ed5e-b801-46f1-97d2-47be3b2a4ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284540309 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.284540309
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1521190915
Short name T114
Test name
Test status
Simulation time 82849701691 ps
CPU time 452.85 seconds
Started Jul 28 06:24:24 PM PDT 24
Finished Jul 28 06:31:57 PM PDT 24
Peak memory 211440 kb
Host smart-2382c073-bb6c-49ec-9e84-ac3ba75c0b6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521190915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1521190915
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.860002441
Short name T51
Test name
Test status
Simulation time 253359243069 ps
CPU time 439.77 seconds
Started Jul 28 06:22:32 PM PDT 24
Finished Jul 28 06:29:52 PM PDT 24
Peak memory 211348 kb
Host smart-c548508f-e2a5-4764-8f5a-ec90a4003313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860002441 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.860002441
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3891118144
Short name T104
Test name
Test status
Simulation time 250754415691 ps
CPU time 467.67 seconds
Started Jul 28 06:23:42 PM PDT 24
Finished Jul 28 06:31:29 PM PDT 24
Peak memory 211376 kb
Host smart-c89494f7-143d-43f3-8e15-df3bbd2ea53f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891118144 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3891118144
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3914747590
Short name T14
Test name
Test status
Simulation time 233511265129 ps
CPU time 153.17 seconds
Started Jul 28 06:22:03 PM PDT 24
Finished Jul 28 06:24:36 PM PDT 24
Peak memory 191828 kb
Host smart-3d2e8472-2da1-4cf7-8c4f-835973b6d246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914747590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3914747590
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4170115945
Short name T57
Test name
Test status
Simulation time 214863673171 ps
CPU time 644.75 seconds
Started Jul 28 06:22:20 PM PDT 24
Finished Jul 28 06:33:05 PM PDT 24
Peak memory 214192 kb
Host smart-0bc245a5-293f-4484-a5c7-4f6661666a8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170115945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4170115945
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3265394951
Short name T24
Test name
Test status
Simulation time 3987840992 ps
CPU time 2.39 seconds
Started Jul 28 06:22:04 PM PDT 24
Finished Jul 28 06:22:06 PM PDT 24
Peak memory 215344 kb
Host smart-2b961aaa-1b37-4b28-8973-00ea76846351
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265394951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3265394951
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2991694812
Short name T133
Test name
Test status
Simulation time 53782587333 ps
CPU time 286.37 seconds
Started Jul 28 06:22:08 PM PDT 24
Finished Jul 28 06:26:55 PM PDT 24
Peak memory 199220 kb
Host smart-7d6dde47-aba2-4d2d-a5b2-4bf630c73bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991694812 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2991694812
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2747863433
Short name T168
Test name
Test status
Simulation time 232329518896 ps
CPU time 428.91 seconds
Started Jul 28 06:22:19 PM PDT 24
Finished Jul 28 06:29:28 PM PDT 24
Peak memory 211028 kb
Host smart-fff40662-9507-45a9-b81d-60ff9307a87a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747863433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2747863433
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3217481535
Short name T49
Test name
Test status
Simulation time 39019827518 ps
CPU time 436.14 seconds
Started Jul 28 06:22:20 PM PDT 24
Finished Jul 28 06:29:37 PM PDT 24
Peak memory 208496 kb
Host smart-f490afc0-5863-4100-b88b-7894e9d56a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217481535 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3217481535
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2043949257
Short name T115
Test name
Test status
Simulation time 99845059907 ps
CPU time 419.69 seconds
Started Jul 28 06:22:38 PM PDT 24
Finished Jul 28 06:29:38 PM PDT 24
Peak memory 211136 kb
Host smart-127df52f-a79f-4ba3-8758-b3cdb8bcafc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043949257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2043949257
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2694464214
Short name T129
Test name
Test status
Simulation time 468677378552 ps
CPU time 616.16 seconds
Started Jul 28 06:22:56 PM PDT 24
Finished Jul 28 06:33:12 PM PDT 24
Peak memory 192872 kb
Host smart-21dbefe9-9633-45f3-a54a-e29be35fdec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694464214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2694464214
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2765153132
Short name T136
Test name
Test status
Simulation time 35565412501 ps
CPU time 377.06 seconds
Started Jul 28 06:23:04 PM PDT 24
Finished Jul 28 06:29:21 PM PDT 24
Peak memory 214340 kb
Host smart-14732e89-e834-47ba-85d5-6a36ff1843a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765153132 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2765153132
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4015463283
Short name T142
Test name
Test status
Simulation time 124021829364 ps
CPU time 495.67 seconds
Started Jul 28 06:23:13 PM PDT 24
Finished Jul 28 06:31:29 PM PDT 24
Peak memory 212280 kb
Host smart-1669bbc2-afce-430c-b25b-f0df43809abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015463283 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4015463283
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2781540228
Short name T146
Test name
Test status
Simulation time 61639083450 ps
CPU time 575.75 seconds
Started Jul 28 06:24:10 PM PDT 24
Finished Jul 28 06:33:46 PM PDT 24
Peak memory 211316 kb
Host smart-eceded61-7967-49b0-883a-cf0b9c72814c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781540228 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2781540228
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2215935595
Short name T130
Test name
Test status
Simulation time 70101471552 ps
CPU time 23.84 seconds
Started Jul 28 06:23:33 PM PDT 24
Finished Jul 28 06:23:57 PM PDT 24
Peak memory 192516 kb
Host smart-eacaf3f4-5511-4921-8aac-d5fcccedf9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215935595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2215935595
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.223861389
Short name T117
Test name
Test status
Simulation time 213467779221 ps
CPU time 166.27 seconds
Started Jul 28 06:23:40 PM PDT 24
Finished Jul 28 06:26:26 PM PDT 24
Peak memory 198180 kb
Host smart-a9b0175b-020e-4d9c-b01d-52375fe0df41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223861389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.223861389
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2377759319
Short name T105
Test name
Test status
Simulation time 88312460998 ps
CPU time 442.68 seconds
Started Jul 28 06:22:53 PM PDT 24
Finished Jul 28 06:30:16 PM PDT 24
Peak memory 202992 kb
Host smart-768fcc9a-bfde-471c-a70e-51f848d35c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377759319 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2377759319
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1149575449
Short name T148
Test name
Test status
Simulation time 239048923620 ps
CPU time 29.57 seconds
Started Jul 28 06:24:15 PM PDT 24
Finished Jul 28 06:24:45 PM PDT 24
Peak memory 192840 kb
Host smart-800979e3-f7a2-4075-abd0-1051b2be6af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149575449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1149575449
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1067943453
Short name T101
Test name
Test status
Simulation time 82941663335 ps
CPU time 286.79 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:26:56 PM PDT 24
Peak memory 208584 kb
Host smart-fd5170c1-ff37-4e1d-a0fb-39a6acff296e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067943453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1067943453
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2592224176
Short name T111
Test name
Test status
Simulation time 29667344964 ps
CPU time 41.16 seconds
Started Jul 28 06:22:54 PM PDT 24
Finished Jul 28 06:23:35 PM PDT 24
Peak memory 192972 kb
Host smart-68facbb4-2a37-4d25-9194-c1afadf4a396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592224176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2592224176
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3594002406
Short name T123
Test name
Test status
Simulation time 64823851907 ps
CPU time 708.97 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:35:16 PM PDT 24
Peak memory 213584 kb
Host smart-61d4ba0c-c2ae-4418-bbad-c7f48722ac42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594002406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3594002406
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2235531683
Short name T30
Test name
Test status
Simulation time 43769536465 ps
CPU time 321.8 seconds
Started Jul 28 06:22:53 PM PDT 24
Finished Jul 28 06:28:15 PM PDT 24
Peak memory 206832 kb
Host smart-edc49c0e-861c-472a-8657-e8946f8752da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235531683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2235531683
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1040218688
Short name T175
Test name
Test status
Simulation time 108245711909 ps
CPU time 167.15 seconds
Started Jul 28 06:22:43 PM PDT 24
Finished Jul 28 06:25:30 PM PDT 24
Peak memory 207780 kb
Host smart-4b22e106-5933-4261-91ac-8dbfe12a9d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040218688 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1040218688
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2329310960
Short name T93
Test name
Test status
Simulation time 57246916840 ps
CPU time 34.33 seconds
Started Jul 28 06:23:14 PM PDT 24
Finished Jul 28 06:23:48 PM PDT 24
Peak memory 198184 kb
Host smart-baa194f2-7eab-40b3-8387-a4d7ab1e2419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329310960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2329310960
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1853460730
Short name T71
Test name
Test status
Simulation time 528969868 ps
CPU time 0.92 seconds
Started Jul 28 06:20:31 PM PDT 24
Finished Jul 28 06:20:32 PM PDT 24
Peak memory 193648 kb
Host smart-3bdd1c4c-ab3a-498b-81a7-00a7d8ba5049
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853460730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1853460730
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.965137896
Short name T17
Test name
Test status
Simulation time 10167207513 ps
CPU time 75.09 seconds
Started Jul 28 06:22:48 PM PDT 24
Finished Jul 28 06:24:04 PM PDT 24
Peak memory 198420 kb
Host smart-6fc599a3-fdda-4a96-92b4-2ce1fa705906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965137896 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.965137896
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3548561474
Short name T124
Test name
Test status
Simulation time 267913853160 ps
CPU time 183.49 seconds
Started Jul 28 06:23:00 PM PDT 24
Finished Jul 28 06:26:03 PM PDT 24
Peak memory 206568 kb
Host smart-d7d40413-4cb1-4d34-ba4b-9bbf7458c5ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548561474 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3548561474
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3428391344
Short name T121
Test name
Test status
Simulation time 173756424276 ps
CPU time 64.24 seconds
Started Jul 28 06:23:31 PM PDT 24
Finished Jul 28 06:24:35 PM PDT 24
Peak memory 198180 kb
Host smart-fa430bee-fa2d-4efa-90da-b494ab12e1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428391344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3428391344
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2137891368
Short name T141
Test name
Test status
Simulation time 135817192982 ps
CPU time 106.68 seconds
Started Jul 28 06:23:51 PM PDT 24
Finished Jul 28 06:25:38 PM PDT 24
Peak memory 191768 kb
Host smart-822de255-53f2-4e3c-afd5-11e3bc98d52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137891368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2137891368
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2027032878
Short name T145
Test name
Test status
Simulation time 57133502225 ps
CPU time 42.44 seconds
Started Jul 28 06:24:25 PM PDT 24
Finished Jul 28 06:25:08 PM PDT 24
Peak memory 198208 kb
Host smart-3e00630d-7c8b-4d96-b54e-4163e9e42720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027032878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2027032878
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1308626754
Short name T140
Test name
Test status
Simulation time 49862891885 ps
CPU time 22.13 seconds
Started Jul 28 06:22:50 PM PDT 24
Finished Jul 28 06:23:12 PM PDT 24
Peak memory 198212 kb
Host smart-8461771d-a5cc-4ab2-b585-c482639cdfe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308626754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1308626754
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2132236488
Short name T139
Test name
Test status
Simulation time 184023027583 ps
CPU time 223.37 seconds
Started Jul 28 06:24:03 PM PDT 24
Finished Jul 28 06:27:46 PM PDT 24
Peak memory 192816 kb
Host smart-81000a0f-d011-4fec-9e2e-75415d62c10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132236488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2132236488
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3579495286
Short name T25
Test name
Test status
Simulation time 63936202855 ps
CPU time 99.94 seconds
Started Jul 28 06:22:18 PM PDT 24
Finished Jul 28 06:23:58 PM PDT 24
Peak memory 198172 kb
Host smart-7b24fec9-55b0-4529-8b56-21b50c1c8ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579495286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3579495286
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1314483030
Short name T138
Test name
Test status
Simulation time 39392057587 ps
CPU time 113.33 seconds
Started Jul 28 06:22:33 PM PDT 24
Finished Jul 28 06:24:26 PM PDT 24
Peak memory 206624 kb
Host smart-97af7270-0060-4f9b-8bc3-7b65f634eceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314483030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1314483030
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1134769440
Short name T157
Test name
Test status
Simulation time 72410806095 ps
CPU time 434.93 seconds
Started Jul 28 06:22:52 PM PDT 24
Finished Jul 28 06:30:07 PM PDT 24
Peak memory 200344 kb
Host smart-0e4b0bf9-e5cc-48cc-a34f-03df3dd41ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134769440 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1134769440
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.951323351
Short name T137
Test name
Test status
Simulation time 42350216845 ps
CPU time 62.02 seconds
Started Jul 28 06:22:19 PM PDT 24
Finished Jul 28 06:23:21 PM PDT 24
Peak memory 198224 kb
Host smart-610a292a-6695-4f91-99d9-88108e97d08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951323351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.951323351
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3221265220
Short name T46
Test name
Test status
Simulation time 51338231054 ps
CPU time 192.06 seconds
Started Jul 28 06:23:53 PM PDT 24
Finished Jul 28 06:27:05 PM PDT 24
Peak memory 206656 kb
Host smart-00b98ed3-56c8-4f35-9971-0b9564cc7207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221265220 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3221265220
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.314299209
Short name T179
Test name
Test status
Simulation time 15154591968 ps
CPU time 116.71 seconds
Started Jul 28 06:24:01 PM PDT 24
Finished Jul 28 06:25:58 PM PDT 24
Peak memory 198432 kb
Host smart-53fcb034-4e5b-4a94-8c7d-120fa6ab0930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314299209 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.314299209
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2294988156
Short name T97
Test name
Test status
Simulation time 63503460939 ps
CPU time 20.57 seconds
Started Jul 28 06:22:40 PM PDT 24
Finished Jul 28 06:23:01 PM PDT 24
Peak memory 184080 kb
Host smart-e8892692-1db5-4ea9-b1e1-4eb248f94d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294988156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2294988156
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.109737653
Short name T169
Test name
Test status
Simulation time 27061050553 ps
CPU time 289.88 seconds
Started Jul 28 06:23:16 PM PDT 24
Finished Jul 28 06:28:06 PM PDT 24
Peak memory 198460 kb
Host smart-c858aa59-f5f5-42d8-85c1-86806b810096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109737653 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.109737653
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3391047857
Short name T107
Test name
Test status
Simulation time 244592172939 ps
CPU time 314 seconds
Started Jul 28 06:23:22 PM PDT 24
Finished Jul 28 06:28:36 PM PDT 24
Peak memory 198216 kb
Host smart-1e21c965-43ea-4161-afd2-ba20e8233a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391047857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3391047857
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4163973974
Short name T134
Test name
Test status
Simulation time 75450650609 ps
CPU time 28.21 seconds
Started Jul 28 06:23:41 PM PDT 24
Finished Jul 28 06:24:09 PM PDT 24
Peak memory 191816 kb
Host smart-921e438d-6b32-417d-b10a-a8b083a0a1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163973974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4163973974
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2723167299
Short name T131
Test name
Test status
Simulation time 222073705686 ps
CPU time 87.46 seconds
Started Jul 28 06:23:08 PM PDT 24
Finished Jul 28 06:24:36 PM PDT 24
Peak memory 191844 kb
Host smart-3049de30-e00d-4bd4-94a6-94b3d5ecf1bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723167299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2723167299
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1086405834
Short name T150
Test name
Test status
Simulation time 38448669376 ps
CPU time 145.88 seconds
Started Jul 28 06:23:27 PM PDT 24
Finished Jul 28 06:25:53 PM PDT 24
Peak memory 213840 kb
Host smart-1e5f4db8-5a21-4d3b-b88f-1e6f28524220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086405834 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1086405834
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2999133504
Short name T112
Test name
Test status
Simulation time 122918731362 ps
CPU time 76.9 seconds
Started Jul 28 06:23:34 PM PDT 24
Finished Jul 28 06:24:51 PM PDT 24
Peak memory 191856 kb
Host smart-c5446774-eb9b-4132-b85b-cc02e401dd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999133504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2999133504
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3174982788
Short name T163
Test name
Test status
Simulation time 53861359168 ps
CPU time 19.85 seconds
Started Jul 28 06:22:03 PM PDT 24
Finished Jul 28 06:22:23 PM PDT 24
Peak memory 198128 kb
Host smart-780e1643-4078-4d06-a042-2f40d0a7a2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174982788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3174982788
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2510838789
Short name T118
Test name
Test status
Simulation time 143262186011 ps
CPU time 69.91 seconds
Started Jul 28 06:22:52 PM PDT 24
Finished Jul 28 06:24:02 PM PDT 24
Peak memory 198172 kb
Host smart-c87466dd-3479-4f41-b35e-12928612c75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510838789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2510838789
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.765536347
Short name T36
Test name
Test status
Simulation time 402236085 ps
CPU time 1.18 seconds
Started Jul 28 06:24:07 PM PDT 24
Finished Jul 28 06:24:08 PM PDT 24
Peak memory 196484 kb
Host smart-bf8fc011-5f5d-431c-a7d0-9d0c667542ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765536347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.765536347
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1060058530
Short name T102
Test name
Test status
Simulation time 86950740973 ps
CPU time 341.56 seconds
Started Jul 28 06:22:22 PM PDT 24
Finished Jul 28 06:28:04 PM PDT 24
Peak memory 213152 kb
Host smart-bc2cc9a3-5db0-477b-952b-a58d9edf5dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060058530 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1060058530
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2370980469
Short name T154
Test name
Test status
Simulation time 3990367260 ps
CPU time 2.36 seconds
Started Jul 28 06:23:18 PM PDT 24
Finished Jul 28 06:23:20 PM PDT 24
Peak memory 198124 kb
Host smart-b3a680cb-9271-40e4-a929-81af6901a472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370980469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2370980469
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.42576476
Short name T37
Test name
Test status
Simulation time 23249651217 ps
CPU time 10.11 seconds
Started Jul 28 06:22:08 PM PDT 24
Finished Jul 28 06:22:18 PM PDT 24
Peak memory 192348 kb
Host smart-eef4e79c-c24b-4287-8cae-a39a84ed8a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all
.42576476
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3700724062
Short name T135
Test name
Test status
Simulation time 93684267379 ps
CPU time 136.38 seconds
Started Jul 28 06:22:48 PM PDT 24
Finished Jul 28 06:25:05 PM PDT 24
Peak memory 191844 kb
Host smart-f37ec808-a217-4dc3-8c1d-39388aa0706d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700724062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3700724062
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1669349521
Short name T109
Test name
Test status
Simulation time 526368982561 ps
CPU time 106.92 seconds
Started Jul 28 06:23:57 PM PDT 24
Finished Jul 28 06:25:44 PM PDT 24
Peak memory 198180 kb
Host smart-c27ae2b9-df90-496f-af89-644997530787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669349521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1669349521
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4026904466
Short name T38
Test name
Test status
Simulation time 171199536021 ps
CPU time 286.33 seconds
Started Jul 28 06:22:44 PM PDT 24
Finished Jul 28 06:27:31 PM PDT 24
Peak memory 213384 kb
Host smart-e91822dc-66cd-4b24-b381-028689797d23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026904466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4026904466
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2823622437
Short name T147
Test name
Test status
Simulation time 151586467775 ps
CPU time 14.42 seconds
Started Jul 28 06:22:48 PM PDT 24
Finished Jul 28 06:23:03 PM PDT 24
Peak memory 191856 kb
Host smart-6fcc525d-e6a5-4aee-a73f-7578cceb3f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823622437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2823622437
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.117261320
Short name T172
Test name
Test status
Simulation time 68501124486 ps
CPU time 53.33 seconds
Started Jul 28 06:24:12 PM PDT 24
Finished Jul 28 06:25:05 PM PDT 24
Peak memory 191796 kb
Host smart-c975f63d-29b5-4ad4-b17f-fafa9ad22421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117261320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.117261320
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.668842657
Short name T108
Test name
Test status
Simulation time 27007685410 ps
CPU time 38.97 seconds
Started Jul 28 06:22:32 PM PDT 24
Finished Jul 28 06:23:11 PM PDT 24
Peak memory 192856 kb
Host smart-e4bda537-c98f-4e35-8c24-0cb5b0edce29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668842657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.668842657
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3204377804
Short name T160
Test name
Test status
Simulation time 536481224 ps
CPU time 1.39 seconds
Started Jul 28 06:22:02 PM PDT 24
Finished Jul 28 06:22:03 PM PDT 24
Peak memory 196572 kb
Host smart-356bd478-8afa-476d-bc84-9a118a45c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204377804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3204377804
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.87293512
Short name T158
Test name
Test status
Simulation time 104164704708 ps
CPU time 399.65 seconds
Started Jul 28 06:22:02 PM PDT 24
Finished Jul 28 06:28:41 PM PDT 24
Peak memory 210916 kb
Host smart-5cdd0138-6c0b-4b62-b288-a8347595fb83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87293512 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.87293512
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3839527004
Short name T159
Test name
Test status
Simulation time 367657523 ps
CPU time 1.07 seconds
Started Jul 28 06:22:43 PM PDT 24
Finished Jul 28 06:22:44 PM PDT 24
Peak memory 196556 kb
Host smart-9e84f7e6-3993-42f2-b06e-2ccf6faa2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839527004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3839527004
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3508254010
Short name T127
Test name
Test status
Simulation time 125301148069 ps
CPU time 191.16 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:25:20 PM PDT 24
Peak memory 191844 kb
Host smart-24c919f8-3520-461d-b672-729225b5a3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508254010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3508254010
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3586137286
Short name T185
Test name
Test status
Simulation time 152740165526 ps
CPU time 224.69 seconds
Started Jul 28 06:23:08 PM PDT 24
Finished Jul 28 06:26:53 PM PDT 24
Peak memory 200652 kb
Host smart-a8fa2467-3a08-4b2d-b751-801d94da91a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586137286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3586137286
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1695536930
Short name T52
Test name
Test status
Simulation time 449828251 ps
CPU time 0.73 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:23:27 PM PDT 24
Peak memory 196620 kb
Host smart-6e5f1dab-b981-42f2-aefa-b943df156772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695536930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1695536930
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4168187891
Short name T113
Test name
Test status
Simulation time 467595746 ps
CPU time 1.23 seconds
Started Jul 28 06:24:01 PM PDT 24
Finished Jul 28 06:24:02 PM PDT 24
Peak memory 196632 kb
Host smart-aa091348-8f52-48c9-8bb7-1aaf885e4ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168187891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4168187891
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.289671616
Short name T167
Test name
Test status
Simulation time 220284645237 ps
CPU time 78.24 seconds
Started Jul 28 06:24:04 PM PDT 24
Finished Jul 28 06:25:22 PM PDT 24
Peak memory 198172 kb
Host smart-a8766999-5330-4a15-8db5-5f045c89f2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289671616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.289671616
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.640194085
Short name T164
Test name
Test status
Simulation time 408110363 ps
CPU time 0.71 seconds
Started Jul 28 06:22:55 PM PDT 24
Finished Jul 28 06:22:56 PM PDT 24
Peak memory 196488 kb
Host smart-ce8ce9bf-39c2-4353-af6c-bd38ca1392dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640194085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.640194085
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1596629646
Short name T120
Test name
Test status
Simulation time 84745506691 ps
CPU time 21 seconds
Started Jul 28 06:23:04 PM PDT 24
Finished Jul 28 06:23:25 PM PDT 24
Peak memory 191788 kb
Host smart-eed8117c-fe1a-4980-8ff6-78cac11c4837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596629646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1596629646
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2830299419
Short name T161
Test name
Test status
Simulation time 80475504511 ps
CPU time 54.2 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:24:20 PM PDT 24
Peak memory 184080 kb
Host smart-ffa4f4c9-f846-425e-bc48-39a4cdabac95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830299419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2830299419
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1704252644
Short name T143
Test name
Test status
Simulation time 345039817 ps
CPU time 0.98 seconds
Started Jul 28 06:23:45 PM PDT 24
Finished Jul 28 06:23:46 PM PDT 24
Peak memory 196600 kb
Host smart-7a304fe2-103f-4998-ba5b-f46e8539d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704252644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1704252644
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1728674156
Short name T152
Test name
Test status
Simulation time 493407083 ps
CPU time 1.3 seconds
Started Jul 28 06:22:13 PM PDT 24
Finished Jul 28 06:22:15 PM PDT 24
Peak memory 196536 kb
Host smart-a173cc36-40d0-4bba-949d-ffe9fea5dc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728674156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1728674156
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3100834448
Short name T27
Test name
Test status
Simulation time 165980708610 ps
CPU time 49.46 seconds
Started Jul 28 06:22:24 PM PDT 24
Finished Jul 28 06:23:13 PM PDT 24
Peak memory 198144 kb
Host smart-05604322-2c6a-4105-86bb-01b6b267c137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100834448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3100834448
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3708590965
Short name T128
Test name
Test status
Simulation time 39379138276 ps
CPU time 5.74 seconds
Started Jul 28 06:22:28 PM PDT 24
Finished Jul 28 06:22:34 PM PDT 24
Peak memory 192412 kb
Host smart-dd25bc53-2339-41d1-9a68-7f7398d6d721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708590965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3708590965
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.498054205
Short name T165
Test name
Test status
Simulation time 104360135042 ps
CPU time 68.99 seconds
Started Jul 28 06:22:58 PM PDT 24
Finished Jul 28 06:24:07 PM PDT 24
Peak memory 191772 kb
Host smart-8a8d7790-d98d-4f65-8882-3189dabf3469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498054205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.498054205
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.752300966
Short name T132
Test name
Test status
Simulation time 445222356 ps
CPU time 1.24 seconds
Started Jul 28 06:23:17 PM PDT 24
Finished Jul 28 06:23:18 PM PDT 24
Peak memory 196540 kb
Host smart-37bb434b-841a-4d41-8213-ffa8f15ed1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752300966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.752300966
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3592048922
Short name T171
Test name
Test status
Simulation time 89666290670 ps
CPU time 67.64 seconds
Started Jul 28 06:23:47 PM PDT 24
Finished Jul 28 06:24:55 PM PDT 24
Peak memory 192932 kb
Host smart-9376c901-d866-4177-b8f5-3aa4d95d249a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592048922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3592048922
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2977443407
Short name T180
Test name
Test status
Simulation time 209759380867 ps
CPU time 167.8 seconds
Started Jul 28 06:23:53 PM PDT 24
Finished Jul 28 06:26:41 PM PDT 24
Peak memory 198172 kb
Host smart-77fe7f46-2c34-49a7-bdd7-ca19a6cf556f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977443407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2977443407
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.32135667
Short name T103
Test name
Test status
Simulation time 80246106664 ps
CPU time 136.83 seconds
Started Jul 28 06:24:21 PM PDT 24
Finished Jul 28 06:26:38 PM PDT 24
Peak memory 198448 kb
Host smart-27cafd81-59e1-4205-889a-f4db6e1e7d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32135667 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.32135667
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.337037792
Short name T119
Test name
Test status
Simulation time 6705283407 ps
CPU time 1.64 seconds
Started Jul 28 06:22:29 PM PDT 24
Finished Jul 28 06:22:31 PM PDT 24
Peak memory 198200 kb
Host smart-e0bd44d6-49df-4265-b119-d6982516200d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337037792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.337037792
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3422764785
Short name T181
Test name
Test status
Simulation time 215284291516 ps
CPU time 80.52 seconds
Started Jul 28 06:22:44 PM PDT 24
Finished Jul 28 06:24:05 PM PDT 24
Peak memory 184412 kb
Host smart-3c5efde3-7ca9-4add-8b7c-2816ee32358b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422764785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3422764785
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3631302552
Short name T116
Test name
Test status
Simulation time 394673465 ps
CPU time 0.7 seconds
Started Jul 28 06:23:41 PM PDT 24
Finished Jul 28 06:23:42 PM PDT 24
Peak memory 196536 kb
Host smart-17b5ab11-da43-4c7c-9820-920d4208e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631302552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3631302552
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2502547114
Short name T48
Test name
Test status
Simulation time 146829784656 ps
CPU time 290.61 seconds
Started Jul 28 06:23:41 PM PDT 24
Finished Jul 28 06:28:32 PM PDT 24
Peak memory 201332 kb
Host smart-7eafd6e2-c454-45bd-a5c1-686510db056a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502547114 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2502547114
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2182327319
Short name T178
Test name
Test status
Simulation time 15753714901 ps
CPU time 130.5 seconds
Started Jul 28 06:24:01 PM PDT 24
Finished Jul 28 06:26:12 PM PDT 24
Peak memory 206628 kb
Host smart-c2938196-3619-4527-9568-a7cfc3daf32e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182327319 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2182327319
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1763406921
Short name T155
Test name
Test status
Simulation time 425154212 ps
CPU time 0.71 seconds
Started Jul 28 06:22:20 PM PDT 24
Finished Jul 28 06:22:21 PM PDT 24
Peak memory 196544 kb
Host smart-3109701c-1ad8-40c5-89cc-7a3375c905e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763406921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1763406921
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1680312513
Short name T35
Test name
Test status
Simulation time 421966006 ps
CPU time 0.75 seconds
Started Jul 28 06:21:59 PM PDT 24
Finished Jul 28 06:22:00 PM PDT 24
Peak memory 196516 kb
Host smart-cf7aae2d-0864-493d-834e-a765a7d118e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680312513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1680312513
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.426485438
Short name T61
Test name
Test status
Simulation time 80938462084 ps
CPU time 177.18 seconds
Started Jul 28 06:22:02 PM PDT 24
Finished Jul 28 06:24:59 PM PDT 24
Peak memory 207596 kb
Host smart-4ec115a6-85aa-4478-bcbb-a2fa7f6b784d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426485438 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.426485438
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2310293434
Short name T153
Test name
Test status
Simulation time 113294105424 ps
CPU time 46.49 seconds
Started Jul 28 06:22:40 PM PDT 24
Finished Jul 28 06:23:27 PM PDT 24
Peak memory 191792 kb
Host smart-afb5a684-a9f0-415a-a610-6354a3d31132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310293434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2310293434
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1727186106
Short name T125
Test name
Test status
Simulation time 498708864 ps
CPU time 0.78 seconds
Started Jul 28 06:22:39 PM PDT 24
Finished Jul 28 06:22:40 PM PDT 24
Peak memory 196508 kb
Host smart-a60ae207-c729-4983-867b-3ce4cb7292e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727186106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1727186106
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1951564261
Short name T162
Test name
Test status
Simulation time 584131042 ps
CPU time 1.09 seconds
Started Jul 28 06:22:56 PM PDT 24
Finished Jul 28 06:22:57 PM PDT 24
Peak memory 196568 kb
Host smart-06300484-4b19-4c8e-bf7c-302ee4f81587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951564261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1951564261
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.395528145
Short name T60
Test name
Test status
Simulation time 59138540602 ps
CPU time 186.53 seconds
Started Jul 28 06:23:22 PM PDT 24
Finished Jul 28 06:26:29 PM PDT 24
Peak memory 214400 kb
Host smart-3b74ba08-3879-48f3-8327-92836de9a015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395528145 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.395528145
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3201395791
Short name T11
Test name
Test status
Simulation time 534803941 ps
CPU time 1.29 seconds
Started Jul 28 06:23:24 PM PDT 24
Finished Jul 28 06:23:26 PM PDT 24
Peak memory 196584 kb
Host smart-aa4a0620-0f06-48c7-abce-c96bb0b324bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201395791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3201395791
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3550893816
Short name T189
Test name
Test status
Simulation time 239507596158 ps
CPU time 165.04 seconds
Started Jul 28 06:23:22 PM PDT 24
Finished Jul 28 06:26:08 PM PDT 24
Peak memory 198188 kb
Host smart-d77caf4d-7ef0-4738-9f8f-d6d2e2238d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550893816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3550893816
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.651776353
Short name T122
Test name
Test status
Simulation time 596144589 ps
CPU time 0.81 seconds
Started Jul 28 06:23:24 PM PDT 24
Finished Jul 28 06:23:25 PM PDT 24
Peak memory 196776 kb
Host smart-e7dcac3c-bb55-48e1-814b-66a9986e19c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651776353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.651776353
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4276357128
Short name T31
Test name
Test status
Simulation time 435729651 ps
CPU time 0.94 seconds
Started Jul 28 06:24:21 PM PDT 24
Finished Jul 28 06:24:22 PM PDT 24
Peak memory 196584 kb
Host smart-623c7873-2a68-4fba-8873-73f1c8304258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276357128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4276357128
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2494915614
Short name T208
Test name
Test status
Simulation time 8617624515 ps
CPU time 2.51 seconds
Started Jul 28 06:20:38 PM PDT 24
Finished Jul 28 06:20:41 PM PDT 24
Peak memory 198836 kb
Host smart-e4af730a-e312-47f2-a045-873314ca2c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494915614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2494915614
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2646118229
Short name T1
Test name
Test status
Simulation time 532603917 ps
CPU time 1.39 seconds
Started Jul 28 06:22:28 PM PDT 24
Finished Jul 28 06:22:30 PM PDT 24
Peak memory 196644 kb
Host smart-e3263395-08b7-4287-8446-3cd8fa54a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646118229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2646118229
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3315218326
Short name T166
Test name
Test status
Simulation time 400520777 ps
CPU time 1.23 seconds
Started Jul 28 06:22:43 PM PDT 24
Finished Jul 28 06:22:44 PM PDT 24
Peak memory 196508 kb
Host smart-9605f7ea-39c9-49da-a6d5-323532a350e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315218326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3315218326
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1363422156
Short name T18
Test name
Test status
Simulation time 14373121811 ps
CPU time 85.6 seconds
Started Jul 28 06:22:50 PM PDT 24
Finished Jul 28 06:24:15 PM PDT 24
Peak memory 206652 kb
Host smart-1cc4ce26-f06e-4e4d-b0fa-cdac62c1e0bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363422156 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1363422156
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1548464315
Short name T173
Test name
Test status
Simulation time 540551563 ps
CPU time 0.7 seconds
Started Jul 28 06:23:10 PM PDT 24
Finished Jul 28 06:23:11 PM PDT 24
Peak memory 196500 kb
Host smart-03e66127-fde1-44d9-afb6-cc4d1ca9236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548464315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1548464315
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.71995210
Short name T5
Test name
Test status
Simulation time 484752836 ps
CPU time 1.27 seconds
Started Jul 28 06:23:20 PM PDT 24
Finished Jul 28 06:23:21 PM PDT 24
Peak memory 196468 kb
Host smart-e20a8590-f2c7-43d0-b2c4-18725be37623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71995210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.71995210
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1717000734
Short name T195
Test name
Test status
Simulation time 441810118 ps
CPU time 1.21 seconds
Started Jul 28 06:23:45 PM PDT 24
Finished Jul 28 06:23:46 PM PDT 24
Peak memory 196424 kb
Host smart-760eb5f0-0920-4ee7-9936-7c7eb3794273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717000734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1717000734
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2791836189
Short name T151
Test name
Test status
Simulation time 566225411 ps
CPU time 1.38 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:22:10 PM PDT 24
Peak memory 196512 kb
Host smart-2e17f722-c312-47a1-a246-70cac0668b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791836189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2791836189
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3066726702
Short name T106
Test name
Test status
Simulation time 15584500836 ps
CPU time 113.14 seconds
Started Jul 28 06:23:53 PM PDT 24
Finished Jul 28 06:25:46 PM PDT 24
Peak memory 214668 kb
Host smart-4f085882-eebe-462e-9b97-31a400c3d581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066726702 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3066726702
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3350124408
Short name T149
Test name
Test status
Simulation time 439065794 ps
CPU time 1.23 seconds
Started Jul 28 06:24:11 PM PDT 24
Finished Jul 28 06:24:13 PM PDT 24
Peak memory 196536 kb
Host smart-28f3f25d-62d8-4ca4-a597-4374f1542627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350124408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3350124408
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1878856086
Short name T170
Test name
Test status
Simulation time 402384242 ps
CPU time 0.76 seconds
Started Jul 28 06:22:15 PM PDT 24
Finished Jul 28 06:22:16 PM PDT 24
Peak memory 196636 kb
Host smart-288dd844-894c-434b-8906-fda7fa633b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878856086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1878856086
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.717609720
Short name T126
Test name
Test status
Simulation time 533115447901 ps
CPU time 718.43 seconds
Started Jul 28 06:22:13 PM PDT 24
Finished Jul 28 06:34:12 PM PDT 24
Peak memory 192896 kb
Host smart-9e258f5e-e055-4830-a472-be3f52cd5563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717609720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.717609720
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2109458241
Short name T144
Test name
Test status
Simulation time 483194162 ps
CPU time 0.68 seconds
Started Jul 28 06:22:18 PM PDT 24
Finished Jul 28 06:22:19 PM PDT 24
Peak memory 196532 kb
Host smart-ea301c2f-9176-4d80-add3-cb6bb032e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109458241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2109458241
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3042843937
Short name T199
Test name
Test status
Simulation time 526647508 ps
CPU time 0.75 seconds
Started Jul 28 06:22:27 PM PDT 24
Finished Jul 28 06:22:27 PM PDT 24
Peak memory 196508 kb
Host smart-43d79ce8-e3a3-4d00-8108-df9bc589a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042843937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3042843937
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1003430969
Short name T191
Test name
Test status
Simulation time 109938631135 ps
CPU time 11.65 seconds
Started Jul 28 06:22:33 PM PDT 24
Finished Jul 28 06:22:44 PM PDT 24
Peak memory 192640 kb
Host smart-e2911f19-6056-47b1-b717-b073f963e4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003430969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1003430969
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3747909760
Short name T176
Test name
Test status
Simulation time 592423122 ps
CPU time 1.54 seconds
Started Jul 28 06:22:37 PM PDT 24
Finished Jul 28 06:22:39 PM PDT 24
Peak memory 196644 kb
Host smart-9c452aed-484d-4e08-8007-ade4b92e49a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747909760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3747909760
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.113880637
Short name T174
Test name
Test status
Simulation time 388045974 ps
CPU time 0.74 seconds
Started Jul 28 06:22:59 PM PDT 24
Finished Jul 28 06:22:59 PM PDT 24
Peak memory 196576 kb
Host smart-1a8bb12a-a77d-46e0-9e7e-eb1faf4075bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113880637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.113880637
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1081275472
Short name T198
Test name
Test status
Simulation time 356934019 ps
CPU time 0.84 seconds
Started Jul 28 06:22:08 PM PDT 24
Finished Jul 28 06:22:09 PM PDT 24
Peak memory 196432 kb
Host smart-9a12acc9-c090-4e40-b490-f38a21ad6a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081275472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1081275472
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.426494128
Short name T192
Test name
Test status
Simulation time 485682471 ps
CPU time 0.75 seconds
Started Jul 28 06:23:50 PM PDT 24
Finished Jul 28 06:23:51 PM PDT 24
Peak memory 196488 kb
Host smart-5d3a9a17-ab1c-40d1-b73a-1f0f993d08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426494128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.426494128
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2008844297
Short name T33
Test name
Test status
Simulation time 45013739395 ps
CPU time 187.33 seconds
Started Jul 28 06:23:56 PM PDT 24
Finished Jul 28 06:27:03 PM PDT 24
Peak memory 206620 kb
Host smart-f2a785c7-5ff6-4197-a767-051e2afef42a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008844297 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2008844297
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1434072847
Short name T196
Test name
Test status
Simulation time 47008319525 ps
CPU time 194.06 seconds
Started Jul 28 06:24:06 PM PDT 24
Finished Jul 28 06:27:20 PM PDT 24
Peak memory 212904 kb
Host smart-c8ba8542-999c-4de1-bdf4-1a296ca77fd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434072847 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1434072847
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1427727193
Short name T187
Test name
Test status
Simulation time 52829300915 ps
CPU time 37.27 seconds
Started Jul 28 06:24:20 PM PDT 24
Finished Jul 28 06:24:57 PM PDT 24
Peak memory 192772 kb
Host smart-1dfd3d24-2b04-4bc0-a8a1-40d7c69f7e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427727193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1427727193
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.347072143
Short name T8
Test name
Test status
Simulation time 150253533246 ps
CPU time 47.64 seconds
Started Jul 28 06:22:16 PM PDT 24
Finished Jul 28 06:23:03 PM PDT 24
Peak memory 192924 kb
Host smart-7d9efe99-f849-45d5-a1ce-71143e5b1166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347072143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.347072143
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.263715239
Short name T186
Test name
Test status
Simulation time 386328693 ps
CPU time 0.71 seconds
Started Jul 28 06:22:26 PM PDT 24
Finished Jul 28 06:22:26 PM PDT 24
Peak memory 196496 kb
Host smart-753b6da4-3793-4883-874d-31523be69847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263715239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.263715239
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1208758187
Short name T95
Test name
Test status
Simulation time 535463585 ps
CPU time 0.75 seconds
Started Jul 28 06:22:32 PM PDT 24
Finished Jul 28 06:22:33 PM PDT 24
Peak memory 196476 kb
Host smart-df6a4a9a-8cdf-4d7d-8d3b-4e12441e73f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208758187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1208758187
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3109523833
Short name T193
Test name
Test status
Simulation time 497797174 ps
CPU time 0.7 seconds
Started Jul 28 06:22:50 PM PDT 24
Finished Jul 28 06:22:51 PM PDT 24
Peak memory 196464 kb
Host smart-cca24565-44c7-4e16-b4d1-9efec9f7eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109523833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3109523833
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.245066852
Short name T184
Test name
Test status
Simulation time 405268337 ps
CPU time 0.76 seconds
Started Jul 28 06:22:50 PM PDT 24
Finished Jul 28 06:22:51 PM PDT 24
Peak memory 196528 kb
Host smart-caddccc4-e7ac-456d-bbe9-cbe31095d135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245066852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.245066852
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1737531034
Short name T177
Test name
Test status
Simulation time 580794209 ps
CPU time 1.29 seconds
Started Jul 28 06:23:03 PM PDT 24
Finished Jul 28 06:23:04 PM PDT 24
Peak memory 196472 kb
Host smart-28a7e602-a466-48f4-a458-190377db8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737531034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1737531034
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.392370647
Short name T58
Test name
Test status
Simulation time 483281407 ps
CPU time 1.19 seconds
Started Jul 28 06:23:13 PM PDT 24
Finished Jul 28 06:23:14 PM PDT 24
Peak memory 196492 kb
Host smart-5523e265-a74f-4ecb-b7c5-c5fdbef9940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392370647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.392370647
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.953056230
Short name T202
Test name
Test status
Simulation time 26917961234 ps
CPU time 38.25 seconds
Started Jul 28 06:23:14 PM PDT 24
Finished Jul 28 06:23:52 PM PDT 24
Peak memory 191804 kb
Host smart-2a6b3589-9fd4-44c8-b572-9cf5ca6131f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953056230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.953056230
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.523959759
Short name T55
Test name
Test status
Simulation time 575170461 ps
CPU time 0.77 seconds
Started Jul 28 06:23:33 PM PDT 24
Finished Jul 28 06:23:34 PM PDT 24
Peak memory 196524 kb
Host smart-02e45714-de6f-4915-a049-bb1d2ae0fb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523959759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.523959759
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1520076458
Short name T190
Test name
Test status
Simulation time 469050187 ps
CPU time 0.68 seconds
Started Jul 28 06:23:54 PM PDT 24
Finished Jul 28 06:23:55 PM PDT 24
Peak memory 196400 kb
Host smart-6969fb12-10fc-4db3-b04b-d4fcbaa8d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520076458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1520076458
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4184291117
Short name T183
Test name
Test status
Simulation time 384236384 ps
CPU time 0.75 seconds
Started Jul 28 06:24:02 PM PDT 24
Finished Jul 28 06:24:03 PM PDT 24
Peak memory 196476 kb
Host smart-ae80bbb0-d3d8-41db-bf09-1ac057306474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184291117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4184291117
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1723839924
Short name T81
Test name
Test status
Simulation time 632066352 ps
CPU time 1.48 seconds
Started Jul 28 06:19:47 PM PDT 24
Finished Jul 28 06:19:49 PM PDT 24
Peak memory 184216 kb
Host smart-8fa0665d-5681-4fb2-90a0-16578f2fe37b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723839924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1723839924
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3340006567
Short name T76
Test name
Test status
Simulation time 8060248333 ps
CPU time 4.45 seconds
Started Jul 28 06:19:47 PM PDT 24
Finished Jul 28 06:19:52 PM PDT 24
Peak memory 197000 kb
Host smart-56d858b3-9ac6-418f-b567-04f7b6f0bb30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340006567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3340006567
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1884138536
Short name T384
Test name
Test status
Simulation time 820471463 ps
CPU time 1.21 seconds
Started Jul 28 06:19:50 PM PDT 24
Finished Jul 28 06:19:51 PM PDT 24
Peak memory 193612 kb
Host smart-4bc6620f-d554-4620-8c22-47c0e6fbbfb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884138536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1884138536
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1751741876
Short name T320
Test name
Test status
Simulation time 354368728 ps
CPU time 0.73 seconds
Started Jul 28 06:19:55 PM PDT 24
Finished Jul 28 06:19:56 PM PDT 24
Peak memory 196040 kb
Host smart-de90bd2a-a949-4b79-81bc-007808c80854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751741876 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1751741876
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2963760075
Short name T77
Test name
Test status
Simulation time 402690764 ps
CPU time 0.88 seconds
Started Jul 28 06:19:47 PM PDT 24
Finished Jul 28 06:19:48 PM PDT 24
Peak memory 193828 kb
Host smart-e2a6e5c7-606f-4134-81dc-cc28eaa1d2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963760075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2963760075
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2004115961
Short name T380
Test name
Test status
Simulation time 508563477 ps
CPU time 1.21 seconds
Started Jul 28 06:19:39 PM PDT 24
Finished Jul 28 06:19:40 PM PDT 24
Peak memory 193440 kb
Host smart-b3f1a19f-612c-4600-b743-16f674fa555f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004115961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2004115961
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.545464114
Short name T295
Test name
Test status
Simulation time 517668730 ps
CPU time 0.87 seconds
Started Jul 28 06:19:47 PM PDT 24
Finished Jul 28 06:19:47 PM PDT 24
Peak memory 184152 kb
Host smart-c09936a0-0e58-4e72-bb90-16aa73e9dea1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545464114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.545464114
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4146794134
Short name T327
Test name
Test status
Simulation time 376261821 ps
CPU time 0.6 seconds
Started Jul 28 06:19:42 PM PDT 24
Finished Jul 28 06:19:43 PM PDT 24
Peak memory 184064 kb
Host smart-24442e62-2256-4a6c-abd6-0fc66318015f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146794134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4146794134
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3893410290
Short name T351
Test name
Test status
Simulation time 2742216600 ps
CPU time 7.22 seconds
Started Jul 28 06:19:52 PM PDT 24
Finished Jul 28 06:19:59 PM PDT 24
Peak memory 195588 kb
Host smart-35d51394-abf6-4930-95bf-444587d53a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893410290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3893410290
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2980240569
Short name T343
Test name
Test status
Simulation time 705770428 ps
CPU time 1.44 seconds
Started Jul 28 06:19:39 PM PDT 24
Finished Jul 28 06:19:41 PM PDT 24
Peak memory 199092 kb
Host smart-4af12c27-1820-404b-82c4-c5151f60b103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980240569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2980240569
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.559141717
Short name T43
Test name
Test status
Simulation time 8068471921 ps
CPU time 6.1 seconds
Started Jul 28 06:19:42 PM PDT 24
Finished Jul 28 06:19:48 PM PDT 24
Peak memory 198832 kb
Host smart-8d096843-3c33-4f76-ad9d-273cb8c25e21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559141717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.559141717
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3532581335
Short name T79
Test name
Test status
Simulation time 596683739 ps
CPU time 1.06 seconds
Started Jul 28 06:20:09 PM PDT 24
Finished Jul 28 06:20:10 PM PDT 24
Peak memory 194708 kb
Host smart-7e8f4500-d4b9-4623-8ca2-54bfef9dbf0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532581335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3532581335
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.965491849
Short name T68
Test name
Test status
Simulation time 11613504236 ps
CPU time 9.23 seconds
Started Jul 28 06:20:07 PM PDT 24
Finished Jul 28 06:20:16 PM PDT 24
Peak memory 197012 kb
Host smart-e98fd3ef-cf9f-4777-abed-1b79ee029f5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965491849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.965491849
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3644464773
Short name T383
Test name
Test status
Simulation time 749064871 ps
CPU time 0.94 seconds
Started Jul 28 06:20:05 PM PDT 24
Finished Jul 28 06:20:06 PM PDT 24
Peak memory 192560 kb
Host smart-97fc7744-93a3-4020-b606-668bb2b6dd8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644464773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3644464773
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2984882025
Short name T39
Test name
Test status
Simulation time 542953472 ps
CPU time 0.85 seconds
Started Jul 28 06:20:10 PM PDT 24
Finished Jul 28 06:20:11 PM PDT 24
Peak memory 196440 kb
Host smart-426f25f6-4d17-4a68-b2ed-63afccba8465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984882025 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2984882025
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4288434642
Short name T69
Test name
Test status
Simulation time 523992573 ps
CPU time 0.92 seconds
Started Jul 28 06:20:04 PM PDT 24
Finished Jul 28 06:20:05 PM PDT 24
Peak memory 193740 kb
Host smart-79506cc8-f54f-41e6-b921-1cd5cf606232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288434642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4288434642
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3005633446
Short name T375
Test name
Test status
Simulation time 510016755 ps
CPU time 0.9 seconds
Started Jul 28 06:20:00 PM PDT 24
Finished Jul 28 06:20:01 PM PDT 24
Peak memory 184208 kb
Host smart-a1807cb7-cfa3-4b03-9c57-6544a293aeaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005633446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3005633446
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3037414800
Short name T333
Test name
Test status
Simulation time 505998888 ps
CPU time 1.33 seconds
Started Jul 28 06:20:06 PM PDT 24
Finished Jul 28 06:20:07 PM PDT 24
Peak memory 184140 kb
Host smart-db1adc4a-1ba6-4e95-af2c-31b82d3678aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037414800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3037414800
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4181966914
Short name T290
Test name
Test status
Simulation time 379838399 ps
CPU time 0.85 seconds
Started Jul 28 06:20:10 PM PDT 24
Finished Jul 28 06:20:11 PM PDT 24
Peak memory 184128 kb
Host smart-8d8ac0bd-6705-4bb1-b856-c0388ea092a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181966914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4181966914
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3630503830
Short name T369
Test name
Test status
Simulation time 1146746442 ps
CPU time 1.08 seconds
Started Jul 28 06:20:10 PM PDT 24
Finished Jul 28 06:20:11 PM PDT 24
Peak memory 192388 kb
Host smart-a34fd207-8f0b-4ddf-9718-f680f3339266
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630503830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3630503830
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1105014594
Short name T286
Test name
Test status
Simulation time 649606842 ps
CPU time 2.4 seconds
Started Jul 28 06:19:55 PM PDT 24
Finished Jul 28 06:19:57 PM PDT 24
Peak memory 198972 kb
Host smart-7ca5a34a-c222-467a-8ed5-5bdf6c6737a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105014594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1105014594
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1411436883
Short name T394
Test name
Test status
Simulation time 4219776036 ps
CPU time 6.77 seconds
Started Jul 28 06:20:01 PM PDT 24
Finished Jul 28 06:20:08 PM PDT 24
Peak memory 198608 kb
Host smart-2b78bf99-881f-42da-b010-04afaf729974
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411436883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1411436883
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1228517746
Short name T313
Test name
Test status
Simulation time 530863542 ps
CPU time 1.09 seconds
Started Jul 28 06:21:10 PM PDT 24
Finished Jul 28 06:21:11 PM PDT 24
Peak memory 196828 kb
Host smart-fd0a3b64-f14e-49b6-8160-36136feaf09e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228517746 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1228517746
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2466191867
Short name T72
Test name
Test status
Simulation time 362998740 ps
CPU time 0.67 seconds
Started Jul 28 06:21:12 PM PDT 24
Finished Jul 28 06:21:13 PM PDT 24
Peak memory 193420 kb
Host smart-63935ccd-73d6-4dce-a026-5e950002a274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466191867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2466191867
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3666433886
Short name T303
Test name
Test status
Simulation time 348138852 ps
CPU time 1.13 seconds
Started Jul 28 06:21:11 PM PDT 24
Finished Jul 28 06:21:12 PM PDT 24
Peak memory 193488 kb
Host smart-a5cd79b9-d5fc-4f10-b159-6a2e67d8fe70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666433886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3666433886
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3698999979
Short name T406
Test name
Test status
Simulation time 1066782926 ps
CPU time 0.75 seconds
Started Jul 28 06:21:10 PM PDT 24
Finished Jul 28 06:21:11 PM PDT 24
Peak memory 193384 kb
Host smart-5fac8f39-cfe4-4e7b-a289-f9c4e341b7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698999979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3698999979
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2365717956
Short name T306
Test name
Test status
Simulation time 359459620 ps
CPU time 1.49 seconds
Started Jul 28 06:21:05 PM PDT 24
Finished Jul 28 06:21:06 PM PDT 24
Peak memory 198736 kb
Host smart-aca46fa3-0ebc-4ca3-a0ef-5b0a823d8fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365717956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2365717956
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1417518630
Short name T348
Test name
Test status
Simulation time 3999098225 ps
CPU time 2.13 seconds
Started Jul 28 06:21:07 PM PDT 24
Finished Jul 28 06:21:09 PM PDT 24
Peak memory 196916 kb
Host smart-c9b071ca-e012-4dac-b7bd-9d0ec377d34c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417518630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1417518630
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.842568351
Short name T302
Test name
Test status
Simulation time 366989024 ps
CPU time 1.15 seconds
Started Jul 28 06:21:22 PM PDT 24
Finished Jul 28 06:21:23 PM PDT 24
Peak memory 196232 kb
Host smart-197da4c3-ebe5-4f52-9e14-f8968738c17e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842568351 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.842568351
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3961458953
Short name T393
Test name
Test status
Simulation time 436431331 ps
CPU time 1.05 seconds
Started Jul 28 06:21:14 PM PDT 24
Finished Jul 28 06:21:15 PM PDT 24
Peak memory 192492 kb
Host smart-67f8f532-450f-4a9f-a842-16f56f10821d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961458953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3961458953
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2113929629
Short name T411
Test name
Test status
Simulation time 428986193 ps
CPU time 0.85 seconds
Started Jul 28 06:21:22 PM PDT 24
Finished Jul 28 06:21:23 PM PDT 24
Peak memory 184156 kb
Host smart-3e0eba12-43a3-485a-86bd-c1e3903db836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113929629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2113929629
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4072382119
Short name T89
Test name
Test status
Simulation time 2345669201 ps
CPU time 1.54 seconds
Started Jul 28 06:21:22 PM PDT 24
Finished Jul 28 06:21:23 PM PDT 24
Peak memory 194960 kb
Host smart-6162a532-5c04-4aec-ab95-130010aa6a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072382119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4072382119
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2826197104
Short name T416
Test name
Test status
Simulation time 401640554 ps
CPU time 1.73 seconds
Started Jul 28 06:21:12 PM PDT 24
Finished Jul 28 06:21:14 PM PDT 24
Peak memory 199044 kb
Host smart-2ffb4c8f-c93f-4709-b904-137f4ca6e0db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826197104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2826197104
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.747412897
Short name T330
Test name
Test status
Simulation time 3906758297 ps
CPU time 2.34 seconds
Started Jul 28 06:21:13 PM PDT 24
Finished Jul 28 06:21:15 PM PDT 24
Peak memory 198780 kb
Host smart-76ca651e-b330-4be4-ad8d-2acb35716e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747412897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.747412897
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1438582890
Short name T404
Test name
Test status
Simulation time 442580971 ps
CPU time 1.36 seconds
Started Jul 28 06:21:21 PM PDT 24
Finished Jul 28 06:21:23 PM PDT 24
Peak memory 196656 kb
Host smart-68f3fff0-d557-4c07-82a1-d7f5a12db9b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438582890 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1438582890
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2782369801
Short name T70
Test name
Test status
Simulation time 461928394 ps
CPU time 0.88 seconds
Started Jul 28 06:21:20 PM PDT 24
Finished Jul 28 06:21:21 PM PDT 24
Peak memory 193400 kb
Host smart-01f71702-92ab-4ff0-ab80-bcea9574c880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782369801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2782369801
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3899948380
Short name T362
Test name
Test status
Simulation time 298229415 ps
CPU time 0.63 seconds
Started Jul 28 06:21:25 PM PDT 24
Finished Jul 28 06:21:26 PM PDT 24
Peak memory 184156 kb
Host smart-2d34e318-d17e-489c-abbb-73c277be824d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899948380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3899948380
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.101346346
Short name T388
Test name
Test status
Simulation time 2502464421 ps
CPU time 1.07 seconds
Started Jul 28 06:21:20 PM PDT 24
Finished Jul 28 06:21:21 PM PDT 24
Peak memory 192488 kb
Host smart-dedf28a0-5b7b-45e0-b52c-22acdef896c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101346346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.101346346
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2051975929
Short name T353
Test name
Test status
Simulation time 682351290 ps
CPU time 1.67 seconds
Started Jul 28 06:21:14 PM PDT 24
Finished Jul 28 06:21:16 PM PDT 24
Peak memory 199028 kb
Host smart-131c0370-8852-444c-84a9-ab227339dd02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051975929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2051975929
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1217968815
Short name T44
Test name
Test status
Simulation time 8395795304 ps
CPU time 6.68 seconds
Started Jul 28 06:21:19 PM PDT 24
Finished Jul 28 06:21:26 PM PDT 24
Peak memory 198844 kb
Host smart-589b1c86-9d7f-4c60-8b16-ba24bdd6c66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217968815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1217968815
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1846678750
Short name T325
Test name
Test status
Simulation time 317766245 ps
CPU time 0.73 seconds
Started Jul 28 06:21:26 PM PDT 24
Finished Jul 28 06:21:27 PM PDT 24
Peak memory 196408 kb
Host smart-1205e958-f0c0-4443-99ad-1eb708a229da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846678750 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1846678750
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2454689048
Short name T67
Test name
Test status
Simulation time 279550539 ps
CPU time 0.7 seconds
Started Jul 28 06:21:27 PM PDT 24
Finished Jul 28 06:21:28 PM PDT 24
Peak memory 192500 kb
Host smart-ead17aae-68fd-43bf-a4ef-68c7a6ae5e77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454689048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2454689048
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.634776885
Short name T361
Test name
Test status
Simulation time 285429357 ps
CPU time 0.69 seconds
Started Jul 28 06:21:24 PM PDT 24
Finished Jul 28 06:21:25 PM PDT 24
Peak memory 184244 kb
Host smart-49b6b6b7-c51a-4e7c-af38-ce496bc6bef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634776885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.634776885
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1226803067
Short name T337
Test name
Test status
Simulation time 2394323080 ps
CPU time 3.57 seconds
Started Jul 28 06:21:29 PM PDT 24
Finished Jul 28 06:21:33 PM PDT 24
Peak memory 195420 kb
Host smart-2a61ec1a-bdd7-44e2-831a-84d0cd80a4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226803067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1226803067
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3250029135
Short name T374
Test name
Test status
Simulation time 679917222 ps
CPU time 2.43 seconds
Started Jul 28 06:21:22 PM PDT 24
Finished Jul 28 06:21:24 PM PDT 24
Peak memory 199028 kb
Host smart-10952224-a15d-4ad3-99e7-aa37b581efbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250029135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3250029135
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3217517081
Short name T370
Test name
Test status
Simulation time 4155773073 ps
CPU time 2.35 seconds
Started Jul 28 06:21:25 PM PDT 24
Finished Jul 28 06:21:27 PM PDT 24
Peak memory 197188 kb
Host smart-674b83a9-db29-46a5-b6f1-ec0401ccafa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217517081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3217517081
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1450531057
Short name T397
Test name
Test status
Simulation time 443331939 ps
CPU time 0.89 seconds
Started Jul 28 06:21:26 PM PDT 24
Finished Jul 28 06:21:27 PM PDT 24
Peak memory 196308 kb
Host smart-463382d4-5349-42b3-8ea8-f9a82d7f223c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450531057 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1450531057
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3835866405
Short name T324
Test name
Test status
Simulation time 371690720 ps
CPU time 1.1 seconds
Started Jul 28 06:21:26 PM PDT 24
Finished Jul 28 06:21:27 PM PDT 24
Peak memory 192408 kb
Host smart-1f88180e-7e07-4073-aece-91e8d3d0b256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835866405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3835866405
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1507799609
Short name T338
Test name
Test status
Simulation time 478545926 ps
CPU time 1.15 seconds
Started Jul 28 06:21:26 PM PDT 24
Finished Jul 28 06:21:27 PM PDT 24
Peak memory 184224 kb
Host smart-b7acbdd5-11f3-46da-8bc6-41167f083845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507799609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1507799609
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.241645555
Short name T91
Test name
Test status
Simulation time 1174638730 ps
CPU time 1 seconds
Started Jul 28 06:21:25 PM PDT 24
Finished Jul 28 06:21:26 PM PDT 24
Peak memory 194060 kb
Host smart-8737756a-4997-44e3-bbf5-2d551a1474ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241645555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.241645555
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2289981087
Short name T288
Test name
Test status
Simulation time 583683339 ps
CPU time 2.25 seconds
Started Jul 28 06:21:29 PM PDT 24
Finished Jul 28 06:21:32 PM PDT 24
Peak memory 198988 kb
Host smart-484741e1-d7ea-41d3-b577-bf2b7ac8c1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289981087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2289981087
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3004052791
Short name T382
Test name
Test status
Simulation time 507738129 ps
CPU time 1.31 seconds
Started Jul 28 06:21:29 PM PDT 24
Finished Jul 28 06:21:31 PM PDT 24
Peak memory 195940 kb
Host smart-9e7ecba4-c1d4-400b-bdd3-1711c4e17b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004052791 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3004052791
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3979877000
Short name T349
Test name
Test status
Simulation time 504789636 ps
CPU time 0.76 seconds
Started Jul 28 06:21:30 PM PDT 24
Finished Jul 28 06:21:31 PM PDT 24
Peak memory 193472 kb
Host smart-ddd5acdd-2803-4e0d-bdb9-646767016d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979877000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3979877000
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2196605746
Short name T300
Test name
Test status
Simulation time 460204894 ps
CPU time 0.84 seconds
Started Jul 28 06:21:31 PM PDT 24
Finished Jul 28 06:21:32 PM PDT 24
Peak memory 184168 kb
Host smart-1ec3b0eb-34de-48da-a84c-eb5681f091a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196605746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2196605746
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3200294739
Short name T381
Test name
Test status
Simulation time 2302789759 ps
CPU time 3.61 seconds
Started Jul 28 06:21:32 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 195532 kb
Host smart-310f8289-1a61-4e5b-bbe2-1d758bd69130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200294739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3200294739
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.939132195
Short name T305
Test name
Test status
Simulation time 534055021 ps
CPU time 2.3 seconds
Started Jul 28 06:21:33 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 198964 kb
Host smart-f6b02f83-e89e-4d8a-8ead-cfee191ca8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939132195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.939132195
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2592687118
Short name T401
Test name
Test status
Simulation time 4539028727 ps
CPU time 2.64 seconds
Started Jul 28 06:21:30 PM PDT 24
Finished Jul 28 06:21:32 PM PDT 24
Peak memory 198552 kb
Host smart-f7615259-985d-486b-9fd3-2bce9800e190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592687118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2592687118
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1433767558
Short name T385
Test name
Test status
Simulation time 383753412 ps
CPU time 0.97 seconds
Started Jul 28 06:21:35 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 197864 kb
Host smart-dde42f9a-a63b-44d3-818b-a8e024340f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433767558 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1433767558
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1505899607
Short name T420
Test name
Test status
Simulation time 457672545 ps
CPU time 1.23 seconds
Started Jul 28 06:21:33 PM PDT 24
Finished Jul 28 06:21:34 PM PDT 24
Peak memory 192524 kb
Host smart-80aeda7f-7370-4f7e-84a6-eefe0e0bb464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505899607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1505899607
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2513141076
Short name T354
Test name
Test status
Simulation time 457639497 ps
CPU time 0.72 seconds
Started Jul 28 06:21:31 PM PDT 24
Finished Jul 28 06:21:32 PM PDT 24
Peak memory 193408 kb
Host smart-80564915-700c-49c8-ba02-d5a2a3a4b8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513141076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2513141076
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2033861122
Short name T350
Test name
Test status
Simulation time 2086554044 ps
CPU time 4.37 seconds
Started Jul 28 06:21:35 PM PDT 24
Finished Jul 28 06:21:39 PM PDT 24
Peak memory 192480 kb
Host smart-48bc416b-cc4a-4b01-9b50-f1a27910ad3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033861122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2033861122
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.504764136
Short name T287
Test name
Test status
Simulation time 461294167 ps
CPU time 1.23 seconds
Started Jul 28 06:21:31 PM PDT 24
Finished Jul 28 06:21:32 PM PDT 24
Peak memory 198856 kb
Host smart-2db6831e-a865-4309-9abd-5a83741b535c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504764136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.504764136
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1433436918
Short name T403
Test name
Test status
Simulation time 4024756243 ps
CPU time 6.76 seconds
Started Jul 28 06:21:31 PM PDT 24
Finished Jul 28 06:21:38 PM PDT 24
Peak memory 198612 kb
Host smart-8f783896-6697-4ba8-a05e-20f5ef373151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433436918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1433436918
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2798718339
Short name T319
Test name
Test status
Simulation time 338977160 ps
CPU time 0.92 seconds
Started Jul 28 06:21:35 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 196592 kb
Host smart-8515533f-07d7-46a8-933d-f3cbc623203a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798718339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2798718339
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3098339831
Short name T314
Test name
Test status
Simulation time 474965324 ps
CPU time 0.77 seconds
Started Jul 28 06:21:36 PM PDT 24
Finished Jul 28 06:21:37 PM PDT 24
Peak memory 194460 kb
Host smart-685a1dc2-cbac-40e3-a0e5-491893ebe852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098339831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3098339831
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.919065353
Short name T309
Test name
Test status
Simulation time 483429540 ps
CPU time 1.27 seconds
Started Jul 28 06:21:34 PM PDT 24
Finished Jul 28 06:21:35 PM PDT 24
Peak memory 184212 kb
Host smart-5f6f6478-96b1-4a94-808f-9960c3f075d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919065353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.919065353
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.978943027
Short name T90
Test name
Test status
Simulation time 2683919567 ps
CPU time 1.99 seconds
Started Jul 28 06:21:36 PM PDT 24
Finished Jul 28 06:21:38 PM PDT 24
Peak memory 194416 kb
Host smart-8ee0333b-5cb0-4967-b4c5-302fa26523cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978943027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.978943027
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2708837207
Short name T316
Test name
Test status
Simulation time 493443913 ps
CPU time 2.42 seconds
Started Jul 28 06:21:38 PM PDT 24
Finished Jul 28 06:21:40 PM PDT 24
Peak memory 199060 kb
Host smart-609d9ed1-8ae0-49ae-9143-663191a4e1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708837207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2708837207
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.976658225
Short name T415
Test name
Test status
Simulation time 4759086192 ps
CPU time 1.2 seconds
Started Jul 28 06:21:35 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 197084 kb
Host smart-5f4de286-9e20-486d-9913-3ab9ccf7938d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976658225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.976658225
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3632875436
Short name T211
Test name
Test status
Simulation time 321235600 ps
CPU time 0.99 seconds
Started Jul 28 06:21:39 PM PDT 24
Finished Jul 28 06:21:40 PM PDT 24
Peak memory 196668 kb
Host smart-265dc4d2-33f5-407e-812a-1f9705086c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632875436 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3632875436
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3490715107
Short name T75
Test name
Test status
Simulation time 423830677 ps
CPU time 1.14 seconds
Started Jul 28 06:21:34 PM PDT 24
Finished Jul 28 06:21:35 PM PDT 24
Peak memory 194368 kb
Host smart-14578228-58d1-47de-9e72-404200df5229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490715107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3490715107
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3241543819
Short name T368
Test name
Test status
Simulation time 508138656 ps
CPU time 0.84 seconds
Started Jul 28 06:21:34 PM PDT 24
Finished Jul 28 06:21:35 PM PDT 24
Peak memory 193424 kb
Host smart-fb61972c-15f8-4dd1-bae6-cca2d6d495b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241543819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3241543819
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2767902997
Short name T398
Test name
Test status
Simulation time 1576089947 ps
CPU time 4.52 seconds
Started Jul 28 06:21:42 PM PDT 24
Finished Jul 28 06:21:46 PM PDT 24
Peak memory 194548 kb
Host smart-945d7552-4814-4c50-8fcd-f8c21c801aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767902997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2767902997
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1827140421
Short name T413
Test name
Test status
Simulation time 480706637 ps
CPU time 2.09 seconds
Started Jul 28 06:21:34 PM PDT 24
Finished Jul 28 06:21:36 PM PDT 24
Peak memory 199048 kb
Host smart-a84b3af4-b3e4-4efa-b155-f3f17ad58c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827140421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1827140421
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2142113060
Short name T408
Test name
Test status
Simulation time 8458820969 ps
CPU time 4.03 seconds
Started Jul 28 06:21:35 PM PDT 24
Finished Jul 28 06:21:39 PM PDT 24
Peak memory 198936 kb
Host smart-5c8abe0a-3cce-4e24-a47d-da6884970f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142113060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2142113060
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4229543531
Short name T341
Test name
Test status
Simulation time 421592949 ps
CPU time 1.3 seconds
Started Jul 28 06:21:38 PM PDT 24
Finished Jul 28 06:21:40 PM PDT 24
Peak memory 197060 kb
Host smart-a764c066-dfe2-4243-ab02-a484851ed024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229543531 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4229543531
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2965959496
Short name T80
Test name
Test status
Simulation time 349347604 ps
CPU time 0.97 seconds
Started Jul 28 06:21:40 PM PDT 24
Finished Jul 28 06:21:41 PM PDT 24
Peak memory 192480 kb
Host smart-c681f680-aa40-47a0-af2d-76bd8384750b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965959496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2965959496
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2504587811
Short name T342
Test name
Test status
Simulation time 294738686 ps
CPU time 0.97 seconds
Started Jul 28 06:21:41 PM PDT 24
Finished Jul 28 06:21:42 PM PDT 24
Peak memory 184180 kb
Host smart-6240c915-5f72-4b9a-be1a-3097a71f7e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504587811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2504587811
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3647065586
Short name T40
Test name
Test status
Simulation time 1175877492 ps
CPU time 3.01 seconds
Started Jul 28 06:21:40 PM PDT 24
Finished Jul 28 06:21:43 PM PDT 24
Peak memory 193440 kb
Host smart-3fbe4e63-9569-49cf-aea9-f0ccbe8d862d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647065586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3647065586
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4097104365
Short name T317
Test name
Test status
Simulation time 471174273 ps
CPU time 2.15 seconds
Started Jul 28 06:21:39 PM PDT 24
Finished Jul 28 06:21:41 PM PDT 24
Peak memory 199036 kb
Host smart-2ed9b41f-b26a-4309-9911-91d39dd5599e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097104365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4097104365
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1225072864
Short name T206
Test name
Test status
Simulation time 7950739771 ps
CPU time 12.98 seconds
Started Jul 28 06:21:41 PM PDT 24
Finished Jul 28 06:21:54 PM PDT 24
Peak memory 198760 kb
Host smart-7f3808d9-6850-425e-8444-6afb3d6d8553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225072864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1225072864
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3467800301
Short name T299
Test name
Test status
Simulation time 640724440 ps
CPU time 1.01 seconds
Started Jul 28 06:20:22 PM PDT 24
Finished Jul 28 06:20:23 PM PDT 24
Peak memory 195000 kb
Host smart-0c21dd00-482c-41bc-9f48-46b7d2f66393
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467800301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3467800301
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3422644564
Short name T344
Test name
Test status
Simulation time 14257810687 ps
CPU time 6.98 seconds
Started Jul 28 06:20:22 PM PDT 24
Finished Jul 28 06:20:29 PM PDT 24
Peak memory 196852 kb
Host smart-3d79cefd-0f2c-4422-b248-3a0e6c059c88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422644564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3422644564
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4029909345
Short name T390
Test name
Test status
Simulation time 844426418 ps
CPU time 1.74 seconds
Started Jul 28 06:20:21 PM PDT 24
Finished Jul 28 06:20:22 PM PDT 24
Peak memory 193448 kb
Host smart-195cf905-3cda-471b-89e0-73e61c415cca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029909345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4029909345
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3434514319
Short name T41
Test name
Test status
Simulation time 356840702 ps
CPU time 1.21 seconds
Started Jul 28 06:20:20 PM PDT 24
Finished Jul 28 06:20:21 PM PDT 24
Peak memory 196396 kb
Host smart-99a6d146-94d3-4eea-abfb-47ab6a90d11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434514319 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3434514319
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1495363467
Short name T45
Test name
Test status
Simulation time 456858114 ps
CPU time 1.19 seconds
Started Jul 28 06:20:20 PM PDT 24
Finished Jul 28 06:20:21 PM PDT 24
Peak memory 193428 kb
Host smart-5be7cc09-a81b-4277-80cb-a6f3c98fcca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495363467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1495363467
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.334946430
Short name T395
Test name
Test status
Simulation time 401676889 ps
CPU time 1.11 seconds
Started Jul 28 06:20:15 PM PDT 24
Finished Jul 28 06:20:16 PM PDT 24
Peak memory 184232 kb
Host smart-9cf5ce28-e1e3-452e-8009-f54bde5948bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334946430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.334946430
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.211304063
Short name T355
Test name
Test status
Simulation time 455307185 ps
CPU time 1.3 seconds
Started Jul 28 06:20:17 PM PDT 24
Finished Jul 28 06:20:18 PM PDT 24
Peak memory 184056 kb
Host smart-ca695b74-97f5-4dca-ba7f-1217d2d92fa7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211304063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.211304063
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1137270477
Short name T296
Test name
Test status
Simulation time 337606383 ps
CPU time 0.65 seconds
Started Jul 28 06:20:16 PM PDT 24
Finished Jul 28 06:20:17 PM PDT 24
Peak memory 184076 kb
Host smart-c957140f-1b58-41bf-a52b-67d3bcaf0845
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137270477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1137270477
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3727503776
Short name T92
Test name
Test status
Simulation time 2779423153 ps
CPU time 3.79 seconds
Started Jul 28 06:20:24 PM PDT 24
Finished Jul 28 06:20:27 PM PDT 24
Peak memory 194436 kb
Host smart-77b7b5c5-6438-4b10-9bb5-f218b2c99dd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727503776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3727503776
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2903460246
Short name T283
Test name
Test status
Simulation time 763543738 ps
CPU time 2.49 seconds
Started Jul 28 06:20:09 PM PDT 24
Finished Jul 28 06:20:12 PM PDT 24
Peak memory 199008 kb
Host smart-fcca308c-f581-4415-9c0e-75ab931bd63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903460246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2903460246
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3774364764
Short name T352
Test name
Test status
Simulation time 3631459311 ps
CPU time 6.04 seconds
Started Jul 28 06:20:15 PM PDT 24
Finished Jul 28 06:20:21 PM PDT 24
Peak memory 198676 kb
Host smart-0f86ed78-4ed6-48fc-bfc9-4b5392f963e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774364764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3774364764
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.356457852
Short name T346
Test name
Test status
Simulation time 395008277 ps
CPU time 0.68 seconds
Started Jul 28 06:21:41 PM PDT 24
Finished Jul 28 06:21:42 PM PDT 24
Peak memory 184220 kb
Host smart-74f67151-1305-4645-8e4b-510be0affe71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356457852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.356457852
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1517544756
Short name T328
Test name
Test status
Simulation time 419626116 ps
CPU time 0.71 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184152 kb
Host smart-be9af9a4-54d9-48ab-92a1-011e7601a28d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517544756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1517544756
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.670009419
Short name T318
Test name
Test status
Simulation time 299572884 ps
CPU time 0.97 seconds
Started Jul 28 06:21:43 PM PDT 24
Finished Jul 28 06:21:44 PM PDT 24
Peak memory 184160 kb
Host smart-53872f3b-0943-49d2-97cf-e16408fccad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670009419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.670009419
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.735055806
Short name T399
Test name
Test status
Simulation time 281584692 ps
CPU time 0.95 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184208 kb
Host smart-75c960d4-480b-42c7-844d-754cf834dc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735055806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.735055806
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.536167594
Short name T378
Test name
Test status
Simulation time 389483784 ps
CPU time 0.66 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184220 kb
Host smart-d7ce42af-7691-4330-8a0b-e3c0150f594a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536167594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.536167594
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3722445434
Short name T312
Test name
Test status
Simulation time 469439872 ps
CPU time 0.68 seconds
Started Jul 28 06:21:45 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184212 kb
Host smart-1b861df9-934b-426b-8ce4-974ce647620e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722445434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3722445434
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.196937337
Short name T357
Test name
Test status
Simulation time 414465407 ps
CPU time 1.17 seconds
Started Jul 28 06:21:47 PM PDT 24
Finished Jul 28 06:21:48 PM PDT 24
Peak memory 184220 kb
Host smart-f909ef4b-0bce-413a-be14-c6a36b98f71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196937337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.196937337
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3408535182
Short name T407
Test name
Test status
Simulation time 460962717 ps
CPU time 1.19 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184232 kb
Host smart-be767676-01b4-48f4-a146-31ff05abc81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408535182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3408535182
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3166615091
Short name T292
Test name
Test status
Simulation time 588233371 ps
CPU time 0.58 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:44 PM PDT 24
Peak memory 193396 kb
Host smart-5b3b0cd8-0fde-4f46-ac0e-f85d471f5cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166615091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3166615091
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.451854945
Short name T289
Test name
Test status
Simulation time 398210997 ps
CPU time 1.08 seconds
Started Jul 28 06:21:44 PM PDT 24
Finished Jul 28 06:21:45 PM PDT 24
Peak memory 184136 kb
Host smart-862a42a5-68ee-4594-b3b9-20cf69b9ee67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451854945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.451854945
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2513014968
Short name T412
Test name
Test status
Simulation time 485490668 ps
CPU time 0.87 seconds
Started Jul 28 06:20:30 PM PDT 24
Finished Jul 28 06:20:31 PM PDT 24
Peak memory 193636 kb
Host smart-66eace58-343a-4a78-8879-2c24cdcf9903
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513014968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2513014968
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2924944522
Short name T74
Test name
Test status
Simulation time 6200942691 ps
CPU time 5.2 seconds
Started Jul 28 06:20:30 PM PDT 24
Finished Jul 28 06:20:35 PM PDT 24
Peak memory 192800 kb
Host smart-554b86af-a38b-4814-8cf8-2ae3042714c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924944522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2924944522
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2371500315
Short name T410
Test name
Test status
Simulation time 596352543 ps
CPU time 1.4 seconds
Started Jul 28 06:20:26 PM PDT 24
Finished Jul 28 06:20:28 PM PDT 24
Peak memory 192576 kb
Host smart-4c0802dc-31fa-4f2c-9bf3-2c53cb12e9da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371500315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2371500315
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1348095826
Short name T386
Test name
Test status
Simulation time 491331282 ps
CPU time 1.09 seconds
Started Jul 28 06:20:29 PM PDT 24
Finished Jul 28 06:20:30 PM PDT 24
Peak memory 198812 kb
Host smart-7ea6e79a-3abc-4e06-897c-538e7dc3aa82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348095826 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1348095826
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1471202059
Short name T402
Test name
Test status
Simulation time 356269944 ps
CPU time 0.58 seconds
Started Jul 28 06:20:26 PM PDT 24
Finished Jul 28 06:20:26 PM PDT 24
Peak memory 184224 kb
Host smart-381fd512-113b-491b-96dd-4c248b1d3d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471202059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1471202059
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.349802226
Short name T332
Test name
Test status
Simulation time 287530440 ps
CPU time 0.88 seconds
Started Jul 28 06:20:26 PM PDT 24
Finished Jul 28 06:20:27 PM PDT 24
Peak memory 184072 kb
Host smart-d76bd1c1-0a56-4c88-810c-84e05d51689b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349802226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.349802226
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1027606101
Short name T389
Test name
Test status
Simulation time 388385423 ps
CPU time 0.79 seconds
Started Jul 28 06:20:29 PM PDT 24
Finished Jul 28 06:20:30 PM PDT 24
Peak memory 184292 kb
Host smart-335a8b3d-a9e0-4101-a421-15200761f02c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027606101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1027606101
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2988763932
Short name T387
Test name
Test status
Simulation time 1846161985 ps
CPU time 3.07 seconds
Started Jul 28 06:20:34 PM PDT 24
Finished Jul 28 06:20:37 PM PDT 24
Peak memory 192368 kb
Host smart-7d946925-1920-4f98-939f-177b45e96c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988763932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2988763932
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3082640294
Short name T311
Test name
Test status
Simulation time 447248589 ps
CPU time 2.01 seconds
Started Jul 28 06:20:26 PM PDT 24
Finished Jul 28 06:20:28 PM PDT 24
Peak memory 199032 kb
Host smart-01b982f4-ab8e-47f6-bad6-642555482db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082640294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3082640294
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2769878824
Short name T310
Test name
Test status
Simulation time 9051067606 ps
CPU time 2.99 seconds
Started Jul 28 06:20:26 PM PDT 24
Finished Jul 28 06:20:29 PM PDT 24
Peak memory 198720 kb
Host smart-a9df32a7-52d3-406f-bb75-dd9cebffbecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769878824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2769878824
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2901273962
Short name T335
Test name
Test status
Simulation time 334944399 ps
CPU time 1.06 seconds
Started Jul 28 06:21:47 PM PDT 24
Finished Jul 28 06:21:49 PM PDT 24
Peak memory 193396 kb
Host smart-6ce23110-5171-4685-8b1e-0dee2b44aea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901273962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2901273962
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.395843740
Short name T363
Test name
Test status
Simulation time 338108437 ps
CPU time 0.99 seconds
Started Jul 28 06:21:47 PM PDT 24
Finished Jul 28 06:21:48 PM PDT 24
Peak memory 184192 kb
Host smart-a73ce628-97a3-42c5-837b-e75a6ac44291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395843740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.395843740
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.434199010
Short name T356
Test name
Test status
Simulation time 493701306 ps
CPU time 0.85 seconds
Started Jul 28 06:21:51 PM PDT 24
Finished Jul 28 06:21:52 PM PDT 24
Peak memory 184168 kb
Host smart-61b93dae-c5ff-48a2-8823-09ef55b5a28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434199010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.434199010
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1469839359
Short name T373
Test name
Test status
Simulation time 329726590 ps
CPU time 0.62 seconds
Started Jul 28 06:21:47 PM PDT 24
Finished Jul 28 06:21:48 PM PDT 24
Peak memory 184140 kb
Host smart-abc4b812-8a0e-493a-a1f0-0d6e5fc70072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469839359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1469839359
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2104006723
Short name T323
Test name
Test status
Simulation time 302075940 ps
CPU time 0.59 seconds
Started Jul 28 06:21:48 PM PDT 24
Finished Jul 28 06:21:49 PM PDT 24
Peak memory 184268 kb
Host smart-492ed49a-608c-47e2-a01c-ffb50380b3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104006723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2104006723
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2996154111
Short name T331
Test name
Test status
Simulation time 295936963 ps
CPU time 0.93 seconds
Started Jul 28 06:21:47 PM PDT 24
Finished Jul 28 06:21:48 PM PDT 24
Peak memory 184204 kb
Host smart-512ae998-af16-4930-aa28-137acc08db5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996154111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2996154111
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2403709614
Short name T419
Test name
Test status
Simulation time 432808835 ps
CPU time 1.11 seconds
Started Jul 28 06:21:54 PM PDT 24
Finished Jul 28 06:21:55 PM PDT 24
Peak memory 184188 kb
Host smart-b04fd9df-0c3d-4413-93e6-d4c1a889f011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403709614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2403709614
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3993868876
Short name T339
Test name
Test status
Simulation time 491143973 ps
CPU time 1.24 seconds
Started Jul 28 06:21:56 PM PDT 24
Finished Jul 28 06:21:57 PM PDT 24
Peak memory 184184 kb
Host smart-e17fc214-746e-45b2-958c-b55c7edea81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993868876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3993868876
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1637862395
Short name T291
Test name
Test status
Simulation time 297016451 ps
CPU time 0.75 seconds
Started Jul 28 06:21:56 PM PDT 24
Finished Jul 28 06:21:57 PM PDT 24
Peak memory 184144 kb
Host smart-d1e011e8-0b58-445a-9e92-e48d2954699e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637862395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1637862395
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1576756891
Short name T308
Test name
Test status
Simulation time 623258247 ps
CPU time 0.59 seconds
Started Jul 28 06:21:54 PM PDT 24
Finished Jul 28 06:21:54 PM PDT 24
Peak memory 193372 kb
Host smart-55bf76ec-e38a-4526-bacf-14d5b990a81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576756891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1576756891
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2116097617
Short name T366
Test name
Test status
Simulation time 736174859 ps
CPU time 0.8 seconds
Started Jul 28 06:20:40 PM PDT 24
Finished Jul 28 06:20:41 PM PDT 24
Peak memory 195020 kb
Host smart-ea6642cf-2876-4374-84e1-8888b00f717a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116097617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2116097617
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4195621845
Short name T78
Test name
Test status
Simulation time 1163407236 ps
CPU time 1.6 seconds
Started Jul 28 06:20:45 PM PDT 24
Finished Jul 28 06:20:47 PM PDT 24
Peak memory 196732 kb
Host smart-d940f1ed-6768-4a1b-afdf-30fb18510521
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195621845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4195621845
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2462711507
Short name T336
Test name
Test status
Simulation time 1105812091 ps
CPU time 2.27 seconds
Started Jul 28 06:20:42 PM PDT 24
Finished Jul 28 06:20:45 PM PDT 24
Peak memory 193668 kb
Host smart-725fc291-e38e-4255-8c7b-bbd89285cfe8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462711507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2462711507
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1261403814
Short name T212
Test name
Test status
Simulation time 415714785 ps
CPU time 1 seconds
Started Jul 28 06:20:48 PM PDT 24
Finished Jul 28 06:20:49 PM PDT 24
Peak memory 197092 kb
Host smart-294b73dd-e012-4154-a9ff-1205f0c930d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261403814 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1261403814
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1631905316
Short name T73
Test name
Test status
Simulation time 522010911 ps
CPU time 1.28 seconds
Started Jul 28 06:20:41 PM PDT 24
Finished Jul 28 06:20:42 PM PDT 24
Peak memory 193448 kb
Host smart-14cd4dfb-2f73-49de-acc7-7b905387e94f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631905316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1631905316
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4051660710
Short name T371
Test name
Test status
Simulation time 265686775 ps
CPU time 0.85 seconds
Started Jul 28 06:20:39 PM PDT 24
Finished Jul 28 06:20:40 PM PDT 24
Peak memory 184156 kb
Host smart-22da192a-2243-4b24-b50b-410a95c1dfbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051660710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4051660710
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.32326396
Short name T365
Test name
Test status
Simulation time 515094344 ps
CPU time 1.26 seconds
Started Jul 28 06:20:41 PM PDT 24
Finished Jul 28 06:20:43 PM PDT 24
Peak memory 184164 kb
Host smart-00aa1b65-6c17-4195-833b-2e5947a70de8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32326396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_mem_partial_access.32326396
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3570429266
Short name T421
Test name
Test status
Simulation time 426945302 ps
CPU time 1.16 seconds
Started Jul 28 06:20:36 PM PDT 24
Finished Jul 28 06:20:37 PM PDT 24
Peak memory 184132 kb
Host smart-77bd4a17-623a-4c25-ba1f-3f144e86a177
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570429266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3570429266
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1899840181
Short name T321
Test name
Test status
Simulation time 1247956263 ps
CPU time 1.14 seconds
Started Jul 28 06:20:45 PM PDT 24
Finished Jul 28 06:20:46 PM PDT 24
Peak memory 184220 kb
Host smart-f856f6be-1680-471a-a3bd-6f2de55b2b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899840181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1899840181
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2715220460
Short name T285
Test name
Test status
Simulation time 502398397 ps
CPU time 1.47 seconds
Started Jul 28 06:20:38 PM PDT 24
Finished Jul 28 06:20:40 PM PDT 24
Peak memory 198992 kb
Host smart-d198f1b1-b3cf-47b1-aa52-3f43f8514c57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715220460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2715220460
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2698250787
Short name T326
Test name
Test status
Simulation time 381250528 ps
CPU time 0.85 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:59 PM PDT 24
Peak memory 193616 kb
Host smart-b74a16a1-7653-4ead-9dcb-3feae927e5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698250787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2698250787
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2196757330
Short name T364
Test name
Test status
Simulation time 289162007 ps
CPU time 0.63 seconds
Started Jul 28 06:21:54 PM PDT 24
Finished Jul 28 06:21:55 PM PDT 24
Peak memory 184120 kb
Host smart-a0fcaeae-245f-4cc9-87b9-a85a9aff4cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196757330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2196757330
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3957556499
Short name T391
Test name
Test status
Simulation time 389058686 ps
CPU time 0.85 seconds
Started Jul 28 06:21:56 PM PDT 24
Finished Jul 28 06:21:57 PM PDT 24
Peak memory 193404 kb
Host smart-2a418fa3-0168-4c3d-83c7-3eb52a18bce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957556499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3957556499
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1963874991
Short name T417
Test name
Test status
Simulation time 284015154 ps
CPU time 1.01 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:59 PM PDT 24
Peak memory 193408 kb
Host smart-155c9711-fafd-4528-b138-5bdeaf271a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963874991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1963874991
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2546290341
Short name T334
Test name
Test status
Simulation time 451716413 ps
CPU time 0.72 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:58 PM PDT 24
Peak memory 184220 kb
Host smart-01128218-7a00-4631-976f-c6de02487ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546290341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2546290341
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1906939545
Short name T304
Test name
Test status
Simulation time 407969875 ps
CPU time 0.67 seconds
Started Jul 28 06:21:59 PM PDT 24
Finished Jul 28 06:22:00 PM PDT 24
Peak memory 184168 kb
Host smart-5dda1a1c-0759-4344-907b-d529ba0d8e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906939545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1906939545
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2044129011
Short name T315
Test name
Test status
Simulation time 313668372 ps
CPU time 0.68 seconds
Started Jul 28 06:22:02 PM PDT 24
Finished Jul 28 06:22:03 PM PDT 24
Peak memory 184144 kb
Host smart-35df0186-ae51-49ae-8c22-956e72269e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044129011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2044129011
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2988993774
Short name T284
Test name
Test status
Simulation time 311572634 ps
CPU time 1.02 seconds
Started Jul 28 06:22:02 PM PDT 24
Finished Jul 28 06:22:03 PM PDT 24
Peak memory 193364 kb
Host smart-6dc75f03-5031-4601-ba33-80d4276e71f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988993774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2988993774
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.987852708
Short name T379
Test name
Test status
Simulation time 425662745 ps
CPU time 0.68 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:59 PM PDT 24
Peak memory 193468 kb
Host smart-4582037c-8ac6-43ce-bcc5-33b2c287433b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987852708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.987852708
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2283524194
Short name T298
Test name
Test status
Simulation time 493667947 ps
CPU time 1.15 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:59 PM PDT 24
Peak memory 184192 kb
Host smart-98ce9e31-f593-402a-a61b-d3fc1271e5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283524194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2283524194
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1063778480
Short name T340
Test name
Test status
Simulation time 554506661 ps
CPU time 0.91 seconds
Started Jul 28 06:20:51 PM PDT 24
Finished Jul 28 06:20:52 PM PDT 24
Peak memory 198876 kb
Host smart-bfa62337-8585-403b-9067-52b997f87fe8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063778480 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1063778480
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.951119303
Short name T405
Test name
Test status
Simulation time 373074336 ps
CPU time 0.71 seconds
Started Jul 28 06:20:47 PM PDT 24
Finished Jul 28 06:20:48 PM PDT 24
Peak memory 193620 kb
Host smart-ef42fa9f-5cf1-44fd-9f1a-e3ae77bc3394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951119303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.951119303
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2232642119
Short name T294
Test name
Test status
Simulation time 569557884 ps
CPU time 0.6 seconds
Started Jul 28 06:20:45 PM PDT 24
Finished Jul 28 06:20:46 PM PDT 24
Peak memory 184172 kb
Host smart-9b43b798-c9ae-4050-a176-5d2a1712db4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232642119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2232642119
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1165534070
Short name T88
Test name
Test status
Simulation time 1003792000 ps
CPU time 1.97 seconds
Started Jul 28 06:20:51 PM PDT 24
Finished Jul 28 06:20:53 PM PDT 24
Peak memory 194412 kb
Host smart-e8c7219f-3124-4eaa-afac-ab6f83dfce54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165534070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1165534070
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2368314673
Short name T301
Test name
Test status
Simulation time 358504478 ps
CPU time 1.56 seconds
Started Jul 28 06:20:46 PM PDT 24
Finished Jul 28 06:20:47 PM PDT 24
Peak memory 199016 kb
Host smart-0d317440-19a2-446f-b9b4-1ab6bd9e5126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368314673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2368314673
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3658339111
Short name T409
Test name
Test status
Simulation time 4293148340 ps
CPU time 7.59 seconds
Started Jul 28 06:20:46 PM PDT 24
Finished Jul 28 06:20:54 PM PDT 24
Peak memory 197168 kb
Host smart-c10eff34-6c9e-4b04-adbf-3ed77666dab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658339111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3658339111
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1647057768
Short name T372
Test name
Test status
Simulation time 541201997 ps
CPU time 1.47 seconds
Started Jul 28 06:20:57 PM PDT 24
Finished Jul 28 06:20:58 PM PDT 24
Peak memory 196596 kb
Host smart-3c357d38-bd85-4fc6-aea3-42770cf5c492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647057768 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1647057768
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1633310022
Short name T322
Test name
Test status
Simulation time 420979507 ps
CPU time 0.88 seconds
Started Jul 28 06:20:56 PM PDT 24
Finished Jul 28 06:20:57 PM PDT 24
Peak memory 192496 kb
Host smart-466ab9b0-15a3-4e6e-acfe-8cc13d4c4992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633310022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1633310022
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3944248836
Short name T297
Test name
Test status
Simulation time 438308323 ps
CPU time 0.64 seconds
Started Jul 28 06:20:52 PM PDT 24
Finished Jul 28 06:20:53 PM PDT 24
Peak memory 193360 kb
Host smart-f62e05a1-c1ff-4ca6-941b-7994d2292730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944248836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3944248836
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3371830114
Short name T377
Test name
Test status
Simulation time 1422664089 ps
CPU time 2.52 seconds
Started Jul 28 06:20:58 PM PDT 24
Finished Jul 28 06:21:00 PM PDT 24
Peak memory 193408 kb
Host smart-e1ea447b-f437-4ec2-8a67-28071436d072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371830114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3371830114
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.896602350
Short name T414
Test name
Test status
Simulation time 463014059 ps
CPU time 1.81 seconds
Started Jul 28 06:20:52 PM PDT 24
Finished Jul 28 06:20:54 PM PDT 24
Peak memory 199088 kb
Host smart-38005fed-90df-4616-8159-19f0a6e0b459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896602350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.896602350
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2083538154
Short name T205
Test name
Test status
Simulation time 7988480615 ps
CPU time 6.72 seconds
Started Jul 28 06:20:57 PM PDT 24
Finished Jul 28 06:21:03 PM PDT 24
Peak memory 198772 kb
Host smart-1b53e3af-3a98-4628-9f91-241cde187cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083538154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2083538154
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.346670296
Short name T329
Test name
Test status
Simulation time 505893355 ps
CPU time 1.1 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:02 PM PDT 24
Peak memory 196868 kb
Host smart-de095901-dd10-4d35-8a49-117a196cf7d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346670296 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.346670296
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1442937083
Short name T87
Test name
Test status
Simulation time 492913431 ps
CPU time 1.26 seconds
Started Jul 28 06:20:56 PM PDT 24
Finished Jul 28 06:20:58 PM PDT 24
Peak memory 193652 kb
Host smart-50664884-e458-4ef2-b039-d2863b70b238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442937083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1442937083
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2060441986
Short name T360
Test name
Test status
Simulation time 472205693 ps
CPU time 0.86 seconds
Started Jul 28 06:20:59 PM PDT 24
Finished Jul 28 06:21:00 PM PDT 24
Peak memory 184156 kb
Host smart-f7e31f52-6b8f-43cf-952e-b270ccaef23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060441986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2060441986
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.322603558
Short name T345
Test name
Test status
Simulation time 1244139294 ps
CPU time 0.75 seconds
Started Jul 28 06:20:57 PM PDT 24
Finished Jul 28 06:20:58 PM PDT 24
Peak memory 193464 kb
Host smart-c3a2bada-c2d9-41af-b161-5f80f18c4cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322603558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.322603558
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1605483842
Short name T359
Test name
Test status
Simulation time 447591075 ps
CPU time 1.88 seconds
Started Jul 28 06:20:56 PM PDT 24
Finished Jul 28 06:20:58 PM PDT 24
Peak memory 198968 kb
Host smart-91928eef-e2bd-41da-9c7c-3df8ccf12751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605483842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1605483842
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1608853952
Short name T207
Test name
Test status
Simulation time 8121561583 ps
CPU time 2.72 seconds
Started Jul 28 06:20:55 PM PDT 24
Finished Jul 28 06:20:58 PM PDT 24
Peak memory 198640 kb
Host smart-7f1c9f35-5eeb-4ab4-9777-f88354831c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608853952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1608853952
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2182903734
Short name T307
Test name
Test status
Simulation time 577773074 ps
CPU time 0.74 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:01 PM PDT 24
Peak memory 196832 kb
Host smart-1054603c-cc4d-4582-9ffc-3f501f42c708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182903734 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2182903734
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3385817168
Short name T82
Test name
Test status
Simulation time 463143331 ps
CPU time 0.73 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:02 PM PDT 24
Peak memory 193348 kb
Host smart-a77605b9-9605-4eed-b39b-fab4e0558815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385817168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3385817168
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3977118250
Short name T358
Test name
Test status
Simulation time 401000017 ps
CPU time 0.86 seconds
Started Jul 28 06:21:03 PM PDT 24
Finished Jul 28 06:21:04 PM PDT 24
Peak memory 184232 kb
Host smart-192529db-d634-483e-a87a-2f4a2b0dfc81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977118250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3977118250
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2839610437
Short name T376
Test name
Test status
Simulation time 2348705255 ps
CPU time 7.86 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:09 PM PDT 24
Peak memory 195768 kb
Host smart-728ddf16-9f0c-4d05-80fa-665078fa754d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839610437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2839610437
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.850655929
Short name T392
Test name
Test status
Simulation time 452926690 ps
CPU time 2.01 seconds
Started Jul 28 06:21:00 PM PDT 24
Finished Jul 28 06:21:02 PM PDT 24
Peak memory 199092 kb
Host smart-ba4b4603-dbe7-4fc4-bd71-9eca849342b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850655929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.850655929
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.890801266
Short name T204
Test name
Test status
Simulation time 4432633495 ps
CPU time 7.08 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:08 PM PDT 24
Peak memory 198420 kb
Host smart-ad5660e2-6d92-4c58-ba34-e058919af115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890801266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.890801266
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2424688199
Short name T400
Test name
Test status
Simulation time 565374645 ps
CPU time 0.96 seconds
Started Jul 28 06:21:06 PM PDT 24
Finished Jul 28 06:21:07 PM PDT 24
Peak memory 197396 kb
Host smart-d7b5b988-0779-480b-a98c-464458009b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424688199 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2424688199
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3814364612
Short name T367
Test name
Test status
Simulation time 482692213 ps
CPU time 0.82 seconds
Started Jul 28 06:21:06 PM PDT 24
Finished Jul 28 06:21:07 PM PDT 24
Peak memory 192480 kb
Host smart-90f03c39-5e10-4d8d-83be-d5d5d12cb7d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814364612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3814364612
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2563309926
Short name T396
Test name
Test status
Simulation time 392686175 ps
CPU time 0.58 seconds
Started Jul 28 06:21:06 PM PDT 24
Finished Jul 28 06:21:06 PM PDT 24
Peak memory 184152 kb
Host smart-c48b6c28-6906-4047-baf6-6c9946bb3ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563309926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2563309926
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1888772230
Short name T347
Test name
Test status
Simulation time 3014600404 ps
CPU time 4.63 seconds
Started Jul 28 06:21:10 PM PDT 24
Finished Jul 28 06:21:15 PM PDT 24
Peak memory 195592 kb
Host smart-fd68e216-fc90-4686-ad1f-45d9e07b6126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888772230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1888772230
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2595661331
Short name T293
Test name
Test status
Simulation time 536006237 ps
CPU time 1.39 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:02 PM PDT 24
Peak memory 199016 kb
Host smart-62b04c43-4f81-4726-857e-3225594b007b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595661331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2595661331
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2252238561
Short name T418
Test name
Test status
Simulation time 4244414769 ps
CPU time 2.32 seconds
Started Jul 28 06:21:01 PM PDT 24
Finished Jul 28 06:21:03 PM PDT 24
Peak memory 197308 kb
Host smart-69dc4134-998b-478a-887c-6d792efe4841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252238561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2252238561
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3530754192
Short name T222
Test name
Test status
Simulation time 23076320088 ps
CPU time 8.43 seconds
Started Jul 28 06:21:59 PM PDT 24
Finished Jul 28 06:22:07 PM PDT 24
Peak memory 191824 kb
Host smart-8b028df6-bd40-4935-a408-528b5fa7a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530754192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3530754192
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.56017679
Short name T15
Test name
Test status
Simulation time 528029332 ps
CPU time 0.75 seconds
Started Jul 28 06:21:58 PM PDT 24
Finished Jul 28 06:21:59 PM PDT 24
Peak memory 191712 kb
Host smart-ff14a78b-ae9f-432b-8a23-afbe92a9b9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56017679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.56017679
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2563263101
Short name T85
Test name
Test status
Simulation time 25203088440 ps
CPU time 18.55 seconds
Started Jul 28 06:22:04 PM PDT 24
Finished Jul 28 06:22:22 PM PDT 24
Peak memory 191816 kb
Host smart-61288d67-6285-4378-804d-295ea9dbc89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563263101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2563263101
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3205574768
Short name T21
Test name
Test status
Simulation time 3755417341 ps
CPU time 5.8 seconds
Started Jul 28 06:22:04 PM PDT 24
Finished Jul 28 06:22:10 PM PDT 24
Peak memory 215368 kb
Host smart-915c88c6-7b29-4e62-8589-e2b5cc8993ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205574768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3205574768
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3511983348
Short name T275
Test name
Test status
Simulation time 481215697 ps
CPU time 0.66 seconds
Started Jul 28 06:22:06 PM PDT 24
Finished Jul 28 06:22:07 PM PDT 24
Peak memory 191716 kb
Host smart-48c4fa93-761c-4d25-9948-df8b38b2ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511983348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3511983348
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1277176315
Short name T241
Test name
Test status
Simulation time 498244509 ps
CPU time 1.23 seconds
Started Jul 28 06:22:19 PM PDT 24
Finished Jul 28 06:22:21 PM PDT 24
Peak memory 191636 kb
Host smart-c9791ad6-f30c-4006-ba5d-e8d14a9585a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277176315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1277176315
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1482506853
Short name T96
Test name
Test status
Simulation time 378618745 ps
CPU time 0.7 seconds
Started Jul 28 06:22:18 PM PDT 24
Finished Jul 28 06:22:19 PM PDT 24
Peak memory 191696 kb
Host smart-1206e3ec-c935-4193-9d13-b42f98725ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482506853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1482506853
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3356943662
Short name T100
Test name
Test status
Simulation time 32066238730 ps
CPU time 25.75 seconds
Started Jul 28 06:22:23 PM PDT 24
Finished Jul 28 06:22:49 PM PDT 24
Peak memory 196828 kb
Host smart-a5673674-af31-4418-83f4-d8e72248d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356943662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3356943662
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4251756658
Short name T221
Test name
Test status
Simulation time 519494937 ps
CPU time 0.73 seconds
Started Jul 28 06:22:24 PM PDT 24
Finished Jul 28 06:22:25 PM PDT 24
Peak memory 196560 kb
Host smart-7de2011a-2ab2-46b4-a43f-12327630b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251756658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4251756658
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1700982299
Short name T201
Test name
Test status
Simulation time 462659457 ps
CPU time 0.75 seconds
Started Jul 28 06:22:28 PM PDT 24
Finished Jul 28 06:22:28 PM PDT 24
Peak memory 196516 kb
Host smart-bf07704b-1649-4183-916b-cccfed6346ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700982299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1700982299
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2237855782
Short name T86
Test name
Test status
Simulation time 37533818350 ps
CPU time 27.37 seconds
Started Jul 28 06:22:28 PM PDT 24
Finished Jul 28 06:22:56 PM PDT 24
Peak memory 191824 kb
Host smart-47a7e071-462f-4fc4-a44d-dbb5b13fc741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237855782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2237855782
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4214577834
Short name T223
Test name
Test status
Simulation time 590814582 ps
CPU time 0.65 seconds
Started Jul 28 06:22:29 PM PDT 24
Finished Jul 28 06:22:29 PM PDT 24
Peak memory 191652 kb
Host smart-e3f276a7-4170-49ab-8452-abaed393cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214577834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4214577834
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3864725595
Short name T3
Test name
Test status
Simulation time 23719198298 ps
CPU time 16.84 seconds
Started Jul 28 06:22:27 PM PDT 24
Finished Jul 28 06:22:44 PM PDT 24
Peak memory 196772 kb
Host smart-0831a529-9b2e-437a-aae6-305b02d9c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864725595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3864725595
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3261535797
Short name T6
Test name
Test status
Simulation time 524220316 ps
CPU time 0.71 seconds
Started Jul 28 06:22:27 PM PDT 24
Finished Jul 28 06:22:28 PM PDT 24
Peak memory 196548 kb
Host smart-80d25926-d3a7-4d0e-b83a-1ffbbfc2d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261535797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3261535797
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1074688580
Short name T236
Test name
Test status
Simulation time 19920866708 ps
CPU time 2.46 seconds
Started Jul 28 06:22:35 PM PDT 24
Finished Jul 28 06:22:38 PM PDT 24
Peak memory 191796 kb
Host smart-84161b73-cb97-4b6f-8e13-fee80ef405dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074688580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1074688580
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3372030702
Short name T261
Test name
Test status
Simulation time 390228232 ps
CPU time 1.13 seconds
Started Jul 28 06:22:33 PM PDT 24
Finished Jul 28 06:22:35 PM PDT 24
Peak memory 191720 kb
Host smart-2cb08995-a552-45df-be60-9d083163c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372030702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3372030702
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3354528857
Short name T270
Test name
Test status
Simulation time 35684622242 ps
CPU time 13.61 seconds
Started Jul 28 06:22:33 PM PDT 24
Finished Jul 28 06:22:47 PM PDT 24
Peak memory 196808 kb
Host smart-bf11c431-80f8-44f0-a335-b522f3bfaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354528857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3354528857
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.526723767
Short name T214
Test name
Test status
Simulation time 461137821 ps
CPU time 1.2 seconds
Started Jul 28 06:22:34 PM PDT 24
Finished Jul 28 06:22:35 PM PDT 24
Peak memory 191696 kb
Host smart-685b1a3b-fe86-412c-b073-0f6a2e8e1b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526723767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.526723767
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1138607048
Short name T235
Test name
Test status
Simulation time 8164143547 ps
CPU time 12.4 seconds
Started Jul 28 06:22:38 PM PDT 24
Finished Jul 28 06:22:51 PM PDT 24
Peak memory 191792 kb
Host smart-17dc8d12-7208-4d6f-9514-ea6b7038b157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138607048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1138607048
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1694820890
Short name T34
Test name
Test status
Simulation time 607719204 ps
CPU time 0.98 seconds
Started Jul 28 06:22:38 PM PDT 24
Finished Jul 28 06:22:39 PM PDT 24
Peak memory 196536 kb
Host smart-f89ec619-9d69-4539-b962-eb88b80d68c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694820890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1694820890
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1771019662
Short name T84
Test name
Test status
Simulation time 20542528184 ps
CPU time 145.42 seconds
Started Jul 28 06:22:40 PM PDT 24
Finished Jul 28 06:25:05 PM PDT 24
Peak memory 206660 kb
Host smart-80e7a5ac-3abb-45dc-a82c-acb8a763cc66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771019662 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1771019662
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2744453453
Short name T16
Test name
Test status
Simulation time 5913685694 ps
CPU time 2.33 seconds
Started Jul 28 06:22:43 PM PDT 24
Finished Jul 28 06:22:46 PM PDT 24
Peak memory 191744 kb
Host smart-c4a0e6d8-cb94-4260-b94b-81fc49c9be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744453453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2744453453
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1332295070
Short name T216
Test name
Test status
Simulation time 676717628 ps
CPU time 0.65 seconds
Started Jul 28 06:22:44 PM PDT 24
Finished Jul 28 06:22:45 PM PDT 24
Peak memory 196552 kb
Host smart-1df16ea6-1b95-4b9f-a1f0-106399c1da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332295070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1332295070
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.604680046
Short name T228
Test name
Test status
Simulation time 39560384870 ps
CPU time 14.28 seconds
Started Jul 28 06:22:42 PM PDT 24
Finished Jul 28 06:22:56 PM PDT 24
Peak memory 191820 kb
Host smart-2caf58d6-7dc4-4b5a-99ae-2ceb61f56bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604680046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.604680046
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2041817506
Short name T239
Test name
Test status
Simulation time 445292373 ps
CPU time 0.76 seconds
Started Jul 28 06:22:44 PM PDT 24
Finished Jul 28 06:22:45 PM PDT 24
Peak memory 196428 kb
Host smart-f9cd7ea5-8169-41bc-84c6-327dcfee27f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041817506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2041817506
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3697278639
Short name T234
Test name
Test status
Simulation time 2654162089 ps
CPU time 4.27 seconds
Started Jul 28 06:22:49 PM PDT 24
Finished Jul 28 06:22:53 PM PDT 24
Peak memory 191804 kb
Host smart-725c5e59-c44e-4769-8957-3b2ac89560cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697278639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3697278639
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1747923785
Short name T215
Test name
Test status
Simulation time 550843202 ps
CPU time 0.76 seconds
Started Jul 28 06:22:48 PM PDT 24
Finished Jul 28 06:22:49 PM PDT 24
Peak memory 196552 kb
Host smart-7a865eb2-6b24-46f1-a8e9-3a7a1ba5d95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747923785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1747923785
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.165422329
Short name T182
Test name
Test status
Simulation time 512705822 ps
CPU time 0.79 seconds
Started Jul 28 06:22:08 PM PDT 24
Finished Jul 28 06:22:09 PM PDT 24
Peak memory 196480 kb
Host smart-33ba9cb6-a8ac-49ba-bed4-681e678026a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165422329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.165422329
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.231929676
Short name T265
Test name
Test status
Simulation time 27736774837 ps
CPU time 8.86 seconds
Started Jul 28 06:22:04 PM PDT 24
Finished Jul 28 06:22:13 PM PDT 24
Peak memory 191824 kb
Host smart-5361de5f-a5bc-493e-9711-f11ac5d2830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231929676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.231929676
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3277798751
Short name T23
Test name
Test status
Simulation time 4599125027 ps
CPU time 5.36 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:22:15 PM PDT 24
Peak memory 215712 kb
Host smart-e9aae1b2-6e7d-416d-867a-8ed38817729a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277798751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3277798751
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.590645948
Short name T274
Test name
Test status
Simulation time 424281558 ps
CPU time 0.81 seconds
Started Jul 28 06:22:04 PM PDT 24
Finished Jul 28 06:22:05 PM PDT 24
Peak memory 196536 kb
Host smart-e03751c5-4824-4859-a1e3-58b258d050df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590645948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.590645948
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3558464586
Short name T203
Test name
Test status
Simulation time 508910477 ps
CPU time 1.29 seconds
Started Jul 28 06:22:50 PM PDT 24
Finished Jul 28 06:22:52 PM PDT 24
Peak memory 196520 kb
Host smart-b1bd674b-6c50-44f1-9cbc-53ee2ab4c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558464586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3558464586
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1089632252
Short name T237
Test name
Test status
Simulation time 24594857120 ps
CPU time 34.4 seconds
Started Jul 28 06:22:49 PM PDT 24
Finished Jul 28 06:23:23 PM PDT 24
Peak memory 196832 kb
Host smart-95531df4-1e9c-4359-acba-1d58e801cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089632252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1089632252
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2701743604
Short name T246
Test name
Test status
Simulation time 488031410 ps
CPU time 1.2 seconds
Started Jul 28 06:22:49 PM PDT 24
Finished Jul 28 06:22:50 PM PDT 24
Peak memory 196520 kb
Host smart-c62f4091-11cd-4435-b138-cb78a4c17eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701743604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2701743604
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.634337680
Short name T254
Test name
Test status
Simulation time 791446232 ps
CPU time 1.84 seconds
Started Jul 28 06:22:49 PM PDT 24
Finished Jul 28 06:22:51 PM PDT 24
Peak memory 196428 kb
Host smart-a0254185-8cd9-4a0b-83af-f7b2279c4601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634337680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.634337680
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1889951628
Short name T220
Test name
Test status
Simulation time 382949253 ps
CPU time 0.67 seconds
Started Jul 28 06:22:49 PM PDT 24
Finished Jul 28 06:22:50 PM PDT 24
Peak memory 196504 kb
Host smart-1d6c78a8-eea0-4c2c-b23b-d5c0501d58c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889951628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1889951628
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2680151555
Short name T271
Test name
Test status
Simulation time 19707899998 ps
CPU time 15.24 seconds
Started Jul 28 06:22:54 PM PDT 24
Finished Jul 28 06:23:09 PM PDT 24
Peak memory 191820 kb
Host smart-8f970338-b834-4989-b832-2ec5967b8a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680151555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2680151555
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1840544352
Short name T253
Test name
Test status
Simulation time 605182273 ps
CPU time 0.85 seconds
Started Jul 28 06:22:51 PM PDT 24
Finished Jul 28 06:22:52 PM PDT 24
Peak memory 191664 kb
Host smart-80f4bdb0-077a-4e59-839d-40bb56a12320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840544352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1840544352
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3784083666
Short name T94
Test name
Test status
Simulation time 10383362345 ps
CPU time 4.48 seconds
Started Jul 28 06:22:55 PM PDT 24
Finished Jul 28 06:23:00 PM PDT 24
Peak memory 196816 kb
Host smart-f2edcbe0-da6c-4c8d-a4ab-fb97b79163ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784083666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3784083666
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.764452621
Short name T250
Test name
Test status
Simulation time 395624668 ps
CPU time 0.86 seconds
Started Jul 28 06:22:54 PM PDT 24
Finished Jul 28 06:22:55 PM PDT 24
Peak memory 191664 kb
Host smart-126a604f-59f9-4f2a-99c5-9b99367633b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764452621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.764452621
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.153911112
Short name T210
Test name
Test status
Simulation time 39327967158 ps
CPU time 12.9 seconds
Started Jul 28 06:22:53 PM PDT 24
Finished Jul 28 06:23:06 PM PDT 24
Peak memory 191760 kb
Host smart-9db2071f-cab6-46d3-be81-db1ba0433040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153911112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.153911112
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4267309787
Short name T282
Test name
Test status
Simulation time 432994104 ps
CPU time 0.9 seconds
Started Jul 28 06:22:54 PM PDT 24
Finished Jul 28 06:22:55 PM PDT 24
Peak memory 196552 kb
Host smart-f2383853-e0a0-4635-8e2c-ae4d395e1a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267309787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4267309787
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1081663810
Short name T248
Test name
Test status
Simulation time 21010184532 ps
CPU time 15.98 seconds
Started Jul 28 06:22:58 PM PDT 24
Finished Jul 28 06:23:14 PM PDT 24
Peak memory 191868 kb
Host smart-4d25bd7c-addc-460b-9625-9222daf5d2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081663810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1081663810
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2557224761
Short name T238
Test name
Test status
Simulation time 461521117 ps
CPU time 0.68 seconds
Started Jul 28 06:23:01 PM PDT 24
Finished Jul 28 06:23:01 PM PDT 24
Peak memory 196532 kb
Host smart-a61ab02f-28f8-44fd-80e3-ca8e240478b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557224761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2557224761
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3581012478
Short name T230
Test name
Test status
Simulation time 24715562283 ps
CPU time 19.81 seconds
Started Jul 28 06:23:02 PM PDT 24
Finished Jul 28 06:23:22 PM PDT 24
Peak memory 191836 kb
Host smart-8b764fa4-defe-4c78-b812-250881a3ff82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581012478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3581012478
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.283356854
Short name T260
Test name
Test status
Simulation time 459986602 ps
CPU time 1.13 seconds
Started Jul 28 06:23:02 PM PDT 24
Finished Jul 28 06:23:04 PM PDT 24
Peak memory 191652 kb
Host smart-888cd37a-6685-4a74-aae1-d20b601edc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283356854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.283356854
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2623560084
Short name T50
Test name
Test status
Simulation time 231314727356 ps
CPU time 429.67 seconds
Started Jul 28 06:23:11 PM PDT 24
Finished Jul 28 06:30:20 PM PDT 24
Peak memory 214808 kb
Host smart-08f2e206-95be-4db9-91c6-5eb67e4a992a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623560084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2623560084
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3358838308
Short name T188
Test name
Test status
Simulation time 502995720 ps
CPU time 0.63 seconds
Started Jul 28 06:23:08 PM PDT 24
Finished Jul 28 06:23:09 PM PDT 24
Peak memory 196472 kb
Host smart-bc00fa1b-abbd-4dd5-a21d-0b5fe385ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358838308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3358838308
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2144347919
Short name T4
Test name
Test status
Simulation time 13164724704 ps
CPU time 20.6 seconds
Started Jul 28 06:23:09 PM PDT 24
Finished Jul 28 06:23:29 PM PDT 24
Peak memory 191828 kb
Host smart-30cb5164-d63a-4481-9bdf-45a2e5110b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144347919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2144347919
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1560573190
Short name T65
Test name
Test status
Simulation time 458411172 ps
CPU time 0.9 seconds
Started Jul 28 06:23:08 PM PDT 24
Finished Jul 28 06:23:09 PM PDT 24
Peak memory 196564 kb
Host smart-bb5f3a27-5372-4615-937d-2efc1742936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560573190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1560573190
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3201172437
Short name T32
Test name
Test status
Simulation time 16000087236 ps
CPU time 22.75 seconds
Started Jul 28 06:23:13 PM PDT 24
Finished Jul 28 06:23:36 PM PDT 24
Peak memory 191756 kb
Host smart-01982deb-e65e-4b8c-afba-8cd1df30231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201172437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3201172437
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3818627713
Short name T225
Test name
Test status
Simulation time 580882894 ps
CPU time 0.8 seconds
Started Jul 28 06:23:16 PM PDT 24
Finished Jul 28 06:23:17 PM PDT 24
Peak memory 191668 kb
Host smart-9ef4bc7e-acba-43f6-bb16-d486f905eabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818627713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3818627713
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1124189277
Short name T273
Test name
Test status
Simulation time 38743781138 ps
CPU time 6.05 seconds
Started Jul 28 06:23:17 PM PDT 24
Finished Jul 28 06:23:23 PM PDT 24
Peak memory 191800 kb
Host smart-f760e5ca-7607-4e2a-b8e7-d1d15cd4fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124189277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1124189277
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2022616430
Short name T247
Test name
Test status
Simulation time 546751187 ps
CPU time 0.72 seconds
Started Jul 28 06:23:19 PM PDT 24
Finished Jul 28 06:23:20 PM PDT 24
Peak memory 191700 kb
Host smart-c31a27fe-85fc-4e55-8354-7a6145a9b774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022616430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2022616430
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3316859616
Short name T269
Test name
Test status
Simulation time 1452726102 ps
CPU time 1.13 seconds
Started Jul 28 06:22:13 PM PDT 24
Finished Jul 28 06:22:14 PM PDT 24
Peak memory 191908 kb
Host smart-90ae7ccc-1f5a-4a92-b905-1478db0db427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316859616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3316859616
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1308990198
Short name T22
Test name
Test status
Simulation time 7794340533 ps
CPU time 3.36 seconds
Started Jul 28 06:22:11 PM PDT 24
Finished Jul 28 06:22:14 PM PDT 24
Peak memory 215796 kb
Host smart-097d5134-575f-4a3e-8a4f-5dbdc7384596
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308990198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1308990198
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2622042069
Short name T242
Test name
Test status
Simulation time 411904648 ps
CPU time 1.12 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:22:10 PM PDT 24
Peak memory 196456 kb
Host smart-e55ce443-7c22-4887-8a03-e1f8e074453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622042069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2622042069
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1220211224
Short name T244
Test name
Test status
Simulation time 33186935545 ps
CPU time 48.15 seconds
Started Jul 28 06:23:17 PM PDT 24
Finished Jul 28 06:24:05 PM PDT 24
Peak memory 191824 kb
Host smart-bc539de7-8f46-4f2f-b91e-7b580ade3622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220211224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1220211224
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1179495376
Short name T99
Test name
Test status
Simulation time 575550210 ps
CPU time 0.76 seconds
Started Jul 28 06:23:17 PM PDT 24
Finished Jul 28 06:23:18 PM PDT 24
Peak memory 191648 kb
Host smart-6c02a732-5859-467d-bab3-ab8f7bcd0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179495376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1179495376
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4290089745
Short name T53
Test name
Test status
Simulation time 8412933714 ps
CPU time 8.8 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:23:35 PM PDT 24
Peak memory 196792 kb
Host smart-1fcd41f2-9824-4ab0-9262-e125526bc925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290089745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4290089745
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3268845283
Short name T26
Test name
Test status
Simulation time 580854216 ps
CPU time 1.32 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:23:27 PM PDT 24
Peak memory 191660 kb
Host smart-e24693ca-7378-4d02-9b1e-142a88f18ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268845283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3268845283
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4084603843
Short name T280
Test name
Test status
Simulation time 9657438139 ps
CPU time 14.23 seconds
Started Jul 28 06:23:24 PM PDT 24
Finished Jul 28 06:23:39 PM PDT 24
Peak memory 191788 kb
Host smart-1453ef9c-9642-4d33-ab49-ea2ad90055bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084603843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4084603843
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.692561180
Short name T278
Test name
Test status
Simulation time 385365267 ps
CPU time 0.71 seconds
Started Jul 28 06:23:24 PM PDT 24
Finished Jul 28 06:23:25 PM PDT 24
Peak memory 191660 kb
Host smart-f1f7cce8-1adf-4e43-a7b4-a6043c848276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692561180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.692561180
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2973943141
Short name T156
Test name
Test status
Simulation time 571308195 ps
CPU time 0.82 seconds
Started Jul 28 06:23:27 PM PDT 24
Finished Jul 28 06:23:28 PM PDT 24
Peak memory 196576 kb
Host smart-72a71e6b-c515-4cc8-aa1a-6d0ee416a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973943141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2973943141
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3918624881
Short name T255
Test name
Test status
Simulation time 54877334000 ps
CPU time 35.93 seconds
Started Jul 28 06:23:27 PM PDT 24
Finished Jul 28 06:24:03 PM PDT 24
Peak memory 191808 kb
Host smart-e1afc7f2-f6a7-4136-a483-52bc21689ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918624881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3918624881
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.753558877
Short name T64
Test name
Test status
Simulation time 437453506 ps
CPU time 0.69 seconds
Started Jul 28 06:23:26 PM PDT 24
Finished Jul 28 06:23:27 PM PDT 24
Peak memory 191656 kb
Host smart-61281f90-c4cc-4b70-9f69-d8db0c75a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753558877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.753558877
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4135395732
Short name T218
Test name
Test status
Simulation time 26304962642 ps
CPU time 20.62 seconds
Started Jul 28 06:23:27 PM PDT 24
Finished Jul 28 06:23:48 PM PDT 24
Peak memory 191848 kb
Host smart-a1967c89-08e3-489b-a49e-e1db9a3d97fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135395732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4135395732
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.565859786
Short name T279
Test name
Test status
Simulation time 382379098 ps
CPU time 0.67 seconds
Started Jul 28 06:23:27 PM PDT 24
Finished Jul 28 06:23:28 PM PDT 24
Peak memory 191704 kb
Host smart-52e23221-fdf7-4407-a767-9c81fdee47d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565859786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.565859786
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2651003703
Short name T276
Test name
Test status
Simulation time 28248777433 ps
CPU time 36.51 seconds
Started Jul 28 06:23:33 PM PDT 24
Finished Jul 28 06:24:09 PM PDT 24
Peak memory 191776 kb
Host smart-5a7d5d8b-aa48-4d74-8fbe-ec6c7a4b28a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651003703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2651003703
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.225206824
Short name T257
Test name
Test status
Simulation time 443431262 ps
CPU time 0.65 seconds
Started Jul 28 06:23:32 PM PDT 24
Finished Jul 28 06:23:32 PM PDT 24
Peak memory 196500 kb
Host smart-6cd3416c-9404-43d3-9217-65484ff1474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225206824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.225206824
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3358220608
Short name T9
Test name
Test status
Simulation time 361435817 ps
CPU time 0.69 seconds
Started Jul 28 06:23:37 PM PDT 24
Finished Jul 28 06:23:38 PM PDT 24
Peak memory 196488 kb
Host smart-7ff2c5c7-11c7-4e0d-98bc-d1b1cb68c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358220608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3358220608
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1982053540
Short name T29
Test name
Test status
Simulation time 37201544353 ps
CPU time 55.31 seconds
Started Jul 28 06:23:37 PM PDT 24
Finished Jul 28 06:24:33 PM PDT 24
Peak memory 196792 kb
Host smart-68667b05-9e9f-4ad2-93ec-4bc2a97fbe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982053540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1982053540
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1631950032
Short name T232
Test name
Test status
Simulation time 519906915 ps
CPU time 0.73 seconds
Started Jul 28 06:23:37 PM PDT 24
Finished Jul 28 06:23:37 PM PDT 24
Peak memory 191704 kb
Host smart-9a9422fc-bfdf-4449-b302-943b1a4860e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631950032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1631950032
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2322174984
Short name T267
Test name
Test status
Simulation time 11577457761 ps
CPU time 18.27 seconds
Started Jul 28 06:23:39 PM PDT 24
Finished Jul 28 06:23:57 PM PDT 24
Peak memory 191800 kb
Host smart-320c702c-aae5-4165-ba74-3e739dc835f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322174984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2322174984
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.590372639
Short name T251
Test name
Test status
Simulation time 412241636 ps
CPU time 0.68 seconds
Started Jul 28 06:23:37 PM PDT 24
Finished Jul 28 06:23:38 PM PDT 24
Peak memory 196496 kb
Host smart-716115f6-a18d-496f-b9bb-29a94cca7172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590372639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.590372639
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.257228333
Short name T98
Test name
Test status
Simulation time 29944024378 ps
CPU time 37.82 seconds
Started Jul 28 06:23:42 PM PDT 24
Finished Jul 28 06:24:20 PM PDT 24
Peak memory 191844 kb
Host smart-7315fa52-8a36-4a5b-b71a-d03117b34e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257228333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.257228333
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3561568992
Short name T213
Test name
Test status
Simulation time 412703272 ps
CPU time 1.13 seconds
Started Jul 28 06:23:45 PM PDT 24
Finished Jul 28 06:23:46 PM PDT 24
Peak memory 196416 kb
Host smart-f38da448-f310-4a16-a04b-a7ac7d881fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561568992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3561568992
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.329905758
Short name T240
Test name
Test status
Simulation time 58986107227 ps
CPU time 5.22 seconds
Started Jul 28 06:23:49 PM PDT 24
Finished Jul 28 06:23:54 PM PDT 24
Peak memory 191792 kb
Host smart-8c6ea0cc-323e-4e57-8549-1e80f8468f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329905758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.329905758
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4108115039
Short name T83
Test name
Test status
Simulation time 497917920 ps
CPU time 0.69 seconds
Started Jul 28 06:23:46 PM PDT 24
Finished Jul 28 06:23:47 PM PDT 24
Peak memory 191756 kb
Host smart-97540a34-367e-41d6-94ba-c71ca0afecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108115039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4108115039
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2102314626
Short name T28
Test name
Test status
Simulation time 18615820841 ps
CPU time 5.63 seconds
Started Jul 28 06:22:11 PM PDT 24
Finished Jul 28 06:22:16 PM PDT 24
Peak memory 196888 kb
Host smart-c4fef1af-c809-41be-bce0-141c54e48708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102314626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2102314626
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1400350447
Short name T20
Test name
Test status
Simulation time 4083208854 ps
CPU time 6.12 seconds
Started Jul 28 06:22:09 PM PDT 24
Finished Jul 28 06:22:15 PM PDT 24
Peak memory 215356 kb
Host smart-f60f0979-2979-49ee-92ca-d559e45c4187
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400350447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1400350447
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3805877834
Short name T264
Test name
Test status
Simulation time 408686583 ps
CPU time 0.71 seconds
Started Jul 28 06:22:08 PM PDT 24
Finished Jul 28 06:22:09 PM PDT 24
Peak memory 191700 kb
Host smart-91317dd6-9335-481b-9f00-e980932c0bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805877834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3805877834
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.169708703
Short name T194
Test name
Test status
Simulation time 504403525 ps
CPU time 1.17 seconds
Started Jul 28 06:23:54 PM PDT 24
Finished Jul 28 06:23:55 PM PDT 24
Peak memory 196512 kb
Host smart-2596fdc1-e335-4fab-ae4b-e1d0522a60ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169708703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.169708703
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3645499778
Short name T13
Test name
Test status
Simulation time 21348370973 ps
CPU time 23.73 seconds
Started Jul 28 06:23:50 PM PDT 24
Finished Jul 28 06:24:14 PM PDT 24
Peak memory 191772 kb
Host smart-8c4f134f-3b3b-45d3-b881-50a6dfe56ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645499778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3645499778
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3657153684
Short name T252
Test name
Test status
Simulation time 434833867 ps
CPU time 1.15 seconds
Started Jul 28 06:23:50 PM PDT 24
Finished Jul 28 06:23:51 PM PDT 24
Peak memory 191708 kb
Host smart-c1d43885-7f9b-4729-8015-b74a3497b76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657153684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3657153684
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2436604441
Short name T226
Test name
Test status
Simulation time 47850216200 ps
CPU time 16.92 seconds
Started Jul 28 06:23:49 PM PDT 24
Finished Jul 28 06:24:06 PM PDT 24
Peak memory 191824 kb
Host smart-b72f9898-3c99-4195-ad0c-cb38c4495c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436604441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2436604441
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2702808904
Short name T217
Test name
Test status
Simulation time 495344021 ps
CPU time 1.27 seconds
Started Jul 28 06:23:50 PM PDT 24
Finished Jul 28 06:23:52 PM PDT 24
Peak memory 191668 kb
Host smart-3b98a140-75ef-448a-82d2-2a2106665290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702808904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2702808904
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4248983776
Short name T200
Test name
Test status
Simulation time 218178037112 ps
CPU time 336.27 seconds
Started Jul 28 06:23:57 PM PDT 24
Finished Jul 28 06:29:33 PM PDT 24
Peak memory 192564 kb
Host smart-4c65df86-fc28-485b-9a22-080b49b9ca41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248983776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4248983776
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3874475105
Short name T63
Test name
Test status
Simulation time 35442437041 ps
CPU time 54.76 seconds
Started Jul 28 06:23:56 PM PDT 24
Finished Jul 28 06:24:51 PM PDT 24
Peak memory 191824 kb
Host smart-9db2695b-4c5f-4b4e-bbff-c606d33eb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874475105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3874475105
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.442152066
Short name T231
Test name
Test status
Simulation time 551907066 ps
CPU time 1.39 seconds
Started Jul 28 06:23:55 PM PDT 24
Finished Jul 28 06:23:56 PM PDT 24
Peak memory 191700 kb
Host smart-cb894f5e-0f4b-4be1-ab9b-b43f59e44583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442152066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.442152066
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.160940473
Short name T256
Test name
Test status
Simulation time 37701795796 ps
CPU time 36.16 seconds
Started Jul 28 06:24:05 PM PDT 24
Finished Jul 28 06:24:41 PM PDT 24
Peak memory 196872 kb
Host smart-ef6cc5d5-f4cc-4324-a678-4ca9939db233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160940473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.160940473
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2542084891
Short name T229
Test name
Test status
Simulation time 592876158 ps
CPU time 1.27 seconds
Started Jul 28 06:23:54 PM PDT 24
Finished Jul 28 06:23:55 PM PDT 24
Peak memory 191700 kb
Host smart-da248ae0-01ed-456b-b62a-64b17eda503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542084891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2542084891
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3069924040
Short name T59
Test name
Test status
Simulation time 40271457686 ps
CPU time 61.64 seconds
Started Jul 28 06:24:03 PM PDT 24
Finished Jul 28 06:25:05 PM PDT 24
Peak memory 191840 kb
Host smart-5e35740b-db60-47c2-bfc2-a25370c26651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069924040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3069924040
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.741130355
Short name T245
Test name
Test status
Simulation time 570186703 ps
CPU time 0.76 seconds
Started Jul 28 06:24:02 PM PDT 24
Finished Jul 28 06:24:03 PM PDT 24
Peak memory 191648 kb
Host smart-a0fff8c8-32cf-4cfe-8c30-0e3a756989a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741130355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.741130355
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2407380741
Short name T263
Test name
Test status
Simulation time 19880503764 ps
CPU time 26.3 seconds
Started Jul 28 06:24:09 PM PDT 24
Finished Jul 28 06:24:35 PM PDT 24
Peak memory 191824 kb
Host smart-36240592-2969-4207-bafc-0ccc4be9b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407380741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2407380741
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2012113980
Short name T10
Test name
Test status
Simulation time 539681840 ps
CPU time 0.64 seconds
Started Jul 28 06:24:06 PM PDT 24
Finished Jul 28 06:24:06 PM PDT 24
Peak memory 191684 kb
Host smart-564e5536-888d-4fc9-bba3-16eb08d542fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012113980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2012113980
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3846570756
Short name T12
Test name
Test status
Simulation time 382458173 ps
CPU time 0.86 seconds
Started Jul 28 06:24:12 PM PDT 24
Finished Jul 28 06:24:13 PM PDT 24
Peak memory 196628 kb
Host smart-f07e39e8-171c-44d0-99a0-92bb071e299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846570756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3846570756
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.520791996
Short name T272
Test name
Test status
Simulation time 17387511404 ps
CPU time 25.32 seconds
Started Jul 28 06:24:06 PM PDT 24
Finished Jul 28 06:24:31 PM PDT 24
Peak memory 191840 kb
Host smart-f666c784-ebb6-45e1-88b7-3d7be684a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520791996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.520791996
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2153396735
Short name T2
Test name
Test status
Simulation time 532944032 ps
CPU time 0.97 seconds
Started Jul 28 06:24:04 PM PDT 24
Finished Jul 28 06:24:05 PM PDT 24
Peak memory 191684 kb
Host smart-3cf4e5dc-6de7-4ebc-a436-f58dfc70401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153396735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2153396735
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2398873308
Short name T262
Test name
Test status
Simulation time 1096030847 ps
CPU time 2.16 seconds
Started Jul 28 06:24:11 PM PDT 24
Finished Jul 28 06:24:13 PM PDT 24
Peak memory 196400 kb
Host smart-3c9e1e91-d14c-43f5-a43b-d449150673b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398873308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2398873308
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.664186102
Short name T266
Test name
Test status
Simulation time 401585008 ps
CPU time 1.17 seconds
Started Jul 28 06:24:11 PM PDT 24
Finished Jul 28 06:24:12 PM PDT 24
Peak memory 191728 kb
Host smart-16a92d45-c825-4003-9eaa-986849d1e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664186102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.664186102
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.788351868
Short name T62
Test name
Test status
Simulation time 475341790 ps
CPU time 0.77 seconds
Started Jul 28 06:24:20 PM PDT 24
Finished Jul 28 06:24:21 PM PDT 24
Peak memory 196488 kb
Host smart-74c3ccb4-d6f9-459b-9d99-f44e3c6007c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788351868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.788351868
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4086219012
Short name T258
Test name
Test status
Simulation time 59368624475 ps
CPU time 14.9 seconds
Started Jul 28 06:24:21 PM PDT 24
Finished Jul 28 06:24:36 PM PDT 24
Peak memory 191776 kb
Host smart-e3acd46a-1722-42c1-937a-d7b5155a2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086219012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4086219012
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2799614373
Short name T224
Test name
Test status
Simulation time 430251659 ps
CPU time 1.2 seconds
Started Jul 28 06:24:20 PM PDT 24
Finished Jul 28 06:24:21 PM PDT 24
Peak memory 191748 kb
Host smart-630d4e78-93ab-49ff-9238-e5976ca1c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799614373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2799614373
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2447195464
Short name T249
Test name
Test status
Simulation time 38580669934 ps
CPU time 14.35 seconds
Started Jul 28 06:24:21 PM PDT 24
Finished Jul 28 06:24:35 PM PDT 24
Peak memory 196748 kb
Host smart-49d5666c-48e9-40e5-a6a3-5e08b8d4dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447195464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2447195464
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3323568386
Short name T227
Test name
Test status
Simulation time 463613768 ps
CPU time 1.26 seconds
Started Jul 28 06:24:21 PM PDT 24
Finished Jul 28 06:24:23 PM PDT 24
Peak memory 191744 kb
Host smart-51bccc7d-8c12-48b0-b865-6d9f2da6c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323568386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3323568386
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.50836969
Short name T54
Test name
Test status
Simulation time 2330420895 ps
CPU time 1.24 seconds
Started Jul 28 06:22:12 PM PDT 24
Finished Jul 28 06:22:13 PM PDT 24
Peak memory 191696 kb
Host smart-a3470ed9-a35a-434a-ab8b-dfbb841cdf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50836969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.50836969
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3633490800
Short name T56
Test name
Test status
Simulation time 540651428 ps
CPU time 1.43 seconds
Started Jul 28 06:22:21 PM PDT 24
Finished Jul 28 06:22:23 PM PDT 24
Peak memory 196488 kb
Host smart-e6cc2cdf-0c7b-4f55-8269-5492f8fc7789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633490800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3633490800
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1748353494
Short name T281
Test name
Test status
Simulation time 40263857366 ps
CPU time 27.24 seconds
Started Jul 28 06:22:13 PM PDT 24
Finished Jul 28 06:22:40 PM PDT 24
Peak memory 191800 kb
Host smart-65bcfbff-4727-49eb-b0e8-bc9bec589ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748353494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1748353494
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1217199900
Short name T243
Test name
Test status
Simulation time 488325617 ps
CPU time 1.32 seconds
Started Jul 28 06:22:14 PM PDT 24
Finished Jul 28 06:22:15 PM PDT 24
Peak memory 196600 kb
Host smart-5e622fa1-de3a-4e9e-8853-133fc0f1df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217199900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1217199900
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2553462598
Short name T197
Test name
Test status
Simulation time 353511385 ps
CPU time 1.11 seconds
Started Jul 28 06:22:13 PM PDT 24
Finished Jul 28 06:22:14 PM PDT 24
Peak memory 196440 kb
Host smart-a9c689d3-ad2a-4ea2-899a-85ffe4924148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553462598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2553462598
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3044679402
Short name T233
Test name
Test status
Simulation time 60938760217 ps
CPU time 66.55 seconds
Started Jul 28 06:22:12 PM PDT 24
Finished Jul 28 06:23:19 PM PDT 24
Peak memory 191824 kb
Host smart-0f8f5919-9929-410a-a2bd-dafb4cae1f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044679402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3044679402
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3511474788
Short name T268
Test name
Test status
Simulation time 386299615 ps
CPU time 1.12 seconds
Started Jul 28 06:22:12 PM PDT 24
Finished Jul 28 06:22:14 PM PDT 24
Peak memory 191680 kb
Host smart-47f7679f-006f-41df-af35-0a31f5c24699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511474788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3511474788
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1950888524
Short name T209
Test name
Test status
Simulation time 24426979992 ps
CPU time 9.56 seconds
Started Jul 28 06:22:19 PM PDT 24
Finished Jul 28 06:22:29 PM PDT 24
Peak memory 191780 kb
Host smart-3ce29b29-22a9-4312-b8c0-7bcbea036a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950888524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1950888524
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1851533096
Short name T219
Test name
Test status
Simulation time 609674945 ps
CPU time 0.68 seconds
Started Jul 28 06:22:18 PM PDT 24
Finished Jul 28 06:22:18 PM PDT 24
Peak memory 191708 kb
Host smart-a55f8240-2910-45fa-9402-73deb6fc629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851533096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1851533096
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.941023614
Short name T259
Test name
Test status
Simulation time 32927951061 ps
CPU time 47.62 seconds
Started Jul 28 06:22:18 PM PDT 24
Finished Jul 28 06:23:06 PM PDT 24
Peak memory 191828 kb
Host smart-baf2c54e-970a-4baa-99c9-8aef5f54aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941023614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.941023614
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1691832059
Short name T277
Test name
Test status
Simulation time 471956135 ps
CPU time 0.7 seconds
Started Jul 28 06:22:19 PM PDT 24
Finished Jul 28 06:22:19 PM PDT 24
Peak memory 196452 kb
Host smart-8a2d7f33-ee67-4f71-a97e-c7d37f86bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691832059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1691832059
Directory /workspace/9.aon_timer_smoke/latest
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