Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26426	1		T1	10		T2	11		T3	11
bark[1]	401	1		T5	40		T95	72		T37	21
bark[2]	313	1		T10	21		T39	30		T40	21
bark[3]	304	1		T142	14		T27	7		T97	21
bark[4]	484	1		T4	21		T10	14		T37	43
bark[5]	476	1		T9	21		T111	26		T104	21
bark[6]	1532	1		T5	21		T111	30		T143	74
bark[7]	914	1		T98	14		T102	40		T27	26
bark[8]	641	1		T29	40		T111	30		T95	21
bark[9]	519	1		T9	30		T29	7		T103	30
bark[10]	474	1		T121	14		T95	21		T118	21
bark[11]	239	1		T54	26		T88	26		T150	21
bark[12]	651	1		T4	52		T111	21		T37	182
bark[13]	506	1		T143	42		T38	85		T126	21
bark[14]	478	1		T137	26		T130	14		T143	114
bark[15]	236	1		T29	21		T155	14		T134	14
bark[16]	592	1		T9	82		T13	21		T103	35
bark[17]	847	1		T12	14		T29	7		T137	21
bark[18]	459	1		T95	21		T103	21		T39	39
bark[19]	571	1		T103	42		T134	21		T27	21
bark[20]	475	1		T11	14		T137	21		T97	26
bark[21]	263	1		T155	21		T142	21		T26	14
bark[22]	507	1		T29	21		T184	14		T19	52
bark[23]	259	1		T143	21		T142	21		T106	47
bark[24]	661	1		T4	21		T30	47		T104	21
bark[25]	452	1		T45	14		T155	21		T37	134
bark[26]	305	1		T30	44		T143	21		T19	21
bark[27]	488	1		T137	21		T103	21		T38	5
bark[28]	131	1		T118	51		T27	21		T141	38
bark[29]	1844	1		T175	42		T37	26		T27	132
bark[30]	530	1		T9	42		T30	35		T37	21
bark[31]	672	1		T19	249		T40	7		T49	68
bark_0	4223	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26167	1		T1	9		T2	10		T3	10
bite[1]	368	1		T9	30		T156	13		T55	50
bite[2]	455	1		T95	21		T38	63		T122	4
bite[3]	1207	1		T98	13		T155	13		T37	26
bite[4]	268	1		T177	13		T20	13		T114	42
bite[5]	724	1		T30	26		T111	30		T102	21
bite[6]	593	1		T45	13		T143	113		T146	310
bite[7]	729	1		T111	30		T130	13		T39	51
bite[8]	402	1		T5	21		T9	25		T10	21
bite[9]	482	1		T37	133		T142	21		T166	13
bite[10]	495	1		T9	21		T29	40		T175	42
bite[11]	483	1		T29	6		T142	13		T40	21
bite[12]	678	1		T4	21		T95	30		T129	13
bite[13]	392	1		T5	40		T95	21		T37	42
bite[14]	398	1		T9	21		T137	21		T95	42
bite[15]	425	1		T13	21		T27	21		T99	21
bite[16]	583	1		T143	21		T27	21		T125	13
bite[17]	528	1		T137	21		T104	21		T134	61
bite[18]	475	1		T29	21		T103	35		T21	13
bite[19]	243	1		T103	42		T88	35		T147	13
bite[20]	913	1		T4	21		T10	13		T121	13
bite[21]	253	1		T142	21		T49	21		T105	51
bite[22]	387	1		T29	6		T158	108		T53	6
bite[23]	1137	1		T30	35		T111	26		T118	21
bite[24]	527	1		T12	13		T114	21		T127	4
bite[25]	549	1		T29	21		T37	202		T134	13
bite[26]	308	1		T4	51		T111	21		T143	42
bite[27]	541	1		T9	21		T30	21		T103	30
bite[28]	1232	1		T95	42		T184	13		T19	21
bite[29]	493	1		T155	21		T118	21		T19	42
bite[30]	250	1		T11	13		T143	21		T27	51
bite[31]	538	1		T9	55		T30	44		T137	26
bite_0	4650	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39831	1		T1	17		T2	11		T3	11
auto[1]	8042	1		T2	7		T3	7		T5	78

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	468	1		T10	19		T95	28		T19	19
prescale[1]	620	1		T12	40		T102	24		T153	28
prescale[2]	967	1		T9	78		T12	19		T37	9
prescale[3]	683	1		T13	85		T42	9		T104	36
prescale[4]	1272	1		T13	2		T19	62		T27	19
prescale[5]	632	1		T8	38		T9	82		T44	9
prescale[6]	773	1		T4	9		T6	9		T142	19
prescale[7]	917	1		T8	19		T30	23		T102	19
prescale[8]	775	1		T29	28		T193	9		T19	38
prescale[9]	682	1		T4	23		T8	19		T30	9
prescale[10]	465	1		T8	19		T9	45		T175	35
prescale[11]	486	1		T13	19		T102	23		T37	21
prescale[12]	794	1		T4	47		T12	45		T104	19
prescale[13]	658	1		T5	18		T9	52		T155	24
prescale[14]	835	1		T12	36		T95	40		T134	19
prescale[15]	1073	1		T8	28		T13	138		T29	92
prescale[16]	841	1		T4	28		T5	19		T10	28
prescale[17]	886	1		T9	80		T13	2		T43	9
prescale[18]	609	1		T4	24		T95	63		T134	19
prescale[19]	909	1		T9	9		T13	26		T111	36
prescale[20]	1066	1		T5	19		T12	2		T13	19
prescale[21]	522	1		T10	24		T12	79		T37	2
prescale[22]	544	1		T13	21		T30	67		T175	19
prescale[23]	806	1		T8	9		T29	19		T37	59
prescale[24]	1067	1		T4	23		T8	36		T9	81
prescale[25]	335	1		T10	23		T12	58		T175	19
prescale[26]	666	1		T5	19		T41	9		T175	19
prescale[27]	1021	1		T111	19		T103	19		T134	19
prescale[28]	519	1		T102	19		T39	2		T50	19
prescale[29]	782	1		T8	19		T9	2		T12	52
prescale[30]	850	1		T5	40		T12	52		T175	24
prescale[31]	403	1		T137	19		T143	55		T103	23
prescale_0	23947	1		T1	17		T2	18		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	35766	1		T1	17		T2	9		T3	9
auto[1]	12107	1		T2	9		T3	9		T4	113

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	47873	1		T1	17		T2	18		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27947	1		T1	12		T2	13		T3	13
wkup[1]	322	1		T9	51		T10	21		T37	21
wkup[2]	186	1		T155	15		T95	21		T26	15
wkup[3]	198	1		T104	21		T134	15		T156	15
wkup[4]	188	1		T27	21		T161	21		T53	15
wkup[5]	351	1		T13	21		T30	35		T49	59
wkup[6]	229	1		T102	36		T177	15		T27	26
wkup[7]	145	1		T19	15		T114	21		T49	31
wkup[8]	176	1		T9	21		T27	21		T127	21
wkup[9]	214	1		T4	21		T13	26		T37	21
wkup[10]	359	1		T13	42		T21	15		T39	21
wkup[11]	183	1		T143	21		T40	21		T54	21
wkup[12]	161	1		T38	21		T39	26		T141	21
wkup[13]	403	1		T30	26		T175	21		T111	26
wkup[14]	259	1		T29	21		T102	20		T25	40
wkup[15]	203	1		T13	21		T37	21		T19	26
wkup[16]	269	1		T9	21		T143	21		T37	42
wkup[17]	438	1		T95	21		T103	51		T37	15
wkup[18]	184	1		T30	44		T106	21		T158	21
wkup[19]	361	1		T12	15		T111	30		T142	21
wkup[20]	402	1		T5	30		T29	40		T155	21
wkup[21]	315	1		T12	21		T134	21		T153	21
wkup[22]	342	1		T95	21		T19	21		T27	21
wkup[23]	321	1		T137	21		T142	15		T27	30
wkup[24]	358	1		T121	15		T39	21		T40	21
wkup[25]	197	1		T95	21		T27	21		T153	15
wkup[26]	274	1		T118	30		T114	21		T161	26
wkup[27]	346	1		T103	21		T27	29		T49	21
wkup[28]	296	1		T37	36		T38	6		T39	26
wkup[29]	322	1		T37	21		T19	21		T27	21
wkup[30]	228	1		T10	15		T13	21		T111	21
wkup[31]	243	1		T9	21		T11	15		T19	21
wkup[32]	331	1		T12	30		T19	21		T27	21
wkup[33]	207	1		T37	30		T19	21		T105	21
wkup[34]	200	1		T37	21		T19	21		T54	8
wkup[35]	272	1		T9	21		T29	8		T143	30
wkup[36]	284	1		T13	26		T103	21		T37	21
wkup[37]	224	1		T9	21		T143	21		T39	21
wkup[38]	285	1		T37	21		T19	42		T39	39
wkup[39]	331	1		T134	21		T27	21		T127	21
wkup[40]	253	1		T12	21		T102	21		T19	21
wkup[41]	260	1		T29	36		T19	21		T129	15
wkup[42]	299	1		T130	15		T95	21		T143	21
wkup[43]	173	1		T4	21		T20	15		T39	30
wkup[44]	254	1		T111	30		T37	21		T27	21
wkup[45]	271	1		T104	21		T155	21		T95	42
wkup[46]	229	1		T29	21		T137	26		T95	30
wkup[47]	163	1		T37	30		T184	15		T89	21
wkup[48]	291	1		T137	21		T19	21		T27	26
wkup[49]	284	1		T8	21		T9	30		T30	21
wkup[50]	193	1		T103	21		T19	21		T27	21
wkup[51]	216	1		T103	35		T51	15		T53	26
wkup[52]	310	1		T10	49		T127	21		T53	30
wkup[53]	297	1		T37	51		T134	21		T142	21
wkup[54]	270	1		T4	21		T37	21		T19	30
wkup[55]	335	1		T9	21		T175	21		T143	21
wkup[56]	232	1		T9	21		T29	39		T27	21
wkup[57]	317	1		T12	21		T118	21		T37	35
wkup[58]	238	1		T137	21		T27	15		T125	15
wkup[59]	259	1		T39	42		T127	21		T158	35
wkup[60]	150	1		T27	21		T114	21		T53	36
wkup[61]	227	1		T5	21		T19	26		T27	15
wkup[62]	324	1		T5	21		T13	26		T45	15
wkup[63]	190	1		T89	30		T99	21		T107	26
wkup_0	3284	1		T1	5		T2	5		T3	5