Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.81 99.33 93.67 100.00 98.40 99.51 47.93


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T61 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3920184734 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 422535172 ps
T280 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1672884152 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:08 PM PDT 24 517169622 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4057244238 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:12 PM PDT 24 1698509033 ps
T34 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2446452639 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:19 PM PDT 24 8204031655 ps
T79 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2605916165 Jul 31 05:18:25 PM PDT 24 Jul 31 05:18:30 PM PDT 24 2478205765 ps
T80 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2072094336 Jul 31 05:19:27 PM PDT 24 Jul 31 05:19:29 PM PDT 24 2359300131 ps
T281 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4139154028 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:38 PM PDT 24 713564834 ps
T282 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1924088766 Jul 31 05:18:29 PM PDT 24 Jul 31 05:18:35 PM PDT 24 526092950 ps
T81 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1190979792 Jul 31 05:19:33 PM PDT 24 Jul 31 05:19:35 PM PDT 24 2278312915 ps
T283 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1066580267 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:12 PM PDT 24 1091282036 ps
T284 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3465369922 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:06 PM PDT 24 513219121 ps
T82 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1585325139 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:19 PM PDT 24 1845592960 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2748959501 Jul 31 05:18:13 PM PDT 24 Jul 31 05:18:13 PM PDT 24 372054610 ps
T195 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3923706517 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:02 PM PDT 24 488126199 ps
T286 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.270905006 Jul 31 05:19:05 PM PDT 24 Jul 31 05:19:07 PM PDT 24 521608792 ps
T35 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2612724571 Jul 31 05:18:23 PM PDT 24 Jul 31 05:18:27 PM PDT 24 7777938175 ps
T287 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2036280672 Jul 31 05:18:04 PM PDT 24 Jul 31 05:18:04 PM PDT 24 521193156 ps
T36 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3956684064 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:24 PM PDT 24 8915311020 ps
T288 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2632456876 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 349368749 ps
T289 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3684225268 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 565075883 ps
T290 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3307323542 Jul 31 05:19:31 PM PDT 24 Jul 31 05:19:32 PM PDT 24 473011267 ps
T191 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.315916589 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:11 PM PDT 24 4615403940 ps
T291 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.319675982 Jul 31 05:18:39 PM PDT 24 Jul 31 05:18:40 PM PDT 24 466418984 ps
T292 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2371352539 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:18 PM PDT 24 451758505 ps
T293 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2928025228 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:02 PM PDT 24 341966198 ps
T294 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.865857988 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:04 PM PDT 24 426274551 ps
T295 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1993107362 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:23 PM PDT 24 8855069994 ps
T296 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2206420530 Jul 31 05:18:16 PM PDT 24 Jul 31 05:18:17 PM PDT 24 443917172 ps
T297 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2432954462 Jul 31 05:18:13 PM PDT 24 Jul 31 05:18:14 PM PDT 24 313490581 ps
T298 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1520638464 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:11 PM PDT 24 485506946 ps
T299 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2323605871 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:05 PM PDT 24 356082843 ps
T300 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1720372434 Jul 31 05:19:31 PM PDT 24 Jul 31 05:19:33 PM PDT 24 704336229 ps
T301 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.485351404 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 545098879 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3170540719 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:10 PM PDT 24 485718161 ps
T62 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2073852000 Jul 31 05:18:20 PM PDT 24 Jul 31 05:18:21 PM PDT 24 390946082 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3776348989 Jul 31 05:17:59 PM PDT 24 Jul 31 05:18:00 PM PDT 24 962435460 ps
T304 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3483839857 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:02 PM PDT 24 470330754 ps
T63 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3590588591 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:22 PM PDT 24 376919131 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.40327067 Jul 31 05:18:42 PM PDT 24 Jul 31 05:18:42 PM PDT 24 477687771 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3395565962 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:06 PM PDT 24 1236939214 ps
T65 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.492352116 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:15 PM PDT 24 446361512 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2711567431 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:02 PM PDT 24 1428900416 ps
T307 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2241931091 Jul 31 05:18:26 PM PDT 24 Jul 31 05:18:27 PM PDT 24 421376574 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.475666093 Jul 31 05:18:04 PM PDT 24 Jul 31 05:18:06 PM PDT 24 494216148 ps
T309 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3947712420 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:03 PM PDT 24 436130839 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1980016460 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:03 PM PDT 24 333315320 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.231733482 Jul 31 05:18:16 PM PDT 24 Jul 31 05:18:20 PM PDT 24 7127068793 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.628177552 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:06 PM PDT 24 1097421754 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2930238010 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 1263115991 ps
T313 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.300461685 Jul 31 05:19:32 PM PDT 24 Jul 31 05:19:34 PM PDT 24 1010313661 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2021589756 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:02 PM PDT 24 436287057 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.919690732 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 476733409 ps
T316 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4028565028 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:38 PM PDT 24 8160637975 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3712035470 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:47 PM PDT 24 512637123 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2759951720 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:05 PM PDT 24 426120283 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.971264740 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:03 PM PDT 24 372209162 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2203710665 Jul 31 05:18:30 PM PDT 24 Jul 31 05:18:31 PM PDT 24 397845424 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3477169513 Jul 31 05:18:26 PM PDT 24 Jul 31 05:18:29 PM PDT 24 460979486 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2293737253 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:06 PM PDT 24 413569477 ps
T322 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.797679492 Jul 31 05:18:30 PM PDT 24 Jul 31 05:18:32 PM PDT 24 301080654 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3144436868 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:02 PM PDT 24 454678384 ps
T324 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2650738151 Jul 31 05:17:59 PM PDT 24 Jul 31 05:18:01 PM PDT 24 1420402810 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.194369563 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:13 PM PDT 24 363442149 ps
T326 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1514337422 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 295454388 ps
T327 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.753921538 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:23 PM PDT 24 4550618419 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2038392115 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:14 PM PDT 24 7756288640 ps
T329 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2045359954 Jul 31 05:18:04 PM PDT 24 Jul 31 05:18:05 PM PDT 24 511915964 ps
T330 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2187018700 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:33 PM PDT 24 498235567 ps
T331 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3490894297 Jul 31 05:18:25 PM PDT 24 Jul 31 05:18:26 PM PDT 24 523185468 ps
T332 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4270960672 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 366127279 ps
T333 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1858985675 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:11 PM PDT 24 421488360 ps
T334 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2372377509 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 443270026 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1439469883 Jul 31 05:19:26 PM PDT 24 Jul 31 05:19:27 PM PDT 24 467412484 ps
T192 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2050442288 Jul 31 05:18:35 PM PDT 24 Jul 31 05:18:37 PM PDT 24 9509244808 ps
T336 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2558631424 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:33 PM PDT 24 283931622 ps
T337 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3048831289 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:27 PM PDT 24 385259277 ps
T338 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3703963718 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:03 PM PDT 24 479759156 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2296971335 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:08 PM PDT 24 1088286534 ps
T340 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2037730556 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 367398446 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.435190447 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:13 PM PDT 24 364435351 ps
T342 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.73126720 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:11 PM PDT 24 2368371203 ps
T71 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1578490277 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:06 PM PDT 24 399873206 ps
T343 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3745993729 Jul 31 05:18:20 PM PDT 24 Jul 31 05:18:20 PM PDT 24 454201009 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1022348363 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:07 PM PDT 24 546033105 ps
T345 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1701162195 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:17 PM PDT 24 408391822 ps
T346 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068227787 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:20 PM PDT 24 409135513 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2818134820 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:04 PM PDT 24 339700932 ps
T348 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1936531774 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 361030248 ps
T349 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.569544101 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:18 PM PDT 24 317653014 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4168625055 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:19 PM PDT 24 4472127003 ps
T351 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4026190122 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:07 PM PDT 24 362776053 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3500042815 Jul 31 05:18:34 PM PDT 24 Jul 31 05:18:36 PM PDT 24 503795443 ps
T353 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2599244367 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:04 PM PDT 24 377291033 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3850129389 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:13 PM PDT 24 348979558 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2803720292 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:10 PM PDT 24 348919263 ps
T73 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1258943989 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:07 PM PDT 24 8954991022 ps
T355 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.762075503 Jul 31 05:18:26 PM PDT 24 Jul 31 05:18:27 PM PDT 24 340900927 ps
T356 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1139897085 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:34 PM PDT 24 813530897 ps
T357 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1375557466 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:23 PM PDT 24 500418219 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.555967020 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:02 PM PDT 24 662369243 ps
T359 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1621812676 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:16 PM PDT 24 266914613 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3569359093 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:10 PM PDT 24 4369213334 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2070477057 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:07 PM PDT 24 530959663 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.654444189 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 467044275 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2639521619 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 1065980272 ps
T362 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2455772226 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:05 PM PDT 24 1042366528 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.748102723 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 554797212 ps
T364 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4040462455 Jul 31 05:19:46 PM PDT 24 Jul 31 05:19:48 PM PDT 24 1312612870 ps
T365 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3652500382 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 391760437 ps
T366 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.197760931 Jul 31 05:18:16 PM PDT 24 Jul 31 05:18:17 PM PDT 24 299067788 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4048099150 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:03 PM PDT 24 672732570 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.419972237 Jul 31 05:18:20 PM PDT 24 Jul 31 05:18:22 PM PDT 24 673114149 ps
T369 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2304732753 Jul 31 05:18:01 PM PDT 24 Jul 31 05:18:03 PM PDT 24 502551921 ps
T370 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.900251409 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:14 PM PDT 24 421503113 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2955208090 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:34 PM PDT 24 574641878 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1822990500 Jul 31 05:18:18 PM PDT 24 Jul 31 05:18:19 PM PDT 24 330228313 ps
T373 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.838723717 Jul 31 05:19:05 PM PDT 24 Jul 31 05:19:18 PM PDT 24 8047203509 ps
T188 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3128470505 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:12 PM PDT 24 4485952093 ps
T374 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3516245280 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:24 PM PDT 24 3161028374 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3880972152 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:04 PM PDT 24 476469856 ps
T376 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1713002288 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:33 PM PDT 24 483867599 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2435560383 Jul 31 05:18:18 PM PDT 24 Jul 31 05:18:20 PM PDT 24 8041925000 ps
T378 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2842092440 Jul 31 05:18:20 PM PDT 24 Jul 31 05:18:20 PM PDT 24 384438568 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2227820467 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:21 PM PDT 24 399005894 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3101045539 Jul 31 05:18:03 PM PDT 24 Jul 31 05:18:10 PM PDT 24 2375218851 ps
T381 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4270378932 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:16 PM PDT 24 489599151 ps
T382 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.311617746 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:14 PM PDT 24 339776195 ps
T383 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.731398964 Jul 31 05:18:24 PM PDT 24 Jul 31 05:18:25 PM PDT 24 503237530 ps
T384 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2799702951 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:01 PM PDT 24 374508559 ps
T385 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.639341257 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:01 PM PDT 24 457445004 ps
T386 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3077222186 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:07 PM PDT 24 379385186 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.350055846 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:22 PM PDT 24 452135436 ps
T388 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3556754205 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 438992527 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.229909107 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:15 PM PDT 24 612288799 ps
T389 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1461844479 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:13 PM PDT 24 428413967 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1709168306 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:03 PM PDT 24 4540308006 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1791341570 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:13 PM PDT 24 8291593350 ps
T391 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1285854739 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:15 PM PDT 24 9082167672 ps
T392 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1055926341 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:38 PM PDT 24 2312260369 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3824722520 Jul 31 05:18:38 PM PDT 24 Jul 31 05:18:39 PM PDT 24 496336024 ps
T394 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1197465067 Jul 31 05:18:09 PM PDT 24 Jul 31 05:18:10 PM PDT 24 508111580 ps
T395 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.569471187 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:06 PM PDT 24 355314936 ps
T396 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3792086967 Jul 31 05:18:13 PM PDT 24 Jul 31 05:18:14 PM PDT 24 313551313 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2946353456 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:38 PM PDT 24 514820522 ps
T189 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.191374218 Jul 31 05:18:02 PM PDT 24 Jul 31 05:18:06 PM PDT 24 4339127808 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.342618319 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:10 PM PDT 24 3155226663 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1775846106 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:30 PM PDT 24 7788263542 ps
T400 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.734645759 Jul 31 05:18:00 PM PDT 24 Jul 31 05:18:01 PM PDT 24 462926767 ps
T401 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1499223349 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:38 PM PDT 24 386266631 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3614384639 Jul 31 05:18:28 PM PDT 24 Jul 31 05:18:29 PM PDT 24 360606977 ps
T403 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1736845879 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:32 PM PDT 24 491268664 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3448237286 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:40 PM PDT 24 1141781406 ps
T405 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3282265734 Jul 31 05:19:42 PM PDT 24 Jul 31 05:19:43 PM PDT 24 423767442 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3864223140 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:09 PM PDT 24 2162072390 ps
T407 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.873869961 Jul 31 05:18:12 PM PDT 24 Jul 31 05:18:13 PM PDT 24 297854785 ps
T408 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2199580200 Jul 31 05:18:07 PM PDT 24 Jul 31 05:18:08 PM PDT 24 537721103 ps
T409 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1071825287 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 296722781 ps
T410 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4211712227 Jul 31 05:18:29 PM PDT 24 Jul 31 05:18:30 PM PDT 24 358801304 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3071443573 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:09 PM PDT 24 544133241 ps
T190 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2053325318 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:16 PM PDT 24 8145483943 ps
T412 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.114113689 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 414788041 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.590588386 Jul 31 05:17:58 PM PDT 24 Jul 31 05:18:00 PM PDT 24 740375719 ps
T414 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1351923993 Jul 31 05:18:18 PM PDT 24 Jul 31 05:18:19 PM PDT 24 466235921 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.815562808 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:27 PM PDT 24 8467288954 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.456577994 Jul 31 05:18:22 PM PDT 24 Jul 31 05:18:24 PM PDT 24 717832724 ps
T416 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2490497874 Jul 31 05:18:06 PM PDT 24 Jul 31 05:18:21 PM PDT 24 8367972248 ps

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1114847367
Short name T9
Test name
Test status
Simulation time 47405971553 ps
CPU time 352 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:20:21 PM PDT 24
Peak memory 206692 kb
Host smart-8df2aab5-e468-45f8-85cf-ade5aeb49235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114847367 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1114847367
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4223823324
Short name T30
Test name
Test status
Simulation time 108449195991 ps
CPU time 8.84 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:14 PM PDT 24
Peak memory 198124 kb
Host smart-eda0e8e9-8cd3-4c96-bbe1-62d4982f886d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223823324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4223823324
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.255455576
Short name T18
Test name
Test status
Simulation time 4019005429 ps
CPU time 5.71 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 215292 kb
Host smart-4e1c6f46-51bb-439d-b4b0-a9a0f4c4babe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255455576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.255455576
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2548701105
Short name T49
Test name
Test status
Simulation time 177209877915 ps
CPU time 658.03 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:25:34 PM PDT 24
Peak memory 214264 kb
Host smart-4dd889b2-f0eb-48d8-a39e-4ea34140b24b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548701105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2548701105
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1844837383
Short name T53
Test name
Test status
Simulation time 391659184324 ps
CPU time 480.26 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:22:11 PM PDT 24
Peak memory 214268 kb
Host smart-0e47eea6-51bf-4cef-a49f-5143f21155dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844837383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1844837383
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3680349890
Short name T95
Test name
Test status
Simulation time 118184163354 ps
CPU time 40.79 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:14:52 PM PDT 24
Peak memory 192540 kb
Host smart-bb2dd4fb-b14a-4f6c-bee6-4e599bb5dc9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680349890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3680349890
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2446452639
Short name T34
Test name
Test status
Simulation time 8204031655 ps
CPU time 4.09 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 198436 kb
Host smart-f9ba799e-9f12-4444-919f-c7787938e10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446452639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2446452639
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2686908291
Short name T27
Test name
Test status
Simulation time 103946738354 ps
CPU time 586.2 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:23:57 PM PDT 24
Peak memory 212600 kb
Host smart-bac6e901-0155-4a92-a0b6-eb5308fe020d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686908291 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2686908291
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2254044921
Short name T37
Test name
Test status
Simulation time 207041169444 ps
CPU time 543.63 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:23:29 PM PDT 24
Peak memory 204848 kb
Host smart-594de64a-d2a2-4c48-9c1c-e8608d3eebfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254044921 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2254044921
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.144504231
Short name T112
Test name
Test status
Simulation time 586527408068 ps
CPU time 409.04 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:20:53 PM PDT 24
Peak memory 202976 kb
Host smart-edb35dee-d373-4ba1-92ab-7f8893a987bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144504231 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.144504231
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.509353999
Short name T39
Test name
Test status
Simulation time 101174673958 ps
CPU time 718.56 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:26:15 PM PDT 24
Peak memory 205888 kb
Host smart-9b34ab81-ff24-4ab0-b7b7-b0455a9c8a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509353999 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.509353999
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3594451355
Short name T19
Test name
Test status
Simulation time 75992364865 ps
CPU time 310.5 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:19:35 PM PDT 24
Peak memory 209004 kb
Host smart-a882319a-0d0e-413d-9ddd-cd2a2a5b6cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594451355 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3594451355
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.408100109
Short name T123
Test name
Test status
Simulation time 147093978431 ps
CPU time 585.24 seconds
Started Jul 31 05:14:28 PM PDT 24
Finished Jul 31 05:24:13 PM PDT 24
Peak memory 206684 kb
Host smart-99745493-a2cb-49e9-925b-587485d0e3b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408100109 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.408100109
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3958949398
Short name T103
Test name
Test status
Simulation time 143940508971 ps
CPU time 216.62 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:17:36 PM PDT 24
Peak memory 198276 kb
Host smart-937bcb80-189d-4314-847c-c9f65f47e246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958949398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3958949398
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1821741541
Short name T107
Test name
Test status
Simulation time 90839148935 ps
CPU time 710.86 seconds
Started Jul 31 05:14:37 PM PDT 24
Finished Jul 31 05:26:28 PM PDT 24
Peak memory 206188 kb
Host smart-a1e8be59-66a5-43be-bdfc-6b3caf391c4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821741541 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1821741541
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3114826046
Short name T109
Test name
Test status
Simulation time 288730050921 ps
CPU time 639.26 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:24:40 PM PDT 24
Peak memory 213272 kb
Host smart-b0607d96-5352-43d5-a773-2a2ae93e55ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114826046 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3114826046
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.256807078
Short name T38
Test name
Test status
Simulation time 89855781916 ps
CPU time 755.83 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:26:59 PM PDT 24
Peak memory 214896 kb
Host smart-4e599dd2-c69b-41b5-948c-065ae7e475eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256807078 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.256807078
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3125122431
Short name T114
Test name
Test status
Simulation time 188134469541 ps
CPU time 74.94 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:15:44 PM PDT 24
Peak memory 198176 kb
Host smart-b2044dbf-cf0a-400d-8c5f-97aa0bd9ee4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125122431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3125122431
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1478351609
Short name T106
Test name
Test status
Simulation time 111929775738 ps
CPU time 42.54 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:15:09 PM PDT 24
Peak memory 191900 kb
Host smart-4b728fe2-dc7e-48a3-a546-368856825cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478351609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1478351609
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3431374138
Short name T105
Test name
Test status
Simulation time 5943521106 ps
CPU time 8.13 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:14:09 PM PDT 24
Peak memory 198304 kb
Host smart-7af3d62e-b717-4970-96d4-6e2219939dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431374138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3431374138
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1357355249
Short name T132
Test name
Test status
Simulation time 25187343530 ps
CPU time 33.06 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:15:14 PM PDT 24
Peak memory 192940 kb
Host smart-05528453-f807-4127-a02a-bf133dc874c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357355249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1357355249
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3095071843
Short name T136
Test name
Test status
Simulation time 136102256197 ps
CPU time 84.04 seconds
Started Jul 31 05:14:40 PM PDT 24
Finished Jul 31 05:16:04 PM PDT 24
Peak memory 198212 kb
Host smart-2fc858e0-f703-4011-8f04-9e223d1a6e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095071843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3095071843
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2263020520
Short name T84
Test name
Test status
Simulation time 1003477494930 ps
CPU time 732.24 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:26:35 PM PDT 24
Peak memory 214104 kb
Host smart-63dddb27-0294-4232-8a8c-b8ce03fc6a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263020520 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2263020520
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3730649724
Short name T108
Test name
Test status
Simulation time 258823859509 ps
CPU time 357.39 seconds
Started Jul 31 05:14:31 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 198260 kb
Host smart-2a0a10e1-1161-48e3-ae95-313545077ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730649724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3730649724
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2378711054
Short name T4
Test name
Test status
Simulation time 160560573335 ps
CPU time 63.47 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:15:39 PM PDT 24
Peak memory 192136 kb
Host smart-34aa50ce-d663-414f-bd6f-2860f1ddf690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378711054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2378711054
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3756806172
Short name T143
Test name
Test status
Simulation time 644208636401 ps
CPU time 828.15 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:28:12 PM PDT 24
Peak memory 198228 kb
Host smart-4941d3eb-2186-4f18-b603-b585ad015e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756806172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3756806172
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4151682686
Short name T137
Test name
Test status
Simulation time 78594637776 ps
CPU time 126.35 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 198236 kb
Host smart-7b259a13-b519-4b50-af72-83665aa4c321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151682686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4151682686
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3287368110
Short name T150
Test name
Test status
Simulation time 80784360106 ps
CPU time 313.65 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:19:36 PM PDT 24
Peak memory 201620 kb
Host smart-48ca585f-1f2b-4b9a-82dd-dbab66a35220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287368110 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3287368110
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2823393395
Short name T128
Test name
Test status
Simulation time 4097464399 ps
CPU time 3.69 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 198216 kb
Host smart-c54de2a8-bc2f-495a-8a2e-f76fa77e82dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823393395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2823393395
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3590588591
Short name T63
Test name
Test status
Simulation time 376919131 ps
CPU time 0.69 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:22 PM PDT 24
Peak memory 192988 kb
Host smart-04524065-8860-4bc9-a04a-8f8ae36a62e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590588591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3590588591
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.629450405
Short name T87
Test name
Test status
Simulation time 157631945956 ps
CPU time 836.51 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:28:26 PM PDT 24
Peak memory 207744 kb
Host smart-6a100fc5-0a6a-4c5a-8b3c-5c4fd2bdd783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629450405 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.629450405
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3804417071
Short name T90
Test name
Test status
Simulation time 127838987203 ps
CPU time 487.89 seconds
Started Jul 31 05:14:37 PM PDT 24
Finished Jul 31 05:22:45 PM PDT 24
Peak memory 203516 kb
Host smart-683209be-3545-4d53-8799-501442846dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804417071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3804417071
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.969783826
Short name T124
Test name
Test status
Simulation time 171208899553 ps
CPU time 71.08 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:15:36 PM PDT 24
Peak memory 192960 kb
Host smart-47577d06-7a18-48a3-bf3c-d8197b5ce551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969783826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.969783826
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1220891059
Short name T117
Test name
Test status
Simulation time 13847492002 ps
CPU time 3.55 seconds
Started Jul 31 05:14:31 PM PDT 24
Finished Jul 31 05:14:35 PM PDT 24
Peak memory 191908 kb
Host smart-8218ad5d-e1a9-4d12-9add-f47d859aa0e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220891059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1220891059
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2156837920
Short name T86
Test name
Test status
Simulation time 37319110331 ps
CPU time 300.75 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:19:24 PM PDT 24
Peak memory 214804 kb
Host smart-749c2d90-29cf-4a91-a589-419f3ce9479d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156837920 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2156837920
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.273489208
Short name T97
Test name
Test status
Simulation time 21137461438 ps
CPU time 16.25 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:42 PM PDT 24
Peak memory 198200 kb
Host smart-ea72c558-aa63-4610-a067-833e2966791e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273489208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.273489208
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.367301869
Short name T83
Test name
Test status
Simulation time 75143551308 ps
CPU time 385.6 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:20:49 PM PDT 24
Peak memory 209740 kb
Host smart-f8888ac0-9379-4981-887a-aa25cac6bd1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367301869 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.367301869
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.747252082
Short name T55
Test name
Test status
Simulation time 199377204904 ps
CPU time 73.85 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:15:41 PM PDT 24
Peak memory 192428 kb
Host smart-44de55ac-855d-4c55-bdff-2918b18ed80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747252082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.747252082
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2931578850
Short name T148
Test name
Test status
Simulation time 20517653095 ps
CPU time 140.65 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:16:50 PM PDT 24
Peak memory 198472 kb
Host smart-7ea8e514-b941-46d7-9466-7ed823461e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931578850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2931578850
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1042682245
Short name T144
Test name
Test status
Simulation time 153044789804 ps
CPU time 399.37 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:20:56 PM PDT 24
Peak memory 206648 kb
Host smart-3cca027d-2828-4c5a-83d1-ecdabb0c1d6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042682245 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1042682245
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.341710577
Short name T60
Test name
Test status
Simulation time 123170672465 ps
CPU time 645.29 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:25:08 PM PDT 24
Peak memory 207164 kb
Host smart-28c96486-b70c-4eff-9bb2-99848942a063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341710577 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.341710577
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.146763362
Short name T99
Test name
Test status
Simulation time 86721040191 ps
CPU time 31.15 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:15:14 PM PDT 24
Peak memory 192488 kb
Host smart-e815c04d-cdda-419c-ba78-abac72c2f1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146763362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.146763362
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3620102758
Short name T146
Test name
Test status
Simulation time 29660667527 ps
CPU time 330.4 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:19:35 PM PDT 24
Peak memory 214664 kb
Host smart-daa67e76-4bd7-4caa-83f4-3da1560d03d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620102758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3620102758
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1339803621
Short name T141
Test name
Test status
Simulation time 110097534108 ps
CPU time 157.42 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:17:12 PM PDT 24
Peak memory 192988 kb
Host smart-0e71bd61-a43a-4fdc-9eb1-2a2a87a63f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339803621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1339803621
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2868927789
Short name T129
Test name
Test status
Simulation time 243789489727 ps
CPU time 86.52 seconds
Started Jul 31 05:14:13 PM PDT 24
Finished Jul 31 05:15:40 PM PDT 24
Peak memory 198260 kb
Host smart-698d3551-761a-4051-856d-34ab4f659b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868927789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2868927789
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.956301163
Short name T110
Test name
Test status
Simulation time 73502427988 ps
CPU time 12.53 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:14:16 PM PDT 24
Peak memory 198280 kb
Host smart-32611be4-e347-423a-b7ca-c400524c611b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956301163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.956301163
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3608764054
Short name T85
Test name
Test status
Simulation time 75770196592 ps
CPU time 119.97 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:16:34 PM PDT 24
Peak memory 206676 kb
Host smart-9c1385e8-8214-4b2c-a703-dc5bfb25b1d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608764054 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3608764054
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.490756737
Short name T158
Test name
Test status
Simulation time 203024453306 ps
CPU time 66.65 seconds
Started Jul 31 05:14:41 PM PDT 24
Finished Jul 31 05:15:47 PM PDT 24
Peak memory 192404 kb
Host smart-538f43c4-4a52-408d-942b-226960d10bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490756737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.490756737
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1332715837
Short name T165
Test name
Test status
Simulation time 341962782918 ps
CPU time 538.59 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:23:16 PM PDT 24
Peak memory 191768 kb
Host smart-5ab06ae8-0abd-4dd9-805a-56bdeced81b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332715837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1332715837
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.4002754390
Short name T52
Test name
Test status
Simulation time 126664426905 ps
CPU time 31.85 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:57 PM PDT 24
Peak memory 198156 kb
Host smart-91e651da-d6e6-4920-ac01-036c7899192a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002754390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.4002754390
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2667479894
Short name T94
Test name
Test status
Simulation time 63125054850 ps
CPU time 95.38 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:15:47 PM PDT 24
Peak memory 192600 kb
Host smart-c8a9aad9-e970-4299-85f0-6a340c04edd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667479894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2667479894
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1930443460
Short name T134
Test name
Test status
Simulation time 291716669742 ps
CPU time 126.98 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:16:23 PM PDT 24
Peak memory 192940 kb
Host smart-7f256274-1576-4b80-bac7-00b1cd294a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930443460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1930443460
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.21975046
Short name T13
Test name
Test status
Simulation time 77199559411 ps
CPU time 163.28 seconds
Started Jul 31 05:14:41 PM PDT 24
Finished Jul 31 05:17:25 PM PDT 24
Peak memory 207340 kb
Host smart-4374ae82-ce1f-4db6-915c-08d31c3f546f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21975046 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.21975046
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1575555812
Short name T142
Test name
Test status
Simulation time 274905146183 ps
CPU time 346.18 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:20:02 PM PDT 24
Peak memory 198232 kb
Host smart-2ef05268-7751-4521-a960-7db8386b5ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575555812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1575555812
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2659125772
Short name T29
Test name
Test status
Simulation time 17159127406 ps
CPU time 126.41 seconds
Started Jul 31 05:14:21 PM PDT 24
Finished Jul 31 05:16:27 PM PDT 24
Peak memory 206716 kb
Host smart-4fab4dfa-6ebb-4425-8109-057695861dde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659125772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2659125772
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.224955796
Short name T89
Test name
Test status
Simulation time 18503167276 ps
CPU time 127.83 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:16:20 PM PDT 24
Peak memory 214488 kb
Host smart-a228396d-727e-4f1a-a02b-7829def698e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224955796 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.224955796
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1217084470
Short name T111
Test name
Test status
Simulation time 197779830225 ps
CPU time 135.88 seconds
Started Jul 31 05:14:18 PM PDT 24
Finished Jul 31 05:16:34 PM PDT 24
Peak memory 198328 kb
Host smart-e46441ee-cfee-4b91-bfbe-614815ea90cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217084470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1217084470
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.729847044
Short name T59
Test name
Test status
Simulation time 120460165733 ps
CPU time 259.4 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 198632 kb
Host smart-c36e6012-e284-4ead-bbba-1c13695823fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729847044 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.729847044
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.889310238
Short name T161
Test name
Test status
Simulation time 34510081664 ps
CPU time 283.67 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:19:19 PM PDT 24
Peak memory 206604 kb
Host smart-5dc0f56a-b6af-459b-bc7e-598f888a6775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889310238 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.889310238
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.471852788
Short name T133
Test name
Test status
Simulation time 76262590709 ps
CPU time 28.22 seconds
Started Jul 31 05:14:39 PM PDT 24
Finished Jul 31 05:15:07 PM PDT 24
Peak memory 192900 kb
Host smart-27c3fb2e-09c5-4177-84f4-43cac1d9b851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471852788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.471852788
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3040535477
Short name T157
Test name
Test status
Simulation time 95122637497 ps
CPU time 241.3 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 214052 kb
Host smart-ca08b4bd-16b9-4b08-be99-e662a86176c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040535477 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3040535477
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3646229767
Short name T100
Test name
Test status
Simulation time 267129955248 ps
CPU time 210.28 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:17:45 PM PDT 24
Peak memory 198208 kb
Host smart-2c008114-7dab-42b8-9522-c38ca17856dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646229767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3646229767
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3036684657
Short name T118
Test name
Test status
Simulation time 47460276403 ps
CPU time 6.73 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 198216 kb
Host smart-432ca5c9-77aa-429b-b1d6-b290a6d8aac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036684657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3036684657
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3578038521
Short name T54
Test name
Test status
Simulation time 45100211531 ps
CPU time 96.66 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:16:07 PM PDT 24
Peak memory 198424 kb
Host smart-c8c3d6e1-810f-4d21-96c8-ae06d7beea19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578038521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3578038521
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3566419013
Short name T122
Test name
Test status
Simulation time 40809960442 ps
CPU time 330.56 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:20:05 PM PDT 24
Peak memory 198880 kb
Host smart-883efc8e-d54f-4703-874c-7f6c5bdf8a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566419013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3566419013
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2024233141
Short name T180
Test name
Test status
Simulation time 657374914282 ps
CPU time 224.89 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 191888 kb
Host smart-9bed1458-f122-43d7-a2d3-c32a2eeeef1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024233141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2024233141
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3905710583
Short name T96
Test name
Test status
Simulation time 428537036 ps
CPU time 1.18 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:14:17 PM PDT 24
Peak memory 196620 kb
Host smart-1219fc97-36d5-4951-ba5a-bfa653a12636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905710583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3905710583
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.905673413
Short name T160
Test name
Test status
Simulation time 4921635331 ps
CPU time 2.65 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 191884 kb
Host smart-769cfb9f-a72e-4601-90bc-6f4106507155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905673413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.905673413
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3549311968
Short name T10
Test name
Test status
Simulation time 141129394447 ps
CPU time 196.11 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:17:52 PM PDT 24
Peak memory 192712 kb
Host smart-00bd6f10-df3f-4f01-8c80-c5288a3b2919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549311968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3549311968
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2710187163
Short name T149
Test name
Test status
Simulation time 480179867 ps
CPU time 0.92 seconds
Started Jul 31 05:14:33 PM PDT 24
Finished Jul 31 05:14:34 PM PDT 24
Peak memory 196552 kb
Host smart-fece0e5e-4445-4f7e-b24f-c5aeb740dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710187163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2710187163
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2276909774
Short name T102
Test name
Test status
Simulation time 683940653014 ps
CPU time 478.95 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:22:10 PM PDT 24
Peak memory 198184 kb
Host smart-885b78d5-7e21-4e62-a4e9-73251c3465a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276909774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2276909774
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2719588892
Short name T163
Test name
Test status
Simulation time 147722724213 ps
CPU time 49.59 seconds
Started Jul 31 05:14:14 PM PDT 24
Finished Jul 31 05:15:04 PM PDT 24
Peak memory 192892 kb
Host smart-a19c5e4e-36dd-4e0b-b97d-16c6e731bb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719588892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2719588892
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3887034426
Short name T135
Test name
Test status
Simulation time 565704835 ps
CPU time 1.42 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:25 PM PDT 24
Peak memory 196640 kb
Host smart-55abcecf-8dc9-4085-8909-2e6090eba4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887034426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3887034426
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3622580161
Short name T153
Test name
Test status
Simulation time 176787467959 ps
CPU time 252.79 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:18:36 PM PDT 24
Peak memory 192868 kb
Host smart-64f92881-dd5e-46a3-9aca-4ddca922f92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622580161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3622580161
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2805568159
Short name T104
Test name
Test status
Simulation time 388190092448 ps
CPU time 131.85 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:16:48 PM PDT 24
Peak memory 192540 kb
Host smart-59f1e0a2-c2c9-4529-bf03-062c7c2baca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805568159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2805568159
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2467135484
Short name T98
Test name
Test status
Simulation time 394149747 ps
CPU time 0.89 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:43 PM PDT 24
Peak memory 196644 kb
Host smart-4eb966db-6234-48c4-a813-b02c11261538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467135484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2467135484
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2493200968
Short name T88
Test name
Test status
Simulation time 71192108750 ps
CPU time 406.18 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:20:56 PM PDT 24
Peak memory 201188 kb
Host smart-6e879b90-0f87-4987-b442-522a553ed162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493200968 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2493200968
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2954822566
Short name T40
Test name
Test status
Simulation time 70334407459 ps
CPU time 132.73 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 206792 kb
Host smart-434adb1e-2594-4511-9094-1bc9a999ac67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954822566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2954822566
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1669622590
Short name T151
Test name
Test status
Simulation time 453726939 ps
CPU time 0.89 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 196660 kb
Host smart-e78ccf4e-0592-4ac0-b5ae-579ee049c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669622590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1669622590
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2529173966
Short name T119
Test name
Test status
Simulation time 301753974623 ps
CPU time 114.48 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:16:25 PM PDT 24
Peak memory 192884 kb
Host smart-1d224797-e107-4d69-a3dd-5700de3f080a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529173966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2529173966
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3048690174
Short name T127
Test name
Test status
Simulation time 19698919416 ps
CPU time 207.88 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:17:57 PM PDT 24
Peak memory 198388 kb
Host smart-52b6763f-4429-479d-95bc-410fe2c72ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048690174 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3048690174
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2318014339
Short name T93
Test name
Test status
Simulation time 601250409 ps
CPU time 0.7 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 196708 kb
Host smart-e6c942bb-91c9-48a1-85e0-d8e9126c81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318014339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2318014339
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2762972853
Short name T51
Test name
Test status
Simulation time 539114325 ps
CPU time 0.95 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:05 PM PDT 24
Peak memory 196780 kb
Host smart-da736cbc-8f19-457e-9bfe-70fd1d180adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762972853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2762972853
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1463725684
Short name T116
Test name
Test status
Simulation time 607979429 ps
CPU time 0.84 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:11 PM PDT 24
Peak memory 196752 kb
Host smart-3a210a72-ee85-4093-9fa4-85cf4dac5d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463725684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1463725684
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2477348048
Short name T125
Test name
Test status
Simulation time 373690139 ps
CPU time 1.11 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:14:16 PM PDT 24
Peak memory 196624 kb
Host smart-31199f54-9155-49a5-8247-a6a67af2d4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477348048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2477348048
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2993721777
Short name T21
Test name
Test status
Simulation time 547536794 ps
CPU time 0.95 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 196580 kb
Host smart-0bd95191-81b9-4a54-a2bc-dfcb33687d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993721777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2993721777
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.560973969
Short name T115
Test name
Test status
Simulation time 395312849 ps
CPU time 1.2 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 196656 kb
Host smart-6eace7d7-3431-407d-b77e-a68316b47f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560973969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.560973969
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.203731983
Short name T152
Test name
Test status
Simulation time 412677045 ps
CPU time 0.93 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 196652 kb
Host smart-ed414616-0af3-4f71-b49d-a19e416033e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203731983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.203731983
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1166803345
Short name T145
Test name
Test status
Simulation time 556647464 ps
CPU time 1.41 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 196668 kb
Host smart-b2df6b73-a942-4f55-b43d-0cb269034537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166803345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1166803345
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4182996552
Short name T139
Test name
Test status
Simulation time 585437704 ps
CPU time 0.74 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:43 PM PDT 24
Peak memory 196592 kb
Host smart-9f348d12-2aa5-4826-9791-5c1a77411742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182996552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4182996552
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2434715205
Short name T138
Test name
Test status
Simulation time 429386380 ps
CPU time 0.68 seconds
Started Jul 31 05:14:44 PM PDT 24
Finished Jul 31 05:14:44 PM PDT 24
Peak memory 196688 kb
Host smart-9477f1cf-9376-4257-b60c-25727fcfeb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434715205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2434715205
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2641012594
Short name T185
Test name
Test status
Simulation time 539501807631 ps
CPU time 850.21 seconds
Started Jul 31 05:14:18 PM PDT 24
Finished Jul 31 05:28:28 PM PDT 24
Peak memory 191800 kb
Host smart-ae5d1fc7-1265-4dda-b5bd-a72dc442df72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641012594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2641012594
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3364443710
Short name T113
Test name
Test status
Simulation time 492073017 ps
CPU time 0.72 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 196688 kb
Host smart-710fd1dd-168b-4f91-a7ff-eac95e4b049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364443710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3364443710
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2514676001
Short name T131
Test name
Test status
Simulation time 415872508 ps
CPU time 0.72 seconds
Started Jul 31 05:14:19 PM PDT 24
Finished Jul 31 05:14:20 PM PDT 24
Peak memory 196820 kb
Host smart-11ab7025-ecd9-4cef-8061-f118d28f5de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514676001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2514676001
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2932227533
Short name T5
Test name
Test status
Simulation time 244208009846 ps
CPU time 343 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:20:00 PM PDT 24
Peak memory 192904 kb
Host smart-0cfe17bc-f37d-428e-8910-4e6a9b670e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932227533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2932227533
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2063261122
Short name T155
Test name
Test status
Simulation time 83324959452 ps
CPU time 61.04 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:15:28 PM PDT 24
Peak memory 198140 kb
Host smart-e7d07bf8-96bd-41e1-be05-ad9db6077a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063261122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2063261122
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.883173229
Short name T140
Test name
Test status
Simulation time 543404059 ps
CPU time 0.76 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 196580 kb
Host smart-c3ce45e5-4a87-46c1-89ab-119cce24cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883173229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.883173229
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3180979703
Short name T154
Test name
Test status
Simulation time 99760378846 ps
CPU time 26.26 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:15:03 PM PDT 24
Peak memory 198228 kb
Host smart-19203b8d-d71a-46f5-a3bb-c15a3f18e164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180979703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3180979703
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.418971649
Short name T91
Test name
Test status
Simulation time 181765718612 ps
CPU time 354.55 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:20:29 PM PDT 24
Peak memory 201692 kb
Host smart-28fc74bf-6098-4243-be7c-83e22d205760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418971649 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.418971649
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3517564299
Short name T168
Test name
Test status
Simulation time 548877917 ps
CPU time 1.36 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 196600 kb
Host smart-d60b5182-69d3-476d-887f-afba58367bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517564299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3517564299
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2028236503
Short name T20
Test name
Test status
Simulation time 469028061 ps
CPU time 1.28 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 196600 kb
Host smart-054d687a-3d05-4f85-93c3-5764f29f5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028236503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2028236503
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3036727200
Short name T126
Test name
Test status
Simulation time 187119131432 ps
CPU time 258.93 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 198184 kb
Host smart-c4babca2-889c-4653-8413-6015fa3f3e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036727200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3036727200
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3751094292
Short name T50
Test name
Test status
Simulation time 411918243019 ps
CPU time 368.19 seconds
Started Jul 31 05:14:37 PM PDT 24
Finished Jul 31 05:20:45 PM PDT 24
Peak memory 198164 kb
Host smart-8f140b59-aabe-4d14-afba-be028c88cb5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751094292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3751094292
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3992208565
Short name T120
Test name
Test status
Simulation time 472359131 ps
CPU time 0.77 seconds
Started Jul 31 05:14:45 PM PDT 24
Finished Jul 31 05:14:46 PM PDT 24
Peak memory 196560 kb
Host smart-5603047b-9a62-4720-8649-05a083c03b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992208565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3992208565
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.505914223
Short name T167
Test name
Test status
Simulation time 103262987093 ps
CPU time 42.04 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:47 PM PDT 24
Peak memory 191844 kb
Host smart-0b9db761-76d3-4b19-b226-025288e3ab92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505914223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.505914223
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1570085008
Short name T121
Test name
Test status
Simulation time 403064899 ps
CPU time 0.75 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 196672 kb
Host smart-13c18422-7bfb-4bb4-9f4c-85dfb763f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570085008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1570085008
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.810603020
Short name T164
Test name
Test status
Simulation time 599261565 ps
CPU time 1.42 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:19 PM PDT 24
Peak memory 196740 kb
Host smart-516e1372-e01e-45ce-84aa-237e4344813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810603020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.810603020
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2131801405
Short name T173
Test name
Test status
Simulation time 334880779 ps
CPU time 1.16 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 196648 kb
Host smart-8b33c010-4743-47c9-bf19-6489c741662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131801405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2131801405
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1540686812
Short name T176
Test name
Test status
Simulation time 488743143 ps
CPU time 1.3 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:14:23 PM PDT 24
Peak memory 196632 kb
Host smart-d28339f9-3e5d-40d1-8e8c-66636383e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540686812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1540686812
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.533941534
Short name T11
Test name
Test status
Simulation time 460379757 ps
CPU time 0.75 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:14:23 PM PDT 24
Peak memory 196576 kb
Host smart-8c0ad745-3610-4feb-9883-b0b5787e1b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533941534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.533941534
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1349182263
Short name T177
Test name
Test status
Simulation time 514532584 ps
CPU time 0.79 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 196604 kb
Host smart-7ae063f1-d714-4db0-b9a5-65a788eb0e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349182263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1349182263
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3938379379
Short name T101
Test name
Test status
Simulation time 619113406 ps
CPU time 0.83 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 196624 kb
Host smart-62cee71f-0788-4e07-8c86-f4a08c9d4528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938379379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3938379379
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.801931874
Short name T181
Test name
Test status
Simulation time 436957924 ps
CPU time 0.92 seconds
Started Jul 31 05:14:31 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 196692 kb
Host smart-fffe153c-e1f7-4495-8bd2-29222f870fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801931874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.801931874
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3356274008
Short name T182
Test name
Test status
Simulation time 522945128 ps
CPU time 0.8 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:14:30 PM PDT 24
Peak memory 196612 kb
Host smart-e65fc8b0-63a7-4193-af3e-16d94f57ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356274008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3356274008
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3972015342
Short name T175
Test name
Test status
Simulation time 258654104427 ps
CPU time 398.88 seconds
Started Jul 31 05:14:43 PM PDT 24
Finished Jul 31 05:21:22 PM PDT 24
Peak memory 198248 kb
Host smart-26e52fa9-87ed-4230-aaa4-5fa9c902c330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972015342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3972015342
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2762369300
Short name T184
Test name
Test status
Simulation time 507611960 ps
CPU time 0.96 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:14:40 PM PDT 24
Peak memory 196708 kb
Host smart-830f6d39-7c77-4964-8c39-422ee4f64e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762369300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2762369300
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2603854968
Short name T172
Test name
Test status
Simulation time 399305763 ps
CPU time 0.74 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:14:11 PM PDT 24
Peak memory 196724 kb
Host smart-0021971a-b9d4-4c57-96db-5fc1aee2eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603854968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2603854968
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2053325318
Short name T190
Test name
Test status
Simulation time 8145483943 ps
CPU time 6.27 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:16 PM PDT 24
Peak memory 198240 kb
Host smart-1734a775-db6f-49a7-b1ff-666a2767aaa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053325318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2053325318
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2490497874
Short name T416
Test name
Test status
Simulation time 8367972248 ps
CPU time 14.78 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 198212 kb
Host smart-cd78d672-e1c2-48c9-abc9-82de04211457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490497874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2490497874
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1392712478
Short name T12
Test name
Test status
Simulation time 19139115465 ps
CPU time 188.47 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:17:25 PM PDT 24
Peak memory 213572 kb
Host smart-5d050393-538a-490f-95e5-98bfdee4b332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392712478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1392712478
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3644754083
Short name T159
Test name
Test status
Simulation time 463287470 ps
CPU time 0.73 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 196620 kb
Host smart-3b41c8b9-ae2a-4fee-815c-a717850dc083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644754083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3644754083
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3489781019
Short name T170
Test name
Test status
Simulation time 445720052 ps
CPU time 1.26 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 196648 kb
Host smart-90e7d58d-b511-4914-af4d-68278ac9095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489781019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3489781019
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1382195562
Short name T56
Test name
Test status
Simulation time 469123077 ps
CPU time 1.27 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 196644 kb
Host smart-9e2b3cb2-0aaa-4e98-ac8a-3b3a611a5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382195562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1382195562
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.994607491
Short name T26
Test name
Test status
Simulation time 561716023 ps
CPU time 0.79 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 196500 kb
Host smart-b3d0ce3b-869e-4089-9431-9ec6a181a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994607491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.994607491
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.229909107
Short name T68
Test name
Test status
Simulation time 612288799 ps
CPU time 1.5 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:15 PM PDT 24
Peak memory 183728 kb
Host smart-921e01f8-d0e1-4866-a1c1-dba9a818f163
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229909107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.229909107
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1775846106
Short name T399
Test name
Test status
Simulation time 7788263542 ps
CPU time 4.52 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:30 PM PDT 24
Peak memory 196352 kb
Host smart-eeab91fb-5d99-4a3f-aaf1-221ab3a816ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775846106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1775846106
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2296971335
Short name T339
Test name
Test status
Simulation time 1088286534 ps
CPU time 0.95 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 193160 kb
Host smart-d1060c7e-c755-4262-b4c2-fdd80db0fd07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296971335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2296971335
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3199299276
Short name T32
Test name
Test status
Simulation time 528907675 ps
CPU time 1.32 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 196480 kb
Host smart-a87220ba-2a99-4e9d-aebb-aefd62ad48c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199299276 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3199299276
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3880972152
Short name T375
Test name
Test status
Simulation time 476469856 ps
CPU time 0.75 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 193004 kb
Host smart-752634d1-d2a4-412c-8bd0-3d2f53464928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880972152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3880972152
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1980016460
Short name T310
Test name
Test status
Simulation time 333315320 ps
CPU time 0.62 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 193172 kb
Host smart-2e970a5e-e8ae-4b23-849d-8dbcce0cf1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980016460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1980016460
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3144436868
Short name T323
Test name
Test status
Simulation time 454678384 ps
CPU time 1.24 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 183624 kb
Host smart-ca2f846c-ff9c-48e0-ae22-292baa0e2029
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144436868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3144436868
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.734645759
Short name T400
Test name
Test status
Simulation time 462926767 ps
CPU time 0.54 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 183672 kb
Host smart-816e9d5b-0b09-4717-9b03-109b098baecd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734645759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.734645759
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3395565962
Short name T305
Test name
Test status
Simulation time 1236939214 ps
CPU time 1.48 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 193984 kb
Host smart-6fd79fa1-7e8d-49d2-89e3-3ef461fef5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395565962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3395565962
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3036115314
Short name T278
Test name
Test status
Simulation time 475454152 ps
CPU time 1.49 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 197252 kb
Host smart-99c6b7f8-67e4-47b5-a03a-630d8aacf00a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036115314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3036115314
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1709168306
Short name T390
Test name
Test status
Simulation time 4540308006 ps
CPU time 2.43 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 197744 kb
Host smart-040a4611-1057-4cde-861a-6f65d67e4f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709168306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1709168306
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1022348363
Short name T344
Test name
Test status
Simulation time 546033105 ps
CPU time 0.74 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 193160 kb
Host smart-101b09d8-2b1f-4527-9102-1c43ce9f0882
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022348363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1022348363
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1791341570
Short name T69
Test name
Test status
Simulation time 8291593350 ps
CPU time 5.16 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 195760 kb
Host smart-a4e269ae-01db-454e-b3c4-ebcb0984743f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791341570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1791341570
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2639521619
Short name T75
Test name
Test status
Simulation time 1065980272 ps
CPU time 0.92 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 183816 kb
Host smart-35630884-2c31-4965-a258-d849c8f63da8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639521619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2639521619
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.435190447
Short name T341
Test name
Test status
Simulation time 364435351 ps
CPU time 1.17 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 195292 kb
Host smart-e057e08c-c3a9-492e-9d35-47efa5154cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435190447 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.435190447
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2021589756
Short name T314
Test name
Test status
Simulation time 436287057 ps
CPU time 0.78 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 192968 kb
Host smart-240391a3-2bf9-49e1-82a9-b0d9ba3aabb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021589756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2021589756
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2928025228
Short name T293
Test name
Test status
Simulation time 341966198 ps
CPU time 0.64 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 183792 kb
Host smart-f354da42-2372-4294-9435-3ab6dbe8c5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928025228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2928025228
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.194369563
Short name T325
Test name
Test status
Simulation time 363442149 ps
CPU time 0.57 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 182752 kb
Host smart-946d00f5-861a-4944-bdd4-bdcae80c09d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194369563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.194369563
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3071443573
Short name T411
Test name
Test status
Simulation time 544133241 ps
CPU time 0.58 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 183580 kb
Host smart-9ddc78d5-f74d-4868-a804-a914a271b904
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071443573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3071443573
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2650738151
Short name T324
Test name
Test status
Simulation time 1420402810 ps
CPU time 1.65 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 192904 kb
Host smart-a9bb2e76-1676-4e0b-b8d6-fe809a778541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650738151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2650738151
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.555967020
Short name T358
Test name
Test status
Simulation time 662369243 ps
CPU time 1.53 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 198568 kb
Host smart-fad46bfc-2d90-49b5-a6aa-2d5be38db5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555967020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.555967020
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2187018700
Short name T330
Test name
Test status
Simulation time 498235567 ps
CPU time 1.33 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 195288 kb
Host smart-ad75a850-0bc3-4a2a-ae89-26dcc5d87d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187018700 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2187018700
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3850129389
Short name T72
Test name
Test status
Simulation time 348979558 ps
CPU time 0.65 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 193000 kb
Host smart-9008f9f9-3faa-41bc-be9f-cd0b53fbb5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850129389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3850129389
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2199580200
Short name T408
Test name
Test status
Simulation time 537721103 ps
CPU time 0.6 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 192920 kb
Host smart-d7b2e928-3d68-4689-a57b-8ab455080927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199580200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2199580200
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.342618319
Short name T398
Test name
Test status
Simulation time 3155226663 ps
CPU time 2.22 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 192052 kb
Host smart-590e866d-5524-4f58-b77a-c96a09f4b082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342618319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.342618319
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1375557466
Short name T357
Test name
Test status
Simulation time 500418219 ps
CPU time 1.75 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 198316 kb
Host smart-57cd405c-cd7c-4bdc-8e66-0162eccc8902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375557466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1375557466
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2612724571
Short name T35
Test name
Test status
Simulation time 7777938175 ps
CPU time 3.84 seconds
Started Jul 31 05:18:23 PM PDT 24
Finished Jul 31 05:18:27 PM PDT 24
Peak memory 198416 kb
Host smart-475e2ba5-e8a7-46a9-b3ef-42c0af6855ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612724571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2612724571
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2955208090
Short name T371
Test name
Test status
Simulation time 574641878 ps
CPU time 1.02 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:34 PM PDT 24
Peak memory 198324 kb
Host smart-39651e65-b101-476f-b8dd-8da57fcda1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955208090 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2955208090
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.865857988
Short name T294
Test name
Test status
Simulation time 426274551 ps
CPU time 1.19 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 193992 kb
Host smart-6ef8e7aa-880c-418f-ada1-fb928503b18d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865857988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.865857988
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3465369922
Short name T284
Test name
Test status
Simulation time 513219121 ps
CPU time 0.71 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 192980 kb
Host smart-61ca02ef-aea3-4144-914e-56353f23e470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465369922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3465369922
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2132739533
Short name T33
Test name
Test status
Simulation time 1235118822 ps
CPU time 1.41 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 194052 kb
Host smart-f329ecdd-b185-49b2-9cf0-53e1af5f6e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132739533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2132739533
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1066580267
Short name T283
Test name
Test status
Simulation time 1091282036 ps
CPU time 1.95 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 198568 kb
Host smart-f85cedf9-2724-44d5-92c5-9564baabbf1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066580267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1066580267
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.270905006
Short name T286
Test name
Test status
Simulation time 521608792 ps
CPU time 0.97 seconds
Started Jul 31 05:19:05 PM PDT 24
Finished Jul 31 05:19:07 PM PDT 24
Peak memory 195268 kb
Host smart-4159a6dd-c399-4bb7-ae7b-8f1384585a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270905006 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.270905006
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.311617746
Short name T382
Test name
Test status
Simulation time 339776195 ps
CPU time 0.61 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 183736 kb
Host smart-49b15d3c-0635-40df-9685-672c1314158f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311617746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.311617746
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4040462455
Short name T364
Test name
Test status
Simulation time 1312612870 ps
CPU time 1.91 seconds
Started Jul 31 05:19:46 PM PDT 24
Finished Jul 31 05:19:48 PM PDT 24
Peak memory 192776 kb
Host smart-1f5aaac4-bc8a-4cf0-ba0f-eeafc2185a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040462455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4040462455
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1842721552
Short name T279
Test name
Test status
Simulation time 314384095 ps
CPU time 1.53 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198636 kb
Host smart-faea5ad9-c2ba-4d5b-ada3-df394cc54c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842721552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1842721552
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4168625055
Short name T350
Test name
Test status
Simulation time 4472127003 ps
CPU time 6.86 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 197636 kb
Host smart-978a06fa-ad19-443c-a428-01d7fd3cef69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168625055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4168625055
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1439469883
Short name T335
Test name
Test status
Simulation time 467412484 ps
CPU time 1.39 seconds
Started Jul 31 05:19:26 PM PDT 24
Finished Jul 31 05:19:27 PM PDT 24
Peak memory 196092 kb
Host smart-ab531390-b971-44e2-b13d-0a90bc77d2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439469883 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1439469883
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1351923993
Short name T414
Test name
Test status
Simulation time 466235921 ps
CPU time 0.89 seconds
Started Jul 31 05:18:18 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 192028 kb
Host smart-412522d6-66e7-4d80-a9c8-57727c91fa8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351923993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1351923993
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3282265734
Short name T405
Test name
Test status
Simulation time 423767442 ps
CPU time 0.65 seconds
Started Jul 31 05:19:42 PM PDT 24
Finished Jul 31 05:19:43 PM PDT 24
Peak memory 183544 kb
Host smart-bd1a001e-8256-4764-a2d2-00ba7a6c7dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282265734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3282265734
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2072094336
Short name T80
Test name
Test status
Simulation time 2359300131 ps
CPU time 2.03 seconds
Started Jul 31 05:19:27 PM PDT 24
Finished Jul 31 05:19:29 PM PDT 24
Peak memory 183820 kb
Host smart-e88ca6a2-7c02-463f-9b3c-72b7de50c84e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072094336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2072094336
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3307323542
Short name T290
Test name
Test status
Simulation time 473011267 ps
CPU time 1.19 seconds
Started Jul 31 05:19:31 PM PDT 24
Finished Jul 31 05:19:32 PM PDT 24
Peak memory 198192 kb
Host smart-9ed3aedd-feb5-4e39-82b1-3e2e400f9053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307323542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3307323542
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2038392115
Short name T328
Test name
Test status
Simulation time 7756288640 ps
CPU time 11.88 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 198284 kb
Host smart-dfad6ffe-ab56-4a5c-8ff5-37369aa2a52b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038392115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2038392115
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2599244367
Short name T353
Test name
Test status
Simulation time 377291033 ps
CPU time 0.85 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 197020 kb
Host smart-133b734f-af16-43bc-8c2d-f92b5127636e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599244367 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2599244367
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.40327067
Short name T64
Test name
Test status
Simulation time 477687771 ps
CPU time 0.75 seconds
Started Jul 31 05:18:42 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 192992 kb
Host smart-a7e1728e-a672-4982-87ed-1682108344b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.40327067
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4004731102
Short name T277
Test name
Test status
Simulation time 338189167 ps
CPU time 1.11 seconds
Started Jul 31 05:19:35 PM PDT 24
Finished Jul 31 05:19:36 PM PDT 24
Peak memory 192764 kb
Host smart-9a8f9b90-ff3c-4818-846c-30c3cfe7e681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004731102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4004731102
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1190979792
Short name T81
Test name
Test status
Simulation time 2278312915 ps
CPU time 2.01 seconds
Started Jul 31 05:19:33 PM PDT 24
Finished Jul 31 05:19:35 PM PDT 24
Peak memory 194892 kb
Host smart-2ce83314-abc4-4114-8723-582e88a9f7a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190979792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1190979792
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1720372434
Short name T300
Test name
Test status
Simulation time 704336229 ps
CPU time 2.23 seconds
Started Jul 31 05:19:31 PM PDT 24
Finished Jul 31 05:19:33 PM PDT 24
Peak memory 198412 kb
Host smart-0c53176f-7bbb-46e3-baef-8ea7e1676fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720372434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1720372434
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.838723717
Short name T373
Test name
Test status
Simulation time 8047203509 ps
CPU time 12.31 seconds
Started Jul 31 05:19:05 PM PDT 24
Finished Jul 31 05:19:18 PM PDT 24
Peak memory 196120 kb
Host smart-38b2a368-aa1e-423f-9866-4bafc7216fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838723717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.838723717
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2632456876
Short name T288
Test name
Test status
Simulation time 349368749 ps
CPU time 0.98 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 196028 kb
Host smart-d02567aa-17db-4d11-b4ad-50e5c5d32808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632456876 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2632456876
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3947712420
Short name T309
Test name
Test status
Simulation time 436130839 ps
CPU time 0.85 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 192052 kb
Host smart-25ac442b-1755-4cd4-82a7-4f2bbdc24d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947712420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3947712420
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3652500382
Short name T365
Test name
Test status
Simulation time 391760437 ps
CPU time 1.05 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 192996 kb
Host smart-d76250bb-43ec-46f6-81fb-a19bdeb59300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652500382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3652500382
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.300461685
Short name T313
Test name
Test status
Simulation time 1010313661 ps
CPU time 1.7 seconds
Started Jul 31 05:19:32 PM PDT 24
Finished Jul 31 05:19:34 PM PDT 24
Peak memory 193180 kb
Host smart-7c2e2662-e6af-4e01-8d06-9a4eb3cb4969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300461685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.300461685
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2045359954
Short name T329
Test name
Test status
Simulation time 511915964 ps
CPU time 0.92 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 198332 kb
Host smart-51482a0c-a6c8-49a7-9f9e-2adb67025ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045359954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2045359954
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.191374218
Short name T189
Test name
Test status
Simulation time 4339127808 ps
CPU time 3.72 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 196764 kb
Host smart-590b7794-766b-4395-ba9e-24227f438ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191374218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.191374218
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1499223349
Short name T401
Test name
Test status
Simulation time 386266631 ps
CPU time 0.96 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 196568 kb
Host smart-0df9da8e-57eb-4093-a767-6a46bb4f28c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499223349 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1499223349
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3920184734
Short name T61
Test name
Test status
Simulation time 422535172 ps
CPU time 0.79 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 193520 kb
Host smart-7be6424b-cf26-441c-b618-5d191b25118e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920184734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3920184734
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.654444189
Short name T361
Test name
Test status
Simulation time 467044275 ps
CPU time 0.7 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 193012 kb
Host smart-9740df07-4ff7-440b-8710-9b629fcb8eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654444189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.654444189
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3516245280
Short name T374
Test name
Test status
Simulation time 3161028374 ps
CPU time 8.35 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 194304 kb
Host smart-e04ee11c-df94-44e8-a0b4-df3d637013bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516245280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3516245280
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1701162195
Short name T345
Test name
Test status
Simulation time 408391822 ps
CPU time 2.3 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:17 PM PDT 24
Peak memory 198632 kb
Host smart-048cd343-ded3-4202-b1a4-686d9896da5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701162195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1701162195
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3128470505
Short name T188
Test name
Test status
Simulation time 4485952093 ps
CPU time 3.66 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 197960 kb
Host smart-74e4f0f0-9edc-47bf-b674-bcf6da4df9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128470505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3128470505
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3684225268
Short name T289
Test name
Test status
Simulation time 565075883 ps
CPU time 1.02 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 197800 kb
Host smart-84158443-6ed0-4116-804d-19ae754d5e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684225268 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3684225268
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3556754205
Short name T388
Test name
Test status
Simulation time 438992527 ps
CPU time 0.71 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 194028 kb
Host smart-8108ca7c-eccb-4db7-a2f3-160bccc72740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556754205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3556754205
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2818134820
Short name T347
Test name
Test status
Simulation time 339700932 ps
CPU time 0.58 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 183796 kb
Host smart-89ebab8a-371f-4164-8991-354dab8c6e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818134820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2818134820
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2975854183
Short name T76
Test name
Test status
Simulation time 2125250237 ps
CPU time 0.99 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 183752 kb
Host smart-53007095-82a5-4bb7-9768-ba2b6e415e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975854183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2975854183
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.900251409
Short name T370
Test name
Test status
Simulation time 421503113 ps
CPU time 1.6 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 198308 kb
Host smart-940789f2-f762-4d20-9557-b799a8aa3d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900251409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.900251409
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2050442288
Short name T192
Test name
Test status
Simulation time 9509244808 ps
CPU time 2.09 seconds
Started Jul 31 05:18:35 PM PDT 24
Finished Jul 31 05:18:37 PM PDT 24
Peak memory 198452 kb
Host smart-d939bf9f-be0b-4ceb-a7a9-5dbbcaab2f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050442288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2050442288
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3500042815
Short name T352
Test name
Test status
Simulation time 503795443 ps
CPU time 1.27 seconds
Started Jul 31 05:18:34 PM PDT 24
Finished Jul 31 05:18:36 PM PDT 24
Peak memory 196320 kb
Host smart-2c24fa1b-d09c-42cc-8b9e-89e1e4e00e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500042815 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3500042815
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1197465067
Short name T394
Test name
Test status
Simulation time 508111580 ps
CPU time 0.71 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 192956 kb
Host smart-30b1367c-6671-403b-8717-1c78a14dc1a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197465067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1197465067
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2946353456
Short name T397
Test name
Test status
Simulation time 514820522 ps
CPU time 0.68 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 183720 kb
Host smart-75b76705-6261-4606-8dfb-a0c34494dd6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946353456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2946353456
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1055926341
Short name T392
Test name
Test status
Simulation time 2312260369 ps
CPU time 2.02 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 194924 kb
Host smart-e6287052-e040-427a-9f42-237d93673ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055926341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1055926341
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1139897085
Short name T356
Test name
Test status
Simulation time 813530897 ps
CPU time 1.77 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:34 PM PDT 24
Peak memory 198824 kb
Host smart-6ccd13c5-9638-47c7-b289-908c7c11dad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139897085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1139897085
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.315916589
Short name T191
Test name
Test status
Simulation time 4615403940 ps
CPU time 5.07 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 198076 kb
Host smart-2d14d6e7-6c83-48ee-9706-6f7fdcf9095c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315916589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.315916589
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.485351404
Short name T301
Test name
Test status
Simulation time 545098879 ps
CPU time 0.92 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 197492 kb
Host smart-243b7262-740d-4688-945d-f1c3ad9aec0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485351404 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.485351404
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.492352116
Short name T65
Test name
Test status
Simulation time 446361512 ps
CPU time 0.72 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:15 PM PDT 24
Peak memory 192068 kb
Host smart-3a66dd7e-8c4a-4665-88cc-c9e21473ce50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492352116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.492352116
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2203710665
Short name T319
Test name
Test status
Simulation time 397845424 ps
CPU time 1.07 seconds
Started Jul 31 05:18:30 PM PDT 24
Finished Jul 31 05:18:31 PM PDT 24
Peak memory 183796 kb
Host smart-16e5e809-853c-4aaf-a6d1-8ee0e4f3bc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203710665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2203710665
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2605916165
Short name T79
Test name
Test status
Simulation time 2478205765 ps
CPU time 5.14 seconds
Started Jul 31 05:18:25 PM PDT 24
Finished Jul 31 05:18:30 PM PDT 24
Peak memory 184056 kb
Host smart-a6cb6297-1f23-493f-b3ed-4375dae49907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605916165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2605916165
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3477169513
Short name T320
Test name
Test status
Simulation time 460979486 ps
CPU time 2.48 seconds
Started Jul 31 05:18:26 PM PDT 24
Finished Jul 31 05:18:29 PM PDT 24
Peak memory 198620 kb
Host smart-0e8356ab-c447-4d63-b36a-d72c7d6f83d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477169513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3477169513
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4028565028
Short name T316
Test name
Test status
Simulation time 8160637975 ps
CPU time 7.17 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 198372 kb
Host smart-666b4fe1-8104-4dc8-98b0-a9b773302c22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028565028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4028565028
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.590588386
Short name T413
Test name
Test status
Simulation time 740375719 ps
CPU time 1.27 seconds
Started Jul 31 05:17:58 PM PDT 24
Finished Jul 31 05:18:00 PM PDT 24
Peak memory 191988 kb
Host smart-48ec002d-27e1-429b-9ea0-fd3301eda321
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590588386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.590588386
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.231733482
Short name T66
Test name
Test status
Simulation time 7127068793 ps
CPU time 3.56 seconds
Started Jul 31 05:18:16 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 196580 kb
Host smart-310b012c-425e-45af-ac9c-dfa5ea4048e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231733482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.231733482
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3776348989
Short name T303
Test name
Test status
Simulation time 962435460 ps
CPU time 0.95 seconds
Started Jul 31 05:17:59 PM PDT 24
Finished Jul 31 05:18:00 PM PDT 24
Peak memory 183724 kb
Host smart-df08742c-108d-481d-ba60-7f101ee963f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776348989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3776348989
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3923706517
Short name T195
Test name
Test status
Simulation time 488126199 ps
CPU time 0.79 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 195604 kb
Host smart-8d0850c0-d57d-4d07-bb4e-9d918ec9388b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923706517 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3923706517
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2304732753
Short name T369
Test name
Test status
Simulation time 502551921 ps
CPU time 1.38 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 193316 kb
Host smart-f328543a-060f-4aba-90fe-7d0ca2fd9bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304732753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2304732753
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2803720292
Short name T354
Test name
Test status
Simulation time 348919263 ps
CPU time 0.68 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 183724 kb
Host smart-f0636ef8-854a-4d37-8ec1-641ab73dbaaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803720292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2803720292
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2748959501
Short name T285
Test name
Test status
Simulation time 372054610 ps
CPU time 0.64 seconds
Started Jul 31 05:18:13 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 183648 kb
Host smart-72d88cce-a52e-4ed1-8c54-9721dbfc5c13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748959501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2748959501
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2759951720
Short name T317
Test name
Test status
Simulation time 426120283 ps
CPU time 1.21 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 183580 kb
Host smart-d9c45b8e-aa3c-4ba7-92c3-e0444c844556
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759951720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2759951720
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4057244238
Short name T78
Test name
Test status
Simulation time 1698509033 ps
CPU time 1.24 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 193032 kb
Host smart-cdfeabdd-c69f-4e86-9527-1fbcb5da76ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057244238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4057244238
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4048099150
Short name T367
Test name
Test status
Simulation time 672732570 ps
CPU time 1.56 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 198608 kb
Host smart-3841742d-b006-4604-b4de-bda7d66f6f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048099150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4048099150
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3569359093
Short name T360
Test name
Test status
Simulation time 4369213334 ps
CPU time 7.07 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 197992 kb
Host smart-a8247922-05bf-4067-b982-b25fa9086829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569359093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3569359093
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3048831289
Short name T337
Test name
Test status
Simulation time 385259277 ps
CPU time 0.74 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:27 PM PDT 24
Peak memory 183724 kb
Host smart-cbc5a2f1-df7b-4fc7-ac00-737867137f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048831289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3048831289
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2036280672
Short name T287
Test name
Test status
Simulation time 521193156 ps
CPU time 0.57 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:04 PM PDT 24
Peak memory 183784 kb
Host smart-b7f04f07-f55a-4c35-a21d-47bb5e42e12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036280672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2036280672
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3703963718
Short name T338
Test name
Test status
Simulation time 479759156 ps
CPU time 1.26 seconds
Started Jul 31 05:18:01 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 183756 kb
Host smart-97d7ccde-5e43-411d-8bfa-8a8365777861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703963718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3703963718
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1936531774
Short name T348
Test name
Test status
Simulation time 361030248 ps
CPU time 0.78 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 183724 kb
Host smart-625b186e-e70f-4ab1-8e58-b3771800a7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936531774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1936531774
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.873869961
Short name T407
Test name
Test status
Simulation time 297854785 ps
CPU time 0.72 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 183796 kb
Host smart-f31a35c4-81cb-4b49-8b06-d37467c2cea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873869961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.873869961
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2241931091
Short name T307
Test name
Test status
Simulation time 421376574 ps
CPU time 0.63 seconds
Started Jul 31 05:18:26 PM PDT 24
Finished Jul 31 05:18:27 PM PDT 24
Peak memory 183768 kb
Host smart-c8747005-da84-4ecb-860c-dd7051e59aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241931091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2241931091
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2323605871
Short name T299
Test name
Test status
Simulation time 356082843 ps
CPU time 0.57 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 183736 kb
Host smart-addb4164-d4b1-48f8-8dea-abf40b694378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323605871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2323605871
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3077222186
Short name T386
Test name
Test status
Simulation time 379385186 ps
CPU time 0.75 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 192956 kb
Host smart-ec2dc7d1-088a-49e7-a4b6-ccf6c1a138a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077222186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3077222186
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1071825287
Short name T409
Test name
Test status
Simulation time 296722781 ps
CPU time 0.66 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 183772 kb
Host smart-88d3f015-af74-4386-b26d-8a1f6fba7522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071825287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1071825287
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2842092440
Short name T378
Test name
Test status
Simulation time 384438568 ps
CPU time 0.65 seconds
Started Jul 31 05:18:20 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 183772 kb
Host smart-1a2c959a-552a-4f10-80bf-40cbb27ba050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842092440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2842092440
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2070477057
Short name T74
Test name
Test status
Simulation time 530959663 ps
CPU time 0.94 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 183744 kb
Host smart-b478e47d-4af8-4953-9e05-4a92a416d585
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070477057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2070477057
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1258943989
Short name T73
Test name
Test status
Simulation time 8954991022 ps
CPU time 4.23 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 184132 kb
Host smart-c96e8d3b-b58b-433a-a1e8-488d0ac6f60f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258943989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1258943989
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.628177552
Short name T311
Test name
Test status
Simulation time 1097421754 ps
CPU time 0.95 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 192988 kb
Host smart-b82fd686-34ba-4ff5-af37-05b7090b1586
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628177552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.628177552
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.350055846
Short name T387
Test name
Test status
Simulation time 452135436 ps
CPU time 1.31 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:22 PM PDT 24
Peak memory 196068 kb
Host smart-86720e9f-cf7a-4c96-b859-2e097e48169e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350055846 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.350055846
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.748102723
Short name T363
Test name
Test status
Simulation time 554797212 ps
CPU time 0.77 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 193556 kb
Host smart-f2af58a4-a525-4cb5-8d36-e63194d47f1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748102723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.748102723
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1672884152
Short name T280
Test name
Test status
Simulation time 517169622 ps
CPU time 0.74 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 192964 kb
Host smart-f76e117a-f770-4031-8526-73f231b92c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672884152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1672884152
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1822990500
Short name T372
Test name
Test status
Simulation time 330228313 ps
CPU time 1.03 seconds
Started Jul 31 05:18:18 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 183700 kb
Host smart-8bcf84ba-5af4-49ef-a3b1-d17ad3e661f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822990500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1822990500
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1514337422
Short name T326
Test name
Test status
Simulation time 295454388 ps
CPU time 0.92 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 183640 kb
Host smart-d522a88e-6097-4a68-a7b6-c6f6e1f85864
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514337422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1514337422
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2711567431
Short name T306
Test name
Test status
Simulation time 1428900416 ps
CPU time 1.06 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 191960 kb
Host smart-062bab78-fff5-4693-8256-44e2fbfc1eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711567431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2711567431
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.419972237
Short name T368
Test name
Test status
Simulation time 673114149 ps
CPU time 1.62 seconds
Started Jul 31 05:18:20 PM PDT 24
Finished Jul 31 05:18:22 PM PDT 24
Peak memory 198664 kb
Host smart-1be6b8f2-906d-49b1-903b-e1d7631b72ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419972237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.419972237
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3956684064
Short name T36
Test name
Test status
Simulation time 8915311020 ps
CPU time 11.75 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 198328 kb
Host smart-20fb42bf-552a-477b-a166-f3703e2f6835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956684064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3956684064
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.114113689
Short name T412
Test name
Test status
Simulation time 414788041 ps
CPU time 0.68 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 183716 kb
Host smart-05a22475-f9ef-4c13-8d32-9eef312fedc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114113689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.114113689
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.569544101
Short name T349
Test name
Test status
Simulation time 317653014 ps
CPU time 1.04 seconds
Started Jul 31 05:18:12 PM PDT 24
Finished Jul 31 05:18:18 PM PDT 24
Peak memory 192936 kb
Host smart-42ad46b4-f155-48dd-95e0-46e6fea4d370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569544101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.569544101
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2037730556
Short name T340
Test name
Test status
Simulation time 367398446 ps
CPU time 0.58 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 183756 kb
Host smart-69bb83a0-e536-41f6-92ba-c6ce7487c32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037730556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2037730556
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2558631424
Short name T336
Test name
Test status
Simulation time 283931622 ps
CPU time 0.99 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 183772 kb
Host smart-11cb2acc-279e-405e-9afb-43602a6b42c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558631424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2558631424
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1461844479
Short name T389
Test name
Test status
Simulation time 428413967 ps
CPU time 1.11 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 192944 kb
Host smart-d0be9c04-eb3b-4e33-9f59-fc422e7e8b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461844479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1461844479
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3490894297
Short name T331
Test name
Test status
Simulation time 523185468 ps
CPU time 0.71 seconds
Started Jul 31 05:18:25 PM PDT 24
Finished Jul 31 05:18:26 PM PDT 24
Peak memory 192988 kb
Host smart-17ce6a08-cc5e-4b3b-85d7-a6524dad64a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490894297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3490894297
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.197760931
Short name T366
Test name
Test status
Simulation time 299067788 ps
CPU time 0.73 seconds
Started Jul 31 05:18:16 PM PDT 24
Finished Jul 31 05:18:17 PM PDT 24
Peak memory 192896 kb
Host smart-235c8cb8-2f42-44ae-8198-81de7d855c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197760931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.197760931
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2432954462
Short name T297
Test name
Test status
Simulation time 313490581 ps
CPU time 0.73 seconds
Started Jul 31 05:18:13 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 183724 kb
Host smart-a52880e9-5832-4b1b-ba51-252009bfe4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432954462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2432954462
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2206420530
Short name T296
Test name
Test status
Simulation time 443917172 ps
CPU time 1.19 seconds
Started Jul 31 05:18:16 PM PDT 24
Finished Jul 31 05:18:17 PM PDT 24
Peak memory 183772 kb
Host smart-acc11c15-a2c1-40ac-9bf2-5fd18972f359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206420530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2206420530
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3745993729
Short name T343
Test name
Test status
Simulation time 454201009 ps
CPU time 0.68 seconds
Started Jul 31 05:18:20 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 183724 kb
Host smart-e5c9f1da-d2d0-4f3f-8062-7b4a177f8ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745993729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3745993729
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3712035470
Short name T67
Test name
Test status
Simulation time 512637123 ps
CPU time 1.01 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 194352 kb
Host smart-840c354f-b0b0-450f-b0ee-1b992a032568
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712035470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3712035470
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.456577994
Short name T70
Test name
Test status
Simulation time 717832724 ps
CPU time 1.82 seconds
Started Jul 31 05:18:22 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 192148 kb
Host smart-725d9733-4158-40e9-a1a8-208d066f6cb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456577994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.456577994
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2930238010
Short name T312
Test name
Test status
Simulation time 1263115991 ps
CPU time 0.99 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 193212 kb
Host smart-262bde90-7818-4b0a-8112-d3fb5cc61345
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930238010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2930238010
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.919690732
Short name T315
Test name
Test status
Simulation time 476733409 ps
CPU time 1.35 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 195824 kb
Host smart-ccc42942-99df-4d7d-90a6-319a0b5cb2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919690732 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.919690732
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.590143065
Short name T194
Test name
Test status
Simulation time 410468728 ps
CPU time 0.88 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:08 PM PDT 24
Peak memory 193416 kb
Host smart-ce706fa3-505d-424c-b520-63bd8d965b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590143065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.590143065
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2799702951
Short name T384
Test name
Test status
Simulation time 374508559 ps
CPU time 1.15 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 183680 kb
Host smart-9dec2cfe-9e1b-4165-b6ca-38441e4fc25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799702951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2799702951
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.971264740
Short name T318
Test name
Test status
Simulation time 372209162 ps
CPU time 0.59 seconds
Started Jul 31 05:18:02 PM PDT 24
Finished Jul 31 05:18:03 PM PDT 24
Peak memory 183700 kb
Host smart-7a03cbf2-6ed7-49d9-9102-85159babd3c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971264740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.971264740
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3483839857
Short name T304
Test name
Test status
Simulation time 470330754 ps
CPU time 1.13 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:02 PM PDT 24
Peak memory 183656 kb
Host smart-d60808e4-753f-4904-8392-e0f18f3d268e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483839857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3483839857
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3864223140
Short name T406
Test name
Test status
Simulation time 2162072390 ps
CPU time 1.92 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 192092 kb
Host smart-7225e020-dec3-41d1-9d46-1a9c0458d32a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864223140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3864223140
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3170540719
Short name T302
Test name
Test status
Simulation time 485718161 ps
CPU time 2.22 seconds
Started Jul 31 05:18:07 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 198608 kb
Host smart-e5c0d43c-374c-44fe-b125-a72267690c22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170540719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3170540719
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1285854739
Short name T391
Test name
Test status
Simulation time 9082167672 ps
CPU time 8.1 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:15 PM PDT 24
Peak memory 198136 kb
Host smart-da331bb7-8199-4380-9dec-25587b971363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285854739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1285854739
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1924088766
Short name T282
Test name
Test status
Simulation time 526092950 ps
CPU time 0.69 seconds
Started Jul 31 05:18:29 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 193016 kb
Host smart-56623516-6186-4dd8-af67-98361b07c708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924088766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1924088766
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068227787
Short name T346
Test name
Test status
Simulation time 409135513 ps
CPU time 0.62 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 183720 kb
Host smart-b77a7229-c0af-4c85-9cb5-f9d27cb2e645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068227787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1068227787
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.762075503
Short name T355
Test name
Test status
Simulation time 340900927 ps
CPU time 1.06 seconds
Started Jul 31 05:18:26 PM PDT 24
Finished Jul 31 05:18:27 PM PDT 24
Peak memory 183780 kb
Host smart-68176735-a43c-4e62-8be5-0e4fe20e346b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762075503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.762075503
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1736845879
Short name T403
Test name
Test status
Simulation time 491268664 ps
CPU time 1.24 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:32 PM PDT 24
Peak memory 183768 kb
Host smart-0b851098-5703-4aef-be78-3131139861a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736845879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1736845879
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4026190122
Short name T351
Test name
Test status
Simulation time 362776053 ps
CPU time 1.05 seconds
Started Jul 31 05:18:06 PM PDT 24
Finished Jul 31 05:18:07 PM PDT 24
Peak memory 183736 kb
Host smart-5402c48f-05c9-4a62-b56b-125b22ed4afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026190122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4026190122
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.569471187
Short name T395
Test name
Test status
Simulation time 355314936 ps
CPU time 0.98 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 192672 kb
Host smart-d71fe8ee-0198-4423-9427-f7d75739b8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569471187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.569471187
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1713002288
Short name T376
Test name
Test status
Simulation time 483867599 ps
CPU time 1.26 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 183756 kb
Host smart-50f45949-b9e3-4a52-82c1-d245e95fb175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713002288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1713002288
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1621812676
Short name T359
Test name
Test status
Simulation time 266914613 ps
CPU time 0.88 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:16 PM PDT 24
Peak memory 192992 kb
Host smart-dc248724-241b-4f24-a785-235bd1e5d8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621812676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1621812676
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4270960672
Short name T332
Test name
Test status
Simulation time 366127279 ps
CPU time 1.08 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 183740 kb
Host smart-2b7e6b07-03f3-4215-8503-9adb84adfd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270960672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4270960672
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.319675982
Short name T291
Test name
Test status
Simulation time 466418984 ps
CPU time 0.73 seconds
Started Jul 31 05:18:39 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 183760 kb
Host smart-fd5cd723-e1c9-4d0c-a1b4-e3edc28d4bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319675982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.319675982
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2227820467
Short name T379
Test name
Test status
Simulation time 399005894 ps
CPU time 0.74 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 196020 kb
Host smart-e0c181e5-cede-4549-9ab2-d42a03da19a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227820467 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2227820467
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2073852000
Short name T62
Test name
Test status
Simulation time 390946082 ps
CPU time 0.75 seconds
Started Jul 31 05:18:20 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 193576 kb
Host smart-dbc95fa5-c48e-451b-a288-85f242ca45bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073852000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2073852000
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2372377509
Short name T334
Test name
Test status
Simulation time 443270026 ps
CPU time 0.82 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:09 PM PDT 24
Peak memory 183712 kb
Host smart-d0c954ae-f55e-43f7-8a13-4c35f22ef505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372377509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2372377509
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.266421381
Short name T77
Test name
Test status
Simulation time 1267661236 ps
CPU time 1.03 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 194076 kb
Host smart-791bf43c-c94c-4122-b04a-bd13b0e501b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266421381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.266421381
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.797679492
Short name T322
Test name
Test status
Simulation time 301080654 ps
CPU time 1.48 seconds
Started Jul 31 05:18:30 PM PDT 24
Finished Jul 31 05:18:32 PM PDT 24
Peak memory 198524 kb
Host smart-7caea47b-ded3-4b66-9256-5f9385d6290a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797679492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.797679492
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.731398964
Short name T383
Test name
Test status
Simulation time 503237530 ps
CPU time 0.93 seconds
Started Jul 31 05:18:24 PM PDT 24
Finished Jul 31 05:18:25 PM PDT 24
Peak memory 197868 kb
Host smart-2d5b6277-08ed-40da-a57f-6d05ca608d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731398964 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.731398964
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3792086967
Short name T396
Test name
Test status
Simulation time 313551313 ps
CPU time 0.63 seconds
Started Jul 31 05:18:13 PM PDT 24
Finished Jul 31 05:18:14 PM PDT 24
Peak memory 192900 kb
Host smart-2cd83ef0-b3cc-4824-bb2a-e39a4ad9201e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792086967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3792086967
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2293737253
Short name T321
Test name
Test status
Simulation time 413569477 ps
CPU time 0.78 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 183760 kb
Host smart-9e7e24e3-aef9-4fd1-a537-7acdd45a8b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293737253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2293737253
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2455772226
Short name T362
Test name
Test status
Simulation time 1042366528 ps
CPU time 2.05 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:05 PM PDT 24
Peak memory 192968 kb
Host smart-1ddea4bd-0f1f-4d27-8751-90fe2fdbac43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455772226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2455772226
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4139154028
Short name T281
Test name
Test status
Simulation time 713564834 ps
CPU time 1.73 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 198600 kb
Host smart-7f9eb27e-a730-4472-a635-c88130611bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139154028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4139154028
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1993107362
Short name T295
Test name
Test status
Simulation time 8855069994 ps
CPU time 13.76 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 198184 kb
Host smart-fa9d680e-1f61-4e67-8c09-8dfcbee2dc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993107362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1993107362
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4211712227
Short name T410
Test name
Test status
Simulation time 358801304 ps
CPU time 0.98 seconds
Started Jul 31 05:18:29 PM PDT 24
Finished Jul 31 05:18:30 PM PDT 24
Peak memory 196084 kb
Host smart-1bd5b2a1-12f0-41da-8170-fd45c6e252ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211712227 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4211712227
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3411558586
Short name T31
Test name
Test status
Simulation time 505923064 ps
CPU time 1.3 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 193372 kb
Host smart-6486b841-293f-41ad-a598-78fe3f7c1159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411558586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3411558586
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3824722520
Short name T393
Test name
Test status
Simulation time 496336024 ps
CPU time 1.31 seconds
Started Jul 31 05:18:38 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 183736 kb
Host smart-a932b7d4-0349-47a4-8500-37dd89914f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824722520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3824722520
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.73126720
Short name T342
Test name
Test status
Simulation time 2368371203 ps
CPU time 1.48 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 195016 kb
Host smart-52d0ff05-79f4-4282-aef4-025f9cd8b8e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73126720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_t
imer_same_csr_outstanding.73126720
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1858985675
Short name T333
Test name
Test status
Simulation time 421488360 ps
CPU time 2.33 seconds
Started Jul 31 05:18:09 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 198652 kb
Host smart-970be2d8-f258-484a-a64f-b410f3183f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858985675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1858985675
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.753921538
Short name T327
Test name
Test status
Simulation time 4550618419 ps
CPU time 4.06 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 197672 kb
Host smart-315434a4-456c-49fb-a830-a0c24d6c0b91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753921538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.753921538
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1520638464
Short name T298
Test name
Test status
Simulation time 485506946 ps
CPU time 0.79 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:11 PM PDT 24
Peak memory 195480 kb
Host smart-adf2a3f3-95b7-4c0d-b1b2-df0371ecc93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520638464 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1520638464
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3614384639
Short name T402
Test name
Test status
Simulation time 360606977 ps
CPU time 0.65 seconds
Started Jul 31 05:18:28 PM PDT 24
Finished Jul 31 05:18:29 PM PDT 24
Peak memory 191960 kb
Host smart-ed2fa36f-835e-42ae-92f0-a02904e6a790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614384639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3614384639
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.475666093
Short name T308
Test name
Test status
Simulation time 494216148 ps
CPU time 1.21 seconds
Started Jul 31 05:18:04 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 183712 kb
Host smart-47727a45-7a24-4005-85d9-1fd7a60639a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475666093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.475666093
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1585325139
Short name T82
Test name
Test status
Simulation time 1845592960 ps
CPU time 3.78 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 193004 kb
Host smart-d0766f40-f851-4ade-96ee-463818fa4b22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585325139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1585325139
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3448237286
Short name T404
Test name
Test status
Simulation time 1141781406 ps
CPU time 2.53 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 198628 kb
Host smart-9d916f0a-f28d-4439-8a4d-94512a68034a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448237286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3448237286
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.815562808
Short name T415
Test name
Test status
Simulation time 8467288954 ps
CPU time 7.96 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:27 PM PDT 24
Peak memory 198308 kb
Host smart-e761934d-9ae1-4164-a280-96504f7f38ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815562808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.815562808
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4270378932
Short name T381
Test name
Test status
Simulation time 489599151 ps
CPU time 1.36 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:16 PM PDT 24
Peak memory 196012 kb
Host smart-a48d0033-3654-4bdc-b760-ee5a0076265e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270378932 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4270378932
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1578490277
Short name T71
Test name
Test status
Simulation time 399873206 ps
CPU time 0.75 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:06 PM PDT 24
Peak memory 193096 kb
Host smart-833cd4b0-daa0-48d9-93a9-c23ff8f8b240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578490277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1578490277
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.639341257
Short name T385
Test name
Test status
Simulation time 457445004 ps
CPU time 1.18 seconds
Started Jul 31 05:18:00 PM PDT 24
Finished Jul 31 05:18:01 PM PDT 24
Peak memory 183756 kb
Host smart-ccf3074f-c372-4dd8-801b-dd9ad9e587b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639341257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.639341257
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3101045539
Short name T380
Test name
Test status
Simulation time 2375218851 ps
CPU time 6.63 seconds
Started Jul 31 05:18:03 PM PDT 24
Finished Jul 31 05:18:10 PM PDT 24
Peak memory 194232 kb
Host smart-286b8da2-9bfd-4f38-95af-af2ad6c86942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101045539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3101045539
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2371352539
Short name T292
Test name
Test status
Simulation time 451758505 ps
CPU time 2.09 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:18 PM PDT 24
Peak memory 198528 kb
Host smart-f5e443a5-3609-4606-bb3e-9282289d5394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371352539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2371352539
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2435560383
Short name T377
Test name
Test status
Simulation time 8041925000 ps
CPU time 2.01 seconds
Started Jul 31 05:18:18 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 198360 kb
Host smart-be6b5aac-822f-4a5d-be16-ccce260dcc73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435560383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2435560383
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3545353292
Short name T179
Test name
Test status
Simulation time 559873900 ps
CPU time 0.9 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:14:01 PM PDT 24
Peak memory 196624 kb
Host smart-9e229bd0-86e1-41ea-8f88-c3699830e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545353292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3545353292
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2078985774
Short name T246
Test name
Test status
Simulation time 9692009953 ps
CPU time 15.48 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:14:16 PM PDT 24
Peak memory 191824 kb
Host smart-19d78d43-13c8-479e-9670-6b434f500123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078985774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2078985774
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1632890974
Short name T2
Test name
Test status
Simulation time 494303416 ps
CPU time 0.95 seconds
Started Jul 31 05:14:00 PM PDT 24
Finished Jul 31 05:14:02 PM PDT 24
Peak memory 191800 kb
Host smart-95ddb911-7936-43cf-a780-a9053ef3c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632890974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1632890974
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4169273352
Short name T269
Test name
Test status
Simulation time 14708399900 ps
CPU time 22.06 seconds
Started Jul 31 05:14:01 PM PDT 24
Finished Jul 31 05:14:23 PM PDT 24
Peak memory 191872 kb
Host smart-3d329f57-66ee-45fc-82f2-823cb83995d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169273352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4169273352
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1476403586
Short name T14
Test name
Test status
Simulation time 8408196895 ps
CPU time 2.43 seconds
Started Jul 31 05:14:02 PM PDT 24
Finished Jul 31 05:14:04 PM PDT 24
Peak memory 215772 kb
Host smart-4309ce67-b626-4308-9a79-3ae9c8d6a72d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476403586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1476403586
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1397026297
Short name T257
Test name
Test status
Simulation time 565670315 ps
CPU time 1.34 seconds
Started Jul 31 05:14:01 PM PDT 24
Finished Jul 31 05:14:02 PM PDT 24
Peak memory 196592 kb
Host smart-51f5c88e-8e73-499f-ad4a-5ecc47da28e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397026297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1397026297
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2752167346
Short name T187
Test name
Test status
Simulation time 577367828 ps
CPU time 1.49 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:14:14 PM PDT 24
Peak memory 196604 kb
Host smart-4d7bf731-8f0a-4f76-9f8c-0be1ee8ea194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752167346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2752167346
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3909763889
Short name T266
Test name
Test status
Simulation time 27153133338 ps
CPU time 18.95 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 196836 kb
Host smart-3cf7cdcd-658b-497b-b980-0b72785355fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909763889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3909763889
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.315578920
Short name T196
Test name
Test status
Simulation time 493233834 ps
CPU time 1.01 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:11 PM PDT 24
Peak memory 191800 kb
Host smart-8e974129-0f83-455c-b6e1-34eb59c17885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315578920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.315578920
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1031287536
Short name T235
Test name
Test status
Simulation time 27855018647 ps
CPU time 36.19 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:47 PM PDT 24
Peak memory 191884 kb
Host smart-8755b23f-ec51-48b9-8b50-c220ee295155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031287536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1031287536
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3431002617
Short name T1
Test name
Test status
Simulation time 468529922 ps
CPU time 0.95 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:14:16 PM PDT 24
Peak memory 196612 kb
Host smart-f313aa86-89e2-4910-8055-19263b0694ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431002617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3431002617
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1126144659
Short name T240
Test name
Test status
Simulation time 17797065050 ps
CPU time 12.98 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:30 PM PDT 24
Peak memory 191868 kb
Host smart-82b4f3fa-7bdb-4849-9479-6fb539971c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126144659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1126144659
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.223363115
Short name T230
Test name
Test status
Simulation time 483411814 ps
CPU time 0.82 seconds
Started Jul 31 05:14:18 PM PDT 24
Finished Jul 31 05:14:19 PM PDT 24
Peak memory 196640 kb
Host smart-0c9a9295-85e3-451c-974e-709d3bc0f9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223363115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.223363115
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1456993738
Short name T171
Test name
Test status
Simulation time 566802636 ps
CPU time 0.83 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:14:17 PM PDT 24
Peak memory 196720 kb
Host smart-ade71e12-b531-4455-a622-a60e16e8433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456993738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1456993738
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3651392297
Short name T256
Test name
Test status
Simulation time 29555164970 ps
CPU time 11.62 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 191860 kb
Host smart-60be9083-a9ab-435e-9135-020334228154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651392297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3651392297
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3867893191
Short name T58
Test name
Test status
Simulation time 541889968 ps
CPU time 0.75 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 196580 kb
Host smart-215cc4ce-6296-48bf-8e21-2fab42a061a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867893191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3867893191
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1700429049
Short name T242
Test name
Test status
Simulation time 545792223 ps
CPU time 0.8 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 196556 kb
Host smart-4bc328a7-d2c4-47b0-9f53-4b38f72b8f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700429049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1700429049
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2994489233
Short name T262
Test name
Test status
Simulation time 411143375 ps
CPU time 0.76 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:14:17 PM PDT 24
Peak memory 191840 kb
Host smart-06fb36b5-ea45-4363-b1d7-dbde6d4dd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994489233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2994489233
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.500214616
Short name T223
Test name
Test status
Simulation time 29990376945 ps
CPU time 19.73 seconds
Started Jul 31 05:14:18 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 191844 kb
Host smart-e2601756-7743-4fa7-b4d8-f71d419ad9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500214616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.500214616
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3248838541
Short name T268
Test name
Test status
Simulation time 441036965 ps
CPU time 0.92 seconds
Started Jul 31 05:14:19 PM PDT 24
Finished Jul 31 05:14:20 PM PDT 24
Peak memory 191744 kb
Host smart-187acab7-752d-41f4-8378-49185793efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248838541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3248838541
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.320015036
Short name T234
Test name
Test status
Simulation time 39021927724 ps
CPU time 13.05 seconds
Started Jul 31 05:14:15 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 191812 kb
Host smart-cd9d8524-fc22-4ef0-962d-9619438c233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320015036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.320015036
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4145384831
Short name T226
Test name
Test status
Simulation time 498178775 ps
CPU time 1.37 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:25 PM PDT 24
Peak memory 191696 kb
Host smart-4b6001b6-4510-4eab-9e62-19cb89e83aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145384831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4145384831
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1146999527
Short name T237
Test name
Test status
Simulation time 2747794233 ps
CPU time 4.62 seconds
Started Jul 31 05:14:16 PM PDT 24
Finished Jul 31 05:14:21 PM PDT 24
Peak memory 196712 kb
Host smart-9cc2a0c9-aca6-4480-ab95-7a1944eb4ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146999527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1146999527
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1740373377
Short name T255
Test name
Test status
Simulation time 514439663 ps
CPU time 0.71 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:24 PM PDT 24
Peak memory 196536 kb
Host smart-3f69f9eb-5dc9-4be6-8680-cb89270f63fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740373377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1740373377
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.556961035
Short name T198
Test name
Test status
Simulation time 37730024187 ps
CPU time 13.81 seconds
Started Jul 31 05:14:18 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 191816 kb
Host smart-217d889e-050c-4a71-a88b-2bd08d30bad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556961035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.556961035
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2334427327
Short name T215
Test name
Test status
Simulation time 679196889 ps
CPU time 0.68 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:24 PM PDT 24
Peak memory 196524 kb
Host smart-597b4469-6cb4-4611-a868-ddf0d36fd008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334427327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2334427327
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.846460873
Short name T239
Test name
Test status
Simulation time 36067154632 ps
CPU time 4.52 seconds
Started Jul 31 05:14:20 PM PDT 24
Finished Jul 31 05:14:25 PM PDT 24
Peak memory 191864 kb
Host smart-e3ea636a-23a0-4b60-842e-26cabe1337c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846460873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.846460873
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.4052383872
Short name T7
Test name
Test status
Simulation time 579161870 ps
CPU time 1.08 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 191784 kb
Host smart-b24fc2a3-821a-4d0c-bed2-86e9ed65f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052383872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4052383872
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.962471176
Short name T183
Test name
Test status
Simulation time 456779283 ps
CPU time 0.78 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:14:04 PM PDT 24
Peak memory 196592 kb
Host smart-7775748b-5f52-4ece-bef0-e47b1bac516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962471176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.962471176
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.220591120
Short name T259
Test name
Test status
Simulation time 27043862551 ps
CPU time 11.1 seconds
Started Jul 31 05:14:06 PM PDT 24
Finished Jul 31 05:14:17 PM PDT 24
Peak memory 196872 kb
Host smart-95279dcb-2576-4def-8a24-12a63106dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220591120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.220591120
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2848613339
Short name T16
Test name
Test status
Simulation time 3926829214 ps
CPU time 3.36 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:07 PM PDT 24
Peak memory 215332 kb
Host smart-34b7480d-5c9c-4637-ab0c-25286434b9da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848613339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2848613339
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1957812445
Short name T253
Test name
Test status
Simulation time 407330104 ps
CPU time 1.2 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:11 PM PDT 24
Peak memory 196620 kb
Host smart-57fd611a-f71e-44d9-93bf-4a2f890c80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957812445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1957812445
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2872392390
Short name T258
Test name
Test status
Simulation time 11918500171 ps
CPU time 15.46 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:40 PM PDT 24
Peak memory 191828 kb
Host smart-673e8057-9f6d-4469-bbe6-f2fa84c80980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872392390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2872392390
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3164959711
Short name T214
Test name
Test status
Simulation time 388684388 ps
CPU time 0.83 seconds
Started Jul 31 05:14:31 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 196664 kb
Host smart-54ef3239-9123-4c44-99c0-13002eaa3631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164959711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3164959711
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3822673958
Short name T200
Test name
Test status
Simulation time 38986516151 ps
CPU time 45.57 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:15:10 PM PDT 24
Peak memory 191780 kb
Host smart-c73556b0-1b68-4cdf-882d-06e4cd4b8648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822673958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3822673958
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.997070034
Short name T212
Test name
Test status
Simulation time 455988944 ps
CPU time 1.13 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 191844 kb
Host smart-bd5f4454-c027-4a48-b7c5-239914d25499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997070034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.997070034
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.41291329
Short name T41
Test name
Test status
Simulation time 51059380680 ps
CPU time 16.1 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:39 PM PDT 24
Peak memory 191848 kb
Host smart-cea27b92-38e7-4afd-9e09-d923c299d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41291329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.41291329
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.980912785
Short name T219
Test name
Test status
Simulation time 432318308 ps
CPU time 1.22 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:14:24 PM PDT 24
Peak memory 191796 kb
Host smart-7c259f09-12f1-4647-bcfb-97419e8f4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980912785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.980912785
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1215463926
Short name T156
Test name
Test status
Simulation time 353825816 ps
CPU time 1.07 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:14:23 PM PDT 24
Peak memory 196652 kb
Host smart-42b8d250-e8cd-4107-ac1e-b189cac0f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215463926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1215463926
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2241213643
Short name T218
Test name
Test status
Simulation time 59895902934 ps
CPU time 86.01 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:15:56 PM PDT 24
Peak memory 191856 kb
Host smart-5e82d044-0b64-404e-9fd8-fdd088436361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241213643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2241213643
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.320838691
Short name T249
Test name
Test status
Simulation time 466796020 ps
CPU time 0.92 seconds
Started Jul 31 05:14:22 PM PDT 24
Finished Jul 31 05:14:24 PM PDT 24
Peak memory 191752 kb
Host smart-229258d6-540f-44c4-8a86-965c139fa299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320838691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.320838691
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3761042841
Short name T162
Test name
Test status
Simulation time 545043878 ps
CPU time 0.79 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 196564 kb
Host smart-2a9eaee7-8a51-462a-9c13-133ed6ef6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761042841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3761042841
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2725045024
Short name T47
Test name
Test status
Simulation time 21493491118 ps
CPU time 14.69 seconds
Started Jul 31 05:14:23 PM PDT 24
Finished Jul 31 05:14:38 PM PDT 24
Peak memory 191848 kb
Host smart-13468739-0c54-401b-859b-7d40a0693657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725045024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2725045024
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.620343771
Short name T210
Test name
Test status
Simulation time 462119740 ps
CPU time 1.32 seconds
Started Jul 31 05:14:25 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 191816 kb
Host smart-1e272f33-f563-4cac-8f0a-d7949c5d95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620343771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.620343771
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2387410959
Short name T206
Test name
Test status
Simulation time 23708539941 ps
CPU time 37.77 seconds
Started Jul 31 05:14:28 PM PDT 24
Finished Jul 31 05:15:06 PM PDT 24
Peak memory 196860 kb
Host smart-05204c0a-4306-4810-a67f-397007fa5dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387410959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2387410959
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2032410406
Short name T229
Test name
Test status
Simulation time 585636932 ps
CPU time 0.77 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 191836 kb
Host smart-60adaf61-1f59-4e73-be41-1fcad403c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032410406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2032410406
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1991086639
Short name T25
Test name
Test status
Simulation time 214256387651 ps
CPU time 280.72 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:19:10 PM PDT 24
Peak memory 191856 kb
Host smart-1fca72eb-df99-483a-91fc-148d25f138e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991086639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1991086639
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.38321044
Short name T220
Test name
Test status
Simulation time 18503035814 ps
CPU time 6.96 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:33 PM PDT 24
Peak memory 196948 kb
Host smart-5c7036c9-c95e-4f93-b54d-cbe906b989f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38321044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.38321044
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4019261273
Short name T248
Test name
Test status
Simulation time 381991292 ps
CPU time 1.04 seconds
Started Jul 31 05:14:32 PM PDT 24
Finished Jul 31 05:14:33 PM PDT 24
Peak memory 191836 kb
Host smart-28613bde-cdee-4a70-b133-76b52a3acd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019261273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4019261273
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3215184833
Short name T23
Test name
Test status
Simulation time 6968789901 ps
CPU time 3.13 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:30 PM PDT 24
Peak memory 191884 kb
Host smart-1e3c82d6-e59d-4132-b65c-603b255ba8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215184833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3215184833
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1279863031
Short name T272
Test name
Test status
Simulation time 442918852 ps
CPU time 1.21 seconds
Started Jul 31 05:14:24 PM PDT 24
Finished Jul 31 05:14:26 PM PDT 24
Peak memory 191804 kb
Host smart-c6d0f5b4-3d36-44af-9872-cdca67ab6c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279863031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1279863031
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2734704709
Short name T130
Test name
Test status
Simulation time 357872149 ps
CPU time 0.88 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 196668 kb
Host smart-4630d5b4-b0f5-492e-aa74-189fb8364fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734704709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2734704709
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.267642392
Short name T48
Test name
Test status
Simulation time 33179437554 ps
CPU time 13.85 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:39 PM PDT 24
Peak memory 196836 kb
Host smart-6bdc0ded-0250-482e-8aa5-d654c009c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267642392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.267642392
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.248881219
Short name T228
Test name
Test status
Simulation time 397968649 ps
CPU time 0.71 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:30 PM PDT 24
Peak memory 196628 kb
Host smart-f98f7f6f-d7f7-4452-af3e-c8051e8d30ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248881219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.248881219
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2602908200
Short name T227
Test name
Test status
Simulation time 19647245889 ps
CPU time 15.27 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:43 PM PDT 24
Peak memory 191892 kb
Host smart-8217149d-1a3b-44c9-865c-2c66129744ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602908200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2602908200
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3393093607
Short name T233
Test name
Test status
Simulation time 520170832 ps
CPU time 0.86 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 191784 kb
Host smart-a51be4c4-fce1-4c65-abe7-a7bde4e79704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393093607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3393093607
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.984712677
Short name T241
Test name
Test status
Simulation time 32434269272 ps
CPU time 15.14 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:14:19 PM PDT 24
Peak memory 196888 kb
Host smart-2bcd63be-dde6-4d82-b8a6-e850f864e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984712677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.984712677
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2041545851
Short name T17
Test name
Test status
Simulation time 8298964062 ps
CPU time 3.01 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 215716 kb
Host smart-6c88d81a-8ec3-4010-8e13-96f4ab8af373
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041545851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2041545851
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1913326786
Short name T236
Test name
Test status
Simulation time 443834818 ps
CPU time 0.87 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:05 PM PDT 24
Peak memory 191744 kb
Host smart-9cdaa9ad-f784-4d63-91c1-1c43bbf5a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913326786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1913326786
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.740196482
Short name T169
Test name
Test status
Simulation time 519287865 ps
CPU time 1.31 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:29 PM PDT 24
Peak memory 196672 kb
Host smart-afec32c4-7030-411e-abe4-772d1b066fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740196482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.740196482
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.535931332
Short name T222
Test name
Test status
Simulation time 20868502019 ps
CPU time 33.32 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:15:16 PM PDT 24
Peak memory 191888 kb
Host smart-c0af5c99-68d6-4f13-8e40-bfeae2caeef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535931332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.535931332
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2676710161
Short name T244
Test name
Test status
Simulation time 573364924 ps
CPU time 0.98 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 191796 kb
Host smart-f8550445-25b9-407f-8cc4-a92430eef6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676710161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2676710161
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3209979000
Short name T276
Test name
Test status
Simulation time 26567374284 ps
CPU time 36.37 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:15:07 PM PDT 24
Peak memory 191868 kb
Host smart-328b26ee-c6de-4f60-a993-89118f9296f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209979000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3209979000
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2323898866
Short name T208
Test name
Test status
Simulation time 401611080 ps
CPU time 1.14 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 191748 kb
Host smart-1466f2a0-674d-4b8a-8092-854b4b5dd17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323898866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2323898866
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.746129368
Short name T44
Test name
Test status
Simulation time 11168533654 ps
CPU time 3.91 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:46 PM PDT 24
Peak memory 191900 kb
Host smart-6028ef77-2f99-474e-84cf-5aee35a3296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746129368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.746129368
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.990317702
Short name T225
Test name
Test status
Simulation time 554634486 ps
CPU time 1.36 seconds
Started Jul 31 05:14:27 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 196624 kb
Host smart-efb6afb5-a890-4495-9b4c-0dbf236357b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990317702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.990317702
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1048456067
Short name T252
Test name
Test status
Simulation time 19303306891 ps
CPU time 7.54 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:38 PM PDT 24
Peak memory 197052 kb
Host smart-55187859-ecb1-468c-8be1-e33a785b4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048456067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1048456067
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.910467843
Short name T264
Test name
Test status
Simulation time 408776742 ps
CPU time 1.11 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 191820 kb
Host smart-ed4b07d8-2aeb-4656-a33d-cc961d1acd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910467843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.910467843
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3290121761
Short name T274
Test name
Test status
Simulation time 18863260703 ps
CPU time 25.35 seconds
Started Jul 31 05:14:28 PM PDT 24
Finished Jul 31 05:14:54 PM PDT 24
Peak memory 191844 kb
Host smart-1d029b77-7902-46b8-adc9-1ce926956609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290121761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3290121761
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2814452899
Short name T232
Test name
Test status
Simulation time 540847267 ps
CPU time 1.31 seconds
Started Jul 31 05:14:26 PM PDT 24
Finished Jul 31 05:14:27 PM PDT 24
Peak memory 191800 kb
Host smart-6baefd14-fec9-4683-aacb-9794400802d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814452899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2814452899
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1165706705
Short name T231
Test name
Test status
Simulation time 57023477386 ps
CPU time 22.24 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:58 PM PDT 24
Peak memory 196640 kb
Host smart-1b0f33ff-110c-49de-b506-c33920bdf738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165706705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1165706705
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1785092019
Short name T254
Test name
Test status
Simulation time 465379086 ps
CPU time 1.29 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:44 PM PDT 24
Peak memory 191836 kb
Host smart-6715390b-949a-4670-b6fa-f62b3bc36b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785092019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1785092019
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2033907372
Short name T265
Test name
Test status
Simulation time 44280543383 ps
CPU time 14.85 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:45 PM PDT 24
Peak memory 191888 kb
Host smart-04310a50-d663-4d49-8ea9-bfac18c9b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033907372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2033907372
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1909836336
Short name T3
Test name
Test status
Simulation time 486505582 ps
CPU time 0.62 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 196624 kb
Host smart-8baab37c-a5b3-4af2-88d0-cb9bb3a88729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909836336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1909836336
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1655519992
Short name T186
Test name
Test status
Simulation time 526815213 ps
CPU time 1.2 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 196612 kb
Host smart-0ff0a2c5-e436-40db-b971-89e4f6135319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655519992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1655519992
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.325252421
Short name T199
Test name
Test status
Simulation time 20947856237 ps
CPU time 14.47 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:55 PM PDT 24
Peak memory 196864 kb
Host smart-5666f278-31ce-473b-9c4a-8bb414292c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325252421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.325252421
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2818212718
Short name T213
Test name
Test status
Simulation time 434191662 ps
CPU time 0.75 seconds
Started Jul 31 05:14:31 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 196600 kb
Host smart-020b2bd9-1a85-4450-b475-9259ae2a4527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818212718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2818212718
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1861313902
Short name T178
Test name
Test status
Simulation time 434031175 ps
CPU time 1.2 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 196600 kb
Host smart-d1159bfe-8e8e-4d5d-9dfc-85e562193ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861313902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1861313902
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.849478846
Short name T273
Test name
Test status
Simulation time 33854848444 ps
CPU time 26.2 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:15:03 PM PDT 24
Peak memory 196848 kb
Host smart-2b80ed2c-265c-43b4-9d8f-7721e5ee3810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849478846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.849478846
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2517153044
Short name T224
Test name
Test status
Simulation time 519635329 ps
CPU time 1.32 seconds
Started Jul 31 05:14:29 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 191836 kb
Host smart-413ed93b-38f0-4234-94fa-5d890586df88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517153044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2517153044
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3574336673
Short name T147
Test name
Test status
Simulation time 391071677 ps
CPU time 0.72 seconds
Started Jul 31 05:14:30 PM PDT 24
Finished Jul 31 05:14:31 PM PDT 24
Peak memory 196704 kb
Host smart-41c87064-9709-4c2b-a79c-7866a1a8da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574336673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3574336673
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1362185314
Short name T42
Test name
Test status
Simulation time 7144083830 ps
CPU time 11.29 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:54 PM PDT 24
Peak memory 191896 kb
Host smart-650762ed-8a6e-4174-a16a-c0012f746899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362185314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1362185314
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.551486025
Short name T261
Test name
Test status
Simulation time 440676611 ps
CPU time 1.27 seconds
Started Jul 31 05:14:28 PM PDT 24
Finished Jul 31 05:14:29 PM PDT 24
Peak memory 196612 kb
Host smart-ae604c40-e465-4668-bd09-d218ec92b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551486025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.551486025
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.637024832
Short name T43
Test name
Test status
Simulation time 22327335466 ps
CPU time 8.09 seconds
Started Jul 31 05:14:06 PM PDT 24
Finished Jul 31 05:14:14 PM PDT 24
Peak memory 191864 kb
Host smart-ea4c7e0c-a84a-40dd-aea5-d4f5c9dba388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637024832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.637024832
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.231082052
Short name T15
Test name
Test status
Simulation time 8469355666 ps
CPU time 2.82 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:07 PM PDT 24
Peak memory 215736 kb
Host smart-5eb864a2-2317-4109-94ac-37335a152bbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231082052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.231082052
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4112185479
Short name T202
Test name
Test status
Simulation time 557509140 ps
CPU time 0.74 seconds
Started Jul 31 05:14:06 PM PDT 24
Finished Jul 31 05:14:07 PM PDT 24
Peak memory 191812 kb
Host smart-f65e1600-0078-4966-8fb5-b22c37ff957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112185479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4112185479
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3398492338
Short name T6
Test name
Test status
Simulation time 8219297301 ps
CPU time 3.47 seconds
Started Jul 31 05:14:33 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 196888 kb
Host smart-90ae2e05-e7f5-4843-aa04-399d1e7dadb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398492338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3398492338
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1507794866
Short name T22
Test name
Test status
Simulation time 379202120 ps
CPU time 0.84 seconds
Started Jul 31 05:14:33 PM PDT 24
Finished Jul 31 05:14:33 PM PDT 24
Peak memory 191824 kb
Host smart-9836eace-4131-45a1-aeda-96b24ca3ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507794866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1507794866
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.823453709
Short name T243
Test name
Test status
Simulation time 3167717943 ps
CPU time 3.04 seconds
Started Jul 31 05:14:38 PM PDT 24
Finished Jul 31 05:14:41 PM PDT 24
Peak memory 191876 kb
Host smart-d32caee0-f392-4ea4-a3c5-11fe1dc8cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823453709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.823453709
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1639280579
Short name T201
Test name
Test status
Simulation time 535325542 ps
CPU time 0.75 seconds
Started Jul 31 05:14:37 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 191828 kb
Host smart-4b9ce00f-be6e-4b27-acf7-ccdcf2adb5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639280579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1639280579
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3238105422
Short name T57
Test name
Test status
Simulation time 25966597983 ps
CPU time 9.24 seconds
Started Jul 31 05:14:37 PM PDT 24
Finished Jul 31 05:14:46 PM PDT 24
Peak memory 191900 kb
Host smart-46ef9b4b-f518-4b58-8d4c-265b630492a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238105422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3238105422
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2491654890
Short name T204
Test name
Test status
Simulation time 412703332 ps
CPU time 1.11 seconds
Started Jul 31 05:14:32 PM PDT 24
Finished Jul 31 05:14:34 PM PDT 24
Peak memory 191812 kb
Host smart-182626dc-0680-457f-9362-3e81ca95e6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491654890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2491654890
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3852444370
Short name T275
Test name
Test status
Simulation time 55722749352 ps
CPU time 20.69 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:56 PM PDT 24
Peak memory 191848 kb
Host smart-6daa22b2-b361-433f-81b3-82c660dd613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852444370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3852444370
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3138233006
Short name T250
Test name
Test status
Simulation time 410175931 ps
CPU time 1.1 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 191828 kb
Host smart-8759afc5-eb97-4d8a-ba4e-330057b92296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138233006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3138233006
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3808788482
Short name T166
Test name
Test status
Simulation time 463400033 ps
CPU time 1.24 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 196604 kb
Host smart-738bfe63-e721-4c00-8cf4-00991a38de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808788482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3808788482
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3546486724
Short name T193
Test name
Test status
Simulation time 11234086947 ps
CPU time 2.16 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 191888 kb
Host smart-1ff0b733-88df-47bb-b8b1-8d1e2ab4adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546486724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3546486724
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1171755149
Short name T271
Test name
Test status
Simulation time 440708029 ps
CPU time 0.67 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 196680 kb
Host smart-2680375e-f4ee-4e48-ad15-30832981040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171755149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1171755149
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2049477530
Short name T45
Test name
Test status
Simulation time 394012665 ps
CPU time 0.78 seconds
Started Jul 31 05:14:33 PM PDT 24
Finished Jul 31 05:14:34 PM PDT 24
Peak memory 196672 kb
Host smart-8638aac7-dc12-40de-a1bd-21f04d31cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049477530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2049477530
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2707107025
Short name T245
Test name
Test status
Simulation time 22717575902 ps
CPU time 34.89 seconds
Started Jul 31 05:14:33 PM PDT 24
Finished Jul 31 05:15:08 PM PDT 24
Peak memory 191844 kb
Host smart-402bda8a-6a84-4393-9e01-6c10835f9eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707107025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2707107025
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.93813586
Short name T217
Test name
Test status
Simulation time 644106216 ps
CPU time 0.7 seconds
Started Jul 31 05:14:35 PM PDT 24
Finished Jul 31 05:14:36 PM PDT 24
Peak memory 191824 kb
Host smart-80cf5ba2-7bb5-4c29-b135-11d4e171c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93813586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.93813586
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.711334906
Short name T197
Test name
Test status
Simulation time 25696481167 ps
CPU time 35.35 seconds
Started Jul 31 05:14:34 PM PDT 24
Finished Jul 31 05:15:09 PM PDT 24
Peak memory 196912 kb
Host smart-9f5052f1-7623-40f2-bae5-e4b8e32d749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711334906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.711334906
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4253002203
Short name T263
Test name
Test status
Simulation time 745508515 ps
CPU time 0.64 seconds
Started Jul 31 05:14:36 PM PDT 24
Finished Jul 31 05:14:37 PM PDT 24
Peak memory 191804 kb
Host smart-afdcabb4-b9d3-4630-8486-ff3af1a3d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253002203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4253002203
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3595029121
Short name T207
Test name
Test status
Simulation time 6723324775 ps
CPU time 2.4 seconds
Started Jul 31 05:14:39 PM PDT 24
Finished Jul 31 05:14:46 PM PDT 24
Peak memory 191864 kb
Host smart-54759be0-c19b-4516-b30c-848a5ca27b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595029121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3595029121
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1813791880
Short name T24
Test name
Test status
Simulation time 392204233 ps
CPU time 1.03 seconds
Started Jul 31 05:14:42 PM PDT 24
Finished Jul 31 05:14:43 PM PDT 24
Peak memory 191700 kb
Host smart-b1685e0e-ec88-4cfb-9fe0-ed9a9dd28fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813791880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1813791880
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.899507407
Short name T8
Test name
Test status
Simulation time 319027773881 ps
CPU time 75.16 seconds
Started Jul 31 05:14:41 PM PDT 24
Finished Jul 31 05:15:57 PM PDT 24
Peak memory 191868 kb
Host smart-148bcb4c-6a57-4d8a-a07e-a6eaabef7b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899507407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.899507407
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1341153314
Short name T216
Test name
Test status
Simulation time 11938648146 ps
CPU time 5.11 seconds
Started Jul 31 05:14:40 PM PDT 24
Finished Jul 31 05:14:45 PM PDT 24
Peak memory 191892 kb
Host smart-089c30e8-b764-4d5a-8231-338767ce9335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341153314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1341153314
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.777047521
Short name T205
Test name
Test status
Simulation time 395319269 ps
CPU time 0.88 seconds
Started Jul 31 05:14:39 PM PDT 24
Finished Jul 31 05:14:40 PM PDT 24
Peak memory 191740 kb
Host smart-d841801f-6efe-4095-b750-a94d69f54e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777047521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.777047521
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1247916576
Short name T238
Test name
Test status
Simulation time 24613601468 ps
CPU time 38.95 seconds
Started Jul 31 05:14:43 PM PDT 24
Finished Jul 31 05:15:22 PM PDT 24
Peak memory 191880 kb
Host smart-1b1394c0-45a4-469d-8d44-f7ee90f24a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247916576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1247916576
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3040683241
Short name T270
Test name
Test status
Simulation time 546805320 ps
CPU time 0.95 seconds
Started Jul 31 05:14:43 PM PDT 24
Finished Jul 31 05:14:44 PM PDT 24
Peak memory 191824 kb
Host smart-36371e20-23cf-413b-b8b5-b9cf52da81a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040683241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3040683241
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3347324777
Short name T46
Test name
Test status
Simulation time 57422893940 ps
CPU time 24.12 seconds
Started Jul 31 05:14:03 PM PDT 24
Finished Jul 31 05:14:28 PM PDT 24
Peak memory 191864 kb
Host smart-f55d9124-81ec-45ac-baa2-6f37531aa56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347324777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3347324777
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1478852569
Short name T247
Test name
Test status
Simulation time 569962235 ps
CPU time 0.65 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:04 PM PDT 24
Peak memory 191824 kb
Host smart-fdedf724-e780-42f7-b0c3-01a682a11fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478852569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1478852569
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2376057800
Short name T211
Test name
Test status
Simulation time 760778715 ps
CPU time 0.88 seconds
Started Jul 31 05:14:04 PM PDT 24
Finished Jul 31 05:14:05 PM PDT 24
Peak memory 191824 kb
Host smart-89fe7977-5e5a-45d7-a7d8-e007b5913b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376057800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2376057800
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.753979958
Short name T28
Test name
Test status
Simulation time 422792213 ps
CPU time 1.11 seconds
Started Jul 31 05:14:05 PM PDT 24
Finished Jul 31 05:14:06 PM PDT 24
Peak memory 196584 kb
Host smart-6b54a5e6-3b69-4f06-8980-559a701ebdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753979958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.753979958
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1889363688
Short name T260
Test name
Test status
Simulation time 2628704718 ps
CPU time 1.47 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:12 PM PDT 24
Peak memory 196660 kb
Host smart-02a1b084-e0c7-4c3c-932d-3dda973fd4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889363688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1889363688
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.626076074
Short name T267
Test name
Test status
Simulation time 499592554 ps
CPU time 0.82 seconds
Started Jul 31 05:14:09 PM PDT 24
Finished Jul 31 05:14:10 PM PDT 24
Peak memory 191756 kb
Host smart-ad706157-0ad3-48fb-b28b-2df24718582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626076074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.626076074
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4106854083
Short name T174
Test name
Test status
Simulation time 424825248 ps
CPU time 0.69 seconds
Started Jul 31 05:14:10 PM PDT 24
Finished Jul 31 05:14:11 PM PDT 24
Peak memory 196744 kb
Host smart-37340d13-8125-4c00-97f5-cb1c3f77efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106854083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4106854083
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1896032763
Short name T221
Test name
Test status
Simulation time 8651955096 ps
CPU time 12.36 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:14:24 PM PDT 24
Peak memory 191820 kb
Host smart-7e94c452-c44f-4580-afb5-f4223a43dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896032763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1896032763
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2483679937
Short name T203
Test name
Test status
Simulation time 463028113 ps
CPU time 1.32 seconds
Started Jul 31 05:14:17 PM PDT 24
Finished Jul 31 05:14:18 PM PDT 24
Peak memory 191820 kb
Host smart-29adacdb-0bcb-40d1-9fa4-cc1f0645f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483679937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2483679937
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1497624025
Short name T209
Test name
Test status
Simulation time 14245256134 ps
CPU time 21.31 seconds
Started Jul 31 05:14:11 PM PDT 24
Finished Jul 31 05:14:32 PM PDT 24
Peak memory 191856 kb
Host smart-1ae48946-260e-4941-8143-867365e4c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497624025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1497624025
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2104932657
Short name T251
Test name
Test status
Simulation time 489781352 ps
CPU time 0.67 seconds
Started Jul 31 05:14:14 PM PDT 24
Finished Jul 31 05:14:15 PM PDT 24
Peak memory 191776 kb
Host smart-8c51aecc-fcb7-4e36-9d9f-5597c6204e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104932657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2104932657
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4094900053
Short name T92
Test name
Test status
Simulation time 10283158009 ps
CPU time 72.36 seconds
Started Jul 31 05:14:12 PM PDT 24
Finished Jul 31 05:15:24 PM PDT 24
Peak memory 206676 kb
Host smart-8575668f-5787-4132-b79d-6874066ec95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094900053 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4094900053
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%