Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	27660	1		T1	12		T2	10		T3	10
bark[1]	138	1		T39	21		T112	21		T192	14
bark[2]	610	1		T5	21		T97	30		T117	21
bark[3]	645	1		T16	21		T33	112		T136	47
bark[4]	995	1		T4	31		T16	31		T30	72
bark[5]	552	1		T8	21		T22	14		T135	7
bark[6]	275	1		T186	14		T143	21		T101	57
bark[7]	959	1		T4	42		T14	26		T30	250
bark[8]	571	1		T140	21		T121	85		T174	14
bark[9]	301	1		T4	21		T14	78		T36	7
bark[10]	822	1		T5	54		T13	65		T15	14
bark[11]	569	1		T43	26		T138	14		T107	81
bark[12]	395	1		T5	21		T140	21		T116	14
bark[13]	430	1		T14	201		T43	42		T124	47
bark[14]	201	1		T14	21		T44	14		T98	26
bark[15]	237	1		T13	43		T146	14		T147	21
bark[16]	456	1		T121	289		T124	21		T147	21
bark[17]	500	1		T31	49		T35	21		T140	59
bark[18]	399	1		T107	21		T119	21		T123	14
bark[19]	737	1		T21	14		T121	21		T99	73
bark[20]	415	1		T31	21		T36	21		T154	21
bark[21]	395	1		T14	26		T37	14		T121	21
bark[22]	587	1		T32	21		T34	7		T117	21
bark[23]	210	1		T199	14		T165	7		T164	26
bark[24]	602	1		T14	30		T30	31		T32	21
bark[25]	617	1		T5	21		T36	210		T121	30
bark[26]	525	1		T31	26		T32	149		T121	206
bark[27]	205	1		T203	14		T149	14		T98	48
bark[28]	486	1		T30	30		T121	21		T102	57
bark[29]	750	1		T8	30		T13	26		T121	26
bark[30]	340	1		T13	5		T136	26		T108	43
bark[31]	526	1		T5	68		T149	21		T127	14
bark_0	4687	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	27675	1		T1	11		T2	9		T3	9
bite[1]	617	1		T31	25		T35	125		T203	13
bite[2]	1005	1		T4	31		T34	114		T36	209
bite[3]	253	1		T121	21		T149	13		T143	21
bite[4]	468	1		T33	111		T124	57		T127	13
bite[5]	285	1		T100	30		T147	21		T107	21
bite[6]	172	1		T4	21		T5	53		T114	21
bite[7]	710	1		T186	13		T101	56		T155	185
bite[8]	324	1		T13	21		T32	21		T121	56
bite[9]	387	1		T13	42		T14	21		T30	71
bite[10]	82	1		T5	30		T135	6		T152	21
bite[11]	521	1		T5	21		T8	30		T13	25
bite[12]	597	1		T30	249		T143	21		T98	215
bite[13]	301	1		T125	21		T122	30		T151	13
bite[14]	162	1		T5	21		T98	47		T174	13
bite[15]	381	1		T5	38		T37	13		T34	6
bite[16]	347	1		T35	21		T140	21		T121	21
bite[17]	1171	1		T21	13		T14	200		T143	32
bite[18]	241	1		T14	33		T30	31		T124	47
bite[19]	1206	1		T16	31		T39	21		T97	30
bite[20]	910	1		T5	38		T16	21		T36	6
bite[21]	318	1		T13	4		T121	84		T117	21
bite[22]	516	1		T13	64		T30	30		T99	21
bite[23]	689	1		T31	48		T44	13		T36	21
bite[24]	177	1		T4	42		T98	25		T154	21
bite[25]	115	1		T143	21		T99	21		T101	21
bite[26]	650	1		T31	21		T32	148		T43	42
bite[27]	372	1		T136	47		T121	21		T164	21
bite[28]	212	1		T14	90		T31	21		T114	21
bite[29]	297	1		T185	13		T199	13		T166	13
bite[30]	506	1		T15	13		T152	32		T161	4
bite[31]	913	1		T8	21		T22	13		T34	207
bite_0	5217	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	41145	1		T1	19		T2	17		T3	17
auto[1]	6652	1		T4	20		T5	68		T7	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1154	1		T30	9		T96	24		T32	67
prescale[1]	1139	1		T32	41		T33	28		T121	76
prescale[2]	803	1		T5	37		T14	77		T30	156
prescale[3]	508	1		T8	32		T14	41		T30	49
prescale[4]	458	1		T8	42		T31	75		T33	2
prescale[5]	1387	1		T5	28		T8	58		T14	24
prescale[6]	1097	1		T10	9		T16	100		T30	125
prescale[7]	853	1		T13	2		T14	9		T30	62
prescale[8]	987	1		T39	28		T30	77		T31	36
prescale[9]	761	1		T13	2		T14	75		T32	9
prescale[10]	625	1		T5	9		T13	32		T30	28
prescale[11]	667	1		T36	51		T143	34		T211	9
prescale[12]	422	1		T14	51		T96	19		T32	109
prescale[13]	426	1		T13	2		T14	37		T16	54
prescale[14]	994	1		T12	9		T14	31		T121	38
prescale[15]	631	1		T14	37		T16	2		T41	9
prescale[16]	697	1		T14	43		T32	40		T43	19
prescale[17]	490	1		T13	2		T30	41		T97	26
prescale[18]	205	1		T14	26		T39	19		T34	19
prescale[19]	749	1		T13	2		T39	64		T31	4
prescale[20]	529	1		T14	4		T36	2		T121	70
prescale[21]	715	1		T30	2		T32	80		T33	2
prescale[22]	501	1		T30	2		T31	51		T97	36
prescale[23]	667	1		T8	58		T13	2		T30	19
prescale[24]	1036	1		T13	2		T14	19		T97	63
prescale[25]	609	1		T16	2		T31	19		T35	26
prescale[26]	644	1		T1	9		T9	9		T14	40
prescale[27]	772	1		T121	43		T105	2		T124	23
prescale[28]	992	1		T30	2		T136	19		T36	55
prescale[29]	695	1		T39	23		T35	70		T136	19
prescale[30]	429	1		T13	2		T32	45		T136	40
prescale[31]	546	1		T8	19		T31	42		T94	9
prescale_0	24609	1		T1	10		T2	17		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	35830	1		T1	9		T2	17		T3	17
auto[1]	11967	1		T1	10		T4	88		T5	81

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	47797	1		T1	19		T2	17		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27848	1		T1	14		T2	12		T3	12
wkup[1]	267	1		T13	30		T30	21		T31	65
wkup[2]	366	1		T16	21		T30	21		T34	21
wkup[3]	78	1		T4	21		T76	21		T170	21
wkup[4]	262	1		T13	26		T14	21		T33	21
wkup[5]	247	1		T14	21		T16	21		T33	21
wkup[6]	271	1		T31	15		T32	21		T121	21
wkup[7]	237	1		T5	21		T140	21		T135	26
wkup[8]	261	1		T32	21		T121	21		T149	21
wkup[9]	224	1		T110	21		T181	21		T161	21
wkup[10]	274	1		T16	8		T37	15		T31	21
wkup[11]	273	1		T4	21		T39	21		T30	21
wkup[12]	379	1		T5	30		T34	21		T35	26
wkup[13]	200	1		T13	6		T14	21		T121	8
wkup[14]	186	1		T185	15		T101	42		T155	21
wkup[15]	395	1		T203	15		T121	51		T114	21
wkup[16]	182	1		T34	21		T43	21		T107	21
wkup[17]	199	1		T32	26		T136	26		T135	21
wkup[18]	189	1		T22	15		T121	35		T135	8
wkup[19]	233	1		T14	30		T45	29		T122	42
wkup[20]	223	1		T13	21		T97	21		T121	26
wkup[21]	305	1		T15	15		T32	21		T44	15
wkup[22]	204	1		T5	21		T8	21		T30	21
wkup[23]	192	1		T32	36		T34	21		T107	30
wkup[24]	304	1		T4	21		T14	21		T30	21
wkup[25]	225	1		T13	21		T16	31		T31	21
wkup[26]	261	1		T13	21		T35	21		T142	21
wkup[27]	233	1		T4	21		T13	8		T30	78
wkup[28]	183	1		T36	21		T117	21		T125	21
wkup[29]	352	1		T5	63		T30	30		T136	26
wkup[30]	327	1		T5	21		T30	30		T142	21
wkup[31]	199	1		T36	47		T99	21		T147	21
wkup[32]	288	1		T14	21		T142	21		T99	42
wkup[33]	209	1		T16	21		T35	21		T121	21
wkup[34]	221	1		T149	30		T107	21		T102	35
wkup[35]	289	1		T14	51		T149	21		T143	21
wkup[36]	306	1		T8	30		T166	15		T164	26
wkup[37]	283	1		T32	30		T36	8		T149	21
wkup[38]	355	1		T31	21		T136	21		T121	21
wkup[39]	140	1		T16	21		T121	21		T134	15
wkup[40]	183	1		T30	21		T36	21		T204	15
wkup[41]	439	1		T5	21		T16	21		T30	60
wkup[42]	244	1		T5	21		T14	26		T136	21
wkup[43]	236	1		T13	21		T32	21		T36	30
wkup[44]	240	1		T97	30		T121	21		T149	21
wkup[45]	457	1		T16	21		T30	21		T34	30
wkup[46]	333	1		T30	34		T121	30		T98	30
wkup[47]	295	1		T4	31		T34	21		T36	15
wkup[48]	133	1		T32	21		T101	8		T152	21
wkup[49]	265	1		T4	21		T16	31		T140	42
wkup[50]	170	1		T100	30		T161	26		T104	21
wkup[51]	352	1		T14	47		T16	26		T30	15
wkup[52]	209	1		T30	21		T121	21		T105	21
wkup[53]	222	1		T13	42		T21	15		T31	21
wkup[54]	269	1		T13	21		T30	30		T34	26
wkup[55]	319	1		T16	21		T31	21		T121	21
wkup[56]	153	1		T30	15		T34	15		T36	15
wkup[57]	206	1		T121	21		T107	42		T175	15
wkup[58]	256	1		T32	29		T121	21		T164	26
wkup[59]	202	1		T43	21		T107	26		T180	15
wkup[60]	330	1		T14	21		T35	21		T98	21
wkup[61]	292	1		T8	30		T32	26		T136	21
wkup[62]	343	1		T13	21		T32	42		T138	15
wkup[63]	280	1		T13	21		T32	21		T121	26
wkup_0	3699	1		T1	5		T2	5		T3	5