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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.66 99.33 93.67 100.00 98.40 99.51 47.07


Total test records in report: 422
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T291 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1963954123 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:12 PM PDT 24 451953782 ps
T23 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2907368059 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:11 PM PDT 24 567872798 ps
T29 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3923801154 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:45 PM PDT 24 496727467 ps
T84 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3661862446 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:36 PM PDT 24 477063304 ps
T292 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3547548830 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 329809947 ps
T293 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3985555436 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:45 PM PDT 24 433167344 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.31769292 Aug 01 06:56:38 PM PDT 24 Aug 01 06:56:39 PM PDT 24 377601468 ps
T24 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.72749134 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:53 PM PDT 24 4045259131 ps
T295 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1689934327 Aug 01 06:57:48 PM PDT 24 Aug 01 06:57:49 PM PDT 24 374929170 ps
T296 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.7711225 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:22 PM PDT 24 775831474 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1149639941 Aug 01 06:56:48 PM PDT 24 Aug 01 06:57:17 PM PDT 24 8750224214 ps
T25 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3302844462 Aug 01 06:57:02 PM PDT 24 Aug 01 06:57:04 PM PDT 24 481541396 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3443301572 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:36 PM PDT 24 470767208 ps
T298 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3503865775 Aug 01 06:56:46 PM PDT 24 Aug 01 06:56:48 PM PDT 24 427629999 ps
T299 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4234551861 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 536599528 ps
T26 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3695553282 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:36 PM PDT 24 8840882271 ps
T300 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1674761876 Aug 01 06:57:47 PM PDT 24 Aug 01 06:57:48 PM PDT 24 372035553 ps
T301 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2753589504 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:48 PM PDT 24 503112009 ps
T302 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1357218219 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:57 PM PDT 24 400041570 ps
T303 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2353665284 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 436010388 ps
T85 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1697593445 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:23 PM PDT 24 1542929191 ps
T304 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2689850729 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:57 PM PDT 24 515904082 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4059475360 Aug 01 06:56:59 PM PDT 24 Aug 01 06:57:03 PM PDT 24 13069863255 ps
T27 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.420438112 Aug 01 06:57:19 PM PDT 24 Aug 01 06:57:26 PM PDT 24 7781301959 ps
T58 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1249617519 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 402003509 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1057678932 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:34 PM PDT 24 554550234 ps
T306 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4207241604 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:35 PM PDT 24 296306234 ps
T208 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.277976519 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:43 PM PDT 24 7707774887 ps
T86 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.239569345 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:39 PM PDT 24 1398460201 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2180804248 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 368639200 ps
T87 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.654599038 Aug 01 06:57:00 PM PDT 24 Aug 01 06:57:03 PM PDT 24 1657193991 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2440548762 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:37 PM PDT 24 659523075 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4000238673 Aug 01 06:57:47 PM PDT 24 Aug 01 06:57:48 PM PDT 24 345897750 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.43162386 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:38 PM PDT 24 387535583 ps
T88 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4061987052 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:35 PM PDT 24 1522969261 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3975264663 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:46 PM PDT 24 756812080 ps
T60 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3210214065 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:35 PM PDT 24 381138441 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1927965540 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:12 PM PDT 24 4766209632 ps
T312 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2168028853 Aug 01 06:56:49 PM PDT 24 Aug 01 06:56:50 PM PDT 24 511216431 ps
T313 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2111453958 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:11 PM PDT 24 4803244354 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3601751508 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:50 PM PDT 24 1160105025 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1747193000 Aug 01 06:56:39 PM PDT 24 Aug 01 06:56:39 PM PDT 24 581007514 ps
T315 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3114736596 Aug 01 06:57:48 PM PDT 24 Aug 01 06:57:49 PM PDT 24 530493141 ps
T316 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1323884300 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 556746886 ps
T62 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4153402350 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:47 PM PDT 24 306660804 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.18896808 Aug 01 06:56:45 PM PDT 24 Aug 01 06:56:46 PM PDT 24 536840748 ps
T89 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3906155268 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:22 PM PDT 24 529059287 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.227752395 Aug 01 06:56:39 PM PDT 24 Aug 01 06:56:40 PM PDT 24 372604953 ps
T319 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.297108887 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:35 PM PDT 24 368329531 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2740308657 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:36 PM PDT 24 380497136 ps
T90 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2024700204 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:46 PM PDT 24 1685778044 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1825575516 Aug 01 06:57:23 PM PDT 24 Aug 01 06:57:24 PM PDT 24 546675281 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3429126148 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:35 PM PDT 24 667161568 ps
T323 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2164677072 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:10 PM PDT 24 978969429 ps
T324 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.815786556 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:45 PM PDT 24 515887686 ps
T91 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.825498837 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:25 PM PDT 24 1804190311 ps
T92 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1137164790 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 484851987 ps
T325 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3660934143 Aug 01 06:57:58 PM PDT 24 Aug 01 06:57:59 PM PDT 24 426852195 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.470615151 Aug 01 06:57:08 PM PDT 24 Aug 01 06:57:09 PM PDT 24 399863771 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3396144168 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:38 PM PDT 24 1259901327 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1948601463 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:27 PM PDT 24 4302216363 ps
T328 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2974299708 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:36 PM PDT 24 349755585 ps
T206 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1861514380 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:47 PM PDT 24 8233050359 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3713194257 Aug 01 06:56:57 PM PDT 24 Aug 01 06:56:59 PM PDT 24 638944723 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385774474 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:37 PM PDT 24 508112033 ps
T330 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3816666283 Aug 01 06:57:36 PM PDT 24 Aug 01 06:57:37 PM PDT 24 492303097 ps
T93 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.656263003 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:23 PM PDT 24 876173072 ps
T63 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2334585026 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:36 PM PDT 24 348659918 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4262987315 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:23 PM PDT 24 1027606582 ps
T332 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1307668129 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:35 PM PDT 24 2324779376 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3118760196 Aug 01 06:57:36 PM PDT 24 Aug 01 06:57:37 PM PDT 24 402368256 ps
T334 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3324836007 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 295619632 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2710074852 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:34 PM PDT 24 484552323 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.34738288 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:25 PM PDT 24 1225385489 ps
T337 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3778428165 Aug 01 06:57:47 PM PDT 24 Aug 01 06:57:48 PM PDT 24 519102196 ps
T338 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1730168727 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:24 PM PDT 24 410932423 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3383178080 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:48 PM PDT 24 273562802 ps
T340 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3793899766 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:57 PM PDT 24 481374126 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4083583799 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:47 PM PDT 24 4677936693 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.468921939 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 437251186 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.203242289 Aug 01 06:56:38 PM PDT 24 Aug 01 06:56:40 PM PDT 24 624500086 ps
T344 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3226378271 Aug 01 06:57:50 PM PDT 24 Aug 01 06:57:53 PM PDT 24 1450828805 ps
T345 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.248785127 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:57 PM PDT 24 439232395 ps
T346 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1840627480 Aug 01 06:57:58 PM PDT 24 Aug 01 06:57:59 PM PDT 24 328551966 ps
T347 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1802910029 Aug 01 06:57:25 PM PDT 24 Aug 01 06:57:26 PM PDT 24 321371387 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2620322550 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:35 PM PDT 24 409773092 ps
T72 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1123279457 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:16 PM PDT 24 12794000366 ps
T349 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1623379221 Aug 01 06:56:38 PM PDT 24 Aug 01 06:56:39 PM PDT 24 278822538 ps
T350 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4170532268 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:34 PM PDT 24 549593863 ps
T351 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2859477141 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 641784444 ps
T73 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.958939772 Aug 01 06:57:37 PM PDT 24 Aug 01 06:57:37 PM PDT 24 553084520 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1200136151 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:35 PM PDT 24 1315212832 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2041034817 Aug 01 06:57:19 PM PDT 24 Aug 01 06:57:22 PM PDT 24 2718121860 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3486475433 Aug 01 06:56:57 PM PDT 24 Aug 01 06:56:58 PM PDT 24 585474568 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1111877727 Aug 01 06:57:19 PM PDT 24 Aug 01 06:57:22 PM PDT 24 4472301354 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3370192542 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:23 PM PDT 24 4559666677 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2736549378 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:48 PM PDT 24 469602226 ps
T357 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1616440431 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:24 PM PDT 24 551892181 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4272054331 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:11 PM PDT 24 489873221 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3016389995 Aug 01 06:56:57 PM PDT 24 Aug 01 06:56:58 PM PDT 24 432486632 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2542291200 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:35 PM PDT 24 672219969 ps
T361 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.453382773 Aug 01 06:57:33 PM PDT 24 Aug 01 06:57:34 PM PDT 24 305494959 ps
T362 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.911851918 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 476964900 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3205865404 Aug 01 06:56:57 PM PDT 24 Aug 01 06:56:59 PM PDT 24 534840454 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2848294419 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:10 PM PDT 24 438181631 ps
T364 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2648649765 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:49 PM PDT 24 4028044974 ps
T365 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.712787422 Aug 01 06:57:37 PM PDT 24 Aug 01 06:57:43 PM PDT 24 4296465312 ps
T366 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1114737601 Aug 01 06:57:55 PM PDT 24 Aug 01 06:57:56 PM PDT 24 461532476 ps
T367 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2263650481 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 493917784 ps
T368 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2972444258 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:57 PM PDT 24 527302954 ps
T209 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2489090028 Aug 01 06:57:36 PM PDT 24 Aug 01 06:57:42 PM PDT 24 8474798496 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2111015991 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:11 PM PDT 24 530512902 ps
T370 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3960525685 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 380252316 ps
T371 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4183248075 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 371352576 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.523250265 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:12 PM PDT 24 397521753 ps
T373 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3304905207 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:49 PM PDT 24 2387251569 ps
T374 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1346377833 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 493740747 ps
T207 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2425388509 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:23 PM PDT 24 4185109690 ps
T375 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3496582627 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:22 PM PDT 24 600374765 ps
T376 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2238579483 Aug 01 06:57:58 PM PDT 24 Aug 01 06:57:59 PM PDT 24 294998593 ps
T377 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4224118919 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 376273718 ps
T66 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3871026484 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:22 PM PDT 24 286889149 ps
T378 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.699068582 Aug 01 06:57:58 PM PDT 24 Aug 01 06:57:59 PM PDT 24 350888853 ps
T379 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1264937096 Aug 01 06:56:39 PM PDT 24 Aug 01 06:56:40 PM PDT 24 407453636 ps
T380 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3297198471 Aug 01 06:56:49 PM PDT 24 Aug 01 06:56:51 PM PDT 24 819989554 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2240595238 Aug 01 06:56:58 PM PDT 24 Aug 01 06:57:01 PM PDT 24 522703513 ps
T382 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1405160692 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:38 PM PDT 24 1093662711 ps
T210 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3017594111 Aug 01 06:56:38 PM PDT 24 Aug 01 06:56:40 PM PDT 24 4281178576 ps
T383 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1402444582 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:45 PM PDT 24 395018007 ps
T384 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1197107664 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:11 PM PDT 24 465853578 ps
T385 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.373294397 Aug 01 06:57:44 PM PDT 24 Aug 01 06:57:45 PM PDT 24 355384337 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1255362161 Aug 01 06:56:58 PM PDT 24 Aug 01 06:56:59 PM PDT 24 269568047 ps
T67 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.420503863 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:45 PM PDT 24 387882627 ps
T387 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3530410482 Aug 01 06:57:48 PM PDT 24 Aug 01 06:57:49 PM PDT 24 573322441 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2357749647 Aug 01 06:57:00 PM PDT 24 Aug 01 06:57:00 PM PDT 24 374263165 ps
T389 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.520417926 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:23 PM PDT 24 324197583 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3551026235 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:11 PM PDT 24 966031898 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.720669837 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:48 PM PDT 24 537288246 ps
T391 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4219148355 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:36 PM PDT 24 468807075 ps
T392 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3228891655 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:36 PM PDT 24 308162359 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1519612397 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:52 PM PDT 24 4303913203 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.95644795 Aug 01 06:57:22 PM PDT 24 Aug 01 06:57:24 PM PDT 24 313443843 ps
T395 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3595667193 Aug 01 06:57:20 PM PDT 24 Aug 01 06:57:21 PM PDT 24 509018614 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.631801375 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:54 PM PDT 24 2883072696 ps
T397 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.337543262 Aug 01 06:57:35 PM PDT 24 Aug 01 06:57:37 PM PDT 24 538375028 ps
T398 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.535476877 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:47 PM PDT 24 534788285 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4196892830 Aug 01 06:57:10 PM PDT 24 Aug 01 06:57:12 PM PDT 24 390529669 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1737426843 Aug 01 06:56:47 PM PDT 24 Aug 01 06:56:48 PM PDT 24 476907570 ps
T401 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.524233391 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:40 PM PDT 24 1371149076 ps
T402 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.263806077 Aug 01 06:57:48 PM PDT 24 Aug 01 06:57:50 PM PDT 24 463531842 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2614465841 Aug 01 06:56:48 PM PDT 24 Aug 01 06:56:52 PM PDT 24 2083915525 ps
T404 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1971223282 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:47 PM PDT 24 314505333 ps
T405 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2893889154 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:47 PM PDT 24 406054764 ps
T83 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1068454773 Aug 01 06:56:57 PM PDT 24 Aug 01 06:57:01 PM PDT 24 7146410773 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1519067089 Aug 01 06:57:46 PM PDT 24 Aug 01 06:57:47 PM PDT 24 431014169 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.213330919 Aug 01 06:56:57 PM PDT 24 Aug 01 06:56:58 PM PDT 24 275789504 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3710094253 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:22 PM PDT 24 313587631 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4086659604 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:37 PM PDT 24 488646152 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3214330309 Aug 01 06:56:36 PM PDT 24 Aug 01 06:56:46 PM PDT 24 13186584693 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1994646577 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:24 PM PDT 24 2258427117 ps
T412 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3968195 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:59 PM PDT 24 347425777 ps
T413 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.639561355 Aug 01 06:57:55 PM PDT 24 Aug 01 06:57:57 PM PDT 24 497659245 ps
T414 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3023519473 Aug 01 06:57:19 PM PDT 24 Aug 01 06:57:22 PM PDT 24 451508323 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3712592233 Aug 01 06:57:09 PM PDT 24 Aug 01 06:57:11 PM PDT 24 2506240179 ps
T416 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3660308150 Aug 01 06:56:59 PM PDT 24 Aug 01 06:57:01 PM PDT 24 4202738142 ps
T417 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3941949865 Aug 01 06:56:37 PM PDT 24 Aug 01 06:56:40 PM PDT 24 4447374318 ps
T69 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.833866725 Aug 01 06:57:45 PM PDT 24 Aug 01 06:57:46 PM PDT 24 419665566 ps
T418 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1887046333 Aug 01 06:57:34 PM PDT 24 Aug 01 06:57:46 PM PDT 24 7844021626 ps
T419 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4170450543 Aug 01 06:57:21 PM PDT 24 Aug 01 06:57:23 PM PDT 24 449764008 ps
T420 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2964085165 Aug 01 06:57:23 PM PDT 24 Aug 01 06:57:24 PM PDT 24 289855247 ps
T421 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.152678092 Aug 01 06:56:46 PM PDT 24 Aug 01 06:56:48 PM PDT 24 1290122831 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.39059918 Aug 01 06:56:58 PM PDT 24 Aug 01 06:56:59 PM PDT 24 545246490 ps

Test location /workspace/coverage/default/6.aon_timer_stress_all.1270833412
Short name T4
Test name
Test status
Simulation time 3644427783 ps
CPU time 2.09 seconds
Started Aug 01 06:51:13 PM PDT 24
Finished Aug 01 06:51:16 PM PDT 24
Peak memory 198240 kb
Host smart-a083a463-791e-4ab5-a34f-a516c313d249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270833412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1270833412
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.410368762
Short name T14
Test name
Test status
Simulation time 74254584872 ps
CPU time 521.86 seconds
Started Aug 01 06:51:34 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 203696 kb
Host smart-afa1a960-5b99-4459-a5aa-f60ffd3c5976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410368762 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.410368762
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.72749134
Short name T24
Test name
Test status
Simulation time 4045259131 ps
CPU time 5.75 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:53 PM PDT 24
Peak memory 197860 kb
Host smart-9d0f0d09-052c-409f-b2a9-da62c03c7fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72749134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_i
ntg_err.72749134
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2256279555
Short name T121
Test name
Test status
Simulation time 778943263850 ps
CPU time 467.68 seconds
Started Aug 01 06:51:27 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 206712 kb
Host smart-1f022d03-e4f5-4f19-8f95-c320bcaadca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256279555 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2256279555
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2165250606
Short name T45
Test name
Test status
Simulation time 71815654961 ps
CPU time 356.47 seconds
Started Aug 01 06:51:18 PM PDT 24
Finished Aug 01 06:57:15 PM PDT 24
Peak memory 213944 kb
Host smart-6dc2ee23-30bd-48f9-ad80-7d1608b141ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165250606 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2165250606
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2197610242
Short name T122
Test name
Test status
Simulation time 62461456245 ps
CPU time 661.83 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 07:02:45 PM PDT 24
Peak memory 204728 kb
Host smart-f3b03150-20c2-4a41-b61a-91fc44428f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197610242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2197610242
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1052811795
Short name T107
Test name
Test status
Simulation time 289749862320 ps
CPU time 513.89 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 07:00:18 PM PDT 24
Peak memory 214900 kb
Host smart-d09bb9d6-8c11-44f7-b68d-54b1f6c4b849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052811795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1052811795
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3595157408
Short name T104
Test name
Test status
Simulation time 353170898749 ps
CPU time 731.56 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 07:03:14 PM PDT 24
Peak memory 206968 kb
Host smart-b6ab202c-2bc2-4687-8d75-17a7b1d300f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595157408 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3595157408
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.335412494
Short name T153
Test name
Test status
Simulation time 220290141724 ps
CPU time 392.14 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:58:02 PM PDT 24
Peak memory 206704 kb
Host smart-e9be3fc6-4ce5-4b89-b61a-b113263e50a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335412494 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.335412494
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1658108374
Short name T5
Test name
Test status
Simulation time 19787511314 ps
CPU time 5.77 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 198356 kb
Host smart-3f83feac-152b-4e67-8858-f1f0ca7b3bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658108374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1658108374
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3998718642
Short name T137
Test name
Test status
Simulation time 281653559306 ps
CPU time 710.55 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 07:03:35 PM PDT 24
Peak memory 214792 kb
Host smart-64a03161-c820-401e-b9a0-1c057bdd900b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998718642 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3998718642
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.697545989
Short name T19
Test name
Test status
Simulation time 4215748121 ps
CPU time 6.19 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:14 PM PDT 24
Peak memory 215456 kb
Host smart-72e63523-1110-4626-9484-c8cbcf0460ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697545989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.697545989
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3750642869
Short name T139
Test name
Test status
Simulation time 429895166880 ps
CPU time 881.53 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 07:06:31 PM PDT 24
Peak memory 209100 kb
Host smart-e85cf477-9571-48fb-8656-0baabf115112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750642869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3750642869
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1622921898
Short name T112
Test name
Test status
Simulation time 524513206821 ps
CPU time 825.92 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 07:05:14 PM PDT 24
Peak memory 192880 kb
Host smart-ec651ff0-25db-464f-af15-19b70c9bb9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622921898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1622921898
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.270597874
Short name T46
Test name
Test status
Simulation time 145359438474 ps
CPU time 187.32 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:54:58 PM PDT 24
Peak memory 192536 kb
Host smart-d93f4e76-c3c0-4bc5-9a15-06153504e9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270597874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.270597874
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1679655728
Short name T102
Test name
Test status
Simulation time 70600358166 ps
CPU time 284.87 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:55:52 PM PDT 24
Peak memory 206736 kb
Host smart-b8082114-1334-429e-88cf-6c7eeaf19863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679655728 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1679655728
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2715267045
Short name T131
Test name
Test status
Simulation time 39439867970 ps
CPU time 13.77 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:17 PM PDT 24
Peak memory 191804 kb
Host smart-0fe41016-39dc-425b-82de-d9ee96aa95b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715267045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2715267045
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.262958633
Short name T170
Test name
Test status
Simulation time 38360111178 ps
CPU time 217.39 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 06:55:23 PM PDT 24
Peak memory 198676 kb
Host smart-75ddb7fe-c600-48ba-a04b-bcc24e0e89f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262958633 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.262958633
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.97827344
Short name T13
Test name
Test status
Simulation time 80715105195 ps
CPU time 509.64 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 07:00:01 PM PDT 24
Peak memory 213896 kb
Host smart-f8bcb1d2-527d-490b-aaaf-b242ac690eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97827344 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.97827344
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2881804684
Short name T149
Test name
Test status
Simulation time 126058539131 ps
CPU time 170.58 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:54:35 PM PDT 24
Peak memory 198216 kb
Host smart-97a2bb2f-43ac-4c4c-9452-99b946e0e408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881804684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2881804684
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1509798822
Short name T177
Test name
Test status
Simulation time 319275689966 ps
CPU time 613.32 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 07:01:45 PM PDT 24
Peak memory 205092 kb
Host smart-8192b12e-527f-4392-91d9-6b86a6f19829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509798822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1509798822
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1532200935
Short name T16
Test name
Test status
Simulation time 159421447605 ps
CPU time 298.99 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:56:08 PM PDT 24
Peak memory 209548 kb
Host smart-ef5eb80f-8072-440a-af64-6ac799475d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532200935 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1532200935
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3912315367
Short name T30
Test name
Test status
Simulation time 92612676719 ps
CPU time 494.33 seconds
Started Aug 01 06:51:32 PM PDT 24
Finished Aug 01 06:59:47 PM PDT 24
Peak memory 213920 kb
Host smart-d09713dc-c171-4085-838d-d2aef56ea04b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912315367 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3912315367
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3491968521
Short name T99
Test name
Test status
Simulation time 133802491915 ps
CPU time 182.44 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:54:48 PM PDT 24
Peak memory 207780 kb
Host smart-fe739e3c-6728-47df-a844-07d698cc88da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491968521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3491968521
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.641693251
Short name T119
Test name
Test status
Simulation time 42635189599 ps
CPU time 59.94 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 06:52:36 PM PDT 24
Peak memory 198196 kb
Host smart-ab42a155-909f-4931-a53e-e546a1872917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641693251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.641693251
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4116173237
Short name T150
Test name
Test status
Simulation time 58205608239 ps
CPU time 22.27 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:52:13 PM PDT 24
Peak memory 192488 kb
Host smart-8f382add-a738-4e52-a9cb-d47ad9366f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116173237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4116173237
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.823004488
Short name T55
Test name
Test status
Simulation time 127007099002 ps
CPU time 215.71 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:55:01 PM PDT 24
Peak memory 200536 kb
Host smart-d08081b0-d6f2-4a74-bf51-62960d04d218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823004488 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.823004488
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3143661835
Short name T110
Test name
Test status
Simulation time 215298631880 ps
CPU time 219.33 seconds
Started Aug 01 06:51:14 PM PDT 24
Finished Aug 01 06:54:53 PM PDT 24
Peak memory 192876 kb
Host smart-4aa4c17c-4234-4134-9eb1-3013c1378f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143661835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3143661835
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.614928907
Short name T164
Test name
Test status
Simulation time 186881368710 ps
CPU time 27.99 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:52:10 PM PDT 24
Peak memory 192444 kb
Host smart-77007c94-9667-43c3-860d-8c77e7d13a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614928907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.614928907
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3161169627
Short name T113
Test name
Test status
Simulation time 27609839645 ps
CPU time 283.27 seconds
Started Aug 01 06:51:15 PM PDT 24
Finished Aug 01 06:55:59 PM PDT 24
Peak memory 206780 kb
Host smart-e6c5e392-0677-4d3b-8646-421c1b372d7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161169627 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3161169627
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4085726797
Short name T161
Test name
Test status
Simulation time 14515217368 ps
CPU time 112.08 seconds
Started Aug 01 06:51:16 PM PDT 24
Finished Aug 01 06:53:08 PM PDT 24
Peak memory 213884 kb
Host smart-56f515d7-8fd0-49a5-a042-daf023cff7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085726797 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4085726797
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1243312099
Short name T120
Test name
Test status
Simulation time 55547633112 ps
CPU time 43.93 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:52:12 PM PDT 24
Peak memory 191860 kb
Host smart-86393a67-16d2-4e72-b1b6-1281a693f244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243312099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1243312099
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1507057215
Short name T147
Test name
Test status
Simulation time 146414983765 ps
CPU time 52.84 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:52:37 PM PDT 24
Peak memory 198196 kb
Host smart-71e41fed-27f1-4d2f-892d-900d3d61944b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507057215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1507057215
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1914052748
Short name T117
Test name
Test status
Simulation time 133991317136 ps
CPU time 200.04 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:54:24 PM PDT 24
Peak memory 193004 kb
Host smart-e4e2d60a-fd53-4515-a096-48fd7e886449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914052748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1914052748
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.996964719
Short name T142
Test name
Test status
Simulation time 156493040226 ps
CPU time 56.67 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:52:40 PM PDT 24
Peak memory 184292 kb
Host smart-e6e08056-b010-4b4b-b40f-331f452918dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996964719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.996964719
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3516120009
Short name T114
Test name
Test status
Simulation time 532539957908 ps
CPU time 53.85 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 198172 kb
Host smart-a77c0e2b-9d72-4345-ac5a-30f9f41de061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516120009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3516120009
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4064660158
Short name T152
Test name
Test status
Simulation time 160926436153 ps
CPU time 200.4 seconds
Started Aug 01 06:51:16 PM PDT 24
Finished Aug 01 06:54:37 PM PDT 24
Peak memory 192880 kb
Host smart-9cfb07b1-4c1e-4f5b-a2bd-15da77e79e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064660158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4064660158
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.4292393973
Short name T135
Test name
Test status
Simulation time 36686852136 ps
CPU time 297.81 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:56:33 PM PDT 24
Peak memory 198452 kb
Host smart-cbd7b7a5-5a87-4e80-9f65-91b26d285462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292393973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.4292393973
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3689984661
Short name T109
Test name
Test status
Simulation time 130049924264 ps
CPU time 497.96 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 211728 kb
Host smart-966e186e-a525-455b-84c2-aabcec0eb1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689984661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3689984661
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.798748472
Short name T111
Test name
Test status
Simulation time 3703124840 ps
CPU time 6.41 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 06:51:55 PM PDT 24
Peak memory 198188 kb
Host smart-26461492-ca21-4be3-a8b2-55453f0db3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798748472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.798748472
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2197973679
Short name T156
Test name
Test status
Simulation time 58647649247 ps
CPU time 128.09 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:53:55 PM PDT 24
Peak memory 206724 kb
Host smart-fb11d122-2168-4a7c-bddb-f5f29201fe0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197973679 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2197973679
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1585074862
Short name T32
Test name
Test status
Simulation time 49929403387 ps
CPU time 88.24 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:52:54 PM PDT 24
Peak memory 198472 kb
Host smart-6921727a-518e-468b-bcb7-4970fad69472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585074862 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1585074862
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1709227834
Short name T124
Test name
Test status
Simulation time 40270624406 ps
CPU time 26.99 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:31 PM PDT 24
Peak memory 191940 kb
Host smart-4df60a7e-5c4d-4872-b78c-a2babb7182be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709227834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1709227834
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.557891400
Short name T159
Test name
Test status
Simulation time 27949082149 ps
CPU time 242.54 seconds
Started Aug 01 06:51:09 PM PDT 24
Finished Aug 01 06:55:11 PM PDT 24
Peak memory 206784 kb
Host smart-7ddf1398-f8a7-4df8-94cc-4ba2947464bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557891400 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.557891400
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.4127545616
Short name T8
Test name
Test status
Simulation time 149786950163 ps
CPU time 109.21 seconds
Started Aug 01 06:51:22 PM PDT 24
Finished Aug 01 06:53:12 PM PDT 24
Peak memory 198276 kb
Host smart-b3db7e74-2bff-44c8-9094-e00dceb36d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127545616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.4127545616
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.373701375
Short name T155
Test name
Test status
Simulation time 71461613193 ps
CPU time 578.07 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 07:01:24 PM PDT 24
Peak memory 203316 kb
Host smart-1baa4d1c-f7e5-45a3-8e87-9ffcfa73c327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373701375 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.373701375
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1808940825
Short name T179
Test name
Test status
Simulation time 97367508050 ps
CPU time 405.41 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 210684 kb
Host smart-535f59df-1fc6-4c1f-b7c2-2d4586892cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808940825 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1808940825
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1633077983
Short name T78
Test name
Test status
Simulation time 136749811121 ps
CPU time 107.4 seconds
Started Aug 01 06:51:14 PM PDT 24
Finished Aug 01 06:53:01 PM PDT 24
Peak memory 192964 kb
Host smart-f365ed87-57b5-4e96-81b1-b0168e9c5fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633077983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1633077983
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3758146696
Short name T34
Test name
Test status
Simulation time 117544218232 ps
CPU time 240.65 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:55:08 PM PDT 24
Peak memory 212844 kb
Host smart-0770bd21-d89d-41f0-911f-3773be3ec062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758146696 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3758146696
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4059475360
Short name T57
Test name
Test status
Simulation time 13069863255 ps
CPU time 3.79 seconds
Started Aug 01 06:56:59 PM PDT 24
Finished Aug 01 06:57:03 PM PDT 24
Peak memory 195740 kb
Host smart-c79e4d0e-ccf5-41bc-9678-74a999e3d6f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059475360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4059475360
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3640663411
Short name T118
Test name
Test status
Simulation time 293256582934 ps
CPU time 119.55 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:53:35 PM PDT 24
Peak memory 198232 kb
Host smart-db119ca5-cc30-4ee4-adf4-88bb3ffbe3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640663411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3640663411
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2365912003
Short name T160
Test name
Test status
Simulation time 81349928209 ps
CPU time 20.01 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:51:50 PM PDT 24
Peak memory 198228 kb
Host smart-e381a52f-5bd8-4c52-a8c6-691d914ac1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365912003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2365912003
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2969156285
Short name T145
Test name
Test status
Simulation time 208508485804 ps
CPU time 271.66 seconds
Started Aug 01 06:51:38 PM PDT 24
Finished Aug 01 06:56:10 PM PDT 24
Peak memory 192468 kb
Host smart-1cb726b8-8466-453e-b5a6-617e949e1db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969156285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2969156285
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1831619848
Short name T35
Test name
Test status
Simulation time 155451606094 ps
CPU time 541.03 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 07:00:37 PM PDT 24
Peak memory 212432 kb
Host smart-84e36ea7-f4cf-4bde-8d47-c46773a44cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831619848 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1831619848
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2415430318
Short name T144
Test name
Test status
Simulation time 46788996865 ps
CPU time 18.95 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 06:51:55 PM PDT 24
Peak memory 198276 kb
Host smart-f766d115-48c1-44e1-bb41-335a26212f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415430318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2415430318
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1952971482
Short name T125
Test name
Test status
Simulation time 279446356410 ps
CPU time 80.89 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:53:01 PM PDT 24
Peak memory 191900 kb
Host smart-c450d014-db88-4a24-aaef-42562ec700ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952971482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1952971482
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3906155268
Short name T89
Test name
Test status
Simulation time 529059287 ps
CPU time 1.34 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 191956 kb
Host smart-de7163a4-2d52-4c1b-8e3a-3ff92eb0e995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906155268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3906155268
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1626711064
Short name T49
Test name
Test status
Simulation time 53603870986 ps
CPU time 19.68 seconds
Started Aug 01 06:51:21 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 198220 kb
Host smart-d2ab5492-6959-42f9-9b6c-0b48864c656f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626711064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1626711064
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1593573303
Short name T140
Test name
Test status
Simulation time 151569472171 ps
CPU time 108.65 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:53:12 PM PDT 24
Peak memory 192984 kb
Host smart-4b9e3dbd-f27b-442d-b21d-d2c0426231bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593573303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1593573303
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.334715015
Short name T168
Test name
Test status
Simulation time 272596295517 ps
CPU time 93.72 seconds
Started Aug 01 06:51:27 PM PDT 24
Finished Aug 01 06:53:02 PM PDT 24
Peak memory 192964 kb
Host smart-3509e46a-ab5b-4600-b119-6d37409bd66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334715015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.334715015
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1534142689
Short name T47
Test name
Test status
Simulation time 291157372214 ps
CPU time 417.8 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:58:40 PM PDT 24
Peak memory 192936 kb
Host smart-0e9e2480-046e-4742-ad26-0c94ad049f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534142689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1534142689
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.823456518
Short name T98
Test name
Test status
Simulation time 85841334535 ps
CPU time 314.64 seconds
Started Aug 01 06:51:34 PM PDT 24
Finished Aug 01 06:56:49 PM PDT 24
Peak memory 213904 kb
Host smart-3fdd9db6-8c5c-4c3e-bdaa-a56c39117aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823456518 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.823456518
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1400211866
Short name T128
Test name
Test status
Simulation time 48022581045 ps
CPU time 104.97 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:53:05 PM PDT 24
Peak memory 213884 kb
Host smart-81a3a9b4-fdb8-47da-939e-f661e11cb3f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400211866 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1400211866
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3008062284
Short name T31
Test name
Test status
Simulation time 39999280783 ps
CPU time 203.71 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:54:31 PM PDT 24
Peak memory 198580 kb
Host smart-73b457b9-d196-4dd8-bbf0-bee67337e5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008062284 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3008062284
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2377026962
Short name T151
Test name
Test status
Simulation time 404166367082 ps
CPU time 33.6 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:53 PM PDT 24
Peak memory 198212 kb
Host smart-c367b0f5-a2e6-47f7-994b-cce69aee8f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377026962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2377026962
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1486784179
Short name T136
Test name
Test status
Simulation time 359709408662 ps
CPU time 540.83 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 07:00:18 PM PDT 24
Peak memory 198200 kb
Host smart-81be7f8b-187c-4135-b75e-96522921684f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486784179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1486784179
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3180792820
Short name T100
Test name
Test status
Simulation time 90320319005 ps
CPU time 714.83 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 07:03:35 PM PDT 24
Peak memory 214884 kb
Host smart-4bc7eaaa-dd1b-4fbc-bce4-633558d0e1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180792820 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3180792820
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.668137354
Short name T132
Test name
Test status
Simulation time 423693196 ps
CPU time 1.17 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 196664 kb
Host smart-e1a70f7b-2d15-406b-a0ed-77fd760da6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668137354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.668137354
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1551441683
Short name T163
Test name
Test status
Simulation time 533854921 ps
CPU time 1.36 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 196680 kb
Host smart-567b9de7-38da-44c5-9b05-8ccc995befd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551441683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1551441683
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3117908780
Short name T143
Test name
Test status
Simulation time 43587220648 ps
CPU time 12.57 seconds
Started Aug 01 06:51:26 PM PDT 24
Finished Aug 01 06:51:39 PM PDT 24
Peak memory 191852 kb
Host smart-386ec20c-b764-45f6-bf20-5dc824c9a59a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117908780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3117908780
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4137621509
Short name T148
Test name
Test status
Simulation time 101702309724 ps
CPU time 69.29 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:52:40 PM PDT 24
Peak memory 184384 kb
Host smart-79a2d618-cb21-4a7f-9ec5-e9f47f549266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137621509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4137621509
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.33481969
Short name T36
Test name
Test status
Simulation time 18094984441 ps
CPU time 144.28 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:54:00 PM PDT 24
Peak memory 206668 kb
Host smart-e549ba45-7fb4-4cc5-86c3-b1825488d63f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33481969 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.33481969
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4009064078
Short name T126
Test name
Test status
Simulation time 78168795780 ps
CPU time 57 seconds
Started Aug 01 06:51:48 PM PDT 24
Finished Aug 01 06:52:46 PM PDT 24
Peak memory 191900 kb
Host smart-205d250f-5f05-46f2-b1bf-65cbe677eda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009064078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4009064078
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1997898130
Short name T22
Test name
Test status
Simulation time 449287082 ps
CPU time 0.73 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:51:45 PM PDT 24
Peak memory 196748 kb
Host smart-ea5a12c9-33ef-406a-925e-6f14b1379725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997898130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1997898130
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1965196014
Short name T157
Test name
Test status
Simulation time 488657461694 ps
CPU time 117.23 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:53:05 PM PDT 24
Peak memory 192996 kb
Host smart-f489f504-1d98-4ed2-bfc9-d75fd18d8492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965196014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1965196014
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1446168851
Short name T134
Test name
Test status
Simulation time 507692690 ps
CPU time 0.81 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 196676 kb
Host smart-fcddefa2-47f4-4661-9053-d4fd06c1f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446168851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1446168851
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.837594271
Short name T130
Test name
Test status
Simulation time 369251251 ps
CPU time 1.13 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:51:10 PM PDT 24
Peak memory 196752 kb
Host smart-317481e2-3630-4c1a-a1f4-94b6c65a5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837594271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.837594271
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.163327500
Short name T146
Test name
Test status
Simulation time 590243575 ps
CPU time 0.81 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:51:51 PM PDT 24
Peak memory 196728 kb
Host smart-9b29c2b0-9c17-4bfe-a44c-738e22f1222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163327500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.163327500
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3302034145
Short name T181
Test name
Test status
Simulation time 55043160603 ps
CPU time 404.25 seconds
Started Aug 01 06:51:26 PM PDT 24
Finished Aug 01 06:58:10 PM PDT 24
Peak memory 208780 kb
Host smart-6cff3a8b-808b-43f3-b544-c0956f656e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302034145 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3302034145
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2291980712
Short name T133
Test name
Test status
Simulation time 59628185088 ps
CPU time 39.6 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:52:15 PM PDT 24
Peak memory 191904 kb
Host smart-82131b08-dd95-4627-b6dd-4964a324be87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291980712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2291980712
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1778774676
Short name T115
Test name
Test status
Simulation time 396252101 ps
CPU time 1.27 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 196712 kb
Host smart-239bb59c-530c-4310-8b6f-6800e0892143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778774676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1778774676
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3461876777
Short name T39
Test name
Test status
Simulation time 278788648067 ps
CPU time 390.13 seconds
Started Aug 01 06:51:18 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 192956 kb
Host smart-09c13aaf-ac61-4cf1-9390-bcccd3add563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461876777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3461876777
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.365342416
Short name T82
Test name
Test status
Simulation time 369019651 ps
CPU time 0.74 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:51:31 PM PDT 24
Peak memory 196660 kb
Host smart-381fd49f-6097-4faa-a0d1-dd8eb4c50900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365342416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.365342416
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.786226197
Short name T44
Test name
Test status
Simulation time 570469763 ps
CPU time 0.77 seconds
Started Aug 01 06:51:21 PM PDT 24
Finished Aug 01 06:51:22 PM PDT 24
Peak memory 196576 kb
Host smart-dd09a556-6e61-4c7b-84f4-f6cc021219a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786226197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.786226197
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2134030736
Short name T138
Test name
Test status
Simulation time 574035535 ps
CPU time 0.73 seconds
Started Aug 01 06:51:09 PM PDT 24
Finished Aug 01 06:51:09 PM PDT 24
Peak memory 196640 kb
Host smart-e05c08cb-ede7-49f3-bb7f-e98c345f0d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134030736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2134030736
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3764582430
Short name T165
Test name
Test status
Simulation time 95561570349 ps
CPU time 211.28 seconds
Started Aug 01 06:51:11 PM PDT 24
Finished Aug 01 06:54:42 PM PDT 24
Peak memory 213992 kb
Host smart-f376ba42-7bbb-4f64-a071-eb3e4d4f8c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764582430 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3764582430
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.118668435
Short name T33
Test name
Test status
Simulation time 22505064650 ps
CPU time 233.83 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:55:41 PM PDT 24
Peak memory 206740 kb
Host smart-45e63c4d-d04c-428c-a5ab-e12dd30d74b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118668435 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.118668435
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.118446816
Short name T127
Test name
Test status
Simulation time 521227198 ps
CPU time 1.37 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:19 PM PDT 24
Peak memory 196656 kb
Host smart-50855fbc-ff3c-48d9-91b8-2e71d8b1f0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118446816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.118446816
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4228912676
Short name T169
Test name
Test status
Simulation time 299743813822 ps
CPU time 209.94 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:54:53 PM PDT 24
Peak memory 198276 kb
Host smart-5a9a15d4-afc3-49c8-a811-19012c3e94e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228912676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4228912676
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1000436439
Short name T21
Test name
Test status
Simulation time 552611684 ps
CPU time 1.07 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:51:26 PM PDT 24
Peak memory 196728 kb
Host smart-1c5ddcdc-d0c1-4536-87c9-139deecfdd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000436439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1000436439
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2882932801
Short name T191
Test name
Test status
Simulation time 56058392810 ps
CPU time 442.27 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:58:58 PM PDT 24
Peak memory 209176 kb
Host smart-50494540-84af-4e49-ba19-68f3f52a696c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882932801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2882932801
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3389433504
Short name T101
Test name
Test status
Simulation time 62290126609 ps
CPU time 606.92 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 07:01:32 PM PDT 24
Peak memory 211232 kb
Host smart-9656191c-b8db-4777-bec9-d95646720ac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389433504 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3389433504
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1631560997
Short name T48
Test name
Test status
Simulation time 445070864 ps
CPU time 0.77 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 196632 kb
Host smart-ed7b6ebe-acdd-4924-afa3-33ea22be1b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631560997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1631560997
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3756145626
Short name T76
Test name
Test status
Simulation time 74900118815 ps
CPU time 475.18 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:59:35 PM PDT 24
Peak memory 209564 kb
Host smart-0c9d1aad-4593-4aa5-b102-8548810a82b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756145626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3756145626
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.234992878
Short name T123
Test name
Test status
Simulation time 525172239 ps
CPU time 0.75 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 06:51:37 PM PDT 24
Peak memory 196876 kb
Host smart-fe5b0ed8-dfb8-4407-a91e-cb283472174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234992878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.234992878
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4060763545
Short name T43
Test name
Test status
Simulation time 153922850049 ps
CPU time 219.53 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:55:24 PM PDT 24
Peak memory 198240 kb
Host smart-11793ff5-6469-4eb8-97cc-6c7815e0ede4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060763545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4060763545
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.935028514
Short name T183
Test name
Test status
Simulation time 76452235770 ps
CPU time 116.28 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:53:04 PM PDT 24
Peak memory 191872 kb
Host smart-40f773b5-3427-48c7-9b13-6939935e1f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935028514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.935028514
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3589979942
Short name T108
Test name
Test status
Simulation time 47022387556 ps
CPU time 87.35 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:52:29 PM PDT 24
Peak memory 198544 kb
Host smart-a6c36a6f-769a-42e5-9dea-f531d578e51b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589979942 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3589979942
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2702353761
Short name T178
Test name
Test status
Simulation time 415419962855 ps
CPU time 142.86 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:53:46 PM PDT 24
Peak memory 191912 kb
Host smart-134d85f0-d64f-45db-acd6-7e1fc916b4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702353761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2702353761
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2312499111
Short name T129
Test name
Test status
Simulation time 102498523602 ps
CPU time 187 seconds
Started Aug 01 06:51:37 PM PDT 24
Finished Aug 01 06:54:45 PM PDT 24
Peak memory 207804 kb
Host smart-7cbdeb5c-7fed-4b23-82ab-e6140f2500ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312499111 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2312499111
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3872709877
Short name T167
Test name
Test status
Simulation time 444719717 ps
CPU time 0.68 seconds
Started Aug 01 06:51:37 PM PDT 24
Finished Aug 01 06:51:38 PM PDT 24
Peak memory 196760 kb
Host smart-fd8760d7-5f32-43da-bac3-2260a221cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872709877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3872709877
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1254162366
Short name T116
Test name
Test status
Simulation time 553810471 ps
CPU time 0.78 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:43 PM PDT 24
Peak memory 196680 kb
Host smart-cafe96cc-957d-4d54-ba4e-38336743cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254162366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1254162366
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1586743421
Short name T158
Test name
Test status
Simulation time 467316942 ps
CPU time 1.14 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 196724 kb
Host smart-279b4db0-cbf1-49d1-98fe-75dad20b8376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586743421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1586743421
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.420438112
Short name T27
Test name
Test status
Simulation time 7781301959 ps
CPU time 6.81 seconds
Started Aug 01 06:57:19 PM PDT 24
Finished Aug 01 06:57:26 PM PDT 24
Peak memory 198284 kb
Host smart-e97b7e03-6fac-4b91-8e42-05a79c1dc964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420438112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.420438112
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1793446125
Short name T201
Test name
Test status
Simulation time 462550811 ps
CPU time 0.9 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:51:24 PM PDT 24
Peak memory 196616 kb
Host smart-e0f994d8-ed78-4cdb-8376-f27717b35591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793446125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1793446125
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2815890233
Short name T105
Test name
Test status
Simulation time 24406419680 ps
CPU time 178.04 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:54:30 PM PDT 24
Peak memory 198400 kb
Host smart-e2dd378a-e7fe-45c5-81fa-ba06b31d30b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815890233 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2815890233
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2990153454
Short name T192
Test name
Test status
Simulation time 464771688 ps
CPU time 1.16 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 196596 kb
Host smart-e82b3d1b-3ed3-4a8c-b733-b3ab888a0157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990153454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2990153454
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2022114301
Short name T141
Test name
Test status
Simulation time 130012884158 ps
CPU time 38.82 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:52:21 PM PDT 24
Peak memory 191912 kb
Host smart-151bae72-60de-474b-a6ef-4e4f8acf7ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022114301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2022114301
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.435560872
Short name T194
Test name
Test status
Simulation time 177249869379 ps
CPU time 70.67 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:53:01 PM PDT 24
Peak memory 191884 kb
Host smart-4ec2b81b-43dd-4c43-876a-339ecdc2cf88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435560872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.435560872
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.38968302
Short name T173
Test name
Test status
Simulation time 23833074964 ps
CPU time 195.89 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 206692 kb
Host smart-0dfd224f-814b-458d-b7d7-b854880dc5fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968302 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.38968302
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2827916606
Short name T196
Test name
Test status
Simulation time 427026998 ps
CPU time 1.24 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:51:37 PM PDT 24
Peak memory 196724 kb
Host smart-e40a8fc0-e609-49e9-bbdc-f0f09aa08bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827916606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2827916606
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1842954863
Short name T15
Test name
Test status
Simulation time 440103345 ps
CPU time 1.12 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:22 PM PDT 24
Peak memory 196644 kb
Host smart-3b264757-7c16-4566-bed6-c60f800a8794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842954863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1842954863
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3315280247
Short name T182
Test name
Test status
Simulation time 498945936 ps
CPU time 0.69 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 196728 kb
Host smart-c0f4503e-f786-48e3-b522-1dcfd6c7e7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315280247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3315280247
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4284678288
Short name T50
Test name
Test status
Simulation time 525354686 ps
CPU time 1.4 seconds
Started Aug 01 06:51:38 PM PDT 24
Finished Aug 01 06:51:40 PM PDT 24
Peak memory 196636 kb
Host smart-b42602da-a247-4baf-8997-f6b788536627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284678288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4284678288
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1649998148
Short name T190
Test name
Test status
Simulation time 435374635 ps
CPU time 1.17 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 196708 kb
Host smart-d0e26b17-e2a6-4ab8-a6d2-0203b7ae466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649998148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1649998148
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2302790639
Short name T175
Test name
Test status
Simulation time 482760781 ps
CPU time 1.36 seconds
Started Aug 01 06:51:38 PM PDT 24
Finished Aug 01 06:51:40 PM PDT 24
Peak memory 196664 kb
Host smart-21500407-76f3-4a8b-be46-3e162f7078b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302790639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2302790639
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1410406343
Short name T166
Test name
Test status
Simulation time 489271400 ps
CPU time 1.07 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 196660 kb
Host smart-fb91f64b-b3c6-4219-a046-bfae7f72cba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410406343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1410406343
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.177278752
Short name T199
Test name
Test status
Simulation time 534035836 ps
CPU time 1.01 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 196600 kb
Host smart-6563ba09-9f37-4f76-ab30-8543b8457240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177278752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.177278752
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3491970613
Short name T193
Test name
Test status
Simulation time 561550001 ps
CPU time 0.66 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 196724 kb
Host smart-880d64f8-4a1d-4fe3-ab8f-0fbe6dea3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491970613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3491970613
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1779626351
Short name T37
Test name
Test status
Simulation time 556099816 ps
CPU time 1.02 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:51:30 PM PDT 24
Peak memory 196632 kb
Host smart-0bff3e3c-9098-4bc4-9088-411614b3e7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779626351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1779626351
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3428211962
Short name T186
Test name
Test status
Simulation time 379792074 ps
CPU time 0.71 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 196636 kb
Host smart-a2bbea7f-839b-4598-a7ed-f7c2a2d0a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428211962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3428211962
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4028631997
Short name T185
Test name
Test status
Simulation time 469143752 ps
CPU time 1.32 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 196592 kb
Host smart-06b9f59e-68b8-4718-a1c0-6b41f57bf4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028631997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4028631997
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4271116866
Short name T154
Test name
Test status
Simulation time 126003473705 ps
CPU time 19.43 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:52:00 PM PDT 24
Peak memory 191852 kb
Host smart-3a04492f-7730-45ff-81d5-ccc80f9c781c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271116866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4271116866
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2347400371
Short name T81
Test name
Test status
Simulation time 544656923 ps
CPU time 1.37 seconds
Started Aug 01 06:51:48 PM PDT 24
Finished Aug 01 06:51:50 PM PDT 24
Peak memory 196628 kb
Host smart-a36e0ca8-dbb1-46db-9802-4012cca2425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347400371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2347400371
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3282538302
Short name T97
Test name
Test status
Simulation time 523730122939 ps
CPU time 496.26 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:59:45 PM PDT 24
Peak memory 198212 kb
Host smart-424e0135-bfec-4ce1-a0e7-46e4095842e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282538302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3282538302
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3873611514
Short name T189
Test name
Test status
Simulation time 538064150 ps
CPU time 0.98 seconds
Started Aug 01 06:51:05 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 196692 kb
Host smart-1341283b-3f02-4d8b-b11c-cab986a0ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873611514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3873611514
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.291069467
Short name T180
Test name
Test status
Simulation time 548134567 ps
CPU time 0.97 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 196596 kb
Host smart-ea527e97-5138-4e42-866b-afc6c96cfbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291069467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.291069467
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1058115845
Short name T54
Test name
Test status
Simulation time 472640747 ps
CPU time 0.86 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 196564 kb
Host smart-408d987a-ce04-4b03-bf24-a6a49cd3b25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058115845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1058115845
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.4050397565
Short name T202
Test name
Test status
Simulation time 466711684 ps
CPU time 0.74 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:21 PM PDT 24
Peak memory 196648 kb
Host smart-04c63b98-85fd-49f1-8fe0-54ef6748c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050397565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4050397565
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.272890430
Short name T198
Test name
Test status
Simulation time 591561967 ps
CPU time 1.51 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:30 PM PDT 24
Peak memory 196600 kb
Host smart-3400209c-177f-4f22-80e7-8e7f22302b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272890430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.272890430
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3736472120
Short name T174
Test name
Test status
Simulation time 434486927 ps
CPU time 0.79 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:51:24 PM PDT 24
Peak memory 196620 kb
Host smart-eb10d8d1-dc44-4cfc-9b7a-b94d4a8454f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736472120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3736472120
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1734350551
Short name T188
Test name
Test status
Simulation time 498910745 ps
CPU time 0.75 seconds
Started Aug 01 06:51:36 PM PDT 24
Finished Aug 01 06:51:37 PM PDT 24
Peak memory 196612 kb
Host smart-dc6da8c4-359c-49d6-b2be-4accf93afd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734350551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1734350551
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2117349884
Short name T205
Test name
Test status
Simulation time 521281512 ps
CPU time 1.29 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 06:51:51 PM PDT 24
Peak memory 196620 kb
Host smart-1225dcc8-1734-4fc0-97ac-10bcd671be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117349884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2117349884
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2298361993
Short name T197
Test name
Test status
Simulation time 421610262 ps
CPU time 0.79 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 196704 kb
Host smart-01759872-469b-406c-83b3-25d433b81eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298361993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2298361993
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1747193000
Short name T314
Test name
Test status
Simulation time 581007514 ps
CPU time 0.76 seconds
Started Aug 01 06:56:39 PM PDT 24
Finished Aug 01 06:56:39 PM PDT 24
Peak memory 183760 kb
Host smart-5de155ce-8ddd-4764-8996-ac78cc0ecc3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747193000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1747193000
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3214330309
Short name T410
Test name
Test status
Simulation time 13186584693 ps
CPU time 8.9 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:46 PM PDT 24
Peak memory 184068 kb
Host smart-9ec7757f-b8be-4a67-848c-225676b6aa30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214330309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3214330309
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3396144168
Short name T70
Test name
Test status
Simulation time 1259901327 ps
CPU time 1.5 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:38 PM PDT 24
Peak memory 192980 kb
Host smart-78caea02-548b-40f7-aac7-45d03356472e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396144168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3396144168
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.227752395
Short name T318
Test name
Test status
Simulation time 372604953 ps
CPU time 0.92 seconds
Started Aug 01 06:56:39 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 197320 kb
Host smart-896e1539-954d-473f-81f6-8505f9237f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227752395 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.227752395
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.43162386
Short name T59
Test name
Test status
Simulation time 387535583 ps
CPU time 1.04 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:38 PM PDT 24
Peak memory 191956 kb
Host smart-962d1091-dd15-41c0-949a-f7a3eefad7f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43162386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.43162386
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.31769292
Short name T294
Test name
Test status
Simulation time 377601468 ps
CPU time 0.84 seconds
Started Aug 01 06:56:38 PM PDT 24
Finished Aug 01 06:56:39 PM PDT 24
Peak memory 192980 kb
Host smart-ace16db6-0673-40d8-8670-6dd2320139c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.31769292
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4086659604
Short name T409
Test name
Test status
Simulation time 488646152 ps
CPU time 0.84 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:37 PM PDT 24
Peak memory 183652 kb
Host smart-de495657-5f4b-4314-ba75-03e829bdfca3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086659604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4086659604
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385774474
Short name T329
Test name
Test status
Simulation time 508112033 ps
CPU time 1.16 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:37 PM PDT 24
Peak memory 183688 kb
Host smart-ef00d664-7711-4d31-93be-8be8cc2057a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385774474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2385774474
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.524233391
Short name T401
Test name
Test status
Simulation time 1371149076 ps
CPU time 3.22 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 192988 kb
Host smart-53577762-544a-4e08-aa90-073025e4236d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524233391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.524233391
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.203242289
Short name T343
Test name
Test status
Simulation time 624500086 ps
CPU time 2.41 seconds
Started Aug 01 06:56:38 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 198600 kb
Host smart-cd86a03e-4d91-4090-a952-55a58c3c3e61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203242289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.203242289
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3941949865
Short name T417
Test name
Test status
Simulation time 4447374318 ps
CPU time 2.66 seconds
Started Aug 01 06:56:37 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 198064 kb
Host smart-b2f42d00-c3cb-4c46-8f79-cecbbaf889be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941949865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3941949865
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2736549378
Short name T356
Test name
Test status
Simulation time 469602226 ps
CPU time 0.97 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 193060 kb
Host smart-bc1a7f5e-eb99-48c7-b8f7-5e9148dabdd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736549378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2736549378
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1149639941
Short name T56
Test name
Test status
Simulation time 8750224214 ps
CPU time 28.63 seconds
Started Aug 01 06:56:48 PM PDT 24
Finished Aug 01 06:57:17 PM PDT 24
Peak memory 195764 kb
Host smart-2467b77e-03d9-4b85-857f-eb54e1f0291b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149639941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1149639941
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.152678092
Short name T421
Test name
Test status
Simulation time 1290122831 ps
CPU time 1.39 seconds
Started Aug 01 06:56:46 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 193340 kb
Host smart-5cd76df9-5a6d-471a-a480-bf28a5654c02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152678092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.152678092
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1737426843
Short name T400
Test name
Test status
Simulation time 476907570 ps
CPU time 0.81 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 196100 kb
Host smart-6d163e45-b014-44e1-929c-636dd3044d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737426843 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1737426843
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.720669837
Short name T68
Test name
Test status
Simulation time 537288246 ps
CPU time 0.76 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 193324 kb
Host smart-198667dd-3d87-4f14-873d-ad1837d9afd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720669837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.720669837
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1264937096
Short name T379
Test name
Test status
Simulation time 407453636 ps
CPU time 1.19 seconds
Started Aug 01 06:56:39 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 192988 kb
Host smart-a7f0fcaf-cde3-40d8-952a-01704d4b9d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264937096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1264937096
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3383178080
Short name T339
Test name
Test status
Simulation time 273562802 ps
CPU time 0.85 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 183664 kb
Host smart-fb3b0544-3984-412e-aee5-5a6c2a697668
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383178080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3383178080
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1623379221
Short name T349
Test name
Test status
Simulation time 278822538 ps
CPU time 0.89 seconds
Started Aug 01 06:56:38 PM PDT 24
Finished Aug 01 06:56:39 PM PDT 24
Peak memory 183668 kb
Host smart-0d20ee86-155c-4e83-9c22-e1d73c5b7a70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623379221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1623379221
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2614465841
Short name T403
Test name
Test status
Simulation time 2083915525 ps
CPU time 3.08 seconds
Started Aug 01 06:56:48 PM PDT 24
Finished Aug 01 06:56:52 PM PDT 24
Peak memory 194796 kb
Host smart-dde6f571-faf8-4be4-9520-2d9bc3161e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614465841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2614465841
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2440548762
Short name T308
Test name
Test status
Simulation time 659523075 ps
CPU time 1.27 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:37 PM PDT 24
Peak memory 198628 kb
Host smart-13088113-ce45-46f1-b833-7ee0af015b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440548762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2440548762
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3017594111
Short name T210
Test name
Test status
Simulation time 4281178576 ps
CPU time 2.31 seconds
Started Aug 01 06:56:38 PM PDT 24
Finished Aug 01 06:56:40 PM PDT 24
Peak memory 196840 kb
Host smart-84bc2eb4-bfd0-43f4-b4a2-276bdbcde133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017594111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3017594111
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3595667193
Short name T395
Test name
Test status
Simulation time 509018614 ps
CPU time 0.99 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 195596 kb
Host smart-bec4b88b-86eb-4a68-9ab2-beb30fafc716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595667193 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3595667193
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1802910029
Short name T347
Test name
Test status
Simulation time 321371387 ps
CPU time 0.94 seconds
Started Aug 01 06:57:25 PM PDT 24
Finished Aug 01 06:57:26 PM PDT 24
Peak memory 183792 kb
Host smart-a86894a8-d547-4a05-85ff-b2adc6b1a436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802910029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1802910029
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1697593445
Short name T85
Test name
Test status
Simulation time 1542929191 ps
CPU time 1.47 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 193784 kb
Host smart-8759d1cc-5c19-4be5-b1ec-b0499a9612a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697593445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1697593445
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4262987315
Short name T331
Test name
Test status
Simulation time 1027606582 ps
CPU time 2.89 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 198552 kb
Host smart-f5d4785b-4ec8-4880-b104-3858199fd1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262987315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4262987315
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1948601463
Short name T327
Test name
Test status
Simulation time 4302216363 ps
CPU time 4.14 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:27 PM PDT 24
Peak memory 197864 kb
Host smart-af9f1c1c-bef0-470d-bbba-c44000ab0491
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948601463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1948601463
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4170532268
Short name T350
Test name
Test status
Simulation time 549593863 ps
CPU time 1.17 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 196552 kb
Host smart-feea99d4-4e50-497a-a44c-c6d61fb3642d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170532268 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4170532268
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3210214065
Short name T60
Test name
Test status
Simulation time 381138441 ps
CPU time 0.78 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 193232 kb
Host smart-86c6cc4f-f470-471c-b096-2018abc206f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210214065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3210214065
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2620322550
Short name T348
Test name
Test status
Simulation time 409773092 ps
CPU time 0.87 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 183820 kb
Host smart-8d94984a-2038-4263-ab08-38a2b9f67b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620322550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2620322550
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1200136151
Short name T352
Test name
Test status
Simulation time 1315212832 ps
CPU time 1.34 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 183904 kb
Host smart-db0670f2-0ff5-49fb-9a66-1c7acde671d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200136151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1200136151
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1730168727
Short name T338
Test name
Test status
Simulation time 410932423 ps
CPU time 1.35 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 198488 kb
Host smart-1dc4dc47-7269-4410-bac8-46d19364dd38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730168727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1730168727
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3695553282
Short name T26
Test name
Test status
Simulation time 8840882271 ps
CPU time 13.48 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 198712 kb
Host smart-90bf2d04-71bc-43a9-87a3-221e4b46d022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695553282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3695553282
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1396596753
Short name T28
Test name
Test status
Simulation time 442499668 ps
CPU time 0.8 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 196492 kb
Host smart-b91ddcac-5f81-4456-9086-2b80556279f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396596753 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1396596753
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.958939772
Short name T73
Test name
Test status
Simulation time 553084520 ps
CPU time 0.69 seconds
Started Aug 01 06:57:37 PM PDT 24
Finished Aug 01 06:57:37 PM PDT 24
Peak memory 194024 kb
Host smart-8712e317-295f-4d6f-b9c1-caf39baec967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958939772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.958939772
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4207241604
Short name T306
Test name
Test status
Simulation time 296306234 ps
CPU time 0.95 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 193016 kb
Host smart-2039dd7a-1c14-48b4-8386-1464681c74cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207241604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4207241604
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1405160692
Short name T382
Test name
Test status
Simulation time 1093662711 ps
CPU time 2.81 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:38 PM PDT 24
Peak memory 193720 kb
Host smart-7ae99e9e-b7dd-4505-9c86-f051bc175280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405160692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1405160692
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2974299708
Short name T328
Test name
Test status
Simulation time 349755585 ps
CPU time 2.66 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 198612 kb
Host smart-c813f03b-0b65-4c68-98a3-c9f706416f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974299708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2974299708
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1887046333
Short name T418
Test name
Test status
Simulation time 7844021626 ps
CPU time 12.04 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 198328 kb
Host smart-caaa0bde-48f9-40d5-b046-535a621e8e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887046333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1887046333
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1057678932
Short name T305
Test name
Test status
Simulation time 554550234 ps
CPU time 1.1 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 197000 kb
Host smart-0c7dba3b-bba8-4e34-a5b0-5d94062126b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057678932 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1057678932
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2710074852
Short name T335
Test name
Test status
Simulation time 484552323 ps
CPU time 0.69 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 192940 kb
Host smart-e4d2ee81-5dd7-423f-8a6d-009efc38b3a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710074852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2710074852
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.297108887
Short name T319
Test name
Test status
Simulation time 368329531 ps
CPU time 1.04 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 183768 kb
Host smart-0f32ada6-659c-4ed4-9814-02e814ea4569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297108887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.297108887
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4061987052
Short name T88
Test name
Test status
Simulation time 1522969261 ps
CPU time 2.15 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 183804 kb
Host smart-18deda24-8e0c-457a-81a9-82bc8fc9ceff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061987052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4061987052
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3429126148
Short name T322
Test name
Test status
Simulation time 667161568 ps
CPU time 1.37 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 198600 kb
Host smart-fba523c3-0788-4582-815f-1519b7a6b541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429126148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3429126148
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.277976519
Short name T208
Test name
Test status
Simulation time 7707774887 ps
CPU time 7.02 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:43 PM PDT 24
Peak memory 198464 kb
Host smart-b226b911-d082-424c-8bde-cfa03f83b67f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277976519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.277976519
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3443301572
Short name T297
Test name
Test status
Simulation time 470767208 ps
CPU time 1.24 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 195688 kb
Host smart-dc96cb7a-a3f5-4e05-8959-bfb7dfd8baf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443301572 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3443301572
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3661862446
Short name T84
Test name
Test status
Simulation time 477063304 ps
CPU time 0.64 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 193060 kb
Host smart-f39475dd-e373-4d9a-9960-3474be78819f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661862446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3661862446
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3228891655
Short name T392
Test name
Test status
Simulation time 308162359 ps
CPU time 0.99 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 192992 kb
Host smart-9dfb5223-e0f3-4f20-a218-078e169a1f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228891655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3228891655
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.239569345
Short name T86
Test name
Test status
Simulation time 1398460201 ps
CPU time 4.57 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:39 PM PDT 24
Peak memory 194048 kb
Host smart-d58504c9-065b-4f3a-9f82-1ef38a7fbb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239569345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.239569345
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2740308657
Short name T320
Test name
Test status
Simulation time 380497136 ps
CPU time 2.32 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 198656 kb
Host smart-fb8ff64b-8a2d-480a-a4d1-772fb8fd2e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740308657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2740308657
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1861514380
Short name T206
Test name
Test status
Simulation time 8233050359 ps
CPU time 13.26 seconds
Started Aug 01 06:57:34 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 198316 kb
Host smart-5b38009f-6d1c-4bb1-9234-04035ff193b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861514380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1861514380
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3118760196
Short name T333
Test name
Test status
Simulation time 402368256 ps
CPU time 0.96 seconds
Started Aug 01 06:57:36 PM PDT 24
Finished Aug 01 06:57:37 PM PDT 24
Peak memory 196008 kb
Host smart-df97e819-0958-42d7-9cab-ffe7c5d66790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118760196 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3118760196
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4219148355
Short name T391
Test name
Test status
Simulation time 468807075 ps
CPU time 1.19 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 193088 kb
Host smart-0b6e69ee-c3bc-403d-8061-e28770782118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219148355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4219148355
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.453382773
Short name T361
Test name
Test status
Simulation time 305494959 ps
CPU time 0.63 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 183732 kb
Host smart-42daee0e-f7c5-419c-bb2f-8c9d5a0576d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453382773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.453382773
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1307668129
Short name T332
Test name
Test status
Simulation time 2324779376 ps
CPU time 1.86 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 194972 kb
Host smart-a8f42fb6-3416-414c-958a-a8fcebaa360f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307668129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1307668129
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.337543262
Short name T397
Test name
Test status
Simulation time 538375028 ps
CPU time 2 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:37 PM PDT 24
Peak memory 198628 kb
Host smart-428a19c3-a7fc-4b87-8eab-92a370ef2bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337543262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.337543262
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2489090028
Short name T209
Test name
Test status
Simulation time 8474798496 ps
CPU time 6.29 seconds
Started Aug 01 06:57:36 PM PDT 24
Finished Aug 01 06:57:42 PM PDT 24
Peak memory 198472 kb
Host smart-83b84a19-5ba2-4102-807e-e4aeb9568d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489090028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2489090028
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1323884300
Short name T316
Test name
Test status
Simulation time 556746886 ps
CPU time 0.96 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 197856 kb
Host smart-46092b52-8749-476c-b508-012ae390ea7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323884300 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1323884300
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2334585026
Short name T63
Test name
Test status
Simulation time 348659918 ps
CPU time 0.82 seconds
Started Aug 01 06:57:35 PM PDT 24
Finished Aug 01 06:57:36 PM PDT 24
Peak memory 193416 kb
Host smart-32e28123-91ae-47dd-b5ec-a85fe025ca1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334585026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2334585026
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3816666283
Short name T330
Test name
Test status
Simulation time 492303097 ps
CPU time 0.88 seconds
Started Aug 01 06:57:36 PM PDT 24
Finished Aug 01 06:57:37 PM PDT 24
Peak memory 193016 kb
Host smart-53047cde-ea8d-476c-9103-7056755f918b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816666283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3816666283
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.631801375
Short name T396
Test name
Test status
Simulation time 2883072696 ps
CPU time 8.74 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:54 PM PDT 24
Peak memory 194984 kb
Host smart-d3151ebe-719b-4e3b-96b3-8b5eae007d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631801375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.631801375
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2542291200
Short name T360
Test name
Test status
Simulation time 672219969 ps
CPU time 1.53 seconds
Started Aug 01 06:57:33 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 198640 kb
Host smart-67e53f02-78d3-4c93-976c-0797f1967451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542291200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2542291200
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.712787422
Short name T365
Test name
Test status
Simulation time 4296465312 ps
CPU time 6.07 seconds
Started Aug 01 06:57:37 PM PDT 24
Finished Aug 01 06:57:43 PM PDT 24
Peak memory 196864 kb
Host smart-51ad5886-53ea-4068-bd1a-2c16366225a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712787422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.712787422
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3923801154
Short name T29
Test name
Test status
Simulation time 496727467 ps
CPU time 1.35 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 196336 kb
Host smart-d626c78b-c160-460a-8834-ea9ff8ee84cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923801154 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3923801154
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.420503863
Short name T67
Test name
Test status
Simulation time 387882627 ps
CPU time 0.66 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 194028 kb
Host smart-906c562e-5d44-4c21-ae52-c85ee46b9b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420503863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.420503863
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2859477141
Short name T351
Test name
Test status
Simulation time 641784444 ps
CPU time 0.57 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 183796 kb
Host smart-511abd85-f3b8-4eb7-9a9b-20c80a5ef7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859477141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2859477141
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3226378271
Short name T344
Test name
Test status
Simulation time 1450828805 ps
CPU time 3.13 seconds
Started Aug 01 06:57:50 PM PDT 24
Finished Aug 01 06:57:53 PM PDT 24
Peak memory 193392 kb
Host smart-2eb1043b-ca1f-49ff-9ed4-55a597091919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226378271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3226378271
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2753589504
Short name T301
Test name
Test status
Simulation time 503112009 ps
CPU time 2.66 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 198620 kb
Host smart-c6a08333-e751-4bba-a35c-bc53ba31623b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753589504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2753589504
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4083583799
Short name T341
Test name
Test status
Simulation time 4677936693 ps
CPU time 1.66 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 196740 kb
Host smart-da3756c3-f2df-4045-abff-f5fa5c431766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083583799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4083583799
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1519067089
Short name T406
Test name
Test status
Simulation time 431014169 ps
CPU time 1.07 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 198444 kb
Host smart-fb0e70e4-d1de-412f-b1fb-35ced33e5c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519067089 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1519067089
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4153402350
Short name T62
Test name
Test status
Simulation time 306660804 ps
CPU time 1.03 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 193036 kb
Host smart-2e2d8fab-b172-46f9-95e1-c7ed4efea2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153402350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4153402350
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4000238673
Short name T309
Test name
Test status
Simulation time 345897750 ps
CPU time 0.68 seconds
Started Aug 01 06:57:47 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 183784 kb
Host smart-ed7bfc0a-f225-42df-82dc-a537afffce74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000238673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4000238673
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3304905207
Short name T373
Test name
Test status
Simulation time 2387251569 ps
CPU time 4.68 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 195136 kb
Host smart-d96b4a25-8dd3-4a50-9e74-13f78f8c88e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304905207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3304905207
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3547548830
Short name T292
Test name
Test status
Simulation time 329809947 ps
CPU time 1.45 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 198404 kb
Host smart-52e43e6d-1e8c-4193-a4f7-c0d184d483b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547548830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3547548830
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2648649765
Short name T364
Test name
Test status
Simulation time 4028044974 ps
CPU time 2.74 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 197824 kb
Host smart-7788a22e-e15b-43ac-a57a-b21fdd998f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648649765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2648649765
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1971223282
Short name T404
Test name
Test status
Simulation time 314505333 ps
CPU time 1.11 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 196024 kb
Host smart-85c7ca9e-4418-4c7b-afaa-207a1adb2dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971223282 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1971223282
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.833866725
Short name T69
Test name
Test status
Simulation time 419665566 ps
CPU time 1.27 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 193400 kb
Host smart-629ea014-b364-4a4a-a04d-a0a695e91652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833866725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.833866725
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3324836007
Short name T334
Test name
Test status
Simulation time 295619632 ps
CPU time 0.74 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 183796 kb
Host smart-6501f31c-7d64-40d1-9c53-b95265f484dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324836007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3324836007
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2024700204
Short name T90
Test name
Test status
Simulation time 1685778044 ps
CPU time 2.47 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 193288 kb
Host smart-bf324bb6-7f72-42b3-b36a-0a464495b749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024700204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2024700204
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3975264663
Short name T310
Test name
Test status
Simulation time 756812080 ps
CPU time 2.04 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 198640 kb
Host smart-a65df7a8-095b-4269-bce6-6f15b618a6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975264663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3975264663
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1519612397
Short name T393
Test name
Test status
Simulation time 4303913203 ps
CPU time 6.83 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:52 PM PDT 24
Peak memory 198440 kb
Host smart-8e65baf8-dc57-42b4-8535-2f034d2611c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519612397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1519612397
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3486475433
Short name T64
Test name
Test status
Simulation time 585474568 ps
CPU time 0.92 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:56:58 PM PDT 24
Peak memory 194620 kb
Host smart-3d4cb55d-364f-4f60-bc19-947404c943b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486475433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3486475433
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3601751508
Short name T61
Test name
Test status
Simulation time 1160105025 ps
CPU time 2.22 seconds
Started Aug 01 06:56:47 PM PDT 24
Finished Aug 01 06:56:50 PM PDT 24
Peak memory 193112 kb
Host smart-8e13bf22-979d-43bc-9c93-305512a247a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601751508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3601751508
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.39059918
Short name T422
Test name
Test status
Simulation time 545246490 ps
CPU time 0.85 seconds
Started Aug 01 06:56:58 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 198352 kb
Host smart-dfd077de-7f35-47ad-b92b-9f2fdf812a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059918 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.39059918
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3016389995
Short name T359
Test name
Test status
Simulation time 432486632 ps
CPU time 0.85 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:56:58 PM PDT 24
Peak memory 192972 kb
Host smart-65855580-ed68-4c93-aefe-89b431ccb359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016389995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3016389995
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3503865775
Short name T298
Test name
Test status
Simulation time 427629999 ps
CPU time 1.07 seconds
Started Aug 01 06:56:46 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 192968 kb
Host smart-cba68524-dc7b-4ecf-ae77-4b6e95933e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503865775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3503865775
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2168028853
Short name T312
Test name
Test status
Simulation time 511216431 ps
CPU time 0.89 seconds
Started Aug 01 06:56:49 PM PDT 24
Finished Aug 01 06:56:50 PM PDT 24
Peak memory 183892 kb
Host smart-f6293a3b-46c1-4626-bf85-c429bc1793ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168028853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2168028853
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.18896808
Short name T317
Test name
Test status
Simulation time 536840748 ps
CPU time 0.66 seconds
Started Aug 01 06:56:45 PM PDT 24
Finished Aug 01 06:56:46 PM PDT 24
Peak memory 183696 kb
Host smart-0a4b3d9f-36c5-4601-b312-6cb6c3dfc08b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wal
k.18896808
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.654599038
Short name T87
Test name
Test status
Simulation time 1657193991 ps
CPU time 2.86 seconds
Started Aug 01 06:57:00 PM PDT 24
Finished Aug 01 06:57:03 PM PDT 24
Peak memory 193012 kb
Host smart-5bc620f1-bb87-43b3-b4c9-4e10b48f41bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654599038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.654599038
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3297198471
Short name T380
Test name
Test status
Simulation time 819989554 ps
CPU time 1.87 seconds
Started Aug 01 06:56:49 PM PDT 24
Finished Aug 01 06:56:51 PM PDT 24
Peak memory 198640 kb
Host smart-f5d15e54-a205-445c-b0d9-e4dc71940a17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297198471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3297198471
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1402444582
Short name T383
Test name
Test status
Simulation time 395018007 ps
CPU time 0.65 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 183768 kb
Host smart-c4e434b0-3e78-476f-903f-65d87b0e92bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402444582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1402444582
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.535476877
Short name T398
Test name
Test status
Simulation time 534788285 ps
CPU time 0.77 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 183752 kb
Host smart-549a7f4b-9d26-45f6-8bb9-96b950b7d8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535476877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.535476877
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1689934327
Short name T295
Test name
Test status
Simulation time 374929170 ps
CPU time 0.61 seconds
Started Aug 01 06:57:48 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 193028 kb
Host smart-7628ec1e-408c-4051-bb32-7e146c9ce25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689934327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1689934327
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.373294397
Short name T385
Test name
Test status
Simulation time 355384337 ps
CPU time 0.66 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 192972 kb
Host smart-7dfa8893-bac5-4372-8ffb-5f3e7eae142b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373294397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.373294397
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1674761876
Short name T300
Test name
Test status
Simulation time 372035553 ps
CPU time 0.61 seconds
Started Aug 01 06:57:47 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 183784 kb
Host smart-b8322813-e646-4be5-a58d-e7378e1057dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674761876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1674761876
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3778428165
Short name T337
Test name
Test status
Simulation time 519102196 ps
CPU time 0.69 seconds
Started Aug 01 06:57:47 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 183740 kb
Host smart-039e9967-76bf-4578-a40c-61093ae00645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778428165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3778428165
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2893889154
Short name T405
Test name
Test status
Simulation time 406054764 ps
CPU time 0.67 seconds
Started Aug 01 06:57:46 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 183780 kb
Host smart-419ffe4d-c2e9-4f21-b1bf-8e4393cbf667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893889154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2893889154
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3985555436
Short name T293
Test name
Test status
Simulation time 433167344 ps
CPU time 1.14 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 183812 kb
Host smart-ad0557a8-62ce-45d7-8899-38abfb343845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985555436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3985555436
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3114736596
Short name T315
Test name
Test status
Simulation time 530493141 ps
CPU time 0.76 seconds
Started Aug 01 06:57:48 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 192960 kb
Host smart-1b967ffd-4a3d-4ac1-96ac-47228fb24c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114736596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3114736596
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4234551861
Short name T299
Test name
Test status
Simulation time 536599528 ps
CPU time 0.68 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 192992 kb
Host smart-ec209ef5-83d3-4fda-b6c0-ea7d19c7b5bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234551861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4234551861
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3302844462
Short name T25
Test name
Test status
Simulation time 481541396 ps
CPU time 1.79 seconds
Started Aug 01 06:57:02 PM PDT 24
Finished Aug 01 06:57:04 PM PDT 24
Peak memory 194656 kb
Host smart-520f0b5a-c0a3-4735-95c0-5013c332a094
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302844462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3302844462
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1068454773
Short name T83
Test name
Test status
Simulation time 7146410773 ps
CPU time 3.54 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:57:01 PM PDT 24
Peak memory 196204 kb
Host smart-b722a71e-8213-460e-a316-a07f401f96c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068454773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1068454773
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3713194257
Short name T71
Test name
Test status
Simulation time 638944723 ps
CPU time 1.37 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 192124 kb
Host smart-e6cc3af2-873d-459b-8378-14e030be6d70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713194257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3713194257
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2111015991
Short name T369
Test name
Test status
Simulation time 530512902 ps
CPU time 0.78 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 195036 kb
Host smart-a602f2ed-4abd-46d9-8703-46e9044b69cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111015991 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2111015991
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3205865404
Short name T363
Test name
Test status
Simulation time 534840454 ps
CPU time 1.35 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 192960 kb
Host smart-e436e9e6-25e8-4fe5-9c3e-78ad9e2589e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205865404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3205865404
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1255362161
Short name T386
Test name
Test status
Simulation time 269568047 ps
CPU time 0.9 seconds
Started Aug 01 06:56:58 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 183784 kb
Host smart-c24a3b91-9e1d-4b08-bdcd-639b60e9fac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255362161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1255362161
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2357749647
Short name T388
Test name
Test status
Simulation time 374263165 ps
CPU time 0.75 seconds
Started Aug 01 06:57:00 PM PDT 24
Finished Aug 01 06:57:00 PM PDT 24
Peak memory 183704 kb
Host smart-f11c2c68-9782-4ba3-97c6-948ec212cfe2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357749647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2357749647
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.213330919
Short name T407
Test name
Test status
Simulation time 275789504 ps
CPU time 0.89 seconds
Started Aug 01 06:56:57 PM PDT 24
Finished Aug 01 06:56:58 PM PDT 24
Peak memory 183628 kb
Host smart-d416a3d3-6012-4663-aca7-1ec8bc9960b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213330919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.213330919
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3551026235
Short name T390
Test name
Test status
Simulation time 966031898 ps
CPU time 1.09 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 193680 kb
Host smart-189560df-3429-4c76-a905-39ff230394d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551026235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3551026235
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2240595238
Short name T381
Test name
Test status
Simulation time 522703513 ps
CPU time 2.84 seconds
Started Aug 01 06:56:58 PM PDT 24
Finished Aug 01 06:57:01 PM PDT 24
Peak memory 198640 kb
Host smart-18181a3a-ef7b-4cfd-b12b-998fa893a924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240595238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2240595238
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3660308150
Short name T416
Test name
Test status
Simulation time 4202738142 ps
CPU time 1.92 seconds
Started Aug 01 06:56:59 PM PDT 24
Finished Aug 01 06:57:01 PM PDT 24
Peak memory 197692 kb
Host smart-b3257b0a-bf23-4bdb-9e1c-e7f2cd83de5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660308150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3660308150
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.815786556
Short name T324
Test name
Test status
Simulation time 515887686 ps
CPU time 0.72 seconds
Started Aug 01 06:57:44 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 183800 kb
Host smart-d285c805-ec6e-4458-85ae-d0f031d9fd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815786556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.815786556
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2353665284
Short name T303
Test name
Test status
Simulation time 436010388 ps
CPU time 0.78 seconds
Started Aug 01 06:57:45 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 183796 kb
Host smart-3b81f1f7-19da-4198-8b27-76873545ed70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353665284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2353665284
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3530410482
Short name T387
Test name
Test status
Simulation time 573322441 ps
CPU time 0.59 seconds
Started Aug 01 06:57:48 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 193028 kb
Host smart-8174b237-a6c6-4e76-aa12-bf99bf85c9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530410482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3530410482
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.263806077
Short name T402
Test name
Test status
Simulation time 463531842 ps
CPU time 1.19 seconds
Started Aug 01 06:57:48 PM PDT 24
Finished Aug 01 06:57:50 PM PDT 24
Peak memory 183808 kb
Host smart-112348a0-8790-4e0e-b8c0-fd37d21fa37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263806077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.263806077
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.639561355
Short name T413
Test name
Test status
Simulation time 497659245 ps
CPU time 1.19 seconds
Started Aug 01 06:57:55 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 193012 kb
Host smart-7cefd9af-c2f9-42af-9ebb-f62e00e6a37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639561355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.639561355
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.248785127
Short name T345
Test name
Test status
Simulation time 439232395 ps
CPU time 0.67 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 183804 kb
Host smart-99906bb5-169b-48b7-8da3-ef9c92b080ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248785127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.248785127
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.699068582
Short name T378
Test name
Test status
Simulation time 350888853 ps
CPU time 0.75 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 183768 kb
Host smart-733207ee-0e10-445e-90e2-342161bba8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699068582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.699068582
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1357218219
Short name T302
Test name
Test status
Simulation time 400041570 ps
CPU time 0.69 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 183756 kb
Host smart-6f77b75a-55c0-4edf-abaa-da3846a27599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357218219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1357218219
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4183248075
Short name T371
Test name
Test status
Simulation time 371352576 ps
CPU time 0.65 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 183760 kb
Host smart-41500e5b-c796-4970-b60d-20cc0a991a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183248075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4183248075
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3793899766
Short name T340
Test name
Test status
Simulation time 481374126 ps
CPU time 1.26 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 183776 kb
Host smart-20c8b356-456f-4458-9f75-ca4bde1f6352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793899766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3793899766
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2907368059
Short name T23
Test name
Test status
Simulation time 567872798 ps
CPU time 1.15 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 195088 kb
Host smart-6368a3f9-d379-4c08-8f67-498ee5bd6257
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907368059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2907368059
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1123279457
Short name T72
Test name
Test status
Simulation time 12794000366 ps
CPU time 6.53 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:16 PM PDT 24
Peak memory 192288 kb
Host smart-bcd62606-6a16-43fb-99c0-416896c5c7a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123279457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1123279457
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2164677072
Short name T323
Test name
Test status
Simulation time 978969429 ps
CPU time 0.89 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:10 PM PDT 24
Peak memory 183760 kb
Host smart-286ef862-a95a-45cc-be33-c65a77c6538b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164677072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2164677072
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4272054331
Short name T358
Test name
Test status
Simulation time 489873221 ps
CPU time 0.96 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 195612 kb
Host smart-a0adf9d1-7291-4275-ba5c-4756385657cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272054331 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4272054331
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2848294419
Short name T65
Test name
Test status
Simulation time 438181631 ps
CPU time 0.9 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:10 PM PDT 24
Peak memory 193132 kb
Host smart-9846a5bd-3aa7-46c3-9b26-db71414caf36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848294419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2848294419
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.470615151
Short name T326
Test name
Test status
Simulation time 399863771 ps
CPU time 0.57 seconds
Started Aug 01 06:57:08 PM PDT 24
Finished Aug 01 06:57:09 PM PDT 24
Peak memory 183756 kb
Host smart-9c6d60e2-9515-414e-b389-65f6a72bc0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470615151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.470615151
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4196892830
Short name T399
Test name
Test status
Simulation time 390529669 ps
CPU time 1.06 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:12 PM PDT 24
Peak memory 183692 kb
Host smart-0125bd0b-7cc6-42bf-96c8-d647efe0e3c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196892830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4196892830
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1197107664
Short name T384
Test name
Test status
Simulation time 465853578 ps
CPU time 0.68 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 183652 kb
Host smart-a1ff2fce-d97b-49ea-bcc7-e1b133755b45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197107664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1197107664
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3712592233
Short name T415
Test name
Test status
Simulation time 2506240179 ps
CPU time 1.85 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 193884 kb
Host smart-86cae51b-a675-42a1-a8f5-eeda6e1980c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712592233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3712592233
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.523250265
Short name T372
Test name
Test status
Simulation time 397521753 ps
CPU time 2.06 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:12 PM PDT 24
Peak memory 198648 kb
Host smart-6206b59a-ed8e-4b55-8215-9212665d1895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523250265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.523250265
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1927965540
Short name T311
Test name
Test status
Simulation time 4766209632 ps
CPU time 2.01 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:12 PM PDT 24
Peak memory 197700 kb
Host smart-62265f5f-d4f5-400d-b0ce-8b8e69fb05dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927965540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1927965540
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1840627480
Short name T346
Test name
Test status
Simulation time 328551966 ps
CPU time 0.96 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 193012 kb
Host smart-108d337c-8710-4037-b5bb-7da58f09dc9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840627480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1840627480
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3660934143
Short name T325
Test name
Test status
Simulation time 426852195 ps
CPU time 0.62 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 183752 kb
Host smart-cffd9858-1b8a-4246-87e8-acf915a1854e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660934143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3660934143
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2972444258
Short name T368
Test name
Test status
Simulation time 527302954 ps
CPU time 0.77 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 193016 kb
Host smart-28a70820-9825-409d-8ca6-8fb8121b62f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972444258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2972444258
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2238579483
Short name T376
Test name
Test status
Simulation time 294998593 ps
CPU time 0.75 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 183776 kb
Host smart-80a99f81-4486-4b79-978c-c830d380509d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238579483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2238579483
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1119769503
Short name T290
Test name
Test status
Simulation time 500524914 ps
CPU time 0.7 seconds
Started Aug 01 06:57:55 PM PDT 24
Finished Aug 01 06:57:56 PM PDT 24
Peak memory 183816 kb
Host smart-1327c01f-b1ea-4d33-a0f4-e6b51dc90f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119769503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1119769503
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3960525685
Short name T370
Test name
Test status
Simulation time 380252316 ps
CPU time 1.08 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 183792 kb
Host smart-ebc4fb96-f466-4323-8025-ac522dc85458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960525685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3960525685
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1114737601
Short name T366
Test name
Test status
Simulation time 461532476 ps
CPU time 0.62 seconds
Started Aug 01 06:57:55 PM PDT 24
Finished Aug 01 06:57:56 PM PDT 24
Peak memory 192948 kb
Host smart-159593e1-80fa-4e91-8b6b-f126717087c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114737601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1114737601
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4224118919
Short name T377
Test name
Test status
Simulation time 376273718 ps
CPU time 0.86 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 192972 kb
Host smart-c7ef1d06-7311-4512-b67f-6e21a2f7552c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224118919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4224118919
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3968195
Short name T412
Test name
Test status
Simulation time 347425777 ps
CPU time 1.01 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 183760 kb
Host smart-4eddfd22-7e06-45b3-90e6-d0f9e5403fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3968195
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2689850729
Short name T304
Test name
Test status
Simulation time 515904082 ps
CPU time 0.74 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 183736 kb
Host smart-5985783b-2834-4ba1-836f-d4013019d0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689850729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2689850729
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3496582627
Short name T375
Test name
Test status
Simulation time 600374765 ps
CPU time 0.76 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 196788 kb
Host smart-73b8e506-a8f6-49a9-b00b-18f574ade0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496582627 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3496582627
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1137164790
Short name T92
Test name
Test status
Simulation time 484851987 ps
CPU time 0.75 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 193380 kb
Host smart-97f30bd7-9d9f-445f-a692-cc8b2f7e9b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137164790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1137164790
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1825575516
Short name T321
Test name
Test status
Simulation time 546675281 ps
CPU time 0.69 seconds
Started Aug 01 06:57:23 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 183788 kb
Host smart-f1722b3a-827d-42a5-a192-6f42d320b9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825575516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1825575516
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.656263003
Short name T93
Test name
Test status
Simulation time 876173072 ps
CPU time 2.22 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 193000 kb
Host smart-3bf1409a-d69d-4ee9-96e3-ec7a071294e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656263003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.656263003
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1963954123
Short name T291
Test name
Test status
Simulation time 451953782 ps
CPU time 1.72 seconds
Started Aug 01 06:57:10 PM PDT 24
Finished Aug 01 06:57:12 PM PDT 24
Peak memory 198628 kb
Host smart-91e0beb4-1d51-4e64-9295-7ac016c80455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963954123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1963954123
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2111453958
Short name T313
Test name
Test status
Simulation time 4803244354 ps
CPU time 2.58 seconds
Started Aug 01 06:57:09 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 197644 kb
Host smart-f93766e0-f40a-420a-a135-a9b5061411d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111453958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2111453958
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2180804248
Short name T307
Test name
Test status
Simulation time 368639200 ps
CPU time 0.93 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 196076 kb
Host smart-9aeb31fe-c1d6-484f-aec0-1a9811205cb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180804248 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2180804248
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2964085165
Short name T420
Test name
Test status
Simulation time 289855247 ps
CPU time 0.97 seconds
Started Aug 01 06:57:23 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 193000 kb
Host smart-cb054f3a-5ed0-46d8-adaf-d30cca24e055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964085165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2964085165
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2263650481
Short name T367
Test name
Test status
Simulation time 493917784 ps
CPU time 0.67 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 183756 kb
Host smart-e34fd3eb-d26c-4e70-8417-ec3ad19c9554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263650481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2263650481
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.825498837
Short name T91
Test name
Test status
Simulation time 1804190311 ps
CPU time 2.64 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:25 PM PDT 24
Peak memory 191996 kb
Host smart-66528acb-8ec1-4341-9d1a-824bfa34723b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825498837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.825498837
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1616440431
Short name T357
Test name
Test status
Simulation time 551892181 ps
CPU time 2.14 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 198604 kb
Host smart-4021dd9a-11d2-4f64-aade-9454bc4daf61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616440431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1616440431
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1346377833
Short name T374
Test name
Test status
Simulation time 493740747 ps
CPU time 0.81 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 196192 kb
Host smart-c67d02c0-85ed-4d6d-ba97-540a42a39ecb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346377833 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1346377833
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3710094253
Short name T408
Test name
Test status
Simulation time 313587631 ps
CPU time 0.78 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 192032 kb
Host smart-6776b155-963b-4e3f-9554-084e406d1edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710094253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3710094253
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.911851918
Short name T362
Test name
Test status
Simulation time 476964900 ps
CPU time 0.9 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 193016 kb
Host smart-39e3d6ee-30d6-46d5-a532-3099c78d2a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911851918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.911851918
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1994646577
Short name T411
Test name
Test status
Simulation time 2258427117 ps
CPU time 1.95 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 192064 kb
Host smart-1febbefb-5d0c-4ae8-9360-286b770cde8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994646577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1994646577
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3023519473
Short name T414
Test name
Test status
Simulation time 451508323 ps
CPU time 2.19 seconds
Started Aug 01 06:57:19 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 198708 kb
Host smart-cb17cf8f-5ffe-4362-8401-b8e7ac89b5d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023519473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3023519473
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1111877727
Short name T354
Test name
Test status
Simulation time 4472301354 ps
CPU time 2.17 seconds
Started Aug 01 06:57:19 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 196748 kb
Host smart-86f825bd-b8b0-4a14-ab96-751ca225dba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111877727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1111877727
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.4170450543
Short name T419
Test name
Test status
Simulation time 449764008 ps
CPU time 1.08 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 198432 kb
Host smart-b50a4c24-deee-4b55-ad20-fff9841d7925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170450543 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.4170450543
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3871026484
Short name T66
Test name
Test status
Simulation time 286889149 ps
CPU time 0.98 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 193052 kb
Host smart-30b9fa9a-ecf9-45cc-9837-107f5bcdde4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871026484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3871026484
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.95644795
Short name T394
Test name
Test status
Simulation time 313443843 ps
CPU time 0.96 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 183752 kb
Host smart-a614a6e2-84f3-46b2-860f-4f69c689a09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95644795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.95644795
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2041034817
Short name T353
Test name
Test status
Simulation time 2718121860 ps
CPU time 2.56 seconds
Started Aug 01 06:57:19 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 195332 kb
Host smart-b8f0bb8f-8fc8-461c-b6c8-f132ba42a152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041034817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2041034817
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.7711225
Short name T296
Test name
Test status
Simulation time 775831474 ps
CPU time 2.18 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 198648 kb
Host smart-0a3c4e13-74d8-439a-8e49-0e38345ba2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7711225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.7711225
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2425388509
Short name T207
Test name
Test status
Simulation time 4185109690 ps
CPU time 2.18 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 196524 kb
Host smart-c41bf5d1-0326-411f-a54c-06e32c1601d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425388509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2425388509
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.468921939
Short name T342
Test name
Test status
Simulation time 437251186 ps
CPU time 0.81 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 195416 kb
Host smart-68bdee57-b736-4872-a60a-f66c6cd35f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468921939 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.468921939
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1249617519
Short name T58
Test name
Test status
Simulation time 402003509 ps
CPU time 0.86 seconds
Started Aug 01 06:57:20 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 193104 kb
Host smart-421281a1-c67f-4248-85d4-6cedf01087b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249617519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1249617519
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.520417926
Short name T389
Test name
Test status
Simulation time 324197583 ps
CPU time 0.66 seconds
Started Aug 01 06:57:22 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 192976 kb
Host smart-1a2e5c1c-93f6-43d2-af02-2b76d488c1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520417926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.520417926
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.34738288
Short name T336
Test name
Test status
Simulation time 1225385489 ps
CPU time 3.68 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:25 PM PDT 24
Peak memory 183796 kb
Host smart-dcad2d64-ccee-4f4a-b20b-cdcace16887d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34738288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_t
imer_same_csr_outstanding.34738288
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4012713571
Short name T289
Test name
Test status
Simulation time 417768982 ps
CPU time 2.05 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 198640 kb
Host smart-dd0d660c-6152-46fc-9184-c3c560c3066f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012713571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4012713571
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3370192542
Short name T355
Test name
Test status
Simulation time 4559666677 ps
CPU time 1.8 seconds
Started Aug 01 06:57:21 PM PDT 24
Finished Aug 01 06:57:23 PM PDT 24
Peak memory 197812 kb
Host smart-60c61f1e-b0bc-44e6-b787-0ab5d9503d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370192542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3370192542
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2818218566
Short name T253
Test name
Test status
Simulation time 9583022731 ps
CPU time 12.7 seconds
Started Aug 01 06:51:05 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 191892 kb
Host smart-24412ce8-c18e-4b8d-bbce-dfd681203306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818218566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2818218566
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3297789727
Short name T259
Test name
Test status
Simulation time 516994617 ps
CPU time 0.95 seconds
Started Aug 01 06:51:05 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 196676 kb
Host smart-4ef7df74-cb1a-48df-a565-3274d73ddedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297789727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3297789727
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2559849125
Short name T252
Test name
Test status
Simulation time 12052843070 ps
CPU time 18.66 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:21 PM PDT 24
Peak memory 196900 kb
Host smart-4639284e-e8d0-4a2d-b46f-17ef960b7cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559849125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2559849125
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2585465268
Short name T20
Test name
Test status
Simulation time 4651355935 ps
CPU time 1.94 seconds
Started Aug 01 06:51:14 PM PDT 24
Finished Aug 01 06:51:16 PM PDT 24
Peak memory 215724 kb
Host smart-f5c16268-db2a-467b-80af-fd766ee10db6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585465268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2585465268
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3348900578
Short name T263
Test name
Test status
Simulation time 371233795 ps
CPU time 0.83 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 196652 kb
Host smart-f56c68a6-63f2-4210-b6f7-e5500a3a46df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348900578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3348900578
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.245775004
Short name T106
Test name
Test status
Simulation time 37955193888 ps
CPU time 71.42 seconds
Started Aug 01 06:51:05 PM PDT 24
Finished Aug 01 06:52:17 PM PDT 24
Peak memory 214000 kb
Host smart-f07ab807-1ce9-4917-9c85-a70ca2d3aa6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245775004 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.245775004
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.207416567
Short name T233
Test name
Test status
Simulation time 39405385905 ps
CPU time 18.76 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:51:27 PM PDT 24
Peak memory 196888 kb
Host smart-ef7bd863-c348-471e-a597-2b396d3b7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207416567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.207416567
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1489865344
Short name T250
Test name
Test status
Simulation time 385135410 ps
CPU time 0.74 seconds
Started Aug 01 06:51:32 PM PDT 24
Finished Aug 01 06:51:33 PM PDT 24
Peak memory 196684 kb
Host smart-56e487f3-e109-4a32-a9b8-08659deef6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489865344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1489865344
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1823134968
Short name T231
Test name
Test status
Simulation time 35395824615 ps
CPU time 4.68 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:51:13 PM PDT 24
Peak memory 196872 kb
Host smart-88fa30b3-0799-4086-bedb-ddad2aaedb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823134968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1823134968
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2253460523
Short name T278
Test name
Test status
Simulation time 477561747 ps
CPU time 0.92 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:20 PM PDT 24
Peak memory 191828 kb
Host smart-25ba4676-9fc2-476e-9819-6f60720ad7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253460523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2253460523
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3240663789
Short name T10
Test name
Test status
Simulation time 9065508022 ps
CPU time 4.3 seconds
Started Aug 01 06:51:18 PM PDT 24
Finished Aug 01 06:51:23 PM PDT 24
Peak memory 196896 kb
Host smart-d40e75cb-23cb-4b6a-ab9e-bd98bb42c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240663789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3240663789
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4127120385
Short name T228
Test name
Test status
Simulation time 364918624 ps
CPU time 1.13 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:51:10 PM PDT 24
Peak memory 196608 kb
Host smart-c44bed9c-b6dc-44ba-89c9-b3485150c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127120385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4127120385
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1023052360
Short name T255
Test name
Test status
Simulation time 14558886380 ps
CPU time 10.78 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 196864 kb
Host smart-96b430a8-65ab-4c5a-9732-fa53dcccc6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023052360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1023052360
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1384446730
Short name T7
Test name
Test status
Simulation time 521894673 ps
CPU time 0.79 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 191740 kb
Host smart-684af5a5-bf29-41e4-960c-fe8d8833b3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384446730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1384446730
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3512761912
Short name T200
Test name
Test status
Simulation time 545286282 ps
CPU time 0.73 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:51:24 PM PDT 24
Peak memory 196720 kb
Host smart-7a5096df-0b72-4799-b5b5-af3a391d4cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512761912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3512761912
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2606185828
Short name T239
Test name
Test status
Simulation time 41777778586 ps
CPU time 16.33 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:36 PM PDT 24
Peak memory 196856 kb
Host smart-5cb87bba-695a-4ddf-aaf3-9c27168e1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606185828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2606185828
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.724314355
Short name T261
Test name
Test status
Simulation time 467757726 ps
CPU time 0.87 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:21 PM PDT 24
Peak memory 191788 kb
Host smart-4ed29e65-47fa-4839-b74d-6048fd53824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724314355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.724314355
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2557211631
Short name T248
Test name
Test status
Simulation time 30861366400 ps
CPU time 12 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:51:35 PM PDT 24
Peak memory 191904 kb
Host smart-887a84b5-ad43-49ff-947d-4a248781b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557211631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2557211631
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2200732885
Short name T80
Test name
Test status
Simulation time 475331496 ps
CPU time 1.25 seconds
Started Aug 01 06:51:37 PM PDT 24
Finished Aug 01 06:51:39 PM PDT 24
Peak memory 196576 kb
Host smart-5a07808e-6c59-4e6a-acc6-ec4a795654c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200732885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2200732885
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4084343463
Short name T286
Test name
Test status
Simulation time 27360703365 ps
CPU time 34.9 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:54 PM PDT 24
Peak memory 191896 kb
Host smart-05f0777b-a32b-4430-929d-6101529d2c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084343463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4084343463
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4285310708
Short name T226
Test name
Test status
Simulation time 345404043 ps
CPU time 1.08 seconds
Started Aug 01 06:51:21 PM PDT 24
Finished Aug 01 06:51:22 PM PDT 24
Peak memory 196672 kb
Host smart-9f43d938-76b8-4e08-970a-3f67442b5be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285310708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4285310708
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3511762347
Short name T217
Test name
Test status
Simulation time 30187548363 ps
CPU time 38.73 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:58 PM PDT 24
Peak memory 196860 kb
Host smart-34448fde-466e-4501-8965-a4fe7365a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511762347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3511762347
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3046790401
Short name T53
Test name
Test status
Simulation time 655882275 ps
CPU time 0.66 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:19 PM PDT 24
Peak memory 191832 kb
Host smart-24f890bf-432e-477f-ab31-e96952785091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046790401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3046790401
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3118638552
Short name T240
Test name
Test status
Simulation time 44956746725 ps
CPU time 33.12 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:53 PM PDT 24
Peak memory 191852 kb
Host smart-4fe912e6-bb6b-43d9-91ba-2c1dd41498f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118638552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3118638552
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3231927553
Short name T279
Test name
Test status
Simulation time 470557906 ps
CPU time 0.77 seconds
Started Aug 01 06:51:27 PM PDT 24
Finished Aug 01 06:51:28 PM PDT 24
Peak memory 196608 kb
Host smart-0d5823ae-0271-484f-b0fe-790a4fc50eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231927553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3231927553
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1028897624
Short name T77
Test name
Test status
Simulation time 9649823209 ps
CPU time 12.72 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 191868 kb
Host smart-148e6379-24a4-48af-b04b-2cbc26f319f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028897624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1028897624
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3925247354
Short name T3
Test name
Test status
Simulation time 527453015 ps
CPU time 1.41 seconds
Started Aug 01 06:51:33 PM PDT 24
Finished Aug 01 06:51:34 PM PDT 24
Peak memory 191836 kb
Host smart-aee11c3b-6c24-4d97-a0ab-85106f3dc6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925247354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3925247354
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1521374114
Short name T288
Test name
Test status
Simulation time 41983087155 ps
CPU time 13.52 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 191880 kb
Host smart-1faff7ef-3865-4877-9713-720a97c77a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521374114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1521374114
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1536313849
Short name T17
Test name
Test status
Simulation time 4071030764 ps
CPU time 6.93 seconds
Started Aug 01 06:51:09 PM PDT 24
Finished Aug 01 06:51:16 PM PDT 24
Peak memory 215356 kb
Host smart-499e5a7f-cc01-4cc9-9e1b-3db254f065da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536313849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1536313849
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1880123063
Short name T282
Test name
Test status
Simulation time 565361618 ps
CPU time 0.77 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 196620 kb
Host smart-00e2a671-3d37-40ba-8f40-a8be590be2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880123063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1880123063
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3078072085
Short name T256
Test name
Test status
Simulation time 11771472471 ps
CPU time 16.8 seconds
Started Aug 01 06:51:22 PM PDT 24
Finished Aug 01 06:51:39 PM PDT 24
Peak memory 191884 kb
Host smart-0b82c7d0-16c0-4f4c-9de0-8f262bc0de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078072085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3078072085
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2846497057
Short name T38
Test name
Test status
Simulation time 447722196 ps
CPU time 1.28 seconds
Started Aug 01 06:51:19 PM PDT 24
Finished Aug 01 06:51:21 PM PDT 24
Peak memory 191320 kb
Host smart-cafd2a4f-1697-45b9-abd3-6a405a9dcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846497057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2846497057
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2809266482
Short name T247
Test name
Test status
Simulation time 36951028871 ps
CPU time 46.6 seconds
Started Aug 01 06:51:16 PM PDT 24
Finished Aug 01 06:52:02 PM PDT 24
Peak memory 191892 kb
Host smart-f9dd3f02-e9ab-4a1a-810c-50bb1de2f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809266482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2809266482
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3851401369
Short name T260
Test name
Test status
Simulation time 491379800 ps
CPU time 0.75 seconds
Started Aug 01 06:51:23 PM PDT 24
Finished Aug 01 06:51:24 PM PDT 24
Peak memory 191824 kb
Host smart-39f8d5bb-cebc-4295-8b6e-8a711ee99493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851401369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3851401369
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2216662429
Short name T162
Test name
Test status
Simulation time 560375089 ps
CPU time 0.66 seconds
Started Aug 01 06:51:21 PM PDT 24
Finished Aug 01 06:51:22 PM PDT 24
Peak memory 196756 kb
Host smart-79db6428-74b7-4402-ab80-4d4f4e649edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216662429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2216662429
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.557856964
Short name T212
Test name
Test status
Simulation time 37934820603 ps
CPU time 51.99 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:52:09 PM PDT 24
Peak memory 196896 kb
Host smart-41e34a2b-46e4-4a4b-a72a-6bad813415c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557856964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.557856964
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3961972568
Short name T2
Test name
Test status
Simulation time 483785320 ps
CPU time 1.41 seconds
Started Aug 01 06:51:32 PM PDT 24
Finished Aug 01 06:51:34 PM PDT 24
Peak memory 196628 kb
Host smart-c8ce71c0-c032-4e57-9f5f-2f4b70285f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961972568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3961972568
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.801802208
Short name T273
Test name
Test status
Simulation time 49266896994 ps
CPU time 35.06 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:52:04 PM PDT 24
Peak memory 191888 kb
Host smart-0fb99caa-d8c9-4bfd-bedd-9d659c2da232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801802208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.801802208
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.789475239
Short name T270
Test name
Test status
Simulation time 372237103 ps
CPU time 0.91 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:33 PM PDT 24
Peak memory 191896 kb
Host smart-7aabfb20-1286-4a7d-bbb3-30854c505668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789475239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.789475239
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1936248703
Short name T211
Test name
Test status
Simulation time 15439350642 ps
CPU time 24.22 seconds
Started Aug 01 06:51:32 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 191828 kb
Host smart-e25ce542-fe86-4198-a155-233c1cf9e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936248703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1936248703
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2073312925
Short name T227
Test name
Test status
Simulation time 381593035 ps
CPU time 0.85 seconds
Started Aug 01 06:51:41 PM PDT 24
Finished Aug 01 06:51:42 PM PDT 24
Peak memory 191832 kb
Host smart-73205f90-ecce-4fcd-9baa-31a3bdc42c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073312925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2073312925
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3950261738
Short name T41
Test name
Test status
Simulation time 29596791149 ps
CPU time 39.56 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 191852 kb
Host smart-a6e0d50b-eb25-4a0a-abe1-d324f46717e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950261738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3950261738
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4063189507
Short name T269
Test name
Test status
Simulation time 587368588 ps
CPU time 1.53 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:51:31 PM PDT 24
Peak memory 191808 kb
Host smart-6229e4e4-d130-445f-a119-c1418696ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063189507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4063189507
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1608621971
Short name T254
Test name
Test status
Simulation time 9705923451 ps
CPU time 12.19 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 196896 kb
Host smart-93af6340-cb21-4887-8d46-a99041db58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608621971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1608621971
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2461122889
Short name T271
Test name
Test status
Simulation time 561712589 ps
CPU time 0.75 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:51:26 PM PDT 24
Peak memory 191780 kb
Host smart-750c11d6-60a2-465d-a67c-2159790ef7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461122889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2461122889
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1596284233
Short name T195
Test name
Test status
Simulation time 560196120 ps
CPU time 0.97 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:51:27 PM PDT 24
Peak memory 196732 kb
Host smart-22377afd-0408-4ce5-ab88-792011f9cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596284233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1596284233
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1266654165
Short name T42
Test name
Test status
Simulation time 12711371004 ps
CPU time 9.61 seconds
Started Aug 01 06:51:34 PM PDT 24
Finished Aug 01 06:51:43 PM PDT 24
Peak memory 191832 kb
Host smart-2d078c92-909e-4020-b6a9-53ceab2330a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266654165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1266654165
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2972382320
Short name T242
Test name
Test status
Simulation time 643943785 ps
CPU time 0.65 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:17 PM PDT 24
Peak memory 191804 kb
Host smart-d53e1df7-160f-42fd-87ec-e06d95c819a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972382320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2972382320
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1000873496
Short name T96
Test name
Test status
Simulation time 41459922724 ps
CPU time 56.11 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:52:24 PM PDT 24
Peak memory 191804 kb
Host smart-438aae13-abbe-4ace-9dd7-3aa2fdd8e693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000873496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1000873496
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.271845938
Short name T266
Test name
Test status
Simulation time 38759083814 ps
CPU time 14.86 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:51:59 PM PDT 24
Peak memory 196904 kb
Host smart-ed6fe525-63ad-44a5-a380-03c258651829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271845938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.271845938
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4267855841
Short name T172
Test name
Test status
Simulation time 356215562 ps
CPU time 0.88 seconds
Started Aug 01 06:51:27 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 191708 kb
Host smart-59047b20-4fe0-4ac0-bb37-d4c0cc21eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267855841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4267855841
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.270520329
Short name T280
Test name
Test status
Simulation time 26555298883 ps
CPU time 16.95 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:52:03 PM PDT 24
Peak memory 191892 kb
Host smart-dee209b8-28a6-4504-a2bf-38b3e8362372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270520329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.270520329
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4055934507
Short name T223
Test name
Test status
Simulation time 473347225 ps
CPU time 1.34 seconds
Started Aug 01 06:51:41 PM PDT 24
Finished Aug 01 06:51:43 PM PDT 24
Peak memory 191836 kb
Host smart-81e00609-c678-4d25-9005-79b191fe8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055934507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4055934507
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.565819110
Short name T262
Test name
Test status
Simulation time 31666327934 ps
CPU time 41.5 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:49 PM PDT 24
Peak memory 191908 kb
Host smart-4e557761-2d24-4c4b-99ea-acebdbe7f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565819110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.565819110
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3282455071
Short name T18
Test name
Test status
Simulation time 8717675305 ps
CPU time 3.34 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 215800 kb
Host smart-99f6fa5f-55b3-4aaf-99ec-b3676520359f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282455071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3282455071
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.357091063
Short name T51
Test name
Test status
Simulation time 394002043 ps
CPU time 0.71 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:08 PM PDT 24
Peak memory 191836 kb
Host smart-4fdd8981-159d-42e4-85d8-e423c6ba1355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357091063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.357091063
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3769286296
Short name T12
Test name
Test status
Simulation time 27348034726 ps
CPU time 9.99 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:38 PM PDT 24
Peak memory 196884 kb
Host smart-e144a9a3-96b8-4b02-a169-e4bf856459b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769286296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3769286296
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3732149001
Short name T275
Test name
Test status
Simulation time 450598465 ps
CPU time 0.73 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:47 PM PDT 24
Peak memory 196548 kb
Host smart-71f764f2-f2f9-4ada-99e5-a22eb1c8c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732149001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3732149001
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1968383423
Short name T103
Test name
Test status
Simulation time 80987212406 ps
CPU time 211.48 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 199852 kb
Host smart-ef928a5f-cd98-46e5-8b54-bdb2fd415253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968383423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1968383423
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2832844929
Short name T220
Test name
Test status
Simulation time 6126077458 ps
CPU time 10.03 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 191876 kb
Host smart-9bd09d11-e5a4-474b-b559-f30940e0345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832844929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2832844929
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2383337796
Short name T246
Test name
Test status
Simulation time 526186101 ps
CPU time 0.78 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:51:30 PM PDT 24
Peak memory 196684 kb
Host smart-84134f40-92fa-44b4-a31c-85505abc2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383337796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2383337796
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.115209549
Short name T251
Test name
Test status
Simulation time 7684758342 ps
CPU time 12.22 seconds
Started Aug 01 06:51:38 PM PDT 24
Finished Aug 01 06:51:51 PM PDT 24
Peak memory 191888 kb
Host smart-b49bd2fc-f711-4ed8-af54-1921559d3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115209549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.115209549
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3714510297
Short name T235
Test name
Test status
Simulation time 462867112 ps
CPU time 0.92 seconds
Started Aug 01 06:51:27 PM PDT 24
Finished Aug 01 06:51:28 PM PDT 24
Peak memory 196624 kb
Host smart-5d058666-d51c-4a13-83d0-25832fb7e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714510297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3714510297
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1332802475
Short name T281
Test name
Test status
Simulation time 52626261961 ps
CPU time 18.06 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:51:47 PM PDT 24
Peak memory 191888 kb
Host smart-73aa2fea-6e0c-4880-baa2-afa68230b4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332802475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1332802475
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3521249253
Short name T95
Test name
Test status
Simulation time 496145507 ps
CPU time 1.21 seconds
Started Aug 01 06:51:26 PM PDT 24
Finished Aug 01 06:51:28 PM PDT 24
Peak memory 191836 kb
Host smart-efb28f6f-92a5-4c80-96af-4472ed20fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521249253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3521249253
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3844411489
Short name T264
Test name
Test status
Simulation time 35974097367 ps
CPU time 13.98 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 191892 kb
Host smart-ba609cdf-048b-4755-b198-fb7e4dc1ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844411489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3844411489
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4253296512
Short name T265
Test name
Test status
Simulation time 594315317 ps
CPU time 0.8 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 191816 kb
Host smart-5a52be20-86a5-4e75-8aef-3ddc448566a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253296512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4253296512
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1398762839
Short name T79
Test name
Test status
Simulation time 33283225269 ps
CPU time 53.41 seconds
Started Aug 01 06:51:30 PM PDT 24
Finished Aug 01 06:52:24 PM PDT 24
Peak memory 196852 kb
Host smart-3cf8b902-b642-401a-96d8-e460826bfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398762839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1398762839
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3468967667
Short name T6
Test name
Test status
Simulation time 443950199 ps
CPU time 0.6 seconds
Started Aug 01 06:51:25 PM PDT 24
Finished Aug 01 06:51:26 PM PDT 24
Peak memory 191828 kb
Host smart-091f56cf-24ec-4b53-98c7-fab53185fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468967667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3468967667
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3368207739
Short name T171
Test name
Test status
Simulation time 481282772 ps
CPU time 0.73 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 196692 kb
Host smart-f50cf05c-3048-48e4-9067-66a0dd7f2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368207739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3368207739
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4283631968
Short name T236
Test name
Test status
Simulation time 30897733790 ps
CPU time 10.8 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:51:55 PM PDT 24
Peak memory 197096 kb
Host smart-43f698b1-0279-4ad1-be4e-4b8e3ed7b408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283631968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4283631968
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2842643137
Short name T274
Test name
Test status
Simulation time 427427845 ps
CPU time 0.72 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:29 PM PDT 24
Peak memory 191780 kb
Host smart-bcfede7d-5d7b-48ff-b229-afdafd317a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842643137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2842643137
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.491207179
Short name T176
Test name
Test status
Simulation time 114648991546 ps
CPU time 144.99 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:54:12 PM PDT 24
Peak memory 192540 kb
Host smart-3faa2342-f06d-4e1d-aff3-e69d83819412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491207179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.491207179
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2934255536
Short name T204
Test name
Test status
Simulation time 565367855 ps
CPU time 0.81 seconds
Started Aug 01 06:51:39 PM PDT 24
Finished Aug 01 06:51:40 PM PDT 24
Peak memory 196608 kb
Host smart-6031a205-058f-4f56-b41d-e7bed6262b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934255536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2934255536
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1225547545
Short name T214
Test name
Test status
Simulation time 57440405993 ps
CPU time 88.73 seconds
Started Aug 01 06:51:35 PM PDT 24
Finished Aug 01 06:53:04 PM PDT 24
Peak memory 191888 kb
Host smart-13020edf-14d5-4e46-a7a8-78843aa10ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225547545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1225547545
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.154073973
Short name T219
Test name
Test status
Simulation time 526983814 ps
CPU time 1.37 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 191808 kb
Host smart-126cfbf9-c65c-4438-b9b9-18e1ccc28387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154073973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.154073973
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.918278340
Short name T218
Test name
Test status
Simulation time 19766162312 ps
CPU time 14.43 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:45 PM PDT 24
Peak memory 191860 kb
Host smart-d2b2ea76-62dc-4efa-8868-83ffee5513bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918278340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.918278340
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3881878744
Short name T244
Test name
Test status
Simulation time 412902299 ps
CPU time 0.99 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 191800 kb
Host smart-37777024-16d3-48af-96c9-694e280ed867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881878744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3881878744
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2283865855
Short name T75
Test name
Test status
Simulation time 363386843 ps
CPU time 0.69 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 196552 kb
Host smart-2c4568aa-983d-447f-8123-a3aeea728b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283865855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2283865855
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1843803522
Short name T213
Test name
Test status
Simulation time 27871754504 ps
CPU time 43.68 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:52:15 PM PDT 24
Peak memory 191884 kb
Host smart-28c155d7-405f-4506-976d-4e35c453b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843803522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1843803522
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1194813837
Short name T268
Test name
Test status
Simulation time 621071883 ps
CPU time 0.79 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:32 PM PDT 24
Peak memory 191804 kb
Host smart-b57805c8-d2ca-4bd7-bf9f-4ab6d74ad320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194813837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1194813837
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1225265149
Short name T215
Test name
Test status
Simulation time 25985940994 ps
CPU time 8.98 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 196888 kb
Host smart-82bd5686-85e6-4f80-a400-25bf7143f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225265149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1225265149
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3502813883
Short name T11
Test name
Test status
Simulation time 8443114831 ps
CPU time 13.19 seconds
Started Aug 01 06:51:08 PM PDT 24
Finished Aug 01 06:51:22 PM PDT 24
Peak memory 215856 kb
Host smart-a9b792a0-27e2-4393-9899-65a56db8c165
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502813883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3502813883
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1448286941
Short name T272
Test name
Test status
Simulation time 486248363 ps
CPU time 1.29 seconds
Started Aug 01 06:51:10 PM PDT 24
Finished Aug 01 06:51:12 PM PDT 24
Peak memory 196692 kb
Host smart-4b68810a-b932-4946-b4fc-160692b01ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448286941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1448286941
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.13867382
Short name T234
Test name
Test status
Simulation time 21844161819 ps
CPU time 16.55 seconds
Started Aug 01 06:51:31 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 191848 kb
Host smart-de190ebf-b243-474d-ba75-a9a355597c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13867382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.13867382
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3739783096
Short name T267
Test name
Test status
Simulation time 548298964 ps
CPU time 0.78 seconds
Started Aug 01 06:51:38 PM PDT 24
Finished Aug 01 06:51:39 PM PDT 24
Peak memory 191836 kb
Host smart-44b47fc8-63e4-4851-8e40-7abaebdcba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739783096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3739783096
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1191479187
Short name T283
Test name
Test status
Simulation time 40738754097 ps
CPU time 15.66 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 06:52:01 PM PDT 24
Peak memory 191888 kb
Host smart-87af85e9-3f21-4ae9-b368-f941fb8d2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191479187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1191479187
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2291361516
Short name T284
Test name
Test status
Simulation time 466806025 ps
CPU time 0.69 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:43 PM PDT 24
Peak memory 191752 kb
Host smart-f282bbf2-7eb5-4aee-a7c1-c96922f4e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291361516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2291361516
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2919745923
Short name T287
Test name
Test status
Simulation time 46331728444 ps
CPU time 58.18 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:52:38 PM PDT 24
Peak memory 191852 kb
Host smart-1ac0b045-2dd0-45a0-adca-d7bece948a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919745923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2919745923
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.491153146
Short name T285
Test name
Test status
Simulation time 366625178 ps
CPU time 1.1 seconds
Started Aug 01 06:51:41 PM PDT 24
Finished Aug 01 06:51:42 PM PDT 24
Peak memory 191812 kb
Host smart-a03608fa-dd7c-4cb1-af77-f438332f8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491153146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.491153146
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.765041230
Short name T203
Test name
Test status
Simulation time 506849077 ps
CPU time 1.31 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:51:42 PM PDT 24
Peak memory 196632 kb
Host smart-1790c9b6-85df-422f-b1ab-8c36a5b0043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765041230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.765041230
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.973594026
Short name T238
Test name
Test status
Simulation time 2879422886 ps
CPU time 1.61 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 191872 kb
Host smart-a751cb94-05ee-41cb-b59e-a80081112f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973594026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.973594026
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3388426007
Short name T230
Test name
Test status
Simulation time 381927939 ps
CPU time 1.09 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:43 PM PDT 24
Peak memory 191820 kb
Host smart-bcaff615-3f9a-46fd-8cef-cff912fa4803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388426007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3388426007
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2957131038
Short name T52
Test name
Test status
Simulation time 4971084793 ps
CPU time 1.99 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:51:45 PM PDT 24
Peak memory 191896 kb
Host smart-443b6b8b-de46-4219-a7de-f8a2d36c6b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957131038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2957131038
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.857981668
Short name T257
Test name
Test status
Simulation time 363049445 ps
CPU time 1.06 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 191896 kb
Host smart-4c1c04a2-66e9-4bb8-a325-6b7747f1ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857981668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.857981668
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.368959902
Short name T9
Test name
Test status
Simulation time 51709743151 ps
CPU time 41.89 seconds
Started Aug 01 06:51:41 PM PDT 24
Finished Aug 01 06:52:23 PM PDT 24
Peak memory 191852 kb
Host smart-6a2e3894-16fd-4cff-aa68-cfe1bd9fee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368959902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.368959902
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2812743523
Short name T249
Test name
Test status
Simulation time 557517134 ps
CPU time 1.38 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 196648 kb
Host smart-9d473fdc-c83c-493a-8f95-c50a373e10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812743523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2812743523
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1521404685
Short name T187
Test name
Test status
Simulation time 508417306 ps
CPU time 1.3 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 196580 kb
Host smart-1791cc66-98d0-41da-9012-cf41d55b228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521404685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1521404685
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1151534432
Short name T94
Test name
Test status
Simulation time 40131892962 ps
CPU time 52.8 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:52:43 PM PDT 24
Peak memory 191912 kb
Host smart-f5f07136-d30e-4480-ab3c-60705d81ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151534432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1151534432
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2550478888
Short name T243
Test name
Test status
Simulation time 429270109 ps
CPU time 0.73 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:47 PM PDT 24
Peak memory 191664 kb
Host smart-125d3f56-45e2-4da8-816a-4b16bb43122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550478888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2550478888
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.311979170
Short name T277
Test name
Test status
Simulation time 16350591791 ps
CPU time 4.84 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 06:51:54 PM PDT 24
Peak memory 191840 kb
Host smart-a0d74da3-97ec-4989-95f2-07a3b66f3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311979170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.311979170
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1028211199
Short name T221
Test name
Test status
Simulation time 569200597 ps
CPU time 0.94 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:48 PM PDT 24
Peak memory 191836 kb
Host smart-72a7df65-1549-41d1-952a-4fd67d5685c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028211199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1028211199
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3963225223
Short name T216
Test name
Test status
Simulation time 31835871289 ps
CPU time 41.42 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:52:25 PM PDT 24
Peak memory 196844 kb
Host smart-e4af9bdf-4efd-465d-9ef6-91d0874eb5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963225223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3963225223
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3930577740
Short name T232
Test name
Test status
Simulation time 562939978 ps
CPU time 0.74 seconds
Started Aug 01 06:51:40 PM PDT 24
Finished Aug 01 06:51:41 PM PDT 24
Peak memory 191764 kb
Host smart-8afa1ea6-4c28-456f-ae24-e3e47b2c3b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930577740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3930577740
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1360379742
Short name T1
Test name
Test status
Simulation time 34334822465 ps
CPU time 13.68 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 06:52:05 PM PDT 24
Peak memory 196968 kb
Host smart-a89bfea0-cf75-4d39-9643-055fc444722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360379742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1360379742
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1208763766
Short name T74
Test name
Test status
Simulation time 479995142 ps
CPU time 1.23 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:51:44 PM PDT 24
Peak memory 191736 kb
Host smart-2585ff7a-6140-4fdf-a92e-d78e8b48f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208763766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1208763766
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2543427736
Short name T237
Test name
Test status
Simulation time 38508940448 ps
CPU time 54.96 seconds
Started Aug 01 06:51:29 PM PDT 24
Finished Aug 01 06:52:24 PM PDT 24
Peak memory 191876 kb
Host smart-5305f266-bc6d-4f14-b2c7-bb39e46d8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543427736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2543427736
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2485582502
Short name T225
Test name
Test status
Simulation time 552516173 ps
CPU time 0.66 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:08 PM PDT 24
Peak memory 196668 kb
Host smart-052c8ddc-5f8c-4286-8ffe-b21af2c0312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485582502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2485582502
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3907630731
Short name T258
Test name
Test status
Simulation time 28618679819 ps
CPU time 36.11 seconds
Started Aug 01 06:51:17 PM PDT 24
Finished Aug 01 06:51:54 PM PDT 24
Peak memory 196860 kb
Host smart-c84f4397-c966-487d-8740-a8be847fb735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907630731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3907630731
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.559271675
Short name T224
Test name
Test status
Simulation time 425163163 ps
CPU time 1.15 seconds
Started Aug 01 06:51:28 PM PDT 24
Finished Aug 01 06:51:30 PM PDT 24
Peak memory 191788 kb
Host smart-b313e9a6-3379-4053-90b0-bd9b9061ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559271675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.559271675
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.832486844
Short name T184
Test name
Test status
Simulation time 519331403 ps
CPU time 1.29 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 196632 kb
Host smart-1e1c5a21-22df-4bf7-8be6-59b88d823ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832486844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.832486844
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1466367018
Short name T222
Test name
Test status
Simulation time 37942741926 ps
CPU time 7.53 seconds
Started Aug 01 06:51:20 PM PDT 24
Finished Aug 01 06:51:27 PM PDT 24
Peak memory 191876 kb
Host smart-9be52de0-e26a-4712-aba2-f1247dc36be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466367018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1466367018
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3823972101
Short name T40
Test name
Test status
Simulation time 474421368 ps
CPU time 1.28 seconds
Started Aug 01 06:51:12 PM PDT 24
Finished Aug 01 06:51:13 PM PDT 24
Peak memory 196676 kb
Host smart-4239957a-ee03-4bcb-b0a6-36d3a5504949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823972101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3823972101
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3376004720
Short name T276
Test name
Test status
Simulation time 10082927651 ps
CPU time 4.29 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:07 PM PDT 24
Peak memory 196872 kb
Host smart-793a2381-0d34-43fe-a8fe-baa6a062ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376004720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3376004720
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.458030527
Short name T245
Test name
Test status
Simulation time 455669163 ps
CPU time 0.68 seconds
Started Aug 01 06:51:07 PM PDT 24
Finished Aug 01 06:51:08 PM PDT 24
Peak memory 191800 kb
Host smart-bbfbe560-18c7-4fd3-814d-e89d51a62513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458030527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.458030527
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1035178789
Short name T241
Test name
Test status
Simulation time 36022204990 ps
CPU time 47.22 seconds
Started Aug 01 06:51:32 PM PDT 24
Finished Aug 01 06:52:19 PM PDT 24
Peak memory 191864 kb
Host smart-8f18bc6d-296c-48c9-a41d-910aaf9600c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035178789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1035178789
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2357005009
Short name T229
Test name
Test status
Simulation time 417425998 ps
CPU time 0.86 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 196596 kb
Host smart-20e4a8b3-5ae7-420f-b57d-e948b21a37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357005009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2357005009
Directory /workspace/9.aon_timer_smoke/latest
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