Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31112	1		T1	322		T2	10		T3	285
bark[1]	617	1		T8	38		T90	14		T100	51
bark[2]	627	1		T42	226		T83	30		T95	21
bark[3]	330	1		T27	14		T109	21		T94	42
bark[4]	325	1		T39	21		T157	60		T98	21
bark[5]	389	1		T11	5		T42	30		T94	21
bark[6]	396	1		T77	21		T87	21		T103	21
bark[7]	994	1		T31	21		T28	40		T106	35
bark[8]	710	1		T39	30		T41	21		T109	466
bark[9]	1119	1		T11	787		T77	21		T126	14
bark[10]	895	1		T9	26		T45	14		T177	21
bark[11]	426	1		T9	82		T20	42		T83	21
bark[12]	518	1		T31	21		T24	21		T39	21
bark[13]	215	1		T25	21		T109	47		T107	21
bark[14]	194	1		T29	21		T182	14		T161	84
bark[15]	551	1		T9	21		T109	35		T77	30
bark[16]	413	1		T1	21		T40	49		T134	21
bark[17]	568	1		T12	271		T29	21		T41	7
bark[18]	356	1		T11	26		T51	14		T21	14
bark[19]	208	1		T50	14		T24	77		T95	21
bark[20]	582	1		T8	45		T107	42		T83	33
bark[21]	798	1		T39	21		T180	14		T77	21
bark[22]	191	1		T103	26		T191	14		T153	95
bark[23]	445	1		T20	21		T83	21		T92	54
bark[24]	1143	1		T9	21		T28	21		T42	43
bark[25]	586	1		T39	109		T40	5		T41	21
bark[26]	156	1		T20	21		T77	31		T106	21
bark[27]	594	1		T8	21		T30	14		T20	21
bark[28]	285	1		T20	35		T82	106		T100	21
bark[29]	1522	1		T1	238		T31	21		T49	14
bark[30]	599	1		T52	14		T25	77		T161	19
bark[31]	324	1		T46	14		T87	30		T103	35
bark_0	5016	1		T1	35		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30932	1		T1	271		T2	9		T3	284
bite[1]	1268	1		T11	786		T77	30		T91	13
bite[2]	498	1		T29	21		T109	49		T77	42
bite[3]	113	1		T51	13		T41	21		T84	21
bite[4]	811	1		T9	21		T25	63		T39	21
bite[5]	239	1		T52	13		T100	13		T119	21
bite[6]	276	1		T42	30		T107	42		T87	30
bite[7]	1138	1		T45	13		T12	270		T39	21
bite[8]	615	1		T1	21		T42	225		T113	13
bite[9]	614	1		T46	13		T39	259		T111	43
bite[10]	205	1		T20	55		T54	80		T105	49
bite[11]	353	1		T31	21		T109	34		T106	69
bite[12]	725	1		T182	13		T77	21		T82	21
bite[13]	662	1		T126	13		T82	105		T95	21
bite[14]	516	1		T188	13		T82	6		T92	54
bite[15]	199	1		T8	38		T21	13		T134	21
bite[16]	838	1		T111	21		T109	465		T161	18
bite[17]	530	1		T11	4		T24	76		T99	21
bite[18]	202	1		T31	21		T94	21		T132	21
bite[19]	521	1		T24	21		T94	21		T106	21
bite[20]	930	1		T1	47		T9	21		T11	25
bite[21]	501	1		T27	13		T28	40		T49	13
bite[22]	325	1		T8	44		T111	21		T142	13
bite[23]	463	1		T161	21		T107	30		T159	25
bite[24]	1228	1		T30	13		T20	42		T40	48
bite[25]	297	1		T28	21		T47	13		T20	21
bite[26]	274	1		T39	138		T79	6		T104	21
bite[27]	711	1		T20	21		T25	21		T161	84
bite[28]	411	1		T1	237		T9	26		T20	38
bite[29]	259	1		T29	21		T90	13		T94	21
bite[30]	464	1		T9	82		T50	13		T41	6
bite[31]	551	1		T8	21		T31	21		T41	21
bite_0	5535	1		T1	40		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45307	1		T1	616		T2	17		T3	264
auto[1]	7897	1		T3	28		T28	78		T197	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	731	1		T8	66		T31	19		T12	134
prescale[1]	832	1		T3	63		T12	19		T24	46
prescale[2]	1409	1		T3	28		T11	78		T28	28
prescale[3]	1383	1		T11	19		T12	78		T29	36
prescale[4]	1081	1		T11	68		T12	45		T24	75
prescale[5]	901	1		T3	19		T8	61		T11	159
prescale[6]	581	1		T11	32		T29	59		T39	53
prescale[7]	811	1		T1	80		T8	28		T11	40
prescale[8]	1343	1		T1	23		T12	19		T24	19
prescale[9]	718	1		T9	19		T11	2		T12	80
prescale[10]	751	1		T18	40		T24	19		T42	2
prescale[11]	900	1		T31	23		T11	84		T24	38
prescale[12]	697	1		T1	91		T12	161		T29	19
prescale[13]	734	1		T1	19		T29	60		T20	23
prescale[14]	605	1		T10	9		T12	2		T29	97
prescale[15]	759	1		T3	19		T12	28		T29	98
prescale[16]	451	1		T29	41		T109	2		T198	9
prescale[17]	364	1		T9	28		T11	2		T29	28
prescale[18]	961	1		T11	167		T12	19		T28	19
prescale[19]	704	1		T1	4		T8	75		T11	2
prescale[20]	686	1		T1	28		T41	2		T42	208
prescale[21]	619	1		T1	19		T11	19		T29	19
prescale[22]	847	1		T43	9		T31	23		T29	19
prescale[23]	735	1		T12	2		T29	87		T39	19
prescale[24]	1130	1		T31	19		T11	28		T29	68
prescale[25]	737	1		T6	9		T12	2		T29	54
prescale[26]	530	1		T29	28		T40	2		T41	2
prescale[27]	713	1		T9	28		T29	127		T177	19
prescale[28]	795	1		T12	24		T20	28		T41	67
prescale[29]	896	1		T3	19		T18	2		T20	57
prescale[30]	997	1		T1	40		T9	73		T11	58
prescale[31]	666	1		T12	21		T28	19		T29	33
prescale_0	27137	1		T1	312		T2	17		T3	144

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39967	1		T1	559		T2	17		T3	176
auto[1]	13237	1		T1	57		T3	116		T6	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53204	1		T1	616		T2	17		T3	292

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	32106	1		T1	322		T2	12		T3	266
wkup[1]	319	1		T1	21		T11	30		T39	30
wkup[2]	145	1		T29	21		T98	26		T89	21
wkup[3]	84	1		T161	21		T93	21		T96	21
wkup[4]	250	1		T159	21		T87	21		T54	42
wkup[5]	208	1		T11	21		T39	35		T84	29
wkup[6]	241	1		T1	39		T24	30		T90	15
wkup[7]	378	1		T30	15		T29	21		T109	21
wkup[8]	261	1		T9	26		T12	21		T29	35
wkup[9]	268	1		T20	15		T94	21		T106	21
wkup[10]	226	1		T45	15		T77	21		T85	26
wkup[11]	331	1		T77	21		T106	21		T107	30
wkup[12]	303	1		T1	21		T11	21		T20	21
wkup[13]	356	1		T9	21		T12	42		T29	47
wkup[14]	218	1		T159	21		T95	21		T79	21
wkup[15]	410	1		T8	26		T12	60		T29	26
wkup[16]	237	1		T77	24		T83	21		T129	21
wkup[17]	380	1		T12	42		T18	30		T111	21
wkup[18]	328	1		T29	15		T39	21		T77	31
wkup[19]	309	1		T29	21		T39	21		T109	21
wkup[20]	276	1		T9	21		T12	21		T29	21
wkup[21]	338	1		T9	21		T109	21		T77	21
wkup[22]	234	1		T12	21		T29	21		T109	21
wkup[23]	238	1		T49	15		T106	21		T159	21
wkup[24]	240	1		T1	21		T24	15		T100	30
wkup[25]	202	1		T1	26		T8	20		T11	21
wkup[26]	298	1		T42	21		T99	30		T82	21
wkup[27]	215	1		T1	21		T9	21		T28	21
wkup[28]	297	1		T8	42		T31	21		T11	21
wkup[29]	408	1		T39	30		T180	15		T42	30
wkup[30]	281	1		T31	21		T20	42		T134	21
wkup[31]	314	1		T11	68		T109	15		T83	30
wkup[32]	204	1		T29	21		T25	21		T39	21
wkup[33]	273	1		T46	15		T29	60		T25	21
wkup[34]	207	1		T1	21		T12	21		T109	21
wkup[35]	137	1		T135	15		T79	21		T129	8
wkup[36]	369	1		T9	21		T11	8		T77	21
wkup[37]	408	1		T1	35		T28	21		T51	15
wkup[38]	418	1		T29	30		T109	30		T94	21
wkup[39]	310	1		T24	21		T87	21		T82	8
wkup[40]	336	1		T11	21		T47	15		T39	21
wkup[41]	264	1		T1	30		T27	15		T29	21
wkup[42]	275	1		T77	21		T161	42		T159	21
wkup[43]	231	1		T18	21		T39	21		T99	21
wkup[44]	188	1		T11	6		T42	26		T118	21
wkup[45]	168	1		T11	21		T25	21		T39	21
wkup[46]	140	1		T24	21		T42	30		T157	21
wkup[47]	141	1		T11	21		T183	21		T84	21
wkup[48]	278	1		T11	30		T130	30		T119	21
wkup[49]	248	1		T12	21		T109	21		T146	21
wkup[50]	311	1		T21	15		T25	21		T39	21
wkup[51]	353	1		T29	21		T42	21		T94	21
wkup[52]	279	1		T3	21		T42	42		T107	15
wkup[53]	251	1		T50	15		T82	21		T100	21
wkup[54]	383	1		T1	26		T29	21		T39	21
wkup[55]	266	1		T24	21		T77	21		T161	20
wkup[56]	323	1		T12	21		T20	21		T94	21
wkup[57]	455	1		T52	15		T20	21		T40	44
wkup[58]	291	1		T1	8		T29	21		T40	6
wkup[59]	229	1		T11	47		T24	21		T77	21
wkup[60]	272	1		T155	15		T82	21		T129	21
wkup[61]	168	1		T8	21		T77	21		T177	21
wkup[62]	259	1		T41	8		T77	31		T161	30
wkup[63]	174	1		T18	21		T111	21		T54	6
wkup_0	3896	1		T1	25		T2	5		T3	5