Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.92 99.33 93.67 100.00 98.40 99.51 48.64


Total test records in report: 427
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T145 /workspace/coverage/default/40.aon_timer_stress_all.1153676499 Aug 02 05:19:02 PM PDT 24 Aug 02 05:24:31 PM PDT 24 241925656820 ps
T165 /workspace/coverage/default/19.aon_timer_jump.4271676002 Aug 02 05:18:21 PM PDT 24 Aug 02 05:18:22 PM PDT 24 360261125 ps
T289 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3918087820 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:50 PM PDT 24 381783210 ps
T290 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2975345946 Aug 02 05:19:12 PM PDT 24 Aug 02 05:19:13 PM PDT 24 494775795 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1154535980 Aug 02 05:18:39 PM PDT 24 Aug 02 05:18:40 PM PDT 24 531484639 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1440958699 Aug 02 05:18:37 PM PDT 24 Aug 02 05:18:38 PM PDT 24 524454842 ps
T32 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.154739267 Aug 02 05:18:44 PM PDT 24 Aug 02 05:18:49 PM PDT 24 1269600190 ps
T33 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1345519790 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:39 PM PDT 24 616951674 ps
T38 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3520967639 Aug 02 05:18:36 PM PDT 24 Aug 02 05:19:04 PM PDT 24 7575322217 ps
T34 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3408595069 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:50 PM PDT 24 414711788 ps
T200 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1664244393 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:52 PM PDT 24 566849535 ps
T199 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1763264505 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:42 PM PDT 24 468226018 ps
T293 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2489319648 Aug 02 05:19:15 PM PDT 24 Aug 02 05:19:15 PM PDT 24 323821369 ps
T201 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.111603512 Aug 02 05:18:50 PM PDT 24 Aug 02 05:18:51 PM PDT 24 552428702 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.752882401 Aug 02 05:18:33 PM PDT 24 Aug 02 05:18:34 PM PDT 24 872416933 ps
T294 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4067550263 Aug 02 05:19:09 PM PDT 24 Aug 02 05:19:10 PM PDT 24 522639917 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.287487394 Aug 02 05:18:49 PM PDT 24 Aug 02 05:19:00 PM PDT 24 7228126700 ps
T296 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1638309627 Aug 02 05:19:05 PM PDT 24 Aug 02 05:19:06 PM PDT 24 578559243 ps
T297 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2790489364 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:41 PM PDT 24 533158226 ps
T298 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.354416440 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:04 PM PDT 24 515972967 ps
T299 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3727040034 Aug 02 05:18:50 PM PDT 24 Aug 02 05:18:52 PM PDT 24 506979827 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.595401469 Aug 02 05:19:13 PM PDT 24 Aug 02 05:19:18 PM PDT 24 1487676467 ps
T71 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.275975730 Aug 02 05:19:11 PM PDT 24 Aug 02 05:19:13 PM PDT 24 2771701888 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4219331967 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:44 PM PDT 24 659092390 ps
T35 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2555990404 Aug 02 05:18:54 PM PDT 24 Aug 02 05:18:58 PM PDT 24 8476334800 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1440071203 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:45 PM PDT 24 347996214 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2129496885 Aug 02 05:18:59 PM PDT 24 Aug 02 05:18:59 PM PDT 24 433542232 ps
T302 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1595032569 Aug 02 05:19:04 PM PDT 24 Aug 02 05:19:05 PM PDT 24 396031386 ps
T73 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3864238941 Aug 02 05:18:37 PM PDT 24 Aug 02 05:18:38 PM PDT 24 330306255 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1041129863 Aug 02 05:18:49 PM PDT 24 Aug 02 05:18:51 PM PDT 24 474574257 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.224939523 Aug 02 05:18:57 PM PDT 24 Aug 02 05:18:58 PM PDT 24 409604894 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3310704014 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:43 PM PDT 24 481397037 ps
T306 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1420409726 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:51 PM PDT 24 429990080 ps
T36 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.342421321 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:56 PM PDT 24 8156255101 ps
T307 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.963346182 Aug 02 05:18:58 PM PDT 24 Aug 02 05:18:59 PM PDT 24 483379868 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2538445383 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:46 PM PDT 24 515138362 ps
T309 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1872372605 Aug 02 05:18:49 PM PDT 24 Aug 02 05:18:50 PM PDT 24 304519491 ps
T310 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3753045835 Aug 02 05:19:06 PM PDT 24 Aug 02 05:19:07 PM PDT 24 292541036 ps
T311 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2931770898 Aug 02 05:18:58 PM PDT 24 Aug 02 05:18:59 PM PDT 24 269835780 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1201331538 Aug 02 05:18:47 PM PDT 24 Aug 02 05:18:47 PM PDT 24 350677201 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1934741391 Aug 02 05:18:25 PM PDT 24 Aug 02 05:18:26 PM PDT 24 1227739506 ps
T312 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4291517548 Aug 02 05:19:09 PM PDT 24 Aug 02 05:19:10 PM PDT 24 447225216 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.756578727 Aug 02 05:18:45 PM PDT 24 Aug 02 05:18:46 PM PDT 24 950813132 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2538818380 Aug 02 05:18:28 PM PDT 24 Aug 02 05:18:29 PM PDT 24 400929502 ps
T315 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1065097533 Aug 02 05:18:59 PM PDT 24 Aug 02 05:19:01 PM PDT 24 469227402 ps
T316 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1615880438 Aug 02 05:19:08 PM PDT 24 Aug 02 05:19:09 PM PDT 24 372328641 ps
T317 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4003388615 Aug 02 05:19:07 PM PDT 24 Aug 02 05:19:08 PM PDT 24 514933430 ps
T318 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3868509942 Aug 02 05:19:46 PM PDT 24 Aug 02 05:19:47 PM PDT 24 497155005 ps
T319 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.89103891 Aug 02 05:18:39 PM PDT 24 Aug 02 05:18:40 PM PDT 24 345920895 ps
T320 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2984981907 Aug 02 05:19:05 PM PDT 24 Aug 02 05:19:06 PM PDT 24 429154303 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3589742044 Aug 02 05:18:57 PM PDT 24 Aug 02 05:18:59 PM PDT 24 418204030 ps
T37 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2629937160 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:58 PM PDT 24 8010718811 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.974387768 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:55 PM PDT 24 13550320524 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3315121628 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:43 PM PDT 24 5046069489 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3544588092 Aug 02 05:19:15 PM PDT 24 Aug 02 05:19:19 PM PDT 24 1258502691 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.423333545 Aug 02 05:18:33 PM PDT 24 Aug 02 05:18:34 PM PDT 24 311411420 ps
T192 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2204690558 Aug 02 05:18:50 PM PDT 24 Aug 02 05:18:57 PM PDT 24 4214042417 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1045994428 Aug 02 05:18:57 PM PDT 24 Aug 02 05:18:58 PM PDT 24 413390600 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1569254704 Aug 02 05:18:30 PM PDT 24 Aug 02 05:18:31 PM PDT 24 369889057 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.176590471 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:39 PM PDT 24 481885158 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1534091551 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:43 PM PDT 24 451945984 ps
T328 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.215854450 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:52 PM PDT 24 372017409 ps
T329 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.696717815 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:50 PM PDT 24 573356533 ps
T330 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3496420713 Aug 02 05:18:54 PM PDT 24 Aug 02 05:18:55 PM PDT 24 445755242 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2118676231 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:39 PM PDT 24 737972989 ps
T65 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.438251895 Aug 02 05:19:00 PM PDT 24 Aug 02 05:19:01 PM PDT 24 389927957 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2786098583 Aug 02 05:18:28 PM PDT 24 Aug 02 05:18:29 PM PDT 24 521474060 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2137157711 Aug 02 05:18:49 PM PDT 24 Aug 02 05:18:49 PM PDT 24 357100647 ps
T75 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.670590134 Aug 02 05:19:06 PM PDT 24 Aug 02 05:19:08 PM PDT 24 3092190837 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.694963097 Aug 02 05:18:57 PM PDT 24 Aug 02 05:19:00 PM PDT 24 470874965 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3369165037 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:49 PM PDT 24 431016701 ps
T335 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4067342636 Aug 02 05:18:59 PM PDT 24 Aug 02 05:19:00 PM PDT 24 324324667 ps
T336 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2467209914 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:04 PM PDT 24 292869099 ps
T337 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1501072156 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:52 PM PDT 24 474757307 ps
T66 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3806843456 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:43 PM PDT 24 430980733 ps
T76 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1187595216 Aug 02 05:19:01 PM PDT 24 Aug 02 05:19:02 PM PDT 24 544603344 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.20121101 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:43 PM PDT 24 345076759 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.495814541 Aug 02 05:18:34 PM PDT 24 Aug 02 05:18:35 PM PDT 24 751766948 ps
T193 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3104678554 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:45 PM PDT 24 4148487581 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.207864363 Aug 02 05:18:35 PM PDT 24 Aug 02 05:18:36 PM PDT 24 456405516 ps
T341 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1894875790 Aug 02 05:19:12 PM PDT 24 Aug 02 05:19:13 PM PDT 24 455365647 ps
T342 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1381505565 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:48 PM PDT 24 581403896 ps
T67 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3422777199 Aug 02 05:19:28 PM PDT 24 Aug 02 05:19:30 PM PDT 24 459258834 ps
T343 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4256715346 Aug 02 05:18:45 PM PDT 24 Aug 02 05:18:46 PM PDT 24 400781957 ps
T344 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.309694198 Aug 02 05:18:45 PM PDT 24 Aug 02 05:18:46 PM PDT 24 430111381 ps
T345 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3470270545 Aug 02 05:18:44 PM PDT 24 Aug 02 05:18:46 PM PDT 24 689328438 ps
T346 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1465355506 Aug 02 05:18:50 PM PDT 24 Aug 02 05:18:51 PM PDT 24 527380261 ps
T347 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1347644497 Aug 02 05:19:05 PM PDT 24 Aug 02 05:19:06 PM PDT 24 473837258 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2189779472 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:44 PM PDT 24 476708731 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3994058309 Aug 02 05:19:06 PM PDT 24 Aug 02 05:19:07 PM PDT 24 314384451 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.684547594 Aug 02 05:18:53 PM PDT 24 Aug 02 05:18:56 PM PDT 24 1812786913 ps
T350 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3507770467 Aug 02 05:19:00 PM PDT 24 Aug 02 05:19:02 PM PDT 24 756318874 ps
T351 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3584262655 Aug 02 05:19:10 PM PDT 24 Aug 02 05:19:11 PM PDT 24 1195443701 ps
T352 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3999258790 Aug 02 05:19:05 PM PDT 24 Aug 02 05:19:05 PM PDT 24 316680719 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.904794535 Aug 02 05:18:47 PM PDT 24 Aug 02 05:18:49 PM PDT 24 618851610 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1537816267 Aug 02 05:18:52 PM PDT 24 Aug 02 05:18:54 PM PDT 24 472906847 ps
T195 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1495747375 Aug 02 05:18:52 PM PDT 24 Aug 02 05:18:57 PM PDT 24 8062823007 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3124129504 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:40 PM PDT 24 1098717573 ps
T356 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.210973292 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:06 PM PDT 24 2062851839 ps
T357 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1638720953 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:05 PM PDT 24 4388871021 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2564564185 Aug 02 05:18:52 PM PDT 24 Aug 02 05:18:58 PM PDT 24 8194240547 ps
T359 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4074970271 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:04 PM PDT 24 452056334 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1004675267 Aug 02 05:18:32 PM PDT 24 Aug 02 05:18:33 PM PDT 24 535912308 ps
T361 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1374108038 Aug 02 05:18:55 PM PDT 24 Aug 02 05:18:56 PM PDT 24 513003885 ps
T362 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.483861439 Aug 02 05:19:09 PM PDT 24 Aug 02 05:19:10 PM PDT 24 355182568 ps
T363 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2096991336 Aug 02 05:18:35 PM PDT 24 Aug 02 05:18:36 PM PDT 24 350380395 ps
T364 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2203995686 Aug 02 05:19:01 PM PDT 24 Aug 02 05:19:02 PM PDT 24 374306314 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3107729808 Aug 02 05:18:47 PM PDT 24 Aug 02 05:18:50 PM PDT 24 563197583 ps
T366 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1825215971 Aug 02 05:18:55 PM PDT 24 Aug 02 05:18:59 PM PDT 24 2195769755 ps
T367 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2264890902 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:43 PM PDT 24 1505844714 ps
T368 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1904407047 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:04 PM PDT 24 348214615 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2734943552 Aug 02 05:18:39 PM PDT 24 Aug 02 05:18:40 PM PDT 24 410544171 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3401508123 Aug 02 05:18:59 PM PDT 24 Aug 02 05:19:05 PM PDT 24 11252335777 ps
T370 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3925150908 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:44 PM PDT 24 4933831715 ps
T196 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2830284613 Aug 02 05:18:47 PM PDT 24 Aug 02 05:18:49 PM PDT 24 4106890098 ps
T371 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2682531087 Aug 02 05:19:01 PM PDT 24 Aug 02 05:19:04 PM PDT 24 1896677433 ps
T194 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4044341404 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:40 PM PDT 24 3958763038 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3657603305 Aug 02 05:18:32 PM PDT 24 Aug 02 05:18:34 PM PDT 24 667341543 ps
T372 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2492235595 Aug 02 05:18:46 PM PDT 24 Aug 02 05:18:48 PM PDT 24 528178804 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1068271771 Aug 02 05:18:30 PM PDT 24 Aug 02 05:18:31 PM PDT 24 427116826 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.374985182 Aug 02 05:18:59 PM PDT 24 Aug 02 05:19:01 PM PDT 24 328544194 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1834897782 Aug 02 05:18:29 PM PDT 24 Aug 02 05:18:30 PM PDT 24 343926883 ps
T375 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1814451693 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:55 PM PDT 24 3800378802 ps
T376 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.549606042 Aug 02 05:19:04 PM PDT 24 Aug 02 05:19:05 PM PDT 24 468493258 ps
T377 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3737512309 Aug 02 05:18:52 PM PDT 24 Aug 02 05:18:54 PM PDT 24 791044880 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1590702470 Aug 02 05:18:39 PM PDT 24 Aug 02 05:18:47 PM PDT 24 2203052633 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3677392106 Aug 02 05:18:28 PM PDT 24 Aug 02 05:18:31 PM PDT 24 8705881741 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4173939775 Aug 02 05:18:55 PM PDT 24 Aug 02 05:18:58 PM PDT 24 4588326467 ps
T381 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2202978386 Aug 02 05:19:13 PM PDT 24 Aug 02 05:19:14 PM PDT 24 394050563 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1857472627 Aug 02 05:18:36 PM PDT 24 Aug 02 05:18:39 PM PDT 24 2527483952 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2400840545 Aug 02 05:18:40 PM PDT 24 Aug 02 05:18:41 PM PDT 24 345780886 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3365301196 Aug 02 05:18:39 PM PDT 24 Aug 02 05:18:40 PM PDT 24 538282432 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3960007855 Aug 02 05:18:44 PM PDT 24 Aug 02 05:18:46 PM PDT 24 517699274 ps
T385 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1170124916 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:49 PM PDT 24 402907552 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.157215056 Aug 02 05:18:31 PM PDT 24 Aug 02 05:18:31 PM PDT 24 363825074 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2459972643 Aug 02 05:18:40 PM PDT 24 Aug 02 05:18:41 PM PDT 24 472657624 ps
T388 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4018815081 Aug 02 05:19:02 PM PDT 24 Aug 02 05:19:03 PM PDT 24 478087567 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3589553809 Aug 02 05:18:37 PM PDT 24 Aug 02 05:18:40 PM PDT 24 1064449267 ps
T390 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.976108079 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:10 PM PDT 24 7789739767 ps
T391 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2850093776 Aug 02 05:19:09 PM PDT 24 Aug 02 05:19:11 PM PDT 24 1089160938 ps
T392 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2276583583 Aug 02 05:18:54 PM PDT 24 Aug 02 05:19:00 PM PDT 24 1969479698 ps
T393 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.598590192 Aug 02 05:18:57 PM PDT 24 Aug 02 05:18:58 PM PDT 24 477168135 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3297614828 Aug 02 05:18:28 PM PDT 24 Aug 02 05:18:39 PM PDT 24 392446547 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2480453848 Aug 02 05:18:54 PM PDT 24 Aug 02 05:18:56 PM PDT 24 2847673352 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1713080635 Aug 02 05:18:44 PM PDT 24 Aug 02 05:18:45 PM PDT 24 490138453 ps
T397 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1140049661 Aug 02 05:19:00 PM PDT 24 Aug 02 05:19:01 PM PDT 24 271007096 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3750102672 Aug 02 05:18:42 PM PDT 24 Aug 02 05:18:44 PM PDT 24 512689945 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2864049529 Aug 02 05:19:17 PM PDT 24 Aug 02 05:19:19 PM PDT 24 582356214 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2513709767 Aug 02 05:18:58 PM PDT 24 Aug 02 05:19:00 PM PDT 24 2460529598 ps
T401 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2416484308 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:54 PM PDT 24 2305255952 ps
T402 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3420459954 Aug 02 05:18:46 PM PDT 24 Aug 02 05:18:48 PM PDT 24 433756477 ps
T403 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2603601301 Aug 02 05:18:56 PM PDT 24 Aug 02 05:18:57 PM PDT 24 318139775 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3120375942 Aug 02 05:18:45 PM PDT 24 Aug 02 05:18:51 PM PDT 24 4313851173 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.640831641 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:45 PM PDT 24 545479026 ps
T406 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2498018614 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:49 PM PDT 24 463971608 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1370094993 Aug 02 05:19:04 PM PDT 24 Aug 02 05:19:06 PM PDT 24 1505295664 ps
T408 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4123473405 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:51 PM PDT 24 382490597 ps
T409 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.551321368 Aug 02 05:19:01 PM PDT 24 Aug 02 05:19:02 PM PDT 24 434900214 ps
T410 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.455989167 Aug 02 05:18:43 PM PDT 24 Aug 02 05:18:45 PM PDT 24 4308662574 ps
T411 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3061504974 Aug 02 05:19:05 PM PDT 24 Aug 02 05:19:06 PM PDT 24 478254298 ps
T412 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3479397605 Aug 02 05:18:41 PM PDT 24 Aug 02 05:18:42 PM PDT 24 357957228 ps
T413 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.394685490 Aug 02 05:19:03 PM PDT 24 Aug 02 05:19:04 PM PDT 24 458243394 ps
T414 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3413154330 Aug 02 05:19:04 PM PDT 24 Aug 02 05:19:05 PM PDT 24 491548024 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2964067939 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:38 PM PDT 24 444562946 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2707281130 Aug 02 05:18:38 PM PDT 24 Aug 02 05:18:53 PM PDT 24 9196685140 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1330944260 Aug 02 05:18:48 PM PDT 24 Aug 02 05:18:54 PM PDT 24 645215605 ps
T417 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2270790547 Aug 02 05:18:49 PM PDT 24 Aug 02 05:18:50 PM PDT 24 540672305 ps
T418 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1534284546 Aug 02 05:18:35 PM PDT 24 Aug 02 05:18:36 PM PDT 24 584512106 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.596825154 Aug 02 05:18:30 PM PDT 24 Aug 02 05:18:32 PM PDT 24 425341051 ps
T420 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.234258429 Aug 02 05:18:29 PM PDT 24 Aug 02 05:18:30 PM PDT 24 471068978 ps
T421 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1327918564 Aug 02 05:19:04 PM PDT 24 Aug 02 05:19:06 PM PDT 24 451598201 ps
T422 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2680511067 Aug 02 05:18:57 PM PDT 24 Aug 02 05:18:59 PM PDT 24 440663124 ps
T423 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2408134331 Aug 02 05:18:56 PM PDT 24 Aug 02 05:19:04 PM PDT 24 8706824428 ps
T424 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4017569072 Aug 02 05:18:51 PM PDT 24 Aug 02 05:18:52 PM PDT 24 342327750 ps
T425 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.357209808 Aug 02 05:18:33 PM PDT 24 Aug 02 05:18:34 PM PDT 24 1065452107 ps
T426 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2719701187 Aug 02 05:18:56 PM PDT 24 Aug 02 05:18:57 PM PDT 24 492662827 ps
T427 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1955175695 Aug 02 05:18:53 PM PDT 24 Aug 02 05:18:54 PM PDT 24 323492255 ps

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2203383525
Short name T1
Test name
Test status
Simulation time 163375316973 ps
CPU time 224.96 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 208420 kb
Host smart-e2328370-824f-4341-b5ee-aa60a2b6bc79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203383525 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2203383525
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1998504515
Short name T12
Test name
Test status
Simulation time 299733349925 ps
CPU time 610.15 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:28:41 PM PDT 24
Peak memory 205256 kb
Host smart-2309bcab-37ef-4755-8ead-21ce90f140e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998504515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1998504515
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2486092727
Short name T13
Test name
Test status
Simulation time 3924627707 ps
CPU time 1.96 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 215584 kb
Host smart-9c21b0f6-2805-4b89-951e-a310c2be6f58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486092727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2486092727
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2114974835
Short name T9
Test name
Test status
Simulation time 135949175173 ps
CPU time 58.94 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:19:32 PM PDT 24
Peak memory 192860 kb
Host smart-d3a8b6e4-ec51-4537-ba01-7b4fe97d4d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114974835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2114974835
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3922830528
Short name T89
Test name
Test status
Simulation time 86861122024 ps
CPU time 932.33 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 211324 kb
Host smart-4ff74963-870e-4f03-a14d-aadee74bef8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922830528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3922830528
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.28940126
Short name T77
Test name
Test status
Simulation time 30718286558 ps
CPU time 230.64 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 198500 kb
Host smart-838fe80b-134a-41b4-8ec4-76b41b7203a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940126 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.28940126
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1123467463
Short name T96
Test name
Test status
Simulation time 48844170289 ps
CPU time 510.74 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:27:15 PM PDT 24
Peak memory 214116 kb
Host smart-cb987087-e448-4ec5-9152-75ee131819e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123467463 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1123467463
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3943524160
Short name T39
Test name
Test status
Simulation time 17161202192 ps
CPU time 116.18 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:20:43 PM PDT 24
Peak memory 206824 kb
Host smart-551b6e2c-d5df-4bb4-a838-2e0fa65eedff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943524160 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3943524160
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3520967639
Short name T38
Test name
Test status
Simulation time 7575322217 ps
CPU time 27.84 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 195828 kb
Host smart-056a2b24-c728-4ea6-8163-1275b60cd6f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520967639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3520967639
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3590165192
Short name T55
Test name
Test status
Simulation time 183321531539 ps
CPU time 769.8 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:31:03 PM PDT 24
Peak memory 207608 kb
Host smart-2b26623b-f1d1-4cc1-9380-7f1545c2e6ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590165192 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3590165192
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2275210363
Short name T85
Test name
Test status
Simulation time 94661682513 ps
CPU time 185.52 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 206728 kb
Host smart-94c2e754-2ed7-4e12-8784-ae2eb6214856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275210363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2275210363
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4240129537
Short name T29
Test name
Test status
Simulation time 76179019146 ps
CPU time 515.38 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:27:01 PM PDT 24
Peak memory 203160 kb
Host smart-36d10fcb-ef39-4a3c-9a16-230aaf494d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240129537 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4240129537
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2251643321
Short name T102
Test name
Test status
Simulation time 21269605508 ps
CPU time 218.43 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:21:57 PM PDT 24
Peak memory 198540 kb
Host smart-ea9a1f2e-7309-4898-8ea1-c9683734edfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251643321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2251643321
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3679976035
Short name T20
Test name
Test status
Simulation time 83109568722 ps
CPU time 24.43 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 192992 kb
Host smart-624cdbc8-415e-4987-8644-0f59664688c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679976035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3679976035
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.833870924
Short name T97
Test name
Test status
Simulation time 83676548373 ps
CPU time 640.22 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 206652 kb
Host smart-b0b96461-8bf7-474a-97fb-c26b3de8c62d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833870924 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.833870924
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3202402352
Short name T84
Test name
Test status
Simulation time 109448657773 ps
CPU time 61.23 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:19:40 PM PDT 24
Peak memory 198840 kb
Host smart-a5c396ce-86a6-48b0-b4c0-6a49b7eab696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202402352 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3202402352
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.145584971
Short name T107
Test name
Test status
Simulation time 249676391717 ps
CPU time 183.28 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:21:31 PM PDT 24
Peak memory 192996 kb
Host smart-991b4a6f-d742-4b66-bfef-46608756b007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145584971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.145584971
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.918225308
Short name T98
Test name
Test status
Simulation time 70819807199 ps
CPU time 94.33 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:19:46 PM PDT 24
Peak memory 192908 kb
Host smart-421032fd-bf88-4a6b-9135-bb22b911042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918225308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.918225308
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2425171463
Short name T93
Test name
Test status
Simulation time 420950970493 ps
CPU time 733.85 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:30:26 PM PDT 24
Peak memory 207784 kb
Host smart-1c0e0656-919c-4ec6-bd23-eb605ae38127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425171463 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2425171463
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.833897773
Short name T116
Test name
Test status
Simulation time 138322761295 ps
CPU time 370.98 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:24:42 PM PDT 24
Peak memory 211016 kb
Host smart-74baed82-0a2d-4a63-bd1b-69ba5092aa2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833897773 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.833897773
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2520078940
Short name T121
Test name
Test status
Simulation time 22838859331 ps
CPU time 10.37 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 191868 kb
Host smart-9adea375-5be1-44fd-80f7-1d49bb29bb6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520078940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2520078940
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.603167673
Short name T132
Test name
Test status
Simulation time 80216910086 ps
CPU time 130.77 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:20:39 PM PDT 24
Peak memory 192908 kb
Host smart-f7609c77-d566-43a9-b5ab-f556ced3c2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603167673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.603167673
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3296494303
Short name T120
Test name
Test status
Simulation time 349282310681 ps
CPU time 865.17 seconds
Started Aug 02 05:18:45 PM PDT 24
Finished Aug 02 05:33:10 PM PDT 24
Peak memory 214820 kb
Host smart-f395a839-9a51-4508-acac-deab2edc097e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296494303 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3296494303
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2725915031
Short name T99
Test name
Test status
Simulation time 56190183433 ps
CPU time 22.29 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 193044 kb
Host smart-7eb811cc-6f28-4a00-a714-5ddc004f1caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725915031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2725915031
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.829372918
Short name T129
Test name
Test status
Simulation time 58730264515 ps
CPU time 461.85 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:26:07 PM PDT 24
Peak memory 201708 kb
Host smart-7dab7015-e45b-4932-969d-59b11290bf06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829372918 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.829372918
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.78439580
Short name T80
Test name
Test status
Simulation time 365680060362 ps
CPU time 918.54 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 214904 kb
Host smart-85a9c703-5a05-4de0-9d98-e3fb2c569ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78439580 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.78439580
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1117343072
Short name T79
Test name
Test status
Simulation time 793024052733 ps
CPU time 1003.53 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 214948 kb
Host smart-528f1e3f-d724-4426-a5b2-5aef396680c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117343072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1117343072
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.342421321
Short name T36
Test name
Test status
Simulation time 8156255101 ps
CPU time 13.21 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:56 PM PDT 24
Peak memory 198292 kb
Host smart-e21e85fd-c65b-4c79-b561-d717e99e395c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342421321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.342421321
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4057440353
Short name T106
Test name
Test status
Simulation time 89794991498 ps
CPU time 14.92 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 192928 kb
Host smart-e5eb368c-f1d6-44ea-bbe9-6f0e9192a8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057440353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4057440353
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4102901995
Short name T95
Test name
Test status
Simulation time 154841452446 ps
CPU time 123.17 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:20:14 PM PDT 24
Peak memory 198244 kb
Host smart-90831fe7-d814-4c3f-8436-55e2e80e4c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102901995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4102901995
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4114352006
Short name T153
Test name
Test status
Simulation time 340419025247 ps
CPU time 296.3 seconds
Started Aug 02 05:17:54 PM PDT 24
Finished Aug 02 05:22:50 PM PDT 24
Peak memory 201740 kb
Host smart-036913e6-9815-4e8d-9096-ea59a26be7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114352006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4114352006
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3485035482
Short name T111
Test name
Test status
Simulation time 89136352737 ps
CPU time 134.51 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:20:29 PM PDT 24
Peak memory 198300 kb
Host smart-19597b2f-c774-4151-90af-3ea3a65f9bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485035482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3485035482
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.204690240
Short name T100
Test name
Test status
Simulation time 18590970157 ps
CPU time 18.27 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 192964 kb
Host smart-88587323-9e98-4246-bf2e-03bae903cd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204690240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.204690240
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1471551356
Short name T42
Test name
Test status
Simulation time 189562192193 ps
CPU time 504.28 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:27:01 PM PDT 24
Peak memory 204088 kb
Host smart-631cebbb-d99c-43f3-b398-69327bd57e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471551356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1471551356
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2340452022
Short name T83
Test name
Test status
Simulation time 52479029778 ps
CPU time 396.81 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:25:06 PM PDT 24
Peak memory 206764 kb
Host smart-df8dcae2-189d-4610-917c-09a33a70c285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340452022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2340452022
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3345191875
Short name T127
Test name
Test status
Simulation time 435790052186 ps
CPU time 329.68 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:23:44 PM PDT 24
Peak memory 198220 kb
Host smart-9c726427-eeb2-4c02-83bf-a8ae38fdb01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345191875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3345191875
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1900709218
Short name T104
Test name
Test status
Simulation time 261105166450 ps
CPU time 83.38 seconds
Started Aug 02 05:18:46 PM PDT 24
Finished Aug 02 05:20:10 PM PDT 24
Peak memory 198256 kb
Host smart-86e996b1-0720-4469-b8ca-0a7a20b50cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900709218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1900709218
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3844901680
Short name T159
Test name
Test status
Simulation time 131897721687 ps
CPU time 275.83 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:22:49 PM PDT 24
Peak memory 214700 kb
Host smart-493a4fd5-2528-45c9-a040-7d01518e357f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844901680 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3844901680
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1153676499
Short name T145
Test name
Test status
Simulation time 241925656820 ps
CPU time 329.08 seconds
Started Aug 02 05:19:02 PM PDT 24
Finished Aug 02 05:24:31 PM PDT 24
Peak memory 198208 kb
Host smart-60a5f644-449f-4e93-9ccb-feae0b775c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153676499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1153676499
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2292173677
Short name T128
Test name
Test status
Simulation time 193502535080 ps
CPU time 256.56 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 193024 kb
Host smart-88c35c74-9247-43aa-817e-82e5506473ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292173677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2292173677
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2912182329
Short name T124
Test name
Test status
Simulation time 200084826938 ps
CPU time 73.06 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:19:25 PM PDT 24
Peak memory 184356 kb
Host smart-66e72303-9aac-4b49-a4e5-eb3e8740167b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912182329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2912182329
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4068818466
Short name T82
Test name
Test status
Simulation time 251754625179 ps
CPU time 522.75 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:26:47 PM PDT 24
Peak memory 212400 kb
Host smart-a70f2726-b602-45ea-972f-f6b8dacad059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068818466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4068818466
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1172039413
Short name T109
Test name
Test status
Simulation time 50372669143 ps
CPU time 340.13 seconds
Started Aug 02 05:18:52 PM PDT 24
Finished Aug 02 05:24:33 PM PDT 24
Peak memory 207220 kb
Host smart-4a3e3752-4127-4355-b907-b6baf7fde6cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172039413 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1172039413
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2302729831
Short name T92
Test name
Test status
Simulation time 463937083377 ps
CPU time 642.44 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 191924 kb
Host smart-e9c32ce2-3a3a-4e43-ba39-3763b61d2da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302729831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2302729831
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.154739267
Short name T32
Test name
Test status
Simulation time 1269600190 ps
CPU time 4.14 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 193432 kb
Host smart-1f0f677e-0046-4024-a283-0f44fc249ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154739267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.154739267
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.189034217
Short name T144
Test name
Test status
Simulation time 65194012700 ps
CPU time 24.89 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:18:56 PM PDT 24
Peak memory 193008 kb
Host smart-20c362f2-910b-49f9-97a7-db040e8065b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189034217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.189034217
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.882670232
Short name T162
Test name
Test status
Simulation time 152408637988 ps
CPU time 404.79 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 202596 kb
Host smart-a050ef2a-afa1-4760-8207-e5f2f43e833d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882670232 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.882670232
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3446849294
Short name T157
Test name
Test status
Simulation time 151599208505 ps
CPU time 284.28 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:23:08 PM PDT 24
Peak memory 209372 kb
Host smart-0e464d36-b59a-4dd9-ab19-8fed3887a832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446849294 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3446849294
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.799760469
Short name T147
Test name
Test status
Simulation time 134653397689 ps
CPU time 258.94 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:22:58 PM PDT 24
Peak memory 200976 kb
Host smart-d7182e08-b891-435c-acc3-a2f7ac2ad788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799760469 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.799760469
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2410993686
Short name T94
Test name
Test status
Simulation time 534126894925 ps
CPU time 188.95 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 191824 kb
Host smart-da18aa13-6a71-4fc3-9715-8d980b582141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410993686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2410993686
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4097756805
Short name T137
Test name
Test status
Simulation time 195540967525 ps
CPU time 135.21 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:20:38 PM PDT 24
Peak memory 198276 kb
Host smart-eeee6857-3e34-4830-8051-b8044abc7111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097756805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4097756805
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3471160685
Short name T152
Test name
Test status
Simulation time 180286973530 ps
CPU time 287.05 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:22:58 PM PDT 24
Peak memory 192864 kb
Host smart-7288ca5a-a3b4-4e73-ab4f-bd2ca19ae558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471160685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3471160685
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3661869606
Short name T119
Test name
Test status
Simulation time 144260243824 ps
CPU time 213.69 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 191916 kb
Host smart-82977282-c61a-4136-a4b8-dd18038b160f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661869606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3661869606
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2823795229
Short name T161
Test name
Test status
Simulation time 79218714480 ps
CPU time 107.22 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:20:18 PM PDT 24
Peak memory 192504 kb
Host smart-c499e420-f48d-4e1e-91dc-dc4d8bfebcd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823795229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2823795229
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3917704988
Short name T160
Test name
Test status
Simulation time 7716161897 ps
CPU time 54.59 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:19:22 PM PDT 24
Peak memory 206688 kb
Host smart-b9f6c6ab-3e10-4541-84fd-9ac144677c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917704988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3917704988
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2974379709
Short name T86
Test name
Test status
Simulation time 27882076753 ps
CPU time 220.53 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 206760 kb
Host smart-9b025b71-3fae-415a-99e0-024b6407f803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974379709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2974379709
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2337496885
Short name T122
Test name
Test status
Simulation time 556917299187 ps
CPU time 1539.02 seconds
Started Aug 02 05:18:16 PM PDT 24
Finished Aug 02 05:43:56 PM PDT 24
Peak memory 217776 kb
Host smart-74030970-8ec0-4b54-a939-dfa84206f253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337496885 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2337496885
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.551804451
Short name T103
Test name
Test status
Simulation time 99382861561 ps
CPU time 12.58 seconds
Started Aug 02 05:18:10 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 198188 kb
Host smart-49494e88-6ade-468a-adb6-23b19ee2e054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551804451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.551804451
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2267939443
Short name T101
Test name
Test status
Simulation time 95412429767 ps
CPU time 69.19 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:19:34 PM PDT 24
Peak memory 198340 kb
Host smart-c35cd447-19f3-487a-8cea-b87f4e037874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267939443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2267939443
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.767835174
Short name T143
Test name
Test status
Simulation time 250358086297 ps
CPU time 54.15 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:19:14 PM PDT 24
Peak memory 198260 kb
Host smart-833449ca-27ba-49e7-98b0-3ae54eb7ed89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767835174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.767835174
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2571447054
Short name T8
Test name
Test status
Simulation time 391370540276 ps
CPU time 157.09 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:20:56 PM PDT 24
Peak memory 193056 kb
Host smart-569cb423-a9a5-42e2-b3a4-8ae6f0ccc8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571447054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2571447054
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.286937218
Short name T125
Test name
Test status
Simulation time 237088862375 ps
CPU time 438.66 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:25:46 PM PDT 24
Peak memory 214092 kb
Host smart-69c63b44-9aae-421b-a2e9-50aab49a7d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286937218 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.286937218
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3955467812
Short name T141
Test name
Test status
Simulation time 404915773169 ps
CPU time 144.25 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:21:01 PM PDT 24
Peak memory 192480 kb
Host smart-0603c5f4-2ff8-4164-b4ce-4c12049ec8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955467812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3955467812
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.905279206
Short name T87
Test name
Test status
Simulation time 101530695182 ps
CPU time 144.48 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:21:04 PM PDT 24
Peak memory 198260 kb
Host smart-73882833-f1eb-4966-96b7-701aec6c3bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905279206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.905279206
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.433385018
Short name T156
Test name
Test status
Simulation time 19444821732 ps
CPU time 14.69 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 198232 kb
Host smart-139c839e-7197-488c-91a2-406f358ece28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433385018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.433385018
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.605322962
Short name T54
Test name
Test status
Simulation time 223115837155 ps
CPU time 278.14 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:22:57 PM PDT 24
Peak memory 199380 kb
Host smart-ab293b8a-e6e2-4d91-b35d-70a4d5df0166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605322962 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.605322962
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3456565203
Short name T178
Test name
Test status
Simulation time 97422766628 ps
CPU time 66.16 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:19:20 PM PDT 24
Peak memory 198236 kb
Host smart-41b4e35f-322b-49cf-8346-fe6e10e6739d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456565203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3456565203
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3277093774
Short name T176
Test name
Test status
Simulation time 118053243579 ps
CPU time 90.69 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:19:55 PM PDT 24
Peak memory 198272 kb
Host smart-c5be0ddc-e6bf-44c2-b37e-70ad2433d910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277093774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3277093774
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.706058691
Short name T146
Test name
Test status
Simulation time 27805515504 ps
CPU time 219.95 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 214764 kb
Host smart-3a7de780-4489-45a1-b83f-0939534fe5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706058691 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.706058691
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2743960802
Short name T11
Test name
Test status
Simulation time 84854615896 ps
CPU time 401.13 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:25:18 PM PDT 24
Peak memory 210664 kb
Host smart-86dfe9b6-1d49-4311-8645-b99f0fb4749b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743960802 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2743960802
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3058137981
Short name T27
Test name
Test status
Simulation time 393148523 ps
CPU time 1.15 seconds
Started Aug 02 05:18:17 PM PDT 24
Finished Aug 02 05:18:18 PM PDT 24
Peak memory 196644 kb
Host smart-dac6fbd5-bb6c-4182-8545-118f75a198da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058137981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3058137981
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3702235289
Short name T142
Test name
Test status
Simulation time 576374660 ps
CPU time 1.45 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 196728 kb
Host smart-b4f4496b-f943-4e9c-9dc7-d5fdc4516684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702235289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3702235289
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1962121380
Short name T105
Test name
Test status
Simulation time 234643945103 ps
CPU time 153.87 seconds
Started Aug 02 05:18:21 PM PDT 24
Finished Aug 02 05:20:55 PM PDT 24
Peak memory 198300 kb
Host smart-e9b0260d-5f98-498b-9e23-63a99d862182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962121380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1962121380
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1503763160
Short name T113
Test name
Test status
Simulation time 365010659 ps
CPU time 1.07 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:33 PM PDT 24
Peak memory 196684 kb
Host smart-0362e0b7-736b-4d81-b21d-e8831121c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503763160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1503763160
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4280054144
Short name T150
Test name
Test status
Simulation time 599090477 ps
CPU time 0.8 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 196700 kb
Host smart-6820e5be-6c90-45ac-b4be-4ba00f968ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280054144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4280054144
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.849107833
Short name T25
Test name
Test status
Simulation time 349207237758 ps
CPU time 283.87 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:22:40 PM PDT 24
Peak memory 184464 kb
Host smart-47461628-ea47-4f71-b125-b91790407e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849107833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.849107833
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1909793120
Short name T154
Test name
Test status
Simulation time 14127064500 ps
CPU time 150.76 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:20:57 PM PDT 24
Peak memory 214276 kb
Host smart-c4889832-a263-4963-bdf5-36e05da4de19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909793120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1909793120
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2317697504
Short name T21
Test name
Test status
Simulation time 437141730 ps
CPU time 0.74 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 196632 kb
Host smart-287d9f54-126f-4f19-990a-f2d82f5f008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317697504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2317697504
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1303477132
Short name T126
Test name
Test status
Simulation time 568737025 ps
CPU time 1 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:35 PM PDT 24
Peak memory 196772 kb
Host smart-533b1b09-d22e-4388-9e16-e6a73312b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303477132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1303477132
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1626476573
Short name T24
Test name
Test status
Simulation time 48020268749 ps
CPU time 264.6 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:23:04 PM PDT 24
Peak memory 206616 kb
Host smart-b7154614-51e8-40b1-b3fc-ece1ab92ab60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626476573 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1626476573
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1260104393
Short name T136
Test name
Test status
Simulation time 597806656 ps
CPU time 1.03 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 196672 kb
Host smart-e686c668-a86a-4157-8bf8-b5b1867cf74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260104393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1260104393
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1486775778
Short name T118
Test name
Test status
Simulation time 108535176706 ps
CPU time 173.09 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:21:07 PM PDT 24
Peak memory 192480 kb
Host smart-494ad399-036b-4f1b-a6d9-e850c3969d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486775778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1486775778
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2172408312
Short name T123
Test name
Test status
Simulation time 345671857 ps
CPU time 1.06 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 196700 kb
Host smart-53780765-f4ab-448e-bba4-ec0d953afc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172408312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2172408312
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.179572560
Short name T138
Test name
Test status
Simulation time 598810595 ps
CPU time 0.79 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 196708 kb
Host smart-0f26048e-ffc8-4347-89d0-7e2c716f215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179572560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.179572560
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3137635419
Short name T41
Test name
Test status
Simulation time 65423655390 ps
CPU time 476.47 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 201940 kb
Host smart-bffdce13-0bf0-4933-bc52-5466f635c03a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137635419 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3137635419
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.163600712
Short name T117
Test name
Test status
Simulation time 586081070 ps
CPU time 0.65 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 196796 kb
Host smart-7d9ba1d7-8f77-4b32-b029-a58638b66ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163600712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.163600712
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.277752551
Short name T149
Test name
Test status
Simulation time 372239998460 ps
CPU time 252.34 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:22:43 PM PDT 24
Peak memory 198280 kb
Host smart-f074e58d-44ca-4b88-871d-4e07d626c94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277752551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.277752551
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2162571832
Short name T91
Test name
Test status
Simulation time 411766971 ps
CPU time 0.76 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 196692 kb
Host smart-3c825341-5c47-44c3-af22-b40fbc3e3655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162571832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2162571832
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1618030156
Short name T133
Test name
Test status
Simulation time 571751834 ps
CPU time 0.65 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:28 PM PDT 24
Peak memory 196804 kb
Host smart-076f9bc1-ba3f-4a99-9426-72a80d2768fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618030156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1618030156
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.423838220
Short name T112
Test name
Test status
Simulation time 451922623 ps
CPU time 1.26 seconds
Started Aug 02 05:18:17 PM PDT 24
Finished Aug 02 05:18:18 PM PDT 24
Peak memory 196676 kb
Host smart-1b033393-9505-4485-a037-770297182276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423838220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.423838220
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2027897009
Short name T139
Test name
Test status
Simulation time 445581640 ps
CPU time 0.73 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:18:05 PM PDT 24
Peak memory 196760 kb
Host smart-82599b9f-fc9b-4430-ab52-e609bb0eb8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027897009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2027897009
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2786517628
Short name T173
Test name
Test status
Simulation time 27971033665 ps
CPU time 151.96 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:20:55 PM PDT 24
Peak memory 206712 kb
Host smart-789d4d96-f5db-4507-8996-58f55acabe4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786517628 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2786517628
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.189648630
Short name T131
Test name
Test status
Simulation time 447274470 ps
CPU time 0.91 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 196696 kb
Host smart-0a6e317e-3b32-4986-aedb-22b6288c5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189648630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.189648630
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2473294567
Short name T50
Test name
Test status
Simulation time 506584518 ps
CPU time 0.74 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:28 PM PDT 24
Peak memory 196780 kb
Host smart-068fdf36-770f-41b0-b91c-b945e3a0acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473294567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2473294567
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1633447904
Short name T30
Test name
Test status
Simulation time 567032983 ps
CPU time 0.79 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 196732 kb
Host smart-10b2ab8b-6c16-4f16-b50c-56356b483f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633447904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1633447904
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2771981112
Short name T151
Test name
Test status
Simulation time 560398779 ps
CPU time 0.8 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:35 PM PDT 24
Peak memory 196744 kb
Host smart-27c09a37-e766-4081-b6d5-300379c1ec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771981112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2771981112
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3488779001
Short name T172
Test name
Test status
Simulation time 494797942028 ps
CPU time 639.45 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:29:21 PM PDT 24
Peak memory 198308 kb
Host smart-b28a1925-8643-42aa-8040-a5842dd8fef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488779001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3488779001
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3924881898
Short name T148
Test name
Test status
Simulation time 382550719 ps
CPU time 1.12 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 196660 kb
Host smart-e84848b5-dc8e-43b8-b382-8d1abeb5d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924881898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3924881898
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1271233979
Short name T134
Test name
Test status
Simulation time 15574170582 ps
CPU time 12.39 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:24 PM PDT 24
Peak memory 191908 kb
Host smart-0f0e0bc2-9da8-4411-880a-b14bd87bcded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271233979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1271233979
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.601980805
Short name T115
Test name
Test status
Simulation time 147548979516 ps
CPU time 109.89 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:19:56 PM PDT 24
Peak memory 193012 kb
Host smart-ebf0ef44-f211-4aed-9c9f-481de222016c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601980805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.601980805
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2230103244
Short name T88
Test name
Test status
Simulation time 463857683 ps
CPU time 1.32 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 196724 kb
Host smart-796584c8-0188-40ff-954c-3b4a364d0800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230103244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2230103244
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3721339946
Short name T114
Test name
Test status
Simulation time 389784718 ps
CPU time 0.84 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 196796 kb
Host smart-81100fb3-b4fe-40e8-a457-4946e8a647be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721339946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3721339946
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3254117164
Short name T175
Test name
Test status
Simulation time 71305539706 ps
CPU time 113.6 seconds
Started Aug 02 05:18:21 PM PDT 24
Finished Aug 02 05:20:14 PM PDT 24
Peak memory 198240 kb
Host smart-37f2366c-c000-41f8-a29a-c8270d96251f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254117164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3254117164
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.29108757
Short name T170
Test name
Test status
Simulation time 56185038624 ps
CPU time 400.83 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:25:04 PM PDT 24
Peak memory 206648 kb
Host smart-5f3fee05-8bec-4726-be3f-b8d0fb59cf24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108757 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.29108757
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.922087877
Short name T140
Test name
Test status
Simulation time 434598322 ps
CPU time 1.17 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:28 PM PDT 24
Peak memory 196648 kb
Host smart-ff4cb055-35b8-4a2d-bff7-7170b45e5b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922087877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.922087877
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3088807816
Short name T90
Test name
Test status
Simulation time 420372972 ps
CPU time 0.86 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 196688 kb
Host smart-47cee612-6db1-465b-83eb-661fd56ef212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088807816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3088807816
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3506239871
Short name T108
Test name
Test status
Simulation time 385743228 ps
CPU time 0.77 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:18:37 PM PDT 24
Peak memory 196004 kb
Host smart-e14b0448-a664-46da-a8b1-581f8076190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506239871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3506239871
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.803558304
Short name T18
Test name
Test status
Simulation time 203262661558 ps
CPU time 209.1 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 200308 kb
Host smart-d664ce8f-8ef3-46d3-bc7c-1f169ad4fe1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803558304 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.803558304
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.840280285
Short name T179
Test name
Test status
Simulation time 536339764 ps
CPU time 1.03 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 196636 kb
Host smart-be089bf7-5dee-45db-9405-964a55d6fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840280285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.840280285
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3464264879
Short name T47
Test name
Test status
Simulation time 414266619 ps
CPU time 0.75 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 196704 kb
Host smart-535aa45c-50ae-4a1d-a79f-6b6c03097178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464264879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3464264879
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1918542221
Short name T31
Test name
Test status
Simulation time 94068483848 ps
CPU time 137.11 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:20:41 PM PDT 24
Peak memory 198260 kb
Host smart-e454a047-5acc-410f-b0da-84d9848042a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918542221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1918542221
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1444155224
Short name T191
Test name
Test status
Simulation time 536965582 ps
CPU time 1.36 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:28 PM PDT 24
Peak memory 196644 kb
Host smart-e2e6b4e4-ae9f-4bdd-8e29-5115c0847179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444155224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1444155224
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2204690558
Short name T192
Test name
Test status
Simulation time 4214042417 ps
CPU time 5.95 seconds
Started Aug 02 05:18:50 PM PDT 24
Finished Aug 02 05:18:57 PM PDT 24
Peak memory 197948 kb
Host smart-1ff810d6-cb18-4493-a678-c9cf7c4b6568
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204690558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2204690558
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3138510777
Short name T174
Test name
Test status
Simulation time 36463250093 ps
CPU time 140.96 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:20:19 PM PDT 24
Peak memory 214012 kb
Host smart-0e6eb2d3-f770-463b-8913-87f7a62c7bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138510777 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3138510777
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3615175126
Short name T155
Test name
Test status
Simulation time 638987802 ps
CPU time 0.76 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 196636 kb
Host smart-f106f05e-5aef-40b3-901b-ece41f44f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615175126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3615175126
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3597495617
Short name T163
Test name
Test status
Simulation time 368199910 ps
CPU time 0.65 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 196656 kb
Host smart-6c252dca-6e70-4b8a-8162-0f7544b1310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597495617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3597495617
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3323395588
Short name T190
Test name
Test status
Simulation time 517687177 ps
CPU time 0.99 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:18:19 PM PDT 24
Peak memory 196612 kb
Host smart-c1873a53-40ea-427d-971e-42d678fa07be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323395588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3323395588
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1870859508
Short name T183
Test name
Test status
Simulation time 141561708281 ps
CPU time 188.48 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:21:18 PM PDT 24
Peak memory 198280 kb
Host smart-7f61af19-b6b6-4691-8abb-e967a8f8f563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870859508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1870859508
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3852644046
Short name T52
Test name
Test status
Simulation time 497159163 ps
CPU time 1.12 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:15 PM PDT 24
Peak memory 196732 kb
Host smart-027ba264-d265-4aa5-a9d4-fffca863aae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852644046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3852644046
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2791856607
Short name T184
Test name
Test status
Simulation time 25706765020 ps
CPU time 99.59 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:20:11 PM PDT 24
Peak memory 206728 kb
Host smart-3bbe706c-e72d-4c1c-a279-4c0091339de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791856607 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2791856607
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2293448264
Short name T171
Test name
Test status
Simulation time 76515575285 ps
CPU time 62.38 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:19:17 PM PDT 24
Peak memory 198228 kb
Host smart-e8344234-b67d-4ce0-8947-7a1c2ffbf5a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293448264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2293448264
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2848326096
Short name T169
Test name
Test status
Simulation time 548338546 ps
CPU time 1.33 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 196608 kb
Host smart-19ca70e6-e0f7-4a8e-bb05-d2a0a8787a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848326096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2848326096
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2115145053
Short name T45
Test name
Test status
Simulation time 437851388 ps
CPU time 0.77 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:33 PM PDT 24
Peak memory 196592 kb
Host smart-21e27565-f09d-4832-bc94-eff775ce2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115145053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2115145053
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2876275437
Short name T167
Test name
Test status
Simulation time 358632115983 ps
CPU time 364.63 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:24:42 PM PDT 24
Peak memory 191872 kb
Host smart-7f651f99-3f3d-4667-b9a8-60696a80734f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876275437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2876275437
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.978030824
Short name T180
Test name
Test status
Simulation time 489240071 ps
CPU time 0.67 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 196648 kb
Host smart-44c07e3e-2a6d-4690-abec-2f96cbd4123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978030824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.978030824
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.575033265
Short name T51
Test name
Test status
Simulation time 453645396 ps
CPU time 0.74 seconds
Started Aug 02 05:18:58 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 196676 kb
Host smart-1234705a-81e1-4379-ab3b-12f452479f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575033265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.575033265
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.411797663
Short name T81
Test name
Test status
Simulation time 68037319465 ps
CPU time 285.43 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:23:26 PM PDT 24
Peak memory 200040 kb
Host smart-b1ad069d-6b54-486a-ba93-80d6d63cf192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411797663 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.411797663
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.218903054
Short name T135
Test name
Test status
Simulation time 440577021 ps
CPU time 0.75 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 196780 kb
Host smart-464a1acf-bc3e-403a-9671-78cc77748121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218903054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.218903054
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1537263082
Short name T49
Test name
Test status
Simulation time 398168578 ps
CPU time 1.13 seconds
Started Aug 02 05:17:47 PM PDT 24
Finished Aug 02 05:17:48 PM PDT 24
Peak memory 196636 kb
Host smart-5629a5d6-920c-427c-bbe8-8148daec874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537263082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1537263082
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.703221047
Short name T110
Test name
Test status
Simulation time 513364781 ps
CPU time 1.3 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 196768 kb
Host smart-599f909b-acbe-44a9-a2c9-b5872e378f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703221047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.703221047
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4215689578
Short name T168
Test name
Test status
Simulation time 365872271 ps
CPU time 1.15 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:28 PM PDT 24
Peak memory 196768 kb
Host smart-996aea0d-bd54-4448-90a5-f3b7d90986fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215689578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4215689578
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3955884283
Short name T158
Test name
Test status
Simulation time 569666983 ps
CPU time 1.33 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 196652 kb
Host smart-ba4c930e-8f0e-47a7-b054-04dd6079d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955884283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3955884283
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3322102631
Short name T130
Test name
Test status
Simulation time 194864296682 ps
CPU time 73.77 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:19:41 PM PDT 24
Peak memory 191936 kb
Host smart-d17631f9-b3c5-4400-bd7c-628b7177ba1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322102631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3322102631
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3074981870
Short name T28
Test name
Test status
Simulation time 21229604188 ps
CPU time 17.46 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:48 PM PDT 24
Peak memory 198240 kb
Host smart-f8b970b9-8997-4922-b48c-cda0277968b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074981870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3074981870
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.211042722
Short name T187
Test name
Test status
Simulation time 83965696629 ps
CPU time 67.67 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:19:37 PM PDT 24
Peak memory 198264 kb
Host smart-007dc245-5389-4c15-91c3-f047252ed456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211042722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.211042722
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1740502418
Short name T46
Test name
Test status
Simulation time 498581085 ps
CPU time 0.91 seconds
Started Aug 02 05:18:40 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 196664 kb
Host smart-4685624d-f1f8-4d7e-bed1-58604f959088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740502418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1740502418
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1021339120
Short name T182
Test name
Test status
Simulation time 546391563 ps
CPU time 1.04 seconds
Started Aug 02 05:18:17 PM PDT 24
Finished Aug 02 05:18:18 PM PDT 24
Peak memory 196624 kb
Host smart-6638234f-b215-46c3-a77d-cfa4f6dba2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021339120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1021339120
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1248201327
Short name T181
Test name
Test status
Simulation time 337477163 ps
CPU time 1.08 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:42 PM PDT 24
Peak memory 196716 kb
Host smart-c90894c2-ce4c-4006-90f6-bbb546d0429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248201327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1248201327
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3365301196
Short name T63
Test name
Test status
Simulation time 538282432 ps
CPU time 1.07 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 193328 kb
Host smart-fb970549-eefc-4345-9811-fceabb71e433
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365301196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3365301196
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3657603305
Short name T62
Test name
Test status
Simulation time 667341543 ps
CPU time 1.52 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 196296 kb
Host smart-a536dfe7-ee19-43ef-8a78-84033453b108
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657603305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3657603305
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3124129504
Short name T355
Test name
Test status
Simulation time 1098717573 ps
CPU time 2.33 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 183816 kb
Host smart-02d83fc0-a732-4d53-a900-e47aeb5a4933
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124129504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3124129504
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.495814541
Short name T339
Test name
Test status
Simulation time 751766948 ps
CPU time 0.78 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:35 PM PDT 24
Peak memory 197484 kb
Host smart-077e7e70-ca13-40f4-acb0-0b1d66459a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495814541 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.495814541
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2096991336
Short name T363
Test name
Test status
Simulation time 350380395 ps
CPU time 1.1 seconds
Started Aug 02 05:18:35 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 193548 kb
Host smart-466b2f02-4be0-46f1-811c-9d446b88804b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096991336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2096991336
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.224939523
Short name T304
Test name
Test status
Simulation time 409604894 ps
CPU time 0.57 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 183828 kb
Host smart-8ae98e14-0262-42c8-91cc-0bc988a34882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224939523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.224939523
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3310704014
Short name T305
Test name
Test status
Simulation time 481397037 ps
CPU time 0.75 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 183708 kb
Host smart-6bb9600b-3324-40b0-948b-984755f9f558
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310704014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3310704014
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.176590471
Short name T326
Test name
Test status
Simulation time 481885158 ps
CPU time 1.22 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 183660 kb
Host smart-4446f4ea-345c-4ba6-b2a7-33ca9d1de645
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176590471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.176590471
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3750102672
Short name T398
Test name
Test status
Simulation time 512689945 ps
CPU time 1.88 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:44 PM PDT 24
Peak memory 198648 kb
Host smart-13335692-c7f9-4267-b161-6c6df5a2d887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750102672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3750102672
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3677392106
Short name T379
Test name
Test status
Simulation time 8705881741 ps
CPU time 2.59 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 198152 kb
Host smart-de89dcce-51ec-4e7b-8029-fa5200b7d66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677392106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3677392106
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1345519790
Short name T33
Test name
Test status
Simulation time 616951674 ps
CPU time 1.21 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 193836 kb
Host smart-33f86cc3-cf27-4340-9c12-5bde2e292710
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345519790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1345519790
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.974387768
Short name T59
Test name
Test status
Simulation time 13550320524 ps
CPU time 13.7 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 184148 kb
Host smart-0b4fda6e-ed68-4d67-9293-2af1a4d3e3f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974387768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.974387768
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.756578727
Short name T313
Test name
Test status
Simulation time 950813132 ps
CPU time 0.96 seconds
Started Aug 02 05:18:45 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 193044 kb
Host smart-fb7c9a9b-098a-4afe-bcf9-33f33bc1f864
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756578727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.756578727
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3369165037
Short name T334
Test name
Test status
Simulation time 431016701 ps
CPU time 0.75 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 196016 kb
Host smart-c14ee94a-f250-499f-a639-20cbf3346b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369165037 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3369165037
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2189779472
Short name T69
Test name
Test status
Simulation time 476708731 ps
CPU time 0.7 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:44 PM PDT 24
Peak memory 194048 kb
Host smart-d3c0f704-26bc-4040-93b7-fed52f0814be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189779472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2189779472
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.596825154
Short name T419
Test name
Test status
Simulation time 425341051 ps
CPU time 1.06 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 183752 kb
Host smart-e89fdd0b-a719-44e8-925c-649a30f26367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596825154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.596825154
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2400840545
Short name T383
Test name
Test status
Simulation time 345780886 ps
CPU time 0.61 seconds
Started Aug 02 05:18:40 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 183712 kb
Host smart-c4a1cc7a-3702-447e-8a2e-b7696803c9fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400840545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2400840545
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.207864363
Short name T340
Test name
Test status
Simulation time 456405516 ps
CPU time 0.83 seconds
Started Aug 02 05:18:35 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 183628 kb
Host smart-afa74570-b7d2-4ca8-82cf-f52bb25accdd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207864363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.207864363
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.595401469
Short name T70
Test name
Test status
Simulation time 1487676467 ps
CPU time 4.42 seconds
Started Aug 02 05:19:13 PM PDT 24
Finished Aug 02 05:19:18 PM PDT 24
Peak memory 194024 kb
Host smart-235aff76-cc90-4f2f-a45b-56eded50854b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595401469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.595401469
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1420409726
Short name T306
Test name
Test status
Simulation time 429990080 ps
CPU time 2.4 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 198620 kb
Host smart-4a471bb9-a21a-4a3c-bc1e-4253d4d30821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420409726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1420409726
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4044341404
Short name T194
Test name
Test status
Simulation time 3958763038 ps
CPU time 2.43 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 197992 kb
Host smart-7c74515a-a7b9-475d-b14c-b205b093c579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044341404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4044341404
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1638309627
Short name T296
Test name
Test status
Simulation time 578559243 ps
CPU time 0.88 seconds
Started Aug 02 05:19:05 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 196340 kb
Host smart-1a9dd6bb-60f4-41db-b19c-8e055214023b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638309627 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1638309627
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4123473405
Short name T408
Test name
Test status
Simulation time 382490597 ps
CPU time 0.84 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 192044 kb
Host smart-4293c94f-a55f-4155-871a-2b0ecbc02d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123473405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4123473405
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1834897782
Short name T374
Test name
Test status
Simulation time 343926883 ps
CPU time 0.98 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 183776 kb
Host smart-a8b0faf7-451e-4a02-9d0b-b6dce62620eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834897782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1834897782
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2264890902
Short name T367
Test name
Test status
Simulation time 1505844714 ps
CPU time 1.29 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 193544 kb
Host smart-e149ea42-5cf7-46d1-aa50-2428513d7f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264890902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2264890902
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.640831641
Short name T405
Test name
Test status
Simulation time 545479026 ps
CPU time 1.16 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:45 PM PDT 24
Peak memory 198460 kb
Host smart-2fbe97c4-be51-4d1c-b8ee-53f725ee3d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640831641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.640831641
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3925150908
Short name T370
Test name
Test status
Simulation time 4933831715 ps
CPU time 1.81 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:44 PM PDT 24
Peak memory 197764 kb
Host smart-1bef3b4e-f28e-4f27-98dc-aba55a56dc24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925150908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3925150908
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1534284546
Short name T418
Test name
Test status
Simulation time 584512106 ps
CPU time 1 seconds
Started Aug 02 05:18:35 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 198436 kb
Host smart-c3f27126-a91a-411c-b0cb-ef74f47b6f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534284546 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1534284546
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2459972643
Short name T387
Test name
Test status
Simulation time 472657624 ps
CPU time 0.69 seconds
Started Aug 02 05:18:40 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 193016 kb
Host smart-bcf6ad12-83e4-4b75-ba3b-5c13773ba29d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459972643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2459972643
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2790489364
Short name T297
Test name
Test status
Simulation time 533158226 ps
CPU time 0.72 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 183820 kb
Host smart-eead419a-5986-493b-a902-e8bed0283ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790489364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2790489364
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.210973292
Short name T356
Test name
Test status
Simulation time 2062851839 ps
CPU time 3.01 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 193984 kb
Host smart-c3cc0c19-8926-410e-a8ee-bfde99f293d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210973292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.210973292
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1381505565
Short name T342
Test name
Test status
Simulation time 581403896 ps
CPU time 2.73 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:48 PM PDT 24
Peak memory 198608 kb
Host smart-51e9dd3f-8e0d-4c8f-95b3-573be0aa860c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381505565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1381505565
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1330944260
Short name T416
Test name
Test status
Simulation time 645215605 ps
CPU time 0.82 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:54 PM PDT 24
Peak memory 197224 kb
Host smart-a7c8f2c7-6e5d-4055-b93a-f38414dfc949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330944260 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1330944260
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.20121101
Short name T338
Test name
Test status
Simulation time 345076759 ps
CPU time 0.83 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 192984 kb
Host smart-c42262a0-00fa-4d84-b5e5-be781f15d60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.20121101
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.423333545
Short name T323
Test name
Test status
Simulation time 311411420 ps
CPU time 0.6 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 183776 kb
Host smart-a55592fd-12fc-4c6e-83b7-b32b8e32ab13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423333545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.423333545
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2850093776
Short name T391
Test name
Test status
Simulation time 1089160938 ps
CPU time 2.17 seconds
Started Aug 02 05:19:09 PM PDT 24
Finished Aug 02 05:19:11 PM PDT 24
Peak memory 193028 kb
Host smart-9a78f1aa-7b52-477e-b02c-ec576828e9b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850093776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2850093776
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.694963097
Short name T333
Test name
Test status
Simulation time 470874965 ps
CPU time 2.86 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 198640 kb
Host smart-cb789f69-7b27-4451-8a1b-b7a6a6849313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694963097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.694963097
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2707281130
Short name T415
Test name
Test status
Simulation time 9196685140 ps
CPU time 15.25 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:53 PM PDT 24
Peak memory 198420 kb
Host smart-ad8a4958-cdf8-47d2-af70-a3961201476c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707281130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2707281130
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1327918564
Short name T421
Test name
Test status
Simulation time 451598201 ps
CPU time 0.93 seconds
Started Aug 02 05:19:04 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 196164 kb
Host smart-10017aea-a3cd-451d-a80e-160e118b1054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327918564 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1327918564
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2270790547
Short name T417
Test name
Test status
Simulation time 540672305 ps
CPU time 1.3 seconds
Started Aug 02 05:18:49 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 193180 kb
Host smart-e1659846-889c-4468-a45a-a86983780547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270790547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2270790547
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3868509942
Short name T318
Test name
Test status
Simulation time 497155005 ps
CPU time 0.63 seconds
Started Aug 02 05:19:46 PM PDT 24
Finished Aug 02 05:19:47 PM PDT 24
Peak memory 183572 kb
Host smart-d6af37a7-e6a0-414f-81fe-ab97ffabaab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868509942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3868509942
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3589553809
Short name T389
Test name
Test status
Simulation time 1064449267 ps
CPU time 2.59 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 192716 kb
Host smart-d6e576ed-697c-4802-9343-d94d92bc2ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589553809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3589553809
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4018815081
Short name T388
Test name
Test status
Simulation time 478087567 ps
CPU time 1.23 seconds
Started Aug 02 05:19:02 PM PDT 24
Finished Aug 02 05:19:03 PM PDT 24
Peak memory 198484 kb
Host smart-3bf75917-1534-44d4-819b-55a9c6d28646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018815081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4018815081
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1814451693
Short name T375
Test name
Test status
Simulation time 3800378802 ps
CPU time 3.76 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 198124 kb
Host smart-868d0a67-f97a-46b8-a2ba-aab919d06ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814451693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1814451693
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2203995686
Short name T364
Test name
Test status
Simulation time 374306314 ps
CPU time 0.74 seconds
Started Aug 02 05:19:01 PM PDT 24
Finished Aug 02 05:19:02 PM PDT 24
Peak memory 195492 kb
Host smart-03f3fc24-d5ee-44f2-961c-c35756c921ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203995686 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2203995686
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3422777199
Short name T67
Test name
Test status
Simulation time 459258834 ps
CPU time 1.27 seconds
Started Aug 02 05:19:28 PM PDT 24
Finished Aug 02 05:19:30 PM PDT 24
Peak memory 193032 kb
Host smart-ac949a7b-e6d2-49a6-ab8e-388cfe368ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422777199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3422777199
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1140049661
Short name T397
Test name
Test status
Simulation time 271007096 ps
CPU time 0.91 seconds
Started Aug 02 05:19:00 PM PDT 24
Finished Aug 02 05:19:01 PM PDT 24
Peak memory 183840 kb
Host smart-2091cdc5-bd6f-41fa-a5a9-06c4161b6e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140049661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1140049661
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2682531087
Short name T371
Test name
Test status
Simulation time 1896677433 ps
CPU time 3.23 seconds
Started Aug 02 05:19:01 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 194908 kb
Host smart-19ff6177-be70-4902-98bd-9d1c246e06b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682531087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2682531087
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.696717815
Short name T329
Test name
Test status
Simulation time 573356533 ps
CPU time 1.14 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 198520 kb
Host smart-0b50f810-f3bd-4479-86e8-29fd3ca77d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696717815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.696717815
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4173939775
Short name T380
Test name
Test status
Simulation time 4588326467 ps
CPU time 2.73 seconds
Started Aug 02 05:18:55 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 197604 kb
Host smart-2cf8cfe8-c260-4c1d-a87f-59c300fba567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173939775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4173939775
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1664244393
Short name T200
Test name
Test status
Simulation time 566849535 ps
CPU time 0.91 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 196776 kb
Host smart-29047a66-b126-44c5-86f8-7fcbc836f864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664244393 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1664244393
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.438251895
Short name T65
Test name
Test status
Simulation time 389927957 ps
CPU time 1.12 seconds
Started Aug 02 05:19:00 PM PDT 24
Finished Aug 02 05:19:01 PM PDT 24
Peak memory 193992 kb
Host smart-98af0ae6-adaa-4fd4-96af-6e3c41b35aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438251895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.438251895
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1872372605
Short name T309
Test name
Test status
Simulation time 304519491 ps
CPU time 0.99 seconds
Started Aug 02 05:18:49 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 183832 kb
Host smart-81267f73-5aed-4540-ba07-d106b7c20594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872372605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1872372605
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1825215971
Short name T366
Test name
Test status
Simulation time 2195769755 ps
CPU time 3.46 seconds
Started Aug 02 05:18:55 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 195040 kb
Host smart-f7c1a443-79de-4b6e-8e4b-652949718093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825215971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1825215971
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2498018614
Short name T406
Test name
Test status
Simulation time 463971608 ps
CPU time 2.15 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 198736 kb
Host smart-77b3ba6b-d827-454a-bf53-d3812c95d0eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498018614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2498018614
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1495747375
Short name T195
Test name
Test status
Simulation time 8062823007 ps
CPU time 5.1 seconds
Started Aug 02 05:18:52 PM PDT 24
Finished Aug 02 05:18:57 PM PDT 24
Peak memory 198420 kb
Host smart-67c87465-f07c-4cfa-aed5-cf514817f7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495747375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1495747375
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.394685490
Short name T413
Test name
Test status
Simulation time 458243394 ps
CPU time 1.48 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 197012 kb
Host smart-a17309cb-a2db-4c99-aa46-306fb467270a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394685490 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.394685490
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2719701187
Short name T426
Test name
Test status
Simulation time 492662827 ps
CPU time 0.91 seconds
Started Aug 02 05:18:56 PM PDT 24
Finished Aug 02 05:18:57 PM PDT 24
Peak memory 193188 kb
Host smart-0ef9f718-ba4d-49aa-a2b8-573d13cc21bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719701187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2719701187
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3753045835
Short name T310
Test name
Test status
Simulation time 292541036 ps
CPU time 1.02 seconds
Started Aug 02 05:19:06 PM PDT 24
Finished Aug 02 05:19:07 PM PDT 24
Peak memory 183828 kb
Host smart-259ac301-df01-40e7-aa18-f6e30fa70994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753045835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3753045835
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2276583583
Short name T392
Test name
Test status
Simulation time 1969479698 ps
CPU time 5.42 seconds
Started Aug 02 05:18:54 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 195032 kb
Host smart-bbdd955e-dc67-446c-8b12-85ac5d6270a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276583583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2276583583
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3507770467
Short name T350
Test name
Test status
Simulation time 756318874 ps
CPU time 2.29 seconds
Started Aug 02 05:19:00 PM PDT 24
Finished Aug 02 05:19:02 PM PDT 24
Peak memory 198700 kb
Host smart-e669eb40-846e-4ddf-884a-8f1d80a859f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507770467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3507770467
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2629937160
Short name T37
Test name
Test status
Simulation time 8010718811 ps
CPU time 6.51 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 198356 kb
Host smart-b005cf74-8f64-41b5-9578-2297d3919404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629937160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2629937160
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4067550263
Short name T294
Test name
Test status
Simulation time 522639917 ps
CPU time 1.3 seconds
Started Aug 02 05:19:09 PM PDT 24
Finished Aug 02 05:19:10 PM PDT 24
Peak memory 198648 kb
Host smart-90a7ef12-a0a7-47ef-ae28-5c8c0dee0ec1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067550263 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4067550263
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1187595216
Short name T76
Test name
Test status
Simulation time 544603344 ps
CPU time 0.64 seconds
Started Aug 02 05:19:01 PM PDT 24
Finished Aug 02 05:19:02 PM PDT 24
Peak memory 193088 kb
Host smart-3d68071a-1a80-4b2b-8f4c-2fc84fb7f2f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187595216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1187595216
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3994058309
Short name T348
Test name
Test status
Simulation time 314384451 ps
CPU time 0.78 seconds
Started Aug 02 05:19:06 PM PDT 24
Finished Aug 02 05:19:07 PM PDT 24
Peak memory 193056 kb
Host smart-af253bd7-5748-4472-8d50-85aa042ff0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994058309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3994058309
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3544588092
Short name T74
Test name
Test status
Simulation time 1258502691 ps
CPU time 3.82 seconds
Started Aug 02 05:19:15 PM PDT 24
Finished Aug 02 05:19:19 PM PDT 24
Peak memory 191972 kb
Host smart-87e4b4f8-3a4a-4524-ac6a-e55541ff84e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544588092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3544588092
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3737512309
Short name T377
Test name
Test status
Simulation time 791044880 ps
CPU time 2.22 seconds
Started Aug 02 05:18:52 PM PDT 24
Finished Aug 02 05:18:54 PM PDT 24
Peak memory 198636 kb
Host smart-c96fc37c-5dff-4606-ac7a-987deb8426db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737512309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3737512309
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.354416440
Short name T298
Test name
Test status
Simulation time 515972967 ps
CPU time 0.97 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 198424 kb
Host smart-a171460e-24b5-4d66-bf08-b9f815a94452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354416440 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.354416440
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1201331538
Short name T57
Test name
Test status
Simulation time 350677201 ps
CPU time 0.68 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:47 PM PDT 24
Peak memory 193256 kb
Host smart-a8a80348-a0e1-4c2c-9085-a366b65ee66f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201331538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1201331538
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1041129863
Short name T303
Test name
Test status
Simulation time 474574257 ps
CPU time 1.17 seconds
Started Aug 02 05:18:49 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 183780 kb
Host smart-73ae8401-a709-4d67-b506-0e2b750913e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041129863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1041129863
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2480453848
Short name T395
Test name
Test status
Simulation time 2847673352 ps
CPU time 1.88 seconds
Started Aug 02 05:18:54 PM PDT 24
Finished Aug 02 05:18:56 PM PDT 24
Peak memory 193992 kb
Host smart-0202b50f-c869-44ce-9f36-58c69df6c0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480453848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2480453848
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3420459954
Short name T402
Test name
Test status
Simulation time 433756477 ps
CPU time 1.85 seconds
Started Aug 02 05:18:46 PM PDT 24
Finished Aug 02 05:18:48 PM PDT 24
Peak memory 198696 kb
Host smart-47d87869-4de1-4b74-b7f4-166e6b9e1613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420459954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3420459954
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1638720953
Short name T357
Test name
Test status
Simulation time 4388871021 ps
CPU time 2.44 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 197916 kb
Host smart-a9172b6e-e29f-4085-98bb-20ec41b0a3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638720953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1638720953
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2603601301
Short name T403
Test name
Test status
Simulation time 318139775 ps
CPU time 0.93 seconds
Started Aug 02 05:18:56 PM PDT 24
Finished Aug 02 05:18:57 PM PDT 24
Peak memory 195256 kb
Host smart-47114710-cfd9-4b91-a906-ebfa86ce653d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603601301 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2603601301
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2129496885
Short name T72
Test name
Test status
Simulation time 433542232 ps
CPU time 0.6 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 193240 kb
Host smart-664bf44e-39fe-47dd-aea8-69b82b9f12c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129496885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2129496885
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1045994428
Short name T324
Test name
Test status
Simulation time 413390600 ps
CPU time 0.76 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 183808 kb
Host smart-be67857e-0032-4f78-beab-241a408ecc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045994428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1045994428
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2416484308
Short name T401
Test name
Test status
Simulation time 2305255952 ps
CPU time 3.36 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:54 PM PDT 24
Peak memory 195460 kb
Host smart-017c5dd9-29ee-433d-93ae-2ced65278798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416484308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2416484308
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3584262655
Short name T351
Test name
Test status
Simulation time 1195443701 ps
CPU time 1.36 seconds
Started Aug 02 05:19:10 PM PDT 24
Finished Aug 02 05:19:11 PM PDT 24
Peak memory 198652 kb
Host smart-77365800-6efa-47bb-9bbf-d2e08d5c2598
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584262655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3584262655
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2408134331
Short name T423
Test name
Test status
Simulation time 8706824428 ps
CPU time 7.58 seconds
Started Aug 02 05:18:56 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 198616 kb
Host smart-9574d364-735a-4898-8c8c-c3bccace68b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408134331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2408134331
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2964067939
Short name T64
Test name
Test status
Simulation time 444562946 ps
CPU time 0.74 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 193408 kb
Host smart-4d277e18-7463-4913-b959-c7af37387d65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964067939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2964067939
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3401508123
Short name T61
Test name
Test status
Simulation time 11252335777 ps
CPU time 5.9 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 192380 kb
Host smart-0c77731b-c15a-43b4-b0b4-14a01e9dbe4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401508123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3401508123
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2118676231
Short name T60
Test name
Test status
Simulation time 737972989 ps
CPU time 1.6 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 183812 kb
Host smart-826e174a-569d-4a6f-831e-d74625333781
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118676231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2118676231
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3297614828
Short name T394
Test name
Test status
Simulation time 392446547 ps
CPU time 1.23 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 195720 kb
Host smart-08f95ef0-1d41-4e6c-9ea6-533146715e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297614828 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3297614828
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1004675267
Short name T360
Test name
Test status
Simulation time 535912308 ps
CPU time 0.97 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:33 PM PDT 24
Peak memory 193256 kb
Host smart-bf3c5c8e-eaf5-4280-8d5a-3c7f63796898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004675267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1004675267
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1068271771
Short name T373
Test name
Test status
Simulation time 427116826 ps
CPU time 0.91 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 183792 kb
Host smart-ea9ce9ab-db90-42ef-8e38-2e6a73c16f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068271771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1068271771
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1154535980
Short name T291
Test name
Test status
Simulation time 531484639 ps
CPU time 0.7 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 183732 kb
Host smart-6dd5b2f3-aa21-44fb-a1dc-87e6591d6431
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154535980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1154535980
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1569254704
Short name T325
Test name
Test status
Simulation time 369889057 ps
CPU time 0.68 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 183708 kb
Host smart-aea45a50-5832-41f6-914b-2018096098a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569254704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1569254704
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1857472627
Short name T382
Test name
Test status
Simulation time 2527483952 ps
CPU time 2.17 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 193884 kb
Host smart-f03dd061-d6ed-4ee9-8509-87deb14d4a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857472627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1857472627
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1440071203
Short name T301
Test name
Test status
Simulation time 347996214 ps
CPU time 1.05 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:45 PM PDT 24
Peak memory 197580 kb
Host smart-472dd67d-b25f-4971-b2e9-47415f3cffee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440071203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1440071203
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3104678554
Short name T193
Test name
Test status
Simulation time 4148487581 ps
CPU time 2.76 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:45 PM PDT 24
Peak memory 197940 kb
Host smart-8b256890-119c-4e16-b624-4cbde374def5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104678554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3104678554
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3061504974
Short name T411
Test name
Test status
Simulation time 478254298 ps
CPU time 0.62 seconds
Started Aug 02 05:19:05 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 192976 kb
Host smart-a1dd96e3-5fee-41a1-8b03-10e231b939e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061504974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3061504974
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2467209914
Short name T336
Test name
Test status
Simulation time 292869099 ps
CPU time 0.68 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 183808 kb
Host smart-7c910ec5-f865-4104-8e34-bd3a8d9a1566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467209914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2467209914
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1615880438
Short name T316
Test name
Test status
Simulation time 372328641 ps
CPU time 0.67 seconds
Started Aug 02 05:19:08 PM PDT 24
Finished Aug 02 05:19:09 PM PDT 24
Peak memory 183832 kb
Host smart-c06dd642-2cf9-4baf-9b5e-3080478d4a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615880438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1615880438
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1595032569
Short name T302
Test name
Test status
Simulation time 396031386 ps
CPU time 1.18 seconds
Started Aug 02 05:19:04 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 193052 kb
Host smart-8ce388fd-359d-4709-8105-67f065d87744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595032569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1595032569
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.549606042
Short name T376
Test name
Test status
Simulation time 468493258 ps
CPU time 1.24 seconds
Started Aug 02 05:19:04 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 193068 kb
Host smart-e298c6df-a7c1-466b-9bf9-e30eb5581126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549606042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.549606042
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.89103891
Short name T319
Test name
Test status
Simulation time 345920895 ps
CPU time 0.96 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 183788 kb
Host smart-ca371da6-04f9-4428-890a-be0ad517f7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89103891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.89103891
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3999258790
Short name T352
Test name
Test status
Simulation time 316680719 ps
CPU time 0.69 seconds
Started Aug 02 05:19:05 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 193048 kb
Host smart-adf88369-481c-43af-8bb5-59941577dcdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999258790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3999258790
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4291517548
Short name T312
Test name
Test status
Simulation time 447225216 ps
CPU time 0.71 seconds
Started Aug 02 05:19:09 PM PDT 24
Finished Aug 02 05:19:10 PM PDT 24
Peak memory 183840 kb
Host smart-eb469201-b586-4973-ad32-9e8bfe812604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291517548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4291517548
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4003388615
Short name T317
Test name
Test status
Simulation time 514933430 ps
CPU time 0.71 seconds
Started Aug 02 05:19:07 PM PDT 24
Finished Aug 02 05:19:08 PM PDT 24
Peak memory 183832 kb
Host smart-ec2d8a97-1f78-4454-869f-91d57591574a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003388615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4003388615
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3727040034
Short name T299
Test name
Test status
Simulation time 506979827 ps
CPU time 1.26 seconds
Started Aug 02 05:18:50 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 193036 kb
Host smart-da7ad120-c30a-4a3d-bb07-a609f4a26af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727040034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3727040034
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1465355506
Short name T346
Test name
Test status
Simulation time 527380261 ps
CPU time 0.89 seconds
Started Aug 02 05:18:50 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 193112 kb
Host smart-02cbaf5a-5782-4396-bc56-d91e0139ef53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465355506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1465355506
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.287487394
Short name T295
Test name
Test status
Simulation time 7228126700 ps
CPU time 10.25 seconds
Started Aug 02 05:18:49 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 196464 kb
Host smart-60c920bb-45f9-4b9a-a7bc-6c684dec3875
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287487394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.287487394
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.752882401
Short name T56
Test name
Test status
Simulation time 872416933 ps
CPU time 0.88 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 183776 kb
Host smart-afbb0435-dcfd-4600-a765-ea1378cb689a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752882401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.752882401
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2786098583
Short name T331
Test name
Test status
Simulation time 521474060 ps
CPU time 0.86 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 197300 kb
Host smart-266ead42-33c8-4ba7-9325-21ea2e0786f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786098583 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2786098583
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3960007855
Short name T384
Test name
Test status
Simulation time 517699274 ps
CPU time 1.35 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 193076 kb
Host smart-8cb90503-6e6d-4756-811a-d5413eacf24b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960007855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3960007855
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.234258429
Short name T420
Test name
Test status
Simulation time 471068978 ps
CPU time 0.86 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 193044 kb
Host smart-ed16a7ae-577b-4de8-b4c4-7b68349acbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234258429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.234258429
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2734943552
Short name T369
Test name
Test status
Simulation time 410544171 ps
CPU time 0.59 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 183740 kb
Host smart-0b40db55-f548-45d1-bf4b-4f4c86424e6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734943552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2734943552
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2538818380
Short name T314
Test name
Test status
Simulation time 400929502 ps
CPU time 0.67 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 183796 kb
Host smart-55b176e0-315c-458c-a25c-750e016439d8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538818380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2538818380
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.684547594
Short name T349
Test name
Test status
Simulation time 1812786913 ps
CPU time 3.07 seconds
Started Aug 02 05:18:53 PM PDT 24
Finished Aug 02 05:18:56 PM PDT 24
Peak memory 194948 kb
Host smart-88af91a0-f2f8-41dc-a807-6ba370adb8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684547594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.684547594
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3470270545
Short name T345
Test name
Test status
Simulation time 689328438 ps
CPU time 2.32 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 198648 kb
Host smart-11ec4c70-2719-4296-b57f-65412b7bb27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470270545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3470270545
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2830284613
Short name T196
Test name
Test status
Simulation time 4106890098 ps
CPU time 1.81 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 198012 kb
Host smart-b4ccb9c3-cf3a-4ea7-8736-5841ea94aa01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830284613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2830284613
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.551321368
Short name T409
Test name
Test status
Simulation time 434900214 ps
CPU time 1.17 seconds
Started Aug 02 05:19:01 PM PDT 24
Finished Aug 02 05:19:02 PM PDT 24
Peak memory 183812 kb
Host smart-63699a80-8284-4ef6-a8a2-4f51ba63124b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551321368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.551321368
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2489319648
Short name T293
Test name
Test status
Simulation time 323821369 ps
CPU time 0.72 seconds
Started Aug 02 05:19:15 PM PDT 24
Finished Aug 02 05:19:15 PM PDT 24
Peak memory 193048 kb
Host smart-fb7ee03e-019f-44cf-b2cb-e7276d1083d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489319648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2489319648
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2931770898
Short name T311
Test name
Test status
Simulation time 269835780 ps
CPU time 0.95 seconds
Started Aug 02 05:18:58 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 193028 kb
Host smart-5ea10e68-f5af-411f-8a26-88d822bc725a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931770898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2931770898
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2984981907
Short name T320
Test name
Test status
Simulation time 429154303 ps
CPU time 0.57 seconds
Started Aug 02 05:19:05 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 183820 kb
Host smart-40c8234b-1da8-48e1-9797-64322048e214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984981907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2984981907
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2202978386
Short name T381
Test name
Test status
Simulation time 394050563 ps
CPU time 0.63 seconds
Started Aug 02 05:19:13 PM PDT 24
Finished Aug 02 05:19:14 PM PDT 24
Peak memory 183896 kb
Host smart-d8f41fef-17ed-4995-b8b1-172bf296b054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202978386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2202978386
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1501072156
Short name T337
Test name
Test status
Simulation time 474757307 ps
CPU time 0.96 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 193032 kb
Host smart-6770468a-1366-4009-a335-04c1f341d19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501072156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1501072156
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.483861439
Short name T362
Test name
Test status
Simulation time 355182568 ps
CPU time 0.65 seconds
Started Aug 02 05:19:09 PM PDT 24
Finished Aug 02 05:19:10 PM PDT 24
Peak memory 183856 kb
Host smart-e027b4ac-36a0-4aa1-a4d3-ee6920cc70c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483861439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.483861439
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3496420713
Short name T330
Test name
Test status
Simulation time 445755242 ps
CPU time 0.62 seconds
Started Aug 02 05:18:54 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 193084 kb
Host smart-c61661b0-c38a-436c-b135-c92c3b92a008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496420713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3496420713
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3918087820
Short name T289
Test name
Test status
Simulation time 381783210 ps
CPU time 1.04 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 193044 kb
Host smart-7849ed42-e87e-454b-9a4a-c62815e7a465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918087820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3918087820
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.215854450
Short name T328
Test name
Test status
Simulation time 372017409 ps
CPU time 0.66 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 193028 kb
Host smart-40c348f0-b673-4e39-a75b-4aefc98cd032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215854450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.215854450
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2864049529
Short name T399
Test name
Test status
Simulation time 582356214 ps
CPU time 1.77 seconds
Started Aug 02 05:19:17 PM PDT 24
Finished Aug 02 05:19:19 PM PDT 24
Peak memory 193208 kb
Host smart-673ff3a5-639b-410b-8b46-7eb0f581ed67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864049529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2864049529
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1934741391
Short name T58
Test name
Test status
Simulation time 1227739506 ps
CPU time 1.03 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 192996 kb
Host smart-6cd091a0-0fb3-4482-9dfd-1501edacfa0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934741391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1934741391
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4017569072
Short name T424
Test name
Test status
Simulation time 342327750 ps
CPU time 1.14 seconds
Started Aug 02 05:18:51 PM PDT 24
Finished Aug 02 05:18:52 PM PDT 24
Peak memory 196208 kb
Host smart-ebcdb461-6687-44d6-9c25-afe84ddf665b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017569072 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4017569072
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3408595069
Short name T34
Test name
Test status
Simulation time 414711788 ps
CPU time 1.21 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 192948 kb
Host smart-e060b42f-7611-4949-93b5-6fe9f9a71efb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408595069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3408595069
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1440958699
Short name T292
Test name
Test status
Simulation time 524454842 ps
CPU time 0.61 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 183816 kb
Host smart-ac84cbf1-3d6c-40c4-a3f6-5b94f52a2ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440958699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1440958699
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1713080635
Short name T396
Test name
Test status
Simulation time 490138453 ps
CPU time 1.12 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:18:45 PM PDT 24
Peak memory 183744 kb
Host smart-1616c3c6-2474-49b8-b4c2-551cc02ff7ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713080635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1713080635
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1534091551
Short name T327
Test name
Test status
Simulation time 451945984 ps
CPU time 0.65 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 183676 kb
Host smart-c3d48a17-89b6-4585-abd1-e5f384bf7b39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534091551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1534091551
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1590702470
Short name T378
Test name
Test status
Simulation time 2203052633 ps
CPU time 7.82 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:47 PM PDT 24
Peak memory 195304 kb
Host smart-9402d233-732b-4f4a-816f-44a5e6d0e98a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590702470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1590702470
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2538445383
Short name T308
Test name
Test status
Simulation time 515138362 ps
CPU time 2.9 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 198616 kb
Host smart-6ba56871-c923-4113-a889-97162269263d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538445383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2538445383
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3315121628
Short name T322
Test name
Test status
Simulation time 5046069489 ps
CPU time 1.26 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 196648 kb
Host smart-d47dcd44-fdd9-46eb-aa2e-a158825975fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315121628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3315121628
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4067342636
Short name T335
Test name
Test status
Simulation time 324324667 ps
CPU time 0.6 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 183752 kb
Host smart-f5c53b9e-faf4-45b6-9fcd-fc3eee9db72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067342636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4067342636
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2975345946
Short name T290
Test name
Test status
Simulation time 494775795 ps
CPU time 0.67 seconds
Started Aug 02 05:19:12 PM PDT 24
Finished Aug 02 05:19:13 PM PDT 24
Peak memory 183816 kb
Host smart-544f4978-e09a-4ec8-a036-eae059de8f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975345946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2975345946
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.598590192
Short name T393
Test name
Test status
Simulation time 477168135 ps
CPU time 1.21 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 193076 kb
Host smart-5a2aaa74-c431-4f2b-a908-4dbc9c5800d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598590192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.598590192
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.963346182
Short name T307
Test name
Test status
Simulation time 483379868 ps
CPU time 1.23 seconds
Started Aug 02 05:18:58 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 193028 kb
Host smart-856292d2-7e53-467f-9937-4ef41eac0951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963346182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.963346182
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1170124916
Short name T385
Test name
Test status
Simulation time 402907552 ps
CPU time 1.08 seconds
Started Aug 02 05:18:48 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 183832 kb
Host smart-a55f8d6c-2716-4f3e-8c37-9ebd806d927c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170124916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1170124916
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1347644497
Short name T347
Test name
Test status
Simulation time 473837258 ps
CPU time 0.7 seconds
Started Aug 02 05:19:05 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 183852 kb
Host smart-9e1a0aa3-d3af-4f1a-b369-35ff19c6f3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347644497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1347644497
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1894875790
Short name T341
Test name
Test status
Simulation time 455365647 ps
CPU time 1.17 seconds
Started Aug 02 05:19:12 PM PDT 24
Finished Aug 02 05:19:13 PM PDT 24
Peak memory 183772 kb
Host smart-e34eb739-fe6c-461d-aaca-e50a4f263ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894875790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1894875790
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.309694198
Short name T344
Test name
Test status
Simulation time 430111381 ps
CPU time 0.68 seconds
Started Aug 02 05:18:45 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 183872 kb
Host smart-a07f11ea-9ffb-4a59-93c5-601695cc6bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309694198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.309694198
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1904407047
Short name T368
Test name
Test status
Simulation time 348214615 ps
CPU time 0.79 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 183828 kb
Host smart-a1305f80-d7b4-41ba-a6b1-b894f5010ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904407047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1904407047
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4074970271
Short name T359
Test name
Test status
Simulation time 452056334 ps
CPU time 1.21 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:04 PM PDT 24
Peak memory 183872 kb
Host smart-0bd1f40b-2521-419a-a0fa-dc9b853a93ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074970271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4074970271
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4256715346
Short name T343
Test name
Test status
Simulation time 400781957 ps
CPU time 1.11 seconds
Started Aug 02 05:18:45 PM PDT 24
Finished Aug 02 05:18:46 PM PDT 24
Peak memory 196180 kb
Host smart-7f41345a-f182-4575-aee3-d760ed58ac17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256715346 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4256715346
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1537816267
Short name T354
Test name
Test status
Simulation time 472906847 ps
CPU time 1.28 seconds
Started Aug 02 05:18:52 PM PDT 24
Finished Aug 02 05:18:54 PM PDT 24
Peak memory 193236 kb
Host smart-729a36f8-581f-4280-bade-a773d9ac58ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537816267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1537816267
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2137157711
Short name T332
Test name
Test status
Simulation time 357100647 ps
CPU time 0.67 seconds
Started Aug 02 05:18:49 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 193024 kb
Host smart-856db759-3f53-4414-ab90-1cd6e579c2da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137157711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2137157711
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.670590134
Short name T75
Test name
Test status
Simulation time 3092190837 ps
CPU time 2.5 seconds
Started Aug 02 05:19:06 PM PDT 24
Finished Aug 02 05:19:08 PM PDT 24
Peak memory 183932 kb
Host smart-97c56472-f8e3-45b2-93b0-c7e79902b7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670590134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.670590134
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1065097533
Short name T315
Test name
Test status
Simulation time 469227402 ps
CPU time 1.67 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:19:01 PM PDT 24
Peak memory 198596 kb
Host smart-d1b1d289-d028-4cd9-b183-0ed556de88d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065097533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1065097533
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2564564185
Short name T358
Test name
Test status
Simulation time 8194240547 ps
CPU time 6.17 seconds
Started Aug 02 05:18:52 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 198396 kb
Host smart-75298a4c-647b-4d77-871c-34d019010d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564564185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2564564185
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3413154330
Short name T414
Test name
Test status
Simulation time 491548024 ps
CPU time 1.39 seconds
Started Aug 02 05:19:04 PM PDT 24
Finished Aug 02 05:19:05 PM PDT 24
Peak memory 195692 kb
Host smart-3e926274-9252-4c66-b7e5-7b371e2275dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413154330 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3413154330
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.374985182
Short name T68
Test name
Test status
Simulation time 328544194 ps
CPU time 0.99 seconds
Started Aug 02 05:18:59 PM PDT 24
Finished Aug 02 05:19:01 PM PDT 24
Peak memory 192972 kb
Host smart-d80fefcc-620c-4d9b-a309-d618dc15ccc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374985182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.374985182
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1374108038
Short name T361
Test name
Test status
Simulation time 513003885 ps
CPU time 0.77 seconds
Started Aug 02 05:18:55 PM PDT 24
Finished Aug 02 05:18:56 PM PDT 24
Peak memory 192972 kb
Host smart-5a618d73-637e-4d6b-84f6-cb150c7613e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374108038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1374108038
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.275975730
Short name T71
Test name
Test status
Simulation time 2771701888 ps
CPU time 1.38 seconds
Started Aug 02 05:19:11 PM PDT 24
Finished Aug 02 05:19:13 PM PDT 24
Peak memory 195232 kb
Host smart-7d157a2e-c7a4-45a7-a68a-46a9ea6a6280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275975730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.275975730
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4219331967
Short name T300
Test name
Test status
Simulation time 659092390 ps
CPU time 1.45 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:44 PM PDT 24
Peak memory 198624 kb
Host smart-5ec69798-b029-4289-91b6-27eb91b51ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219331967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4219331967
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3120375942
Short name T404
Test name
Test status
Simulation time 4313851173 ps
CPU time 5.96 seconds
Started Aug 02 05:18:45 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 198168 kb
Host smart-10c46e3f-7c5d-4761-9691-80f8a9cc8081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120375942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3120375942
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2492235595
Short name T372
Test name
Test status
Simulation time 528178804 ps
CPU time 1.43 seconds
Started Aug 02 05:18:46 PM PDT 24
Finished Aug 02 05:18:48 PM PDT 24
Peak memory 195084 kb
Host smart-ad437d73-b6f4-43c2-951a-3d6b06d983bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492235595 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2492235595
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3864238941
Short name T73
Test name
Test status
Simulation time 330306255 ps
CPU time 0.81 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 193248 kb
Host smart-a079f373-81bb-4a1d-9d50-c4e3ca47403a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864238941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3864238941
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2680511067
Short name T422
Test name
Test status
Simulation time 440663124 ps
CPU time 1.18 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 183824 kb
Host smart-cdc4ad1f-e7cf-46e2-9e17-46488ad12bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680511067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2680511067
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.357209808
Short name T425
Test name
Test status
Simulation time 1065452107 ps
CPU time 1.32 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 193624 kb
Host smart-ba09cb50-e531-4e66-9043-b15df6997821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357209808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.357209808
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3589742044
Short name T321
Test name
Test status
Simulation time 418204030 ps
CPU time 1.33 seconds
Started Aug 02 05:18:57 PM PDT 24
Finished Aug 02 05:18:59 PM PDT 24
Peak memory 198460 kb
Host smart-8d4f6dc2-fc10-4c81-a4ff-d4c6d052e382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589742044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3589742044
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.976108079
Short name T390
Test name
Test status
Simulation time 7789739767 ps
CPU time 6.71 seconds
Started Aug 02 05:19:03 PM PDT 24
Finished Aug 02 05:19:10 PM PDT 24
Peak memory 198448 kb
Host smart-8b9566c3-bb6f-40c6-890b-decda9d208b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976108079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.976108079
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.111603512
Short name T201
Test name
Test status
Simulation time 552428702 ps
CPU time 1.45 seconds
Started Aug 02 05:18:50 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 196688 kb
Host smart-b844548e-f2b5-48c5-b94e-c49a24cff80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111603512 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.111603512
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3806843456
Short name T66
Test name
Test status
Simulation time 430980733 ps
CPU time 0.76 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 194008 kb
Host smart-20560966-36db-41a6-a3a3-cb2d36f34a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806843456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3806843456
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.157215056
Short name T386
Test name
Test status
Simulation time 363825074 ps
CPU time 0.63 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 193000 kb
Host smart-0c7e48ac-5e4f-447c-b914-6300b04c0239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157215056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.157215056
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1370094993
Short name T407
Test name
Test status
Simulation time 1505295664 ps
CPU time 2.7 seconds
Started Aug 02 05:19:04 PM PDT 24
Finished Aug 02 05:19:06 PM PDT 24
Peak memory 193052 kb
Host smart-7ee56f91-4262-4ee6-9cc1-22cc86b6253b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370094993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1370094993
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.904794535
Short name T353
Test name
Test status
Simulation time 618851610 ps
CPU time 1.87 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 198736 kb
Host smart-57064410-e2f1-4dec-93de-e784cbf69b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904794535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.904794535
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2555990404
Short name T35
Test name
Test status
Simulation time 8476334800 ps
CPU time 4.6 seconds
Started Aug 02 05:18:54 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 198532 kb
Host smart-d4bd3a08-3e6c-43c3-ae96-851998c7a112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555990404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2555990404
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1763264505
Short name T199
Test name
Test status
Simulation time 468226018 ps
CPU time 0.84 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:42 PM PDT 24
Peak memory 197560 kb
Host smart-7a6641b7-8a51-483a-a941-446b0c4b48d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763264505 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1763264505
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3479397605
Short name T412
Test name
Test status
Simulation time 357957228 ps
CPU time 1.06 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:42 PM PDT 24
Peak memory 193048 kb
Host smart-d8a9328d-dc71-43a0-a6c7-75b2ece80c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479397605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3479397605
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1955175695
Short name T427
Test name
Test status
Simulation time 323492255 ps
CPU time 0.65 seconds
Started Aug 02 05:18:53 PM PDT 24
Finished Aug 02 05:18:54 PM PDT 24
Peak memory 192996 kb
Host smart-1a3da4ce-1d79-4375-b922-75bc53e3034c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955175695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1955175695
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2513709767
Short name T400
Test name
Test status
Simulation time 2460529598 ps
CPU time 2.04 seconds
Started Aug 02 05:18:58 PM PDT 24
Finished Aug 02 05:19:00 PM PDT 24
Peak memory 194088 kb
Host smart-6069b405-736a-49c6-bed3-43f9c5fb1013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513709767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2513709767
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3107729808
Short name T365
Test name
Test status
Simulation time 563197583 ps
CPU time 2.41 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:50 PM PDT 24
Peak memory 198684 kb
Host smart-37a5eb06-bf94-4b45-aac2-0612fd977c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107729808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3107729808
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.455989167
Short name T410
Test name
Test status
Simulation time 4308662574 ps
CPU time 1.74 seconds
Started Aug 02 05:18:43 PM PDT 24
Finished Aug 02 05:18:45 PM PDT 24
Peak memory 198016 kb
Host smart-e98d1558-616a-48a2-b414-a1d55f985c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455989167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.455989167
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4139232266
Short name T275
Test name
Test status
Simulation time 31610127420 ps
CPU time 10.71 seconds
Started Aug 02 05:17:49 PM PDT 24
Finished Aug 02 05:18:00 PM PDT 24
Peak memory 196932 kb
Host smart-546b42a5-1217-4037-8e44-3fbe326aaf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139232266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4139232266
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1632016198
Short name T254
Test name
Test status
Simulation time 537852218 ps
CPU time 0.69 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 191760 kb
Host smart-f26ee4bc-9eb6-4c68-8bfc-1bc62bd8aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632016198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1632016198
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3987550555
Short name T229
Test name
Test status
Simulation time 9850594692 ps
CPU time 13.94 seconds
Started Aug 02 05:17:59 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 191924 kb
Host smart-f15eed9e-897d-4946-9b6c-3708284abed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987550555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3987550555
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.921350176
Short name T15
Test name
Test status
Simulation time 8145850150 ps
CPU time 6.97 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 215812 kb
Host smart-fdaab983-4fca-42dd-b6f5-284d6abe0c1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921350176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.921350176
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2379253734
Short name T2
Test name
Test status
Simulation time 405855989 ps
CPU time 0.73 seconds
Started Aug 02 05:17:52 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 191812 kb
Host smart-ac3dad98-8759-42a5-a6af-5741c3352f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379253734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2379253734
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4087327234
Short name T44
Test name
Test status
Simulation time 39023648318 ps
CPU time 31.26 seconds
Started Aug 02 05:18:06 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 191884 kb
Host smart-370f6eab-c66d-4b13-8937-cba2b3f3fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087327234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4087327234
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2681396094
Short name T281
Test name
Test status
Simulation time 499009694 ps
CPU time 0.9 seconds
Started Aug 02 05:17:55 PM PDT 24
Finished Aug 02 05:17:56 PM PDT 24
Peak memory 191808 kb
Host smart-3491d680-cf0a-4c59-aa14-836ce545d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681396094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2681396094
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.665544393
Short name T202
Test name
Test status
Simulation time 9260619984 ps
CPU time 13.01 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 191908 kb
Host smart-3e2a2519-87fd-43f9-b72d-6753a81e2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665544393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.665544393
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2864225209
Short name T263
Test name
Test status
Simulation time 397933281 ps
CPU time 1.17 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 191720 kb
Host smart-3d2d60c1-16d3-48f7-bd7f-0a699faa98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864225209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2864225209
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.694630544
Short name T252
Test name
Test status
Simulation time 48824107088 ps
CPU time 15.59 seconds
Started Aug 02 05:18:16 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 191944 kb
Host smart-c1b912d4-c88b-4705-bd7f-b5305aae326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694630544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.694630544
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.656932044
Short name T203
Test name
Test status
Simulation time 470267969 ps
CPU time 0.88 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:18:19 PM PDT 24
Peak memory 191824 kb
Host smart-2b9d83eb-6611-44d8-8a4b-49a6c9317e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656932044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.656932044
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3687036278
Short name T256
Test name
Test status
Simulation time 32885764573 ps
CPU time 31.75 seconds
Started Aug 02 05:18:19 PM PDT 24
Finished Aug 02 05:18:51 PM PDT 24
Peak memory 196924 kb
Host smart-bbb99c6f-c022-4926-9db3-24c6713d862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687036278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3687036278
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.765435737
Short name T287
Test name
Test status
Simulation time 451798136 ps
CPU time 0.84 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 191820 kb
Host smart-ebe261c7-d628-43d8-b58e-63e2609cd0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765435737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.765435737
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2335034612
Short name T78
Test name
Test status
Simulation time 22486837761 ps
CPU time 222.3 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 206728 kb
Host smart-ef558b3f-96e7-4ae7-87e6-1ddf4df18257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335034612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2335034612
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3135955506
Short name T198
Test name
Test status
Simulation time 21633911335 ps
CPU time 8.59 seconds
Started Aug 02 05:18:17 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 196856 kb
Host smart-d656d157-3ead-4d8e-8dd6-3fec93b18a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135955506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3135955506
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.512680795
Short name T279
Test name
Test status
Simulation time 468963702 ps
CPU time 0.94 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 191836 kb
Host smart-dd765c70-089d-402a-9341-884021c06091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512680795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.512680795
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2655547731
Short name T265
Test name
Test status
Simulation time 21302277258 ps
CPU time 34.69 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:18:49 PM PDT 24
Peak memory 191888 kb
Host smart-451cab9a-ce8b-4034-a336-1a280b10326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655547731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2655547731
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1359102643
Short name T222
Test name
Test status
Simulation time 528185971 ps
CPU time 1.3 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 191872 kb
Host smart-5b1583b8-0f5a-4818-9be4-6213a1cff622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359102643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1359102643
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.699531994
Short name T185
Test name
Test status
Simulation time 522603486 ps
CPU time 0.67 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 196620 kb
Host smart-4eb98354-ce58-4528-9641-e447870c33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699531994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.699531994
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1154573070
Short name T230
Test name
Test status
Simulation time 37503110447 ps
CPU time 3.53 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 191900 kb
Host smart-c371a7f3-8c17-41ff-8df4-964b2720d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154573070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1154573070
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3054201454
Short name T217
Test name
Test status
Simulation time 528040577 ps
CPU time 0.73 seconds
Started Aug 02 05:18:15 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 196636 kb
Host smart-6d980f5d-e0ab-4684-8902-5a1e9a2c5493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054201454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3054201454
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3318219903
Short name T189
Test name
Test status
Simulation time 388097492 ps
CPU time 0.88 seconds
Started Aug 02 05:18:22 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 196620 kb
Host smart-8793d7eb-4133-4e66-927c-eaa008a42051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318219903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3318219903
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2040624047
Short name T274
Test name
Test status
Simulation time 23399619157 ps
CPU time 33.87 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:18:47 PM PDT 24
Peak memory 191928 kb
Host smart-e92c203b-6f66-4a01-a437-5be7f3ff61f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040624047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2040624047
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2569370650
Short name T204
Test name
Test status
Simulation time 444385644 ps
CPU time 0.82 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 196624 kb
Host smart-0b0ab6d7-1bf3-404f-bda4-45ff588b6c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569370650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2569370650
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.75597493
Short name T248
Test name
Test status
Simulation time 46012916755 ps
CPU time 4.07 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:18:17 PM PDT 24
Peak memory 191900 kb
Host smart-ea593bdc-6989-481f-9a03-af414d041351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75597493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.75597493
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2706713758
Short name T260
Test name
Test status
Simulation time 438008524 ps
CPU time 0.94 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:12 PM PDT 24
Peak memory 191668 kb
Host smart-23e482a5-63b4-40a9-9bc6-40d17a95f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706713758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2706713758
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4271676002
Short name T165
Test name
Test status
Simulation time 360261125 ps
CPU time 1.07 seconds
Started Aug 02 05:18:21 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 196660 kb
Host smart-c0887440-b9dc-4d47-a489-5b204bad6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271676002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4271676002
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3247236565
Short name T238
Test name
Test status
Simulation time 13447233224 ps
CPU time 5.66 seconds
Started Aug 02 05:18:16 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 191876 kb
Host smart-9a142df6-f1be-47b4-be75-4b550f422625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247236565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3247236565
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2768781007
Short name T231
Test name
Test status
Simulation time 615186894 ps
CPU time 0.76 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:35 PM PDT 24
Peak memory 191876 kb
Host smart-ba61f979-ef10-4bf2-9d2b-84429d42cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768781007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2768781007
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3107101890
Short name T220
Test name
Test status
Simulation time 20134125352 ps
CPU time 6.62 seconds
Started Aug 02 05:17:51 PM PDT 24
Finished Aug 02 05:17:58 PM PDT 24
Peak memory 191928 kb
Host smart-d526cc71-7032-405a-9814-510b1dbed0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107101890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3107101890
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.273284392
Short name T17
Test name
Test status
Simulation time 7835459210 ps
CPU time 3.44 seconds
Started Aug 02 05:18:10 PM PDT 24
Finished Aug 02 05:18:14 PM PDT 24
Peak memory 215856 kb
Host smart-5fb22425-f425-465d-b374-c60b0b8547ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273284392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.273284392
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3861048440
Short name T216
Test name
Test status
Simulation time 486735506 ps
CPU time 1.19 seconds
Started Aug 02 05:18:07 PM PDT 24
Finished Aug 02 05:18:08 PM PDT 24
Peak memory 191912 kb
Host smart-e9a9f9ab-44e9-4009-99de-d628f6f27051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861048440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3861048440
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.697568589
Short name T282
Test name
Test status
Simulation time 44056577842 ps
CPU time 9.16 seconds
Started Aug 02 05:18:09 PM PDT 24
Finished Aug 02 05:18:18 PM PDT 24
Peak memory 191952 kb
Host smart-f2d338a1-f35b-446b-b340-89669e1fb4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697568589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.697568589
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3192350248
Short name T280
Test name
Test status
Simulation time 397030444 ps
CPU time 0.89 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 191860 kb
Host smart-c97ae75d-12cf-4cd7-b417-1549a5ee71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192350248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3192350248
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2960324318
Short name T40
Test name
Test status
Simulation time 34064123702 ps
CPU time 176.11 seconds
Started Aug 02 05:18:18 PM PDT 24
Finished Aug 02 05:21:14 PM PDT 24
Peak memory 206708 kb
Host smart-0e4aa315-1afe-41d0-b1b3-f2f11caedc9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960324318 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2960324318
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.335898297
Short name T221
Test name
Test status
Simulation time 11455513169 ps
CPU time 4.55 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 196868 kb
Host smart-de2b2c5e-167c-418b-8398-a3cbbbe2062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335898297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.335898297
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1872623800
Short name T4
Test name
Test status
Simulation time 583182146 ps
CPU time 0.63 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:30 PM PDT 24
Peak memory 196636 kb
Host smart-64617d0f-7481-445e-9386-a0dadb39478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872623800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1872623800
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.4278890560
Short name T269
Test name
Test status
Simulation time 7300626166 ps
CPU time 11.98 seconds
Started Aug 02 05:18:10 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 191896 kb
Host smart-84fe36aa-4aae-434c-bb06-d28ec62da125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278890560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4278890560
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1762977593
Short name T228
Test name
Test status
Simulation time 438202949 ps
CPU time 1.25 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:24 PM PDT 24
Peak memory 191836 kb
Host smart-c49c854d-cd66-4231-a8f3-9bb5c541d56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762977593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1762977593
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.730025279
Short name T10
Test name
Test status
Simulation time 28209469879 ps
CPU time 10.01 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 196928 kb
Host smart-414b6679-e5bf-415c-988b-f83fb94f9b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730025279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.730025279
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.998197457
Short name T212
Test name
Test status
Simulation time 397611220 ps
CPU time 0.79 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 191908 kb
Host smart-0d2668a6-30e7-4415-bdf3-f5563bbd0031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998197457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.998197457
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1571154744
Short name T227
Test name
Test status
Simulation time 50359030267 ps
CPU time 435.38 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:25:40 PM PDT 24
Peak memory 200348 kb
Host smart-7444fea8-7dfa-4129-a83e-e0629402cf3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571154744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1571154744
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.216713786
Short name T211
Test name
Test status
Simulation time 54936629514 ps
CPU time 75.14 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:19:53 PM PDT 24
Peak memory 196956 kb
Host smart-10d29079-e606-4ff5-b94d-88f759763630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216713786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.216713786
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1512598735
Short name T219
Test name
Test status
Simulation time 608052237 ps
CPU time 0.77 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 191812 kb
Host smart-4702e2af-fb7a-47a3-9baf-d18ca0915c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512598735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1512598735
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2569498969
Short name T259
Test name
Test status
Simulation time 37191858553 ps
CPU time 13.68 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 196964 kb
Host smart-a0fe85fa-ec65-481d-b226-d1dddce6509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569498969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2569498969
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3775881232
Short name T251
Test name
Test status
Simulation time 554836341 ps
CPU time 0.79 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:23 PM PDT 24
Peak memory 191888 kb
Host smart-515e930f-0cc7-4fa8-91b4-5523f022d2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775881232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3775881232
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1284639180
Short name T223
Test name
Test status
Simulation time 44643614821 ps
CPU time 67.75 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:19:38 PM PDT 24
Peak memory 191892 kb
Host smart-7247e318-77d3-421f-a432-cb9001e653a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284639180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1284639180
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3891000784
Short name T5
Test name
Test status
Simulation time 604069317 ps
CPU time 0.65 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 191808 kb
Host smart-b5f50e04-92a5-45fa-ba5d-cae369c6be5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891000784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3891000784
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4012816487
Short name T255
Test name
Test status
Simulation time 32723843355 ps
CPU time 21.09 seconds
Started Aug 02 05:18:16 PM PDT 24
Finished Aug 02 05:18:37 PM PDT 24
Peak memory 191924 kb
Host smart-d2dfc5a4-ba8d-4007-b1c9-50b55417cc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012816487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4012816487
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.931229815
Short name T23
Test name
Test status
Simulation time 346027909 ps
CPU time 0.85 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 191880 kb
Host smart-0e3dcac6-3548-4c80-b501-3fcf0aa29d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931229815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.931229815
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2139860910
Short name T3
Test name
Test status
Simulation time 117957920137 ps
CPU time 82.6 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:19:47 PM PDT 24
Peak memory 198256 kb
Host smart-a10a2c7c-0b65-42fd-8be5-eef53990bba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139860910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2139860910
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.340394244
Short name T164
Test name
Test status
Simulation time 566937326 ps
CPU time 0.72 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:24 PM PDT 24
Peak memory 196740 kb
Host smart-6485d67d-ec7a-4eb6-9799-73286028f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340394244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.340394244
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1661088881
Short name T232
Test name
Test status
Simulation time 28922874960 ps
CPU time 22.08 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 196940 kb
Host smart-d3e9abd8-b79e-4245-901c-9e6bd2cf5aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661088881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1661088881
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.668819928
Short name T261
Test name
Test status
Simulation time 452743913 ps
CPU time 1.24 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 196648 kb
Host smart-12597433-8669-4748-8d01-a04b04b65250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668819928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.668819928
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.26271862
Short name T244
Test name
Test status
Simulation time 39125025861 ps
CPU time 54.24 seconds
Started Aug 02 05:18:21 PM PDT 24
Finished Aug 02 05:19:16 PM PDT 24
Peak memory 196916 kb
Host smart-2ee9437c-7e53-4b47-aad6-0873cb756bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26271862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.26271862
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2382780477
Short name T267
Test name
Test status
Simulation time 356506083 ps
CPU time 0.85 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:18:25 PM PDT 24
Peak memory 191756 kb
Host smart-182235c6-7f2d-4fe1-bf72-1197f588675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382780477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2382780477
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.212848605
Short name T276
Test name
Test status
Simulation time 28630984792 ps
CPU time 19.13 seconds
Started Aug 02 05:18:00 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 196928 kb
Host smart-91af40ac-8bf9-4ab2-a0d1-fdaf453c3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212848605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.212848605
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4236691805
Short name T16
Test name
Test status
Simulation time 3978451761 ps
CPU time 6.47 seconds
Started Aug 02 05:18:12 PM PDT 24
Finished Aug 02 05:18:19 PM PDT 24
Peak memory 215468 kb
Host smart-50cdfa7c-a798-4b1a-afb8-9452f3a36b35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236691805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4236691805
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1953444938
Short name T53
Test name
Test status
Simulation time 589844502 ps
CPU time 1.34 seconds
Started Aug 02 05:18:08 PM PDT 24
Finished Aug 02 05:18:09 PM PDT 24
Peak memory 191816 kb
Host smart-649a8c3f-3968-4d1b-8c4c-1865c022e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953444938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1953444938
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1789230974
Short name T209
Test name
Test status
Simulation time 7008945260 ps
CPU time 2.3 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 191888 kb
Host smart-d156580f-24e9-4fb8-bfcf-1ef6ee9db49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789230974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1789230974
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1677880739
Short name T7
Test name
Test status
Simulation time 597330241 ps
CPU time 0.89 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 196672 kb
Host smart-6a36abaa-293b-4ee6-9dc0-aa9c8d20a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677880739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1677880739
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3992187376
Short name T213
Test name
Test status
Simulation time 43903206525 ps
CPU time 36.77 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:19:18 PM PDT 24
Peak memory 196900 kb
Host smart-570c5f7e-bd18-4a74-a2e0-34bf8226f7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992187376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3992187376
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2529992508
Short name T247
Test name
Test status
Simulation time 644554415 ps
CPU time 0.71 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 191876 kb
Host smart-2fc19e85-b87f-41fb-b8bf-3aa3bb05563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529992508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2529992508
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2000449388
Short name T19
Test name
Test status
Simulation time 10632306772 ps
CPU time 14.14 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 191972 kb
Host smart-75ed1409-f769-422e-bee6-69c652101413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000449388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2000449388
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.620936151
Short name T277
Test name
Test status
Simulation time 487433862 ps
CPU time 0.76 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:27 PM PDT 24
Peak memory 191864 kb
Host smart-44e4cbc3-8797-4a96-b90d-c25a93ad0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620936151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.620936151
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3576730705
Short name T6
Test name
Test status
Simulation time 49461986644 ps
CPU time 16.61 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:18:41 PM PDT 24
Peak memory 196920 kb
Host smart-2d59d802-a78e-4c61-bffc-b27e8e231f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576730705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3576730705
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1292424124
Short name T22
Test name
Test status
Simulation time 588908523 ps
CPU time 0.64 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 196660 kb
Host smart-26af0d40-d974-4a4b-99bf-2a84ef9c0aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292424124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1292424124
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.660444122
Short name T270
Test name
Test status
Simulation time 49906320903 ps
CPU time 75.87 seconds
Started Aug 02 05:18:13 PM PDT 24
Finished Aug 02 05:19:29 PM PDT 24
Peak memory 191924 kb
Host smart-7ce18e83-c399-4cc9-94a2-67026e90d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660444122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.660444122
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4124254169
Short name T225
Test name
Test status
Simulation time 580105170 ps
CPU time 0.8 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 196656 kb
Host smart-0c9ce05a-362a-46f1-baaa-4fa9932cce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124254169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4124254169
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4079597155
Short name T48
Test name
Test status
Simulation time 60891980191 ps
CPU time 8.32 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 196904 kb
Host smart-8421d03f-9968-4d76-b2f7-42cf3f3b70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079597155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4079597155
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1557972848
Short name T283
Test name
Test status
Simulation time 392698004 ps
CPU time 0.69 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 191840 kb
Host smart-48b58412-f58d-4db6-b5ec-5cd9ba08ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557972848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1557972848
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2411162953
Short name T237
Test name
Test status
Simulation time 19901995777 ps
CPU time 31 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:19:08 PM PDT 24
Peak memory 191900 kb
Host smart-58c3eec2-4215-4365-b490-ae0c9e4050e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411162953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2411162953
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1986621222
Short name T240
Test name
Test status
Simulation time 592084184 ps
CPU time 0.98 seconds
Started Aug 02 05:18:47 PM PDT 24
Finished Aug 02 05:18:48 PM PDT 24
Peak memory 196664 kb
Host smart-9432d5a3-d516-48f9-8bef-04386f768804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986621222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1986621222
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3109310311
Short name T253
Test name
Test status
Simulation time 50272594942 ps
CPU time 19 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:58 PM PDT 24
Peak memory 191908 kb
Host smart-9dc86049-1e7e-437c-b764-879afaf4de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109310311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3109310311
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1244267382
Short name T210
Test name
Test status
Simulation time 523895312 ps
CPU time 0.62 seconds
Started Aug 02 05:18:33 PM PDT 24
Finished Aug 02 05:18:34 PM PDT 24
Peak memory 191908 kb
Host smart-f3850070-a84e-48d3-adbb-cd3e70f65dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244267382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1244267382
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2855600062
Short name T239
Test name
Test status
Simulation time 39601535319 ps
CPU time 51.91 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:19:22 PM PDT 24
Peak memory 191888 kb
Host smart-251aba06-51fd-4034-9d45-49fdb27c6cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855600062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2855600062
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3980325665
Short name T266
Test name
Test status
Simulation time 528983455 ps
CPU time 0.59 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:18:37 PM PDT 24
Peak memory 191816 kb
Host smart-be6c19ee-d80e-4cc3-87e6-b066914c827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980325665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3980325665
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1465385241
Short name T241
Test name
Test status
Simulation time 10493171723 ps
CPU time 84.88 seconds
Started Aug 02 05:18:40 PM PDT 24
Finished Aug 02 05:20:05 PM PDT 24
Peak memory 206736 kb
Host smart-dae5cb77-9dcb-488a-8bd5-87a2a058e546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465385241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1465385241
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2765261466
Short name T235
Test name
Test status
Simulation time 32447583826 ps
CPU time 24.33 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:19:01 PM PDT 24
Peak memory 191972 kb
Host smart-cb4d2593-0fc5-4843-b3a9-aa47fda1548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765261466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2765261466
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3737347831
Short name T205
Test name
Test status
Simulation time 528982046 ps
CPU time 0.94 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 191832 kb
Host smart-ccb342a5-cd38-48dc-8617-338960ec94cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737347831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3737347831
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2193235319
Short name T207
Test name
Test status
Simulation time 30075878505 ps
CPU time 5.38 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 191932 kb
Host smart-897df859-5e55-423d-9b05-3c5a70cf8a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193235319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2193235319
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2839485715
Short name T14
Test name
Test status
Simulation time 7900258401 ps
CPU time 2.51 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 215876 kb
Host smart-3c16544e-7528-42ee-9190-75e8dd48e30b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839485715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2839485715
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2213325064
Short name T278
Test name
Test status
Simulation time 523230619 ps
CPU time 0.73 seconds
Started Aug 02 05:18:20 PM PDT 24
Finished Aug 02 05:18:20 PM PDT 24
Peak memory 191828 kb
Host smart-79fa6fef-dff5-4c82-901f-830ecd978581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213325064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2213325064
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1857822879
Short name T233
Test name
Test status
Simulation time 33581334877 ps
CPU time 10.78 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 196940 kb
Host smart-7b1b1be6-328a-48ba-9e7f-69ba2a0e9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857822879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1857822879
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.430262660
Short name T246
Test name
Test status
Simulation time 618580611 ps
CPU time 0.78 seconds
Started Aug 02 05:18:35 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 191828 kb
Host smart-440bbaf3-de7b-4d75-8663-563b8f82bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430262660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.430262660
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.438540068
Short name T166
Test name
Test status
Simulation time 367060136 ps
CPU time 0.72 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 196724 kb
Host smart-38d59807-d9d5-4dc2-bda4-5e2ecdd0ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438540068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.438540068
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1293114036
Short name T262
Test name
Test status
Simulation time 857951765 ps
CPU time 0.88 seconds
Started Aug 02 05:18:37 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 191868 kb
Host smart-31c7b309-7e57-4223-979b-617ad2313e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293114036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1293114036
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1775014617
Short name T208
Test name
Test status
Simulation time 388892825 ps
CPU time 0.64 seconds
Started Aug 02 05:18:39 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 191828 kb
Host smart-b04c3a75-3683-47f0-9168-235cf934754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775014617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1775014617
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2535128580
Short name T245
Test name
Test status
Simulation time 46521126707 ps
CPU time 57.07 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:19:25 PM PDT 24
Peak memory 191904 kb
Host smart-866383da-a448-4619-8e99-839dcddeecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535128580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2535128580
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1939994088
Short name T264
Test name
Test status
Simulation time 424873800 ps
CPU time 0.7 seconds
Started Aug 02 05:18:28 PM PDT 24
Finished Aug 02 05:18:29 PM PDT 24
Peak memory 191844 kb
Host smart-60bd871a-42fa-4595-bb1a-49c2d8fd9f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939994088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1939994088
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.528983703
Short name T273
Test name
Test status
Simulation time 75196083548 ps
CPU time 18.59 seconds
Started Aug 02 05:18:34 PM PDT 24
Finished Aug 02 05:18:53 PM PDT 24
Peak memory 191916 kb
Host smart-60660bdb-5e75-48c2-9219-158aab329a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528983703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.528983703
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.72187911
Short name T215
Test name
Test status
Simulation time 35163568442 ps
CPU time 53.2 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:19:26 PM PDT 24
Peak memory 191904 kb
Host smart-a7b915df-0042-463f-89d2-663079861d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72187911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.72187911
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2920439259
Short name T218
Test name
Test status
Simulation time 598438040 ps
CPU time 1 seconds
Started Aug 02 05:18:36 PM PDT 24
Finished Aug 02 05:18:37 PM PDT 24
Peak memory 196660 kb
Host smart-55ed7371-bf9b-4826-9847-a1c4f759bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920439259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2920439259
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1895004239
Short name T177
Test name
Test status
Simulation time 197808809578 ps
CPU time 61.29 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:19:34 PM PDT 24
Peak memory 191920 kb
Host smart-cf66387b-850c-47af-9b6f-0268f9e16368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895004239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1895004239
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3271622833
Short name T288
Test name
Test status
Simulation time 11097007270 ps
CPU time 15.01 seconds
Started Aug 02 05:18:27 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 191888 kb
Host smart-4d641a08-624a-4f4d-854d-31a985c171bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271622833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3271622833
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.603381685
Short name T268
Test name
Test status
Simulation time 417367112 ps
CPU time 1.24 seconds
Started Aug 02 05:18:32 PM PDT 24
Finished Aug 02 05:18:33 PM PDT 24
Peak memory 196664 kb
Host smart-a088422d-fc64-44fa-a19b-e93147f7a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603381685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.603381685
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3559368258
Short name T272
Test name
Test status
Simulation time 16638214795 ps
CPU time 13.74 seconds
Started Aug 02 05:18:44 PM PDT 24
Finished Aug 02 05:18:57 PM PDT 24
Peak memory 191908 kb
Host smart-b248b76f-6e3e-40e5-af1d-2263f94b0adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559368258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3559368258
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4255517743
Short name T258
Test name
Test status
Simulation time 552854690 ps
CPU time 1.02 seconds
Started Aug 02 05:18:30 PM PDT 24
Finished Aug 02 05:18:31 PM PDT 24
Peak memory 191844 kb
Host smart-1add6b9f-8c0b-48f6-9362-6742cc536cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255517743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4255517743
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3588950441
Short name T224
Test name
Test status
Simulation time 17119984813 ps
CPU time 24.48 seconds
Started Aug 02 05:18:31 PM PDT 24
Finished Aug 02 05:18:55 PM PDT 24
Peak memory 191876 kb
Host smart-13a47760-e234-4311-a0ff-fa453752feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588950441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3588950441
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1654944300
Short name T197
Test name
Test status
Simulation time 379698280 ps
CPU time 0.71 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 191852 kb
Host smart-d0b98773-522c-460a-9a14-f9f9281bfaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654944300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1654944300
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3668033438
Short name T249
Test name
Test status
Simulation time 14665146876 ps
CPU time 10.82 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:40 PM PDT 24
Peak memory 191892 kb
Host smart-88e016cc-dd5b-4552-8206-020241b94be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668033438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3668033438
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4019609818
Short name T214
Test name
Test status
Simulation time 484913102 ps
CPU time 0.66 seconds
Started Aug 02 05:18:35 PM PDT 24
Finished Aug 02 05:18:36 PM PDT 24
Peak memory 191876 kb
Host smart-0487dabb-fccc-4876-ba26-ce9b23c02e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019609818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4019609818
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.320687808
Short name T43
Test name
Test status
Simulation time 28864092628 ps
CPU time 40.63 seconds
Started Aug 02 05:18:46 PM PDT 24
Finished Aug 02 05:19:27 PM PDT 24
Peak memory 196924 kb
Host smart-5900e53e-ec93-4a7b-b874-54f9aec78148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320687808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.320687808
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4166863810
Short name T271
Test name
Test status
Simulation time 343957231 ps
CPU time 1.13 seconds
Started Aug 02 05:18:41 PM PDT 24
Finished Aug 02 05:18:42 PM PDT 24
Peak memory 196688 kb
Host smart-fe01d817-74a3-48f7-8c98-21555abc5caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166863810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4166863810
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2483625931
Short name T236
Test name
Test status
Simulation time 14640807300 ps
CPU time 6.56 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:32 PM PDT 24
Peak memory 191208 kb
Host smart-eae0c4e1-4ff1-468d-a640-bd79402d750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483625931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2483625931
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.716106506
Short name T242
Test name
Test status
Simulation time 401921850 ps
CPU time 0.7 seconds
Started Aug 02 05:18:38 PM PDT 24
Finished Aug 02 05:18:39 PM PDT 24
Peak memory 196728 kb
Host smart-cad6bbf6-ef2e-4f29-a05d-268763772469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716106506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.716106506
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.174284476
Short name T26
Test name
Test status
Simulation time 10866798263 ps
CPU time 15.1 seconds
Started Aug 02 05:18:29 PM PDT 24
Finished Aug 02 05:18:44 PM PDT 24
Peak memory 191976 kb
Host smart-eba16c91-c426-49e1-8e47-bce9923089c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174284476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.174284476
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3500323913
Short name T243
Test name
Test status
Simulation time 550337189 ps
CPU time 1.25 seconds
Started Aug 02 05:18:42 PM PDT 24
Finished Aug 02 05:18:43 PM PDT 24
Peak memory 196640 kb
Host smart-9b7e2423-4787-4c75-83b1-ead6288477e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500323913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3500323913
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3114303326
Short name T186
Test name
Test status
Simulation time 511336259 ps
CPU time 0.79 seconds
Started Aug 02 05:18:24 PM PDT 24
Finished Aug 02 05:18:25 PM PDT 24
Peak memory 196572 kb
Host smart-1dfec7f2-eda8-4722-8497-fe59b79bd877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114303326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3114303326
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1150348523
Short name T257
Test name
Test status
Simulation time 26636887978 ps
CPU time 4.09 seconds
Started Aug 02 05:18:11 PM PDT 24
Finished Aug 02 05:18:16 PM PDT 24
Peak memory 191804 kb
Host smart-96913fb6-2a72-43fb-9545-a5e3b50c305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150348523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1150348523
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3385662101
Short name T284
Test name
Test status
Simulation time 514120699 ps
CPU time 0.77 seconds
Started Aug 02 05:18:14 PM PDT 24
Finished Aug 02 05:18:15 PM PDT 24
Peak memory 191884 kb
Host smart-8042d0f0-1844-4b26-889d-7a4698c01c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385662101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3385662101
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3078973765
Short name T250
Test name
Test status
Simulation time 31364045637 ps
CPU time 11.36 seconds
Started Aug 02 05:18:26 PM PDT 24
Finished Aug 02 05:18:37 PM PDT 24
Peak memory 191912 kb
Host smart-814f2738-de94-44a8-8fcb-5a6b2827fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078973765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3078973765
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1002550595
Short name T234
Test name
Test status
Simulation time 493623187 ps
CPU time 1.27 seconds
Started Aug 02 05:18:05 PM PDT 24
Finished Aug 02 05:18:07 PM PDT 24
Peak memory 196692 kb
Host smart-8fa62417-5664-4e17-9f68-aef4c8e651e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002550595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1002550595
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4162740628
Short name T206
Test name
Test status
Simulation time 22835776350 ps
CPU time 18.09 seconds
Started Aug 02 05:18:04 PM PDT 24
Finished Aug 02 05:18:22 PM PDT 24
Peak memory 196904 kb
Host smart-cd15c544-b44d-4c91-b2e5-fda77208714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162740628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4162740628
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3931790838
Short name T286
Test name
Test status
Simulation time 540529444 ps
CPU time 0.61 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:24 PM PDT 24
Peak memory 191800 kb
Host smart-4c23d050-c532-478e-9f97-75f2e9fbf865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931790838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3931790838
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2009519227
Short name T188
Test name
Test status
Simulation time 405604354 ps
CPU time 1.16 seconds
Started Aug 02 05:18:25 PM PDT 24
Finished Aug 02 05:18:26 PM PDT 24
Peak memory 196616 kb
Host smart-b45e8619-c367-4954-b86d-6cdbb3ecb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009519227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2009519227
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.208705965
Short name T285
Test name
Test status
Simulation time 13807965584 ps
CPU time 18.92 seconds
Started Aug 02 05:18:23 PM PDT 24
Finished Aug 02 05:18:42 PM PDT 24
Peak memory 191912 kb
Host smart-cd554b4f-25c4-4951-8700-c1ac3466e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208705965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.208705965
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2488763909
Short name T226
Test name
Test status
Simulation time 345990603 ps
CPU time 1.09 seconds
Started Aug 02 05:17:58 PM PDT 24
Finished Aug 02 05:17:59 PM PDT 24
Peak memory 191848 kb
Host smart-88474901-c2b5-410e-bfcc-f204b620d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488763909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2488763909
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%