Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29474	1		T3	10		T4	210		T6	10
bark[1]	795	1		T11	40		T12	21		T31	21
bark[2]	357	1		T11	43		T17	30		T171	48
bark[3]	242	1		T17	40		T82	94		T22	21
bark[4]	811	1		T8	14		T31	222		T89	57
bark[5]	602	1		T7	39		T48	14		T147	21
bark[6]	257	1		T11	5		T30	21		T39	21
bark[7]	605	1		T36	260		T180	14		T188	14
bark[8]	650	1		T4	19		T9	197		T40	35
bark[9]	699	1		T50	14		T22	21		T107	26
bark[10]	655	1		T7	43		T38	251		T55	47
bark[11]	458	1		T5	14		T9	21		T17	21
bark[12]	323	1		T138	14		T50	21		T109	59
bark[13]	317	1		T143	26		T135	51		T130	26
bark[14]	246	1		T12	21		T38	35		T53	14
bark[15]	716	1		T45	14		T171	21		T138	21
bark[16]	664	1		T2	14		T31	93		T166	14
bark[17]	907	1		T1	14		T9	251		T166	92
bark[18]	699	1		T17	21		T48	39		T49	21
bark[19]	312	1		T7	21		T12	42		T26	21
bark[20]	860	1		T31	44		T48	21		T81	21
bark[21]	370	1		T171	21		T95	26		T82	43
bark[22]	654	1		T31	21		T97	14		T88	248
bark[23]	469	1		T48	21		T49	21		T87	43
bark[24]	671	1		T4	21		T46	14		T138	26
bark[25]	248	1		T37	21		T49	21		T81	28
bark[26]	419	1		T12	14		T17	21		T152	14
bark[27]	392	1		T138	26		T37	52		T38	21
bark[28]	523	1		T12	21		T170	14		T107	209
bark[29]	508	1		T4	21		T7	74		T12	21
bark[30]	250	1		T36	64		T37	21		T40	31
bark[31]	565	1		T189	14		T84	7		T20	21
bark_0	4781	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29324	1		T3	9		T4	210		T6	9
bite[1]	498	1		T9	21		T88	21		T89	56
bite[2]	604	1		T11	4		T12	21		T30	63
bite[3]	153	1		T50	21		T111	13		T112	13
bite[4]	621	1		T1	13		T12	42		T37	21
bite[5]	505	1		T11	25		T37	21		T136	13
bite[6]	917	1		T36	259		T39	142		T50	42
bite[7]	840	1		T7	21		T12	21		T40	35
bite[8]	700	1		T31	221		T17	21		T36	63
bite[9]	690	1		T166	13		T83	85		T84	6
bite[10]	414	1		T8	13		T17	30		T189	13
bite[11]	287	1		T31	21		T49	21		T82	93
bite[12]	453	1		T138	13		T48	13		T125	21
bite[13]	456	1		T46	13		T38	250		T129	21
bite[14]	320	1		T7	73		T17	21		T138	26
bite[15]	265	1		T48	21		T49	21		T50	13
bite[16]	246	1		T49	21		T82	59		T83	21
bite[17]	790	1		T4	21		T17	40		T138	26
bite[18]	346	1		T171	21		T48	21		T180	13
bite[19]	570	1		T30	21		T36	94		T38	21
bite[20]	208	1		T4	18		T12	21		T143	13
bite[21]	485	1		T4	21		T168	13		T48	21
bite[22]	628	1		T11	42		T79	13		T37	51
bite[23]	351	1		T171	21		T166	92		T81	21
bite[24]	780	1		T7	39		T9	250		T31	21
bite[25]	630	1		T45	13		T49	42		T52	13
bite[26]	215	1		T12	21		T138	21		T22	21
bite[27]	506	1		T87	42		T98	21		T90	21
bite[28]	851	1		T2	13		T9	196		T12	13
bite[29]	516	1		T7	42		T31	43		T17	21
bite[30]	260	1		T11	40		T143	25		T86	65
bite[31]	797	1		T5	13		T171	47		T95	21
bite_0	5273	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	41451	1		T1	21		T2	21		T3	17
auto[1]	9048	1		T4	77		T9	230		T11	66

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	855	1		T36	40		T38	59		T39	36
prescale[1]	878	1		T38	117		T55	26		T109	47
prescale[2]	934	1		T7	24		T11	40		T31	111
prescale[3]	893	1		T31	36		T203	9		T166	42
prescale[4]	566	1		T30	199		T187	46		T36	2
prescale[5]	533	1		T204	9		T30	9		T81	2
prescale[6]	570	1		T9	98		T39	2		T88	36
prescale[7]	618	1		T4	28		T9	83		T17	23
prescale[8]	755	1		T9	2		T42	9		T38	56
prescale[9]	799	1		T9	19		T11	2		T31	41
prescale[10]	599	1		T11	19		T31	2		T205	9
prescale[11]	856	1		T30	47		T31	4		T187	95
prescale[12]	854	1		T7	9		T9	75		T12	65
prescale[13]	1085	1		T4	72		T30	28		T38	45
prescale[14]	991	1		T7	19		T9	9		T31	19
prescale[15]	996	1		T31	85		T17	19		T206	9
prescale[16]	943	1		T9	23		T207	9		T208	9
prescale[17]	915	1		T48	23		T49	9		T55	54
prescale[18]	619	1		T4	37		T31	56		T36	19
prescale[19]	863	1		T7	2		T11	21		T17	19
prescale[20]	697	1		T4	19		T9	40		T37	83
prescale[21]	389	1		T9	19		T11	2		T36	2
prescale[22]	634	1		T36	2		T138	28		T39	23
prescale[23]	519	1		T30	21		T166	19		T38	45
prescale[24]	617	1		T11	2		T171	66		T37	2
prescale[25]	325	1		T13	9		T30	2		T187	26
prescale[26]	810	1		T17	38		T49	19		T83	75
prescale[27]	738	1		T7	2		T11	108		T138	23
prescale[28]	610	1		T30	100		T37	28		T82	2
prescale[29]	894	1		T36	2		T39	2		T40	36
prescale[30]	546	1		T7	2		T9	78		T10	9
prescale[31]	481	1		T9	19		T81	2		T82	19
prescale_0	27117	1		T1	21		T2	21		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36855	1		T1	21		T2	9		T3	17
auto[1]	13644	1		T2	12		T4	176		T5	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50499	1		T1	21		T2	21		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	29058	1		T1	1		T2	1		T3	12
wkup[1]	198	1		T25	21		T107	21		T121	21
wkup[2]	193	1		T9	21		T138	21		T88	21
wkup[3]	198	1		T166	15		T81	21		T26	21
wkup[4]	221	1		T36	21		T171	21		T88	21
wkup[5]	360	1		T4	21		T9	21		T11	21
wkup[6]	341	1		T12	15		T49	21		T50	21
wkup[7]	245	1		T8	15		T12	21		T79	15
wkup[8]	164	1		T30	21		T48	21		T88	21
wkup[9]	283	1		T166	35		T37	42		T55	35
wkup[10]	151	1		T55	21		T88	47		T175	26
wkup[11]	213	1		T55	21		T95	21		T107	21
wkup[12]	257	1		T9	21		T11	6		T31	26
wkup[13]	187	1		T30	21		T88	26		T83	23
wkup[14]	376	1		T30	8		T87	21		T97	15
wkup[15]	210	1		T48	39		T49	21		T109	15
wkup[16]	287	1		T7	21		T9	21		T38	21
wkup[17]	394	1		T31	47		T187	21		T138	26
wkup[18]	277	1		T7	21		T55	8		T82	21
wkup[19]	454	1		T7	26		T30	21		T95	8
wkup[20]	535	1		T38	8		T82	21		T83	21
wkup[21]	231	1		T5	15		T83	21		T20	48
wkup[22]	225	1		T11	21		T30	42		T83	21
wkup[23]	131	1		T36	21		T82	26		T116	21
wkup[24]	239	1		T4	21		T12	21		T31	21
wkup[25]	277	1		T2	15		T7	39		T11	21
wkup[26]	316	1		T4	20		T36	21		T88	42
wkup[27]	306	1		T12	21		T46	15		T17	21
wkup[28]	323	1		T30	21		T40	21		T88	24
wkup[29]	297	1		T38	51		T88	36		T83	21
wkup[30]	286	1		T7	21		T30	21		T52	15
wkup[31]	281	1		T11	26		T36	30		T38	51
wkup[32]	198	1		T189	15		T168	15		T129	21
wkup[33]	417	1		T9	21		T31	8		T17	21
wkup[34]	203	1		T4	21		T82	30		T136	15
wkup[35]	197	1		T49	21		T50	21		T130	21
wkup[36]	312	1		T11	21		T36	21		T38	47
wkup[37]	215	1		T36	42		T25	30		T104	42
wkup[38]	328	1		T37	21		T48	21		T88	21
wkup[39]	291	1		T7	21		T12	21		T38	21
wkup[40]	429	1		T7	35		T11	30		T37	21
wkup[41]	203	1		T9	51		T12	21		T187	21
wkup[42]	245	1		T95	26		T83	21		T177	21
wkup[43]	289	1		T17	21		T138	26		T88	21
wkup[44]	327	1		T1	15		T88	30		T125	33
wkup[45]	275	1		T30	21		T171	21		T88	21
wkup[46]	243	1		T39	21		T53	15		T88	21
wkup[47]	353	1		T45	15		T17	21		T89	26
wkup[48]	176	1		T31	26		T40	21		T82	21
wkup[49]	236	1		T38	21		T55	21		T81	47
wkup[50]	251	1		T7	21		T82	21		T26	15
wkup[51]	404	1		T152	15		T171	21		T38	21
wkup[52]	359	1		T30	21		T31	21		T40	35
wkup[53]	266	1		T9	51		T48	21		T82	21
wkup[54]	357	1		T11	40		T171	21		T38	35
wkup[55]	275	1		T9	8		T50	21		T88	26
wkup[56]	349	1		T17	30		T171	21		T37	21
wkup[57]	271	1		T171	21		T38	21		T48	21
wkup[58]	261	1		T55	21		T82	21		T88	21
wkup[59]	270	1		T138	15		T37	30		T129	21
wkup[60]	467	1		T9	42		T30	21		T36	51
wkup[61]	244	1		T30	21		T37	21		T49	21
wkup[62]	198	1		T12	21		T40	21		T125	21
wkup[63]	364	1		T11	56		T31	21		T36	21
wkup_0	3712	1		T1	5		T2	5		T3	5