| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 90.38 | 99.33 | 93.67 | 100.00 | 98.40 | 99.51 | 51.36 |
| T32 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4175793936 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 4209314168 ps | ||
| T282 | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.178718990 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 329156823 ps | ||
| T33 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2877502789 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 388274795 ps | ||
| T283 | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.631324313 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 388322730 ps | ||
| T34 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1665265666 | Aug 03 04:26:03 PM PDT 24 | Aug 03 04:26:10 PM PDT 24 | 8348128874 ps | ||
| T284 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2495826458 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 418241565 ps | ||
| T70 | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.22888437 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 2339054574 ps | ||
| T285 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3372054937 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 530279176 ps | ||
| T209 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3841828747 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 304140984 ps | ||
| T286 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2250251352 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 844143667 ps | ||
| T287 | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2419439112 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 334302837 ps | ||
| T288 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.489842744 | Aug 03 04:25:47 PM PDT 24 | Aug 03 04:25:47 PM PDT 24 | 370186441 ps | ||
| T289 | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3726316348 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 284213617 ps | ||
| T290 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3341041299 | Aug 03 04:26:55 PM PDT 24 | Aug 03 04:26:57 PM PDT 24 | 358400746 ps | ||
| T210 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.804527958 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 953836634 ps | ||
| T291 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4108848893 | Aug 03 04:25:54 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 479869501 ps | ||
| T35 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1219635061 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:25:53 PM PDT 24 | 4398102904 ps | ||
| T292 | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1676088334 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 595469750 ps | ||
| T293 | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.769001773 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 490731474 ps | ||
| T294 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4205276921 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 495338730 ps | ||
| T295 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3622357018 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 533081224 ps | ||
| T296 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1247448970 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 458435621 ps | ||
| T297 | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2709028774 | Aug 03 04:25:54 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 349711912 ps | ||
| T199 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.342725013 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:10 PM PDT 24 | 8253357536 ps | ||
| T57 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1697538806 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 469401169 ps | ||
| T298 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2781590533 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 284181571 ps | ||
| T299 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3622903341 | Aug 03 04:26:55 PM PDT 24 | Aug 03 04:27:02 PM PDT 24 | 4520258314 ps | ||
| T300 | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.182118444 | Aug 03 04:26:15 PM PDT 24 | Aug 03 04:26:16 PM PDT 24 | 346380221 ps | ||
| T71 | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1325587428 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 2659175203 ps | ||
| T72 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.351916311 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 504650355 ps | ||
| T301 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3038952479 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:57 PM PDT 24 | 442066153 ps | ||
| T302 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1550617085 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 393046927 ps | ||
| T303 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.346031967 | Aug 03 04:26:09 PM PDT 24 | Aug 03 04:26:11 PM PDT 24 | 311823808 ps | ||
| T304 | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1591711217 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 405198208 ps | ||
| T305 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3254023260 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 536051288 ps | ||
| T306 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.561323713 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 351598511 ps | ||
| T307 | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.12016908 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 439052559 ps | ||
| T308 | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3735417376 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 328192721 ps | ||
| T309 | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1731198326 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 401489490 ps | ||
| T310 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3774830967 | Aug 03 04:25:52 PM PDT 24 | Aug 03 04:25:53 PM PDT 24 | 879582134 ps | ||
| T311 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.261343682 | Aug 03 04:26:09 PM PDT 24 | Aug 03 04:26:11 PM PDT 24 | 543688700 ps | ||
| T312 | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4126742304 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 498011509 ps | ||
| T313 | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2239313283 | Aug 03 04:26:07 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 318361528 ps | ||
| T73 | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1292358946 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:25:53 PM PDT 24 | 1276888635 ps | ||
| T314 | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2025166375 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 474555375 ps | ||
| T74 | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4022902455 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 1825735850 ps | ||
| T315 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2793787894 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 787743514 ps | ||
| T316 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2060938667 | Aug 03 04:25:45 PM PDT 24 | Aug 03 04:25:46 PM PDT 24 | 350392451 ps | ||
| T58 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3311532877 | Aug 03 04:25:42 PM PDT 24 | Aug 03 04:25:43 PM PDT 24 | 334975318 ps | ||
| T59 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1722508941 | Aug 03 04:25:54 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 349539478 ps | ||
| T75 | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.98082336 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 2272956747 ps | ||
| T317 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2179500193 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 403292486 ps | ||
| T318 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1339263024 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 479960655 ps | ||
| T76 | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1089847268 | Aug 03 04:26:54 PM PDT 24 | Aug 03 04:26:58 PM PDT 24 | 1683814203 ps | ||
| T319 | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4128389083 | Aug 03 04:26:13 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 337564074 ps | ||
| T320 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3177035960 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 4403462071 ps | ||
| T321 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2405180420 | Aug 03 04:25:37 PM PDT 24 | Aug 03 04:25:38 PM PDT 24 | 310799983 ps | ||
| T322 | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4248079055 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 460781491 ps | ||
| T77 | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3780001389 | Aug 03 04:25:37 PM PDT 24 | Aug 03 04:25:41 PM PDT 24 | 1391048922 ps | ||
| T323 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1061669002 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 443909762 ps | ||
| T324 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4062926176 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:25:51 PM PDT 24 | 461606699 ps | ||
| T325 | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1586263154 | Aug 03 04:26:12 PM PDT 24 | Aug 03 04:26:13 PM PDT 24 | 510062167 ps | ||
| T326 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.254655682 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 655399995 ps | ||
| T60 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4070182361 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 681390668 ps | ||
| T327 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3212063093 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 523490767 ps | ||
| T328 | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.195151445 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 401354732 ps | ||
| T329 | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3070570782 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 368877067 ps | ||
| T330 | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.289298345 | Aug 03 04:26:11 PM PDT 24 | Aug 03 04:26:12 PM PDT 24 | 385184076 ps | ||
| T331 | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.643244504 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 372214395 ps | ||
| T332 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3221291411 | Aug 03 04:25:39 PM PDT 24 | Aug 03 04:25:40 PM PDT 24 | 522293110 ps | ||
| T333 | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4108915985 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 512383540 ps | ||
| T334 | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3676081352 | Aug 03 04:26:19 PM PDT 24 | Aug 03 04:26:19 PM PDT 24 | 331939813 ps | ||
| T335 | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1731747143 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:25:49 PM PDT 24 | 1251951780 ps | ||
| T336 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3276401287 | Aug 03 04:25:49 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 6879221588 ps | ||
| T337 | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4075800220 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 508448691 ps | ||
| T61 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2063614286 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:25:49 PM PDT 24 | 527287724 ps | ||
| T338 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.64253833 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 4727040689 ps | ||
| T339 | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2413704599 | Aug 03 04:26:18 PM PDT 24 | Aug 03 04:26:19 PM PDT 24 | 328048063 ps | ||
| T340 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.273180987 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:53 PM PDT 24 | 508213241 ps | ||
| T341 | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1944183941 | Aug 03 04:26:10 PM PDT 24 | Aug 03 04:26:11 PM PDT 24 | 547577980 ps | ||
| T342 | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1565723452 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:13 PM PDT 24 | 2106302871 ps | ||
| T62 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1746051230 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 512368611 ps | ||
| T343 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2595264877 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:57 PM PDT 24 | 305713785 ps | ||
| T344 | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2122167725 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 349914684 ps | ||
| T63 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.461768908 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:57 PM PDT 24 | 297199828 ps | ||
| T67 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2995264399 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 6842989406 ps | ||
| T345 | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1876653483 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 2522475164 ps | ||
| T346 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.644999657 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 326037794 ps | ||
| T347 | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4197293544 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:25:54 PM PDT 24 | 1221859714 ps | ||
| T348 | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1764687537 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 1387076051 ps | ||
| T349 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1445393575 | Aug 03 04:25:54 PM PDT 24 | Aug 03 04:26:09 PM PDT 24 | 8618943366 ps | ||
| T350 | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1821458334 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 461762891 ps | ||
| T351 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1946009066 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 379944958 ps | ||
| T352 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3566491886 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 8766988043 ps | ||
| T353 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3297191423 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 8250184822 ps | ||
| T354 | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1941061254 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:57 PM PDT 24 | 1699939036 ps | ||
| T355 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1937873417 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 732324417 ps | ||
| T356 | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3532664634 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 315614047 ps | ||
| T357 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3256242997 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 534122146 ps | ||
| T358 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2197941270 | Aug 03 04:26:03 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 426633935 ps | ||
| T68 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2266460179 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:54 PM PDT 24 | 849336067 ps | ||
| T359 | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3904309010 | Aug 03 04:26:13 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 468175552 ps | ||
| T360 | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2388533620 | Aug 03 04:26:15 PM PDT 24 | Aug 03 04:26:16 PM PDT 24 | 463653642 ps | ||
| T361 | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2422046976 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 2827085302 ps | ||
| T362 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3591379821 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 670784207 ps | ||
| T363 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3418294624 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 484309771 ps | ||
| T364 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3931146995 | Aug 03 04:26:03 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 463076596 ps | ||
| T64 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2247024054 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 489589529 ps | ||
| T365 | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1012256063 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:54 PM PDT 24 | 371983171 ps | ||
| T366 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3566039562 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 864591298 ps | ||
| T367 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3478098939 | Aug 03 04:25:47 PM PDT 24 | Aug 03 04:25:48 PM PDT 24 | 1123333641 ps | ||
| T368 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1263101305 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:53 PM PDT 24 | 673357337 ps | ||
| T369 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3508707322 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 310024648 ps | ||
| T370 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2238266877 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 8334741317 ps | ||
| T371 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2569251630 | Aug 03 04:26:03 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 399485617 ps | ||
| T372 | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2905963536 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 1536623550 ps | ||
| T373 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3540679928 | Aug 03 04:25:46 PM PDT 24 | Aug 03 04:25:49 PM PDT 24 | 930520067 ps | ||
| T374 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1780390983 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 511534630 ps | ||
| T375 | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2262719565 | Aug 03 04:26:16 PM PDT 24 | Aug 03 04:26:16 PM PDT 24 | 371444257 ps | ||
| T376 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.371989324 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:54 PM PDT 24 | 358884231 ps | ||
| T377 | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3626681639 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 432963948 ps | ||
| T378 | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.269910876 | Aug 03 04:26:13 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 404721989 ps | ||
| T379 | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4082070755 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 466558854 ps | ||
| T380 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1323507055 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:25:49 PM PDT 24 | 371002059 ps | ||
| T381 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2651308520 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 754795988 ps | ||
| T382 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2131646438 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 372334467 ps | ||
| T383 | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1953768714 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 1236490072 ps | ||
| T384 | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3854598447 | Aug 03 04:26:12 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 301936041 ps | ||
| T385 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1061765800 | Aug 03 04:25:49 PM PDT 24 | Aug 03 04:25:52 PM PDT 24 | 1105842387 ps | ||
| T386 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2329741432 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:26:11 PM PDT 24 | 8250429665 ps | ||
| T387 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.404604056 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 325132831 ps | ||
| T388 | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4136630993 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 2448407599 ps | ||
| T389 | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4011284349 | Aug 03 04:26:13 PM PDT 24 | Aug 03 04:26:14 PM PDT 24 | 476425154 ps | ||
| T390 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1932670096 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 330381085 ps | ||
| T200 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2775775199 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 7654642260 ps | ||
| T391 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.508505891 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 363353800 ps | ||
| T392 | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1202693281 | Aug 03 04:25:53 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 2142828500 ps | ||
| T393 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2243160128 | Aug 03 04:26:55 PM PDT 24 | Aug 03 04:26:56 PM PDT 24 | 444727706 ps | ||
| T394 | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.200275713 | Aug 03 04:26:07 PM PDT 24 | Aug 03 04:26:07 PM PDT 24 | 383079017 ps | ||
| T69 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2928314273 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:26:25 PM PDT 24 | 12782772650 ps | ||
| T395 | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2366784989 | Aug 03 04:25:58 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 416085581 ps | ||
| T396 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1101639732 | Aug 03 04:25:54 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 353195986 ps | ||
| T201 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2522313143 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 7987073435 ps | ||
| T397 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3370342260 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 4216417848 ps | ||
| T398 | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2001903297 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 452673256 ps | ||
| T399 | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1610337572 | Aug 03 04:25:45 PM PDT 24 | Aug 03 04:25:48 PM PDT 24 | 2574683717 ps | ||
| T400 | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4200646895 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 312391740 ps | ||
| T401 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1235380573 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:55 PM PDT 24 | 512209206 ps | ||
| T402 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3868499538 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:25:58 PM PDT 24 | 499063961 ps | ||
| T403 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2565119144 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:01 PM PDT 24 | 710402022 ps | ||
| T404 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.198689391 | Aug 03 04:26:04 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 332287633 ps | ||
| T405 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3331104344 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:25:49 PM PDT 24 | 624775011 ps | ||
| T406 | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1453565327 | Aug 03 04:25:55 PM PDT 24 | Aug 03 04:25:56 PM PDT 24 | 487534398 ps | ||
| T407 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2614382339 | Aug 03 04:26:02 PM PDT 24 | Aug 03 04:26:04 PM PDT 24 | 424806049 ps | ||
| T408 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3626270439 | Aug 03 04:25:47 PM PDT 24 | Aug 03 04:25:51 PM PDT 24 | 8459814810 ps | ||
| T409 | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3881051442 | Aug 03 04:26:16 PM PDT 24 | Aug 03 04:26:17 PM PDT 24 | 456197531 ps | ||
| T410 | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1723138585 | Aug 03 04:26:03 PM PDT 24 | Aug 03 04:26:05 PM PDT 24 | 1487377464 ps | ||
| T202 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3790014686 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 4386493027 ps | ||
| T411 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1752409134 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 441368055 ps | ||
| T412 | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1717891680 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 382621684 ps | ||
| T65 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2392744489 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 4433747352 ps | ||
| T413 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3718927234 | Aug 03 04:25:51 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 7068453464 ps | ||
| T414 | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2171448562 | Aug 03 04:26:14 PM PDT 24 | Aug 03 04:26:15 PM PDT 24 | 316358909 ps | ||
| T415 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.185180426 | Aug 03 04:25:48 PM PDT 24 | Aug 03 04:25:50 PM PDT 24 | 307285961 ps | ||
| T416 | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.703266558 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 373386338 ps | ||
| T417 | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1355250940 | Aug 03 04:26:09 PM PDT 24 | Aug 03 04:26:11 PM PDT 24 | 499762868 ps | ||
| T418 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4069229773 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 531136031 ps | ||
| T419 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.785220641 | Aug 03 04:25:50 PM PDT 24 | Aug 03 04:26:03 PM PDT 24 | 7817283261 ps | ||
| T420 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.446822781 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 4427867635 ps | ||
| T66 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.23565453 | Aug 03 04:26:00 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 473621286 ps | ||
| T421 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1640803751 | Aug 03 04:26:06 PM PDT 24 | Aug 03 04:26:08 PM PDT 24 | 492887819 ps | ||
| T422 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1994024561 | Aug 03 04:25:56 PM PDT 24 | Aug 03 04:26:00 PM PDT 24 | 4438442411 ps | ||
| T423 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1335566514 | Aug 03 04:26:01 PM PDT 24 | Aug 03 04:26:02 PM PDT 24 | 487780019 ps | ||
| T424 | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3494681022 | Aug 03 04:26:05 PM PDT 24 | Aug 03 04:26:06 PM PDT 24 | 416092830 ps | ||
| T425 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1620775473 | Aug 03 04:25:57 PM PDT 24 | Aug 03 04:25:59 PM PDT 24 | 426168732 ps |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.234089477 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 42045298223 ps |
| CPU time | 258.05 seconds |
| Started | Aug 03 04:28:05 PM PDT 24 |
| Finished | Aug 03 04:32:23 PM PDT 24 |
| Peak memory | 206580 kb |
| Host | smart-35600761-86fc-4253-85f4-7f3f30e1a360 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234089477 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.234089477 |
| Directory | /workspace/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.473208814 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 68595508212 ps |
| CPU time | 448.97 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:35:35 PM PDT 24 |
| Peak memory | 209272 kb |
| Host | smart-f8d75df2-2d26-47e8-99b2-f32525cded80 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473208814 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.473208814 |
| Directory | /workspace/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all.762268863 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 129851665664 ps |
| CPU time | 202.33 seconds |
| Started | Aug 03 04:27:43 PM PDT 24 |
| Finished | Aug 03 04:31:06 PM PDT 24 |
| Peak memory | 192656 kb |
| Host | smart-c443d534-adf3-4bc0-b441-19020fb8d95f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762268863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a ll.762268863 |
| Directory | /workspace/24.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1665265666 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8348128874 ps |
| CPU time | 6.61 seconds |
| Started | Aug 03 04:26:03 PM PDT 24 |
| Finished | Aug 03 04:26:10 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-499e1f6d-2629-4a97-a736-2199dd087e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665265666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t l_intg_err.1665265666 |
| Directory | /workspace/16.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1764844324 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 259099235690 ps |
| CPU time | 985.59 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:44:04 PM PDT 24 |
| Peak memory | 209064 kb |
| Host | smart-4f59a706-feaf-4140-a7de-19ed0249d312 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764844324 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1764844324 |
| Directory | /workspace/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2824775083 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 91457602622 ps |
| CPU time | 165.38 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:30:51 PM PDT 24 |
| Peak memory | 213756 kb |
| Host | smart-4a2c1fc3-8072-4942-822f-11acdadaa13c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824775083 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2824775083 |
| Directory | /workspace/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1612700072 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 80057965705 ps |
| CPU time | 425.29 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:34:49 PM PDT 24 |
| Peak memory | 199008 kb |
| Host | smart-da3399c5-2595-4d5f-bb04-aaf4e31072a8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612700072 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1612700072 |
| Directory | /workspace/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1462110110 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 133367911356 ps |
| CPU time | 429.39 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:34:55 PM PDT 24 |
| Peak memory | 211300 kb |
| Host | smart-d9861167-6d64-4b83-b3a4-a7b04521bb31 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462110110 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1462110110 |
| Directory | /workspace/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3220394835 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 379914869393 ps |
| CPU time | 735.49 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:40:22 PM PDT 24 |
| Peak memory | 214648 kb |
| Host | smart-60874b2d-8ae8-45ee-9529-6bebb87c29b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220394835 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3220394835 |
| Directory | /workspace/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3266368902 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 91097063645 ps |
| CPU time | 340.88 seconds |
| Started | Aug 03 04:27:42 PM PDT 24 |
| Finished | Aug 03 04:33:23 PM PDT 24 |
| Peak memory | 206616 kb |
| Host | smart-5671cdde-be88-4af5-a789-8529352c1f53 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266368902 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3266368902 |
| Directory | /workspace/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4278837204 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 201868606390 ps |
| CPU time | 822.39 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:41:12 PM PDT 24 |
| Peak memory | 214608 kb |
| Host | smart-b510a619-8c22-4578-bd20-1b89bb8a9a8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278837204 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4278837204 |
| Directory | /workspace/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all.374953951 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 121534645922 ps |
| CPU time | 44.97 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:28:14 PM PDT 24 |
| Peak memory | 197976 kb |
| Host | smart-361578aa-2331-46e3-a5b8-1f45e1288ccc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374953951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al l.374953951 |
| Directory | /workspace/3.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.554326350 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 218820443547 ps |
| CPU time | 388.73 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:34:25 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-b9f50531-c7ca-4eef-b2e6-98ea84137085 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554326350 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.554326350 |
| Directory | /workspace/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_sec_cm.1529386080 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4478194364 ps |
| CPU time | 2.31 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 215612 kb |
| Host | smart-d3c0d1c6-6563-44e9-9545-7a2bc046cc27 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529386080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1529386080 |
| Directory | /workspace/0.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1033066320 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 105019409487 ps |
| CPU time | 573.82 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:37:12 PM PDT 24 |
| Peak memory | 212852 kb |
| Host | smart-b3712b28-958f-498e-a9a6-ab789429828b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033066320 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1033066320 |
| Directory | /workspace/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all.1154033942 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 117596846147 ps |
| CPU time | 183.1 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:31:04 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-4117fa39-8621-46ff-95ad-2cf6edd9ba17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154033942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_ all.1154033942 |
| Directory | /workspace/47.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all.461023892 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 38632589841 ps |
| CPU time | 57.52 seconds |
| Started | Aug 03 04:28:08 PM PDT 24 |
| Finished | Aug 03 04:29:05 PM PDT 24 |
| Peak memory | 184288 kb |
| Host | smart-c1ec2956-ef63-41bc-b8d9-c8aa2687f99a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461023892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a ll.461023892 |
| Directory | /workspace/46.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all.3945981383 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 82283471317 ps |
| CPU time | 130.34 seconds |
| Started | Aug 03 04:27:34 PM PDT 24 |
| Finished | Aug 03 04:29:44 PM PDT 24 |
| Peak memory | 198052 kb |
| Host | smart-9c38734c-b222-4a20-a9e4-5e33fd7440b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945981383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_ all.3945981383 |
| Directory | /workspace/11.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.32333605 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 299914276422 ps |
| CPU time | 409.51 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:34:51 PM PDT 24 |
| Peak memory | 213992 kb |
| Host | smart-3e6a3407-382b-4c22-b64e-b3563734d632 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32333605 -assert nopo stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.32333605 |
| Directory | /workspace/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.815993560 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 218016496603 ps |
| CPU time | 482.93 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:35:55 PM PDT 24 |
| Peak memory | 203804 kb |
| Host | smart-f928a113-8dc9-4f27-aebd-9d7aa9610c35 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815993560 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.815993560 |
| Directory | /workspace/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.910079805 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 87445131194 ps |
| CPU time | 834.48 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:42:01 PM PDT 24 |
| Peak memory | 214640 kb |
| Host | smart-b0db44c1-2c55-476c-91ac-5b49eda2f356 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910079805 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.910079805 |
| Directory | /workspace/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all.1605564970 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 60909720306 ps |
| CPU time | 24.03 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:28:30 PM PDT 24 |
| Peak memory | 198184 kb |
| Host | smart-e5528ef3-b21c-4376-bb5e-ad03f62d3a51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605564970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_ all.1605564970 |
| Directory | /workspace/49.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all.715270604 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 153744737389 ps |
| CPU time | 232.42 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:31:53 PM PDT 24 |
| Peak memory | 198016 kb |
| Host | smart-cd46395d-53db-482f-8578-2cf7ee9ba122 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715270604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a ll.715270604 |
| Directory | /workspace/37.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all.934527528 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 109798347627 ps |
| CPU time | 68.54 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:29:05 PM PDT 24 |
| Peak memory | 192808 kb |
| Host | smart-0c9bfa0e-ea32-4558-bc8d-b726b8a770e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934527528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a ll.934527528 |
| Directory | /workspace/38.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all.2820899525 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 116980394604 ps |
| CPU time | 10.64 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:27:50 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-29464d9c-dab4-4e5a-8781-e98baf10e5ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820899525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_ all.2820899525 |
| Directory | /workspace/18.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all.1061734416 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 97639207841 ps |
| CPU time | 33.62 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:35 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-aaf89fff-2f25-4888-a786-3c9bab42ac46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061734416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_ all.1061734416 |
| Directory | /workspace/45.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3297317954 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 63906506744 ps |
| CPU time | 220.88 seconds |
| Started | Aug 03 04:27:53 PM PDT 24 |
| Finished | Aug 03 04:31:33 PM PDT 24 |
| Peak memory | 206416 kb |
| Host | smart-25996749-956e-4190-b462-2d1772540b24 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297317954 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3297317954 |
| Directory | /workspace/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3511581000 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 121084247595 ps |
| CPU time | 321.02 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:33:15 PM PDT 24 |
| Peak memory | 206488 kb |
| Host | smart-f6e25254-8b3f-47aa-ac7f-28c077e684f9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511581000 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3511581000 |
| Directory | /workspace/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all.3341380120 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 153230902543 ps |
| CPU time | 113.76 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:29:29 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-430616c5-b2e5-4682-b4da-a23d3ade0f71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341380120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_ all.3341380120 |
| Directory | /workspace/14.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all.3244077958 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 120863859275 ps |
| CPU time | 38.7 seconds |
| Started | Aug 03 04:27:25 PM PDT 24 |
| Finished | Aug 03 04:28:04 PM PDT 24 |
| Peak memory | 192776 kb |
| Host | smart-8f15decc-91d6-4e4e-8655-6633ca780658 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244077958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a ll.3244077958 |
| Directory | /workspace/2.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all.2996046371 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 24433180022 ps |
| CPU time | 8.99 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:28:07 PM PDT 24 |
| Peak memory | 191664 kb |
| Host | smart-0a628493-2fb9-4cf8-9d35-982976fb4749 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996046371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_ all.2996046371 |
| Directory | /workspace/35.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1722508941 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 349539478 ps |
| CPU time | 1.1 seconds |
| Started | Aug 03 04:25:54 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 193108 kb |
| Host | smart-e9bec7f8-f24f-4007-afa6-9e81df440098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722508941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1722508941 |
| Directory | /workspace/4.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all.507113691 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 510613721370 ps |
| CPU time | 102.47 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:29:28 PM PDT 24 |
| Peak memory | 197964 kb |
| Host | smart-d2e9ef9c-fca7-437a-84bb-c6f9ce8a5e15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507113691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a ll.507113691 |
| Directory | /workspace/23.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1090465724 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 50968616167 ps |
| CPU time | 501.01 seconds |
| Started | Aug 03 04:27:59 PM PDT 24 |
| Finished | Aug 03 04:36:20 PM PDT 24 |
| Peak memory | 201768 kb |
| Host | smart-a91789a4-1da4-4fd2-89ae-0ceb111fe19c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090465724 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1090465724 |
| Directory | /workspace/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.274778515 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 99955750631 ps |
| CPU time | 1105.21 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:46:26 PM PDT 24 |
| Peak memory | 214728 kb |
| Host | smart-07846c73-1999-4d55-b247-e24c310c36f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274778515 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.274778515 |
| Directory | /workspace/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3729821205 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 186363771937 ps |
| CPU time | 427.24 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:34:34 PM PDT 24 |
| Peak memory | 202452 kb |
| Host | smart-825a00e8-3e18-4b9c-94e8-486e3cfcb485 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729821205 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3729821205 |
| Directory | /workspace/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all.1054208307 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 156218077053 ps |
| CPU time | 62.47 seconds |
| Started | Aug 03 04:27:59 PM PDT 24 |
| Finished | Aug 03 04:29:01 PM PDT 24 |
| Peak memory | 198036 kb |
| Host | smart-5d6a3212-7481-45cd-b76f-016490e290c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054208307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_ all.1054208307 |
| Directory | /workspace/43.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1301639796 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 201323569840 ps |
| CPU time | 370.53 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:33:40 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-cebb786a-8c23-40b0-8321-71c1e77d5383 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301639796 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1301639796 |
| Directory | /workspace/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all.2431046275 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 147001758164 ps |
| CPU time | 161.02 seconds |
| Started | Aug 03 04:27:49 PM PDT 24 |
| Finished | Aug 03 04:30:30 PM PDT 24 |
| Peak memory | 192720 kb |
| Host | smart-2299089b-1830-4bb3-af3c-d85e7a3ff712 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431046275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_ all.2431046275 |
| Directory | /workspace/16.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all.67868185 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 30277496639 ps |
| CPU time | 10.14 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 191876 kb |
| Host | smart-ca9350d2-4197-466e-8e71-3e2e51eee366 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67868185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_al l.67868185 |
| Directory | /workspace/27.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1115064459 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 286994673158 ps |
| CPU time | 525.8 seconds |
| Started | Aug 03 04:27:32 PM PDT 24 |
| Finished | Aug 03 04:36:18 PM PDT 24 |
| Peak memory | 212228 kb |
| Host | smart-223c11bf-6c7d-44b4-9442-2daf9563a57e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115064459 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1115064459 |
| Directory | /workspace/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1511428259 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12338595208 ps |
| CPU time | 109.93 seconds |
| Started | Aug 03 04:27:36 PM PDT 24 |
| Finished | Aug 03 04:29:26 PM PDT 24 |
| Peak memory | 198384 kb |
| Host | smart-821ec3b9-177f-41b9-968f-e5923d3f6e0a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511428259 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1511428259 |
| Directory | /workspace/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all.638097933 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 127133444134 ps |
| CPU time | 89.37 seconds |
| Started | Aug 03 04:27:56 PM PDT 24 |
| Finished | Aug 03 04:29:26 PM PDT 24 |
| Peak memory | 192736 kb |
| Host | smart-21a6e27f-1c1c-4834-abb8-cdcd9adb17ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638097933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a ll.638097933 |
| Directory | /workspace/28.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all.3153315306 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 162842129226 ps |
| CPU time | 63.97 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:29:06 PM PDT 24 |
| Peak memory | 198016 kb |
| Host | smart-e31ccbbe-6967-43d7-b725-eae689b5e583 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153315306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_ all.3153315306 |
| Directory | /workspace/33.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.441798145 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 123922526814 ps |
| CPU time | 474.72 seconds |
| Started | Aug 03 04:27:59 PM PDT 24 |
| Finished | Aug 03 04:35:54 PM PDT 24 |
| Peak memory | 211300 kb |
| Host | smart-03e35f9c-efa3-4ea0-8723-e19b73786505 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441798145 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.441798145 |
| Directory | /workspace/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all.2154639862 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 427852558542 ps |
| CPU time | 683.21 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:39:02 PM PDT 24 |
| Peak memory | 192728 kb |
| Host | smart-f39b14ba-d433-471f-9597-74ee24b60ba6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154639862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_ all.2154639862 |
| Directory | /workspace/19.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3926981683 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 83587231742 ps |
| CPU time | 578.92 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:37:36 PM PDT 24 |
| Peak memory | 214072 kb |
| Host | smart-51567fce-ee31-475c-a40e-c60defb8b8cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926981683 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3926981683 |
| Directory | /workspace/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all.1170144461 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 109364893184 ps |
| CPU time | 37.35 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:28:35 PM PDT 24 |
| Peak memory | 198008 kb |
| Host | smart-4bf14c06-da24-4ff3-b921-9b9d54b98aa8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170144461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_ all.1170144461 |
| Directory | /workspace/36.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1946541847 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 46298503900 ps |
| CPU time | 264.57 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:32:25 PM PDT 24 |
| Peak memory | 206460 kb |
| Host | smart-6424e447-3142-4e0d-882d-1fb9ff9cadd7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946541847 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1946541847 |
| Directory | /workspace/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all.854823955 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5871919214 ps |
| CPU time | 5.3 seconds |
| Started | Aug 03 04:28:07 PM PDT 24 |
| Finished | Aug 03 04:28:12 PM PDT 24 |
| Peak memory | 191664 kb |
| Host | smart-a049c85a-f191-4d1d-9297-6df230725749 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854823955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a ll.854823955 |
| Directory | /workspace/44.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3002934923 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 195382524494 ps |
| CPU time | 295.32 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:32:39 PM PDT 24 |
| Peak memory | 206544 kb |
| Host | smart-a488469a-9395-4e07-a625-cc8e28030bde |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002934923 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3002934923 |
| Directory | /workspace/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.479423072 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 32764667144 ps |
| CPU time | 264.32 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:32:25 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-32ad5496-5bb8-418d-aef6-656aa4e8672e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479423072 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.479423072 |
| Directory | /workspace/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all.560979371 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 219512991416 ps |
| CPU time | 341.66 seconds |
| Started | Aug 03 04:27:32 PM PDT 24 |
| Finished | Aug 03 04:33:14 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-253e5873-6488-4f3a-a5a8-00dfa55065fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560979371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a ll.560979371 |
| Directory | /workspace/12.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all.4250561500 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 85333884012 ps |
| CPU time | 28.15 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-96b89393-c742-4aa9-a0ff-daed09a77bcf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250561500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_ all.4250561500 |
| Directory | /workspace/13.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all.3337611415 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 91730744079 ps |
| CPU time | 127.14 seconds |
| Started | Aug 03 04:27:48 PM PDT 24 |
| Finished | Aug 03 04:29:56 PM PDT 24 |
| Peak memory | 191692 kb |
| Host | smart-3392273a-6205-48b8-bd2e-b653dbdd31ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337611415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_ all.3337611415 |
| Directory | /workspace/31.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2947259883 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 47964375795 ps |
| CPU time | 277.96 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:32:32 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-eab8ef14-a237-4b7e-b23b-280e29a1ed68 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947259883 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2947259883 |
| Directory | /workspace/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all.2291018198 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 116855888323 ps |
| CPU time | 158.45 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:30:07 PM PDT 24 |
| Peak memory | 192804 kb |
| Host | smart-7004a9b1-cf83-4178-82b4-4b4fc8a6ea2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291018198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a ll.2291018198 |
| Directory | /workspace/6.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all.3130377983 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 68654497730 ps |
| CPU time | 47.7 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:28:15 PM PDT 24 |
| Peak memory | 197976 kb |
| Host | smart-bc6e1766-b4ea-4c4a-ab11-0931e6146559 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130377983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a ll.3130377983 |
| Directory | /workspace/0.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all.315808481 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 68510896225 ps |
| CPU time | 92.58 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:29:13 PM PDT 24 |
| Peak memory | 198096 kb |
| Host | smart-585a999b-ef76-4285-8fdf-0f3a3afb8e1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315808481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a ll.315808481 |
| Directory | /workspace/21.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2759366085 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 69885713303 ps |
| CPU time | 275.17 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:32:22 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-8d73f712-9f56-4905-b3c8-844e81f02328 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759366085 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2759366085 |
| Directory | /workspace/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all.1716178990 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 217704853686 ps |
| CPU time | 229.23 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:31:16 PM PDT 24 |
| Peak memory | 198380 kb |
| Host | smart-e354e316-4d51-4f68-93ad-0918b2ce2375 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716178990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a ll.1716178990 |
| Directory | /workspace/8.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4210898911 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 49376721127 ps |
| CPU time | 346.32 seconds |
| Started | Aug 03 04:27:30 PM PDT 24 |
| Finished | Aug 03 04:33:17 PM PDT 24 |
| Peak memory | 207456 kb |
| Host | smart-9d9987a1-cbfa-4843-a7d8-c39732fad1e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210898911 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4210898911 |
| Directory | /workspace/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all.1999714223 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 51252369307 ps |
| CPU time | 65 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:29:09 PM PDT 24 |
| Peak memory | 198120 kb |
| Host | smart-03d2df50-d37d-44ed-b485-15e126cfe65d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999714223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_ all.1999714223 |
| Directory | /workspace/32.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3191471715 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 45009114517 ps |
| CPU time | 88.8 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:29:23 PM PDT 24 |
| Peak memory | 214508 kb |
| Host | smart-716fc7ae-c137-4a24-802d-d7ef8c47b541 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191471715 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3191471715 |
| Directory | /workspace/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1541406559 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 56991168796 ps |
| CPU time | 592.73 seconds |
| Started | Aug 03 04:28:18 PM PDT 24 |
| Finished | Aug 03 04:38:10 PM PDT 24 |
| Peak memory | 211476 kb |
| Host | smart-58adbe38-b8c6-449b-bd3e-ca7f0b833c07 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541406559 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1541406559 |
| Directory | /workspace/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all.3054002199 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 176971596442 ps |
| CPU time | 38.06 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:28:23 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-73423cc5-5872-4e7c-9e6d-b32700216826 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054002199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a ll.3054002199 |
| Directory | /workspace/1.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all.4280029458 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 82829461509 ps |
| CPU time | 121.26 seconds |
| Started | Aug 03 04:27:47 PM PDT 24 |
| Finished | Aug 03 04:29:48 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-fff46c3f-63e8-4c37-bd84-f72542dd99a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280029458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_ all.4280029458 |
| Directory | /workspace/29.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2556453698 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 48084039450 ps |
| CPU time | 500.67 seconds |
| Started | Aug 03 04:27:53 PM PDT 24 |
| Finished | Aug 03 04:36:14 PM PDT 24 |
| Peak memory | 200844 kb |
| Host | smart-f087deae-d7ed-47ae-b6a9-d082bab03640 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556453698 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2556453698 |
| Directory | /workspace/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all.1311022593 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 107461338465 ps |
| CPU time | 150.03 seconds |
| Started | Aug 03 04:27:53 PM PDT 24 |
| Finished | Aug 03 04:30:23 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-df8d6f1d-1454-4938-b135-5be028d259a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311022593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_ all.1311022593 |
| Directory | /workspace/34.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all.2488200971 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 230177432663 ps |
| CPU time | 82.78 seconds |
| Started | Aug 03 04:27:59 PM PDT 24 |
| Finished | Aug 03 04:29:21 PM PDT 24 |
| Peak memory | 191592 kb |
| Host | smart-e5a35b21-ab4d-486a-b521-16b26df84175 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488200971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_ all.2488200971 |
| Directory | /workspace/48.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all.1166645546 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 694834173440 ps |
| CPU time | 224.11 seconds |
| Started | Aug 03 04:27:36 PM PDT 24 |
| Finished | Aug 03 04:31:21 PM PDT 24 |
| Peak memory | 192720 kb |
| Host | smart-782347a0-235d-4bee-a1f7-9c8bd2c8a059 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166645546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a ll.1166645546 |
| Directory | /workspace/5.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3755323097 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 128897326160 ps |
| CPU time | 266.43 seconds |
| Started | Aug 03 04:27:47 PM PDT 24 |
| Finished | Aug 03 04:32:13 PM PDT 24 |
| Peak memory | 206452 kb |
| Host | smart-4825a4f4-9d94-474b-a62a-2dd3920e4639 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755323097 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3755323097 |
| Directory | /workspace/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1124605385 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 57932723801 ps |
| CPU time | 426.72 seconds |
| Started | Aug 03 04:27:50 PM PDT 24 |
| Finished | Aug 03 04:34:57 PM PDT 24 |
| Peak memory | 213708 kb |
| Host | smart-aa5dc0dc-2fd5-4faa-bf92-522f966d3190 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124605385 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1124605385 |
| Directory | /workspace/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.aon_timer_jump.1701544253 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 415216498 ps |
| CPU time | 1.13 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 196596 kb |
| Host | smart-da56ce57-1aea-4292-82ae-3553614913e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701544253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1701544253 |
| Directory | /workspace/3.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2946051231 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 23262423764 ps |
| CPU time | 181.36 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:30:53 PM PDT 24 |
| Peak memory | 206492 kb |
| Host | smart-72a17d9e-84e0-4eb7-b0ec-70ed30f12054 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946051231 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2946051231 |
| Directory | /workspace/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all.1641848925 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 285457455935 ps |
| CPU time | 383.9 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:33:53 PM PDT 24 |
| Peak memory | 192808 kb |
| Host | smart-7487d66e-4011-45e7-bc06-d0c3952a41a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641848925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a ll.1641848925 |
| Directory | /workspace/9.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.aon_timer_jump.1208749365 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 427786122 ps |
| CPU time | 0.96 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-737db913-834a-4048-a369-d75a95ba9161 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208749365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1208749365 |
| Directory | /workspace/1.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3507785712 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 59467948523 ps |
| CPU time | 254.96 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:31:43 PM PDT 24 |
| Peak memory | 198888 kb |
| Host | smart-b6c2ab2f-8589-46c2-8fc2-9bec54988c55 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507785712 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3507785712 |
| Directory | /workspace/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2728714288 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 24396954607 ps |
| CPU time | 175.62 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:30:31 PM PDT 24 |
| Peak memory | 206424 kb |
| Host | smart-8067ec1f-aac3-4bed-9c51-1dc4167959d1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728714288 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2728714288 |
| Directory | /workspace/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4035218013 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 29219053483 ps |
| CPU time | 201.58 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:31:15 PM PDT 24 |
| Peak memory | 206588 kb |
| Host | smart-e0bc295a-d980-4304-b72b-0ff63443907d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035218013 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4035218013 |
| Directory | /workspace/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_jump.2737962574 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 514669235 ps |
| CPU time | 0.68 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-18a83593-7ab1-4662-8dca-80cfaf633928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737962574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2737962574 |
| Directory | /workspace/39.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_jump.2573265037 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 463482779 ps |
| CPU time | 1.21 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:27:37 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-a71962bc-3a20-4029-a005-e755df1af647 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573265037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2573265037 |
| Directory | /workspace/13.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all.4236773449 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 107606882384 ps |
| CPU time | 99.62 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:29:19 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-9416d0b5-36e1-4554-aec7-e0de5a10ba6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236773449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_ all.4236773449 |
| Directory | /workspace/15.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all.2969681445 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 201590436750 ps |
| CPU time | 293.2 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:32:26 PM PDT 24 |
| Peak memory | 191688 kb |
| Host | smart-59144bae-2776-46f0-9c87-bd513df29d6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969681445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_ all.2969681445 |
| Directory | /workspace/17.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.aon_timer_jump.4042955683 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 490741526 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:27:40 PM PDT 24 |
| Finished | Aug 03 04:27:41 PM PDT 24 |
| Peak memory | 196560 kb |
| Host | smart-46cd32af-3022-429a-b69e-c9762cabbf10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042955683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.4042955683 |
| Directory | /workspace/23.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/28.aon_timer_jump.866621418 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 475105604 ps |
| CPU time | 1.26 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:27:53 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-fd706771-e1c1-466b-ada6-c36084223c0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866621418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.866621418 |
| Directory | /workspace/28.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/49.aon_timer_jump.1268169307 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 596664163 ps |
| CPU time | 1.37 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 196516 kb |
| Host | smart-096c6e2c-d541-47d4-893f-5eb9768ef2a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268169307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1268169307 |
| Directory | /workspace/49.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/8.aon_timer_jump.2803727535 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 442159557 ps |
| CPU time | 0.76 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:27:39 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-9b1afa04-a3f9-4325-ae37-d303833ee533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803727535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2803727535 |
| Directory | /workspace/8.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.387728683 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 58420143607 ps |
| CPU time | 368.87 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:33:38 PM PDT 24 |
| Peak memory | 213808 kb |
| Host | smart-89339b9a-140f-4910-8336-e0d708de6437 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387728683 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.387728683 |
| Directory | /workspace/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_jump.179317717 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 586762431 ps |
| CPU time | 0.83 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:27:34 PM PDT 24 |
| Peak memory | 196468 kb |
| Host | smart-129fbecc-ff89-4d80-9ef0-db7dfb584cd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179317717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.179317717 |
| Directory | /workspace/12.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/18.aon_timer_jump.643717575 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 447027429 ps |
| CPU time | 0.75 seconds |
| Started | Aug 03 04:27:50 PM PDT 24 |
| Finished | Aug 03 04:27:51 PM PDT 24 |
| Peak memory | 196468 kb |
| Host | smart-0992de21-66e6-42c9-917b-5ee828a7aaa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643717575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.643717575 |
| Directory | /workspace/18.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/2.aon_timer_jump.3244136657 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 477494419 ps |
| CPU time | 0.9 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 196576 kb |
| Host | smart-7232bfa3-079f-4314-9a53-bc2cded25b01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244136657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3244136657 |
| Directory | /workspace/2.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all.3964415579 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 297835986369 ps |
| CPU time | 225.47 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:31:26 PM PDT 24 |
| Peak memory | 191668 kb |
| Host | smart-8d470ec5-9e2a-4616-83ec-afbec9c1cc6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964415579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_ all.3964415579 |
| Directory | /workspace/20.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3096882586 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 27116966377 ps |
| CPU time | 194.49 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:31:13 PM PDT 24 |
| Peak memory | 206460 kb |
| Host | smart-73c5004c-b1e8-4b9d-bf48-bd4daa3fa5c0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096882586 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3096882586 |
| Directory | /workspace/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.aon_timer_jump.3723607119 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 476432162 ps |
| CPU time | 1.33 seconds |
| Started | Aug 03 04:28:08 PM PDT 24 |
| Finished | Aug 03 04:28:10 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-c2613a14-646a-4375-b311-1a8477ce1d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723607119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3723607119 |
| Directory | /workspace/43.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/45.aon_timer_jump.1663079534 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 418087646 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 196560 kb |
| Host | smart-61ec056b-5e3b-416b-92a3-94f61112a178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663079534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1663079534 |
| Directory | /workspace/45.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all.1155974338 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 497193673526 ps |
| CPU time | 355.54 seconds |
| Started | Aug 03 04:27:31 PM PDT 24 |
| Finished | Aug 03 04:33:27 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-fc61b64e-1f06-4333-9e51-da6d957778d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155974338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a ll.1155974338 |
| Directory | /workspace/7.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1317821695 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 28636126966 ps |
| CPU time | 233.55 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:31:27 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-90226f03-1054-4b2a-a717-343b3d673684 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317821695 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1317821695 |
| Directory | /workspace/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_jump.2416509260 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 414834463 ps |
| CPU time | 1.24 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:27:28 PM PDT 24 |
| Peak memory | 196592 kb |
| Host | smart-fd0357e1-4e78-4563-ad98-bfe0e7d77f1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416509260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2416509260 |
| Directory | /workspace/0.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/10.aon_timer_jump.2027419610 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 348994434 ps |
| CPU time | 1.07 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:27:36 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-64b2534a-1ae9-4bd7-96ed-2d20bc1f940b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027419610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2027419610 |
| Directory | /workspace/10.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_jump.607730034 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 461397114 ps |
| CPU time | 1.29 seconds |
| Started | Aug 03 04:27:40 PM PDT 24 |
| Finished | Aug 03 04:27:41 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-8c30f7e1-d026-49df-9e31-18185c2f7b73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607730034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.607730034 |
| Directory | /workspace/25.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/33.aon_timer_jump.2433704252 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 485204104 ps |
| CPU time | 1.32 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:27:53 PM PDT 24 |
| Peak memory | 196484 kb |
| Host | smart-b273516c-2a75-4c0e-ae8d-4aeeb01e2926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433704252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2433704252 |
| Directory | /workspace/33.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/34.aon_timer_jump.909991444 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 575054736 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-f0700fd9-7d10-4f73-b59c-d46a8f674256 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909991444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.909991444 |
| Directory | /workspace/34.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all.2368798764 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 214513577951 ps |
| CPU time | 280.79 seconds |
| Started | Aug 03 04:27:31 PM PDT 24 |
| Finished | Aug 03 04:32:12 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-f1efcb35-5955-449f-a7f2-2b868c8fac8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368798764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a ll.2368798764 |
| Directory | /workspace/4.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all.3955450225 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 193946391895 ps |
| CPU time | 244.02 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:32:08 PM PDT 24 |
| Peak memory | 197984 kb |
| Host | smart-ae02d8c4-8c4b-4370-9eba-4e3e360d1408 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955450225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_ all.3955450225 |
| Directory | /workspace/41.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_jump.1312761655 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 429967416 ps |
| CPU time | 0.73 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:02 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-d1516169-ac76-45ba-b6ea-2b9a5dcbaa2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312761655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1312761655 |
| Directory | /workspace/48.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1692344135 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 45017549159 ps |
| CPU time | 322.23 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:33:02 PM PDT 24 |
| Peak memory | 198544 kb |
| Host | smart-e4f7c388-1058-4ac9-8c3a-a8bbd7e951cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692344135 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1692344135 |
| Directory | /workspace/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.aon_timer_jump.457856722 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 482653709 ps |
| CPU time | 0.8 seconds |
| Started | Aug 03 04:27:40 PM PDT 24 |
| Finished | Aug 03 04:27:40 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-a7c9cfa9-3e8c-4d5c-bd1e-bcdba749e136 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457856722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.457856722 |
| Directory | /workspace/21.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all.2780203961 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 162431291783 ps |
| CPU time | 238.35 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:31:43 PM PDT 24 |
| Peak memory | 191708 kb |
| Host | smart-ef487e50-6356-410a-9697-a37cc0d3030a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780203961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_ all.2780203961 |
| Directory | /workspace/22.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.aon_timer_jump.2493548308 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 394882062 ps |
| CPU time | 0.82 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:45 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-40a442e0-9f3c-4fe1-8db0-243e924b606a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493548308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2493548308 |
| Directory | /workspace/24.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/38.aon_timer_jump.1231611043 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 503447408 ps |
| CPU time | 0.96 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:27:53 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-d5f1d79d-33ff-432e-a041-2683c5569f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231611043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1231611043 |
| Directory | /workspace/38.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/46.aon_timer_jump.783858524 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 392202167 ps |
| CPU time | 1.12 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-707abcb0-79ab-4b5b-8d3a-f64b71c29a85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783858524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.783858524 |
| Directory | /workspace/46.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/5.aon_timer_jump.2963452467 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 482657171 ps |
| CPU time | 0.92 seconds |
| Started | Aug 03 04:27:26 PM PDT 24 |
| Finished | Aug 03 04:27:27 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-c929abb5-5af2-4fd7-8dfa-604fb1c12346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963452467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2963452467 |
| Directory | /workspace/5.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all.322382360 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 417982390330 ps |
| CPU time | 151.71 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:30:12 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-e41ca6bd-86d6-4fce-9ae5-94106fa4aadd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322382360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a ll.322382360 |
| Directory | /workspace/10.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.aon_timer_jump.2313145519 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 435544106 ps |
| CPU time | 1.16 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:27:46 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-0a419fff-c5f7-4bea-b22d-f093b1ee1a31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313145519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2313145519 |
| Directory | /workspace/11.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/14.aon_timer_jump.284346148 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 571494708 ps |
| CPU time | 1.34 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:27:40 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-6e3c7808-33ad-41b7-9457-b760d396ca6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284346148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.284346148 |
| Directory | /workspace/14.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.772166417 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 53522869833 ps |
| CPU time | 450.21 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:35:23 PM PDT 24 |
| Peak memory | 208920 kb |
| Host | smart-8ce7074f-5f50-4582-9891-110977b0ea75 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772166417 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.772166417 |
| Directory | /workspace/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.aon_timer_jump.637636616 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 450628004 ps |
| CPU time | 1.16 seconds |
| Started | Aug 03 04:27:48 PM PDT 24 |
| Finished | Aug 03 04:27:49 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-aa2e8cc3-94f0-4dc0-a10d-416e6e2ed62b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637636616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.637636616 |
| Directory | /workspace/27.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all.1275897424 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 216566560023 ps |
| CPU time | 27.35 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:28:25 PM PDT 24 |
| Peak memory | 192764 kb |
| Host | smart-530189ef-ef49-48d2-87c7-2d6ba7da8566 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275897424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_ all.1275897424 |
| Directory | /workspace/30.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_jump.2284876482 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 400691524 ps |
| CPU time | 1.17 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:27:47 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-a6e99979-7b9a-44c6-b058-fccb3cca4dd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284876482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2284876482 |
| Directory | /workspace/31.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/32.aon_timer_jump.1889974076 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 357546899 ps |
| CPU time | 1.13 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 196520 kb |
| Host | smart-2fbf0511-a4ac-4e21-b24a-ac5ef97cb1e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889974076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1889974076 |
| Directory | /workspace/32.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/36.aon_timer_jump.4034126405 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 594576135 ps |
| CPU time | 0.7 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:27:54 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-89e0a209-7926-4477-8085-736d68885947 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034126405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4034126405 |
| Directory | /workspace/36.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_jump.3672386091 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 439237049 ps |
| CPU time | 0.95 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:02 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-bf448603-68d3-4833-8772-8cb7da676388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672386091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3672386091 |
| Directory | /workspace/40.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all.3222902399 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 55683129545 ps |
| CPU time | 84.45 seconds |
| Started | Aug 03 04:28:05 PM PDT 24 |
| Finished | Aug 03 04:29:29 PM PDT 24 |
| Peak memory | 191660 kb |
| Host | smart-0243d3bc-aebf-45c6-a43b-e0dd914cefbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222902399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_ all.3222902399 |
| Directory | /workspace/42.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.aon_timer_jump.1044999321 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 699451283 ps |
| CPU time | 0.66 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:27:28 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-ef9035af-8e40-4d6d-b295-21c0d760dba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044999321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1044999321 |
| Directory | /workspace/7.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2522313143 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 7987073435 ps |
| CPU time | 6.76 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-73778b8a-2249-4d99-b80f-83996d69422b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522313143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl _intg_err.2522313143 |
| Directory | /workspace/0.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4175793936 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4209314168 ps |
| CPU time | 6.79 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 197964 kb |
| Host | smart-b9c97d00-5b7b-4c67-bb0e-9b4ba3f6d25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175793936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t l_intg_err.4175793936 |
| Directory | /workspace/12.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/16.aon_timer_jump.9568698 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 499886692 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:27:34 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-4eb26521-bd8c-4364-b2f2-cde8f0b40188 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9568698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.9568698 |
| Directory | /workspace/16.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/17.aon_timer_jump.976134433 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 589447866 ps |
| CPU time | 1.08 seconds |
| Started | Aug 03 04:27:48 PM PDT 24 |
| Finished | Aug 03 04:27:49 PM PDT 24 |
| Peak memory | 196360 kb |
| Host | smart-f2b705ec-af9e-4569-a487-018b6295c382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976134433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.976134433 |
| Directory | /workspace/17.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_jump.3124484515 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 566158428 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:45 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-befb5a87-5b72-4e0f-82aa-892a306b16c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124484515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3124484515 |
| Directory | /workspace/22.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all.1183166968 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 135559420677 ps |
| CPU time | 47.65 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:28:34 PM PDT 24 |
| Peak memory | 198008 kb |
| Host | smart-25cb7e14-7e48-453a-aa48-98be66878ec0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183166968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_ all.1183166968 |
| Directory | /workspace/25.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.aon_timer_jump.1448012144 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 351800683 ps |
| CPU time | 1.13 seconds |
| Started | Aug 03 04:27:55 PM PDT 24 |
| Finished | Aug 03 04:27:57 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-7ed2b5c2-7806-459c-aee8-aaedf2c3c148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448012144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1448012144 |
| Directory | /workspace/26.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/29.aon_timer_jump.3565936450 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 454496494 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:28:07 PM PDT 24 |
| Finished | Aug 03 04:28:07 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-3e603d7f-c235-453c-b47a-9bdc2eefcc14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565936450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3565936450 |
| Directory | /workspace/29.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/35.aon_timer_jump.3556717183 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 541390329 ps |
| CPU time | 1.36 seconds |
| Started | Aug 03 04:27:50 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-735ddaaa-9864-488c-81a3-8c57d940ace5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556717183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3556717183 |
| Directory | /workspace/35.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/37.aon_timer_jump.58881358 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 564797378 ps |
| CPU time | 0.75 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:27:53 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-b1cdfd5e-e88c-4d13-8869-c3e5b178e43e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58881358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.58881358 |
| Directory | /workspace/37.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all.3462467495 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 16862869665 ps |
| CPU time | 23.1 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:26 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-64d48949-2926-4b00-9820-f39980cd34c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462467495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_ all.3462467495 |
| Directory | /workspace/39.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_jump.1300470636 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 441760547 ps |
| CPU time | 1.33 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-b8a24e17-581a-43f6-82e6-b029a75a2323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300470636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1300470636 |
| Directory | /workspace/4.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all.3619423235 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 115486704048 ps |
| CPU time | 19.3 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:23 PM PDT 24 |
| Peak memory | 197996 kb |
| Host | smart-92d7ee5e-25fc-43f1-86b0-4b88cc234725 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619423235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_ all.3619423235 |
| Directory | /workspace/40.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.aon_timer_jump.1441362899 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 349088714 ps |
| CPU time | 1.09 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-ae95440a-0f4a-4f05-83b9-66d3afdc8b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441362899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1441362899 |
| Directory | /workspace/41.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/47.aon_timer_jump.56623632 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 440873533 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-471b0638-7c23-4aac-aaea-d1f33adbc3c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56623632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.56623632 |
| Directory | /workspace/47.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/6.aon_timer_jump.3282326341 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 607504758 ps |
| CPU time | 0.8 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 196388 kb |
| Host | smart-d2cbe090-3db5-4673-8f6d-b577f89f3f6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282326341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3282326341 |
| Directory | /workspace/6.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3221291411 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 522293110 ps |
| CPU time | 1.39 seconds |
| Started | Aug 03 04:25:39 PM PDT 24 |
| Finished | Aug 03 04:25:40 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-ad076bc6-3c26-45dd-9aeb-90e0ef5141d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221291411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a liasing.3221291411 |
| Directory | /workspace/0.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2928314273 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 12782772650 ps |
| CPU time | 36.49 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:26:25 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-e993cdd6-885e-4880-b9ae-b6358654138d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928314273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b it_bash.2928314273 |
| Directory | /workspace/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3774830967 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 879582134 ps |
| CPU time | 0.88 seconds |
| Started | Aug 03 04:25:52 PM PDT 24 |
| Finished | Aug 03 04:25:53 PM PDT 24 |
| Peak memory | 191988 kb |
| Host | smart-ca27a3f2-b330-467f-9aa7-e09ad00bd9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774830967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h w_reset.3774830967 |
| Directory | /workspace/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.185180426 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 307285961 ps |
| CPU time | 0.83 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:25:50 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-823265b5-8417-455f-a20f-17bd756f0f0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185180426 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.185180426 |
| Directory | /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1550617085 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 393046927 ps |
| CPU time | 1.06 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 192932 kb |
| Host | smart-0ad49894-d30a-49b6-b385-426dc692ca8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550617085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1550617085 |
| Directory | /workspace/0.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3070570782 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 368877067 ps |
| CPU time | 0.82 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 183676 kb |
| Host | smart-b8419595-0548-4447-907e-b4f4c2217655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070570782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3070570782 |
| Directory | /workspace/0.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4062926176 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 461606699 ps |
| CPU time | 1.06 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:25:51 PM PDT 24 |
| Peak memory | 183452 kb |
| Host | smart-8a339f22-bf76-423b-93d2-cb60e61ed77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062926176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t imer_mem_partial_access.4062926176 |
| Directory | /workspace/0.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2595264877 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 305713785 ps |
| CPU time | 0.71 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:57 PM PDT 24 |
| Peak memory | 183420 kb |
| Host | smart-bc3f88a9-6af2-4a26-8f83-4fdfcb1fd536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595264877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w alk.2595264877 |
| Directory | /workspace/0.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3780001389 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1391048922 ps |
| CPU time | 3.84 seconds |
| Started | Aug 03 04:25:37 PM PDT 24 |
| Finished | Aug 03 04:25:41 PM PDT 24 |
| Peak memory | 192760 kb |
| Host | smart-3a24dd11-ccea-4d25-a7e5-339ceecd9a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780001389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon _timer_same_csr_outstanding.3780001389 |
| Directory | /workspace/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3540679928 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 930520067 ps |
| CPU time | 2.29 seconds |
| Started | Aug 03 04:25:46 PM PDT 24 |
| Finished | Aug 03 04:25:49 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-4d01e461-cf31-4be8-94ee-4e7f7943c0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540679928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3540679928 |
| Directory | /workspace/0.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4070182361 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 681390668 ps |
| CPU time | 0.97 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 194672 kb |
| Host | smart-6b700911-23b0-49b2-900a-271106db66f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070182361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a liasing.4070182361 |
| Directory | /workspace/1.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3276401287 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6879221588 ps |
| CPU time | 10.01 seconds |
| Started | Aug 03 04:25:49 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 192120 kb |
| Host | smart-2754dde3-0bfa-4f58-89ec-828aff8bb258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276401287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b it_bash.3276401287 |
| Directory | /workspace/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1061765800 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1105842387 ps |
| CPU time | 2.03 seconds |
| Started | Aug 03 04:25:49 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 193140 kb |
| Host | smart-1e45b8d1-f927-46d4-8f6c-96268e9a71aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061765800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h w_reset.1061765800 |
| Directory | /workspace/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.804527958 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 953836634 ps |
| CPU time | 0.88 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 197984 kb |
| Host | smart-0556d511-6d44-41d9-af64-ecdf9aea8c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804527958 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.804527958 |
| Directory | /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2781590533 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 284181571 ps |
| CPU time | 0.94 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-e6dfc895-0324-4695-a1c2-58907207460e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781590533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2781590533 |
| Directory | /workspace/1.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1453565327 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 487534398 ps |
| CPU time | 0.72 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-8b9e6884-b4f1-4e8a-ae4e-9d4efca5bae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453565327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1453565327 |
| Directory | /workspace/1.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4108848893 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 479869501 ps |
| CPU time | 0.68 seconds |
| Started | Aug 03 04:25:54 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 183592 kb |
| Host | smart-29f87607-882a-49c6-8041-3fee414e8e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108848893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t imer_mem_partial_access.4108848893 |
| Directory | /workspace/1.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2405180420 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 310799983 ps |
| CPU time | 0.66 seconds |
| Started | Aug 03 04:25:37 PM PDT 24 |
| Finished | Aug 03 04:25:38 PM PDT 24 |
| Peak memory | 183544 kb |
| Host | smart-3b353fbf-8c94-4985-9c8c-2d04d0ab343a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405180420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w alk.2405180420 |
| Directory | /workspace/1.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1953768714 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1236490072 ps |
| CPU time | 0.85 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 192836 kb |
| Host | smart-a7569e47-7c7f-4c55-9207-42aa8a774587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953768714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon _timer_same_csr_outstanding.1953768714 |
| Directory | /workspace/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.644999657 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 326037794 ps |
| CPU time | 2.26 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-2bc21258-3744-428b-8028-f3bb393d796b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644999657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.644999657 |
| Directory | /workspace/1.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3626270439 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 8459814810 ps |
| CPU time | 4.07 seconds |
| Started | Aug 03 04:25:47 PM PDT 24 |
| Finished | Aug 03 04:25:51 PM PDT 24 |
| Peak memory | 198052 kb |
| Host | smart-010510b8-c917-467a-9a4d-a05573e52b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626270439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl _intg_err.3626270439 |
| Directory | /workspace/1.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2651308520 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 754795988 ps |
| CPU time | 0.91 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 198048 kb |
| Host | smart-f079330a-613f-453b-a631-4ea178debd5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651308520 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2651308520 |
| Directory | /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2243160128 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 444727706 ps |
| CPU time | 0.83 seconds |
| Started | Aug 03 04:26:55 PM PDT 24 |
| Finished | Aug 03 04:26:56 PM PDT 24 |
| Peak memory | 192528 kb |
| Host | smart-9c6cf18d-301c-4ee5-9f88-3cc02be6cb8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243160128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2243160128 |
| Directory | /workspace/10.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2366784989 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 416085581 ps |
| CPU time | 0.61 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 183552 kb |
| Host | smart-de96b266-52ae-4152-a005-967e85246e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366784989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2366784989 |
| Directory | /workspace/10.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1202693281 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2142828500 ps |
| CPU time | 3.34 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 193684 kb |
| Host | smart-40a14412-fa10-4104-abad-aa4e107fd7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202693281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao n_timer_same_csr_outstanding.1202693281 |
| Directory | /workspace/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.273180987 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 508213241 ps |
| CPU time | 1.71 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:53 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-b1e53e8e-03e0-44f6-a26d-2c5a24f92890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273180987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.273180987 |
| Directory | /workspace/10.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.785220641 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 7817283261 ps |
| CPU time | 12.19 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-0a585a42-86f0-48e7-b780-88b6a14cb61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785220641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl _intg_err.785220641 |
| Directory | /workspace/10.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3868499538 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 499063961 ps |
| CPU time | 1.3 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-be6e8ddb-3fec-4c37-a877-beec9556dbb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868499538 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3868499538 |
| Directory | /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2197941270 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 426633935 ps |
| CPU time | 1.3 seconds |
| Started | Aug 03 04:26:03 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 193268 kb |
| Host | smart-cd13e0aa-e130-4d81-a8c6-90f72646acca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197941270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2197941270 |
| Directory | /workspace/11.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1591711217 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 405198208 ps |
| CPU time | 0.66 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 183448 kb |
| Host | smart-d7b772b2-3ee1-4cb0-81a4-c06478930b21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591711217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1591711217 |
| Directory | /workspace/11.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1089847268 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1683814203 ps |
| CPU time | 3.54 seconds |
| Started | Aug 03 04:26:54 PM PDT 24 |
| Finished | Aug 03 04:26:58 PM PDT 24 |
| Peak memory | 193488 kb |
| Host | smart-4e7d705c-f6fc-4577-8586-8457c831b838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089847268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao n_timer_same_csr_outstanding.1089847268 |
| Directory | /workspace/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3341041299 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 358400746 ps |
| CPU time | 1.14 seconds |
| Started | Aug 03 04:26:55 PM PDT 24 |
| Finished | Aug 03 04:26:57 PM PDT 24 |
| Peak memory | 198012 kb |
| Host | smart-c0e43a7b-b577-485e-b904-9d280a3f5bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341041299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3341041299 |
| Directory | /workspace/11.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1445393575 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 8618943366 ps |
| CPU time | 14.7 seconds |
| Started | Aug 03 04:25:54 PM PDT 24 |
| Finished | Aug 03 04:26:09 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-ed7b1a90-0d53-43d7-87b2-ff8becf78c3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445393575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t l_intg_err.1445393575 |
| Directory | /workspace/11.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3254023260 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 536051288 ps |
| CPU time | 0.83 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 195920 kb |
| Host | smart-ddae640b-7036-496f-8b29-a08ed64406ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254023260 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3254023260 |
| Directory | /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2877502789 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 388274795 ps |
| CPU time | 1.17 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 193156 kb |
| Host | smart-f28593f8-572b-4d71-a438-c257c5c3adec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877502789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2877502789 |
| Directory | /workspace/12.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2419439112 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 334302837 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-5f1d11dd-ec82-4a9c-861a-ebd5f04535e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419439112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2419439112 |
| Directory | /workspace/12.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1731747143 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1251951780 ps |
| CPU time | 1.33 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:25:49 PM PDT 24 |
| Peak memory | 193912 kb |
| Host | smart-a1737c99-e9ce-45e5-b461-d3e7fe316d0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731747143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao n_timer_same_csr_outstanding.1731747143 |
| Directory | /workspace/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2565119144 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 710402022 ps |
| CPU time | 1.85 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-a2314cde-b4dc-444d-9eb3-4201e1652c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565119144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2565119144 |
| Directory | /workspace/12.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1061669002 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 443909762 ps |
| CPU time | 1.25 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 195384 kb |
| Host | smart-89d45809-b2b7-42db-9df6-56c140143174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061669002 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1061669002 |
| Directory | /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3256242997 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 534122146 ps |
| CPU time | 1.27 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-2237a1ee-8c56-4557-ada9-9944979fb64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256242997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3256242997 |
| Directory | /workspace/13.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4108915985 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 512383540 ps |
| CPU time | 0.6 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 183592 kb |
| Host | smart-c0f331ed-e29f-4025-b577-8c2312f50bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108915985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4108915985 |
| Directory | /workspace/13.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1941061254 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1699939036 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:57 PM PDT 24 |
| Peak memory | 192864 kb |
| Host | smart-e18327bf-e7b1-4ea5-8742-70b1c181762b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941061254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao n_timer_same_csr_outstanding.1941061254 |
| Directory | /workspace/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2793787894 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 787743514 ps |
| CPU time | 2.32 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 198480 kb |
| Host | smart-0d1e465a-3d70-4b19-8e3b-3ed74cc065ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793787894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2793787894 |
| Directory | /workspace/13.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3177035960 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4403462071 ps |
| CPU time | 3.01 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 197688 kb |
| Host | smart-064c6147-fc27-4e94-ae14-7dca227c420d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177035960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t l_intg_err.3177035960 |
| Directory | /workspace/13.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1780390983 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 511534630 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-f91ca16c-7926-49db-b53c-6a3aa18a158b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780390983 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1780390983 |
| Directory | /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4069229773 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 531136031 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 193044 kb |
| Host | smart-03c4cd30-409b-4083-9603-c8449e41a82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069229773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4069229773 |
| Directory | /workspace/14.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.12016908 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 439052559 ps |
| CPU time | 0.67 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 183676 kb |
| Host | smart-c8fc52cb-9e7a-4eb7-8354-b69f23b888c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.12016908 |
| Directory | /workspace/14.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2905963536 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1536623550 ps |
| CPU time | 1.26 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 193312 kb |
| Host | smart-fd4e73af-c7fa-40d2-8307-90d7f8b752dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905963536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao n_timer_same_csr_outstanding.2905963536 |
| Directory | /workspace/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.561323713 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 351598511 ps |
| CPU time | 1.91 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 198500 kb |
| Host | smart-1d6a06cf-9888-4898-bb37-bafb20340f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561323713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.561323713 |
| Directory | /workspace/14.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2775775199 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7654642260 ps |
| CPU time | 6.04 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-6cae089c-fa23-426e-bf5d-45534fa99ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775775199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t l_intg_err.2775775199 |
| Directory | /workspace/14.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1620775473 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 426168732 ps |
| CPU time | 1.22 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 196224 kb |
| Host | smart-06232d50-0736-4ea8-97cb-0cf9f2756525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620775473 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1620775473 |
| Directory | /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.198689391 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 332287633 ps |
| CPU time | 1.04 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 192868 kb |
| Host | smart-31ee13b0-f79c-486c-b2ca-59caeb913dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198689391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.198689391 |
| Directory | /workspace/15.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2001903297 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 452673256 ps |
| CPU time | 0.67 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-65db2262-a54c-49f9-86bb-3189103d122d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001903297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2001903297 |
| Directory | /workspace/15.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.98082336 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2272956747 ps |
| CPU time | 1.55 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 194344 kb |
| Host | smart-6f98c7dd-e6be-42f6-9db3-2a7107486b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98082336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ timer_same_csr_outstanding.98082336 |
| Directory | /workspace/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3372054937 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 530279176 ps |
| CPU time | 3.32 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-23905f03-8879-44e5-85af-cef627e3adc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372054937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3372054937 |
| Directory | /workspace/15.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.64253833 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4727040689 ps |
| CPU time | 7.23 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-163d8c60-7c64-4a51-b8dc-31ce22c29a3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64253833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_ intg_err.64253833 |
| Directory | /workspace/15.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1640803751 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 492887819 ps |
| CPU time | 1.3 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-a3d715e9-7a99-4da4-92df-a8893a7d10b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640803751 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1640803751 |
| Directory | /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3622357018 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 533081224 ps |
| CPU time | 0.71 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 192896 kb |
| Host | smart-6953fbe8-b56f-45f6-9165-68b53cc4580b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622357018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3622357018 |
| Directory | /workspace/16.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4248079055 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 460781491 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-a19336bb-cbb3-444d-a476-1bc16ec74553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248079055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4248079055 |
| Directory | /workspace/16.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1325587428 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2659175203 ps |
| CPU time | 1.61 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 191804 kb |
| Host | smart-a04b6cd0-60cb-4cba-8fbb-3585c87dee87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325587428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao n_timer_same_csr_outstanding.1325587428 |
| Directory | /workspace/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1937873417 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 732324417 ps |
| CPU time | 2.45 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 198484 kb |
| Host | smart-521985f8-9e60-4bff-8d83-6b418b58eb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937873417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1937873417 |
| Directory | /workspace/16.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.346031967 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 311823808 ps |
| CPU time | 0.9 seconds |
| Started | Aug 03 04:26:09 PM PDT 24 |
| Finished | Aug 03 04:26:11 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-eedfa1db-6edc-4f1c-bb68-706de0bcc4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346031967 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.346031967 |
| Directory | /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1335566514 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 487780019 ps |
| CPU time | 1.24 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 193004 kb |
| Host | smart-3e7c6366-9eaa-4f2b-b36c-1217f25b1001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335566514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1335566514 |
| Directory | /workspace/17.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.703266558 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 373386338 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 183584 kb |
| Host | smart-9228a7ec-b24a-41f6-a90b-8ac5398021aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703266558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.703266558 |
| Directory | /workspace/17.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2422046976 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2827085302 ps |
| CPU time | 1.63 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 191652 kb |
| Host | smart-38404af2-0e22-4180-b94a-0f70fd7de67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422046976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao n_timer_same_csr_outstanding.2422046976 |
| Directory | /workspace/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1932670096 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 330381085 ps |
| CPU time | 1.83 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 198472 kb |
| Host | smart-03ebd665-5a35-48e1-a773-39c227c5c1c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932670096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1932670096 |
| Directory | /workspace/17.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3297191423 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 8250184822 ps |
| CPU time | 12.57 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 198016 kb |
| Host | smart-acf294b2-1875-4f88-8631-a564a004dd14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297191423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t l_intg_err.3297191423 |
| Directory | /workspace/17.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.261343682 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 543688700 ps |
| CPU time | 1.15 seconds |
| Started | Aug 03 04:26:09 PM PDT 24 |
| Finished | Aug 03 04:26:11 PM PDT 24 |
| Peak memory | 198144 kb |
| Host | smart-4815af66-74c2-43bb-8534-163c72826036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261343682 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.261343682 |
| Directory | /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.23565453 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 473621286 ps |
| CPU time | 0.78 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 192808 kb |
| Host | smart-b801f84a-8947-4983-b5b6-dc703bbd18be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23565453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.23565453 |
| Directory | /workspace/18.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.289298345 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 385184076 ps |
| CPU time | 0.54 seconds |
| Started | Aug 03 04:26:11 PM PDT 24 |
| Finished | Aug 03 04:26:12 PM PDT 24 |
| Peak memory | 183732 kb |
| Host | smart-e26fe5c6-6598-4278-a84c-75933e026cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289298345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.289298345 |
| Directory | /workspace/18.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1565723452 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2106302871 ps |
| CPU time | 7.02 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:13 PM PDT 24 |
| Peak memory | 195100 kb |
| Host | smart-24900163-bbec-48f9-9052-2ec320438a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565723452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao n_timer_same_csr_outstanding.1565723452 |
| Directory | /workspace/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3591379821 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 670784207 ps |
| CPU time | 2.7 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-3fd70193-3758-4c30-917a-319f86daaff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591379821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3591379821 |
| Directory | /workspace/18.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3790014686 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4386493027 ps |
| CPU time | 2.34 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 197724 kb |
| Host | smart-82034f4d-72ba-48c4-a509-c901b8754c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790014686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t l_intg_err.3790014686 |
| Directory | /workspace/18.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4205276921 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 495338730 ps |
| CPU time | 0.95 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-478eec89-38ae-404a-8751-186d4301a2cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205276921 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4205276921 |
| Directory | /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2569251630 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 399485617 ps |
| CPU time | 0.95 seconds |
| Started | Aug 03 04:26:03 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 193868 kb |
| Host | smart-65caca34-6b65-44ed-ac57-6f6f72a633a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569251630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2569251630 |
| Directory | /workspace/19.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3494681022 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 416092830 ps |
| CPU time | 0.68 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-f7e3ac9b-0b73-4831-9177-a474211f5624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494681022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3494681022 |
| Directory | /workspace/19.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1876653483 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2522475164 ps |
| CPU time | 1.37 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-6933d131-c3b7-4805-8c59-27167467874d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876653483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao n_timer_same_csr_outstanding.1876653483 |
| Directory | /workspace/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3566039562 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 864591298 ps |
| CPU time | 1.56 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-7e609ea5-2dbd-4fa7-8d54-dfdb3735a1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566039562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3566039562 |
| Directory | /workspace/19.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3370342260 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4216417848 ps |
| CPU time | 7.19 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 197832 kb |
| Host | smart-32c1c923-3046-429f-a672-504f5875b10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370342260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t l_intg_err.3370342260 |
| Directory | /workspace/19.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2063614286 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 527287724 ps |
| CPU time | 1.15 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:25:49 PM PDT 24 |
| Peak memory | 194180 kb |
| Host | smart-12c2adb2-2425-4f37-9db7-377d7744a72b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063614286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a liasing.2063614286 |
| Directory | /workspace/2.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2392744489 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4433747352 ps |
| CPU time | 2.68 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 192132 kb |
| Host | smart-f375e5e4-f61b-4324-a182-21a9e8822e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392744489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b it_bash.2392744489 |
| Directory | /workspace/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3331104344 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 624775011 ps |
| CPU time | 1.24 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:25:49 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-cb129342-0b3d-4c33-a890-c524129f04a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331104344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h w_reset.3331104344 |
| Directory | /workspace/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3841828747 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 304140984 ps |
| CPU time | 0.92 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 194916 kb |
| Host | smart-3bd90e5d-4186-463f-881c-bbd4a7e63e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841828747 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3841828747 |
| Directory | /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2179500193 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 403292486 ps |
| CPU time | 0.61 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 193012 kb |
| Host | smart-02390416-f521-44f2-9e11-647bc712f221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179500193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2179500193 |
| Directory | /workspace/2.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4075800220 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 508448691 ps |
| CPU time | 0.71 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 192820 kb |
| Host | smart-268ee9fa-10a9-45d6-ac2e-d838f3bd9a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075800220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4075800220 |
| Directory | /workspace/2.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3038952479 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 442066153 ps |
| CPU time | 1.07 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:57 PM PDT 24 |
| Peak memory | 183536 kb |
| Host | smart-4c33586a-b7fd-44ee-9f1a-839137c14569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038952479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t imer_mem_partial_access.3038952479 |
| Directory | /workspace/2.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.371989324 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 358884231 ps |
| CPU time | 0.81 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:54 PM PDT 24 |
| Peak memory | 183468 kb |
| Host | smart-dc99e90c-a140-4a7c-8cf3-7bc661509fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371989324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa lk.371989324 |
| Directory | /workspace/2.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4197293544 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1221859714 ps |
| CPU time | 3.08 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:25:54 PM PDT 24 |
| Peak memory | 193524 kb |
| Host | smart-ccc755a8-8723-43ea-9e2d-996fa6c71851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197293544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon _timer_same_csr_outstanding.4197293544 |
| Directory | /workspace/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1263101305 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 673357337 ps |
| CPU time | 2.16 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:53 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-08b0733e-6dce-443e-818d-b2db8cdad7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263101305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1263101305 |
| Directory | /workspace/2.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2329741432 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 8250429665 ps |
| CPU time | 12.6 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:26:11 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-8758dd94-ec1d-49ae-aa52-a7aefd3e9a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329741432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl _intg_err.2329741432 |
| Directory | /workspace/2.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2025166375 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 474555375 ps |
| CPU time | 0.61 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 183508 kb |
| Host | smart-7d8c65ab-c254-428c-b079-1248d735fa1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025166375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2025166375 |
| Directory | /workspace/20.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.631324313 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 388322730 ps |
| CPU time | 0.6 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:06 PM PDT 24 |
| Peak memory | 192868 kb |
| Host | smart-6a6f63ca-6f49-471d-9744-43deac7651b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631324313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.631324313 |
| Directory | /workspace/21.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1731198326 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 401489490 ps |
| CPU time | 0.59 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-199d66a9-23d8-4388-ac01-b4750f5a7dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731198326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1731198326 |
| Directory | /workspace/22.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.769001773 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 490731474 ps |
| CPU time | 0.66 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-a1d9e06b-5c7f-4d44-833b-a5a17ccab528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769001773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.769001773 |
| Directory | /workspace/23.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.643244504 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 372214395 ps |
| CPU time | 0.73 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 192780 kb |
| Host | smart-f2875677-f966-4dc2-bcae-59e503c47d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643244504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.643244504 |
| Directory | /workspace/24.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2262719565 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 371444257 ps |
| CPU time | 0.64 seconds |
| Started | Aug 03 04:26:16 PM PDT 24 |
| Finished | Aug 03 04:26:16 PM PDT 24 |
| Peak memory | 192864 kb |
| Host | smart-ff65c9e5-0175-4032-85e5-7a29b57f13d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262719565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2262719565 |
| Directory | /workspace/25.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4011284349 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 476425154 ps |
| CPU time | 0.86 seconds |
| Started | Aug 03 04:26:13 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-df6fcf1e-920c-407e-b284-b7e6379bf574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011284349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4011284349 |
| Directory | /workspace/26.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2122167725 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 349914684 ps |
| CPU time | 0.97 seconds |
| Started | Aug 03 04:26:04 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 183572 kb |
| Host | smart-e53dc668-0dcf-40df-ab69-911b740209ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122167725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2122167725 |
| Directory | /workspace/27.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1355250940 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 499762868 ps |
| CPU time | 1.3 seconds |
| Started | Aug 03 04:26:09 PM PDT 24 |
| Finished | Aug 03 04:26:11 PM PDT 24 |
| Peak memory | 192832 kb |
| Host | smart-5191e8cc-7f91-4077-8a54-cf6e83b1aa8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355250940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1355250940 |
| Directory | /workspace/28.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3532664634 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 315614047 ps |
| CPU time | 0.68 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-98b233c7-4120-4846-8693-349b086287dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532664634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3532664634 |
| Directory | /workspace/29.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1746051230 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 512368611 ps |
| CPU time | 1.36 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 183928 kb |
| Host | smart-ca615a58-7072-428d-9a70-06c33c8d00b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746051230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a liasing.1746051230 |
| Directory | /workspace/3.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3718927234 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 7068453464 ps |
| CPU time | 9.52 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 192180 kb |
| Host | smart-fcaef187-2eee-4f87-a85e-9db51e971477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718927234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b it_bash.3718927234 |
| Directory | /workspace/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2266460179 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 849336067 ps |
| CPU time | 0.84 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:54 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-6140e72e-3f2a-48ce-86e0-2e8679284d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266460179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h w_reset.2266460179 |
| Directory | /workspace/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1323507055 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 371002059 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:25:48 PM PDT 24 |
| Finished | Aug 03 04:25:49 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-87bd4627-1489-49fc-9937-0a97491a2d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323507055 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1323507055 |
| Directory | /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3311532877 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 334975318 ps |
| CPU time | 0.7 seconds |
| Started | Aug 03 04:25:42 PM PDT 24 |
| Finished | Aug 03 04:25:43 PM PDT 24 |
| Peak memory | 193236 kb |
| Host | smart-8b5efe78-8d16-4830-8857-30180d5ea52f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311532877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3311532877 |
| Directory | /workspace/3.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.178718990 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 329156823 ps |
| CPU time | 1.05 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 192848 kb |
| Host | smart-560b09b0-5988-4ad9-8a62-94bf68d49e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178718990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.178718990 |
| Directory | /workspace/3.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.489842744 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 370186441 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:25:47 PM PDT 24 |
| Finished | Aug 03 04:25:47 PM PDT 24 |
| Peak memory | 183560 kb |
| Host | smart-90585821-9293-4d79-9f50-082aa16bd216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489842744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti mer_mem_partial_access.489842744 |
| Directory | /workspace/3.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2131646438 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 372334467 ps |
| CPU time | 0.64 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-5d7dee88-478c-4f22-a114-545a5219f78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131646438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w alk.2131646438 |
| Directory | /workspace/3.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4136630993 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2448407599 ps |
| CPU time | 1.49 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-3f6deed8-dce1-4ec3-ad39-afa7ba34ff1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136630993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon _timer_same_csr_outstanding.4136630993 |
| Directory | /workspace/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1752409134 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 441368055 ps |
| CPU time | 2.6 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-2d814bb7-22f2-494f-a091-5ebb564f6063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752409134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1752409134 |
| Directory | /workspace/3.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.342725013 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 8253357536 ps |
| CPU time | 3.76 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:10 PM PDT 24 |
| Peak memory | 197920 kb |
| Host | smart-98355892-5447-4f0f-8015-80506e8017a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342725013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_ intg_err.342725013 |
| Directory | /workspace/3.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3735417376 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 328192721 ps |
| CPU time | 0.63 seconds |
| Started | Aug 03 04:26:06 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 183616 kb |
| Host | smart-f537d997-dfcf-4004-bea7-7c69d21ea279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735417376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3735417376 |
| Directory | /workspace/30.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1586263154 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 510062167 ps |
| CPU time | 0.58 seconds |
| Started | Aug 03 04:26:12 PM PDT 24 |
| Finished | Aug 03 04:26:13 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-731adb64-ab16-4355-bcf1-283242517f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586263154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1586263154 |
| Directory | /workspace/31.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2239313283 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 318361528 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:26:07 PM PDT 24 |
| Finished | Aug 03 04:26:08 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-d0825f9c-9075-4159-a5f1-9cd3b8d69071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239313283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2239313283 |
| Directory | /workspace/32.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.200275713 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 383079017 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:26:07 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 183732 kb |
| Host | smart-c093158a-0dfa-43e8-9245-e9279c468c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200275713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.200275713 |
| Directory | /workspace/33.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3904309010 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 468175552 ps |
| CPU time | 0.84 seconds |
| Started | Aug 03 04:26:13 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-21d3a93a-ef11-4f55-abde-10ab2611efdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904309010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3904309010 |
| Directory | /workspace/34.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1944183941 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 547577980 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:26:10 PM PDT 24 |
| Finished | Aug 03 04:26:11 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-44f4b475-c703-496b-b316-cb6ef531c75c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944183941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1944183941 |
| Directory | /workspace/35.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.195151445 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 401354732 ps |
| CPU time | 0.68 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 192840 kb |
| Host | smart-25cdada6-7620-484e-a384-ca2bb851dd91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195151445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.195151445 |
| Directory | /workspace/36.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1717891680 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 382621684 ps |
| CPU time | 1.08 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 183576 kb |
| Host | smart-d8f58da0-752a-4f73-a8cf-c45b3dffad96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717891680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1717891680 |
| Directory | /workspace/37.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2388533620 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 463653642 ps |
| CPU time | 0.88 seconds |
| Started | Aug 03 04:26:15 PM PDT 24 |
| Finished | Aug 03 04:26:16 PM PDT 24 |
| Peak memory | 192872 kb |
| Host | smart-07343378-dda3-42f6-abfd-37bf1aeda366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388533620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2388533620 |
| Directory | /workspace/38.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3854598447 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 301936041 ps |
| CPU time | 0.94 seconds |
| Started | Aug 03 04:26:12 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 192820 kb |
| Host | smart-08bd7c70-90d8-4a08-9180-e52edf7c0c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854598447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3854598447 |
| Directory | /workspace/39.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2247024054 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 489589529 ps |
| CPU time | 0.95 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 194560 kb |
| Host | smart-43946496-fbfe-4a2c-96dc-944c037eac6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247024054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a liasing.2247024054 |
| Directory | /workspace/4.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2995264399 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6842989406 ps |
| CPU time | 4.13 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 192048 kb |
| Host | smart-f77be1d3-66e1-4b6e-a6e0-22e91b4c5730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995264399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b it_bash.2995264399 |
| Directory | /workspace/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3478098939 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1123333641 ps |
| CPU time | 1.34 seconds |
| Started | Aug 03 04:25:47 PM PDT 24 |
| Finished | Aug 03 04:25:48 PM PDT 24 |
| Peak memory | 193160 kb |
| Host | smart-c647c55a-c387-4220-9f7b-ce8d2f1e0b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478098939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h w_reset.3478098939 |
| Directory | /workspace/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.254655682 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 655399995 ps |
| CPU time | 0.84 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-f40957c1-581c-4578-87d4-44cb783fa444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254655682 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.254655682 |
| Directory | /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1012256063 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 371983171 ps |
| CPU time | 1.04 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:54 PM PDT 24 |
| Peak memory | 183592 kb |
| Host | smart-68b05aee-4385-4803-b57f-a40932be9d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012256063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1012256063 |
| Directory | /workspace/4.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2060938667 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 350392451 ps |
| CPU time | 1.02 seconds |
| Started | Aug 03 04:25:45 PM PDT 24 |
| Finished | Aug 03 04:25:46 PM PDT 24 |
| Peak memory | 183560 kb |
| Host | smart-0311bf78-ce20-4e32-9c59-c98709f2e4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060938667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t imer_mem_partial_access.2060938667 |
| Directory | /workspace/4.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1339263024 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 479960655 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:25:51 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 183540 kb |
| Host | smart-4ab5f464-73e5-49a6-8b74-de67e264cd76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339263024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w alk.1339263024 |
| Directory | /workspace/4.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.22888437 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2339054574 ps |
| CPU time | 2.68 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 193856 kb |
| Host | smart-36a4147b-f887-4ffd-9937-71a8335ee041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t imer_same_csr_outstanding.22888437 |
| Directory | /workspace/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2495826458 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 418241565 ps |
| CPU time | 2.04 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-86c557b9-8d4a-436f-a034-5660f92fb300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495826458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2495826458 |
| Directory | /workspace/4.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2238266877 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 8334741317 ps |
| CPU time | 14.03 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 198136 kb |
| Host | smart-9dab2a73-898a-440e-8ccc-463bd2dac8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238266877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl _intg_err.2238266877 |
| Directory | /workspace/4.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.269910876 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 404721989 ps |
| CPU time | 0.83 seconds |
| Started | Aug 03 04:26:13 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 192884 kb |
| Host | smart-7f64df71-c163-4e58-b413-5381bbb3f8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269910876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.269910876 |
| Directory | /workspace/40.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.182118444 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 346380221 ps |
| CPU time | 0.65 seconds |
| Started | Aug 03 04:26:15 PM PDT 24 |
| Finished | Aug 03 04:26:16 PM PDT 24 |
| Peak memory | 183752 kb |
| Host | smart-9dae20b6-dffb-4b9a-957d-a00397fdf944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182118444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.182118444 |
| Directory | /workspace/41.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3881051442 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 456197531 ps |
| CPU time | 0.71 seconds |
| Started | Aug 03 04:26:16 PM PDT 24 |
| Finished | Aug 03 04:26:17 PM PDT 24 |
| Peak memory | 183648 kb |
| Host | smart-6d1ca262-e2b4-4726-8f32-73887be4e364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881051442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3881051442 |
| Directory | /workspace/42.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4128389083 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 337564074 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:26:13 PM PDT 24 |
| Finished | Aug 03 04:26:14 PM PDT 24 |
| Peak memory | 192844 kb |
| Host | smart-4e293001-18a3-4ce7-ab81-dfb5c1dda286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128389083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4128389083 |
| Directory | /workspace/43.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2413704599 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 328048063 ps |
| CPU time | 0.7 seconds |
| Started | Aug 03 04:26:18 PM PDT 24 |
| Finished | Aug 03 04:26:19 PM PDT 24 |
| Peak memory | 183648 kb |
| Host | smart-1835330b-3b7d-4829-acae-9fec55630254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413704599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2413704599 |
| Directory | /workspace/44.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3626681639 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 432963948 ps |
| CPU time | 1.09 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 192968 kb |
| Host | smart-fb872832-4761-42bc-9190-d42f1f6debda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626681639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3626681639 |
| Directory | /workspace/45.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1676088334 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 595469750 ps |
| CPU time | 0.6 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-93c8962a-4c28-411a-b774-4f2c0629e154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676088334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1676088334 |
| Directory | /workspace/46.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1821458334 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 461762891 ps |
| CPU time | 1.17 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-3c17f2ed-ef1d-43ca-8c06-ce8129f6b4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821458334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1821458334 |
| Directory | /workspace/47.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2171448562 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 316358909 ps |
| CPU time | 0.66 seconds |
| Started | Aug 03 04:26:14 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 183648 kb |
| Host | smart-579c2569-3f69-4925-b76d-e3394d1c1787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171448562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2171448562 |
| Directory | /workspace/48.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3676081352 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 331939813 ps |
| CPU time | 0.63 seconds |
| Started | Aug 03 04:26:19 PM PDT 24 |
| Finished | Aug 03 04:26:19 PM PDT 24 |
| Peak memory | 183584 kb |
| Host | smart-6891a535-feb9-4d15-9cd4-145926be307b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676081352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3676081352 |
| Directory | /workspace/49.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1946009066 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 379944958 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 195852 kb |
| Host | smart-9b33150d-747a-4922-93bd-18fa2fd95aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946009066 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1946009066 |
| Directory | /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1697538806 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 469401169 ps |
| CPU time | 0.64 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 192884 kb |
| Host | smart-0985125d-57ca-4047-99d8-3f2c9dde98f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697538806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1697538806 |
| Directory | /workspace/5.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2709028774 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 349711912 ps |
| CPU time | 0.65 seconds |
| Started | Aug 03 04:25:54 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-b250ec80-4172-4426-bc0b-e946adff5225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709028774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2709028774 |
| Directory | /workspace/5.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4022902455 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1825735850 ps |
| CPU time | 1.76 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 192900 kb |
| Host | smart-df324016-6109-4349-9cf9-f49c7eff9559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022902455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon _timer_same_csr_outstanding.4022902455 |
| Directory | /workspace/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3418294624 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 484309771 ps |
| CPU time | 1.91 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-beca871c-c0c5-4818-b52e-61c1f0d0f895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418294624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3418294624 |
| Directory | /workspace/5.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1219635061 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4398102904 ps |
| CPU time | 2.44 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:25:53 PM PDT 24 |
| Peak memory | 197624 kb |
| Host | smart-2fe4502a-38c7-4f80-b4bf-48e6adfbbf64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219635061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl _intg_err.1219635061 |
| Directory | /workspace/5.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1247448970 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 458435621 ps |
| CPU time | 1.42 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-a4109750-1f65-49df-86dc-eb5986dec243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247448970 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1247448970 |
| Directory | /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.508505891 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 363353800 ps |
| CPU time | 0.99 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-3027a74c-ca4c-49d9-98cc-6ad65b67fb5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508505891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.508505891 |
| Directory | /workspace/6.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4082070755 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 466558854 ps |
| CPU time | 1.08 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 192896 kb |
| Host | smart-dff4f62d-aa87-441b-a955-733ea2cecbd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082070755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4082070755 |
| Directory | /workspace/6.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1292358946 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1276888635 ps |
| CPU time | 2.29 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:25:53 PM PDT 24 |
| Peak memory | 193220 kb |
| Host | smart-e30442f9-ed13-492d-a96f-be5c85bf7877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292358946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon _timer_same_csr_outstanding.1292358946 |
| Directory | /workspace/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2250251352 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 844143667 ps |
| CPU time | 2.08 seconds |
| Started | Aug 03 04:25:53 PM PDT 24 |
| Finished | Aug 03 04:25:56 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-202d5c80-d229-4ca6-87f5-6169f783f3a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250251352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2250251352 |
| Directory | /workspace/6.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1994024561 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4438442411 ps |
| CPU time | 3.81 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-536b7d0a-731d-4a4b-abbb-d44c5dbddbba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994024561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl _intg_err.1994024561 |
| Directory | /workspace/6.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3931146995 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 463076596 ps |
| CPU time | 1.45 seconds |
| Started | Aug 03 04:26:03 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 196040 kb |
| Host | smart-13f966b5-ea2d-4afc-a85b-d4dc9b472b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931146995 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3931146995 |
| Directory | /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.461768908 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 297199828 ps |
| CPU time | 0.97 seconds |
| Started | Aug 03 04:25:56 PM PDT 24 |
| Finished | Aug 03 04:25:57 PM PDT 24 |
| Peak memory | 192848 kb |
| Host | smart-973a07c7-49fc-4e85-8d8f-dfb31a903189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461768908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.461768908 |
| Directory | /workspace/7.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4126742304 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 498011509 ps |
| CPU time | 0.67 seconds |
| Started | Aug 03 04:26:01 PM PDT 24 |
| Finished | Aug 03 04:26:02 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-e11c5df9-f8f2-444e-87da-9ff0783758f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126742304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4126742304 |
| Directory | /workspace/7.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1764687537 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1387076051 ps |
| CPU time | 0.76 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 192844 kb |
| Host | smart-881a5990-918b-4cb8-8c15-de2fad9ad349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764687537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon _timer_same_csr_outstanding.1764687537 |
| Directory | /workspace/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.404604056 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 325132831 ps |
| CPU time | 1.91 seconds |
| Started | Aug 03 04:26:05 PM PDT 24 |
| Finished | Aug 03 04:26:07 PM PDT 24 |
| Peak memory | 198464 kb |
| Host | smart-318fd60c-b11f-44c9-95e3-c3e5de934de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404604056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.404604056 |
| Directory | /workspace/7.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3622903341 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4520258314 ps |
| CPU time | 7.35 seconds |
| Started | Aug 03 04:26:55 PM PDT 24 |
| Finished | Aug 03 04:27:02 PM PDT 24 |
| Peak memory | 197520 kb |
| Host | smart-afca28ee-e585-4058-93fa-8a6656e8c124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622903341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl _intg_err.3622903341 |
| Directory | /workspace/7.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3508707322 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 310024648 ps |
| CPU time | 0.99 seconds |
| Started | Aug 03 04:26:00 PM PDT 24 |
| Finished | Aug 03 04:26:01 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-0c381c0f-32d9-45b5-be56-fa705a1d80e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508707322 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3508707322 |
| Directory | /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.351916311 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 504650355 ps |
| CPU time | 1.03 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:03 PM PDT 24 |
| Peak memory | 192880 kb |
| Host | smart-0d3d10c0-0318-485e-a787-ea8b1087f084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351916311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.351916311 |
| Directory | /workspace/8.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4200646895 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 312391740 ps |
| CPU time | 0.79 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:25:58 PM PDT 24 |
| Peak memory | 192848 kb |
| Host | smart-8db7ccda-e356-4cd5-84c6-b580cd53508d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200646895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4200646895 |
| Directory | /workspace/8.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1723138585 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1487377464 ps |
| CPU time | 1.31 seconds |
| Started | Aug 03 04:26:03 PM PDT 24 |
| Finished | Aug 03 04:26:05 PM PDT 24 |
| Peak memory | 192916 kb |
| Host | smart-2f98d6ee-8f70-450d-a882-81b085ff7c75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723138585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon _timer_same_csr_outstanding.1723138585 |
| Directory | /workspace/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3212063093 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 523490767 ps |
| CPU time | 1.69 seconds |
| Started | Aug 03 04:25:50 PM PDT 24 |
| Finished | Aug 03 04:25:52 PM PDT 24 |
| Peak memory | 198380 kb |
| Host | smart-cc9804c0-9e12-4e7c-b8bb-09acf265889b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212063093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3212063093 |
| Directory | /workspace/8.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3566491886 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 8766988043 ps |
| CPU time | 12.46 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:15 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-c43f7b63-77b2-4384-8084-5bcfb7e87a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566491886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl _intg_err.3566491886 |
| Directory | /workspace/8.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1101639732 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 353195986 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:25:54 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 196288 kb |
| Host | smart-3739d781-3483-407d-8fb9-ca60d486dfa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101639732 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1101639732 |
| Directory | /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1235380573 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 512209206 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:25:55 PM PDT 24 |
| Finished | Aug 03 04:25:55 PM PDT 24 |
| Peak memory | 192900 kb |
| Host | smart-ef4e6bdf-a445-4d7f-a947-168f0dca0fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235380573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1235380573 |
| Directory | /workspace/9.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3726316348 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 284213617 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:25:58 PM PDT 24 |
| Finished | Aug 03 04:25:59 PM PDT 24 |
| Peak memory | 183616 kb |
| Host | smart-c7ff6486-0a80-4b8d-9b40-6626f6e535c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726316348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3726316348 |
| Directory | /workspace/9.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1610337572 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2574683717 ps |
| CPU time | 2.8 seconds |
| Started | Aug 03 04:25:45 PM PDT 24 |
| Finished | Aug 03 04:25:48 PM PDT 24 |
| Peak memory | 193876 kb |
| Host | smart-8fb03b79-d3ad-40b0-8fd2-9c0bf44438a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610337572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon _timer_same_csr_outstanding.1610337572 |
| Directory | /workspace/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2614382339 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 424806049 ps |
| CPU time | 1.46 seconds |
| Started | Aug 03 04:26:02 PM PDT 24 |
| Finished | Aug 03 04:26:04 PM PDT 24 |
| Peak memory | 198472 kb |
| Host | smart-b5113bad-e72a-488e-bb6c-109ad8c76411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614382339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2614382339 |
| Directory | /workspace/9.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.446822781 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4427867635 ps |
| CPU time | 2.04 seconds |
| Started | Aug 03 04:25:57 PM PDT 24 |
| Finished | Aug 03 04:26:00 PM PDT 24 |
| Peak memory | 197752 kb |
| Host | smart-a21174c3-6852-451b-bfbf-68b356d3a53d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446822781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_ intg_err.446822781 |
| Directory | /workspace/9.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.aon_timer_prescaler.1038949979 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11708729288 ps |
| CPU time | 5.05 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:27:40 PM PDT 24 |
| Peak memory | 191700 kb |
| Host | smart-cca6d4fe-94da-4f46-9cae-209fa7aad61b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038949979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1038949979 |
| Directory | /workspace/0.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/0.aon_timer_smoke.3252507704 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 482959306 ps |
| CPU time | 0.7 seconds |
| Started | Aug 03 04:27:25 PM PDT 24 |
| Finished | Aug 03 04:27:26 PM PDT 24 |
| Peak memory | 191556 kb |
| Host | smart-96d7cbe6-44af-4102-ac96-7bc3734b5be0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252507704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3252507704 |
| Directory | /workspace/0.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/1.aon_timer_prescaler.249261740 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 17643491641 ps |
| CPU time | 7.76 seconds |
| Started | Aug 03 04:27:48 PM PDT 24 |
| Finished | Aug 03 04:27:55 PM PDT 24 |
| Peak memory | 196832 kb |
| Host | smart-fcab0dda-e030-46c8-8d40-de632a9b48e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249261740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.249261740 |
| Directory | /workspace/1.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/1.aon_timer_sec_cm.2287573153 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8635688543 ps |
| CPU time | 2.04 seconds |
| Started | Aug 03 04:27:34 PM PDT 24 |
| Finished | Aug 03 04:27:36 PM PDT 24 |
| Peak memory | 215576 kb |
| Host | smart-1aedc32e-83f6-4d39-ae0e-e91b7dc381ca |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287573153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2287573153 |
| Directory | /workspace/1.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.aon_timer_smoke.2854893605 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 599547545 ps |
| CPU time | 0.8 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:27:28 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-ebf4e050-ff1c-4b43-8f8c-523d128d6dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854893605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2854893605 |
| Directory | /workspace/1.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/10.aon_timer_prescaler.332145358 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8962956338 ps |
| CPU time | 1.43 seconds |
| Started | Aug 03 04:27:34 PM PDT 24 |
| Finished | Aug 03 04:27:36 PM PDT 24 |
| Peak memory | 191696 kb |
| Host | smart-3a21408d-6de4-4557-98d8-ca86dbfb9c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332145358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.332145358 |
| Directory | /workspace/10.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/10.aon_timer_smoke.1233200786 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 567765772 ps |
| CPU time | 1.4 seconds |
| Started | Aug 03 04:27:42 PM PDT 24 |
| Finished | Aug 03 04:27:43 PM PDT 24 |
| Peak memory | 196396 kb |
| Host | smart-ec9f8c60-46fa-4db6-bc87-e57fce196b7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233200786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1233200786 |
| Directory | /workspace/10.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/11.aon_timer_prescaler.858396285 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2877429579 ps |
| CPU time | 2.46 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:27:48 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-a67fda18-7034-4636-b272-9f6b9151dbd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858396285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.858396285 |
| Directory | /workspace/11.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/11.aon_timer_smoke.2354352225 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 515044332 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:27:43 PM PDT 24 |
| Finished | Aug 03 04:27:44 PM PDT 24 |
| Peak memory | 191572 kb |
| Host | smart-c7b9f875-43b7-484e-8804-b438782fbaef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354352225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2354352225 |
| Directory | /workspace/11.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/12.aon_timer_prescaler.889414304 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12609659072 ps |
| CPU time | 18.7 seconds |
| Started | Aug 03 04:27:42 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 191680 kb |
| Host | smart-0bb14b8c-4e54-4ee2-8e56-4644d462c436 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889414304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.889414304 |
| Directory | /workspace/12.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/12.aon_timer_smoke.205419360 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 443343970 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:27:36 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-78b0f5b7-e60f-43ca-a09c-fb6a94a3bfa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205419360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.205419360 |
| Directory | /workspace/12.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/13.aon_timer_prescaler.2873863822 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 36447650019 ps |
| CPU time | 12.66 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:27:51 PM PDT 24 |
| Peak memory | 191696 kb |
| Host | smart-a49ba9c3-1bdf-4eb8-a671-6dbcce7f7706 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873863822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2873863822 |
| Directory | /workspace/13.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/13.aon_timer_smoke.2729646416 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 587780092 ps |
| CPU time | 1.36 seconds |
| Started | Aug 03 04:27:42 PM PDT 24 |
| Finished | Aug 03 04:27:44 PM PDT 24 |
| Peak memory | 191972 kb |
| Host | smart-e47c48b9-11df-4e51-8d8c-6a411f6a7275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729646416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2729646416 |
| Directory | /workspace/13.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/14.aon_timer_prescaler.3875201610 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 25171543006 ps |
| CPU time | 20.96 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:28:00 PM PDT 24 |
| Peak memory | 191700 kb |
| Host | smart-ad23cf6e-e370-42b7-ac41-7ed06bab67f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875201610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3875201610 |
| Directory | /workspace/14.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/14.aon_timer_smoke.608034013 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 442408674 ps |
| CPU time | 0.67 seconds |
| Started | Aug 03 04:27:33 PM PDT 24 |
| Finished | Aug 03 04:27:34 PM PDT 24 |
| Peak memory | 191620 kb |
| Host | smart-008ecc1e-26ff-4715-a04c-aabf9d4d82f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608034013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.608034013 |
| Directory | /workspace/14.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/15.aon_timer_jump.3462600223 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 441683103 ps |
| CPU time | 0.97 seconds |
| Started | Aug 03 04:27:40 PM PDT 24 |
| Finished | Aug 03 04:27:41 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-de950c1a-e06c-4667-b719-f1c09d74542b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462600223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3462600223 |
| Directory | /workspace/15.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_prescaler.1694828301 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 24616153232 ps |
| CPU time | 16.9 seconds |
| Started | Aug 03 04:27:35 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 191636 kb |
| Host | smart-92dfaf6c-aa15-4b89-bbaf-4d0d9c2cf69b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694828301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1694828301 |
| Directory | /workspace/15.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/15.aon_timer_smoke.1094562018 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 410174075 ps |
| CPU time | 0.72 seconds |
| Started | Aug 03 04:27:31 PM PDT 24 |
| Finished | Aug 03 04:27:32 PM PDT 24 |
| Peak memory | 196364 kb |
| Host | smart-f6ce6343-313d-4fff-824a-cf3338d2393c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094562018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1094562018 |
| Directory | /workspace/15.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_prescaler.2535567702 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 20029311851 ps |
| CPU time | 29 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:28:07 PM PDT 24 |
| Peak memory | 191656 kb |
| Host | smart-060a558f-b86c-4e28-b391-f3e3539a08e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535567702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2535567702 |
| Directory | /workspace/16.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/16.aon_timer_smoke.3337368767 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 407085236 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:27:37 PM PDT 24 |
| Finished | Aug 03 04:27:38 PM PDT 24 |
| Peak memory | 191592 kb |
| Host | smart-f2fe9fed-2584-4efc-87c8-dfa0930cb3ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337368767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3337368767 |
| Directory | /workspace/16.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/17.aon_timer_prescaler.1850311722 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 36921294199 ps |
| CPU time | 59.87 seconds |
| Started | Aug 03 04:27:36 PM PDT 24 |
| Finished | Aug 03 04:28:36 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-d458fd44-c810-49f2-9c1e-276c7b92452c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850311722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1850311722 |
| Directory | /workspace/17.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/17.aon_timer_smoke.3825212598 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 448920031 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:27:39 PM PDT 24 |
| Peak memory | 191592 kb |
| Host | smart-1961b890-ba08-497b-9f7e-da44de5430ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825212598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3825212598 |
| Directory | /workspace/17.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/18.aon_timer_prescaler.54732488 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 35000858493 ps |
| CPU time | 45.51 seconds |
| Started | Aug 03 04:27:37 PM PDT 24 |
| Finished | Aug 03 04:28:22 PM PDT 24 |
| Peak memory | 196716 kb |
| Host | smart-02cbf458-e2e4-4cc2-8500-d972f271febe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54732488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.54732488 |
| Directory | /workspace/18.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/18.aon_timer_smoke.2929595726 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 623292627 ps |
| CPU time | 0.94 seconds |
| Started | Aug 03 04:27:43 PM PDT 24 |
| Finished | Aug 03 04:27:44 PM PDT 24 |
| Peak memory | 191568 kb |
| Host | smart-17a6a3da-e400-4969-9359-8c2cfced145b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929595726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2929595726 |
| Directory | /workspace/18.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/19.aon_timer_jump.385384474 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 381948506 ps |
| CPU time | 0.76 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:45 PM PDT 24 |
| Peak memory | 196400 kb |
| Host | smart-c5866769-3574-4754-b286-4c42efa09850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385384474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.385384474 |
| Directory | /workspace/19.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/19.aon_timer_prescaler.1552194408 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 41348123981 ps |
| CPU time | 11.43 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:55 PM PDT 24 |
| Peak memory | 196600 kb |
| Host | smart-38f710f8-a3cf-4177-a53e-c8e2bd74e1da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552194408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1552194408 |
| Directory | /workspace/19.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/19.aon_timer_smoke.2584466971 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 592312425 ps |
| CPU time | 0.91 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 191972 kb |
| Host | smart-b2f02909-ab09-467e-85ec-1ec366419c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584466971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2584466971 |
| Directory | /workspace/19.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/2.aon_timer_prescaler.1724187700 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 30981513605 ps |
| CPU time | 3.83 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:27:44 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-8b66a30c-bafc-49f8-a946-b25994ced621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724187700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1724187700 |
| Directory | /workspace/2.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/2.aon_timer_sec_cm.1969518814 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4434303577 ps |
| CPU time | 2.39 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 215720 kb |
| Host | smart-05947a46-88e6-44cf-a1d1-ee6589897857 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969518814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1969518814 |
| Directory | /workspace/2.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.aon_timer_smoke.1478042778 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 536297728 ps |
| CPU time | 1.32 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-b2f8e287-88e5-4676-aca5-c5f79d8c496f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478042778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1478042778 |
| Directory | /workspace/2.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/20.aon_timer_jump.3358009801 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 445238779 ps |
| CPU time | 0.95 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-6e5fde36-e09a-4010-94dd-2c1fa7849057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358009801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3358009801 |
| Directory | /workspace/20.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_prescaler.2423269787 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 16727675068 ps |
| CPU time | 24.23 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:28:10 PM PDT 24 |
| Peak memory | 191632 kb |
| Host | smart-4ec258ca-da9b-4342-93d8-11cefb1669ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423269787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2423269787 |
| Directory | /workspace/20.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/20.aon_timer_smoke.1348923952 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 544695757 ps |
| CPU time | 0.67 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:27:47 PM PDT 24 |
| Peak memory | 196352 kb |
| Host | smart-a96e4d23-450d-436c-8b5a-432b221dc4c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348923952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1348923952 |
| Directory | /workspace/20.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/21.aon_timer_prescaler.1680479122 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 32009415768 ps |
| CPU time | 42.46 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:28:27 PM PDT 24 |
| Peak memory | 196708 kb |
| Host | smart-a2bfe30e-3864-4cb8-8888-7c6b854c4b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680479122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1680479122 |
| Directory | /workspace/21.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/21.aon_timer_smoke.4145230351 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 453245460 ps |
| CPU time | 0.94 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:27:55 PM PDT 24 |
| Peak memory | 191624 kb |
| Host | smart-c13322f4-7105-49dc-b2ad-229381a56ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145230351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4145230351 |
| Directory | /workspace/21.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/22.aon_timer_prescaler.4255517893 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 15271129487 ps |
| CPU time | 21.42 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:28:08 PM PDT 24 |
| Peak memory | 191628 kb |
| Host | smart-200b2dc1-a5bf-4ef8-b2ef-cf9bbef87346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255517893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4255517893 |
| Directory | /workspace/22.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/22.aon_timer_smoke.3195115214 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 507827342 ps |
| CPU time | 1.4 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:45 PM PDT 24 |
| Peak memory | 191624 kb |
| Host | smart-85a37178-aad7-47f4-9295-2004101a9701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195115214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3195115214 |
| Directory | /workspace/22.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/23.aon_timer_prescaler.1046742708 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 20462769700 ps |
| CPU time | 8.07 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:28:00 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-55220056-e957-42d1-bcac-0a10bd996943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046742708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1046742708 |
| Directory | /workspace/23.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/23.aon_timer_smoke.3910068805 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 617575986 ps |
| CPU time | 0.8 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 191588 kb |
| Host | smart-fecb7405-9457-49ed-b034-60e9d690f50d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910068805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3910068805 |
| Directory | /workspace/23.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/24.aon_timer_prescaler.3570311986 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 6906665415 ps |
| CPU time | 2.89 seconds |
| Started | Aug 03 04:27:49 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 191632 kb |
| Host | smart-4ba2f118-39ed-408d-93a2-b97b3c90350d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570311986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3570311986 |
| Directory | /workspace/24.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/24.aon_timer_smoke.4079312095 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 414292302 ps |
| CPU time | 0.87 seconds |
| Started | Aug 03 04:27:39 PM PDT 24 |
| Finished | Aug 03 04:27:40 PM PDT 24 |
| Peak memory | 191632 kb |
| Host | smart-8da9b7cd-3ba9-4de3-b919-8827bbe3bb56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079312095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4079312095 |
| Directory | /workspace/24.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/25.aon_timer_prescaler.269166295 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 40476232757 ps |
| CPU time | 56.14 seconds |
| Started | Aug 03 04:27:38 PM PDT 24 |
| Finished | Aug 03 04:28:35 PM PDT 24 |
| Peak memory | 191632 kb |
| Host | smart-4f24ea69-cb93-44d2-8abd-34c1014a4a3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269166295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.269166295 |
| Directory | /workspace/25.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/25.aon_timer_smoke.393103694 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 540607490 ps |
| CPU time | 0.72 seconds |
| Started | Aug 03 04:27:47 PM PDT 24 |
| Finished | Aug 03 04:27:48 PM PDT 24 |
| Peak memory | 191564 kb |
| Host | smart-b27f0e4b-06b1-4be3-8879-a44984739553 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393103694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.393103694 |
| Directory | /workspace/25.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/26.aon_timer_prescaler.1087490418 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 32632773045 ps |
| CPU time | 15.62 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:28:16 PM PDT 24 |
| Peak memory | 191700 kb |
| Host | smart-2dc4694b-5c69-43f9-a992-6aa27bdc92dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087490418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1087490418 |
| Directory | /workspace/26.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/26.aon_timer_smoke.2656345760 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 437337711 ps |
| CPU time | 0.91 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:27:42 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-9239324c-5033-476b-8af5-817b23530f2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656345760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2656345760 |
| Directory | /workspace/26.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all.78614471 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 44250597674 ps |
| CPU time | 15.94 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:28:08 PM PDT 24 |
| Peak memory | 198028 kb |
| Host | smart-850e4f1f-8dd6-4266-a926-6b48e9959911 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78614471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_al l.78614471 |
| Directory | /workspace/26.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.aon_timer_prescaler.3568513151 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3654226406 ps |
| CPU time | 2.07 seconds |
| Started | Aug 03 04:27:48 PM PDT 24 |
| Finished | Aug 03 04:27:50 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-24f01f7f-33b3-4a19-9772-715953eb88fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568513151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3568513151 |
| Directory | /workspace/27.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/27.aon_timer_smoke.1441463572 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 526831469 ps |
| CPU time | 0.76 seconds |
| Started | Aug 03 04:27:54 PM PDT 24 |
| Finished | Aug 03 04:27:55 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-b4d789d4-de51-4f9e-b34f-49b244dae1e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441463572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1441463572 |
| Directory | /workspace/27.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/28.aon_timer_prescaler.2304176273 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 6098706127 ps |
| CPU time | 9.58 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:27:55 PM PDT 24 |
| Peak memory | 191660 kb |
| Host | smart-f4cfd70c-2e34-41e4-b6c9-273c45a67163 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304176273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2304176273 |
| Directory | /workspace/28.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/28.aon_timer_smoke.2690150768 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 559515575 ps |
| CPU time | 1.4 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:27:59 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-b7cdf4b7-8549-44df-9762-1cc0c0ca5a7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690150768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2690150768 |
| Directory | /workspace/28.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/29.aon_timer_prescaler.3400722167 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5248785958 ps |
| CPU time | 2.55 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:27:48 PM PDT 24 |
| Peak memory | 191636 kb |
| Host | smart-366c7ff4-c422-4c47-bbf2-4c26377e26c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400722167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3400722167 |
| Directory | /workspace/29.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/29.aon_timer_smoke.3230723339 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 558389720 ps |
| CPU time | 1.16 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 196348 kb |
| Host | smart-524905b3-7f8b-4911-97d2-801d2a454211 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230723339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3230723339 |
| Directory | /workspace/29.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/3.aon_timer_prescaler.2862551144 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 27480126616 ps |
| CPU time | 6.58 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 196656 kb |
| Host | smart-dbb1da90-afa3-4a11-97e3-21b938d2c37b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862551144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2862551144 |
| Directory | /workspace/3.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/3.aon_timer_sec_cm.1877666662 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8473702129 ps |
| CPU time | 2.33 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:31 PM PDT 24 |
| Peak memory | 215488 kb |
| Host | smart-dd7ca499-6034-4f61-bd99-b96a8fb6e167 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877666662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1877666662 |
| Directory | /workspace/3.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.aon_timer_smoke.4011906830 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 419827157 ps |
| CPU time | 0.82 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 191596 kb |
| Host | smart-6cae6985-a514-44b0-a7fc-8f5a06e6a9bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011906830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.4011906830 |
| Directory | /workspace/3.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/30.aon_timer_jump.516082706 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 550193486 ps |
| CPU time | 1.41 seconds |
| Started | Aug 03 04:27:46 PM PDT 24 |
| Finished | Aug 03 04:27:48 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-f6f4ff8b-6e19-4a50-90bc-e85dedff1f95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516082706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.516082706 |
| Directory | /workspace/30.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/30.aon_timer_prescaler.2971568864 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5285196154 ps |
| CPU time | 8.7 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-c9f787ba-f145-436f-a058-ac4625a039f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971568864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2971568864 |
| Directory | /workspace/30.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/30.aon_timer_smoke.4265420292 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 451146563 ps |
| CPU time | 0.9 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:02 PM PDT 24 |
| Peak memory | 196468 kb |
| Host | smart-2b181ce3-468f-4cb9-adf7-ac08a64f476a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265420292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4265420292 |
| Directory | /workspace/30.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/31.aon_timer_prescaler.670491008 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 59933869483 ps |
| CPU time | 92.61 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:29:24 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-55a0966e-1f8a-40fb-83c3-ebc7e79bca41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670491008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.670491008 |
| Directory | /workspace/31.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/31.aon_timer_smoke.1432952855 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 541058677 ps |
| CPU time | 1.42 seconds |
| Started | Aug 03 04:27:44 PM PDT 24 |
| Finished | Aug 03 04:27:45 PM PDT 24 |
| Peak memory | 191116 kb |
| Host | smart-22ef629e-243a-49f1-a800-7efcba055971 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432952855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1432952855 |
| Directory | /workspace/31.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/32.aon_timer_prescaler.3213932364 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 35584336499 ps |
| CPU time | 49.07 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:28:53 PM PDT 24 |
| Peak memory | 196780 kb |
| Host | smart-ccf79b25-620d-42c2-b8d0-30ec5c3e0968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213932364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3213932364 |
| Directory | /workspace/32.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/32.aon_timer_smoke.1254261991 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 589022931 ps |
| CPU time | 0.78 seconds |
| Started | Aug 03 04:27:45 PM PDT 24 |
| Finished | Aug 03 04:27:46 PM PDT 24 |
| Peak memory | 191628 kb |
| Host | smart-3a87c92c-337d-41e8-b5d4-d804c1e2af4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254261991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1254261991 |
| Directory | /workspace/32.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/33.aon_timer_prescaler.484674510 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 23818333399 ps |
| CPU time | 9.55 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:28:01 PM PDT 24 |
| Peak memory | 191652 kb |
| Host | smart-ebc43e0b-55d7-44d1-9f09-e007ff4e16f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484674510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.484674510 |
| Directory | /workspace/33.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/33.aon_timer_smoke.3398774500 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 499861246 ps |
| CPU time | 1.32 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 191580 kb |
| Host | smart-74235a09-1045-4d62-a929-65c68015b7b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398774500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3398774500 |
| Directory | /workspace/33.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/34.aon_timer_prescaler.3692071259 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 25775041380 ps |
| CPU time | 7.32 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-83273461-2129-4763-9bb2-a8bda7abd222 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692071259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3692071259 |
| Directory | /workspace/34.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/34.aon_timer_smoke.42451674 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 438917066 ps |
| CPU time | 1.27 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:27:53 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-3cb582c0-f1cc-44f9-9c4d-7cb3a6f2c295 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42451674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.42451674 |
| Directory | /workspace/34.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/35.aon_timer_prescaler.172577931 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 31695442871 ps |
| CPU time | 50.86 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:52 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-9574f904-4440-4eac-8c3d-4b20da96e355 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172577931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.172577931 |
| Directory | /workspace/35.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/35.aon_timer_smoke.1269982739 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 488441022 ps |
| CPU time | 0.62 seconds |
| Started | Aug 03 04:27:51 PM PDT 24 |
| Finished | Aug 03 04:27:52 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-514a76aa-69a0-4e0a-85e0-a8f55191da03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269982739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1269982739 |
| Directory | /workspace/35.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/36.aon_timer_prescaler.203898190 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 14680120389 ps |
| CPU time | 11.58 seconds |
| Started | Aug 03 04:27:53 PM PDT 24 |
| Finished | Aug 03 04:28:05 PM PDT 24 |
| Peak memory | 191600 kb |
| Host | smart-9e402555-acc1-4fe6-969b-7d682a4d470e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203898190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.203898190 |
| Directory | /workspace/36.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/36.aon_timer_smoke.3672381102 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 437700651 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:04 PM PDT 24 |
| Peak memory | 191660 kb |
| Host | smart-630beb14-9924-43c1-9ff9-fc7af21eb0b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672381102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3672381102 |
| Directory | /workspace/36.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/37.aon_timer_prescaler.3218358126 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 18969901711 ps |
| CPU time | 24.3 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:28:17 PM PDT 24 |
| Peak memory | 191656 kb |
| Host | smart-6fd4a98c-5d43-4f8a-97b8-7f9f57ad8816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218358126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3218358126 |
| Directory | /workspace/37.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/37.aon_timer_smoke.1588665718 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 383549531 ps |
| CPU time | 1.07 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:02 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-fb668918-6327-4f7e-a91e-e441bbdbf9c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588665718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1588665718 |
| Directory | /workspace/37.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/38.aon_timer_prescaler.1660742440 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 27496505516 ps |
| CPU time | 23.13 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:26 PM PDT 24 |
| Peak memory | 191696 kb |
| Host | smart-36627e00-0d17-4f39-9d6a-42f974fe23f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660742440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1660742440 |
| Directory | /workspace/38.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/38.aon_timer_smoke.3966762504 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 489533291 ps |
| CPU time | 0.93 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 196508 kb |
| Host | smart-642c10d9-1ddd-4aed-842d-14f2625fef00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966762504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3966762504 |
| Directory | /workspace/38.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/39.aon_timer_prescaler.2333451408 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 31220089541 ps |
| CPU time | 47.12 seconds |
| Started | Aug 03 04:27:52 PM PDT 24 |
| Finished | Aug 03 04:28:39 PM PDT 24 |
| Peak memory | 191768 kb |
| Host | smart-5759d6cd-2208-42a6-a191-e117dafa9f5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333451408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2333451408 |
| Directory | /workspace/39.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/39.aon_timer_smoke.3756553521 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 385945987 ps |
| CPU time | 0.69 seconds |
| Started | Aug 03 04:27:53 PM PDT 24 |
| Finished | Aug 03 04:27:54 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-147ef089-5670-40e7-ab7b-1b6d5dcadfbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756553521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3756553521 |
| Directory | /workspace/39.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/4.aon_timer_prescaler.434943125 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5722019633 ps |
| CPU time | 9.48 seconds |
| Started | Aug 03 04:27:41 PM PDT 24 |
| Finished | Aug 03 04:27:50 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-9ea3c237-0ddd-4c31-9ce4-5708d0ca71f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=434943125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.434943125 |
| Directory | /workspace/4.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/4.aon_timer_sec_cm.1216192721 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4129699562 ps |
| CPU time | 6.92 seconds |
| Started | Aug 03 04:27:26 PM PDT 24 |
| Finished | Aug 03 04:27:33 PM PDT 24 |
| Peak memory | 215136 kb |
| Host | smart-bd085ef5-eab1-4972-937d-7a0ee82a5914 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216192721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1216192721 |
| Directory | /workspace/4.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.aon_timer_smoke.3481383950 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 390509949 ps |
| CPU time | 0.78 seconds |
| Started | Aug 03 04:27:25 PM PDT 24 |
| Finished | Aug 03 04:27:26 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-3eb6bcdb-9b93-4dff-abc7-b47b3300e42b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481383950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3481383950 |
| Directory | /workspace/4.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/40.aon_timer_prescaler.1929792026 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5706997977 ps |
| CPU time | 8.81 seconds |
| Started | Aug 03 04:27:59 PM PDT 24 |
| Finished | Aug 03 04:28:08 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-d106f055-f086-49eb-a41d-6c914d67b671 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929792026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1929792026 |
| Directory | /workspace/40.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/40.aon_timer_smoke.2217649656 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 466282432 ps |
| CPU time | 1.28 seconds |
| Started | Aug 03 04:27:56 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 191720 kb |
| Host | smart-7e2fdb20-55e4-40dc-8d0d-e080f4e9e0c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217649656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2217649656 |
| Directory | /workspace/40.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/41.aon_timer_prescaler.3356761058 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 10406772883 ps |
| CPU time | 3.49 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:06 PM PDT 24 |
| Peak memory | 191672 kb |
| Host | smart-865e37e5-e039-4f8f-8a3c-aa4dc67ad09b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356761058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3356761058 |
| Directory | /workspace/41.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/41.aon_timer_smoke.118961095 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 550212843 ps |
| CPU time | 1.29 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 191604 kb |
| Host | smart-b9745653-b132-4800-a5d4-59f1f9be85eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118961095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.118961095 |
| Directory | /workspace/41.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/42.aon_timer_jump.3763755560 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 589565924 ps |
| CPU time | 0.72 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-3d06c1c0-08fe-43cd-9e48-657dd8e8a8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763755560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3763755560 |
| Directory | /workspace/42.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/42.aon_timer_prescaler.4165583519 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 57905600062 ps |
| CPU time | 23.49 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:28:21 PM PDT 24 |
| Peak memory | 191640 kb |
| Host | smart-42bbbe89-f903-4c4d-8deb-69a2a4692af5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165583519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4165583519 |
| Directory | /workspace/42.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/42.aon_timer_smoke.4226943502 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 463977700 ps |
| CPU time | 1.17 seconds |
| Started | Aug 03 04:28:07 PM PDT 24 |
| Finished | Aug 03 04:28:08 PM PDT 24 |
| Peak memory | 191640 kb |
| Host | smart-c8ab8203-8cb0-4f71-a3f7-29b340b58acc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226943502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4226943502 |
| Directory | /workspace/42.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/43.aon_timer_prescaler.4225311936 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 12568925437 ps |
| CPU time | 1.84 seconds |
| Started | Aug 03 04:28:07 PM PDT 24 |
| Finished | Aug 03 04:28:09 PM PDT 24 |
| Peak memory | 196688 kb |
| Host | smart-a3132762-a28c-4a03-929f-1f60af2346b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225311936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4225311936 |
| Directory | /workspace/43.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/43.aon_timer_smoke.2124011013 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 623136554 ps |
| CPU time | 0.74 seconds |
| Started | Aug 03 04:28:02 PM PDT 24 |
| Finished | Aug 03 04:28:02 PM PDT 24 |
| Peak memory | 191612 kb |
| Host | smart-8ebc3257-8af3-45c5-9bfa-f5a5806a7e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124011013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2124011013 |
| Directory | /workspace/43.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/44.aon_timer_jump.2387297552 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 638795163 ps |
| CPU time | 0.64 seconds |
| Started | Aug 03 04:27:57 PM PDT 24 |
| Finished | Aug 03 04:27:58 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-ef5a21e1-4bff-4d34-887b-ab47eabb53b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387297552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2387297552 |
| Directory | /workspace/44.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_prescaler.2676283702 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 18858091171 ps |
| CPU time | 29.48 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:31 PM PDT 24 |
| Peak memory | 196688 kb |
| Host | smart-68d084da-209a-4ce2-bec7-92ad14db7d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676283702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2676283702 |
| Directory | /workspace/44.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/44.aon_timer_smoke.1538548591 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 562965280 ps |
| CPU time | 1.03 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:27:59 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-46165f1f-09ca-46b9-b17b-192d82933e13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538548591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1538548591 |
| Directory | /workspace/44.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/45.aon_timer_prescaler.3557440152 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 39877399150 ps |
| CPU time | 14.73 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:28:19 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-6e9e5ba0-9caa-459f-8f05-70b0f5244d76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557440152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3557440152 |
| Directory | /workspace/45.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/45.aon_timer_smoke.3083234887 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 456535076 ps |
| CPU time | 0.72 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:04 PM PDT 24 |
| Peak memory | 191592 kb |
| Host | smart-0650cf7e-8d3c-4994-ab5d-4bb81bc8ef8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083234887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3083234887 |
| Directory | /workspace/45.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/46.aon_timer_prescaler.2199461382 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 11305320555 ps |
| CPU time | 17.25 seconds |
| Started | Aug 03 04:28:04 PM PDT 24 |
| Finished | Aug 03 04:28:22 PM PDT 24 |
| Peak memory | 191732 kb |
| Host | smart-9c44d723-3c80-46f8-b3ba-c6568863a20b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199461382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2199461382 |
| Directory | /workspace/46.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/46.aon_timer_smoke.718574302 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 633467681 ps |
| CPU time | 0.77 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:27:59 PM PDT 24 |
| Peak memory | 191560 kb |
| Host | smart-2a643b34-1c1a-40a3-85ce-4aac56b7238e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718574302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.718574302 |
| Directory | /workspace/46.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3672697325 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 84262148687 ps |
| CPU time | 92.83 seconds |
| Started | Aug 03 04:28:05 PM PDT 24 |
| Finished | Aug 03 04:29:38 PM PDT 24 |
| Peak memory | 206472 kb |
| Host | smart-e46e332d-c076-4111-b612-ab9160aef93d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672697325 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3672697325 |
| Directory | /workspace/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.aon_timer_prescaler.1229102501 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 34873092982 ps |
| CPU time | 28.25 seconds |
| Started | Aug 03 04:28:01 PM PDT 24 |
| Finished | Aug 03 04:28:30 PM PDT 24 |
| Peak memory | 196684 kb |
| Host | smart-0b4d47a7-90a8-444e-a6df-0d4eaa46b363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229102501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1229102501 |
| Directory | /workspace/47.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/47.aon_timer_smoke.3503025061 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 356998478 ps |
| CPU time | 1.08 seconds |
| Started | Aug 03 04:28:11 PM PDT 24 |
| Finished | Aug 03 04:28:12 PM PDT 24 |
| Peak memory | 191588 kb |
| Host | smart-349d4307-f4fa-4757-bf42-4ec5bcad84e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503025061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3503025061 |
| Directory | /workspace/47.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/48.aon_timer_prescaler.2789937147 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3048438662 ps |
| CPU time | 3.01 seconds |
| Started | Aug 03 04:28:00 PM PDT 24 |
| Finished | Aug 03 04:28:03 PM PDT 24 |
| Peak memory | 191704 kb |
| Host | smart-13bce280-cd3c-4e87-82f5-ce2127334fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789937147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2789937147 |
| Directory | /workspace/48.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/48.aon_timer_smoke.2228255562 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 446742267 ps |
| CPU time | 0.73 seconds |
| Started | Aug 03 04:28:03 PM PDT 24 |
| Finished | Aug 03 04:28:04 PM PDT 24 |
| Peak memory | 191640 kb |
| Host | smart-01691cac-b6ce-457d-9242-b0acb36553b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228255562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2228255562 |
| Directory | /workspace/48.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/49.aon_timer_prescaler.2409070630 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 31802877492 ps |
| CPU time | 42.49 seconds |
| Started | Aug 03 04:28:06 PM PDT 24 |
| Finished | Aug 03 04:28:48 PM PDT 24 |
| Peak memory | 191652 kb |
| Host | smart-b3e18fdd-0c95-4bb7-8f02-d5739a8515e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409070630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2409070630 |
| Directory | /workspace/49.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/49.aon_timer_smoke.2663910253 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 441618912 ps |
| CPU time | 1 seconds |
| Started | Aug 03 04:27:58 PM PDT 24 |
| Finished | Aug 03 04:28:00 PM PDT 24 |
| Peak memory | 191596 kb |
| Host | smart-05debe16-33cb-4e74-a839-a582ebd0818d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663910253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2663910253 |
| Directory | /workspace/49.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/5.aon_timer_prescaler.560921347 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 49634149811 ps |
| CPU time | 4.09 seconds |
| Started | Aug 03 04:27:25 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 191668 kb |
| Host | smart-a64369a4-a994-46a0-b311-9cf17d053838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560921347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.560921347 |
| Directory | /workspace/5.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/5.aon_timer_smoke.4167366517 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 554931770 ps |
| CPU time | 1.43 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:27:29 PM PDT 24 |
| Peak memory | 191580 kb |
| Host | smart-59e70883-4b61-49a7-aff2-6df9448292b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4167366517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4167366517 |
| Directory | /workspace/5.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/6.aon_timer_prescaler.1372902948 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 38918485370 ps |
| CPU time | 12.98 seconds |
| Started | Aug 03 04:27:27 PM PDT 24 |
| Finished | Aug 03 04:27:41 PM PDT 24 |
| Peak memory | 191636 kb |
| Host | smart-4bfe18af-92ea-489d-bde3-2e4b05bf9516 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372902948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1372902948 |
| Directory | /workspace/6.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/6.aon_timer_smoke.2707776834 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 495168986 ps |
| CPU time | 0.71 seconds |
| Started | Aug 03 04:27:26 PM PDT 24 |
| Finished | Aug 03 04:27:27 PM PDT 24 |
| Peak memory | 196312 kb |
| Host | smart-8d715eed-11cf-490c-9517-e11f6b889bdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707776834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2707776834 |
| Directory | /workspace/6.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/7.aon_timer_prescaler.2623180359 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 36516698909 ps |
| CPU time | 3.21 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:31 PM PDT 24 |
| Peak memory | 191672 kb |
| Host | smart-3e946160-1e01-4c77-9209-071372e544d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623180359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2623180359 |
| Directory | /workspace/7.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/7.aon_timer_smoke.182254791 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 573673729 ps |
| CPU time | 0.81 seconds |
| Started | Aug 03 04:27:30 PM PDT 24 |
| Finished | Aug 03 04:27:31 PM PDT 24 |
| Peak memory | 191644 kb |
| Host | smart-d1b9d67d-b810-41a8-9896-a0044eddc4f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182254791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.182254791 |
| Directory | /workspace/7.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/8.aon_timer_prescaler.1151811931 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 21032919750 ps |
| CPU time | 28.51 seconds |
| Started | Aug 03 04:27:28 PM PDT 24 |
| Finished | Aug 03 04:27:57 PM PDT 24 |
| Peak memory | 191672 kb |
| Host | smart-485a0e59-8cf4-4e3b-9ade-53a68a913a7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151811931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1151811931 |
| Directory | /workspace/8.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/8.aon_timer_smoke.4043861631 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 500158628 ps |
| CPU time | 1.27 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-437171f9-f37a-4041-96b2-fbe8ab709822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043861631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4043861631 |
| Directory | /workspace/8.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_jump.3856667434 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 452942895 ps |
| CPU time | 1.22 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 196548 kb |
| Host | smart-282b3822-1a8a-43dd-991d-55b9d0afd0d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856667434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3856667434 |
| Directory | /workspace/9.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/9.aon_timer_prescaler.29319083 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 38902579454 ps |
| CPU time | 27.21 seconds |
| Started | Aug 03 04:27:31 PM PDT 24 |
| Finished | Aug 03 04:27:59 PM PDT 24 |
| Peak memory | 191692 kb |
| Host | smart-5886107a-a588-403d-953b-b15b0f32c37a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29319083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.29319083 |
| Directory | /workspace/9.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/9.aon_timer_smoke.489730974 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 442927180 ps |
| CPU time | 0.88 seconds |
| Started | Aug 03 04:27:29 PM PDT 24 |
| Finished | Aug 03 04:27:30 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-c689bc89-6662-414e-9d49-07fd9eeb1410 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489730974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.489730974 |
| Directory | /workspace/9.aon_timer_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |