Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	25215	1		T1	12		T2	215		T3	381
bark[1]	757	1		T30	81		T96	56		T103	21
bark[2]	576	1		T13	14		T15	21		T91	14
bark[3]	631	1		T103	51		T39	21		T105	21
bark[4]	397	1		T32	146		T40	21		T136	14
bark[5]	219	1		T4	26		T37	21		T38	21
bark[6]	703	1		T3	76		T91	85		T42	65
bark[7]	476	1		T96	21		T140	119		T180	14
bark[8]	207	1		T39	21		T108	21		T117	21
bark[9]	746	1		T4	135		T15	49		T96	21
bark[10]	203	1		T13	26		T36	14		T155	14
bark[11]	230	1		T96	21		T37	30		T38	59
bark[12]	107	1		T12	14		T14	21		T16	21
bark[13]	149	1		T91	21		T127	21		T135	14
bark[14]	352	1		T103	21		T32	21		T130	26
bark[15]	273	1		T2	21		T15	26		T103	21
bark[16]	926	1		T32	7		T33	209		T140	30
bark[17]	320	1		T2	31		T7	14		T30	26
bark[18]	340	1		T10	26		T13	104		T41	14
bark[19]	320	1		T155	21		T99	21		T88	47
bark[20]	447	1		T2	38		T13	21		T34	45
bark[21]	1379	1		T14	21		T38	21		T182	14
bark[22]	805	1		T183	14		T117	568		T44	21
bark[23]	368	1		T15	43		T38	47		T190	14
bark[24]	311	1		T14	21		T24	14		T38	21
bark[25]	673	1		T8	14		T10	250		T151	14
bark[26]	718	1		T15	42		T137	21		T108	21
bark[27]	456	1		T3	30		T10	21		T15	160
bark[28]	464	1		T130	40		T85	5		T47	21
bark[29]	294	1		T37	14		T40	14		T87	31
bark[30]	515	1		T16	26		T39	21		T127	49
bark[31]	484	1		T14	52		T34	7		T87	200
bark_0	4332	1		T1	7		T2	7		T3	37

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	25156	1		T1	11		T2	214		T3	378
bite[1]	541	1		T12	13		T91	85		T96	30
bite[2]	606	1		T10	25		T87	30		T131	26
bite[3]	388	1		T4	26		T112	13		T108	21
bite[4]	338	1		T3	30		T140	30		T167	13
bite[5]	835	1		T15	25		T37	21		T38	38
bite[6]	631	1		T3	75		T14	21		T105	21
bite[7]	291	1		T2	21		T14	51		T137	21
bite[8]	360	1		T38	21		T103	21		T39	21
bite[9]	445	1		T13	104		T14	21		T127	21
bite[10]	358	1		T14	21		T16	21		T96	26
bite[11]	221	1		T13	21		T15	21		T37	13
bite[12]	154	1		T40	21		T170	18		T189	13
bite[13]	366	1		T4	135		T38	47		T155	21
bite[14]	521	1		T10	21		T91	13		T33	21
bite[15]	668	1		T37	30		T130	40		T153	13
bite[16]	475	1		T30	80		T96	21		T34	6
bite[17]	328	1		T15	90		T38	21		T103	21
bite[18]	239	1		T33	21		T155	21		T45	13
bite[19]	581	1		T13	26		T39	21		T140	118
bite[20]	443	1		T15	21		T103	21		T144	13
bite[21]	717	1		T10	249		T37	21		T183	13
bite[22]	360	1		T16	26		T140	21		T135	13
bite[23]	226	1		T36	13		T137	21		T99	21
bite[24]	416	1		T91	21		T96	21		T87	89
bite[25]	218	1		T103	21		T40	21		T127	49
bite[26]	725	1		T2	38		T24	13		T41	13
bite[27]	1795	1		T32	145		T182	13		T140	1097
bite[28]	446	1		T2	31		T13	13		T15	21
bite[29]	424	1		T8	13		T34	46		T147	21
bite[30]	84	1		T47	21		T134	21		T73	21
bite[31]	268	1		T30	47		T38	21		T103	21
bite_0	4769	1		T1	8		T2	8		T3	41

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37210	1		T1	19		T2	305		T3	524
auto[1]	7183	1		T2	7		T6	7		T13	20

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1008	1		T3	28		T14	136		T15	57
prescale[1]	507	1		T4	19		T37	19		T33	71
prescale[2]	340	1		T38	23		T197	9		T105	19
prescale[3]	972	1		T1	9		T14	19		T91	44
prescale[4]	771	1		T13	28		T30	2		T32	19
prescale[5]	621	1		T14	24		T96	42		T130	51
prescale[6]	435	1		T10	30		T103	23		T39	9
prescale[7]	322	1		T31	28		T127	32		T130	19
prescale[8]	894	1		T84	9		T103	19		T35	49
prescale[9]	544	1		T4	19		T14	83		T30	2
prescale[10]	920	1		T4	36		T14	47		T38	23
prescale[11]	1250	1		T3	97		T4	19		T10	2
prescale[12]	429	1		T94	9		T32	42		T33	26
prescale[13]	688	1		T91	28		T117	2		T88	94
prescale[14]	1284	1		T14	56		T15	2		T32	131
prescale[15]	716	1		T4	57		T14	19		T15	79
prescale[16]	1095	1		T2	36		T3	61		T4	19
prescale[17]	1430	1		T10	19		T13	23		T14	9
prescale[18]	645	1		T15	19		T91	28		T96	19
prescale[19]	648	1		T31	36		T198	9		T38	9
prescale[20]	667	1		T14	136		T96	24		T33	40
prescale[21]	528	1		T10	2		T14	2		T15	2
prescale[22]	760	1		T2	73		T13	38		T15	61
prescale[23]	417	1		T3	2		T96	9		T199	9
prescale[24]	515	1		T3	35		T30	2		T200	9
prescale[25]	694	1		T3	24		T10	2		T15	19
prescale[26]	463	1		T4	19		T16	36		T37	19
prescale[27]	680	1		T2	41		T14	51		T30	2
prescale[28]	407	1		T14	28		T15	9		T31	19
prescale[29]	661	1		T4	28		T13	23		T14	28
prescale[30]	550	1		T4	36		T14	19		T15	4
prescale[31]	774	1		T2	28		T10	87		T15	2
prescale_0	21758	1		T1	10		T2	134		T3	277

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32193	1		T1	9		T2	207		T3	408
auto[1]	12200	1		T1	10		T2	105		T3	116

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	44393	1		T1	19		T2	312		T3	524

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	25792	1		T1	14		T2	234		T3	360
wkup[1]	178	1		T131	26		T117	21		T86	21
wkup[2]	328	1		T3	21		T10	15		T39	21
wkup[3]	315	1		T34	21		T127	30		T108	21
wkup[4]	220	1		T31	6		T140	21		T130	21
wkup[5]	287	1		T2	31		T10	21		T33	21
wkup[6]	115	1		T50	21		T86	31		T100	21
wkup[7]	198	1		T31	21		T37	21		T88	21
wkup[8]	262	1		T13	21		T14	21		T15	21
wkup[9]	197	1		T15	21		T87	30		T117	26
wkup[10]	305	1		T4	21		T184	15		T105	21
wkup[11]	193	1		T14	21		T31	21		T140	26
wkup[12]	247	1		T14	51		T103	26		T33	21
wkup[13]	240	1		T4	21		T15	21		T38	26
wkup[14]	284	1		T103	21		T117	21		T154	21
wkup[15]	300	1		T10	51		T14	15		T33	21
wkup[16]	346	1		T24	15		T34	21		T108	21
wkup[17]	190	1		T137	21		T190	15		T88	21
wkup[18]	209	1		T2	21		T36	15		T41	15
wkup[19]	374	1		T30	21		T103	21		T32	21
wkup[20]	213	1		T10	21		T35	21		T127	21
wkup[21]	293	1		T13	15		T14	21		T15	21
wkup[22]	194	1		T15	21		T105	21		T89	21
wkup[23]	86	1		T108	21		T130	15		T122	21
wkup[24]	412	1		T15	15		T30	21		T103	30
wkup[25]	262	1		T32	26		T85	35		T189	15
wkup[26]	206	1		T4	26		T32	21		T33	21
wkup[27]	290	1		T31	26		T40	21		T112	15
wkup[28]	311	1		T37	15		T33	26		T130	26
wkup[29]	161	1		T91	21		T130	21		T147	21
wkup[30]	281	1		T32	8		T33	21		T140	39
wkup[31]	180	1		T103	21		T151	15		T42	30
wkup[32]	258	1		T14	21		T103	21		T40	15
wkup[33]	187	1		T3	21		T15	30		T136	15
wkup[34]	240	1		T91	21		T40	21		T137	21
wkup[35]	219	1		T15	21		T40	21		T117	21
wkup[36]	249	1		T14	21		T15	21		T32	21
wkup[37]	185	1		T31	35		T140	42		T137	21
wkup[38]	221	1		T7	15		T13	21		T40	21
wkup[39]	250	1		T16	26		T140	21		T42	21
wkup[40]	196	1		T96	26		T37	21		T33	21
wkup[41]	246	1		T3	21		T37	30		T38	42
wkup[42]	359	1		T15	44		T39	21		T117	26
wkup[43]	394	1		T10	21		T14	51		T15	51
wkup[44]	299	1		T2	21		T34	21		T87	21
wkup[45]	280	1		T30	21		T91	21		T31	21
wkup[46]	195	1		T15	26		T38	21		T39	21
wkup[47]	203	1		T12	15		T103	21		T32	21
wkup[48]	200	1		T3	21		T10	21		T14	21
wkup[49]	256	1		T13	26		T140	47		T117	21
wkup[50]	343	1		T14	21		T140	30		T105	21
wkup[51]	215	1		T3	21		T15	21		T88	21
wkup[52]	243	1		T14	21		T91	21		T140	21
wkup[53]	280	1		T38	21		T33	42		T135	15
wkup[54]	232	1		T144	15		T85	21		T160	15
wkup[55]	193	1		T35	21		T182	15		T127	21
wkup[56]	141	1		T87	21		T170	21		T86	21
wkup[57]	194	1		T32	29		T90	21		T70	21
wkup[58]	285	1		T91	26		T35	21		T87	26
wkup[59]	161	1		T14	26		T42	21		T86	21
wkup[60]	149	1		T3	30		T8	15		T117	21
wkup[61]	240	1		T15	21		T91	15		T137	21
wkup[62]	99	1		T99	21		T138	21		T124	21
wkup[63]	352	1		T10	35		T96	42		T32	21
wkup_0	3360	1		T1	5		T2	5		T3	29