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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.06 99.33 93.67 100.00 98.40 99.51 49.48


Total test records in report: 423
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T286 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3259616822 Aug 04 04:30:58 PM PDT 24 Aug 04 04:30:59 PM PDT 24 628927450 ps
T22 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3593888236 Aug 04 04:30:40 PM PDT 24 Aug 04 04:30:42 PM PDT 24 533251987 ps
T23 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4165867271 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:41 PM PDT 24 8514819061 ps
T28 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2103661611 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:38 PM PDT 24 540790705 ps
T29 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1341949540 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:44 PM PDT 24 1962267788 ps
T202 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2525518395 Aug 04 04:30:33 PM PDT 24 Aug 04 04:30:34 PM PDT 24 503349565 ps
T53 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.458792029 Aug 04 04:30:44 PM PDT 24 Aug 04 04:30:46 PM PDT 24 536093197 ps
T287 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2419255903 Aug 04 04:30:54 PM PDT 24 Aug 04 04:30:55 PM PDT 24 768839275 ps
T201 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3795532586 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:39 PM PDT 24 464827842 ps
T288 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.491831670 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:38 PM PDT 24 486893285 ps
T78 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2510327082 Aug 04 04:31:03 PM PDT 24 Aug 04 04:31:05 PM PDT 24 1062825174 ps
T289 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2719973355 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:50 PM PDT 24 436352785 ps
T25 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1447592365 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:36 PM PDT 24 8407105834 ps
T54 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4259390990 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:09 PM PDT 24 475070976 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1034163206 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:31 PM PDT 24 539821588 ps
T291 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3195811954 Aug 04 04:30:35 PM PDT 24 Aug 04 04:30:35 PM PDT 24 442663517 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2959264386 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:47 PM PDT 24 487566105 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.667113775 Aug 04 04:30:36 PM PDT 24 Aug 04 04:30:37 PM PDT 24 414943036 ps
T294 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2742632592 Aug 04 04:31:05 PM PDT 24 Aug 04 04:31:06 PM PDT 24 497926000 ps
T295 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.227713425 Aug 04 04:30:56 PM PDT 24 Aug 04 04:30:57 PM PDT 24 450172214 ps
T296 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.654865428 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:50 PM PDT 24 293231045 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1983870285 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:42 PM PDT 24 302265252 ps
T55 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2818407559 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:01 PM PDT 24 312305164 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4206541471 Aug 04 04:30:25 PM PDT 24 Aug 04 04:30:26 PM PDT 24 1332181834 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2636836158 Aug 04 04:30:44 PM PDT 24 Aug 04 04:30:45 PM PDT 24 412751032 ps
T298 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4164292529 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:42 PM PDT 24 457423282 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1923785654 Aug 04 04:30:36 PM PDT 24 Aug 04 04:30:37 PM PDT 24 575397328 ps
T299 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1880375643 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:02 PM PDT 24 342406550 ps
T300 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.240491737 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:40 PM PDT 24 1115360314 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2953575188 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:39 PM PDT 24 1229004984 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4032420912 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:35 PM PDT 24 347949350 ps
T26 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.495620088 Aug 04 04:30:47 PM PDT 24 Aug 04 04:30:54 PM PDT 24 7714724883 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1329402612 Aug 04 04:31:05 PM PDT 24 Aug 04 04:31:08 PM PDT 24 379204044 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3193117595 Aug 04 04:30:26 PM PDT 24 Aug 04 04:30:28 PM PDT 24 549337604 ps
T194 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2802551910 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:34 PM PDT 24 4064326896 ps
T80 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.703291920 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:50 PM PDT 24 313356207 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1902189076 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:33 PM PDT 24 323311574 ps
T305 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3094772898 Aug 04 04:30:48 PM PDT 24 Aug 04 04:30:50 PM PDT 24 694373950 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.123545182 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:31 PM PDT 24 457810982 ps
T307 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.88852555 Aug 04 04:30:43 PM PDT 24 Aug 04 04:30:44 PM PDT 24 450617463 ps
T308 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2223086046 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:45 PM PDT 24 550595861 ps
T193 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2101742077 Aug 04 04:31:15 PM PDT 24 Aug 04 04:31:22 PM PDT 24 4223460785 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1874072727 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:52 PM PDT 24 1319343304 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3985904747 Aug 04 04:30:43 PM PDT 24 Aug 04 04:30:44 PM PDT 24 609913899 ps
T81 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2314107378 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:39 PM PDT 24 406577564 ps
T310 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2565852922 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:48 PM PDT 24 4015739237 ps
T311 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3784894211 Aug 04 04:30:56 PM PDT 24 Aug 04 04:30:57 PM PDT 24 376459111 ps
T312 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3760703087 Aug 04 04:31:04 PM PDT 24 Aug 04 04:31:07 PM PDT 24 388732191 ps
T82 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4218291709 Aug 04 04:31:03 PM PDT 24 Aug 04 04:31:05 PM PDT 24 532094491 ps
T313 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1915830131 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:07 PM PDT 24 310710947 ps
T83 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1685365558 Aug 04 04:30:35 PM PDT 24 Aug 04 04:30:36 PM PDT 24 1334447267 ps
T314 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2205811399 Aug 04 04:30:55 PM PDT 24 Aug 04 04:30:57 PM PDT 24 404708340 ps
T315 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2885480276 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:21 PM PDT 24 598558125 ps
T62 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1545857923 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:50 PM PDT 24 308253859 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1218441511 Aug 04 04:30:43 PM PDT 24 Aug 04 04:30:44 PM PDT 24 463057259 ps
T317 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3918733031 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:44 PM PDT 24 2021587565 ps
T318 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2721811559 Aug 04 04:30:42 PM PDT 24 Aug 04 04:30:44 PM PDT 24 2196440520 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.200088996 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:39 PM PDT 24 524892769 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1636410340 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:53 PM PDT 24 1530300012 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3285746973 Aug 04 04:31:04 PM PDT 24 Aug 04 04:31:06 PM PDT 24 4875606058 ps
T322 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2028666655 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:51 PM PDT 24 613152937 ps
T323 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2748119672 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:03 PM PDT 24 478834264 ps
T324 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.984318334 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:39 PM PDT 24 428993330 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1761245233 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:49 PM PDT 24 12336705597 ps
T325 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2517307355 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:07 PM PDT 24 1942129400 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4120219033 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:41 PM PDT 24 1474987659 ps
T64 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1213729725 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:38 PM PDT 24 612502742 ps
T327 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2912093365 Aug 04 04:31:22 PM PDT 24 Aug 04 04:31:23 PM PDT 24 465777990 ps
T328 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1052514283 Aug 04 04:30:48 PM PDT 24 Aug 04 04:30:50 PM PDT 24 486702874 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3277319209 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:04 PM PDT 24 520514656 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3425277349 Aug 04 04:30:40 PM PDT 24 Aug 04 04:30:41 PM PDT 24 1327005734 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2241780735 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:41 PM PDT 24 1526023721 ps
T332 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.772442189 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:31 PM PDT 24 434795625 ps
T333 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4066422527 Aug 04 04:30:33 PM PDT 24 Aug 04 04:30:35 PM PDT 24 1558933610 ps
T65 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.256032442 Aug 04 04:31:03 PM PDT 24 Aug 04 04:31:04 PM PDT 24 399644997 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2788957538 Aug 04 04:30:57 PM PDT 24 Aug 04 04:30:58 PM PDT 24 367672844 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3037677198 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:32 PM PDT 24 412183682 ps
T336 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3407291886 Aug 04 04:31:03 PM PDT 24 Aug 04 04:31:04 PM PDT 24 406918843 ps
T337 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4206481533 Aug 04 04:31:19 PM PDT 24 Aug 04 04:31:20 PM PDT 24 418152027 ps
T338 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2934968341 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:45 PM PDT 24 461010903 ps
T339 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.773768489 Aug 04 04:30:52 PM PDT 24 Aug 04 04:31:02 PM PDT 24 8266916554 ps
T340 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2668651655 Aug 04 04:30:27 PM PDT 24 Aug 04 04:30:29 PM PDT 24 373469587 ps
T341 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3195300785 Aug 04 04:30:28 PM PDT 24 Aug 04 04:30:30 PM PDT 24 774936010 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3001625933 Aug 04 04:30:52 PM PDT 24 Aug 04 04:30:53 PM PDT 24 317669773 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1273200639 Aug 04 04:30:28 PM PDT 24 Aug 04 04:30:30 PM PDT 24 483902397 ps
T344 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1191750739 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:07 PM PDT 24 2339321422 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1601451147 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:02 PM PDT 24 328610313 ps
T346 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4060250383 Aug 04 04:31:09 PM PDT 24 Aug 04 04:31:10 PM PDT 24 471677610 ps
T347 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4065413287 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:04 PM PDT 24 4179510698 ps
T348 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3091707811 Aug 04 04:30:33 PM PDT 24 Aug 04 04:30:34 PM PDT 24 826904773 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.575715607 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:42 PM PDT 24 288064949 ps
T350 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3405839616 Aug 04 04:30:57 PM PDT 24 Aug 04 04:30:58 PM PDT 24 490332230 ps
T351 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3603265634 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:18 PM PDT 24 506263010 ps
T352 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1280107820 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:46 PM PDT 24 311957617 ps
T353 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3767974359 Aug 04 04:30:43 PM PDT 24 Aug 04 04:30:44 PM PDT 24 448946360 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.700885233 Aug 04 04:30:48 PM PDT 24 Aug 04 04:31:02 PM PDT 24 8280796851 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3515795750 Aug 04 04:30:54 PM PDT 24 Aug 04 04:30:56 PM PDT 24 2820677178 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3523889733 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:00 PM PDT 24 524485324 ps
T357 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3725452870 Aug 04 04:31:07 PM PDT 24 Aug 04 04:31:12 PM PDT 24 3331806053 ps
T358 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2123881709 Aug 04 04:30:47 PM PDT 24 Aug 04 04:30:48 PM PDT 24 366641007 ps
T359 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1075379953 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:48 PM PDT 24 4221588469 ps
T360 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3937113289 Aug 04 04:30:28 PM PDT 24 Aug 04 04:30:30 PM PDT 24 448369054 ps
T361 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2259833196 Aug 04 04:31:01 PM PDT 24 Aug 04 04:31:02 PM PDT 24 432905348 ps
T362 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3382529193 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:36 PM PDT 24 1144146341 ps
T363 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1811344530 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:46 PM PDT 24 428791222 ps
T364 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.910623061 Aug 04 04:30:33 PM PDT 24 Aug 04 04:30:34 PM PDT 24 498781877 ps
T365 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1930982860 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:42 PM PDT 24 471958318 ps
T366 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1679034303 Aug 04 04:30:40 PM PDT 24 Aug 04 04:30:41 PM PDT 24 421409359 ps
T367 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3157228799 Aug 04 04:30:55 PM PDT 24 Aug 04 04:31:02 PM PDT 24 457445472 ps
T368 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3204232988 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:07 PM PDT 24 342056091 ps
T369 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.960156191 Aug 04 04:31:11 PM PDT 24 Aug 04 04:31:12 PM PDT 24 320912153 ps
T195 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4285697002 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:43 PM PDT 24 8541928930 ps
T370 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1791560315 Aug 04 04:30:57 PM PDT 24 Aug 04 04:30:59 PM PDT 24 405200905 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.287303842 Aug 04 04:30:35 PM PDT 24 Aug 04 04:30:36 PM PDT 24 301512552 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1459205144 Aug 04 04:30:57 PM PDT 24 Aug 04 04:31:02 PM PDT 24 456163831 ps
T372 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1582677210 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:00 PM PDT 24 495221138 ps
T373 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4205706492 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:00 PM PDT 24 409961778 ps
T374 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1310383371 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:35 PM PDT 24 477205212 ps
T375 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1056337035 Aug 04 04:30:53 PM PDT 24 Aug 04 04:30:54 PM PDT 24 379370459 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2993970116 Aug 04 04:30:35 PM PDT 24 Aug 04 04:30:36 PM PDT 24 357774475 ps
T377 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2703944767 Aug 04 04:30:49 PM PDT 24 Aug 04 04:30:50 PM PDT 24 392728817 ps
T378 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.269982529 Aug 04 04:30:44 PM PDT 24 Aug 04 04:30:45 PM PDT 24 497378669 ps
T379 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2994390368 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:39 PM PDT 24 497967672 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2025853406 Aug 04 04:30:41 PM PDT 24 Aug 04 04:30:42 PM PDT 24 333847077 ps
T381 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.219639248 Aug 04 04:31:12 PM PDT 24 Aug 04 04:31:16 PM PDT 24 8607581928 ps
T382 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1356404369 Aug 04 04:30:51 PM PDT 24 Aug 04 04:30:53 PM PDT 24 484546161 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3153973507 Aug 04 04:31:20 PM PDT 24 Aug 04 04:31:22 PM PDT 24 518895491 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1073198641 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:34 PM PDT 24 724660019 ps
T385 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1958907237 Aug 04 04:30:55 PM PDT 24 Aug 04 04:30:59 PM PDT 24 8826934921 ps
T386 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.424505258 Aug 04 04:30:52 PM PDT 24 Aug 04 04:30:53 PM PDT 24 327045186 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2590064785 Aug 04 04:31:21 PM PDT 24 Aug 04 04:31:22 PM PDT 24 407303473 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1046721012 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:46 PM PDT 24 13493100744 ps
T196 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1524964174 Aug 04 04:31:18 PM PDT 24 Aug 04 04:31:23 PM PDT 24 4659217831 ps
T388 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1543349321 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:39 PM PDT 24 529684276 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3869322585 Aug 04 04:30:25 PM PDT 24 Aug 04 04:30:30 PM PDT 24 6812713742 ps
T389 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2909524015 Aug 04 04:31:16 PM PDT 24 Aug 04 04:31:17 PM PDT 24 505608380 ps
T390 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3450443470 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:41 PM PDT 24 2331056654 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3831196980 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:01 PM PDT 24 2675761665 ps
T392 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3240145099 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:09 PM PDT 24 499211279 ps
T393 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4076766616 Aug 04 04:31:00 PM PDT 24 Aug 04 04:31:03 PM PDT 24 2147081287 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2382355902 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:42 PM PDT 24 11137668472 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1766479411 Aug 04 04:30:36 PM PDT 24 Aug 04 04:30:37 PM PDT 24 554686578 ps
T395 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.861874953 Aug 04 04:30:59 PM PDT 24 Aug 04 04:31:00 PM PDT 24 478678971 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3173318491 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:03 PM PDT 24 328131238 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.542597670 Aug 04 04:30:53 PM PDT 24 Aug 04 04:30:55 PM PDT 24 557584010 ps
T398 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2586611060 Aug 04 04:31:08 PM PDT 24 Aug 04 04:31:10 PM PDT 24 494383639 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.989177496 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:39 PM PDT 24 637596321 ps
T400 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1641313022 Aug 04 04:31:06 PM PDT 24 Aug 04 04:31:07 PM PDT 24 340011221 ps
T401 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1214214670 Aug 04 04:30:47 PM PDT 24 Aug 04 04:30:48 PM PDT 24 325427097 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.653461432 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:44 PM PDT 24 4739329361 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1733377773 Aug 04 04:31:02 PM PDT 24 Aug 04 04:31:03 PM PDT 24 529209503 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.131159360 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:37 PM PDT 24 4318261336 ps
T404 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.313493036 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:38 PM PDT 24 1235776789 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2900699186 Aug 04 04:30:37 PM PDT 24 Aug 04 04:30:39 PM PDT 24 418147131 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3814121112 Aug 04 04:30:29 PM PDT 24 Aug 04 04:30:30 PM PDT 24 538473028 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1417471852 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:39 PM PDT 24 8484667528 ps
T408 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2149484545 Aug 04 04:30:54 PM PDT 24 Aug 04 04:30:55 PM PDT 24 373371778 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1126897050 Aug 04 04:30:52 PM PDT 24 Aug 04 04:30:53 PM PDT 24 396940723 ps
T410 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3525926842 Aug 04 04:30:44 PM PDT 24 Aug 04 04:30:45 PM PDT 24 513143740 ps
T411 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1110119382 Aug 04 04:30:44 PM PDT 24 Aug 04 04:30:46 PM PDT 24 304689901 ps
T412 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1057633268 Aug 04 04:31:04 PM PDT 24 Aug 04 04:31:05 PM PDT 24 470367449 ps
T413 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4270193963 Aug 04 04:30:39 PM PDT 24 Aug 04 04:30:40 PM PDT 24 463134733 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3590446177 Aug 04 04:30:29 PM PDT 24 Aug 04 04:30:30 PM PDT 24 347397725 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.852340031 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:38 PM PDT 24 2839970429 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.867385298 Aug 04 04:30:29 PM PDT 24 Aug 04 04:30:30 PM PDT 24 478522214 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3848875770 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:39 PM PDT 24 4539003658 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.767455967 Aug 04 04:30:32 PM PDT 24 Aug 04 04:30:33 PM PDT 24 487345650 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3353753358 Aug 04 04:30:38 PM PDT 24 Aug 04 04:30:39 PM PDT 24 430977816 ps
T420 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.500165908 Aug 04 04:30:45 PM PDT 24 Aug 04 04:30:53 PM PDT 24 635603991 ps
T421 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.966244286 Aug 04 04:30:43 PM PDT 24 Aug 04 04:30:45 PM PDT 24 799684092 ps
T422 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.254782892 Aug 04 04:30:34 PM PDT 24 Aug 04 04:30:38 PM PDT 24 7754233846 ps
T423 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.941946777 Aug 04 04:30:31 PM PDT 24 Aug 04 04:30:32 PM PDT 24 446705834 ps
T192 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1370977471 Aug 04 04:30:40 PM PDT 24 Aug 04 04:30:54 PM PDT 24 8658963435 ps

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2812958645
Short name T3
Test name
Test status
Simulation time 15038019154 ps
CPU time 119.22 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 206684 kb
Host smart-cd6b5878-34f1-4264-a2aa-d74e4f070fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812958645 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2812958645
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1341295310
Short name T2
Test name
Test status
Simulation time 259844773309 ps
CPU time 49.41 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:29:45 PM PDT 24
Peak memory 192924 kb
Host smart-7171c75f-6102-4a06-a787-3324a35f2593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341295310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1341295310
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1058781767
Short name T86
Test name
Test status
Simulation time 77016236154 ps
CPU time 548.01 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:37:55 PM PDT 24
Peak memory 206608 kb
Host smart-9fdb1121-c704-4ef1-b78f-ce9feca96978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058781767 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1058781767
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4165867271
Short name T23
Test name
Test status
Simulation time 8514819061 ps
CPU time 4.5 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 198140 kb
Host smart-c2b62b5f-4aac-4ffd-939b-9aeca3735f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165867271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4165867271
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2636836158
Short name T57
Test name
Test status
Simulation time 412751032 ps
CPU time 0.71 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 193052 kb
Host smart-e56eb911-c2d4-491b-923e-bf1ba0985b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636836158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2636836158
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3079109813
Short name T103
Test name
Test status
Simulation time 61579730887 ps
CPU time 97.08 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:30:21 PM PDT 24
Peak memory 193072 kb
Host smart-5f5fbdc6-c1d0-462b-8990-f11bf2b9b84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079109813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3079109813
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.545862675
Short name T140
Test name
Test status
Simulation time 38248414728 ps
CPU time 259.5 seconds
Started Aug 04 05:28:47 PM PDT 24
Finished Aug 04 05:33:06 PM PDT 24
Peak memory 198464 kb
Host smart-0cc6734a-a15c-478b-80af-7e75e1491734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545862675 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.545862675
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1341501717
Short name T146
Test name
Test status
Simulation time 5396655366 ps
CPU time 2.68 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 191864 kb
Host smart-c7a7ec68-a40f-46a2-b5cd-e84e7b5fd9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341501717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1341501717
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3575467708
Short name T102
Test name
Test status
Simulation time 190164755491 ps
CPU time 173.33 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:31:36 PM PDT 24
Peak memory 191768 kb
Host smart-b7086612-510e-4f1f-8eda-2af3994a13e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575467708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3575467708
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2291874274
Short name T18
Test name
Test status
Simulation time 3948675498 ps
CPU time 2.21 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 215384 kb
Host smart-826598c2-b6cf-4cac-abc1-1fae871c37ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291874274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2291874274
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.420786117
Short name T85
Test name
Test status
Simulation time 54468049988 ps
CPU time 547.79 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:37:56 PM PDT 24
Peak memory 202404 kb
Host smart-35153ea5-a46a-4885-a67a-a16e16a7756f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420786117 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.420786117
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2268668952
Short name T33
Test name
Test status
Simulation time 202765075721 ps
CPU time 619.52 seconds
Started Aug 04 05:28:51 PM PDT 24
Finished Aug 04 05:39:11 PM PDT 24
Peak memory 213628 kb
Host smart-4073e4d2-83e4-482a-9b0c-47db0d2a3cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268668952 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2268668952
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2876931454
Short name T124
Test name
Test status
Simulation time 623045498931 ps
CPU time 255.16 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:32:57 PM PDT 24
Peak memory 208712 kb
Host smart-cccf7b37-5a53-48dc-90fd-df47ac345602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876931454 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2876931454
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.184013031
Short name T133
Test name
Test status
Simulation time 37704603651 ps
CPU time 403.35 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 199876 kb
Host smart-ed2b10ef-60ed-440a-be0a-69ac6a1a2402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184013031 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.184013031
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1457784972
Short name T110
Test name
Test status
Simulation time 58526425346 ps
CPU time 505.44 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:37:02 PM PDT 24
Peak memory 202656 kb
Host smart-4baf876a-2e8f-46c6-8ee0-a7ee6846d2bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457784972 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1457784972
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1660356895
Short name T88
Test name
Test status
Simulation time 267089744176 ps
CPU time 194.11 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:32:02 PM PDT 24
Peak memory 200260 kb
Host smart-931a6521-71f2-4e48-a3bd-034c82ac1f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660356895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1660356895
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.9507263
Short name T118
Test name
Test status
Simulation time 208063322511 ps
CPU time 417.39 seconds
Started Aug 04 05:28:51 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 202880 kb
Host smart-c4467ff0-227d-4bda-82ac-7c3814baed58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9507263 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.9507263
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2113678666
Short name T126
Test name
Test status
Simulation time 28733408303 ps
CPU time 199.98 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:32:15 PM PDT 24
Peak memory 206640 kb
Host smart-dfe11c79-a327-47fa-aaf7-b22c06b2bcc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113678666 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2113678666
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3168098697
Short name T105
Test name
Test status
Simulation time 67619753223 ps
CPU time 6.47 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 191784 kb
Host smart-fe8cd1c4-c39b-4d98-990b-a6b83006d458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168098697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3168098697
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1654339301
Short name T40
Test name
Test status
Simulation time 69835880565 ps
CPU time 109 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 191892 kb
Host smart-71e2eee1-5c2a-43cc-a7ca-d75ea75a6ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654339301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1654339301
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.95665123
Short name T15
Test name
Test status
Simulation time 77834900087 ps
CPU time 629.66 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:39:07 PM PDT 24
Peak memory 204820 kb
Host smart-d06f759a-348b-47ed-819f-336670041559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95665123 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.95665123
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3341125018
Short name T125
Test name
Test status
Simulation time 209146486908 ps
CPU time 86.92 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:30:11 PM PDT 24
Peak memory 191912 kb
Host smart-7fb185c0-caa3-4dc0-b972-3c7f9da76d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341125018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3341125018
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1529960558
Short name T47
Test name
Test status
Simulation time 88160854603 ps
CPU time 121.01 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:30:56 PM PDT 24
Peak memory 198184 kb
Host smart-d767a841-f5bc-4a91-90bf-27aaf7925894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529960558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1529960558
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4185689554
Short name T134
Test name
Test status
Simulation time 286091537289 ps
CPU time 442.28 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 193160 kb
Host smart-a1e00857-fbab-4722-845a-cd3aebdcb8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185689554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4185689554
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3755476956
Short name T104
Test name
Test status
Simulation time 296529845031 ps
CPU time 303.48 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:33:40 PM PDT 24
Peak memory 206512 kb
Host smart-003ccea9-d3b6-4766-96b7-cd11e57e6dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755476956 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3755476956
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.277828905
Short name T123
Test name
Test status
Simulation time 199222294926 ps
CPU time 280.11 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:33:23 PM PDT 24
Peak memory 198160 kb
Host smart-603c5be2-98b4-4994-9803-afd03055f759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277828905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.277828905
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4277924370
Short name T128
Test name
Test status
Simulation time 140988955294 ps
CPU time 124.24 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:30:48 PM PDT 24
Peak memory 198096 kb
Host smart-3f5a4c13-9a51-4bab-ab18-90e9513ac121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277924370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4277924370
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2214596928
Short name T14
Test name
Test status
Simulation time 40795660259 ps
CPU time 335.83 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:34:13 PM PDT 24
Peak memory 198620 kb
Host smart-517636ea-051c-49f8-a100-01a42192aa5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214596928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2214596928
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.557231610
Short name T38
Test name
Test status
Simulation time 31078437404 ps
CPU time 13.17 seconds
Started Aug 04 05:28:49 PM PDT 24
Finished Aug 04 05:29:02 PM PDT 24
Peak memory 192156 kb
Host smart-56e0d135-2265-4881-89cd-fcbd94b2bbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557231610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.557231610
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2374043038
Short name T115
Test name
Test status
Simulation time 289716586112 ps
CPU time 77.85 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:30:06 PM PDT 24
Peak memory 191896 kb
Host smart-217ccc5b-720c-446c-b6b2-e52c833363ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374043038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2374043038
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2685690753
Short name T44
Test name
Test status
Simulation time 91664679768 ps
CPU time 148.46 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:31:07 PM PDT 24
Peak memory 198120 kb
Host smart-a572fc4f-9e2a-4ad4-ad07-7c3d9a43105b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685690753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2685690753
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2769293752
Short name T111
Test name
Test status
Simulation time 99463877715 ps
CPU time 37.58 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:29:15 PM PDT 24
Peak memory 184064 kb
Host smart-1d91f142-7ddc-46d4-a47e-f8f38cc6282e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769293752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2769293752
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.838362034
Short name T120
Test name
Test status
Simulation time 36612006400 ps
CPU time 69.84 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:29:43 PM PDT 24
Peak memory 198428 kb
Host smart-7b56616f-4811-4383-a462-3e17b927cece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838362034 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.838362034
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2496259663
Short name T156
Test name
Test status
Simulation time 60930787733 ps
CPU time 21.35 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 192924 kb
Host smart-7f1a09a5-fef6-4ec0-a108-2e96b3ac852f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496259663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2496259663
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.84034306
Short name T73
Test name
Test status
Simulation time 121773134591 ps
CPU time 178.9 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:31:35 PM PDT 24
Peak memory 208084 kb
Host smart-36eb99c4-6ee4-40f5-a110-592b6c069386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84034306 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.84034306
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1853616960
Short name T130
Test name
Test status
Simulation time 139793573245 ps
CPU time 187.73 seconds
Started Aug 04 05:29:00 PM PDT 24
Finished Aug 04 05:32:08 PM PDT 24
Peak memory 192956 kb
Host smart-d4e66f13-a72a-475d-8820-755442e155df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853616960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1853616960
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.901290984
Short name T99
Test name
Test status
Simulation time 64913291593 ps
CPU time 43.2 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:29:20 PM PDT 24
Peak memory 191840 kb
Host smart-4882d887-05ec-4888-bf4c-17c087da9d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901290984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.901290984
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3447214771
Short name T117
Test name
Test status
Simulation time 192056908717 ps
CPU time 775.37 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:41:34 PM PDT 24
Peak memory 207460 kb
Host smart-d93c4e87-9f01-4ee0-92fb-5a6e7156753b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447214771 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3447214771
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.54814953
Short name T97
Test name
Test status
Simulation time 140809673639 ps
CPU time 213.59 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:32:16 PM PDT 24
Peak memory 184072 kb
Host smart-fdb3b670-aed4-4932-a040-009577fbea59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54814953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_al
l.54814953
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3047013666
Short name T96
Test name
Test status
Simulation time 139699247709 ps
CPU time 56.07 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:29:44 PM PDT 24
Peak memory 198172 kb
Host smart-d268726f-c546-45f8-bc39-982e19deee69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047013666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3047013666
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.418772773
Short name T37
Test name
Test status
Simulation time 474385056742 ps
CPU time 629.51 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:39:07 PM PDT 24
Peak memory 192720 kb
Host smart-541f5832-01ab-4ef5-a82f-d914a96d34fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418772773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.418772773
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1118993158
Short name T107
Test name
Test status
Simulation time 95647264028 ps
CPU time 131.06 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:31:07 PM PDT 24
Peak memory 192900 kb
Host smart-2781e566-5a76-4621-9480-6e21908a284a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118993158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1118993158
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.587242324
Short name T155
Test name
Test status
Simulation time 153918914843 ps
CPU time 222.31 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:32:30 PM PDT 24
Peak memory 192996 kb
Host smart-0d00330c-859a-45ab-8528-bb24e8b0589c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587242324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.587242324
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3428093964
Short name T108
Test name
Test status
Simulation time 39875478591 ps
CPU time 56.65 seconds
Started Aug 04 05:28:54 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 191864 kb
Host smart-23b5ee4a-13ea-49f6-aceb-f6150a31747c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428093964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3428093964
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3059969280
Short name T89
Test name
Test status
Simulation time 16603172261 ps
CPU time 114.97 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:30:38 PM PDT 24
Peak memory 198500 kb
Host smart-9c8a2b72-e7e0-4194-8742-3a90660a2574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059969280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3059969280
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3942602798
Short name T32
Test name
Test status
Simulation time 103607027345 ps
CPU time 850.61 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:42:50 PM PDT 24
Peak memory 207748 kb
Host smart-804dd330-029a-460e-b231-b34d571439e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942602798 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3942602798
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1930845684
Short name T98
Test name
Test status
Simulation time 67304527427 ps
CPU time 23.18 seconds
Started Aug 04 05:28:47 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 198236 kb
Host smart-129e33c3-8877-4db9-b477-50691feb7ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930845684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1930845684
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.646699752
Short name T127
Test name
Test status
Simulation time 113652664249 ps
CPU time 182.5 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:31:40 PM PDT 24
Peak memory 191816 kb
Host smart-c6b1c83a-cdf2-4a42-b44f-d21b10b1103f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646699752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.646699752
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3925037382
Short name T75
Test name
Test status
Simulation time 317219472640 ps
CPU time 42.9 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 198248 kb
Host smart-434bfda4-e05e-4110-a2b1-47fbfcaaa588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925037382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3925037382
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3030730582
Short name T49
Test name
Test status
Simulation time 204802358874 ps
CPU time 64.47 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:29:47 PM PDT 24
Peak memory 193112 kb
Host smart-3d1e0aad-2bf2-4b0d-8f24-b7029ecbd995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030730582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3030730582
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4020219167
Short name T42
Test name
Test status
Simulation time 160714536646 ps
CPU time 402.94 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:35:16 PM PDT 24
Peak memory 203064 kb
Host smart-15ffecdc-abb6-48aa-9d42-162f24b7a834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020219167 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4020219167
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3218673055
Short name T70
Test name
Test status
Simulation time 168004065580 ps
CPU time 446.46 seconds
Started Aug 04 05:28:59 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 206588 kb
Host smart-f71ee8e5-7193-47f4-8d7f-a7b9e2ce98e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218673055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3218673055
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1147112476
Short name T164
Test name
Test status
Simulation time 85174264059 ps
CPU time 248.32 seconds
Started Aug 04 05:28:50 PM PDT 24
Finished Aug 04 05:32:59 PM PDT 24
Peak memory 200868 kb
Host smart-a79514b1-910e-4711-8d08-e4a02f0b9e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147112476 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1147112476
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3316631422
Short name T69
Test name
Test status
Simulation time 59571095715 ps
CPU time 251.02 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:32:58 PM PDT 24
Peak memory 206696 kb
Host smart-444b1464-c28f-4d93-b034-b05767c311fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316631422 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3316631422
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1677829100
Short name T119
Test name
Test status
Simulation time 583507911616 ps
CPU time 396.58 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:35:13 PM PDT 24
Peak memory 192948 kb
Host smart-4b6a4e4c-b13d-4f67-a108-334e257eab2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677829100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1677829100
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.632795111
Short name T132
Test name
Test status
Simulation time 209084218483 ps
CPU time 300.57 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:33:44 PM PDT 24
Peak memory 193004 kb
Host smart-ab574fab-79a7-4df8-8dab-37aa7c236340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632795111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.632795111
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2795842687
Short name T138
Test name
Test status
Simulation time 57280725412 ps
CPU time 432.93 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 214048 kb
Host smart-1d4e36a5-c275-400b-a164-d6abc2950f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795842687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2795842687
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2520469907
Short name T39
Test name
Test status
Simulation time 33313139738 ps
CPU time 12.03 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:29:01 PM PDT 24
Peak memory 192476 kb
Host smart-52928bc8-0c5d-4deb-87b4-feb8f42df7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520469907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2520469907
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1542306913
Short name T122
Test name
Test status
Simulation time 22036382992 ps
CPU time 141.78 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:31:14 PM PDT 24
Peak memory 198568 kb
Host smart-b068d20f-2cf1-4196-82c8-a1ec246e722d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542306913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1542306913
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.616769106
Short name T106
Test name
Test status
Simulation time 127593035572 ps
CPU time 93.35 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:30:19 PM PDT 24
Peak memory 191896 kb
Host smart-caf7006c-802b-45f3-831a-2842b8534c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616769106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.616769106
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3096890694
Short name T48
Test name
Test status
Simulation time 35032294246 ps
CPU time 238.44 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:32:36 PM PDT 24
Peak memory 198416 kb
Host smart-67efde77-f126-4bf6-8a06-3c08546503b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096890694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3096890694
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3906557682
Short name T100
Test name
Test status
Simulation time 47994841677 ps
CPU time 514.33 seconds
Started Aug 04 05:28:50 PM PDT 24
Finished Aug 04 05:37:24 PM PDT 24
Peak memory 201956 kb
Host smart-0cd87c6d-5435-417c-abab-a2d0fa0b2f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906557682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3906557682
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2372524152
Short name T147
Test name
Test status
Simulation time 149396958878 ps
CPU time 232.69 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:32:49 PM PDT 24
Peak memory 192832 kb
Host smart-de75a7c0-cf97-446b-b02d-82e78f521677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372524152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2372524152
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3815904841
Short name T113
Test name
Test status
Simulation time 83109953324 ps
CPU time 116.22 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 192840 kb
Host smart-c572b340-d2eb-43dc-8009-82fde63858e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815904841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3815904841
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3230363283
Short name T114
Test name
Test status
Simulation time 178887298916 ps
CPU time 118.76 seconds
Started Aug 04 05:29:02 PM PDT 24
Finished Aug 04 05:31:01 PM PDT 24
Peak memory 192604 kb
Host smart-1ba46664-7519-4291-af08-59e9f50b05a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230363283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3230363283
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3572988550
Short name T4
Test name
Test status
Simulation time 491601984964 ps
CPU time 194.41 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:31:53 PM PDT 24
Peak memory 192824 kb
Host smart-402f2be9-09dc-4b69-99ae-ea3fcbdc6a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572988550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3572988550
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2247416880
Short name T163
Test name
Test status
Simulation time 52846449111 ps
CPU time 185.51 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:31:39 PM PDT 24
Peak memory 198568 kb
Host smart-3a8511f3-bd75-434a-baff-31aacfbb01d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247416880 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2247416880
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3868069432
Short name T137
Test name
Test status
Simulation time 290961894750 ps
CPU time 111.92 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 192876 kb
Host smart-20631fb9-2e31-42e2-a208-7af1c077c0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868069432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3868069432
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.720871588
Short name T50
Test name
Test status
Simulation time 81256508720 ps
CPU time 165.85 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:31:31 PM PDT 24
Peak memory 214532 kb
Host smart-d44ab611-137f-48b9-8bc4-e5ce80c124fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720871588 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.720871588
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2238711912
Short name T91
Test name
Test status
Simulation time 64802073323 ps
CPU time 26.54 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 192644 kb
Host smart-033d82de-a77f-4b0c-acdc-c6a43fed7851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238711912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2238711912
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.750073262
Short name T159
Test name
Test status
Simulation time 87049857467 ps
CPU time 333.63 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:34:11 PM PDT 24
Peak memory 206680 kb
Host smart-b5194e45-a9ab-439f-860e-0a00d7c1099f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750073262 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.750073262
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1838073759
Short name T116
Test name
Test status
Simulation time 518475033 ps
CPU time 1.31 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 196496 kb
Host smart-c6f785c8-877e-4fa4-9104-6d98f2b8a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838073759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1838073759
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.311826571
Short name T151
Test name
Test status
Simulation time 470102094 ps
CPU time 0.7 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 196696 kb
Host smart-31b795e3-4b7c-4862-a368-cbc323bc11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311826571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.311826571
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.511069604
Short name T87
Test name
Test status
Simulation time 22626997392 ps
CPU time 82.96 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:30:07 PM PDT 24
Peak memory 198420 kb
Host smart-f5c30d36-317e-4cb5-9cf3-d52715a44e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511069604 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.511069604
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3456344646
Short name T7
Test name
Test status
Simulation time 404917892 ps
CPU time 0.76 seconds
Started Aug 04 05:28:47 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 196584 kb
Host smart-488bc316-6bc6-42e7-9110-15dcefa4f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456344646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3456344646
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1876923143
Short name T148
Test name
Test status
Simulation time 210128169502 ps
CPU time 71.9 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:30:00 PM PDT 24
Peak memory 198096 kb
Host smart-5bba4b5b-6951-4a8b-9255-07319e94d6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876923143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1876923143
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.395484431
Short name T149
Test name
Test status
Simulation time 565785257 ps
CPU time 1.5 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:36 PM PDT 24
Peak memory 196776 kb
Host smart-11b83a21-97f7-4cee-b65a-08d463285db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395484431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.395484431
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.534905647
Short name T36
Test name
Test status
Simulation time 589080438 ps
CPU time 0.81 seconds
Started Aug 04 05:28:51 PM PDT 24
Finished Aug 04 05:28:52 PM PDT 24
Peak memory 196552 kb
Host smart-a9b59cef-78d1-4078-ad02-fd7d1864f005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534905647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.534905647
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2437385464
Short name T141
Test name
Test status
Simulation time 379974804 ps
CPU time 0.74 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196716 kb
Host smart-990e8966-85bf-4329-ae93-2ec72c044510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437385464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2437385464
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3145058475
Short name T173
Test name
Test status
Simulation time 366378275974 ps
CPU time 28.2 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 192796 kb
Host smart-2604af31-f392-4d28-a06a-7ceaec5e849d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145058475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3145058475
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2560131765
Short name T13
Test name
Test status
Simulation time 159290859518 ps
CPU time 121.33 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:30:43 PM PDT 24
Peak memory 191964 kb
Host smart-1a00dcf5-774a-40e9-938c-aafcbccf3abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560131765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2560131765
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.787433783
Short name T150
Test name
Test status
Simulation time 391828011 ps
CPU time 0.95 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 196696 kb
Host smart-93d6bc0e-6199-46ee-b8a0-1c671fc6487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787433783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.787433783
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1813368111
Short name T153
Test name
Test status
Simulation time 532867444 ps
CPU time 1.23 seconds
Started Aug 04 05:28:49 PM PDT 24
Finished Aug 04 05:28:51 PM PDT 24
Peak memory 196656 kb
Host smart-e776d80d-4da9-4a91-9a05-8869cea0cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813368111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1813368111
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2026939120
Short name T158
Test name
Test status
Simulation time 268397020336 ps
CPU time 189.12 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:31:58 PM PDT 24
Peak memory 192908 kb
Host smart-c604d257-4719-4fd5-9679-c36567070c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026939120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2026939120
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1044756913
Short name T169
Test name
Test status
Simulation time 29695934932 ps
CPU time 316.11 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:34:05 PM PDT 24
Peak memory 206700 kb
Host smart-58c0087e-4ee0-4990-8d75-79d4e7825776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044756913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1044756913
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1063602569
Short name T131
Test name
Test status
Simulation time 366117601213 ps
CPU time 600.38 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:38:38 PM PDT 24
Peak memory 192928 kb
Host smart-1d05ab71-6b08-4ccb-be40-20ddd46f9155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063602569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1063602569
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3663754637
Short name T142
Test name
Test status
Simulation time 522699986 ps
CPU time 1.32 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 196536 kb
Host smart-b3d889bc-6e66-462e-bbb3-87076fcb732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663754637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3663754637
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1812958022
Short name T10
Test name
Test status
Simulation time 46728619572 ps
CPU time 522.75 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:37:18 PM PDT 24
Peak memory 201500 kb
Host smart-2fd555c0-79d3-4c7e-8655-7c8f70fd75f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812958022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1812958022
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3058044732
Short name T31
Test name
Test status
Simulation time 8875130319 ps
CPU time 46.36 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 206624 kb
Host smart-4092ff08-55d1-476e-8ebf-2cee023f5742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058044732 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3058044732
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.525707645
Short name T161
Test name
Test status
Simulation time 6440241535 ps
CPU time 57.52 seconds
Started Aug 04 05:29:06 PM PDT 24
Finished Aug 04 05:30:03 PM PDT 24
Peak memory 214660 kb
Host smart-12d10bfb-a8e7-4daa-83e2-48557dc90429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525707645 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.525707645
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4178838388
Short name T135
Test name
Test status
Simulation time 514766865 ps
CPU time 0.8 seconds
Started Aug 04 05:28:58 PM PDT 24
Finished Aug 04 05:28:59 PM PDT 24
Peak memory 196636 kb
Host smart-40418f71-431e-47df-a0e0-686d457638c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178838388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4178838388
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.19207794
Short name T170
Test name
Test status
Simulation time 120050113616 ps
CPU time 43.58 seconds
Started Aug 04 05:28:57 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 191876 kb
Host smart-f9937866-8537-4b9f-90e6-40b5d537ca9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19207794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_al
l.19207794
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2055629198
Short name T143
Test name
Test status
Simulation time 172943951182 ps
CPU time 114.09 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 192884 kb
Host smart-55415183-1c40-4a97-a0a5-b55d738c9da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055629198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2055629198
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.599875887
Short name T35
Test name
Test status
Simulation time 64342300239 ps
CPU time 261.79 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:32:59 PM PDT 24
Peak memory 214092 kb
Host smart-d3aa26b4-1aad-4df7-ba81-da74aeb8c37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599875887 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.599875887
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2789717895
Short name T139
Test name
Test status
Simulation time 384234242 ps
CPU time 0.7 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196680 kb
Host smart-40db328f-2b71-4440-b06a-dd050721b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789717895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2789717895
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2403506146
Short name T145
Test name
Test status
Simulation time 439269878 ps
CPU time 0.79 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:28:57 PM PDT 24
Peak memory 196936 kb
Host smart-3487b665-0702-4f02-bc45-f9244775c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403506146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2403506146
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1787071791
Short name T129
Test name
Test status
Simulation time 24289457075 ps
CPU time 203.9 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:32:03 PM PDT 24
Peak memory 206700 kb
Host smart-072670b4-d37b-4482-ac9a-4ffaf7f66af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787071791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1787071791
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3093460829
Short name T144
Test name
Test status
Simulation time 410116537 ps
CPU time 0.76 seconds
Started Aug 04 05:28:29 PM PDT 24
Finished Aug 04 05:28:30 PM PDT 24
Peak memory 196672 kb
Host smart-c2d55522-269e-4d7c-b13e-be841301f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093460829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3093460829
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3259583134
Short name T165
Test name
Test status
Simulation time 52237369920 ps
CPU time 142.15 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:31:04 PM PDT 24
Peak memory 198304 kb
Host smart-3600f9cb-b17d-4c6e-b45a-ff5ee950fb0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259583134 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3259583134
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3875799699
Short name T181
Test name
Test status
Simulation time 181914690647 ps
CPU time 65.53 seconds
Started Aug 04 05:28:54 PM PDT 24
Finished Aug 04 05:30:00 PM PDT 24
Peak memory 192844 kb
Host smart-2f47bef7-c89c-4506-8824-a6b7e87bf10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875799699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3875799699
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1301381915
Short name T41
Test name
Test status
Simulation time 466333758 ps
CPU time 1.26 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196716 kb
Host smart-314d161a-5ae0-44e0-8663-86e557f96508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301381915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1301381915
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1689037353
Short name T24
Test name
Test status
Simulation time 415988814 ps
CPU time 1.2 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 196608 kb
Host smart-33322baf-2f05-4c9d-918b-5f83cbfaa3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689037353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1689037353
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1565145539
Short name T166
Test name
Test status
Simulation time 99032851840 ps
CPU time 290.81 seconds
Started Aug 04 05:28:58 PM PDT 24
Finished Aug 04 05:33:49 PM PDT 24
Peak memory 213884 kb
Host smart-7dfe286c-3a10-409b-b233-a6609131c90a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565145539 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1565145539
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3455730127
Short name T157
Test name
Test status
Simulation time 560588317 ps
CPU time 0.81 seconds
Started Aug 04 05:28:40 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 196640 kb
Host smart-6b47d327-38de-4731-a1a7-4199482c2c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455730127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3455730127
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1378387421
Short name T188
Test name
Test status
Simulation time 367270704 ps
CPU time 1.14 seconds
Started Aug 04 05:28:32 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 196572 kb
Host smart-10f887b3-1320-4694-9599-2811e08bfeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378387421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1378387421
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.493199254
Short name T112
Test name
Test status
Simulation time 376582373 ps
CPU time 0.7 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196648 kb
Host smart-93b62daa-9b21-421c-974e-6f07339cc333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493199254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.493199254
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2430715416
Short name T152
Test name
Test status
Simulation time 518321507 ps
CPU time 0.75 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 196708 kb
Host smart-75761a2a-8e1e-4252-b4df-ba2259f8e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430715416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2430715416
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2682782093
Short name T109
Test name
Test status
Simulation time 592534717 ps
CPU time 0.83 seconds
Started Aug 04 05:28:57 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 196584 kb
Host smart-92a9c8cb-6c1a-4cb0-a941-d98f8630f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682782093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2682782093
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4202704985
Short name T16
Test name
Test status
Simulation time 221208910941 ps
CPU time 70.65 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:29:53 PM PDT 24
Peak memory 198084 kb
Host smart-6a8b5f4f-643d-42d9-aa45-3ad06d1e582d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202704985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4202704985
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.964684499
Short name T187
Test name
Test status
Simulation time 571601779 ps
CPU time 1.32 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196616 kb
Host smart-94ee198d-3905-4e86-97b8-ed3b045f9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964684499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.964684499
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.452951691
Short name T190
Test name
Test status
Simulation time 532670185 ps
CPU time 1.39 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 196724 kb
Host smart-2c605ba2-c71e-4844-b84e-41648a5a5402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452951691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.452951691
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3587538186
Short name T176
Test name
Test status
Simulation time 394632388 ps
CPU time 1.17 seconds
Started Aug 04 05:28:50 PM PDT 24
Finished Aug 04 05:28:56 PM PDT 24
Peak memory 196548 kb
Host smart-e00a95ee-3044-4c49-9065-11a71f593d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587538186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3587538186
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1484535313
Short name T8
Test name
Test status
Simulation time 398148305 ps
CPU time 1.11 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 196496 kb
Host smart-ada18371-623b-46b9-82a8-77274af992dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484535313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1484535313
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3894430420
Short name T52
Test name
Test status
Simulation time 50023230848 ps
CPU time 548.33 seconds
Started Aug 04 05:28:53 PM PDT 24
Finished Aug 04 05:38:01 PM PDT 24
Peak memory 202104 kb
Host smart-59b0a8e9-9904-44d4-b0f8-e64dc4e5757a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894430420 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3894430420
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2694248265
Short name T90
Test name
Test status
Simulation time 97307423941 ps
CPU time 333.11 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:34:14 PM PDT 24
Peak memory 206712 kb
Host smart-30e8ca16-4098-4bde-a9bd-52134bae5e82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694248265 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2694248265
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3360286471
Short name T174
Test name
Test status
Simulation time 549802187 ps
CPU time 0.73 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196496 kb
Host smart-9a0cadeb-5a07-4ed6-9894-471db8a948ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360286471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3360286471
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1474438182
Short name T34
Test name
Test status
Simulation time 24662325967 ps
CPU time 86.61 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:30:08 PM PDT 24
Peak memory 198540 kb
Host smart-f8789497-fd07-4b40-82c7-3990d27a8316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474438182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1474438182
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2388104980
Short name T182
Test name
Test status
Simulation time 478758455 ps
CPU time 0.74 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 196720 kb
Host smart-2842f7ff-1f07-4469-8800-404d0d39ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388104980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2388104980
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.915499559
Short name T45
Test name
Test status
Simulation time 386331490 ps
CPU time 1.2 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196620 kb
Host smart-2b2ebab1-ca54-4483-ab3e-c8cc00686b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915499559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.915499559
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3562365758
Short name T172
Test name
Test status
Simulation time 537403664 ps
CPU time 1.33 seconds
Started Aug 04 05:28:57 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 196676 kb
Host smart-c32a65f2-94c7-4f9b-9b6c-aabe7e47b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562365758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3562365758
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3192851396
Short name T154
Test name
Test status
Simulation time 263005027081 ps
CPU time 367.35 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:34:45 PM PDT 24
Peak memory 192632 kb
Host smart-0b0e5987-20c6-4d67-92a3-7abf9d65a796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192851396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3192851396
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2982754271
Short name T162
Test name
Test status
Simulation time 570877718 ps
CPU time 0.85 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196712 kb
Host smart-bea48abf-b21b-4df2-b3c8-58dc05f14882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982754271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2982754271
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3879350475
Short name T136
Test name
Test status
Simulation time 344013303 ps
CPU time 1.17 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 196736 kb
Host smart-3925e67a-1d11-4338-a2c4-88e8dcd0c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879350475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3879350475
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1487650371
Short name T72
Test name
Test status
Simulation time 422624988 ps
CPU time 1.14 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:32 PM PDT 24
Peak memory 196704 kb
Host smart-78b5457f-929c-4218-9b81-0c32485c235c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487650371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1487650371
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1368334888
Short name T168
Test name
Test status
Simulation time 393203355 ps
CPU time 0.73 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 196528 kb
Host smart-57fc7225-4245-4d12-aefd-f1bc05b4128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368334888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1368334888
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3372640859
Short name T101
Test name
Test status
Simulation time 585688102 ps
CPU time 1.41 seconds
Started Aug 04 05:29:01 PM PDT 24
Finished Aug 04 05:29:03 PM PDT 24
Peak memory 196632 kb
Host smart-e70df3ac-45ce-4ce8-9d9c-bc3f481ac7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372640859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3372640859
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2520948581
Short name T178
Test name
Test status
Simulation time 539321682 ps
CPU time 0.66 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 196520 kb
Host smart-358a800d-75b4-4843-bb64-333ff7ef0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520948581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2520948581
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3787326459
Short name T71
Test name
Test status
Simulation time 407215343 ps
CPU time 0.68 seconds
Started Aug 04 05:28:56 PM PDT 24
Finished Aug 04 05:28:57 PM PDT 24
Peak memory 196508 kb
Host smart-79bf91ae-d384-4830-860c-9de255c57aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787326459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3787326459
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1727907911
Short name T121
Test name
Test status
Simulation time 434006006 ps
CPU time 1.06 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196636 kb
Host smart-ce8227ae-e1a5-414a-a2bd-ce179c02349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727907911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1727907911
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4285697002
Short name T195
Test name
Test status
Simulation time 8541928930 ps
CPU time 3.63 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:43 PM PDT 24
Peak memory 198336 kb
Host smart-e3bc951b-3bfc-4a98-aa9e-b0ee1f6f1aef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285697002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4285697002
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3777574797
Short name T171
Test name
Test status
Simulation time 100097683144 ps
CPU time 151.43 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:31:12 PM PDT 24
Peak memory 191888 kb
Host smart-4c38c768-8e68-4844-8cee-521fa992b4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777574797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3777574797
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.28048407
Short name T167
Test name
Test status
Simulation time 489062806 ps
CPU time 0.71 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:28:53 PM PDT 24
Peak memory 196640 kb
Host smart-8957e3e7-9e2d-4e5e-a6a9-368be0ab75e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28048407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.28048407
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1541429663
Short name T180
Test name
Test status
Simulation time 558466452 ps
CPU time 1.16 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196592 kb
Host smart-335d2027-130b-4618-bd0f-7cb8f2d0f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541429663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1541429663
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3961634301
Short name T30
Test name
Test status
Simulation time 24843565123 ps
CPU time 91.41 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:30:14 PM PDT 24
Peak memory 206548 kb
Host smart-d1336e9b-2b2f-4171-b677-3ff1a52065c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961634301 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3961634301
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3906536924
Short name T191
Test name
Test status
Simulation time 620532422 ps
CPU time 0.84 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 196576 kb
Host smart-bd0de0ca-c0e3-4c85-aec5-1cc96be3236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906536924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3906536924
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1239593732
Short name T12
Test name
Test status
Simulation time 523740823 ps
CPU time 0.92 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 196588 kb
Host smart-08dc8500-1e11-4085-a527-f916e8e481cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239593732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1239593732
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.255940940
Short name T179
Test name
Test status
Simulation time 634867131 ps
CPU time 0.77 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 196500 kb
Host smart-f92f45f5-6677-4cdd-94ad-d0cad830a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255940940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.255940940
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4017677078
Short name T184
Test name
Test status
Simulation time 545320205 ps
CPU time 0.81 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:28:56 PM PDT 24
Peak memory 196584 kb
Host smart-865e349d-0962-486d-8eb6-9e02820b5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017677078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4017677078
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3789482042
Short name T186
Test name
Test status
Simulation time 440686428 ps
CPU time 0.96 seconds
Started Aug 04 05:29:02 PM PDT 24
Finished Aug 04 05:29:03 PM PDT 24
Peak memory 196500 kb
Host smart-f837573c-b81f-4eb6-85a8-5d55f0b8ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789482042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3789482042
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3410157882
Short name T175
Test name
Test status
Simulation time 575596949 ps
CPU time 1.41 seconds
Started Aug 04 05:29:08 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 196496 kb
Host smart-4c0c3062-4b7e-42b7-9712-c18f12d666f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410157882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3410157882
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1220241995
Short name T177
Test name
Test status
Simulation time 586046359 ps
CPU time 1.43 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 196504 kb
Host smart-92db32e3-8596-4621-adc5-e93164d72b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220241995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1220241995
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3985904747
Short name T309
Test name
Test status
Simulation time 609913899 ps
CPU time 0.74 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 193176 kb
Host smart-2169f3b4-c05d-4cc5-a008-6e57f00b55e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985904747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3985904747
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1046721012
Short name T67
Test name
Test status
Simulation time 13493100744 ps
CPU time 13.3 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 196388 kb
Host smart-c076dc63-4bfd-4e1e-aee0-3550b8623b66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046721012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1046721012
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4206541471
Short name T56
Test name
Test status
Simulation time 1332181834 ps
CPU time 1.06 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:26 PM PDT 24
Peak memory 193108 kb
Host smart-6a4227e9-f9af-4764-93d4-31b40432da54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206541471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4206541471
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3193117595
Short name T303
Test name
Test status
Simulation time 549337604 ps
CPU time 1.58 seconds
Started Aug 04 04:30:26 PM PDT 24
Finished Aug 04 04:30:28 PM PDT 24
Peak memory 195844 kb
Host smart-189e2fed-4e31-4611-ac92-04a64a81cd68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193117595 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3193117595
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.772442189
Short name T332
Test name
Test status
Simulation time 434795625 ps
CPU time 0.61 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 192880 kb
Host smart-eb5400ff-f32e-4d74-ae0f-86a3f0fa6156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772442189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.772442189
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3037677198
Short name T335
Test name
Test status
Simulation time 412183682 ps
CPU time 0.71 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 183668 kb
Host smart-fc2f3529-9e4e-4848-b4b2-f3aff3035387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037677198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3037677198
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3814121112
Short name T406
Test name
Test status
Simulation time 538473028 ps
CPU time 0.67 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 183560 kb
Host smart-acdc1161-8a53-4b24-91a0-fa2befdbe9a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814121112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3814121112
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4032420912
Short name T301
Test name
Test status
Simulation time 347949350 ps
CPU time 0.64 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 183564 kb
Host smart-d56d5857-bf95-4980-9f98-a74d2bba666a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032420912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4032420912
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2953575188
Short name T79
Test name
Test status
Simulation time 1229004984 ps
CPU time 1.98 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 192884 kb
Host smart-250e0ebb-f4b4-41eb-adb6-366d537a9916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953575188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2953575188
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1273200639
Short name T343
Test name
Test status
Simulation time 483902397 ps
CPU time 2.11 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 198564 kb
Host smart-e1628b12-5e99-4e6b-9cb9-0eccdd032fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273200639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1273200639
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1075379953
Short name T359
Test name
Test status
Simulation time 4221588469 ps
CPU time 6.69 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:48 PM PDT 24
Peak memory 197896 kb
Host smart-cdfdac9e-dd6c-40e0-aff0-27e9ab1ad599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075379953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1075379953
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1923785654
Short name T58
Test name
Test status
Simulation time 575397328 ps
CPU time 1.61 seconds
Started Aug 04 04:30:36 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 183784 kb
Host smart-03cffe22-2dd4-4c5f-bd60-30a84150daf7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923785654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1923785654
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1761245233
Short name T63
Test name
Test status
Simulation time 12336705597 ps
CPU time 16.56 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:49 PM PDT 24
Peak memory 192172 kb
Host smart-eccba877-6a42-49d7-99df-dd1d6bf6ee03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761245233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1761245233
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1073198641
Short name T384
Test name
Test status
Simulation time 724660019 ps
CPU time 1.78 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 183768 kb
Host smart-92c213d4-31de-4be5-8d74-af7ee2509781
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073198641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1073198641
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2900699186
Short name T405
Test name
Test status
Simulation time 418147131 ps
CPU time 1.2 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 196016 kb
Host smart-25b5199d-a4b8-4f9c-9031-a484ae2a41e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900699186 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2900699186
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.767455967
Short name T418
Test name
Test status
Simulation time 487345650 ps
CPU time 1.22 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 192904 kb
Host smart-26e1701a-3a76-43ec-8fb8-32644efcc1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767455967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.767455967
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4164292529
Short name T298
Test name
Test status
Simulation time 457423282 ps
CPU time 0.81 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 183672 kb
Host smart-10928d4e-9c35-4dab-9ff1-cccb615cfbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164292529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4164292529
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3590446177
Short name T414
Test name
Test status
Simulation time 347397725 ps
CPU time 1.01 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 183352 kb
Host smart-0f49bd95-8ae1-4166-b45f-a9f0979d811d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590446177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3590446177
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1983870285
Short name T297
Test name
Test status
Simulation time 302265252 ps
CPU time 0.93 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 183564 kb
Host smart-cd22e0fe-0fc7-4e6e-8984-7095f99ea4a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983870285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1983870285
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.852340031
Short name T415
Test name
Test status
Simulation time 2839970429 ps
CPU time 7.58 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 195372 kb
Host smart-755aba9a-6d6f-4036-a3fd-e0a412b5460c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852340031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.852340031
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3937113289
Short name T360
Test name
Test status
Simulation time 448369054 ps
CPU time 2.45 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 198640 kb
Host smart-9eb6c963-b346-4432-b7d4-eaff45a82f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937113289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3937113289
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2565852922
Short name T310
Test name
Test status
Simulation time 4015739237 ps
CPU time 3.57 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:48 PM PDT 24
Peak memory 196688 kb
Host smart-1c958a92-7360-468a-b3db-55782ca871ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565852922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2565852922
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3405839616
Short name T350
Test name
Test status
Simulation time 490332230 ps
CPU time 1.39 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:30:58 PM PDT 24
Peak memory 195632 kb
Host smart-a37aa121-b6f1-4d12-a55b-9e29439fcb2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405839616 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3405839616
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1213729725
Short name T64
Test name
Test status
Simulation time 612502742 ps
CPU time 0.63 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 193048 kb
Host smart-d7cfc177-9655-4de3-834a-0c1127ad02c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213729725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1213729725
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2742632592
Short name T294
Test name
Test status
Simulation time 497926000 ps
CPU time 0.86 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 183628 kb
Host smart-e6648803-c61f-4540-bf6d-0d87946e7942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742632592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2742632592
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1685365558
Short name T83
Test name
Test status
Simulation time 1334447267 ps
CPU time 1.23 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 183856 kb
Host smart-33757ff9-a5e5-4d59-9b12-b35bd5f682a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685365558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1685365558
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1791560315
Short name T370
Test name
Test status
Simulation time 405200905 ps
CPU time 1.8 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:30:59 PM PDT 24
Peak memory 198596 kb
Host smart-e1d3cb26-9402-4b8b-b244-c0aeab26a413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791560315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1791560315
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1417471852
Short name T407
Test name
Test status
Simulation time 8484667528 ps
CPU time 5.21 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 198364 kb
Host smart-2a326fd1-f0ee-4f46-b380-244b1325d67a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417471852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1417471852
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2912093365
Short name T327
Test name
Test status
Simulation time 465777990 ps
CPU time 0.97 seconds
Started Aug 04 04:31:22 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 196532 kb
Host smart-4de22b0a-9339-444d-b82e-af3704c1e4b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912093365 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2912093365
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.256032442
Short name T65
Test name
Test status
Simulation time 399644997 ps
CPU time 0.63 seconds
Started Aug 04 04:31:03 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 191912 kb
Host smart-4d760801-97ab-403b-b436-34f0377f7abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256032442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.256032442
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3204232988
Short name T368
Test name
Test status
Simulation time 342056091 ps
CPU time 1.08 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 183636 kb
Host smart-02003e20-120d-4735-9623-5d9623d8f5fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204232988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3204232988
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3831196980
Short name T391
Test name
Test status
Simulation time 2675761665 ps
CPU time 1.94 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:01 PM PDT 24
Peak memory 195088 kb
Host smart-44f3efca-4fde-4bf6-b48c-0cb1882ac675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831196980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3831196980
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3094772898
Short name T305
Test name
Test status
Simulation time 694373950 ps
CPU time 1.87 seconds
Started Aug 04 04:30:48 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 198472 kb
Host smart-752357bf-bdb2-459e-85bc-e11986b79f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094772898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3094772898
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.219639248
Short name T381
Test name
Test status
Simulation time 8607581928 ps
CPU time 4.33 seconds
Started Aug 04 04:31:12 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 198148 kb
Host smart-3648f182-7553-49d5-91a5-1fccd34c568f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219639248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.219639248
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3091707811
Short name T348
Test name
Test status
Simulation time 826904773 ps
CPU time 0.91 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 198316 kb
Host smart-8d702379-35c6-4385-99d1-8f84df4ffcd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091707811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3091707811
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3153973507
Short name T383
Test name
Test status
Simulation time 518895491 ps
CPU time 1.25 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 193352 kb
Host smart-131ee6fb-77df-4afb-a383-8990e3bfd579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153973507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3153973507
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.88852555
Short name T307
Test name
Test status
Simulation time 450617463 ps
CPU time 0.65 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 183672 kb
Host smart-3a42adbf-5b9b-4884-a6df-ea3dc5e3e432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88852555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.88852555
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1191750739
Short name T344
Test name
Test status
Simulation time 2339321422 ps
CPU time 5.65 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 194916 kb
Host smart-1623d803-3c78-4422-81b2-39078e7dac3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191750739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1191750739
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3525926842
Short name T410
Test name
Test status
Simulation time 513143740 ps
CPU time 1.63 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 198208 kb
Host smart-d9ad01a6-0c51-4f27-9892-c1d550309288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525926842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3525926842
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1447592365
Short name T25
Test name
Test status
Simulation time 8407105834 ps
CPU time 4.32 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 198000 kb
Host smart-13ffcaa1-b709-4cf2-8981-d74bfd84b784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447592365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1447592365
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1930982860
Short name T365
Test name
Test status
Simulation time 471958318 ps
CPU time 1.22 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 196848 kb
Host smart-4f7ce25c-00f1-4910-8b92-cbdd49e3b693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930982860 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1930982860
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2314107378
Short name T81
Test name
Test status
Simulation time 406577564 ps
CPU time 1.17 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 193028 kb
Host smart-f2ba976b-61d9-418d-acf2-e1ea62d65d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314107378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2314107378
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2590064785
Short name T387
Test name
Test status
Simulation time 407303473 ps
CPU time 0.99 seconds
Started Aug 04 04:31:21 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 192844 kb
Host smart-48f9120d-d25e-437e-aac3-a82b70eaf4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590064785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2590064785
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4076766616
Short name T393
Test name
Test status
Simulation time 2147081287 ps
CPU time 2.71 seconds
Started Aug 04 04:31:00 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 193880 kb
Host smart-4fc32639-05d6-4651-81d4-963c4bc52ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076766616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4076766616
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3603265634
Short name T351
Test name
Test status
Simulation time 506263010 ps
CPU time 1.44 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:18 PM PDT 24
Peak memory 198508 kb
Host smart-8a292885-43b4-48a0-ac9a-849d868c2f55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603265634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3603265634
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.495620088
Short name T26
Test name
Test status
Simulation time 7714724883 ps
CPU time 6.96 seconds
Started Aug 04 04:30:47 PM PDT 24
Finished Aug 04 04:30:54 PM PDT 24
Peak memory 198352 kb
Host smart-959fad09-aec6-466a-9d71-912ba7c54355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495620088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.495620088
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2934968341
Short name T338
Test name
Test status
Simulation time 461010903 ps
CPU time 1.24 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 195820 kb
Host smart-248f41e5-f402-4ad1-aa50-332c17a06d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934968341 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2934968341
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1545857923
Short name T62
Test name
Test status
Simulation time 308253859 ps
CPU time 1.02 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 193900 kb
Host smart-49a29f13-0738-47bc-ad8f-f49e8cd90c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545857923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1545857923
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2994390368
Short name T379
Test name
Test status
Simulation time 497967672 ps
CPU time 0.57 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 192848 kb
Host smart-5b080c97-1745-4feb-ad85-61c20d450cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994390368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2994390368
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1341949540
Short name T29
Test name
Test status
Simulation time 1962267788 ps
CPU time 3.11 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 191936 kb
Host smart-e57be29b-7a3b-45c5-8f01-4f22b7dfbc4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341949540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1341949540
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2223086046
Short name T308
Test name
Test status
Simulation time 550595861 ps
CPU time 1.71 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 198468 kb
Host smart-c74713ec-95c7-4d2c-907f-9b528e66f757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223086046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2223086046
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.773768489
Short name T339
Test name
Test status
Simulation time 8266916554 ps
CPU time 10.05 seconds
Started Aug 04 04:30:52 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 198244 kb
Host smart-c549c628-2877-4158-bf2a-7a2679eab200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773768489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.773768489
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1543349321
Short name T388
Test name
Test status
Simulation time 529684276 ps
CPU time 1.35 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 196272 kb
Host smart-ef77194b-89a1-482f-b99e-63a6414a330a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543349321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1543349321
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.575715607
Short name T349
Test name
Test status
Simulation time 288064949 ps
CPU time 0.77 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 192884 kb
Host smart-c7098ac7-d830-401b-b82b-d967f12155ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575715607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.575715607
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2025853406
Short name T380
Test name
Test status
Simulation time 333847077 ps
CPU time 0.8 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 193204 kb
Host smart-5f809a1c-d3ab-433a-ab4e-18e2f5dd60c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025853406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2025853406
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3425277349
Short name T330
Test name
Test status
Simulation time 1327005734 ps
CPU time 1.01 seconds
Started Aug 04 04:30:40 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 193520 kb
Host smart-091afae0-0c2a-4fcc-9e41-c1c95d8b85d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425277349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3425277349
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4270193963
Short name T413
Test name
Test status
Simulation time 463134733 ps
CPU time 1.54 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:40 PM PDT 24
Peak memory 197228 kb
Host smart-dc23c9df-b395-4998-9c04-5c745d75b314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270193963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4270193963
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3075960614
Short name T21
Test name
Test status
Simulation time 420333024 ps
CPU time 0.75 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:16 PM PDT 24
Peak memory 195748 kb
Host smart-1be10625-994d-4abd-9efe-28f4f8df558c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075960614 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3075960614
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4259390990
Short name T54
Test name
Test status
Simulation time 475070976 ps
CPU time 0.82 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 192900 kb
Host smart-6da872d7-6fba-4b38-b65d-c18ec2b6c3a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259390990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4259390990
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3173318491
Short name T396
Test name
Test status
Simulation time 328131238 ps
CPU time 0.94 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 183668 kb
Host smart-d4e30428-dc99-4945-9d90-32b269946304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173318491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3173318491
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3450443470
Short name T390
Test name
Test status
Simulation time 2331056654 ps
CPU time 3.49 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 183904 kb
Host smart-d7c4f591-f9f7-43ca-b59b-be617d6dbc4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450443470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3450443470
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.500165908
Short name T420
Test name
Test status
Simulation time 635603991 ps
CPU time 2.5 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 198484 kb
Host smart-2b911abf-a149-43e8-80d5-0c2e5b51b6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500165908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.500165908
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4065413287
Short name T347
Test name
Test status
Simulation time 4179510698 ps
CPU time 3.66 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 198056 kb
Host smart-08edcf98-c675-4af6-82b1-c10eafe2ac27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065413287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4065413287
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1110119382
Short name T411
Test name
Test status
Simulation time 304689901 ps
CPU time 0.98 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 195864 kb
Host smart-915ff2dc-6e75-4766-9b21-a437b14b38e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110119382 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1110119382
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2818407559
Short name T55
Test name
Test status
Simulation time 312305164 ps
CPU time 0.66 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:01 PM PDT 24
Peak memory 192868 kb
Host smart-36288b95-a03b-474a-bad7-f1686c78ff36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818407559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2818407559
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3001625933
Short name T342
Test name
Test status
Simulation time 317669773 ps
CPU time 0.77 seconds
Started Aug 04 04:30:52 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 183984 kb
Host smart-50011bd2-517a-48f3-9c4c-bb6137de65ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001625933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3001625933
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2241780735
Short name T331
Test name
Test status
Simulation time 1526023721 ps
CPU time 1.03 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 193344 kb
Host smart-3017a04e-3e62-404b-8e47-5d4c7a93577c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241780735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2241780735
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1329402612
Short name T302
Test name
Test status
Simulation time 379204044 ps
CPU time 2.98 seconds
Started Aug 04 04:31:05 PM PDT 24
Finished Aug 04 04:31:08 PM PDT 24
Peak memory 198528 kb
Host smart-a982c6a9-a625-417f-8a25-c29da26d6921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329402612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1329402612
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1524964174
Short name T196
Test name
Test status
Simulation time 4659217831 ps
CPU time 4.81 seconds
Started Aug 04 04:31:18 PM PDT 24
Finished Aug 04 04:31:23 PM PDT 24
Peak memory 198132 kb
Host smart-3e1e5511-cb1b-4a34-a856-f783afdb7b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524964174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1524964174
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3593888236
Short name T22
Test name
Test status
Simulation time 533251987 ps
CPU time 1.42 seconds
Started Aug 04 04:30:40 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 195388 kb
Host smart-7aa7e057-33df-405b-8594-7aff4a67e005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593888236 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3593888236
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.269982529
Short name T378
Test name
Test status
Simulation time 497378669 ps
CPU time 1.13 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 183624 kb
Host smart-d7731a85-2bac-4df5-98dd-9e02312da0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269982529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.269982529
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3725452870
Short name T357
Test name
Test status
Simulation time 3331806053 ps
CPU time 4.79 seconds
Started Aug 04 04:31:07 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 194284 kb
Host smart-80848694-cadf-4e07-b631-05dc8a8d96d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725452870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3725452870
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.542597670
Short name T397
Test name
Test status
Simulation time 557584010 ps
CPU time 2.06 seconds
Started Aug 04 04:30:53 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 198348 kb
Host smart-cafcdb6e-ff9c-4638-9376-9cad54cc013c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542597670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.542597670
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1370977471
Short name T192
Test name
Test status
Simulation time 8658963435 ps
CPU time 14.28 seconds
Started Aug 04 04:30:40 PM PDT 24
Finished Aug 04 04:30:54 PM PDT 24
Peak memory 198280 kb
Host smart-63cdfebb-f585-4655-a990-ae8ba268a196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370977471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1370977471
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2719973355
Short name T289
Test name
Test status
Simulation time 436352785 ps
CPU time 1.14 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 198216 kb
Host smart-244d48e7-e19e-4718-aece-267db6e6e8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719973355 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2719973355
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.703291920
Short name T80
Test name
Test status
Simulation time 313356207 ps
CPU time 0.92 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 191964 kb
Host smart-0bfdadab-9c27-4083-932c-e50d21cbe946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703291920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.703291920
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1733377773
Short name T402
Test name
Test status
Simulation time 529209503 ps
CPU time 0.74 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 183656 kb
Host smart-1f94f527-d261-4eb7-86b8-a25268ccc5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733377773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1733377773
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3382529193
Short name T362
Test name
Test status
Simulation time 1144146341 ps
CPU time 1.3 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 193740 kb
Host smart-b51317a0-818b-433a-8662-89c6b06c39d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382529193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3382529193
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3760703087
Short name T312
Test name
Test status
Simulation time 388732191 ps
CPU time 2.16 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 198504 kb
Host smart-4ce08863-79e5-4546-b802-c50b9fc79093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760703087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3760703087
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1958907237
Short name T385
Test name
Test status
Simulation time 8826934921 ps
CPU time 3.15 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:59 PM PDT 24
Peak memory 198508 kb
Host smart-8598eda6-094e-4351-b221-78373d70f4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958907237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1958907237
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.989177496
Short name T399
Test name
Test status
Simulation time 637596321 ps
CPU time 1.01 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 183552 kb
Host smart-ceb4e878-9266-484b-9698-4a0c15a83894
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989177496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.989177496
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.653461432
Short name T61
Test name
Test status
Simulation time 4739329361 ps
CPU time 6.72 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 192168 kb
Host smart-392efb30-ebc9-43cc-9514-6c9b9834102a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653461432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.653461432
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2419255903
Short name T287
Test name
Test status
Simulation time 768839275 ps
CPU time 0.86 seconds
Started Aug 04 04:30:54 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 183660 kb
Host smart-21ae5a02-58b7-4c4d-aecb-7fb0a29ce4c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419255903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2419255903
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2885480276
Short name T315
Test name
Test status
Simulation time 598558125 ps
CPU time 0.79 seconds
Started Aug 04 04:31:20 PM PDT 24
Finished Aug 04 04:31:21 PM PDT 24
Peak memory 195912 kb
Host smart-298c0261-200c-4cd6-a93b-037823a1a77d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885480276 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2885480276
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.910623061
Short name T364
Test name
Test status
Simulation time 498781877 ps
CPU time 1.35 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 193104 kb
Host smart-245c08e1-726b-477a-8b60-2d9730b00109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910623061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.910623061
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1218441511
Short name T316
Test name
Test status
Simulation time 463057259 ps
CPU time 1.18 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 192892 kb
Host smart-f62ad161-5c6c-4e25-a0b9-3d3c2d5df8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218441511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1218441511
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.123545182
Short name T306
Test name
Test status
Simulation time 457810982 ps
CPU time 0.8 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 183584 kb
Host smart-02ac4ef4-70f2-4159-b725-699f19adc6d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123545182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.123545182
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.984318334
Short name T324
Test name
Test status
Simulation time 428993330 ps
CPU time 1.18 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 183656 kb
Host smart-a724031e-ffb8-4daa-a09a-390967791700
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984318334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.984318334
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1636410340
Short name T320
Test name
Test status
Simulation time 1530300012 ps
CPU time 4.18 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 193352 kb
Host smart-fd14800a-1376-4001-afc8-c156b619956a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636410340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1636410340
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1601451147
Short name T345
Test name
Test status
Simulation time 328610313 ps
CPU time 1.7 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 198544 kb
Host smart-96d9e8e6-cb71-4fbb-8324-e424f19a7f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601451147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1601451147
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3848875770
Short name T417
Test name
Test status
Simulation time 4539003658 ps
CPU time 7.33 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 196648 kb
Host smart-08bab323-d02c-43b9-ad60-c3b2fa96b5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848875770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3848875770
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1641313022
Short name T400
Test name
Test status
Simulation time 340011221 ps
CPU time 0.83 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 193204 kb
Host smart-b103f3ac-cb1e-4df9-98fe-44c7032fb246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641313022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1641313022
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.960156191
Short name T369
Test name
Test status
Simulation time 320912153 ps
CPU time 0.82 seconds
Started Aug 04 04:31:11 PM PDT 24
Finished Aug 04 04:31:12 PM PDT 24
Peak memory 192892 kb
Host smart-86f4256b-297a-4f95-a096-ccbdaa05f7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960156191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.960156191
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2123881709
Short name T358
Test name
Test status
Simulation time 366641007 ps
CPU time 1.03 seconds
Started Aug 04 04:30:47 PM PDT 24
Finished Aug 04 04:30:48 PM PDT 24
Peak memory 183700 kb
Host smart-c051f723-eb4e-4e45-b298-3932e765f291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123881709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2123881709
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2748119672
Short name T323
Test name
Test status
Simulation time 478834264 ps
CPU time 1.25 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:03 PM PDT 24
Peak memory 183660 kb
Host smart-e51d87b0-c84a-435e-b24d-20c1f171f4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748119672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2748119672
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3407291886
Short name T336
Test name
Test status
Simulation time 406918843 ps
CPU time 0.71 seconds
Started Aug 04 04:31:03 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 183664 kb
Host smart-3d3478ac-9a17-42af-a55f-6a3ad993339d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407291886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3407291886
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2205811399
Short name T314
Test name
Test status
Simulation time 404708340 ps
CPU time 1.12 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:30:57 PM PDT 24
Peak memory 183668 kb
Host smart-ac89025d-e145-4c49-8314-73f8933e6f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205811399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2205811399
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4060250383
Short name T346
Test name
Test status
Simulation time 471677610 ps
CPU time 1.19 seconds
Started Aug 04 04:31:09 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 183656 kb
Host smart-fd5d5f2c-814f-478e-8bd0-d1b5c44f3393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060250383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4060250383
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1280107820
Short name T352
Test name
Test status
Simulation time 311957617 ps
CPU time 0.96 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 192900 kb
Host smart-fa4014db-8d32-4ab0-9234-a24ab21322ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280107820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1280107820
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1582677210
Short name T372
Test name
Test status
Simulation time 495221138 ps
CPU time 0.91 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:00 PM PDT 24
Peak memory 183676 kb
Host smart-e360e225-14fd-4b5a-acc9-26e87fb2fa94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582677210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1582677210
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1679034303
Short name T366
Test name
Test status
Simulation time 421409359 ps
CPU time 0.63 seconds
Started Aug 04 04:30:40 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 183644 kb
Host smart-f1b203cc-88bf-4020-ba83-ade6a8c9fd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679034303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1679034303
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1459205144
Short name T66
Test name
Test status
Simulation time 456163831 ps
CPU time 0.75 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 183588 kb
Host smart-070d4204-a258-487c-b059-e0c837072ae2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459205144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1459205144
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3869322585
Short name T68
Test name
Test status
Simulation time 6812713742 ps
CPU time 5.63 seconds
Started Aug 04 04:30:25 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 192156 kb
Host smart-530af63c-8e1c-4106-82c1-6c44c340bc23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869322585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3869322585
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1874072727
Short name T59
Test name
Test status
Simulation time 1319343304 ps
CPU time 1.06 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:52 PM PDT 24
Peak memory 193064 kb
Host smart-24539fab-b0e0-41ee-b78d-a699b668d04c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874072727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1874072727
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.287303842
Short name T371
Test name
Test status
Simulation time 301512552 ps
CPU time 0.81 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 195628 kb
Host smart-d9c86916-04c2-41aa-8529-aaf78cd01273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287303842 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.287303842
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2788957538
Short name T334
Test name
Test status
Simulation time 367672844 ps
CPU time 0.7 seconds
Started Aug 04 04:30:57 PM PDT 24
Finished Aug 04 04:30:58 PM PDT 24
Peak memory 191984 kb
Host smart-14535b5e-4f3b-4def-a9f0-b14a24a53634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788957538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2788957538
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1034163206
Short name T290
Test name
Test status
Simulation time 539821588 ps
CPU time 0.77 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:31 PM PDT 24
Peak memory 192664 kb
Host smart-5c1cb06d-52ac-4cac-ad0e-3dba814eef91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034163206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1034163206
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3195811954
Short name T291
Test name
Test status
Simulation time 442663517 ps
CPU time 0.89 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 183544 kb
Host smart-b01754e1-0bca-4603-93a0-d46ea4302d67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195811954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3195811954
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.491831670
Short name T288
Test name
Test status
Simulation time 486893285 ps
CPU time 0.62 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 183536 kb
Host smart-a7c29226-7959-4b3e-8527-40dcae37f0f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491831670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.491831670
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2510327082
Short name T78
Test name
Test status
Simulation time 1062825174 ps
CPU time 1.54 seconds
Started Aug 04 04:31:03 PM PDT 24
Finished Aug 04 04:31:05 PM PDT 24
Peak memory 183668 kb
Host smart-ab7dce5f-4de5-4a8c-bf71-1bc8e7d5f3d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510327082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2510327082
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2668651655
Short name T340
Test name
Test status
Simulation time 373469587 ps
CPU time 2.42 seconds
Started Aug 04 04:30:27 PM PDT 24
Finished Aug 04 04:30:29 PM PDT 24
Peak memory 198508 kb
Host smart-05f5232b-adbd-4430-845d-173be012a2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668651655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2668651655
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.424505258
Short name T386
Test name
Test status
Simulation time 327045186 ps
CPU time 0.79 seconds
Started Aug 04 04:30:52 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 183668 kb
Host smart-c3a524d0-670c-4ccc-813a-bf1be0af386c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424505258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.424505258
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1880375643
Short name T299
Test name
Test status
Simulation time 342406550 ps
CPU time 0.65 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 183656 kb
Host smart-d62e3ac4-cc20-436f-9eb1-6106590565e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880375643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1880375643
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1214214670
Short name T401
Test name
Test status
Simulation time 325427097 ps
CPU time 1.01 seconds
Started Aug 04 04:30:47 PM PDT 24
Finished Aug 04 04:30:48 PM PDT 24
Peak memory 183660 kb
Host smart-eea64a14-8527-474b-9ddf-e0171a6927c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214214670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1214214670
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3240145099
Short name T392
Test name
Test status
Simulation time 499211279 ps
CPU time 0.85 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:09 PM PDT 24
Peak memory 183700 kb
Host smart-45e7b2f9-cd70-408f-b8c9-82831f52d21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240145099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3240145099
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1915830131
Short name T313
Test name
Test status
Simulation time 310710947 ps
CPU time 0.66 seconds
Started Aug 04 04:31:06 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 192804 kb
Host smart-790304e8-e9f7-484b-97cd-981263e7c0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915830131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1915830131
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3157228799
Short name T367
Test name
Test status
Simulation time 457445472 ps
CPU time 1.17 seconds
Started Aug 04 04:30:55 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 192864 kb
Host smart-d0ce19a1-c7d1-43db-b0d7-33f856822bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157228799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3157228799
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2909524015
Short name T389
Test name
Test status
Simulation time 505608380 ps
CPU time 0.71 seconds
Started Aug 04 04:31:16 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 183704 kb
Host smart-9a71aacf-4942-42c7-86ac-5d18a6166814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909524015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2909524015
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4205706492
Short name T373
Test name
Test status
Simulation time 409961778 ps
CPU time 0.7 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:00 PM PDT 24
Peak memory 192888 kb
Host smart-4bd87cbe-eadf-4a5f-9321-0d2a6eb1f2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205706492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4205706492
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.861874953
Short name T395
Test name
Test status
Simulation time 478678971 ps
CPU time 0.68 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:00 PM PDT 24
Peak memory 183588 kb
Host smart-0b7b4725-c632-4a38-acc6-dd5c42a7ed07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861874953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.861874953
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3259616822
Short name T286
Test name
Test status
Simulation time 628927450 ps
CPU time 0.6 seconds
Started Aug 04 04:30:58 PM PDT 24
Finished Aug 04 04:30:59 PM PDT 24
Peak memory 183688 kb
Host smart-2ece4f3a-8f1a-44e9-b39f-8dac1ecd087d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259616822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3259616822
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.200088996
Short name T319
Test name
Test status
Simulation time 524892769 ps
CPU time 1.01 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 183684 kb
Host smart-7a9be454-5370-47ad-b47c-9294903c89cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200088996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.200088996
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2382355902
Short name T60
Test name
Test status
Simulation time 11137668472 ps
CPU time 3.68 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:42 PM PDT 24
Peak memory 196376 kb
Host smart-44a72c2a-ba3e-4c11-80b9-9b9598b4cf47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382355902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2382355902
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.313493036
Short name T404
Test name
Test status
Simulation time 1235776789 ps
CPU time 0.67 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 183552 kb
Host smart-bb6ae54b-ba11-456c-9378-310b6e3e24ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313493036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.313493036
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.667113775
Short name T293
Test name
Test status
Simulation time 414943036 ps
CPU time 0.97 seconds
Started Aug 04 04:30:36 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 196968 kb
Host smart-1c05d0d2-56fe-466f-b4d5-3754b114b483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667113775 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.667113775
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3353753358
Short name T419
Test name
Test status
Simulation time 430977816 ps
CPU time 0.85 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 193316 kb
Host smart-f63b116e-37c0-4138-9c88-1dc3aaeb0336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353753358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3353753358
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.941946777
Short name T423
Test name
Test status
Simulation time 446705834 ps
CPU time 1.14 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:32 PM PDT 24
Peak memory 192832 kb
Host smart-3639cbd8-faf8-4e1e-ab48-d97025c3eb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941946777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.941946777
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.867385298
Short name T416
Test name
Test status
Simulation time 478522214 ps
CPU time 0.89 seconds
Started Aug 04 04:30:29 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 183588 kb
Host smart-adfc5ef4-346f-4565-9cea-8777b6715c3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867385298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.867385298
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2993970116
Short name T376
Test name
Test status
Simulation time 357774475 ps
CPU time 0.77 seconds
Started Aug 04 04:30:35 PM PDT 24
Finished Aug 04 04:30:36 PM PDT 24
Peak memory 183556 kb
Host smart-4867041d-3e9d-40a8-8e6f-566efca63573
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993970116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2993970116
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4066422527
Short name T333
Test name
Test status
Simulation time 1558933610 ps
CPU time 1.48 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 192824 kb
Host smart-474b81de-53e4-4c41-a390-bfb6f33d3804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066422527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4066422527
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3277319209
Short name T329
Test name
Test status
Simulation time 520514656 ps
CPU time 1.98 seconds
Started Aug 04 04:31:02 PM PDT 24
Finished Aug 04 04:31:04 PM PDT 24
Peak memory 198420 kb
Host smart-43378eaa-a2bd-460f-ada3-bd8ba4ef41c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277319209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3277319209
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.131159360
Short name T403
Test name
Test status
Simulation time 4318261336 ps
CPU time 2.37 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 197632 kb
Host smart-a5a6bb34-46ea-42f2-a0db-d5647a1abbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131159360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.131159360
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2259833196
Short name T361
Test name
Test status
Simulation time 432905348 ps
CPU time 0.71 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 192852 kb
Host smart-fb1755a6-f326-40e8-9334-1438bfe7803b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259833196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2259833196
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.654865428
Short name T296
Test name
Test status
Simulation time 293231045 ps
CPU time 0.6 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 183680 kb
Host smart-42675c7f-b516-4846-9246-689d2395ead6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654865428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.654865428
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4206481533
Short name T337
Test name
Test status
Simulation time 418152027 ps
CPU time 0.73 seconds
Started Aug 04 04:31:19 PM PDT 24
Finished Aug 04 04:31:20 PM PDT 24
Peak memory 192892 kb
Host smart-024b34a9-6928-4c36-87d1-edcefabf0239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206481533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4206481533
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1811344530
Short name T363
Test name
Test status
Simulation time 428791222 ps
CPU time 0.56 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 183696 kb
Host smart-7e15aa57-867f-4d3d-93ff-c2c8f35d816a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811344530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1811344530
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1057633268
Short name T412
Test name
Test status
Simulation time 470367449 ps
CPU time 0.57 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:05 PM PDT 24
Peak memory 183676 kb
Host smart-141f79f8-ed6c-454d-9d27-15eedddfc122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057633268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1057633268
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2703944767
Short name T377
Test name
Test status
Simulation time 392728817 ps
CPU time 1.07 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 183628 kb
Host smart-4592211c-7ff4-4623-9134-13c605d8fc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703944767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2703944767
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.227713425
Short name T295
Test name
Test status
Simulation time 450172214 ps
CPU time 0.9 seconds
Started Aug 04 04:30:56 PM PDT 24
Finished Aug 04 04:30:57 PM PDT 24
Peak memory 192908 kb
Host smart-c3e0a0eb-8cef-407d-a89c-4831f138c1d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227713425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.227713425
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3784894211
Short name T311
Test name
Test status
Simulation time 376459111 ps
CPU time 0.73 seconds
Started Aug 04 04:30:56 PM PDT 24
Finished Aug 04 04:30:57 PM PDT 24
Peak memory 192916 kb
Host smart-f43b214a-f795-46d7-9dae-170345c38ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784894211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3784894211
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2586611060
Short name T398
Test name
Test status
Simulation time 494383639 ps
CPU time 1.2 seconds
Started Aug 04 04:31:08 PM PDT 24
Finished Aug 04 04:31:10 PM PDT 24
Peak memory 183588 kb
Host smart-f85e520b-b10f-40d5-8b20-ade4a54fb6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586611060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2586611060
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1052514283
Short name T328
Test name
Test status
Simulation time 486702874 ps
CPU time 1.2 seconds
Started Aug 04 04:30:48 PM PDT 24
Finished Aug 04 04:30:50 PM PDT 24
Peak memory 192876 kb
Host smart-e848d1b6-e2fc-4a49-bbe3-4df8c2db1645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052514283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1052514283
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2525518395
Short name T202
Test name
Test status
Simulation time 503349565 ps
CPU time 1.2 seconds
Started Aug 04 04:30:33 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 195888 kb
Host smart-6175c28f-2b06-4ef9-9faa-6000adc34ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525518395 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2525518395
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.458792029
Short name T53
Test name
Test status
Simulation time 536093197 ps
CPU time 1.33 seconds
Started Aug 04 04:30:44 PM PDT 24
Finished Aug 04 04:30:46 PM PDT 24
Peak memory 191964 kb
Host smart-be328632-6035-4bc3-9819-cb7697fac4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458792029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.458792029
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1126897050
Short name T409
Test name
Test status
Simulation time 396940723 ps
CPU time 0.66 seconds
Started Aug 04 04:30:52 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 183680 kb
Host smart-c661f7fd-6da0-451e-b6b8-7a6a29b5bab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126897050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1126897050
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4120219033
Short name T326
Test name
Test status
Simulation time 1474987659 ps
CPU time 1.98 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:41 PM PDT 24
Peak memory 192924 kb
Host smart-dd436335-2c25-45cc-8315-a259a34d3bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120219033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4120219033
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2028666655
Short name T322
Test name
Test status
Simulation time 613152937 ps
CPU time 1.54 seconds
Started Aug 04 04:30:49 PM PDT 24
Finished Aug 04 04:30:51 PM PDT 24
Peak memory 198548 kb
Host smart-36766f92-8636-40ce-8821-f8f02cb172e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028666655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2028666655
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3285746973
Short name T321
Test name
Test status
Simulation time 4875606058 ps
CPU time 1.47 seconds
Started Aug 04 04:31:04 PM PDT 24
Finished Aug 04 04:31:06 PM PDT 24
Peak memory 196640 kb
Host smart-4c1c07bd-088d-4d53-8592-daf9ba8fff2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285746973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3285746973
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3795532586
Short name T201
Test name
Test status
Simulation time 464827842 ps
CPU time 0.99 seconds
Started Aug 04 04:30:38 PM PDT 24
Finished Aug 04 04:30:39 PM PDT 24
Peak memory 195520 kb
Host smart-aaacd7c2-0f70-4b1f-a5c2-2bf0fe7ebd12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795532586 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3795532586
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2103661611
Short name T28
Test name
Test status
Simulation time 540790705 ps
CPU time 0.97 seconds
Started Aug 04 04:30:37 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 193264 kb
Host smart-952a5d78-be2a-4b32-9494-6c862629b7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103661611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2103661611
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1310383371
Short name T374
Test name
Test status
Simulation time 477205212 ps
CPU time 0.92 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:35 PM PDT 24
Peak memory 183612 kb
Host smart-372e2ae8-ef0c-487d-a9ea-963d582bda13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310383371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1310383371
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2721811559
Short name T318
Test name
Test status
Simulation time 2196440520 ps
CPU time 2.1 seconds
Started Aug 04 04:30:42 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 193776 kb
Host smart-ee748993-f6e0-4335-9048-88b1499f94f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721811559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2721811559
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3767974359
Short name T353
Test name
Test status
Simulation time 448946360 ps
CPU time 0.99 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 198280 kb
Host smart-89196aed-8b32-43f1-92fe-e0478e08a239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767974359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3767974359
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2802551910
Short name T194
Test name
Test status
Simulation time 4064326896 ps
CPU time 2.26 seconds
Started Aug 04 04:30:31 PM PDT 24
Finished Aug 04 04:30:34 PM PDT 24
Peak memory 197796 kb
Host smart-038aecc8-1fc8-43c0-8bda-50e888647b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802551910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2802551910
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1356404369
Short name T382
Test name
Test status
Simulation time 484546161 ps
CPU time 1.19 seconds
Started Aug 04 04:30:51 PM PDT 24
Finished Aug 04 04:30:53 PM PDT 24
Peak memory 196720 kb
Host smart-db809f0f-1560-49bd-b368-1aa2e8205ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356404369 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1356404369
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3523889733
Short name T356
Test name
Test status
Simulation time 524485324 ps
CPU time 0.77 seconds
Started Aug 04 04:30:59 PM PDT 24
Finished Aug 04 04:31:00 PM PDT 24
Peak memory 192976 kb
Host smart-11d0284a-b490-45d2-8e0d-46a4d87c4f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523889733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3523889733
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1902189076
Short name T304
Test name
Test status
Simulation time 323311574 ps
CPU time 0.76 seconds
Started Aug 04 04:30:32 PM PDT 24
Finished Aug 04 04:30:33 PM PDT 24
Peak memory 183768 kb
Host smart-a7c117dc-3dba-4640-abed-d4ccd30e0565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902189076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1902189076
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3515795750
Short name T355
Test name
Test status
Simulation time 2820677178 ps
CPU time 1.58 seconds
Started Aug 04 04:30:54 PM PDT 24
Finished Aug 04 04:30:56 PM PDT 24
Peak memory 194972 kb
Host smart-2a23a7dc-8435-4429-90e6-868571ebdba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515795750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3515795750
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.966244286
Short name T421
Test name
Test status
Simulation time 799684092 ps
CPU time 1.91 seconds
Started Aug 04 04:30:43 PM PDT 24
Finished Aug 04 04:30:45 PM PDT 24
Peak memory 198528 kb
Host smart-9396f155-5c58-45a8-9f34-9ea440ce10ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966244286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.966244286
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.700885233
Short name T354
Test name
Test status
Simulation time 8280796851 ps
CPU time 13.65 seconds
Started Aug 04 04:30:48 PM PDT 24
Finished Aug 04 04:31:02 PM PDT 24
Peak memory 198036 kb
Host smart-b84ad5c5-c2fc-4f25-8bbc-fbd04249e26b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700885233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.700885233
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1766479411
Short name T394
Test name
Test status
Simulation time 554686578 ps
CPU time 1.02 seconds
Started Aug 04 04:30:36 PM PDT 24
Finished Aug 04 04:30:37 PM PDT 24
Peak memory 195444 kb
Host smart-944d6d3c-82ee-4c37-95a8-cc826595ca60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766479411 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1766479411
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1056337035
Short name T375
Test name
Test status
Simulation time 379370459 ps
CPU time 0.87 seconds
Started Aug 04 04:30:53 PM PDT 24
Finished Aug 04 04:30:54 PM PDT 24
Peak memory 192976 kb
Host smart-02bcf72e-5acd-42a9-b3c7-5f901d848d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056337035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1056337035
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2959264386
Short name T292
Test name
Test status
Simulation time 487566105 ps
CPU time 1.26 seconds
Started Aug 04 04:30:45 PM PDT 24
Finished Aug 04 04:30:47 PM PDT 24
Peak memory 183768 kb
Host smart-65726f32-6211-43d8-8064-f13ef7492290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959264386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2959264386
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2517307355
Short name T325
Test name
Test status
Simulation time 1942129400 ps
CPU time 5.84 seconds
Started Aug 04 04:31:01 PM PDT 24
Finished Aug 04 04:31:07 PM PDT 24
Peak memory 193804 kb
Host smart-65933bb6-2461-49e4-8b2e-130eb1806ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517307355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2517307355
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.240491737
Short name T300
Test name
Test status
Simulation time 1115360314 ps
CPU time 1.19 seconds
Started Aug 04 04:30:39 PM PDT 24
Finished Aug 04 04:30:40 PM PDT 24
Peak memory 198536 kb
Host smart-a1881342-ec03-4b76-bd57-25f4ad3227fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240491737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.240491737
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.254782892
Short name T422
Test name
Test status
Simulation time 7754233846 ps
CPU time 3.44 seconds
Started Aug 04 04:30:34 PM PDT 24
Finished Aug 04 04:30:38 PM PDT 24
Peak memory 198396 kb
Host smart-a7f93bb0-5591-4bcc-95ab-3de4e9d704f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254782892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.254782892
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2740035436
Short name T27
Test name
Test status
Simulation time 406567550 ps
CPU time 1.19 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:17 PM PDT 24
Peak memory 195064 kb
Host smart-42e5afa9-3982-4dbd-8dbd-f7338a6f43e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740035436 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2740035436
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4218291709
Short name T82
Test name
Test status
Simulation time 532094491 ps
CPU time 1.38 seconds
Started Aug 04 04:31:03 PM PDT 24
Finished Aug 04 04:31:05 PM PDT 24
Peak memory 192856 kb
Host smart-2fc8b6d9-5683-4fd3-8d04-92a32023178f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218291709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4218291709
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2149484545
Short name T408
Test name
Test status
Simulation time 373371778 ps
CPU time 0.8 seconds
Started Aug 04 04:30:54 PM PDT 24
Finished Aug 04 04:30:55 PM PDT 24
Peak memory 183620 kb
Host smart-d41248f7-2012-4452-94df-fca9851f3fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149484545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2149484545
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3918733031
Short name T317
Test name
Test status
Simulation time 2021587565 ps
CPU time 2.69 seconds
Started Aug 04 04:30:41 PM PDT 24
Finished Aug 04 04:30:44 PM PDT 24
Peak memory 194872 kb
Host smart-353128e8-4f26-464c-8a4d-169236a49502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918733031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3918733031
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3195300785
Short name T341
Test name
Test status
Simulation time 774936010 ps
CPU time 2.45 seconds
Started Aug 04 04:30:28 PM PDT 24
Finished Aug 04 04:30:30 PM PDT 24
Peak memory 198488 kb
Host smart-cf9db310-a48e-43e9-9a18-1d165b8518df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195300785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3195300785
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2101742077
Short name T193
Test name
Test status
Simulation time 4223460785 ps
CPU time 6.37 seconds
Started Aug 04 04:31:15 PM PDT 24
Finished Aug 04 04:31:22 PM PDT 24
Peak memory 197968 kb
Host smart-64167721-28c7-4aee-912d-b56892eba41d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101742077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2101742077
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2283755267
Short name T279
Test name
Test status
Simulation time 4798573700 ps
CPU time 1.05 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 191844 kb
Host smart-7febd3d3-95f7-4046-9647-d4325121d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283755267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2283755267
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4095002874
Short name T267
Test name
Test status
Simulation time 559922159 ps
CPU time 0.97 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 191748 kb
Host smart-c7168d9c-ef4a-4f0c-b681-65a129fb0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095002874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4095002874
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3351494951
Short name T218
Test name
Test status
Simulation time 21746637049 ps
CPU time 15.91 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:50 PM PDT 24
Peak memory 191888 kb
Host smart-684a0599-1609-44ac-9394-ec67283dc0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351494951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3351494951
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1659541314
Short name T20
Test name
Test status
Simulation time 7966824422 ps
CPU time 6.97 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 215824 kb
Host smart-d017f840-304e-4189-80a8-06a12737a7bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659541314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1659541314
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1744411189
Short name T247
Test name
Test status
Simulation time 580809244 ps
CPU time 0.78 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 196564 kb
Host smart-3a7c4170-f52b-4c77-a61e-0a257d009eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744411189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1744411189
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.900539243
Short name T198
Test name
Test status
Simulation time 37160297775 ps
CPU time 55.63 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:29:30 PM PDT 24
Peak memory 191876 kb
Host smart-02e742d2-2264-4c2f-8aff-e81f6fba5ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900539243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.900539243
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.427436704
Short name T253
Test name
Test status
Simulation time 451483906 ps
CPU time 1.31 seconds
Started Aug 04 05:28:38 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 191852 kb
Host smart-25156f96-dddb-4383-a749-ef58115510a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427436704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.427436704
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3026798515
Short name T197
Test name
Test status
Simulation time 3798877033 ps
CPU time 6.26 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 196716 kb
Host smart-9bfd1f0a-baf1-4b32-8b40-51d5dda9f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026798515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3026798515
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2303701404
Short name T210
Test name
Test status
Simulation time 580951276 ps
CPU time 1.47 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196644 kb
Host smart-03c1df42-ca1b-48e1-8ef5-2e29da984bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303701404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2303701404
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4035247471
Short name T208
Test name
Test status
Simulation time 31524375857 ps
CPU time 44.03 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 191892 kb
Host smart-c8a7b900-56d5-4bce-bae9-bc35406d72d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035247471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4035247471
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1226441528
Short name T283
Test name
Test status
Simulation time 562433523 ps
CPU time 0.77 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 191800 kb
Host smart-1ae37346-6e71-4d1d-998b-e2ea0ad27b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226441528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1226441528
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3376274143
Short name T46
Test name
Test status
Simulation time 573156449 ps
CPU time 1.3 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 196792 kb
Host smart-971efdc9-171e-49c9-8719-b61facd21445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376274143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3376274143
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2912208460
Short name T265
Test name
Test status
Simulation time 30505455406 ps
CPU time 37.8 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:29:17 PM PDT 24
Peak memory 191884 kb
Host smart-458622df-1695-444f-8981-b1e7bfc2cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912208460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2912208460
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.833743075
Short name T238
Test name
Test status
Simulation time 570632512 ps
CPU time 1.37 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 191760 kb
Host smart-6dd9496a-e9f2-4710-8ebe-26c1ead85a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833743075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.833743075
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3718036432
Short name T280
Test name
Test status
Simulation time 7495614267 ps
CPU time 3.46 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 191788 kb
Host smart-51dc993e-36cc-4a5f-bd37-1277ffc0028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718036432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3718036432
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1006266982
Short name T220
Test name
Test status
Simulation time 586212449 ps
CPU time 1.44 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 196476 kb
Host smart-e6a92585-9bbe-40a4-8093-d533b1ccd9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006266982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1006266982
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2602839989
Short name T235
Test name
Test status
Simulation time 32608324684 ps
CPU time 12.47 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 191888 kb
Host smart-d51ef571-5446-4858-860d-a622da790097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602839989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2602839989
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1075460436
Short name T284
Test name
Test status
Simulation time 575037232 ps
CPU time 0.8 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 191824 kb
Host smart-57c8d651-81a9-40cf-b834-129d4705987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075460436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1075460436
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.16192376
Short name T272
Test name
Test status
Simulation time 8314646976 ps
CPU time 3.62 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 191884 kb
Host smart-7fe7a9dd-07dc-4c63-ba5f-cd8c87954685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16192376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.16192376
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4060413937
Short name T282
Test name
Test status
Simulation time 419766262 ps
CPU time 1.03 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 191840 kb
Host smart-d01ec249-c199-4069-a1d6-bc0e1a71a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060413937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4060413937
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1469437719
Short name T281
Test name
Test status
Simulation time 3988152290 ps
CPU time 6.17 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 196624 kb
Host smart-e7006da6-ddb0-45f2-8be3-c138c669ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469437719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1469437719
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.94132080
Short name T225
Test name
Test status
Simulation time 605843157 ps
CPU time 1.48 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 191724 kb
Host smart-c532c459-0e0f-4795-96fb-e19ab14091b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94132080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.94132080
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1509402940
Short name T232
Test name
Test status
Simulation time 6161480818 ps
CPU time 2.72 seconds
Started Aug 04 05:28:51 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 192084 kb
Host smart-367a4608-c0ce-4fee-8881-996b458ee81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509402940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1509402940
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.512035111
Short name T251
Test name
Test status
Simulation time 431210938 ps
CPU time 0.71 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 196668 kb
Host smart-a02741d7-7720-4856-8ead-8a45c0669426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512035111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.512035111
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1265900946
Short name T228
Test name
Test status
Simulation time 23889718610 ps
CPU time 33.5 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:29:08 PM PDT 24
Peak memory 191876 kb
Host smart-0969af2d-5891-41af-8f1d-17c629473f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265900946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1265900946
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2268560423
Short name T51
Test name
Test status
Simulation time 374250803 ps
CPU time 0.69 seconds
Started Aug 04 05:28:53 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 191760 kb
Host smart-d8b4d7bc-77c9-4b64-b6e4-057a8884ab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268560423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2268560423
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1168568624
Short name T230
Test name
Test status
Simulation time 26718555086 ps
CPU time 5.48 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 196796 kb
Host smart-921c11af-2f80-4d1b-9fe6-3220a79fcc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168568624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1168568624
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3068199315
Short name T17
Test name
Test status
Simulation time 7514382272 ps
CPU time 3.25 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 215812 kb
Host smart-09f230f1-af35-4772-8447-df02d7f6f804
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068199315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3068199315
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2465314145
Short name T255
Test name
Test status
Simulation time 508317714 ps
CPU time 0.68 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 191676 kb
Host smart-9b6d6321-f75b-45ee-a735-29ea6713a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465314145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2465314145
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2247561077
Short name T185
Test name
Test status
Simulation time 626629794 ps
CPU time 0.62 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196552 kb
Host smart-875a209d-73b5-4afc-ac5d-9e5ecf5f06bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247561077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2247561077
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4013787490
Short name T215
Test name
Test status
Simulation time 21057023639 ps
CPU time 7.1 seconds
Started Aug 04 05:28:40 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 191808 kb
Host smart-44ef9ee0-1613-45a8-9ea8-a8b311256515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013787490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4013787490
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.128128058
Short name T268
Test name
Test status
Simulation time 381792917 ps
CPU time 0.72 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 196616 kb
Host smart-9bfef795-99fe-490a-8391-1f52fcb070d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128128058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.128128058
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4010269147
Short name T74
Test name
Test status
Simulation time 17180902994 ps
CPU time 4.97 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 191924 kb
Host smart-bbb3214f-35bd-4e41-808c-4d694a8d75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010269147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4010269147
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4064410468
Short name T93
Test name
Test status
Simulation time 393296043 ps
CPU time 1.12 seconds
Started Aug 04 05:28:38 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 191804 kb
Host smart-90de110b-c20d-4011-bc4e-f526a04efd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064410468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4064410468
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.856742233
Short name T205
Test name
Test status
Simulation time 36115705239 ps
CPU time 14.51 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 191828 kb
Host smart-910ea864-b02d-4373-9501-9881f5d459ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856742233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.856742233
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1779178020
Short name T223
Test name
Test status
Simulation time 524019490 ps
CPU time 1.45 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 192016 kb
Host smart-0e48d753-36dd-424e-a4ae-11cd1e31b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779178020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1779178020
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1388311966
Short name T204
Test name
Test status
Simulation time 40829308533 ps
CPU time 13.51 seconds
Started Aug 04 05:28:35 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 191872 kb
Host smart-d6c865a9-7ece-4528-9477-4372a803b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388311966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1388311966
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1902665418
Short name T233
Test name
Test status
Simulation time 511307040 ps
CPU time 1.34 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 191748 kb
Host smart-f7be50d8-3b32-45ba-aa08-05130c265399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902665418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1902665418
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1068000329
Short name T1
Test name
Test status
Simulation time 6882551805 ps
CPU time 9.95 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 191892 kb
Host smart-1644b037-6e70-42cb-a26c-778de68809a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068000329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1068000329
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.789408912
Short name T211
Test name
Test status
Simulation time 583828147 ps
CPU time 0.96 seconds
Started Aug 04 05:28:36 PM PDT 24
Finished Aug 04 05:28:37 PM PDT 24
Peak memory 196644 kb
Host smart-0e824124-b85e-472b-bb88-c7d2a275aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789408912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.789408912
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3543964397
Short name T237
Test name
Test status
Simulation time 21883112596 ps
CPU time 8.48 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 191816 kb
Host smart-7c7090eb-f21c-4b5c-80ec-fd0305131710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543964397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3543964397
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1307749539
Short name T239
Test name
Test status
Simulation time 442105925 ps
CPU time 1.31 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:42 PM PDT 24
Peak memory 191848 kb
Host smart-1c87261d-7313-4dde-b744-7ca806f7f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307749539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1307749539
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.672626366
Short name T183
Test name
Test status
Simulation time 455047906 ps
CPU time 1.28 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:36 PM PDT 24
Peak memory 196620 kb
Host smart-2fff5ae4-b860-4d77-b346-f834848921cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672626366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.672626366
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3976192070
Short name T236
Test name
Test status
Simulation time 17560926908 ps
CPU time 5.79 seconds
Started Aug 04 05:28:59 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 191832 kb
Host smart-1c34bc29-8c64-49d1-91b2-d2857f12cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976192070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3976192070
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2694739736
Short name T229
Test name
Test status
Simulation time 475272309 ps
CPU time 0.85 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 191668 kb
Host smart-00aa1fd6-d816-40bf-aaf3-680e95707319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694739736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2694739736
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3428788858
Short name T250
Test name
Test status
Simulation time 46565273656 ps
CPU time 18.12 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:29:01 PM PDT 24
Peak memory 196836 kb
Host smart-9863d4a6-844f-49b9-84d9-d54afe9020a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428788858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3428788858
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1079090702
Short name T274
Test name
Test status
Simulation time 443372999 ps
CPU time 0.89 seconds
Started Aug 04 05:28:57 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 191760 kb
Host smart-c95d44a5-3649-4398-9341-59c96d777822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079090702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1079090702
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3710279312
Short name T199
Test name
Test status
Simulation time 29681150481 ps
CPU time 20.48 seconds
Started Aug 04 05:29:01 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 196908 kb
Host smart-4cc1a6ab-a3c3-4af5-a71e-e4f687aaadb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710279312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3710279312
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.335211367
Short name T209
Test name
Test status
Simulation time 512656110 ps
CPU time 0.74 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 196560 kb
Host smart-9e4c3dd0-4c90-4b4f-bc39-e4728607dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335211367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.335211367
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.167630545
Short name T244
Test name
Test status
Simulation time 23606979446 ps
CPU time 36.82 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:29:16 PM PDT 24
Peak memory 196904 kb
Host smart-a6531c0c-e92b-4ad7-8a82-f44b229ce6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167630545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.167630545
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.677911575
Short name T234
Test name
Test status
Simulation time 435419902 ps
CPU time 0.86 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 191804 kb
Host smart-a08a8419-c37b-4029-9408-c48c0bfca812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677911575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.677911575
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2689698402
Short name T219
Test name
Test status
Simulation time 27822406523 ps
CPU time 40.02 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:29:13 PM PDT 24
Peak memory 191908 kb
Host smart-456b061e-e93f-46b0-90af-03a0c305a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689698402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2689698402
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2907878338
Short name T19
Test name
Test status
Simulation time 7207061444 ps
CPU time 6.95 seconds
Started Aug 04 05:28:31 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 215748 kb
Host smart-1d5c1192-98ec-462c-aec6-8cf6933443e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907878338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2907878338
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.658005945
Short name T5
Test name
Test status
Simulation time 391009647 ps
CPU time 0.7 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:34 PM PDT 24
Peak memory 191676 kb
Host smart-37e202f5-eeb4-44ed-9bb1-00b1f765d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658005945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.658005945
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2522077569
Short name T249
Test name
Test status
Simulation time 53013933163 ps
CPU time 72.12 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:29:53 PM PDT 24
Peak memory 191836 kb
Host smart-0eff65f0-a9b8-4c2c-8b14-673294747f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522077569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2522077569
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.174534436
Short name T271
Test name
Test status
Simulation time 393948619 ps
CPU time 0.88 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 196572 kb
Host smart-00f06cdc-2801-4554-97a3-1cff2c4993e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174534436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.174534436
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2344262925
Short name T227
Test name
Test status
Simulation time 12713307705 ps
CPU time 5.47 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 191892 kb
Host smart-86914199-953f-41a7-ab8f-622a5252403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344262925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2344262925
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1469299242
Short name T226
Test name
Test status
Simulation time 587393527 ps
CPU time 0.81 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 191836 kb
Host smart-5e59c16f-b0ca-4262-8236-2a0ba5f3b8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469299242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1469299242
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2077648392
Short name T217
Test name
Test status
Simulation time 23526640630 ps
CPU time 17.55 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 191844 kb
Host smart-79a36523-f7be-4827-94f7-1895c233b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077648392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2077648392
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3108722989
Short name T43
Test name
Test status
Simulation time 547881596 ps
CPU time 0.74 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:43 PM PDT 24
Peak memory 191820 kb
Host smart-25034e8e-f88a-4c64-8ee4-70bd4c06aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108722989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3108722989
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1235108775
Short name T264
Test name
Test status
Simulation time 15373903884 ps
CPU time 5.47 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 191840 kb
Host smart-aaac9f7b-95b9-4df1-b9fd-104b5456b0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235108775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1235108775
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2755583545
Short name T248
Test name
Test status
Simulation time 471135932 ps
CPU time 1.2 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 191828 kb
Host smart-2dc48036-07fd-4f49-b8ec-5af65ea04955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755583545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2755583545
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2120255451
Short name T231
Test name
Test status
Simulation time 25723392477 ps
CPU time 8.45 seconds
Started Aug 04 05:28:42 PM PDT 24
Finished Aug 04 05:28:50 PM PDT 24
Peak memory 191868 kb
Host smart-870b3f40-9068-446b-86a7-56a2e4d1205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120255451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2120255451
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2111219323
Short name T266
Test name
Test status
Simulation time 397044651 ps
CPU time 0.7 seconds
Started Aug 04 05:28:38 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 191796 kb
Host smart-beb96e8a-66b5-40e1-9da0-8adfe8442066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111219323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2111219323
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.287676141
Short name T273
Test name
Test status
Simulation time 31455679157 ps
CPU time 15.49 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:29:01 PM PDT 24
Peak memory 191876 kb
Host smart-c67b2732-6e3d-4ad3-8289-46d7d58dd930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287676141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.287676141
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1917889226
Short name T241
Test name
Test status
Simulation time 376052820 ps
CPU time 1.13 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 196604 kb
Host smart-7c5674d7-4f54-4c02-a356-2aa4a8acedc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917889226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1917889226
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3495299331
Short name T277
Test name
Test status
Simulation time 27284567247 ps
CPU time 11.16 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:55 PM PDT 24
Peak memory 196832 kb
Host smart-f944bf67-b5c7-409e-9a5e-b385b3b6fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495299331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3495299331
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.534190335
Short name T6
Test name
Test status
Simulation time 551058421 ps
CPU time 1.45 seconds
Started Aug 04 05:28:47 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 191696 kb
Host smart-59c2d761-0729-4a00-946a-a33d51e87d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534190335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.534190335
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1597906365
Short name T257
Test name
Test status
Simulation time 41074900503 ps
CPU time 56.93 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:29:41 PM PDT 24
Peak memory 196904 kb
Host smart-67cf9f04-5019-4d8a-83d4-b9ebbdbbe33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597906365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1597906365
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.360040112
Short name T261
Test name
Test status
Simulation time 438290060 ps
CPU time 0.74 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 191712 kb
Host smart-da542a0c-19dc-4182-ad02-9acdad0c62ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360040112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.360040112
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1331758342
Short name T189
Test name
Test status
Simulation time 570144200 ps
CPU time 0.77 seconds
Started Aug 04 05:28:43 PM PDT 24
Finished Aug 04 05:28:44 PM PDT 24
Peak memory 196700 kb
Host smart-d8dc65b6-9f97-4d11-a0bf-8e779fbf2441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331758342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1331758342
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2076211799
Short name T263
Test name
Test status
Simulation time 48211095243 ps
CPU time 37.71 seconds
Started Aug 04 05:28:50 PM PDT 24
Finished Aug 04 05:29:27 PM PDT 24
Peak memory 191808 kb
Host smart-9f90854c-3365-4ddf-89f1-2780c1972b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076211799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2076211799
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2832820101
Short name T92
Test name
Test status
Simulation time 424851630 ps
CPU time 0.64 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 191800 kb
Host smart-547b6c8a-9abc-49c2-9695-f7ee3f5431c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832820101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2832820101
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1422814374
Short name T221
Test name
Test status
Simulation time 24604917570 ps
CPU time 34 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:29:27 PM PDT 24
Peak memory 191844 kb
Host smart-bdf5b014-2f52-4c37-9516-79f0e1c773f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422814374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1422814374
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2782428049
Short name T243
Test name
Test status
Simulation time 554701651 ps
CPU time 1.47 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 196620 kb
Host smart-d50af752-bd24-471a-aef0-244f793f3035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782428049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2782428049
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.732854416
Short name T214
Test name
Test status
Simulation time 2119695983 ps
CPU time 1.12 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 191832 kb
Host smart-5ce10557-8ff9-4e86-80d5-5b8bd807b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732854416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.732854416
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.470651479
Short name T11
Test name
Test status
Simulation time 8496249453 ps
CPU time 13.63 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 215656 kb
Host smart-99e672d7-ecb1-416f-a924-aa1c7335a1ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470651479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.470651479
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2092147010
Short name T258
Test name
Test status
Simulation time 504021989 ps
CPU time 0.99 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 191800 kb
Host smart-58cd704f-1c20-48c6-a77b-9ba97bf796dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092147010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2092147010
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2254496227
Short name T200
Test name
Test status
Simulation time 46839995947 ps
CPU time 7.95 seconds
Started Aug 04 05:28:49 PM PDT 24
Finished Aug 04 05:28:57 PM PDT 24
Peak memory 191892 kb
Host smart-8be2a3a4-d735-454d-95e0-34c1d97c72a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254496227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2254496227
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3464307934
Short name T9
Test name
Test status
Simulation time 529087185 ps
CPU time 0.78 seconds
Started Aug 04 05:28:46 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 191800 kb
Host smart-7cb1e480-22ac-49fd-9806-537ffc6719d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464307934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3464307934
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2404713444
Short name T275
Test name
Test status
Simulation time 18961880845 ps
CPU time 15.62 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:29:04 PM PDT 24
Peak memory 196900 kb
Host smart-3e23c165-0e03-479d-a729-e0ab430d4321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404713444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2404713444
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.599883671
Short name T224
Test name
Test status
Simulation time 365651230 ps
CPU time 0.7 seconds
Started Aug 04 05:28:44 PM PDT 24
Finished Aug 04 05:28:45 PM PDT 24
Peak memory 191860 kb
Host smart-88a544c2-e81a-4797-8eb8-6586b5593bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599883671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.599883671
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2531009447
Short name T77
Test name
Test status
Simulation time 28507504935 ps
CPU time 36.22 seconds
Started Aug 04 05:28:49 PM PDT 24
Finished Aug 04 05:29:25 PM PDT 24
Peak memory 191884 kb
Host smart-8580648c-be0b-48b7-b465-5998a185bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531009447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2531009447
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2811673163
Short name T252
Test name
Test status
Simulation time 478110130 ps
CPU time 0.92 seconds
Started Aug 04 05:29:01 PM PDT 24
Finished Aug 04 05:29:02 PM PDT 24
Peak memory 191736 kb
Host smart-1af3f8ee-d9e9-4db7-a4da-c84396b787ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811673163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2811673163
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2686942366
Short name T285
Test name
Test status
Simulation time 9812632714 ps
CPU time 74.17 seconds
Started Aug 04 05:28:45 PM PDT 24
Finished Aug 04 05:29:59 PM PDT 24
Peak memory 213968 kb
Host smart-8a4cc72b-3bfd-4e19-af8e-1273756479c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686942366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2686942366
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2881503754
Short name T160
Test name
Test status
Simulation time 584459842 ps
CPU time 0.82 seconds
Started Aug 04 05:28:59 PM PDT 24
Finished Aug 04 05:29:00 PM PDT 24
Peak memory 196596 kb
Host smart-47b4db36-7bf5-4b6e-bd30-0685a502dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881503754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2881503754
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3569310028
Short name T245
Test name
Test status
Simulation time 38111548714 ps
CPU time 54.1 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:29:51 PM PDT 24
Peak memory 196780 kb
Host smart-42b024cf-811c-440f-9c72-b13548028802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569310028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3569310028
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.409654614
Short name T95
Test name
Test status
Simulation time 434284216 ps
CPU time 1.05 seconds
Started Aug 04 05:28:49 PM PDT 24
Finished Aug 04 05:28:50 PM PDT 24
Peak memory 191744 kb
Host smart-5701d2bf-41b9-4dde-9a48-80fa26259cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409654614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.409654614
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1578242719
Short name T254
Test name
Test status
Simulation time 36502464274 ps
CPU time 27.74 seconds
Started Aug 04 05:29:07 PM PDT 24
Finished Aug 04 05:29:34 PM PDT 24
Peak memory 191812 kb
Host smart-1cfbd3ec-f227-4084-9273-5aaeda7c6592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578242719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1578242719
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2908034152
Short name T207
Test name
Test status
Simulation time 588281071 ps
CPU time 0.8 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:28:48 PM PDT 24
Peak memory 191828 kb
Host smart-f59be842-d602-4b43-8312-bcf25a188792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908034152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2908034152
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3957702366
Short name T256
Test name
Test status
Simulation time 47417264298 ps
CPU time 16.44 seconds
Started Aug 04 05:29:04 PM PDT 24
Finished Aug 04 05:29:21 PM PDT 24
Peak memory 196888 kb
Host smart-93662902-681c-4535-b24a-7e71f94c5637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957702366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3957702366
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.602141628
Short name T276
Test name
Test status
Simulation time 418814362 ps
CPU time 0.71 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:28:52 PM PDT 24
Peak memory 196608 kb
Host smart-55062c2d-4edc-4e9f-aa3a-ec2f92563afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602141628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.602141628
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3739179041
Short name T94
Test name
Test status
Simulation time 24587390142 ps
CPU time 33.47 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:29:22 PM PDT 24
Peak memory 196856 kb
Host smart-198f9724-b21c-43d3-8069-3115f27b1f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739179041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3739179041
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1745522195
Short name T206
Test name
Test status
Simulation time 407909881 ps
CPU time 0.89 seconds
Started Aug 04 05:28:48 PM PDT 24
Finished Aug 04 05:28:49 PM PDT 24
Peak memory 196660 kb
Host smart-136934a3-d218-4450-ac84-4630d93489c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745522195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1745522195
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3031398269
Short name T278
Test name
Test status
Simulation time 53118495201 ps
CPU time 19.99 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:29:12 PM PDT 24
Peak memory 191876 kb
Host smart-91c00e3f-b69e-4465-a60c-6c102d0e3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031398269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3031398269
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2947779547
Short name T270
Test name
Test status
Simulation time 407310110 ps
CPU time 0.99 seconds
Started Aug 04 05:28:55 PM PDT 24
Finished Aug 04 05:28:56 PM PDT 24
Peak memory 191708 kb
Host smart-6821cb7b-8b4b-4d8a-a579-cfeb4abe7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947779547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2947779547
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.931596064
Short name T222
Test name
Test status
Simulation time 13537179122 ps
CPU time 21.21 seconds
Started Aug 04 05:29:05 PM PDT 24
Finished Aug 04 05:29:27 PM PDT 24
Peak memory 191900 kb
Host smart-202ba028-bab8-4682-9260-5d480b59b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931596064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.931596064
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2188062196
Short name T212
Test name
Test status
Simulation time 516431034 ps
CPU time 0.66 seconds
Started Aug 04 05:29:01 PM PDT 24
Finished Aug 04 05:29:02 PM PDT 24
Peak memory 196604 kb
Host smart-ac132a11-40de-471b-aee5-048e04788692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188062196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2188062196
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1840690912
Short name T262
Test name
Test status
Simulation time 15576714698 ps
CPU time 6.51 seconds
Started Aug 04 05:28:52 PM PDT 24
Finished Aug 04 05:28:58 PM PDT 24
Peak memory 191900 kb
Host smart-7d379832-59b2-484b-b64a-3b0c841c3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840690912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1840690912
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.957821638
Short name T213
Test name
Test status
Simulation time 618736084 ps
CPU time 0.65 seconds
Started Aug 04 05:28:54 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 196512 kb
Host smart-2e8b61cf-fd0b-4d1e-bce7-6ef6efdd6a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957821638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.957821638
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1012780244
Short name T246
Test name
Test status
Simulation time 50001218347 ps
CPU time 17.56 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:51 PM PDT 24
Peak memory 191900 kb
Host smart-328979dc-e077-4bea-8f75-704934a153e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012780244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1012780244
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2695014289
Short name T76
Test name
Test status
Simulation time 437319467 ps
CPU time 1.23 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:35 PM PDT 24
Peak memory 191696 kb
Host smart-d78afb05-1b56-46d3-a16c-f394b70e824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695014289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2695014289
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3774579630
Short name T242
Test name
Test status
Simulation time 3539232536 ps
CPU time 2.33 seconds
Started Aug 04 05:28:38 PM PDT 24
Finished Aug 04 05:28:41 PM PDT 24
Peak memory 191732 kb
Host smart-2bf853f1-afd9-46a5-bdc8-5e6524afb623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774579630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3774579630
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4249232850
Short name T216
Test name
Test status
Simulation time 363625437 ps
CPU time 1.07 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:39 PM PDT 24
Peak memory 191676 kb
Host smart-d79cb786-513f-4763-9ea0-907c75895403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249232850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4249232850
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3388383143
Short name T203
Test name
Test status
Simulation time 49800885841 ps
CPU time 32.79 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:29:10 PM PDT 24
Peak memory 191872 kb
Host smart-8fe598e3-2686-4d72-b00b-e4f0c8cc20e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388383143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3388383143
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1451873178
Short name T259
Test name
Test status
Simulation time 556774195 ps
CPU time 0.97 seconds
Started Aug 04 05:28:37 PM PDT 24
Finished Aug 04 05:28:38 PM PDT 24
Peak memory 191796 kb
Host smart-a66bc841-3b89-4cd7-97ef-6dbc2da62bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451873178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1451873178
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3810713409
Short name T269
Test name
Test status
Simulation time 15948450013 ps
CPU time 20.78 seconds
Started Aug 04 05:28:33 PM PDT 24
Finished Aug 04 05:28:54 PM PDT 24
Peak memory 196832 kb
Host smart-8f8e318f-b24d-402f-81c8-061dc7596089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810713409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3810713409
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1139340595
Short name T260
Test name
Test status
Simulation time 385138889 ps
CPU time 1.17 seconds
Started Aug 04 05:28:39 PM PDT 24
Finished Aug 04 05:28:40 PM PDT 24
Peak memory 191728 kb
Host smart-61ea12cb-bb7e-465a-9bec-f185e89344f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139340595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1139340595
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3123243726
Short name T84
Test name
Test status
Simulation time 11941106447 ps
CPU time 4.99 seconds
Started Aug 04 05:28:41 PM PDT 24
Finished Aug 04 05:28:46 PM PDT 24
Peak memory 191892 kb
Host smart-71897d6e-740c-4367-ba5d-582aa1c53386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123243726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3123243726
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3171366443
Short name T240
Test name
Test status
Simulation time 479731130 ps
CPU time 1.28 seconds
Started Aug 04 05:28:34 PM PDT 24
Finished Aug 04 05:28:36 PM PDT 24
Peak memory 191772 kb
Host smart-bc610576-db44-4971-9e89-bd475200f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171366443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3171366443
Directory /workspace/9.aon_timer_smoke/latest
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