Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30282	1		T1	11		T2	12		T3	10
bark[1]	309	1		T35	21		T110	21		T73	21
bark[2]	473	1		T35	21		T95	21		T26	228
bark[3]	231	1		T48	14		T150	21		T132	21
bark[4]	566	1		T32	14		T54	14		T132	26
bark[5]	457	1		T44	30		T148	69		T115	21
bark[6]	490	1		T43	278		T120	21		T122	21
bark[7]	555	1		T52	14		T45	64		T58	21
bark[8]	717	1		T33	111		T58	54		T144	40
bark[9]	430	1		T5	85		T95	26		T101	14
bark[10]	929	1		T132	219		T139	42		T170	224
bark[11]	541	1		T5	47		T87	14		T110	21
bark[12]	611	1		T13	26		T45	48		T132	21
bark[13]	731	1		T5	43		T44	120		T73	54
bark[14]	841	1		T19	39		T34	83		T35	21
bark[15]	396	1		T35	21		T73	268		T117	21
bark[16]	330	1		T13	39		T59	14		T35	21
bark[17]	816	1		T19	48		T176	21		T132	257
bark[18]	415	1		T9	14		T35	21		T148	64
bark[19]	215	1		T13	21		T189	21		T144	40
bark[20]	565	1		T8	111		T88	14		T33	217
bark[21]	521	1		T50	14		T44	205		T34	26
bark[22]	428	1		T5	30		T13	21		T14	30
bark[23]	243	1		T44	21		T35	30		T125	21
bark[24]	260	1		T5	121		T13	21		T96	21
bark[25]	778	1		T34	266		T57	14		T46	21
bark[26]	286	1		T15	21		T44	74		T132	21
bark[27]	204	1		T136	30		T27	78		T137	40
bark[28]	1246	1		T44	179		T33	21		T35	21
bark[29]	692	1		T31	14		T44	85		T47	66
bark[30]	608	1		T33	285		T176	42		T26	21
bark[31]	444	1		T34	26		T139	21		T140	14
bark_0	4481	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29729	1		T1	10		T2	11		T3	9
bite[1]	469	1		T15	21		T57	13		T74	244
bite[2]	191	1		T132	21		T74	30		T108	13
bite[3]	256	1		T34	25		T35	21		T110	21
bite[4]	738	1		T34	68		T176	42		T105	21
bite[5]	313	1		T5	120		T44	30		T34	13
bite[6]	190	1		T44	21		T35	21		T27	21
bite[7]	259	1		T139	21		T144	39		T90	30
bite[8]	837	1		T88	13		T44	204		T59	13
bite[9]	558	1		T31	13		T125	21		T95	21
bite[10]	741	1		T52	13		T132	25		T136	21
bite[11]	594	1		T14	30		T54	13		T132	218
bite[12]	397	1		T13	26		T33	216		T46	4
bite[13]	921	1		T5	130		T33	277		T58	21
bite[14]	387	1		T33	21		T45	47		T35	30
bite[15]	541	1		T48	13		T46	21		T47	65
bite[16]	553	1		T8	79		T47	21		T132	21
bite[17]	270	1		T13	42		T19	39		T44	73
bite[18]	416	1		T32	13		T132	21		T148	228
bite[19]	278	1		T5	42		T150	21		T132	21
bite[20]	566	1		T34	265		T35	21		T110	21
bite[21]	1133	1		T9	13		T43	307		T150	21
bite[22]	549	1		T8	110		T87	13		T58	54
bite[23]	1167	1		T5	231		T8	21		T19	48
bite[24]	646	1		T13	21		T44	119		T144	40
bite[25]	268	1		T50	13		T110	26		T176	21
bite[26]	723	1		T13	39		T44	178		T132	21
bite[27]	388	1		T110	21		T150	21		T73	21
bite[28]	478	1		T15	6		T44	63		T33	110
bite[29]	704	1		T34	25		T110	68		T144	228
bite[30]	614	1		T5	30		T35	21		T136	21
bite[31]	191	1		T148	63		T161	59		T92	6
bite_0	5026	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42956	1		T1	11		T2	19		T3	17
auto[1]	8135	1		T1	7		T4	7		T5	26

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1111	1		T8	28		T15	176		T43	28
prescale[1]	705	1		T2	9		T13	49		T33	74
prescale[2]	1029	1		T43	75		T132	84		T95	2
prescale[3]	864	1		T8	64		T43	36		T23	75
prescale[4]	962	1		T5	23		T14	19		T202	9
prescale[5]	994	1		T5	23		T19	44		T47	2
prescale[6]	1217	1		T5	19		T34	84		T132	134
prescale[7]	1334	1		T8	243		T44	171		T33	76
prescale[8]	370	1		T8	36		T132	9		T95	2
prescale[9]	514	1		T5	24		T14	23		T19	31
prescale[10]	809	1		T8	49		T139	23		T203	9
prescale[11]	619	1		T5	9		T14	45		T204	9
prescale[12]	1001	1		T5	122		T8	2		T13	23
prescale[13]	607	1		T8	63		T13	54		T45	23
prescale[14]	865	1		T5	9		T8	38		T34	2
prescale[15]	586	1		T15	47		T43	2		T44	19
prescale[16]	880	1		T8	78		T44	2		T34	2
prescale[17]	1130	1		T19	19		T33	2		T35	58
prescale[18]	836	1		T8	151		T44	45		T170	19
prescale[19]	583	1		T5	19		T34	120		T132	55
prescale[20]	1368	1		T43	47		T34	23		T56	30
prescale[21]	930	1		T8	19		T11	9		T44	19
prescale[22]	975	1		T5	128		T8	170		T44	2
prescale[23]	623	1		T51	9		T15	25		T33	2
prescale[24]	515	1		T14	9		T15	36		T44	2
prescale[25]	701	1		T8	62		T12	9		T43	9
prescale[26]	1003	1		T8	202		T14	95		T15	2
prescale[27]	598	1		T8	19		T44	4		T33	14
prescale[28]	817	1		T8	77		T49	9		T148	53
prescale[29]	511	1		T5	2		T8	9		T58	23
prescale[30]	727	1		T8	153		T13	9		T15	19
prescale[31]	570	1		T5	2		T8	38		T34	2
prescale_0	24737	1		T1	18		T2	10		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37509	1		T1	9		T2	9		T3	17
auto[1]	13582	1		T1	9		T2	10		T4	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51091	1		T1	18		T2	19		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30043	1		T1	13		T2	14		T3	12
wkup[1]	376	1		T44	21		T34	21		T150	21
wkup[2]	218	1		T44	21		T46	21		T139	21
wkup[3]	185	1		T34	21		T95	21		T28	21
wkup[4]	269	1		T139	21		T170	15		T144	26
wkup[5]	236	1		T5	30		T46	30		T132	21
wkup[6]	433	1		T8	21		T15	21		T59	15
wkup[7]	221	1		T5	21		T8	21		T88	15
wkup[8]	270	1		T44	21		T45	21		T136	21
wkup[9]	251	1		T19	39		T34	21		T132	21
wkup[10]	352	1		T44	30		T33	30		T47	44
wkup[11]	388	1		T8	30		T33	21		T110	21
wkup[12]	444	1		T5	40		T15	15		T44	21
wkup[13]	275	1		T5	8		T8	21		T52	15
wkup[14]	320	1		T15	21		T176	21		T170	21
wkup[15]	393	1		T8	21		T14	21		T33	21
wkup[16]	223	1		T13	26		T31	15		T56	15
wkup[17]	76	1		T33	21		T34	8		T193	21
wkup[18]	214	1		T8	21		T15	21		T132	21
wkup[19]	351	1		T5	21		T8	21		T144	56
wkup[20]	279	1		T8	21		T14	30		T15	21
wkup[21]	193	1		T110	21		T47	26		T136	21
wkup[22]	210	1		T5	21		T34	21		T35	21
wkup[23]	96	1		T13	21		T120	30		T192	30
wkup[24]	215	1		T5	21		T8	39		T34	30
wkup[25]	171	1		T8	21		T144	15		T74	44
wkup[26]	251	1		T8	21		T58	26		T35	21
wkup[27]	363	1		T34	51		T45	21		T132	42
wkup[28]	300	1		T5	21		T8	21		T132	26
wkup[29]	269	1		T43	44		T35	21		T47	36
wkup[30]	363	1		T9	15		T44	21		T34	21
wkup[31]	226	1		T5	29		T33	40		T110	26
wkup[32]	249	1		T5	21		T8	47		T148	35
wkup[33]	313	1		T8	21		T125	21		T170	30
wkup[34]	293	1		T33	21		T132	30		T144	21
wkup[35]	345	1		T5	63		T46	42		T47	21
wkup[36]	224	1		T132	15		T189	21		T148	21
wkup[37]	256	1		T43	26		T33	21		T132	21
wkup[38]	195	1		T33	30		T54	15		T45	8
wkup[39]	311	1		T13	21		T34	15		T95	21
wkup[40]	192	1		T5	15		T8	21		T33	21
wkup[41]	215	1		T5	21		T8	35		T19	21
wkup[42]	179	1		T46	21		T194	15		T77	15
wkup[43]	346	1		T44	42		T34	26		T57	15
wkup[44]	314	1		T5	21		T8	48		T176	21
wkup[45]	306	1		T110	21		T132	21		T170	51
wkup[46]	287	1		T8	21		T50	15		T87	15
wkup[47]	384	1		T19	48		T44	21		T47	21
wkup[48]	343	1		T8	8		T14	21		T56	30
wkup[49]	367	1		T5	21		T8	26		T15	21
wkup[50]	210	1		T45	21		T46	21		T150	21
wkup[51]	259	1		T44	21		T95	26		T170	21
wkup[52]	375	1		T5	21		T33	71		T56	21
wkup[53]	255	1		T8	26		T34	21		T132	21
wkup[54]	221	1		T15	42		T44	39		T150	21
wkup[55]	299	1		T13	21		T34	21		T46	6
wkup[56]	251	1		T5	47		T44	21		T132	21
wkup[57]	221	1		T110	21		T47	21		T125	21
wkup[58]	331	1		T8	72		T44	21		T132	21
wkup[59]	409	1		T8	21		T13	39		T43	21
wkup[60]	282	1		T8	21		T15	8		T47	21
wkup[61]	302	1		T5	21		T8	21		T33	21
wkup[62]	307	1		T35	21		T144	21		T60	30
wkup[63]	280	1		T148	51		T24	21		T107	26
wkup_0	3496	1		T1	5		T2	5		T3	5