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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.93 99.33 93.67 100.00 98.40 99.51 48.66


Total test records in report: 424
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T282 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2761589674 Aug 05 05:26:54 PM PDT 24 Aug 05 05:26:55 PM PDT 24 485360501 ps
T283 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.914027822 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:22 PM PDT 24 487603215 ps
T41 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3176922779 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:37 PM PDT 24 407170528 ps
T284 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1927092244 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:21 PM PDT 24 515356716 ps
T285 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4234184753 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:54 PM PDT 24 445771461 ps
T36 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3256141453 Aug 05 05:26:39 PM PDT 24 Aug 05 05:26:52 PM PDT 24 7867828626 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2319496681 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 304540450 ps
T42 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.828492395 Aug 05 05:26:32 PM PDT 24 Aug 05 05:26:33 PM PDT 24 422420395 ps
T287 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1555663148 Aug 05 05:26:55 PM PDT 24 Aug 05 05:26:56 PM PDT 24 385301151 ps
T288 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.776791156 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:55 PM PDT 24 410947030 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2005042625 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:22 PM PDT 24 1884935288 ps
T205 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3275511632 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:26 PM PDT 24 398648956 ps
T289 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.686232115 Aug 05 05:26:27 PM PDT 24 Aug 05 05:26:29 PM PDT 24 434440226 ps
T38 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3958218850 Aug 05 05:26:27 PM PDT 24 Aug 05 05:26:31 PM PDT 24 2540995676 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2675872052 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:22 PM PDT 24 4708397695 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2482011243 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:25 PM PDT 24 405517573 ps
T64 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.618806937 Aug 05 05:26:29 PM PDT 24 Aug 05 05:26:30 PM PDT 24 493401750 ps
T80 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.595349423 Aug 05 05:26:44 PM PDT 24 Aug 05 05:26:45 PM PDT 24 2212351834 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.113771538 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:18 PM PDT 24 332741299 ps
T65 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4163296465 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 446324768 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.131969827 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:37 PM PDT 24 1053728905 ps
T293 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3794593602 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 437014126 ps
T294 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2632777226 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:26 PM PDT 24 553513284 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1214324492 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:18 PM PDT 24 437030832 ps
T39 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1893012516 Aug 05 05:26:16 PM PDT 24 Aug 05 05:26:23 PM PDT 24 4094332800 ps
T40 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1708316170 Aug 05 05:26:34 PM PDT 24 Aug 05 05:26:37 PM PDT 24 8264843201 ps
T296 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3049263443 Aug 05 05:26:49 PM PDT 24 Aug 05 05:26:50 PM PDT 24 466629103 ps
T297 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1866814617 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:53 PM PDT 24 480871683 ps
T81 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1526058136 Aug 05 05:27:01 PM PDT 24 Aug 05 05:27:05 PM PDT 24 1404703302 ps
T298 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4000502195 Aug 05 05:26:21 PM PDT 24 Aug 05 05:26:23 PM PDT 24 364888617 ps
T299 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4075931521 Aug 05 05:26:38 PM PDT 24 Aug 05 05:26:40 PM PDT 24 472336933 ps
T198 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3867833114 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:27 PM PDT 24 4051300545 ps
T82 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1487716380 Aug 05 05:26:54 PM PDT 24 Aug 05 05:26:56 PM PDT 24 941546335 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2028408422 Aug 05 05:26:44 PM PDT 24 Aug 05 05:26:45 PM PDT 24 410402382 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.911720798 Aug 05 05:26:21 PM PDT 24 Aug 05 05:26:22 PM PDT 24 270172368 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3650874814 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 473864068 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1058162774 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:44 PM PDT 24 555371809 ps
T304 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2753169391 Aug 05 05:26:54 PM PDT 24 Aug 05 05:26:55 PM PDT 24 270037233 ps
T305 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3931692618 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:39 PM PDT 24 3900854234 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.32468437 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:53 PM PDT 24 435276249 ps
T83 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3938391947 Aug 05 05:26:37 PM PDT 24 Aug 05 05:26:39 PM PDT 24 2098834772 ps
T84 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.348519012 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 1260920217 ps
T307 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1867388698 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 315979267 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2718058851 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:25 PM PDT 24 544464145 ps
T309 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2624377856 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:54 PM PDT 24 448932185 ps
T310 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.204291850 Aug 05 05:26:38 PM PDT 24 Aug 05 05:26:39 PM PDT 24 405659605 ps
T311 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3997338351 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 282660078 ps
T312 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3189322680 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:25 PM PDT 24 365885345 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.290301515 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:19 PM PDT 24 323584216 ps
T66 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4199114613 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:36 PM PDT 24 385319318 ps
T314 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3938137308 Aug 05 05:26:56 PM PDT 24 Aug 05 05:26:57 PM PDT 24 354286475 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3402630947 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:20 PM PDT 24 1185245440 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2057550188 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 515931511 ps
T316 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.863774897 Aug 05 05:26:50 PM PDT 24 Aug 05 05:26:51 PM PDT 24 417231017 ps
T317 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3006796336 Aug 05 05:26:28 PM PDT 24 Aug 05 05:26:37 PM PDT 24 8189687428 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.9192486 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:44 PM PDT 24 535315785 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2616956536 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:19 PM PDT 24 375702710 ps
T320 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3655680662 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 417139810 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1289402011 Aug 05 05:26:27 PM PDT 24 Aug 05 05:26:28 PM PDT 24 565486382 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2385544143 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:20 PM PDT 24 505055001 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3602959289 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 718428188 ps
T323 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.902483166 Aug 05 05:26:38 PM PDT 24 Aug 05 05:26:39 PM PDT 24 552073461 ps
T324 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.248845043 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 406006778 ps
T325 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2678795468 Aug 05 05:26:58 PM PDT 24 Aug 05 05:26:59 PM PDT 24 442500366 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3943560485 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:24 PM PDT 24 453185924 ps
T327 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4136521649 Aug 05 05:26:50 PM PDT 24 Aug 05 05:26:51 PM PDT 24 513896782 ps
T78 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4284168133 Aug 05 05:27:00 PM PDT 24 Aug 05 05:27:01 PM PDT 24 379356207 ps
T328 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3638380499 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:44 PM PDT 24 401215485 ps
T329 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2164223426 Aug 05 05:26:36 PM PDT 24 Aug 05 05:26:38 PM PDT 24 753607512 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4059121006 Aug 05 05:26:17 PM PDT 24 Aug 05 05:26:18 PM PDT 24 739869471 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4166058869 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:20 PM PDT 24 537373890 ps
T85 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.299468589 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:44 PM PDT 24 453218542 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2740796893 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 452222404 ps
T332 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1373949170 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 336044388 ps
T333 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1642357869 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 453374984 ps
T334 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.340567356 Aug 05 05:26:31 PM PDT 24 Aug 05 05:26:32 PM PDT 24 540963782 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3695773666 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:50 PM PDT 24 4243468859 ps
T336 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1841843681 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 358269497 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3370475881 Aug 05 05:26:39 PM PDT 24 Aug 05 05:26:40 PM PDT 24 348337205 ps
T79 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3063987689 Aug 05 05:26:32 PM PDT 24 Aug 05 05:26:33 PM PDT 24 378566288 ps
T86 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2827339536 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:27 PM PDT 24 1154969711 ps
T338 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.866261943 Aug 05 05:26:40 PM PDT 24 Aug 05 05:26:41 PM PDT 24 384888492 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3836312829 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:19 PM PDT 24 446252050 ps
T340 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2461945441 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:54 PM PDT 24 439658132 ps
T200 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2672195082 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:55 PM PDT 24 8184998473 ps
T341 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1851223452 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:44 PM PDT 24 1605775916 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4264503683 Aug 05 05:26:16 PM PDT 24 Aug 05 05:26:17 PM PDT 24 425942785 ps
T343 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1609449351 Aug 05 05:26:41 PM PDT 24 Aug 05 05:26:43 PM PDT 24 619402567 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.608281991 Aug 05 05:26:22 PM PDT 24 Aug 05 05:26:24 PM PDT 24 562652957 ps
T345 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.311029822 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 496960637 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1353524944 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:21 PM PDT 24 628537613 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.525803744 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:43 PM PDT 24 495576608 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1467816427 Aug 05 05:26:17 PM PDT 24 Aug 05 05:26:18 PM PDT 24 1263207845 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4007104166 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:25 PM PDT 24 323984102 ps
T201 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1091341805 Aug 05 05:26:21 PM PDT 24 Aug 05 05:26:24 PM PDT 24 4107034103 ps
T350 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1160050411 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 433029714 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1965005503 Aug 05 05:26:22 PM PDT 24 Aug 05 05:26:23 PM PDT 24 479824826 ps
T352 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4001375390 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 408697951 ps
T353 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3556542319 Aug 05 05:26:30 PM PDT 24 Aug 05 05:26:32 PM PDT 24 1373662507 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3977937212 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:30 PM PDT 24 9736863295 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1248337064 Aug 05 05:26:23 PM PDT 24 Aug 05 05:26:29 PM PDT 24 7201352830 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4071694514 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:44 PM PDT 24 413347020 ps
T356 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3952620884 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 465109605 ps
T357 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2682739386 Aug 05 05:26:41 PM PDT 24 Aug 05 05:26:45 PM PDT 24 8272360650 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2332437887 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 361711623 ps
T359 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.844182708 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 272359903 ps
T199 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2858469957 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:49 PM PDT 24 4293994868 ps
T360 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1474970999 Aug 05 05:26:50 PM PDT 24 Aug 05 05:26:51 PM PDT 24 408736408 ps
T361 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.402725381 Aug 05 05:26:33 PM PDT 24 Aug 05 05:26:35 PM PDT 24 440714078 ps
T362 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2925009707 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:45 PM PDT 24 512466454 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3805461510 Aug 05 05:26:42 PM PDT 24 Aug 05 05:26:49 PM PDT 24 4468009547 ps
T364 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.744399514 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 4174233319 ps
T365 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1520654345 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 492676456 ps
T366 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.643557015 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:23 PM PDT 24 8372981350 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.56068312 Aug 05 05:26:36 PM PDT 24 Aug 05 05:26:38 PM PDT 24 450446899 ps
T368 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.112846481 Aug 05 05:26:56 PM PDT 24 Aug 05 05:26:57 PM PDT 24 410577980 ps
T369 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4167695004 Aug 05 05:26:55 PM PDT 24 Aug 05 05:26:56 PM PDT 24 2288557488 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2075170178 Aug 05 05:26:15 PM PDT 24 Aug 05 05:26:16 PM PDT 24 1313499621 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2033581175 Aug 05 05:26:41 PM PDT 24 Aug 05 05:26:42 PM PDT 24 423089755 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1694133285 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:37 PM PDT 24 8323385658 ps
T373 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.534048335 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 388488174 ps
T374 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.790390005 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 400909085 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3672529267 Aug 05 05:26:41 PM PDT 24 Aug 05 05:26:42 PM PDT 24 1070298063 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.65809222 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:25 PM PDT 24 8586678345 ps
T377 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1286581159 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:44 PM PDT 24 479650652 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1410677037 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:21 PM PDT 24 501464916 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2373061812 Aug 05 05:26:29 PM PDT 24 Aug 05 05:26:30 PM PDT 24 319821534 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2772338883 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 337129294 ps
T381 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3043493909 Aug 05 05:26:49 PM PDT 24 Aug 05 05:26:49 PM PDT 24 513880395 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2019891290 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:31 PM PDT 24 4358812727 ps
T383 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.447112862 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:54 PM PDT 24 4139073072 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1090994415 Aug 05 05:26:29 PM PDT 24 Aug 05 05:26:40 PM PDT 24 6916536178 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3221303285 Aug 05 05:26:33 PM PDT 24 Aug 05 05:26:35 PM PDT 24 490870675 ps
T386 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3870327777 Aug 05 05:26:56 PM PDT 24 Aug 05 05:26:57 PM PDT 24 306116961 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3181242205 Aug 05 05:26:21 PM PDT 24 Aug 05 05:26:22 PM PDT 24 625934072 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2117690672 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 346842495 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4069169124 Aug 05 05:26:34 PM PDT 24 Aug 05 05:26:36 PM PDT 24 402463582 ps
T390 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2700967039 Aug 05 05:26:33 PM PDT 24 Aug 05 05:26:34 PM PDT 24 642632968 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2212586541 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:21 PM PDT 24 2562042765 ps
T392 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1397383500 Aug 05 05:26:34 PM PDT 24 Aug 05 05:26:35 PM PDT 24 506990638 ps
T393 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2198723000 Aug 05 05:26:51 PM PDT 24 Aug 05 05:26:52 PM PDT 24 430575157 ps
T394 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3259006656 Aug 05 05:26:32 PM PDT 24 Aug 05 05:26:34 PM PDT 24 1538587033 ps
T395 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4136491388 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:43 PM PDT 24 333102895 ps
T396 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3001772516 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:39 PM PDT 24 4574531915 ps
T397 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2443276590 Aug 05 05:26:32 PM PDT 24 Aug 05 05:26:33 PM PDT 24 328720052 ps
T398 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3909825370 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 3012075104 ps
T399 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3404515615 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:31 PM PDT 24 4233593026 ps
T400 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1184836621 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:36 PM PDT 24 1790087215 ps
T401 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1411781850 Aug 05 05:26:57 PM PDT 24 Aug 05 05:26:58 PM PDT 24 985917634 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3249368778 Aug 05 05:26:19 PM PDT 24 Aug 05 05:26:20 PM PDT 24 414459162 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2778801183 Aug 05 05:26:24 PM PDT 24 Aug 05 05:26:25 PM PDT 24 847533204 ps
T403 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1799813758 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:54 PM PDT 24 346956856 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1180674409 Aug 05 05:26:34 PM PDT 24 Aug 05 05:26:34 PM PDT 24 380040958 ps
T405 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4178133998 Aug 05 05:26:27 PM PDT 24 Aug 05 05:26:28 PM PDT 24 427091115 ps
T406 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1323150605 Aug 05 05:26:50 PM PDT 24 Aug 05 05:26:50 PM PDT 24 366272081 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2066511852 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:37 PM PDT 24 511884372 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.53593885 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:21 PM PDT 24 1196484150 ps
T409 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2059044264 Aug 05 05:26:43 PM PDT 24 Aug 05 05:26:45 PM PDT 24 324705446 ps
T410 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1600170456 Aug 05 05:26:52 PM PDT 24 Aug 05 05:26:53 PM PDT 24 459629091 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2032985283 Aug 05 05:26:26 PM PDT 24 Aug 05 05:26:29 PM PDT 24 513791649 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2655984578 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:27 PM PDT 24 821206319 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4183642130 Aug 05 05:26:21 PM PDT 24 Aug 05 05:26:22 PM PDT 24 548257184 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1416970947 Aug 05 05:26:28 PM PDT 24 Aug 05 05:26:28 PM PDT 24 519156052 ps
T415 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1359279174 Aug 05 05:26:35 PM PDT 24 Aug 05 05:26:37 PM PDT 24 2160415112 ps
T416 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4196720358 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:27 PM PDT 24 615980887 ps
T417 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3363721025 Aug 05 05:26:53 PM PDT 24 Aug 05 05:26:55 PM PDT 24 588174438 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1345047493 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 271324878 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1070657164 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:21 PM PDT 24 486773022 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1492365753 Aug 05 05:26:37 PM PDT 24 Aug 05 05:26:39 PM PDT 24 809517464 ps
T421 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.656251593 Aug 05 05:26:20 PM PDT 24 Aug 05 05:26:40 PM PDT 24 14311066297 ps
T72 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1802469804 Aug 05 05:26:40 PM PDT 24 Aug 05 05:26:41 PM PDT 24 444407045 ps
T422 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.371630955 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 1377000972 ps
T423 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2706985235 Aug 05 05:26:25 PM PDT 24 Aug 05 05:26:26 PM PDT 24 566010259 ps
T424 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1406070197 Aug 05 05:26:18 PM PDT 24 Aug 05 05:26:18 PM PDT 24 401345835 ps

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2176704991
Short name T5
Test name
Test status
Simulation time 165819714888 ps
CPU time 465.9 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:55:33 PM PDT 24
Peak memory 211984 kb
Host smart-22db76b3-fdf5-4e02-b900-222d75d87735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176704991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2176704991
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4190867582
Short name T15
Test name
Test status
Simulation time 404166607455 ps
CPU time 375.64 seconds
Started Aug 05 05:47:41 PM PDT 24
Finished Aug 05 05:53:57 PM PDT 24
Peak memory 201632 kb
Host smart-663ee521-765f-4bea-96ad-3bfa2eb3ab40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190867582 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4190867582
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3256141453
Short name T36
Test name
Test status
Simulation time 7867828626 ps
CPU time 12.72 seconds
Started Aug 05 05:26:39 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 198400 kb
Host smart-bbe488d5-3924-438c-b107-952907d4b020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256141453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3256141453
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4237565952
Short name T96
Test name
Test status
Simulation time 286455938803 ps
CPU time 562.23 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:57:29 PM PDT 24
Peak memory 212572 kb
Host smart-b71bb361-8bac-4ebd-a220-d37cf984a371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237565952 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4237565952
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.434212469
Short name T144
Test name
Test status
Simulation time 81873676144 ps
CPU time 321.16 seconds
Started Aug 05 05:47:59 PM PDT 24
Finished Aug 05 05:53:20 PM PDT 24
Peak memory 206668 kb
Host smart-b0f554a4-9c5b-45f3-bc6d-299d1f74a26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434212469 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.434212469
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2232542227
Short name T62
Test name
Test status
Simulation time 45758599023 ps
CPU time 493.26 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:56:36 PM PDT 24
Peak memory 209404 kb
Host smart-70950f81-ff24-4495-b626-7d01fce6607c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232542227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2232542227
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2699667364
Short name T35
Test name
Test status
Simulation time 145636630794 ps
CPU time 209.9 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:51:44 PM PDT 24
Peak memory 192468 kb
Host smart-c3d523f6-3549-4aa1-9dc0-60a070808726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699667364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2699667364
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.373441213
Short name T90
Test name
Test status
Simulation time 163947606517 ps
CPU time 402.59 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:54:55 PM PDT 24
Peak memory 202808 kb
Host smart-07761253-306e-4c75-aff7-58f1a6f79047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373441213 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.373441213
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3940054955
Short name T132
Test name
Test status
Simulation time 37253404818 ps
CPU time 387.45 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:54:41 PM PDT 24
Peak memory 199224 kb
Host smart-9449157b-76d3-4658-a9bf-824aa583b034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940054955 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3940054955
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4072242953
Short name T10
Test name
Test status
Simulation time 361281284 ps
CPU time 0.77 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 191844 kb
Host smart-c801cacd-c8f3-4415-a6ce-3df68fe2e125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072242953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4072242953
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1606146608
Short name T93
Test name
Test status
Simulation time 777241056708 ps
CPU time 887.95 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 06:02:28 PM PDT 24
Peak memory 214864 kb
Host smart-b66c870e-e3e9-49e1-ba7f-1e45ab82b034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606146608 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1606146608
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2272606690
Short name T16
Test name
Test status
Simulation time 7856599792 ps
CPU time 12.51 seconds
Started Aug 05 05:47:50 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 215788 kb
Host smart-9d96935d-def3-4d4e-b1e8-c87b5b52a184
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272606690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2272606690
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1722635598
Short name T120
Test name
Test status
Simulation time 206788550097 ps
CPU time 567.78 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:57:38 PM PDT 24
Peak memory 206716 kb
Host smart-b93115a8-143f-4b27-843b-3bb6b32856e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722635598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1722635598
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.176971806
Short name T34
Test name
Test status
Simulation time 490235140167 ps
CPU time 556.64 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:57:12 PM PDT 24
Peak memory 204640 kb
Host smart-fa05d804-bde2-4eba-aac0-f70ed51fbbc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176971806 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.176971806
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2546118158
Short name T91
Test name
Test status
Simulation time 84216659541 ps
CPU time 668.48 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:59:25 PM PDT 24
Peak memory 212672 kb
Host smart-633dcdf5-4546-4518-8477-20fdb085e668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546118158 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2546118158
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2726215051
Short name T26
Test name
Test status
Simulation time 67917024770 ps
CPU time 127.32 seconds
Started Aug 05 05:47:52 PM PDT 24
Finished Aug 05 05:50:00 PM PDT 24
Peak memory 198444 kb
Host smart-a029040e-ad33-4d00-bb1e-9ee03eae7ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726215051 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2726215051
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2077855701
Short name T105
Test name
Test status
Simulation time 80338393043 ps
CPU time 34.61 seconds
Started Aug 05 05:47:34 PM PDT 24
Finished Aug 05 05:48:09 PM PDT 24
Peak memory 192504 kb
Host smart-9ca527c3-a9cc-4560-98a0-517559ba0af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077855701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2077855701
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4025246350
Short name T94
Test name
Test status
Simulation time 221962215614 ps
CPU time 837.87 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 06:01:38 PM PDT 24
Peak memory 207816 kb
Host smart-3227fb38-6d69-4f23-aee9-50f540c0d678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025246350 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4025246350
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1757292676
Short name T73
Test name
Test status
Simulation time 75642956369 ps
CPU time 373.32 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:54:09 PM PDT 24
Peak memory 201244 kb
Host smart-229d3e82-93e5-4cd1-ab4e-e82a9e4f3476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757292676 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1757292676
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4220745154
Short name T148
Test name
Test status
Simulation time 136385860097 ps
CPU time 332.96 seconds
Started Aug 05 05:47:49 PM PDT 24
Finished Aug 05 05:53:22 PM PDT 24
Peak memory 201624 kb
Host smart-529f72c7-b924-481f-a662-43867a88f3f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220745154 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4220745154
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3358028829
Short name T139
Test name
Test status
Simulation time 153709851812 ps
CPU time 52.6 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 198228 kb
Host smart-3658c308-1d21-4b72-9c26-fb245a6a9f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358028829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3358028829
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3082021993
Short name T104
Test name
Test status
Simulation time 311628751489 ps
CPU time 79.24 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:49:32 PM PDT 24
Peak memory 192500 kb
Host smart-1ce52ba1-9bfd-4b62-9032-5092ad967fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082021993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3082021993
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3718868586
Short name T126
Test name
Test status
Simulation time 146641878528 ps
CPU time 62.81 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 191888 kb
Host smart-ba0c92ac-2298-424d-bd66-87dbde7660b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718868586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3718868586
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.554520613
Short name T117
Test name
Test status
Simulation time 97335242044 ps
CPU time 32.81 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 192392 kb
Host smart-7678633f-0f68-42d3-aa07-217e910c4df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554520613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.554520613
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3572220789
Short name T74
Test name
Test status
Simulation time 458995093384 ps
CPU time 591.9 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:58:10 PM PDT 24
Peak memory 214856 kb
Host smart-9ce5e14e-5541-4eca-b495-19dc37a780c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572220789 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3572220789
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3141112315
Short name T8
Test name
Test status
Simulation time 76322806840 ps
CPU time 837.42 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 06:02:14 PM PDT 24
Peak memory 207796 kb
Host smart-278fc414-bbce-4ba8-b752-f776fb4ce592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141112315 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3141112315
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2019815926
Short name T111
Test name
Test status
Simulation time 354045645643 ps
CPU time 132.15 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:50:18 PM PDT 24
Peak memory 193012 kb
Host smart-c74b9317-6a7f-4856-b8c7-45ed1d031645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019815926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2019815926
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1688782359
Short name T122
Test name
Test status
Simulation time 35862595155 ps
CPU time 13.69 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 192892 kb
Host smart-6c0f05eb-971c-4e0c-873c-b4e697baa515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688782359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1688782359
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2675872052
Short name T63
Test name
Test status
Simulation time 4708397695 ps
CPU time 3.77 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 196064 kb
Host smart-eb3e4e85-3b23-488c-a074-ba1ba8a94c45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675872052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2675872052
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1212027969
Short name T33
Test name
Test status
Simulation time 22674062924 ps
CPU time 170.79 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:50:45 PM PDT 24
Peak memory 198444 kb
Host smart-628e59d3-a2c3-4476-a546-7af4a7c3298f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212027969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1212027969
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1413913420
Short name T44
Test name
Test status
Simulation time 99686379080 ps
CPU time 374.87 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:54:21 PM PDT 24
Peak memory 210124 kb
Host smart-3d1ac3ad-6061-4a44-a476-691739c7886d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413913420 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1413913420
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.39078869
Short name T102
Test name
Test status
Simulation time 506104536711 ps
CPU time 639.82 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:58:45 PM PDT 24
Peak memory 192984 kb
Host smart-d6db1fec-8909-4aaf-9afe-e15f5b3bf4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39078869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_al
l.39078869
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2478391288
Short name T149
Test name
Test status
Simulation time 182106096130 ps
CPU time 243.59 seconds
Started Aug 05 05:47:57 PM PDT 24
Finished Aug 05 05:52:01 PM PDT 24
Peak memory 191876 kb
Host smart-a21b9dea-07c2-440c-8c8c-1c92746b3992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478391288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2478391288
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1941689563
Short name T95
Test name
Test status
Simulation time 73112773011 ps
CPU time 451.22 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:55:07 PM PDT 24
Peak memory 209328 kb
Host smart-5d88ad89-6cde-4e73-867c-9568a062d850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941689563 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1941689563
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1784496053
Short name T110
Test name
Test status
Simulation time 127003069713 ps
CPU time 40.87 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 192424 kb
Host smart-dc181087-42b6-4003-8180-908445fd529a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784496053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1784496053
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.63114745
Short name T130
Test name
Test status
Simulation time 41237469316 ps
CPU time 29.99 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 191920 kb
Host smart-8fa01f41-8f2d-43e5-bfff-699df0f35237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63114745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_al
l.63114745
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3171411218
Short name T135
Test name
Test status
Simulation time 62596303097 ps
CPU time 46.58 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 198212 kb
Host smart-5d74b1f9-343c-423d-9d3f-6a8b4a573753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171411218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3171411218
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3606617935
Short name T13
Test name
Test status
Simulation time 173669865682 ps
CPU time 87.12 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:49:49 PM PDT 24
Peak memory 192912 kb
Host smart-268f4d4b-f116-4fd9-b041-9ff1364b3c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606617935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3606617935
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3125531479
Short name T116
Test name
Test status
Simulation time 91440688469 ps
CPU time 15.9 seconds
Started Aug 05 05:48:03 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 198268 kb
Host smart-f4fd9eab-8b36-4dbb-bf38-12ed0e25577a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125531479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3125531479
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1090934671
Short name T142
Test name
Test status
Simulation time 34906807228 ps
CPU time 12.56 seconds
Started Aug 05 05:48:27 PM PDT 24
Finished Aug 05 05:48:39 PM PDT 24
Peak memory 198228 kb
Host smart-bc4e4ee4-9cb4-4a32-9439-6ca28b65c353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090934671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1090934671
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1324078552
Short name T154
Test name
Test status
Simulation time 163165200839 ps
CPU time 204.31 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:51:07 PM PDT 24
Peak memory 200364 kb
Host smart-66334acd-c44e-413b-a8ef-d3cec57a78e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324078552 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1324078552
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2218317706
Short name T109
Test name
Test status
Simulation time 161345197141 ps
CPU time 85.92 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:49:36 PM PDT 24
Peak memory 193000 kb
Host smart-aeb6da2a-c37e-4251-906f-d90fd23f4ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218317706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2218317706
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3147301009
Short name T128
Test name
Test status
Simulation time 253389218722 ps
CPU time 89.5 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 191856 kb
Host smart-983d664a-50f9-424a-8607-7898484393dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147301009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3147301009
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2521474929
Short name T150
Test name
Test status
Simulation time 63876297631 ps
CPU time 25.64 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 192880 kb
Host smart-d465b4a1-3043-4061-b439-05f32b62409f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521474929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2521474929
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.599227333
Short name T166
Test name
Test status
Simulation time 164318612463 ps
CPU time 407.99 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:54:28 PM PDT 24
Peak memory 202484 kb
Host smart-33ca273b-6a35-441c-8951-e36f88d266eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599227333 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.599227333
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3524911491
Short name T114
Test name
Test status
Simulation time 248693238187 ps
CPU time 262.84 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:52:14 PM PDT 24
Peak memory 198556 kb
Host smart-7b8b49d7-e333-4dfe-97a6-a5bdd73ef3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524911491 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3524911491
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3234395918
Short name T125
Test name
Test status
Simulation time 373500277940 ps
CPU time 384.34 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:54:13 PM PDT 24
Peak memory 198256 kb
Host smart-4f9d7048-c1de-409c-894b-6ab8bbd7c62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234395918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3234395918
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1858506929
Short name T161
Test name
Test status
Simulation time 30307371988 ps
CPU time 25.71 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 191904 kb
Host smart-9e0f3178-81a6-40f0-aee3-63d60cb15aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858506929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1858506929
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.9130123
Short name T47
Test name
Test status
Simulation time 20838556571 ps
CPU time 207.39 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:51:57 PM PDT 24
Peak memory 198504 kb
Host smart-ebb9473c-a894-4bc3-8768-d0a75e8f56f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9130123 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.9130123
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2487976624
Short name T107
Test name
Test status
Simulation time 8541089911 ps
CPU time 68.13 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 198576 kb
Host smart-82aa36b9-1681-4bdf-a24e-466f98d92267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487976624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2487976624
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3168419387
Short name T151
Test name
Test status
Simulation time 149490267396 ps
CPU time 55.15 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 198272 kb
Host smart-f6e51b59-02af-4afc-b511-2c7d3c3630ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168419387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3168419387
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1358357876
Short name T138
Test name
Test status
Simulation time 73404878875 ps
CPU time 11.34 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 198236 kb
Host smart-371a2637-f77d-48d2-ae79-6539926d8cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358357876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1358357876
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.137469142
Short name T28
Test name
Test status
Simulation time 79751324101 ps
CPU time 109.04 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 191912 kb
Host smart-bead58bc-87e5-4893-b183-062519c5651c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137469142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.137469142
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3143852373
Short name T45
Test name
Test status
Simulation time 99791415195 ps
CPU time 244.41 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:52:29 PM PDT 24
Peak memory 200740 kb
Host smart-e3007876-6a3c-44cb-b04a-e7796dfd8df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143852373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3143852373
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2209509780
Short name T145
Test name
Test status
Simulation time 404278384617 ps
CPU time 561.39 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:57:27 PM PDT 24
Peak memory 192988 kb
Host smart-3c82c63f-f1ea-4ac5-8ebd-3f32026e8a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209509780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2209509780
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.886403381
Short name T106
Test name
Test status
Simulation time 152132120309 ps
CPU time 243.45 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:52:09 PM PDT 24
Peak memory 208864 kb
Host smart-76a8d045-59d4-4c3e-91d9-042c52c9c3e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886403381 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.886403381
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.545486462
Short name T97
Test name
Test status
Simulation time 79876380703 ps
CPU time 169.2 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:50:43 PM PDT 24
Peak memory 207036 kb
Host smart-29641bc9-027b-4b35-9aec-bc6fc80aecb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545486462 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.545486462
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2422916800
Short name T136
Test name
Test status
Simulation time 138480732211 ps
CPU time 176.42 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:51:14 PM PDT 24
Peak memory 198236 kb
Host smart-eddd14b0-c2ed-4c85-adf2-cab0ba9a3331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422916800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2422916800
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2005042625
Short name T37
Test name
Test status
Simulation time 1884935288 ps
CPU time 2.18 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 193536 kb
Host smart-5b027f64-b02d-4934-9d63-e1966ae043c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005042625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2005042625
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.244767206
Short name T24
Test name
Test status
Simulation time 84736382325 ps
CPU time 920.6 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 06:03:17 PM PDT 24
Peak memory 214932 kb
Host smart-53d945f6-d14d-4ed1-908e-150315a5c81c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244767206 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.244767206
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3442533905
Short name T19
Test name
Test status
Simulation time 140332679827 ps
CPU time 24.17 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 198252 kb
Host smart-03946801-632d-4c1c-92dd-efb5fafd8556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442533905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3442533905
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1508416352
Short name T23
Test name
Test status
Simulation time 103914201174 ps
CPU time 576.66 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:57:55 PM PDT 24
Peak memory 214624 kb
Host smart-e9502433-5234-4bec-abc7-9e791fb38c75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508416352 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1508416352
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1965391584
Short name T137
Test name
Test status
Simulation time 351911665566 ps
CPU time 272.75 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:52:27 PM PDT 24
Peak memory 193096 kb
Host smart-2c5ad723-3396-4337-a64a-d728c36e74e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965391584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1965391584
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.549896092
Short name T58
Test name
Test status
Simulation time 340549782810 ps
CPU time 414.25 seconds
Started Aug 05 05:47:49 PM PDT 24
Finished Aug 05 05:54:44 PM PDT 24
Peak memory 191912 kb
Host smart-23ac084d-64d6-467f-bad9-7d0bf5dae38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549896092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.549896092
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2964711428
Short name T124
Test name
Test status
Simulation time 262611331137 ps
CPU time 370.41 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:54:05 PM PDT 24
Peak memory 192896 kb
Host smart-7cb0e3c2-1cde-4cf3-8152-5d6bc752ddb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964711428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2964711428
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1766263174
Short name T141
Test name
Test status
Simulation time 50555950906 ps
CPU time 52.71 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 191872 kb
Host smart-c7999385-4dcb-4cd8-97fd-12358ada4e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766263174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1766263174
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2790577177
Short name T108
Test name
Test status
Simulation time 391768272 ps
CPU time 0.77 seconds
Started Aug 05 05:48:11 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 196744 kb
Host smart-f73b2c2d-7780-4cfb-94b3-62c3712bd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790577177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2790577177
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1080174286
Short name T134
Test name
Test status
Simulation time 408959680 ps
CPU time 0.94 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:47:43 PM PDT 24
Peak memory 196716 kb
Host smart-72a73e3a-d021-4e1a-9900-69006bd9248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080174286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1080174286
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2554711039
Short name T27
Test name
Test status
Simulation time 5479087882 ps
CPU time 3.39 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:47:58 PM PDT 24
Peak memory 191888 kb
Host smart-b23db546-71fd-4b22-891e-67a03e8a45cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554711039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2554711039
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3652983249
Short name T178
Test name
Test status
Simulation time 41782981343 ps
CPU time 419.91 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:54:52 PM PDT 24
Peak memory 206656 kb
Host smart-54a414c7-d251-41da-8a4a-d192e46644ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652983249 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3652983249
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.848617873
Short name T123
Test name
Test status
Simulation time 66902048013 ps
CPU time 174.12 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:50:49 PM PDT 24
Peak memory 214016 kb
Host smart-9eb5e892-f86d-47a4-a0df-0a9ab9dcdf18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848617873 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.848617873
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.162503290
Short name T121
Test name
Test status
Simulation time 423132706 ps
CPU time 0.7 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 196656 kb
Host smart-630d5584-9d91-459f-b25c-081e06199c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162503290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.162503290
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.636835022
Short name T143
Test name
Test status
Simulation time 167879376079 ps
CPU time 65.72 seconds
Started Aug 05 05:47:38 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 191916 kb
Host smart-db266e17-a57b-4f9b-9011-e3db0b688944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636835022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.636835022
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3258847852
Short name T165
Test name
Test status
Simulation time 157230196430 ps
CPU time 228.14 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:51:50 PM PDT 24
Peak memory 191892 kb
Host smart-ab5fb9a1-ec91-4fe9-aa3e-54a81e62f99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258847852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3258847852
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.956313969
Short name T127
Test name
Test status
Simulation time 503411508 ps
CPU time 1.3 seconds
Started Aug 05 05:48:11 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 196652 kb
Host smart-0811bb32-5827-471a-9f74-f72ddd704964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956313969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.956313969
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4274782550
Short name T156
Test name
Test status
Simulation time 526537174 ps
CPU time 1.46 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 196744 kb
Host smart-379ebbf7-4c05-42b9-98bf-d687f8ffc0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274782550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4274782550
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2880622973
Short name T163
Test name
Test status
Simulation time 411274513 ps
CPU time 1.15 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:15 PM PDT 24
Peak memory 196728 kb
Host smart-ff4a169c-e517-4a58-9f45-a0b2043a8d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880622973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2880622973
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1109567023
Short name T159
Test name
Test status
Simulation time 592075604 ps
CPU time 0.82 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 196708 kb
Host smart-14358046-8013-4e7c-8fed-c6ad8e49efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109567023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1109567023
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.58758054
Short name T119
Test name
Test status
Simulation time 505546709 ps
CPU time 1.3 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 196752 kb
Host smart-01619124-4648-48b5-9739-da47f53052cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58758054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.58758054
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2752727916
Short name T177
Test name
Test status
Simulation time 545576877643 ps
CPU time 727.42 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 192976 kb
Host smart-8f5c3533-6757-429d-80e5-9d6fa3736f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752727916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2752727916
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3706629041
Short name T146
Test name
Test status
Simulation time 375588629 ps
CPU time 0.7 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:48:14 PM PDT 24
Peak memory 196672 kb
Host smart-3fe87b50-eee5-464d-a2ad-d51837782292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706629041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3706629041
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2165131265
Short name T162
Test name
Test status
Simulation time 562795133 ps
CPU time 1.47 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:47:55 PM PDT 24
Peak memory 196600 kb
Host smart-df357ddc-327b-47c7-a6cb-c939e77e00de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165131265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2165131265
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3642336602
Short name T98
Test name
Test status
Simulation time 55923397098 ps
CPU time 251.85 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:52:05 PM PDT 24
Peak memory 206636 kb
Host smart-abf7d169-385d-44f6-a84f-5638293cd507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642336602 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3642336602
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.544610344
Short name T46
Test name
Test status
Simulation time 27215569665 ps
CPU time 192.46 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:51:06 PM PDT 24
Peak memory 198496 kb
Host smart-26cbe622-8ee5-44c6-bda2-111637f1becc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544610344 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.544610344
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2137258243
Short name T115
Test name
Test status
Simulation time 265507743176 ps
CPU time 109.63 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 192924 kb
Host smart-1398c4e2-e12b-444e-88fe-8c81771ddd48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137258243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2137258243
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2373309293
Short name T147
Test name
Test status
Simulation time 580356538 ps
CPU time 1.38 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 196652 kb
Host smart-ae2ad1f5-9a2a-438c-952b-d417cae99e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373309293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2373309293
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1935437855
Short name T29
Test name
Test status
Simulation time 474448161 ps
CPU time 1.22 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 196632 kb
Host smart-72e6c4fa-f486-483e-9d3a-039617392b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935437855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1935437855
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.732174220
Short name T174
Test name
Test status
Simulation time 75790114318 ps
CPU time 421.62 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:55:16 PM PDT 24
Peak memory 210440 kb
Host smart-dbcb5641-2662-4af3-8db6-d2c3bb2d8b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732174220 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.732174220
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3860306569
Short name T101
Test name
Test status
Simulation time 417523331 ps
CPU time 0.94 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:47:48 PM PDT 24
Peak memory 196744 kb
Host smart-585cc159-5872-47b4-b85e-07e80d6cf556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860306569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3860306569
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3755744380
Short name T155
Test name
Test status
Simulation time 3096002030 ps
CPU time 3.26 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:43 PM PDT 24
Peak memory 191904 kb
Host smart-c570c469-d46f-42ab-83e3-57cac7cfe454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755744380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3755744380
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3996831400
Short name T152
Test name
Test status
Simulation time 379392565 ps
CPU time 1.13 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:47:54 PM PDT 24
Peak memory 196744 kb
Host smart-c2271464-cb5e-4606-9c69-5822c3504d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996831400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3996831400
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2037985321
Short name T160
Test name
Test status
Simulation time 214855407668 ps
CPU time 51.04 seconds
Started Aug 05 05:47:58 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 191892 kb
Host smart-bb04d1af-b37a-4516-ad3f-c44c6fc93165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037985321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2037985321
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2704677724
Short name T131
Test name
Test status
Simulation time 279836241286 ps
CPU time 107.89 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:49:57 PM PDT 24
Peak memory 192684 kb
Host smart-557199ed-f2a7-4a46-9f37-7baa057fac7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704677724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2704677724
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1093999464
Short name T153
Test name
Test status
Simulation time 488336813 ps
CPU time 0.77 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 196656 kb
Host smart-dbc3952b-ca35-41f4-a1fa-d61f5577591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093999464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1093999464
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.744294197
Short name T189
Test name
Test status
Simulation time 411739871708 ps
CPU time 585.18 seconds
Started Aug 05 05:47:49 PM PDT 24
Finished Aug 05 05:57:34 PM PDT 24
Peak memory 192988 kb
Host smart-e0f9cc2c-5e55-4ead-9f1e-3257c2009830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744294197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.744294197
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4128898410
Short name T31
Test name
Test status
Simulation time 378484270 ps
CPU time 1.25 seconds
Started Aug 05 05:47:50 PM PDT 24
Finished Aug 05 05:47:51 PM PDT 24
Peak memory 196776 kb
Host smart-cbb94d9b-592b-48aa-9c7f-501a66527f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128898410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4128898410
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1433006598
Short name T167
Test name
Test status
Simulation time 48519422802 ps
CPU time 256.87 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:52:10 PM PDT 24
Peak memory 214644 kb
Host smart-699b6875-bab5-4a11-b80c-2146806725ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433006598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1433006598
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1863833438
Short name T32
Test name
Test status
Simulation time 591541184 ps
CPU time 1.02 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:47:48 PM PDT 24
Peak memory 196756 kb
Host smart-adda7a08-b13a-4cb4-aa61-da88c0c17143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863833438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1863833438
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2709188680
Short name T14
Test name
Test status
Simulation time 542200413656 ps
CPU time 773.44 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 06:00:41 PM PDT 24
Peak memory 192876 kb
Host smart-02887cca-109b-49d9-93e5-02d4535ddc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709188680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2709188680
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4217651129
Short name T157
Test name
Test status
Simulation time 124844042063 ps
CPU time 47.5 seconds
Started Aug 05 05:47:52 PM PDT 24
Finished Aug 05 05:48:40 PM PDT 24
Peak memory 191980 kb
Host smart-08074d0c-c1ea-4f16-b42f-f7e01bfc4c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217651129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4217651129
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1152724761
Short name T112
Test name
Test status
Simulation time 447439441 ps
CPU time 1.18 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 196640 kb
Host smart-56575b16-b8b6-4a0c-b7af-fc16208a4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152724761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1152724761
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4087869034
Short name T52
Test name
Test status
Simulation time 495279520 ps
CPU time 0.75 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:48:06 PM PDT 24
Peak memory 196584 kb
Host smart-761c08a7-e8b8-4dbb-b3ad-1f6367e0cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087869034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4087869034
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1540367553
Short name T129
Test name
Test status
Simulation time 573322276 ps
CPU time 0.97 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 196720 kb
Host smart-af24d18d-9d5e-4cd4-9fba-933d05bcc0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540367553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1540367553
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1543175431
Short name T194
Test name
Test status
Simulation time 518876036 ps
CPU time 1.32 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 196640 kb
Host smart-154385bf-f3a9-4581-b0d0-a57e29648c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543175431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1543175431
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1682445677
Short name T186
Test name
Test status
Simulation time 508413522 ps
CPU time 0.97 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:48:10 PM PDT 24
Peak memory 196648 kb
Host smart-f8efbbaa-da01-408e-af36-44452e9a23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682445677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1682445677
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3787949463
Short name T171
Test name
Test status
Simulation time 123326210277 ps
CPU time 198.49 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:51:14 PM PDT 24
Peak memory 191896 kb
Host smart-cae16904-2a4b-4d5f-aba5-5051e917767d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787949463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3787949463
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3005208267
Short name T169
Test name
Test status
Simulation time 406929235670 ps
CPU time 168.21 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:50:27 PM PDT 24
Peak memory 192920 kb
Host smart-d49fc651-a9ad-4482-b999-d84169e13aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005208267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3005208267
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2565686225
Short name T158
Test name
Test status
Simulation time 10410630555 ps
CPU time 32.67 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:48:15 PM PDT 24
Peak memory 206688 kb
Host smart-b3caccae-a8fb-46f2-9393-61d721f419c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565686225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2565686225
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3255754614
Short name T181
Test name
Test status
Simulation time 87574117347 ps
CPU time 14.07 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 192068 kb
Host smart-1eddd4da-2e6e-476e-a5b9-9d8294cb790d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255754614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3255754614
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2614938632
Short name T56
Test name
Test status
Simulation time 98281944497 ps
CPU time 141.03 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:50:21 PM PDT 24
Peak memory 191896 kb
Host smart-4124a9a1-0e78-42ab-beae-9a70e0af95b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614938632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2614938632
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3481377785
Short name T103
Test name
Test status
Simulation time 389278680 ps
CPU time 0.82 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 196676 kb
Host smart-8fd074dd-6ea8-4c4e-bcf5-8e649413462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481377785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3481377785
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4183278977
Short name T118
Test name
Test status
Simulation time 459019987 ps
CPU time 0.73 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 196664 kb
Host smart-c1ac68cd-ca31-4038-a693-cf20fcf2e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183278977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4183278977
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2858469957
Short name T199
Test name
Test status
Simulation time 4293994868 ps
CPU time 7.33 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:49 PM PDT 24
Peak memory 198296 kb
Host smart-66d25a74-de31-4bd2-813e-ba06fbbcbdce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858469957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2858469957
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4023697259
Short name T50
Test name
Test status
Simulation time 507037248 ps
CPU time 0.98 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:47:38 PM PDT 24
Peak memory 196732 kb
Host smart-9ec0e9e8-0b35-48de-b530-2c1ee5ab4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023697259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4023697259
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3826996007
Short name T43
Test name
Test status
Simulation time 17636802576 ps
CPU time 51.59 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 206716 kb
Host smart-b7d57143-e1c2-4015-ae31-5dc8d7bd4fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826996007 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3826996007
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3969379980
Short name T9
Test name
Test status
Simulation time 483904450 ps
CPU time 0.73 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 196724 kb
Host smart-b15f9254-f227-44a2-aa30-07d6fc6b1f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969379980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3969379980
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3073251456
Short name T77
Test name
Test status
Simulation time 381466245 ps
CPU time 1.18 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:47:54 PM PDT 24
Peak memory 196728 kb
Host smart-fee2f69f-ff9e-4ce3-b294-bce0fd159aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073251456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3073251456
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4170523410
Short name T183
Test name
Test status
Simulation time 586871411 ps
CPU time 1.51 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:57 PM PDT 24
Peak memory 196564 kb
Host smart-f88330c5-cda6-422d-aed5-4142faa4e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170523410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4170523410
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.370065499
Short name T197
Test name
Test status
Simulation time 492458925 ps
CPU time 0.77 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:47:43 PM PDT 24
Peak memory 196700 kb
Host smart-ea0a0781-c04a-48fa-815e-0603b5202321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370065499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.370065499
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2343309716
Short name T176
Test name
Test status
Simulation time 34501825087 ps
CPU time 50.06 seconds
Started Aug 05 05:47:42 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 191896 kb
Host smart-10794d3d-2933-44db-8e33-f90c77b7e8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343309716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2343309716
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3316998094
Short name T173
Test name
Test status
Simulation time 410378096123 ps
CPU time 647.03 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:58:41 PM PDT 24
Peak memory 192628 kb
Host smart-fd1b18d7-f893-42c1-b47c-649ac689fa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316998094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3316998094
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2484231999
Short name T191
Test name
Test status
Simulation time 594855371 ps
CPU time 0.8 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:48:01 PM PDT 24
Peak memory 196724 kb
Host smart-a0319855-6203-4165-ae0d-61980c1138da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484231999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2484231999
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3671198537
Short name T59
Test name
Test status
Simulation time 635697035 ps
CPU time 1.01 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:09 PM PDT 24
Peak memory 196628 kb
Host smart-5b4d742b-a23b-407f-9407-453041b2f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671198537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3671198537
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2875077731
Short name T140
Test name
Test status
Simulation time 417329941 ps
CPU time 1.16 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 196660 kb
Host smart-a7937051-6474-4fcf-b6a0-a7bdc1e1562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875077731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2875077731
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3834559865
Short name T172
Test name
Test status
Simulation time 530510068 ps
CPU time 0.86 seconds
Started Aug 05 05:48:03 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 196716 kb
Host smart-5595c97b-7aae-4a6a-92c1-c9710fda754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834559865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3834559865
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.510147490
Short name T113
Test name
Test status
Simulation time 573619676 ps
CPU time 1.05 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:47:57 PM PDT 24
Peak memory 196668 kb
Host smart-ae7e68d2-3e5f-467f-b2d9-e272b77c5585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510147490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.510147490
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.382939554
Short name T133
Test name
Test status
Simulation time 355081139 ps
CPU time 1.05 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:10 PM PDT 24
Peak memory 196680 kb
Host smart-e218c154-c4b0-48b0-9b4c-48aca39f8e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382939554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.382939554
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1162433673
Short name T168
Test name
Test status
Simulation time 113000615479 ps
CPU time 12.74 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:53 PM PDT 24
Peak memory 198272 kb
Host smart-c583d1d6-d9fb-4faf-aacd-1d29809ddc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162433673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1162433673
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3410721123
Short name T170
Test name
Test status
Simulation time 48642880300 ps
CPU time 85.81 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:49:32 PM PDT 24
Peak memory 213876 kb
Host smart-2903b930-1fca-454e-8658-d2f97a283c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410721123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3410721123
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2602732632
Short name T192
Test name
Test status
Simulation time 145704720570 ps
CPU time 365.24 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:54:15 PM PDT 24
Peak memory 210664 kb
Host smart-e3092bac-3c99-4643-8bf6-72c0cf1ad758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602732632 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2602732632
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1954920043
Short name T188
Test name
Test status
Simulation time 522115134 ps
CPU time 1.02 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 196716 kb
Host smart-d2515a07-1efa-41aa-8169-7a45adfb27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954920043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1954920043
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3810894374
Short name T87
Test name
Test status
Simulation time 548639357 ps
CPU time 0.68 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:48:05 PM PDT 24
Peak memory 196652 kb
Host smart-c3a7cfe2-92ac-4a5a-9d62-6539545f6938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810894374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3810894374
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.536912389
Short name T92
Test name
Test status
Simulation time 249700267834 ps
CPU time 436.07 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:55:10 PM PDT 24
Peak memory 211068 kb
Host smart-17f5e09d-6cbf-4dc5-8d31-ece209e150f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536912389 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.536912389
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2641569664
Short name T57
Test name
Test status
Simulation time 575272963 ps
CPU time 0.78 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 196556 kb
Host smart-37e9b8ba-d465-4cc2-b45c-3abb53ae7aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641569664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2641569664
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1152594992
Short name T60
Test name
Test status
Simulation time 86558181168 ps
CPU time 279.42 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:52:33 PM PDT 24
Peak memory 207232 kb
Host smart-8955b955-a6b2-48af-82fe-6f3eeca809ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152594992 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1152594992
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.202999089
Short name T184
Test name
Test status
Simulation time 106249433563 ps
CPU time 83.36 seconds
Started Aug 05 05:47:46 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 192652 kb
Host smart-ffafd134-6da4-407e-a06f-2e2b6c797e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202999089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.202999089
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3130403697
Short name T48
Test name
Test status
Simulation time 443010494 ps
CPU time 1.24 seconds
Started Aug 05 05:47:50 PM PDT 24
Finished Aug 05 05:47:51 PM PDT 24
Peak memory 196732 kb
Host smart-7007586b-ff28-41c6-97e5-11b1bbf02b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130403697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3130403697
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.742302483
Short name T187
Test name
Test status
Simulation time 510433592 ps
CPU time 1.22 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:17 PM PDT 24
Peak memory 196628 kb
Host smart-40325ee3-b6a5-451c-9d63-52e62521a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742302483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.742302483
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3253646414
Short name T88
Test name
Test status
Simulation time 750445712 ps
CPU time 0.65 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 196632 kb
Host smart-0229d3d2-91bd-48d3-b940-0678ab7d6c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253646414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3253646414
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3477729460
Short name T182
Test name
Test status
Simulation time 419885755 ps
CPU time 1.26 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 196776 kb
Host smart-04cbe1b0-b828-462b-a50f-a05457f11425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477729460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3477729460
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1898128635
Short name T193
Test name
Test status
Simulation time 20070716439 ps
CPU time 230.41 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:52:06 PM PDT 24
Peak memory 206928 kb
Host smart-bf563e0f-1ecb-4848-913b-5f581c9f1a30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898128635 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1898128635
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2718058851
Short name T308
Test name
Test status
Simulation time 544464145 ps
CPU time 1.05 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 193196 kb
Host smart-fa16a71e-f018-4d06-850b-a4b64e035d08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718058851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2718058851
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1467816427
Short name T348
Test name
Test status
Simulation time 1263207845 ps
CPU time 0.76 seconds
Started Aug 05 05:26:17 PM PDT 24
Finished Aug 05 05:26:18 PM PDT 24
Peak memory 193004 kb
Host smart-a33fb7fe-6499-424b-82eb-a152bd95563c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467816427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1467816427
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1070657164
Short name T419
Test name
Test status
Simulation time 486773022 ps
CPU time 0.9 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 195764 kb
Host smart-7a4a395b-bcec-4859-b4ef-c0582cc74268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070657164 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1070657164
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3836312829
Short name T339
Test name
Test status
Simulation time 446252050 ps
CPU time 0.93 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:19 PM PDT 24
Peak memory 193088 kb
Host smart-d3da3cf3-629a-494a-af8a-ae6ce9d8db9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836312829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3836312829
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2616956536
Short name T319
Test name
Test status
Simulation time 375702710 ps
CPU time 1.07 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:19 PM PDT 24
Peak memory 183996 kb
Host smart-872436c5-cca4-4fcc-af5b-3d5a2398a6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616956536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2616956536
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1214324492
Short name T295
Test name
Test status
Simulation time 437030832 ps
CPU time 0.64 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:18 PM PDT 24
Peak memory 183640 kb
Host smart-c3ec0b3d-9eb2-4d10-b9bd-7eb9e9f5b096
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214324492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1214324492
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.113771538
Short name T291
Test name
Test status
Simulation time 332741299 ps
CPU time 0.59 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:18 PM PDT 24
Peak memory 183696 kb
Host smart-4549bea1-e652-4c02-b399-90172b57c745
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113771538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.113771538
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2075170178
Short name T370
Test name
Test status
Simulation time 1313499621 ps
CPU time 0.77 seconds
Started Aug 05 05:26:15 PM PDT 24
Finished Aug 05 05:26:16 PM PDT 24
Peak memory 191908 kb
Host smart-8d0d3ac5-28dc-4af2-b714-b558d841fa7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075170178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2075170178
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1353524944
Short name T346
Test name
Test status
Simulation time 628537613 ps
CPU time 1.98 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 198552 kb
Host smart-4e6e1856-7e35-40b2-97d0-2880302806dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353524944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1353524944
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1893012516
Short name T39
Test name
Test status
Simulation time 4094332800 ps
CPU time 7.11 seconds
Started Aug 05 05:26:16 PM PDT 24
Finished Aug 05 05:26:23 PM PDT 24
Peak memory 197812 kb
Host smart-eb27f75c-388f-4fce-a8c9-6310b8c8b0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893012516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1893012516
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4059121006
Short name T70
Test name
Test status
Simulation time 739869471 ps
CPU time 0.95 seconds
Started Aug 05 05:26:17 PM PDT 24
Finished Aug 05 05:26:18 PM PDT 24
Peak memory 183756 kb
Host smart-9f125b61-ccc4-4eac-ac60-02cbcbc452b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059121006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4059121006
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.656251593
Short name T421
Test name
Test status
Simulation time 14311066297 ps
CPU time 19.87 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:40 PM PDT 24
Peak memory 192316 kb
Host smart-d315795b-f219-4787-b904-c20e800463a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656251593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.656251593
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.53593885
Short name T408
Test name
Test status
Simulation time 1196484150 ps
CPU time 0.75 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 192924 kb
Host smart-7987fe16-76d0-4e1b-8f55-c3d36f0b45c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53593885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_
reset.53593885
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.290301515
Short name T313
Test name
Test status
Simulation time 323584216 ps
CPU time 1.01 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:19 PM PDT 24
Peak memory 195232 kb
Host smart-5167e863-f851-43b0-b511-13bb6f17cfd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290301515 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.290301515
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3249368778
Short name T69
Test name
Test status
Simulation time 414459162 ps
CPU time 1.13 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:20 PM PDT 24
Peak memory 192032 kb
Host smart-e434bd36-8e93-490a-bb83-bcaf9a7d6547
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249368778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3249368778
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1965005503
Short name T351
Test name
Test status
Simulation time 479824826 ps
CPU time 0.6 seconds
Started Aug 05 05:26:22 PM PDT 24
Finished Aug 05 05:26:23 PM PDT 24
Peak memory 193028 kb
Host smart-31ba4ff7-f6d4-4367-8c39-3c42a0c75aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965005503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1965005503
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4264503683
Short name T342
Test name
Test status
Simulation time 425942785 ps
CPU time 1.11 seconds
Started Aug 05 05:26:16 PM PDT 24
Finished Aug 05 05:26:17 PM PDT 24
Peak memory 183696 kb
Host smart-01412fb1-dda6-4c3b-9b7f-1fda224b9152
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264503683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4264503683
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2385544143
Short name T321
Test name
Test status
Simulation time 505055001 ps
CPU time 0.88 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:20 PM PDT 24
Peak memory 183608 kb
Host smart-1fcb646b-9eed-41e1-9d11-2bc17c8bbba1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385544143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2385544143
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4000502195
Short name T298
Test name
Test status
Simulation time 364888617 ps
CPU time 2.35 seconds
Started Aug 05 05:26:21 PM PDT 24
Finished Aug 05 05:26:23 PM PDT 24
Peak memory 198604 kb
Host smart-895b1990-1ddf-4db3-8ad9-2dacf2be364b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000502195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4000502195
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.643557015
Short name T366
Test name
Test status
Simulation time 8372981350 ps
CPU time 2.25 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:23 PM PDT 24
Peak memory 198540 kb
Host smart-6f73820d-e5b6-4434-984a-12571f047adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643557015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.643557015
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2066511852
Short name T407
Test name
Test status
Simulation time 511884372 ps
CPU time 1.51 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 196292 kb
Host smart-5ca07056-4e41-4922-b1dd-fc8019ac2b57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066511852 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2066511852
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3063987689
Short name T79
Test name
Test status
Simulation time 378566288 ps
CPU time 0.8 seconds
Started Aug 05 05:26:32 PM PDT 24
Finished Aug 05 05:26:33 PM PDT 24
Peak memory 192920 kb
Host smart-b7d4374b-4a07-4cf2-88fb-df98dfa588d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063987689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3063987689
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.204291850
Short name T310
Test name
Test status
Simulation time 405659605 ps
CPU time 0.65 seconds
Started Aug 05 05:26:38 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 183796 kb
Host smart-08b53520-96a8-4dee-b911-07be8fc9de56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204291850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.204291850
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1359279174
Short name T415
Test name
Test status
Simulation time 2160415112 ps
CPU time 2.2 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 193068 kb
Host smart-7a7f71f7-fec1-4744-90a0-1373649ddb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359279174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1359279174
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1492365753
Short name T420
Test name
Test status
Simulation time 809517464 ps
CPU time 1.91 seconds
Started Aug 05 05:26:37 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 198640 kb
Host smart-8cdb7716-f1a8-480f-af4d-75a71ea0b379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492365753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1492365753
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3001772516
Short name T396
Test name
Test status
Simulation time 4574531915 ps
CPU time 4.07 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 197904 kb
Host smart-5bd20c76-56ea-4699-878b-d58b2c7735b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001772516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3001772516
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.828492395
Short name T42
Test name
Test status
Simulation time 422420395 ps
CPU time 0.76 seconds
Started Aug 05 05:26:32 PM PDT 24
Finished Aug 05 05:26:33 PM PDT 24
Peak memory 195704 kb
Host smart-fc9dabe8-37e5-4040-a890-3d795e206df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828492395 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.828492395
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3176922779
Short name T41
Test name
Test status
Simulation time 407170528 ps
CPU time 1.26 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 193444 kb
Host smart-b4d3eb6d-a19a-4351-a4d5-a41459c65214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176922779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3176922779
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4075931521
Short name T299
Test name
Test status
Simulation time 472336933 ps
CPU time 1.26 seconds
Started Aug 05 05:26:38 PM PDT 24
Finished Aug 05 05:26:40 PM PDT 24
Peak memory 193016 kb
Host smart-41af77ae-34dd-4fe4-8df5-16f7a47ef751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075931521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4075931521
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1184836621
Short name T400
Test name
Test status
Simulation time 1790087215 ps
CPU time 1.42 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:36 PM PDT 24
Peak memory 194164 kb
Host smart-1c9c3937-8101-4174-8127-65b7832a7693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184836621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1184836621
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4069169124
Short name T389
Test name
Test status
Simulation time 402463582 ps
CPU time 2.13 seconds
Started Aug 05 05:26:34 PM PDT 24
Finished Aug 05 05:26:36 PM PDT 24
Peak memory 198640 kb
Host smart-ecb17bf4-d582-4f3b-95aa-a05b6942fe36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069169124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4069169124
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1708316170
Short name T40
Test name
Test status
Simulation time 8264843201 ps
CPU time 2.83 seconds
Started Aug 05 05:26:34 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 198280 kb
Host smart-0e686b24-6e6b-428e-bdf9-a773171b7f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708316170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1708316170
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2700967039
Short name T390
Test name
Test status
Simulation time 642632968 ps
CPU time 0.94 seconds
Started Aug 05 05:26:33 PM PDT 24
Finished Aug 05 05:26:34 PM PDT 24
Peak memory 198184 kb
Host smart-7c4f7fd5-249f-4c0d-a832-7410d0de443c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700967039 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2700967039
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4199114613
Short name T66
Test name
Test status
Simulation time 385319318 ps
CPU time 0.7 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:36 PM PDT 24
Peak memory 191980 kb
Host smart-38ce2cdd-5258-4940-94df-a5642555f4fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199114613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4199114613
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1397383500
Short name T392
Test name
Test status
Simulation time 506990638 ps
CPU time 0.69 seconds
Started Aug 05 05:26:34 PM PDT 24
Finished Aug 05 05:26:35 PM PDT 24
Peak memory 183772 kb
Host smart-f6dd3103-f2df-46ed-8e55-c6141e2a948c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397383500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1397383500
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3938391947
Short name T83
Test name
Test status
Simulation time 2098834772 ps
CPU time 1.93 seconds
Started Aug 05 05:26:37 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 193912 kb
Host smart-919a5a94-dc67-4fc4-b9da-b9485b304003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938391947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3938391947
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.131969827
Short name T292
Test name
Test status
Simulation time 1053728905 ps
CPU time 2.34 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 198612 kb
Host smart-184400b2-a294-4cfb-a5f1-8ffe3cdb3256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131969827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.131969827
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3794593602
Short name T293
Test name
Test status
Simulation time 437014126 ps
CPU time 0.82 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 196200 kb
Host smart-82a93228-1481-471f-afdc-24f152a2f117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794593602 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3794593602
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1802469804
Short name T72
Test name
Test status
Simulation time 444407045 ps
CPU time 0.87 seconds
Started Aug 05 05:26:40 PM PDT 24
Finished Aug 05 05:26:41 PM PDT 24
Peak memory 193924 kb
Host smart-c00d9e9b-01af-4088-8bfa-f9be5f85db33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802469804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1802469804
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2925009707
Short name T362
Test name
Test status
Simulation time 512466454 ps
CPU time 1.4 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 192984 kb
Host smart-418334c0-0c89-46bb-84e5-6536183ab002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925009707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2925009707
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1851223452
Short name T341
Test name
Test status
Simulation time 1605775916 ps
CPU time 1.78 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 193648 kb
Host smart-b5fbdedd-fdf1-472b-ac9b-f8675ba8b773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851223452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1851223452
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2164223426
Short name T329
Test name
Test status
Simulation time 753607512 ps
CPU time 1.64 seconds
Started Aug 05 05:26:36 PM PDT 24
Finished Aug 05 05:26:38 PM PDT 24
Peak memory 197552 kb
Host smart-b41074ff-4894-42bd-a8e3-eecab16b7efe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164223426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2164223426
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2682739386
Short name T357
Test name
Test status
Simulation time 8272360650 ps
CPU time 4.01 seconds
Started Aug 05 05:26:41 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 198176 kb
Host smart-c5603c37-350c-4db6-a05a-54c01fdac277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682739386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2682739386
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3638380499
Short name T328
Test name
Test status
Simulation time 401215485 ps
CPU time 1.2 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 196964 kb
Host smart-00a1a83b-0da6-4da8-b93f-9d669573e7c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638380499 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3638380499
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.299468589
Short name T85
Test name
Test status
Simulation time 453218542 ps
CPU time 0.86 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 193360 kb
Host smart-a6aaab22-25e9-4352-bcfb-06eeba59000e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299468589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.299468589
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.866261943
Short name T338
Test name
Test status
Simulation time 384888492 ps
CPU time 1.04 seconds
Started Aug 05 05:26:40 PM PDT 24
Finished Aug 05 05:26:41 PM PDT 24
Peak memory 193016 kb
Host smart-04f9781c-932a-4a77-999d-75e032b361ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866261943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.866261943
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.595349423
Short name T80
Test name
Test status
Simulation time 2212351834 ps
CPU time 1.14 seconds
Started Aug 05 05:26:44 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 193900 kb
Host smart-d70df14d-ba06-4a85-b7e9-33f28005bb81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595349423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.595349423
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2059044264
Short name T409
Test name
Test status
Simulation time 324705446 ps
CPU time 2.05 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 198612 kb
Host smart-df49103b-63a7-4d1b-bbbf-cb9ba1b93391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059044264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2059044264
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3805461510
Short name T363
Test name
Test status
Simulation time 4468009547 ps
CPU time 7.54 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:49 PM PDT 24
Peak memory 197972 kb
Host smart-87a41917-96d5-49d6-b049-e0279226968a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805461510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3805461510
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2033581175
Short name T371
Test name
Test status
Simulation time 423089755 ps
CPU time 0.85 seconds
Started Aug 05 05:26:41 PM PDT 24
Finished Aug 05 05:26:42 PM PDT 24
Peak memory 196632 kb
Host smart-5b6621cd-bafd-4c31-9947-0927a8cd667b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033581175 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2033581175
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4163296465
Short name T65
Test name
Test status
Simulation time 446324768 ps
CPU time 0.72 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 193168 kb
Host smart-d81371b3-0cd7-4fa9-8204-a56ac49da434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163296465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4163296465
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2028408422
Short name T300
Test name
Test status
Simulation time 410402382 ps
CPU time 0.85 seconds
Started Aug 05 05:26:44 PM PDT 24
Finished Aug 05 05:26:45 PM PDT 24
Peak memory 183720 kb
Host smart-b058a7c0-ff9e-400b-8888-e4cbc65cf48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028408422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2028408422
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1526058136
Short name T81
Test name
Test status
Simulation time 1404703302 ps
CPU time 4.01 seconds
Started Aug 05 05:27:01 PM PDT 24
Finished Aug 05 05:27:05 PM PDT 24
Peak memory 192984 kb
Host smart-853707ea-3527-43bd-98db-58853bd0475d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526058136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1526058136
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1058162774
Short name T303
Test name
Test status
Simulation time 555371809 ps
CPU time 1.35 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 198668 kb
Host smart-2379e28a-b686-461c-a558-88b1f8c70c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058162774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1058162774
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1286581159
Short name T377
Test name
Test status
Simulation time 479650652 ps
CPU time 0.88 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 196584 kb
Host smart-ab0b0306-faf4-4239-b2af-3345a7bc2eb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286581159 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1286581159
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4136491388
Short name T395
Test name
Test status
Simulation time 333102895 ps
CPU time 0.67 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 192996 kb
Host smart-72841abe-c490-48a2-a0a3-aaae195243c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136491388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4136491388
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1867388698
Short name T307
Test name
Test status
Simulation time 315979267 ps
CPU time 0.63 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 183708 kb
Host smart-171f6b83-a8ad-4828-b380-9f8587a7ff95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867388698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1867388698
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3672529267
Short name T375
Test name
Test status
Simulation time 1070298063 ps
CPU time 0.85 seconds
Started Aug 05 05:26:41 PM PDT 24
Finished Aug 05 05:26:42 PM PDT 24
Peak memory 194028 kb
Host smart-2a43975a-2b5d-4f29-8384-cd2cfdb555d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672529267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3672529267
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4071694514
Short name T355
Test name
Test status
Simulation time 413347020 ps
CPU time 1.56 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 198556 kb
Host smart-94aa433b-4866-4922-8a5e-2b7b3b054ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071694514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4071694514
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3695773666
Short name T335
Test name
Test status
Simulation time 4243468859 ps
CPU time 6.97 seconds
Started Aug 05 05:26:43 PM PDT 24
Finished Aug 05 05:26:50 PM PDT 24
Peak memory 196804 kb
Host smart-0f842db0-b80c-4495-a159-21d9d3e9066e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695773666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3695773666
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.525803744
Short name T347
Test name
Test status
Simulation time 495576608 ps
CPU time 0.87 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 196024 kb
Host smart-6936fce8-0d20-4e62-9d2e-a4ed0307763d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525803744 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.525803744
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.9192486
Short name T318
Test name
Test status
Simulation time 535315785 ps
CPU time 1.45 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:44 PM PDT 24
Peak memory 193344 kb
Host smart-8c98f905-1e77-4fd3-b424-078d4464a368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9192486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.9192486
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3650874814
Short name T302
Test name
Test status
Simulation time 473864068 ps
CPU time 0.98 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 183816 kb
Host smart-3f8bb1fe-41b4-480a-8469-5980dce6b0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650874814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3650874814
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1411781850
Short name T401
Test name
Test status
Simulation time 985917634 ps
CPU time 1.54 seconds
Started Aug 05 05:26:57 PM PDT 24
Finished Aug 05 05:26:58 PM PDT 24
Peak memory 193472 kb
Host smart-93c76e53-98a9-454b-b2fb-2d2066044d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411781850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1411781850
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1609449351
Short name T343
Test name
Test status
Simulation time 619402567 ps
CPU time 1.93 seconds
Started Aug 05 05:26:41 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 198620 kb
Host smart-347b8427-96d7-4391-91e4-9d7b469fa47a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609449351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1609449351
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2672195082
Short name T200
Test name
Test status
Simulation time 8184998473 ps
CPU time 12.77 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:55 PM PDT 24
Peak memory 198248 kb
Host smart-2e915ae6-587f-4f99-be8b-46010e21cf4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672195082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2672195082
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2117690672
Short name T388
Test name
Test status
Simulation time 346842495 ps
CPU time 1.14 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 196248 kb
Host smart-efaed4bf-bcab-4a16-9424-b1aca0775dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117690672 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2117690672
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4284168133
Short name T78
Test name
Test status
Simulation time 379356207 ps
CPU time 0.71 seconds
Started Aug 05 05:27:00 PM PDT 24
Finished Aug 05 05:27:01 PM PDT 24
Peak memory 194004 kb
Host smart-0e1e000d-cc69-4151-b1c1-86f0f410b1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284168133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4284168133
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3043493909
Short name T381
Test name
Test status
Simulation time 513880395 ps
CPU time 0.7 seconds
Started Aug 05 05:26:49 PM PDT 24
Finished Aug 05 05:26:49 PM PDT 24
Peak memory 193000 kb
Host smart-14b798c3-8579-4418-822c-344e4d55b1df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043493909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3043493909
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.348519012
Short name T84
Test name
Test status
Simulation time 1260920217 ps
CPU time 1.04 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 193652 kb
Host smart-76b51087-b81a-47fb-8d3d-aa2c9f8313ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348519012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.348519012
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3655680662
Short name T320
Test name
Test status
Simulation time 417139810 ps
CPU time 1.28 seconds
Started Aug 05 05:26:42 PM PDT 24
Finished Aug 05 05:26:43 PM PDT 24
Peak memory 198332 kb
Host smart-1e0469f4-cf4f-4e1e-8202-81a4e1142b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655680662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3655680662
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.447112862
Short name T383
Test name
Test status
Simulation time 4139073072 ps
CPU time 2.56 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:54 PM PDT 24
Peak memory 198012 kb
Host smart-f02187da-e5b2-4355-acbb-6810ae536cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447112862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.447112862
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.32468437
Short name T306
Test name
Test status
Simulation time 435276249 ps
CPU time 1.35 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 195980 kb
Host smart-7f2e3155-0bde-4b21-a229-82621a686b9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468437 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.32468437
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2740796893
Short name T331
Test name
Test status
Simulation time 452222404 ps
CPU time 0.62 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 191988 kb
Host smart-185995d4-2ea2-4e39-99c2-a1d75f244e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740796893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2740796893
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.844182708
Short name T359
Test name
Test status
Simulation time 272359903 ps
CPU time 0.76 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 183820 kb
Host smart-34282ed6-5862-464f-917c-e1151b89398e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844182708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.844182708
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1487716380
Short name T82
Test name
Test status
Simulation time 941546335 ps
CPU time 2.21 seconds
Started Aug 05 05:26:54 PM PDT 24
Finished Aug 05 05:26:56 PM PDT 24
Peak memory 183788 kb
Host smart-0134c800-0c56-4546-acad-a6d961442383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487716380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1487716380
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3363721025
Short name T417
Test name
Test status
Simulation time 588174438 ps
CPU time 2.09 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:55 PM PDT 24
Peak memory 198656 kb
Host smart-bc9085eb-04b1-4418-8d06-dc8d7216754f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363721025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3363721025
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.744399514
Short name T364
Test name
Test status
Simulation time 4174233319 ps
CPU time 1.27 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 196840 kb
Host smart-e55a1a4d-fee5-46a6-8840-d0997d68143f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744399514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.744399514
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4183642130
Short name T413
Test name
Test status
Simulation time 548257184 ps
CPU time 1.42 seconds
Started Aug 05 05:26:21 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 193952 kb
Host smart-71a53ec4-5b33-4fed-97a9-17b79f059644
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183642130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4183642130
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1248337064
Short name T354
Test name
Test status
Simulation time 7201352830 ps
CPU time 5.57 seconds
Started Aug 05 05:26:23 PM PDT 24
Finished Aug 05 05:26:29 PM PDT 24
Peak memory 192272 kb
Host smart-e12b535f-0fbd-4aa6-9546-d1ee6d9f31f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248337064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1248337064
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3402630947
Short name T67
Test name
Test status
Simulation time 1185245440 ps
CPU time 1.96 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:20 PM PDT 24
Peak memory 193920 kb
Host smart-045ee41b-8b83-4871-a61d-e7133b41660f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402630947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3402630947
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3181242205
Short name T387
Test name
Test status
Simulation time 625934072 ps
CPU time 1.04 seconds
Started Aug 05 05:26:21 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 198356 kb
Host smart-d2f903ec-d8ec-4879-8fa7-4fd920a04c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181242205 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3181242205
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1410677037
Short name T378
Test name
Test status
Simulation time 501464916 ps
CPU time 1.34 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 193336 kb
Host smart-86a9bf4b-54d7-47be-be2e-7135afc3268c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410677037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1410677037
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4234184753
Short name T285
Test name
Test status
Simulation time 445771461 ps
CPU time 1.09 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:54 PM PDT 24
Peak memory 183816 kb
Host smart-cf04e1b1-ff31-4c1f-ac81-70ed17786622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234184753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4234184753
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2332437887
Short name T358
Test name
Test status
Simulation time 361711623 ps
CPU time 1.01 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 183732 kb
Host smart-6a911d44-904d-4a5b-a14c-b0d8a6a07443
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332437887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2332437887
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1406070197
Short name T424
Test name
Test status
Simulation time 401345835 ps
CPU time 0.68 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:18 PM PDT 24
Peak memory 183692 kb
Host smart-a0783cfa-06db-4f6a-a08d-b2aa9baf2cc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406070197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1406070197
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2212586541
Short name T391
Test name
Test status
Simulation time 2562042765 ps
CPU time 2.3 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 195080 kb
Host smart-3a02c953-cf41-475c-9d37-3019a2446bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212586541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2212586541
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1927092244
Short name T284
Test name
Test status
Simulation time 515356716 ps
CPU time 2.62 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:21 PM PDT 24
Peak memory 198660 kb
Host smart-bfc42859-dc00-49e8-8bf7-4f511e21e7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927092244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1927092244
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.65809222
Short name T376
Test name
Test status
Simulation time 8586678345 ps
CPU time 7.8 seconds
Started Aug 05 05:26:18 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 198320 kb
Host smart-e9fc6fd2-c5ec-42b5-b995-002efe79d9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65809222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_i
ntg_err.65809222
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3870327777
Short name T386
Test name
Test status
Simulation time 306116961 ps
CPU time 1.03 seconds
Started Aug 05 05:26:56 PM PDT 24
Finished Aug 05 05:26:57 PM PDT 24
Peak memory 183780 kb
Host smart-2588d123-c82f-4b16-8e76-0700c076d904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870327777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3870327777
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.112846481
Short name T368
Test name
Test status
Simulation time 410577980 ps
CPU time 0.84 seconds
Started Aug 05 05:26:56 PM PDT 24
Finished Aug 05 05:26:57 PM PDT 24
Peak memory 192940 kb
Host smart-434c046b-60b5-4cfd-b3fb-25bc2b7ce9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112846481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.112846481
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.248845043
Short name T324
Test name
Test status
Simulation time 406006778 ps
CPU time 1.17 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 192984 kb
Host smart-3d8569fc-d3b6-41c5-92d0-703367a137ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248845043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.248845043
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1600170456
Short name T410
Test name
Test status
Simulation time 459629091 ps
CPU time 1.16 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 192944 kb
Host smart-9d22cfd3-80a3-4544-8f4f-194f6c37b907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600170456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1600170456
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2678795468
Short name T325
Test name
Test status
Simulation time 442500366 ps
CPU time 1.21 seconds
Started Aug 05 05:26:58 PM PDT 24
Finished Aug 05 05:26:59 PM PDT 24
Peak memory 192940 kb
Host smart-e0f9e213-c7c1-47e9-a0d7-aa82d03827e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678795468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2678795468
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1555663148
Short name T287
Test name
Test status
Simulation time 385301151 ps
CPU time 0.86 seconds
Started Aug 05 05:26:55 PM PDT 24
Finished Aug 05 05:26:56 PM PDT 24
Peak memory 183900 kb
Host smart-2235e150-4101-442f-a491-872a4002affa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555663148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1555663148
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2198723000
Short name T393
Test name
Test status
Simulation time 430575157 ps
CPU time 1.08 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 183780 kb
Host smart-1a04da71-4290-4bf5-90d2-2e19f329c174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198723000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2198723000
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.534048335
Short name T373
Test name
Test status
Simulation time 388488174 ps
CPU time 0.69 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 193020 kb
Host smart-fee693d7-843b-451a-bd9d-1934752d6c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534048335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.534048335
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.776791156
Short name T288
Test name
Test status
Simulation time 410947030 ps
CPU time 1.08 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:55 PM PDT 24
Peak memory 183796 kb
Host smart-79142c3b-92f6-475a-94a5-ec5b8d67cb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776791156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.776791156
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4001375390
Short name T352
Test name
Test status
Simulation time 408697951 ps
CPU time 1.2 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 183772 kb
Host smart-65de83f5-e92d-4b12-866f-bb9f0b7c3907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001375390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4001375390
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2057550188
Short name T315
Test name
Test status
Simulation time 515931511 ps
CPU time 0.87 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 194132 kb
Host smart-549f4736-c9d3-4734-9aaa-8510891a242d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057550188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2057550188
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1090994415
Short name T384
Test name
Test status
Simulation time 6916536178 ps
CPU time 11.33 seconds
Started Aug 05 05:26:29 PM PDT 24
Finished Aug 05 05:26:40 PM PDT 24
Peak memory 192296 kb
Host smart-d4ab3752-fa29-4fce-a29e-b5bf5aab5df2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090994415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1090994415
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2778801183
Short name T402
Test name
Test status
Simulation time 847533204 ps
CPU time 0.88 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 192100 kb
Host smart-f4d5e2ec-1e9e-42a8-b7cd-bd4c27bb33b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778801183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2778801183
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1416970947
Short name T414
Test name
Test status
Simulation time 519156052 ps
CPU time 0.89 seconds
Started Aug 05 05:26:28 PM PDT 24
Finished Aug 05 05:26:28 PM PDT 24
Peak memory 195540 kb
Host smart-bc790b7f-37b3-4dfb-89c5-fb22856e03ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416970947 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1416970947
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3275511632
Short name T205
Test name
Test status
Simulation time 398648956 ps
CPU time 1.14 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 192912 kb
Host smart-b299669e-3ac4-45f7-be33-34968b08741d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275511632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3275511632
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.914027822
Short name T283
Test name
Test status
Simulation time 487603215 ps
CPU time 0.87 seconds
Started Aug 05 05:26:20 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 183768 kb
Host smart-94faad52-32b2-41f6-9c28-131360d37a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914027822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.914027822
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4007104166
Short name T349
Test name
Test status
Simulation time 323984102 ps
CPU time 0.65 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 183700 kb
Host smart-a068589a-48e5-4c41-8c67-3a1e1f7d4f60
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007104166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4007104166
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.911720798
Short name T301
Test name
Test status
Simulation time 270172368 ps
CPU time 0.77 seconds
Started Aug 05 05:26:21 PM PDT 24
Finished Aug 05 05:26:22 PM PDT 24
Peak memory 183716 kb
Host smart-46f9b079-97ec-4fb4-8b53-042bb7a930e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911720798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.911720798
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2827339536
Short name T86
Test name
Test status
Simulation time 1154969711 ps
CPU time 1.19 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:27 PM PDT 24
Peak memory 192920 kb
Host smart-ff4d55fc-2a22-491f-88c9-0015b1343ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827339536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2827339536
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4166058869
Short name T330
Test name
Test status
Simulation time 537373890 ps
CPU time 1.75 seconds
Started Aug 05 05:26:19 PM PDT 24
Finished Aug 05 05:26:20 PM PDT 24
Peak memory 198436 kb
Host smart-76272af5-afd8-46a4-af7e-5148281a7cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166058869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4166058869
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1091341805
Short name T201
Test name
Test status
Simulation time 4107034103 ps
CPU time 2.73 seconds
Started Aug 05 05:26:21 PM PDT 24
Finished Aug 05 05:26:24 PM PDT 24
Peak memory 198000 kb
Host smart-13ea59b9-aebc-4c3d-bd50-6e9c8b3cd4ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091341805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1091341805
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2461945441
Short name T340
Test name
Test status
Simulation time 439658132 ps
CPU time 0.94 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:54 PM PDT 24
Peak memory 193004 kb
Host smart-d669ea2f-e290-4497-9812-74fad7e6d188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461945441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2461945441
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1373949170
Short name T332
Test name
Test status
Simulation time 336044388 ps
CPU time 1.03 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 183812 kb
Host smart-626523f0-8d36-44ab-beb9-3b8ab57be8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373949170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1373949170
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.863774897
Short name T316
Test name
Test status
Simulation time 417231017 ps
CPU time 0.9 seconds
Started Aug 05 05:26:50 PM PDT 24
Finished Aug 05 05:26:51 PM PDT 24
Peak memory 192924 kb
Host smart-54185f9b-a2a9-4ceb-9c15-89a24e92ea0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863774897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.863774897
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3049263443
Short name T296
Test name
Test status
Simulation time 466629103 ps
CPU time 0.73 seconds
Started Aug 05 05:26:49 PM PDT 24
Finished Aug 05 05:26:50 PM PDT 24
Peak memory 192924 kb
Host smart-c3baba33-7389-461c-b747-d9f1fc8b7386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049263443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3049263443
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4136521649
Short name T327
Test name
Test status
Simulation time 513896782 ps
CPU time 0.94 seconds
Started Aug 05 05:26:50 PM PDT 24
Finished Aug 05 05:26:51 PM PDT 24
Peak memory 183768 kb
Host smart-8e8942c8-51e8-473b-8508-7a01c49458ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136521649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4136521649
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1323150605
Short name T406
Test name
Test status
Simulation time 366272081 ps
CPU time 0.62 seconds
Started Aug 05 05:26:50 PM PDT 24
Finished Aug 05 05:26:50 PM PDT 24
Peak memory 183764 kb
Host smart-881e6ec3-6d6b-408f-a84f-ca09cca8010d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323150605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1323150605
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1520654345
Short name T365
Test name
Test status
Simulation time 492676456 ps
CPU time 0.71 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 183720 kb
Host smart-e157105d-d0b9-4345-9207-f2c2c2c00f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520654345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1520654345
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1799813758
Short name T403
Test name
Test status
Simulation time 346956856 ps
CPU time 0.7 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:54 PM PDT 24
Peak memory 192988 kb
Host smart-89f627a1-7567-4a33-9de2-c55303207812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799813758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1799813758
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1474970999
Short name T360
Test name
Test status
Simulation time 408736408 ps
CPU time 0.73 seconds
Started Aug 05 05:26:50 PM PDT 24
Finished Aug 05 05:26:51 PM PDT 24
Peak memory 193000 kb
Host smart-3806219e-bfe4-4230-8e83-ae2828e64789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474970999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1474970999
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3952620884
Short name T356
Test name
Test status
Simulation time 465109605 ps
CPU time 0.74 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 183800 kb
Host smart-7554ce04-8588-4885-8160-81706b898e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952620884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3952620884
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1289402011
Short name T68
Test name
Test status
Simulation time 565486382 ps
CPU time 0.87 seconds
Started Aug 05 05:26:27 PM PDT 24
Finished Aug 05 05:26:28 PM PDT 24
Peak memory 183788 kb
Host smart-858262be-fa2a-4a34-badb-ec9b88242659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289402011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1289402011
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3977937212
Short name T71
Test name
Test status
Simulation time 9736863295 ps
CPU time 4.64 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:30 PM PDT 24
Peak memory 196112 kb
Host smart-807b8f61-27d2-4581-80e0-b28a17057996
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977937212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3977937212
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2655984578
Short name T412
Test name
Test status
Simulation time 821206319 ps
CPU time 1.69 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:27 PM PDT 24
Peak memory 192136 kb
Host smart-b21935e2-39c5-490c-899e-c12950c66543
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655984578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2655984578
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3602959289
Short name T322
Test name
Test status
Simulation time 718428188 ps
CPU time 0.93 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 198428 kb
Host smart-84e64725-2939-492c-8c51-b7bfdd27629e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602959289 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3602959289
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1345047493
Short name T418
Test name
Test status
Simulation time 271324878 ps
CPU time 0.94 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 192056 kb
Host smart-4d948a8e-46c1-4d87-9983-96860d0201d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345047493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1345047493
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2772338883
Short name T380
Test name
Test status
Simulation time 337129294 ps
CPU time 1.08 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 183792 kb
Host smart-1513fe76-6115-43b2-b823-9693aaf344a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772338883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2772338883
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2319496681
Short name T286
Test name
Test status
Simulation time 304540450 ps
CPU time 0.92 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 183712 kb
Host smart-f56b0cba-2403-45f9-a400-f18ffc6b4dfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319496681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2319496681
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2373061812
Short name T379
Test name
Test status
Simulation time 319821534 ps
CPU time 0.97 seconds
Started Aug 05 05:26:29 PM PDT 24
Finished Aug 05 05:26:30 PM PDT 24
Peak memory 183700 kb
Host smart-837b14e7-d653-4fd6-ba22-bd77a9d7ba7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373061812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2373061812
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3958218850
Short name T38
Test name
Test status
Simulation time 2540995676 ps
CPU time 3.86 seconds
Started Aug 05 05:26:27 PM PDT 24
Finished Aug 05 05:26:31 PM PDT 24
Peak memory 184036 kb
Host smart-3ffbd783-8647-4143-ab73-104a15dcf4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958218850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3958218850
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.608281991
Short name T344
Test name
Test status
Simulation time 562652957 ps
CPU time 1.52 seconds
Started Aug 05 05:26:22 PM PDT 24
Finished Aug 05 05:26:24 PM PDT 24
Peak memory 198632 kb
Host smart-81d0ead6-3d7e-42a9-abe2-ba26b7b0cde5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608281991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.608281991
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2019891290
Short name T382
Test name
Test status
Simulation time 4358812727 ps
CPU time 6.71 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:31 PM PDT 24
Peak memory 197524 kb
Host smart-e0271fb6-d849-4e0d-b652-9d08ec9bf892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019891290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2019891290
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2761589674
Short name T282
Test name
Test status
Simulation time 485360501 ps
CPU time 0.72 seconds
Started Aug 05 05:26:54 PM PDT 24
Finished Aug 05 05:26:55 PM PDT 24
Peak memory 184000 kb
Host smart-7d85c511-4645-4a50-bd77-822b5f19f4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761589674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2761589674
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.790390005
Short name T374
Test name
Test status
Simulation time 400909085 ps
CPU time 0.89 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 183720 kb
Host smart-2ebcc613-8d31-4df0-93c6-d5b912cb19fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790390005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.790390005
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1160050411
Short name T350
Test name
Test status
Simulation time 433029714 ps
CPU time 1.14 seconds
Started Aug 05 05:26:52 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 183784 kb
Host smart-cbc1d318-ccd9-4b4a-a2e4-cba788ee1bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160050411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1160050411
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2753169391
Short name T304
Test name
Test status
Simulation time 270037233 ps
CPU time 0.76 seconds
Started Aug 05 05:26:54 PM PDT 24
Finished Aug 05 05:26:55 PM PDT 24
Peak memory 193016 kb
Host smart-78fde307-c426-4f23-9953-79907e137c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753169391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2753169391
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3938137308
Short name T314
Test name
Test status
Simulation time 354286475 ps
CPU time 1.07 seconds
Started Aug 05 05:26:56 PM PDT 24
Finished Aug 05 05:26:57 PM PDT 24
Peak memory 183780 kb
Host smart-35b9e58f-3619-492e-99e7-25556da077ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938137308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3938137308
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3074394950
Short name T281
Test name
Test status
Simulation time 360163608 ps
CPU time 1.06 seconds
Started Aug 05 05:26:56 PM PDT 24
Finished Aug 05 05:26:57 PM PDT 24
Peak memory 192940 kb
Host smart-081b0735-208a-4014-ac6b-bb7c970e8667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074394950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3074394950
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1866814617
Short name T297
Test name
Test status
Simulation time 480871683 ps
CPU time 1.23 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:53 PM PDT 24
Peak memory 192928 kb
Host smart-64984c88-c2a0-4ed4-8ea6-ca7e2f5bdcdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866814617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1866814617
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3997338351
Short name T311
Test name
Test status
Simulation time 282660078 ps
CPU time 0.74 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 183688 kb
Host smart-522e935f-cd16-4ad9-b3ec-e425614d56c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997338351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3997338351
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2624377856
Short name T309
Test name
Test status
Simulation time 448932185 ps
CPU time 0.69 seconds
Started Aug 05 05:26:53 PM PDT 24
Finished Aug 05 05:26:54 PM PDT 24
Peak memory 183900 kb
Host smart-c4a2b36d-660e-44f7-a010-2a153c9612c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624377856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2624377856
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1841843681
Short name T336
Test name
Test status
Simulation time 358269497 ps
CPU time 0.75 seconds
Started Aug 05 05:26:51 PM PDT 24
Finished Aug 05 05:26:52 PM PDT 24
Peak memory 193032 kb
Host smart-7b761711-7a02-49f5-bd4a-9e93b5a10c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841843681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1841843681
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2443276590
Short name T397
Test name
Test status
Simulation time 328720052 ps
CPU time 0.81 seconds
Started Aug 05 05:26:32 PM PDT 24
Finished Aug 05 05:26:33 PM PDT 24
Peak memory 196248 kb
Host smart-dd6a9743-9607-42aa-ac1f-7d22ca5eefd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443276590 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2443276590
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3943560485
Short name T326
Test name
Test status
Simulation time 453185924 ps
CPU time 0.72 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:24 PM PDT 24
Peak memory 193352 kb
Host smart-e67d9f23-9113-4ee5-8786-bde6299f931d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943560485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3943560485
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.311029822
Short name T345
Test name
Test status
Simulation time 496960637 ps
CPU time 0.89 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 193012 kb
Host smart-8e137346-f0f2-4589-a80a-5cc164807a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311029822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.311029822
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.371630955
Short name T422
Test name
Test status
Simulation time 1377000972 ps
CPU time 1.27 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 191980 kb
Host smart-a1e827d7-01e6-482d-ad09-a01d1456236b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371630955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.371630955
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.686232115
Short name T289
Test name
Test status
Simulation time 434440226 ps
CPU time 2.01 seconds
Started Aug 05 05:26:27 PM PDT 24
Finished Aug 05 05:26:29 PM PDT 24
Peak memory 198588 kb
Host smart-be645528-8211-4816-9512-ef1579b1c0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686232115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.686232115
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1694133285
Short name T372
Test name
Test status
Simulation time 8323385658 ps
CPU time 12.01 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 198280 kb
Host smart-f67819b4-805b-42e6-b90a-1d0426ac8fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694133285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1694133285
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3189322680
Short name T312
Test name
Test status
Simulation time 365885345 ps
CPU time 0.94 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 197708 kb
Host smart-b9c4db4b-6c93-4dcf-a9cf-892407127c46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189322680 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3189322680
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.618806937
Short name T64
Test name
Test status
Simulation time 493401750 ps
CPU time 0.78 seconds
Started Aug 05 05:26:29 PM PDT 24
Finished Aug 05 05:26:30 PM PDT 24
Peak memory 192056 kb
Host smart-9a0a4f87-9fcd-49cb-ab8a-4a7936286f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618806937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.618806937
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2482011243
Short name T290
Test name
Test status
Simulation time 405517573 ps
CPU time 1.19 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:25 PM PDT 24
Peak memory 183800 kb
Host smart-7598c246-7275-464d-9dc6-21d5729fbb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482011243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2482011243
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3556542319
Short name T353
Test name
Test status
Simulation time 1373662507 ps
CPU time 1.63 seconds
Started Aug 05 05:26:30 PM PDT 24
Finished Aug 05 05:26:32 PM PDT 24
Peak memory 193312 kb
Host smart-661c7d4f-c34e-48e1-ab96-ae93fab9793d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556542319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3556542319
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2632777226
Short name T294
Test name
Test status
Simulation time 553513284 ps
CPU time 1.52 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 198636 kb
Host smart-4c123f32-522f-472a-b513-ccfef8aaee99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632777226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2632777226
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3867833114
Short name T198
Test name
Test status
Simulation time 4051300545 ps
CPU time 2.4 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:27 PM PDT 24
Peak memory 197800 kb
Host smart-f4f506a3-8cac-4ee3-9808-d1f3978465e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867833114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3867833114
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2706985235
Short name T423
Test name
Test status
Simulation time 566010259 ps
CPU time 1.15 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 197964 kb
Host smart-fa690d84-5b3d-4fe6-95d4-bf643d97a330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706985235 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2706985235
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4178133998
Short name T405
Test name
Test status
Simulation time 427091115 ps
CPU time 0.94 seconds
Started Aug 05 05:26:27 PM PDT 24
Finished Aug 05 05:26:28 PM PDT 24
Peak memory 193404 kb
Host smart-2901617e-80f4-43d6-9219-e1fa25cc4db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178133998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4178133998
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1642357869
Short name T333
Test name
Test status
Simulation time 453374984 ps
CPU time 0.86 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 183716 kb
Host smart-7a905ef2-d5f9-4829-af90-84956b37660d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642357869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1642357869
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3909825370
Short name T398
Test name
Test status
Simulation time 3012075104 ps
CPU time 1.11 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:26 PM PDT 24
Peak memory 195468 kb
Host smart-cab6558e-0d8a-4c68-bec6-1791f6a897e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909825370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3909825370
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2032985283
Short name T411
Test name
Test status
Simulation time 513791649 ps
CPU time 3.19 seconds
Started Aug 05 05:26:26 PM PDT 24
Finished Aug 05 05:26:29 PM PDT 24
Peak memory 198844 kb
Host smart-a464f526-a65a-48fd-99db-60dd06f84ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032985283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2032985283
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3404515615
Short name T399
Test name
Test status
Simulation time 4233593026 ps
CPU time 7.31 seconds
Started Aug 05 05:26:24 PM PDT 24
Finished Aug 05 05:26:31 PM PDT 24
Peak memory 196620 kb
Host smart-74b483bc-5306-4e11-9a25-51472ddb2efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404515615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3404515615
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3221303285
Short name T385
Test name
Test status
Simulation time 490870675 ps
CPU time 1.39 seconds
Started Aug 05 05:26:33 PM PDT 24
Finished Aug 05 05:26:35 PM PDT 24
Peak memory 196440 kb
Host smart-0f39de36-1efd-492a-9c44-5658508ee4e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221303285 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3221303285
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.340567356
Short name T334
Test name
Test status
Simulation time 540963782 ps
CPU time 1.02 seconds
Started Aug 05 05:26:31 PM PDT 24
Finished Aug 05 05:26:32 PM PDT 24
Peak memory 193168 kb
Host smart-436eca69-045b-495d-b598-9c9d67db6bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340567356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.340567356
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1180674409
Short name T404
Test name
Test status
Simulation time 380040958 ps
CPU time 0.72 seconds
Started Aug 05 05:26:34 PM PDT 24
Finished Aug 05 05:26:34 PM PDT 24
Peak memory 183792 kb
Host smart-a5ac359b-c96c-4882-ae0d-f41a06635320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180674409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1180674409
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4167695004
Short name T369
Test name
Test status
Simulation time 2288557488 ps
CPU time 1.27 seconds
Started Aug 05 05:26:55 PM PDT 24
Finished Aug 05 05:26:56 PM PDT 24
Peak memory 195096 kb
Host smart-0ad78139-f334-4b14-977f-a6a3f2cd7813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167695004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4167695004
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4196720358
Short name T416
Test name
Test status
Simulation time 615980887 ps
CPU time 1.47 seconds
Started Aug 05 05:26:25 PM PDT 24
Finished Aug 05 05:26:27 PM PDT 24
Peak memory 198616 kb
Host smart-571976e9-abf3-4831-82bc-a89dac5781cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196720358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4196720358
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3006796336
Short name T317
Test name
Test status
Simulation time 8189687428 ps
CPU time 9.17 seconds
Started Aug 05 05:26:28 PM PDT 24
Finished Aug 05 05:26:37 PM PDT 24
Peak memory 198304 kb
Host smart-b758168d-708c-4784-8095-188150a17e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006796336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3006796336
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.402725381
Short name T361
Test name
Test status
Simulation time 440714078 ps
CPU time 1.29 seconds
Started Aug 05 05:26:33 PM PDT 24
Finished Aug 05 05:26:35 PM PDT 24
Peak memory 196236 kb
Host smart-5174cbf1-b8b1-4067-93c7-ec4589538014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402725381 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.402725381
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3370475881
Short name T337
Test name
Test status
Simulation time 348337205 ps
CPU time 0.7 seconds
Started Aug 05 05:26:39 PM PDT 24
Finished Aug 05 05:26:40 PM PDT 24
Peak memory 193240 kb
Host smart-b8c14817-75b1-40f9-9c0c-f184a14a5cff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370475881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3370475881
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.902483166
Short name T323
Test name
Test status
Simulation time 552073461 ps
CPU time 0.63 seconds
Started Aug 05 05:26:38 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 183792 kb
Host smart-a59f7ad9-0d89-4f74-8302-ce30c7b391a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902483166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.902483166
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3259006656
Short name T394
Test name
Test status
Simulation time 1538587033 ps
CPU time 1.51 seconds
Started Aug 05 05:26:32 PM PDT 24
Finished Aug 05 05:26:34 PM PDT 24
Peak memory 193020 kb
Host smart-e95126b9-01c3-40ec-a7e1-ded18cd1c027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259006656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3259006656
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.56068312
Short name T367
Test name
Test status
Simulation time 450446899 ps
CPU time 1.34 seconds
Started Aug 05 05:26:36 PM PDT 24
Finished Aug 05 05:26:38 PM PDT 24
Peak memory 197688 kb
Host smart-12dac040-8728-48f1-8452-5fc0f925441e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56068312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.56068312
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3931692618
Short name T305
Test name
Test status
Simulation time 3900854234 ps
CPU time 4.3 seconds
Started Aug 05 05:26:35 PM PDT 24
Finished Aug 05 05:26:39 PM PDT 24
Peak memory 197872 kb
Host smart-362176c9-2f7c-4b7c-ba8f-b70c6d859439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931692618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3931692618
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2089840087
Short name T195
Test name
Test status
Simulation time 489950291 ps
CPU time 1.04 seconds
Started Aug 05 05:47:31 PM PDT 24
Finished Aug 05 05:47:32 PM PDT 24
Peak memory 196736 kb
Host smart-dd8737d4-78ec-41ac-8d2c-a9cd0b1c0e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089840087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2089840087
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4050766467
Short name T254
Test name
Test status
Simulation time 12773503937 ps
CPU time 10.75 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 191896 kb
Host smart-16b59140-ff85-41fc-81ee-ed5db65701ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050766467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4050766467
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3123475178
Short name T55
Test name
Test status
Simulation time 426491910 ps
CPU time 0.64 seconds
Started Aug 05 05:47:59 PM PDT 24
Finished Aug 05 05:48:00 PM PDT 24
Peak memory 191836 kb
Host smart-57f77d57-fcc2-4f48-98ff-1a6aa95ee606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123475178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3123475178
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3257501445
Short name T185
Test name
Test status
Simulation time 601789344 ps
CPU time 0.84 seconds
Started Aug 05 05:47:37 PM PDT 24
Finished Aug 05 05:47:37 PM PDT 24
Peak memory 196636 kb
Host smart-6709ac01-b5a2-4e07-98be-1091e374d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257501445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3257501445
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4144236665
Short name T226
Test name
Test status
Simulation time 29909722529 ps
CPU time 47.61 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 196788 kb
Host smart-0242c745-0fc6-4831-8c24-67a9e9145f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144236665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4144236665
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2482129923
Short name T17
Test name
Test status
Simulation time 4135727734 ps
CPU time 6.85 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:47:59 PM PDT 24
Peak memory 215468 kb
Host smart-7ed67c0c-e944-4e68-ba55-335a235f6ef4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482129923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2482129923
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.12605460
Short name T262
Test name
Test status
Simulation time 429851745 ps
CPU time 0.76 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 191832 kb
Host smart-99faa3c1-47a4-47aa-84c1-1e4440770f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12605460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.12605460
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1922317679
Short name T190
Test name
Test status
Simulation time 384366482 ps
CPU time 1.16 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 196620 kb
Host smart-0ac2bac3-e78e-47e9-b7f2-efe454ff543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922317679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1922317679
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2751122603
Short name T235
Test name
Test status
Simulation time 17430779271 ps
CPU time 11.91 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:47:48 PM PDT 24
Peak memory 191888 kb
Host smart-aa3f3c15-1459-44d0-b01d-09dadf7de26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751122603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2751122603
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4133007807
Short name T76
Test name
Test status
Simulation time 599354361 ps
CPU time 0.8 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 191820 kb
Host smart-7c234234-397d-4c4b-9632-c3cb7180a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133007807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4133007807
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1315129084
Short name T237
Test name
Test status
Simulation time 47914666390 ps
CPU time 73.75 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 191896 kb
Host smart-60323342-f07c-46a6-8e63-152374e42332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315129084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1315129084
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3933244917
Short name T223
Test name
Test status
Simulation time 483131385 ps
CPU time 0.73 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:47:40 PM PDT 24
Peak memory 191824 kb
Host smart-d3bbc320-3fa6-4570-aefb-b6f6cb4967a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933244917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3933244917
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3688908017
Short name T241
Test name
Test status
Simulation time 30721106363 ps
CPU time 11.68 seconds
Started Aug 05 05:47:59 PM PDT 24
Finished Aug 05 05:48:10 PM PDT 24
Peak memory 196908 kb
Host smart-16dc074c-35df-450e-8318-3fb47e98bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688908017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3688908017
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3242542420
Short name T219
Test name
Test status
Simulation time 462266287 ps
CPU time 1.3 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:42 PM PDT 24
Peak memory 196604 kb
Host smart-0b1b8b50-2bab-4cb8-93db-da18c0e6639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242542420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3242542420
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1685108414
Short name T221
Test name
Test status
Simulation time 26456344662 ps
CPU time 10.86 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:48:11 PM PDT 24
Peak memory 196884 kb
Host smart-4cdd7069-40cf-4f56-82f5-4ceb5768e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685108414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1685108414
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.146418678
Short name T277
Test name
Test status
Simulation time 374403619 ps
CPU time 1.12 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:42 PM PDT 24
Peak memory 191824 kb
Host smart-19f32180-db7f-4680-9656-2bb7757c2e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146418678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.146418678
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3256689357
Short name T246
Test name
Test status
Simulation time 7312268760 ps
CPU time 5.98 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 191892 kb
Host smart-61c5c9d4-fe32-46e0-ab5a-00a5137231c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256689357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3256689357
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3505124055
Short name T228
Test name
Test status
Simulation time 421384191 ps
CPU time 1.3 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:09 PM PDT 24
Peak memory 191848 kb
Host smart-21d6cfef-760b-4d4a-a2e4-452c681c6a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505124055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3505124055
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1154313501
Short name T240
Test name
Test status
Simulation time 847503197 ps
CPU time 1.14 seconds
Started Aug 05 05:47:50 PM PDT 24
Finished Aug 05 05:47:52 PM PDT 24
Peak memory 196544 kb
Host smart-152b202e-f989-4ca8-a3bb-ecd036612f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154313501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1154313501
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2837920988
Short name T274
Test name
Test status
Simulation time 429450253 ps
CPU time 0.77 seconds
Started Aug 05 05:47:40 PM PDT 24
Finished Aug 05 05:47:41 PM PDT 24
Peak memory 191824 kb
Host smart-d155745d-c38a-4de4-a947-fc4916d32eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837920988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2837920988
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.664644000
Short name T204
Test name
Test status
Simulation time 22805468266 ps
CPU time 9.54 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 191872 kb
Host smart-3e197066-5d4f-440b-ad8c-92db227fec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664644000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.664644000
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2713634917
Short name T217
Test name
Test status
Simulation time 471102086 ps
CPU time 0.75 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 191832 kb
Host smart-136e0eec-4083-4604-9a69-784cef2bff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713634917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2713634917
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2004615120
Short name T252
Test name
Test status
Simulation time 4145001352 ps
CPU time 2.17 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:47:54 PM PDT 24
Peak memory 191888 kb
Host smart-d37baa57-209c-467c-a719-9d5e4e0bcba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004615120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2004615120
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2597477927
Short name T256
Test name
Test status
Simulation time 501619759 ps
CPU time 0.93 seconds
Started Aug 05 05:47:58 PM PDT 24
Finished Aug 05 05:47:59 PM PDT 24
Peak memory 191840 kb
Host smart-6fb8e7e8-6777-4b1e-be8c-a32c2b5ca672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597477927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2597477927
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2799660713
Short name T279
Test name
Test status
Simulation time 39766216827 ps
CPU time 29.57 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 196920 kb
Host smart-c6217c33-2c5c-432c-95a4-21bee08b1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799660713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2799660713
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4226607777
Short name T214
Test name
Test status
Simulation time 426265680 ps
CPU time 0.72 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:48:11 PM PDT 24
Peak memory 191840 kb
Host smart-99d3fef8-3436-4bca-b56d-56a7ff9b5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226607777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4226607777
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1591891488
Short name T263
Test name
Test status
Simulation time 16452746215 ps
CPU time 7.35 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 196888 kb
Host smart-340c1a0a-ba25-45e3-9036-5d741d8794b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591891488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1591891488
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3608651184
Short name T251
Test name
Test status
Simulation time 390826204 ps
CPU time 0.72 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 191836 kb
Host smart-a65be49a-3540-4079-81c6-0eb4c4f5eda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608651184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3608651184
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1815636173
Short name T51
Test name
Test status
Simulation time 45984053089 ps
CPU time 26.17 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 191896 kb
Host smart-74e06d43-58e3-4bdb-9c9a-7a0d7e512f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815636173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1815636173
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3512286945
Short name T18
Test name
Test status
Simulation time 7611111805 ps
CPU time 12.95 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:47:52 PM PDT 24
Peak memory 215724 kb
Host smart-776793d5-2065-4e5c-978a-32805d2e386e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512286945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3512286945
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2681091489
Short name T273
Test name
Test status
Simulation time 592876609 ps
CPU time 1.48 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:37 PM PDT 24
Peak memory 196536 kb
Host smart-b1321eac-3d44-43ba-86e3-dc0fa8effc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681091489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2681091489
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1630285149
Short name T249
Test name
Test status
Simulation time 26554562228 ps
CPU time 30.17 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 191892 kb
Host smart-76d0b91c-a715-46f7-896c-06b1f8c23113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630285149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1630285149
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3902062411
Short name T236
Test name
Test status
Simulation time 593420702 ps
CPU time 1.05 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 196856 kb
Host smart-872ffdf3-8853-4fcf-bf32-77e80d7a45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902062411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3902062411
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2003449378
Short name T215
Test name
Test status
Simulation time 19895921247 ps
CPU time 4.8 seconds
Started Aug 05 05:47:59 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 196908 kb
Host smart-393993b4-9416-42ad-bdb3-a8a22846f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003449378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2003449378
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3588843545
Short name T229
Test name
Test status
Simulation time 500069825 ps
CPU time 1.27 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 196640 kb
Host smart-330def68-4e55-4f1d-a0f5-226e6a669bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588843545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3588843545
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.920449764
Short name T245
Test name
Test status
Simulation time 36864583473 ps
CPU time 44.31 seconds
Started Aug 05 05:47:49 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 191808 kb
Host smart-1f7e94fc-a890-4e93-b780-0d0ed2390148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920449764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.920449764
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2084123145
Short name T243
Test name
Test status
Simulation time 508495050 ps
CPU time 0.75 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 191696 kb
Host smart-c835cbbf-be88-4c18-955f-200286c7ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084123145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2084123145
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3342825691
Short name T180
Test name
Test status
Simulation time 601185377 ps
CPU time 1 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 196624 kb
Host smart-a9923958-40fe-49b0-b7c0-310429f53bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342825691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3342825691
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1717115392
Short name T247
Test name
Test status
Simulation time 2984608809 ps
CPU time 1.61 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:47:49 PM PDT 24
Peak memory 191892 kb
Host smart-2adcf7b4-800e-4a6a-aab6-d3efef88112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717115392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1717115392
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1967155658
Short name T242
Test name
Test status
Simulation time 424473917 ps
CPU time 1.03 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:48:15 PM PDT 24
Peak memory 191828 kb
Host smart-05d746f4-6316-4070-b236-6506137a5ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967155658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1967155658
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3136722523
Short name T211
Test name
Test status
Simulation time 31071567814 ps
CPU time 11.42 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 191916 kb
Host smart-bbaf5ebd-fe77-49fe-9efe-269861f7fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136722523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3136722523
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.981839958
Short name T253
Test name
Test status
Simulation time 491587695 ps
CPU time 1 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 196616 kb
Host smart-ce36b02c-31fb-4448-81a9-5acb8f90ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981839958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.981839958
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.792431817
Short name T250
Test name
Test status
Simulation time 29661613431 ps
CPU time 11.37 seconds
Started Aug 05 05:47:48 PM PDT 24
Finished Aug 05 05:47:59 PM PDT 24
Peak memory 191764 kb
Host smart-46ac7ff5-5478-41e8-886e-01bd22a482de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792431817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.792431817
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1898899235
Short name T164
Test name
Test status
Simulation time 464359602 ps
CPU time 1.29 seconds
Started Aug 05 05:47:51 PM PDT 24
Finished Aug 05 05:47:52 PM PDT 24
Peak memory 191828 kb
Host smart-0c91ae2a-c56e-4246-af3e-c09604ca6e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898899235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1898899235
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1903564030
Short name T224
Test name
Test status
Simulation time 2347396975 ps
CPU time 1.62 seconds
Started Aug 05 05:47:52 PM PDT 24
Finished Aug 05 05:47:54 PM PDT 24
Peak memory 191884 kb
Host smart-df41abfd-9d68-45ed-9c1f-78e873d48bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903564030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1903564030
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2204533038
Short name T238
Test name
Test status
Simulation time 36862586284 ps
CPU time 3.24 seconds
Started Aug 05 05:47:52 PM PDT 24
Finished Aug 05 05:47:55 PM PDT 24
Peak memory 191876 kb
Host smart-7db7b490-6d39-465c-b603-ad90a0f8b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204533038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2204533038
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3570989946
Short name T265
Test name
Test status
Simulation time 458642148 ps
CPU time 0.61 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 191832 kb
Host smart-1ced80f6-1504-4170-bba4-9e2af2d1cc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570989946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3570989946
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2399500292
Short name T222
Test name
Test status
Simulation time 54778275224 ps
CPU time 18.38 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 191888 kb
Host smart-ecbe8ed7-4038-4cb8-a4b5-c17c9dcb9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399500292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2399500292
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4044997703
Short name T267
Test name
Test status
Simulation time 358968370 ps
CPU time 1.11 seconds
Started Aug 05 05:47:58 PM PDT 24
Finished Aug 05 05:47:59 PM PDT 24
Peak memory 191804 kb
Host smart-b3912dde-77d4-46c2-87de-e1328a83c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044997703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4044997703
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1810253108
Short name T227
Test name
Test status
Simulation time 24239478756 ps
CPU time 9.68 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 191920 kb
Host smart-9015d5f8-ef59-41fc-be40-ceb93eeb7d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810253108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1810253108
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.74325779
Short name T207
Test name
Test status
Simulation time 406988538 ps
CPU time 1.18 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:47:57 PM PDT 24
Peak memory 191828 kb
Host smart-1b12386e-89d5-4aeb-b8d5-3975a5425668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74325779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.74325779
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.217723274
Short name T175
Test name
Test status
Simulation time 385661437 ps
CPU time 0.89 seconds
Started Aug 05 05:47:44 PM PDT 24
Finished Aug 05 05:47:45 PM PDT 24
Peak memory 196620 kb
Host smart-6fe20d11-4d72-4d60-8a32-cb0992e86df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217723274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.217723274
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1102547425
Short name T261
Test name
Test status
Simulation time 59855864463 ps
CPU time 44.39 seconds
Started Aug 05 05:47:39 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 191888 kb
Host smart-3ebafdab-bb21-4e42-89ab-c9d41bfc7b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102547425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1102547425
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1451703163
Short name T21
Test name
Test status
Simulation time 7731293814 ps
CPU time 2.63 seconds
Started Aug 05 05:47:47 PM PDT 24
Finished Aug 05 05:47:50 PM PDT 24
Peak memory 215712 kb
Host smart-be3bcd3c-1088-447b-9af7-e28bfaa364f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451703163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1451703163
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2663549996
Short name T206
Test name
Test status
Simulation time 376163988 ps
CPU time 1.08 seconds
Started Aug 05 05:47:49 PM PDT 24
Finished Aug 05 05:47:51 PM PDT 24
Peak memory 191828 kb
Host smart-04de4a0f-c699-49b4-a88a-54cad22ece4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663549996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2663549996
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4214619291
Short name T196
Test name
Test status
Simulation time 414695957 ps
CPU time 0.66 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:15 PM PDT 24
Peak memory 196664 kb
Host smart-2053754b-403a-4ebd-99a6-89902fbe3fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214619291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4214619291
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3446492042
Short name T239
Test name
Test status
Simulation time 56618017909 ps
CPU time 75.91 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 191892 kb
Host smart-bd52da28-a0c2-4934-b212-29b649a6dc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446492042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3446492042
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4011790615
Short name T99
Test name
Test status
Simulation time 548542390 ps
CPU time 1.33 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:57 PM PDT 24
Peak memory 191764 kb
Host smart-937fd8b7-f3b3-465c-ae0e-7cf3f78317f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011790615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4011790615
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4225867796
Short name T30
Test name
Test status
Simulation time 56992047295 ps
CPU time 79.19 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 191868 kb
Host smart-8ca44231-5449-40b8-b321-85118d689dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225867796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4225867796
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.281177784
Short name T266
Test name
Test status
Simulation time 559487191 ps
CPU time 0.64 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 191820 kb
Host smart-7f2331f3-b5fe-406f-9cc9-c00405f37c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281177784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.281177784
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2589638462
Short name T257
Test name
Test status
Simulation time 3460266889 ps
CPU time 4.3 seconds
Started Aug 05 05:47:58 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 196676 kb
Host smart-52c995c7-6864-4c9f-b236-0f2298043c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589638462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2589638462
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3390996113
Short name T210
Test name
Test status
Simulation time 489084469 ps
CPU time 0.89 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:48:05 PM PDT 24
Peak memory 191916 kb
Host smart-c01f4f0c-bb4d-48ea-bd09-7db972f8242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390996113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3390996113
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1219908031
Short name T216
Test name
Test status
Simulation time 11700577494 ps
CPU time 14.89 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 191888 kb
Host smart-a5ea6c05-b4c4-4c2f-affb-949aca8b113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219908031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1219908031
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1313697924
Short name T272
Test name
Test status
Simulation time 470055559 ps
CPU time 1.16 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 196672 kb
Host smart-d28e2aec-060f-4b34-94f0-93a0fc2ceade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313697924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1313697924
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4047957824
Short name T75
Test name
Test status
Simulation time 29389269548 ps
CPU time 22.81 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 191784 kb
Host smart-353f2881-9227-4b7d-be04-2542e302eb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047957824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4047957824
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3686695090
Short name T260
Test name
Test status
Simulation time 426199447 ps
CPU time 0.73 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 191844 kb
Host smart-935daa8f-165f-49eb-98b8-7ab912eec663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686695090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3686695090
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.275054984
Short name T232
Test name
Test status
Simulation time 7985373977 ps
CPU time 12.2 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:48:17 PM PDT 24
Peak memory 196856 kb
Host smart-cc324454-79c6-40e5-b32d-bbd0a6c4dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275054984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.275054984
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.595212499
Short name T230
Test name
Test status
Simulation time 548374691 ps
CPU time 1.41 seconds
Started Aug 05 05:47:53 PM PDT 24
Finished Aug 05 05:47:54 PM PDT 24
Peak memory 196676 kb
Host smart-1a18a4f1-6461-434b-ac5a-ed54755d615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595212499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.595212499
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.492499047
Short name T278
Test name
Test status
Simulation time 36586144904 ps
CPU time 17.23 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 196880 kb
Host smart-c303762d-8166-493e-ae84-f4f4212b46a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492499047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.492499047
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.410279053
Short name T22
Test name
Test status
Simulation time 465615849 ps
CPU time 1.31 seconds
Started Aug 05 05:47:56 PM PDT 24
Finished Aug 05 05:47:57 PM PDT 24
Peak memory 191816 kb
Host smart-6a3492a0-4361-496e-97e4-4f634856075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410279053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.410279053
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.651151065
Short name T231
Test name
Test status
Simulation time 18982826281 ps
CPU time 6.68 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 191884 kb
Host smart-7a411de4-4046-4c49-b4c3-e73169e352ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651151065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.651151065
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2379821262
Short name T100
Test name
Test status
Simulation time 384394515 ps
CPU time 0.9 seconds
Started Aug 05 05:47:57 PM PDT 24
Finished Aug 05 05:47:58 PM PDT 24
Peak memory 191808 kb
Host smart-d61b07bf-0769-4d38-8c53-ed6f07e63711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379821262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2379821262
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2363173991
Short name T244
Test name
Test status
Simulation time 19585867113 ps
CPU time 6.85 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 191892 kb
Host smart-6cbd0294-83b2-4d01-ac28-023e82c14e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363173991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2363173991
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4031053303
Short name T255
Test name
Test status
Simulation time 450259833 ps
CPU time 0.73 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 191792 kb
Host smart-90bd8862-492f-4ffc-92f9-909237e6f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031053303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4031053303
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3206215721
Short name T203
Test name
Test status
Simulation time 21368933851 ps
CPU time 28.53 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 191808 kb
Host smart-1def7fdd-5b35-40df-9312-3ffb4199ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206215721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3206215721
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2382556656
Short name T270
Test name
Test status
Simulation time 611935388 ps
CPU time 0.79 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 191824 kb
Host smart-73ebabaa-f29f-4bf4-a610-75728eda5aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382556656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2382556656
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.714580265
Short name T53
Test name
Test status
Simulation time 23839187319 ps
CPU time 36.9 seconds
Started Aug 05 05:47:46 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 191892 kb
Host smart-58d1eada-4f33-4148-abab-12c36c9259ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714580265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.714580265
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2030397338
Short name T20
Test name
Test status
Simulation time 7769868894 ps
CPU time 3.87 seconds
Started Aug 05 05:47:59 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 215812 kb
Host smart-0bc442e5-25e9-4389-9e92-5410677e747d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030397338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2030397338
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2689080525
Short name T25
Test name
Test status
Simulation time 444474548 ps
CPU time 1.22 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 191788 kb
Host smart-2be9b755-0559-44fa-b716-8a69e942b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689080525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2689080525
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2974205141
Short name T61
Test name
Test status
Simulation time 57783124366 ps
CPU time 206.53 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:51:02 PM PDT 24
Peak memory 198480 kb
Host smart-c3c5a557-717d-456d-8a5d-1cf37e886f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974205141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2974205141
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3377111603
Short name T271
Test name
Test status
Simulation time 13764372342 ps
CPU time 20.91 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 196904 kb
Host smart-5d1360e8-8152-4e31-a7ac-a60f09ec61fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377111603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3377111603
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3665559220
Short name T248
Test name
Test status
Simulation time 508444812 ps
CPU time 0.8 seconds
Started Aug 05 05:48:11 PM PDT 24
Finished Aug 05 05:48:11 PM PDT 24
Peak memory 191796 kb
Host smart-110811e3-1c11-49c0-b7ff-e7c8a1cbc179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665559220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3665559220
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3050297028
Short name T276
Test name
Test status
Simulation time 4441065169 ps
CPU time 3.72 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 196856 kb
Host smart-64850ef3-47d1-4539-9ca5-ab66fc7bcf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050297028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3050297028
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.907536851
Short name T208
Test name
Test status
Simulation time 524906136 ps
CPU time 0.8 seconds
Started Aug 05 05:48:11 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 191788 kb
Host smart-dc8043bc-20f3-4745-9c43-d716f456442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907536851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.907536851
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1987207278
Short name T225
Test name
Test status
Simulation time 31150507220 ps
CPU time 10.96 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 196908 kb
Host smart-31a75f4f-c7e6-4dd8-8fd2-8d6578a8728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987207278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1987207278
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3598366209
Short name T1
Test name
Test status
Simulation time 355157839 ps
CPU time 1.11 seconds
Started Aug 05 05:48:31 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 191804 kb
Host smart-58addbdd-2999-493f-b23a-3def3818aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598366209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3598366209
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2141486222
Short name T234
Test name
Test status
Simulation time 52609014985 ps
CPU time 20.56 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:39 PM PDT 24
Peak memory 191828 kb
Host smart-957a6dca-606c-4c2e-a55c-e64f347146e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141486222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2141486222
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.116423299
Short name T213
Test name
Test status
Simulation time 554509416 ps
CPU time 0.75 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:17 PM PDT 24
Peak memory 191792 kb
Host smart-bebabbf4-97c8-4087-840e-2aa2bff5845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116423299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.116423299
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2344314794
Short name T218
Test name
Test status
Simulation time 41395786284 ps
CPU time 14.98 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 191792 kb
Host smart-8d92be0c-8d02-47d2-bd74-c0495c983098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344314794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2344314794
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1151936980
Short name T4
Test name
Test status
Simulation time 391515792 ps
CPU time 0.73 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 196684 kb
Host smart-3f800361-8558-419a-b9fb-eb6aa9c7c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151936980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1151936980
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1564499108
Short name T49
Test name
Test status
Simulation time 54399844279 ps
CPU time 41.66 seconds
Started Aug 05 05:48:26 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 191892 kb
Host smart-9bba9694-c97e-4eec-afa3-d3b39a2c870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564499108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1564499108
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2965692094
Short name T258
Test name
Test status
Simulation time 597528126 ps
CPU time 1.06 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 191820 kb
Host smart-337a5a40-dd49-4f8e-a744-584972b5dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965692094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2965692094
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1360690751
Short name T2
Test name
Test status
Simulation time 3829027447 ps
CPU time 6.16 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 196712 kb
Host smart-208c3011-ca99-4281-992d-06fe88dd7964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360690751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1360690751
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2413155542
Short name T89
Test name
Test status
Simulation time 418153696 ps
CPU time 0.76 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 191916 kb
Host smart-caffc29a-6dac-46b6-91cc-1cc550f661ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413155542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2413155542
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2542006662
Short name T11
Test name
Test status
Simulation time 27861520639 ps
CPU time 18.86 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 196824 kb
Host smart-30cfd479-b4ff-4f68-b721-86d7e64f45a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542006662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2542006662
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.408596251
Short name T3
Test name
Test status
Simulation time 398073618 ps
CPU time 0.72 seconds
Started Aug 05 05:48:03 PM PDT 24
Finished Aug 05 05:48:04 PM PDT 24
Peak memory 196656 kb
Host smart-eb6749ea-e83a-4e15-b6ac-8875511bbbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408596251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.408596251
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.726443527
Short name T268
Test name
Test status
Simulation time 30650165536 ps
CPU time 21.44 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 191892 kb
Host smart-d29faf2e-aa4f-49d7-b3b6-9dc39ed65e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726443527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.726443527
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1527417894
Short name T264
Test name
Test status
Simulation time 456619688 ps
CPU time 0.64 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 191820 kb
Host smart-10a7c1dc-144c-40da-99cb-f0a0dba200e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527417894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1527417894
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1952758561
Short name T12
Test name
Test status
Simulation time 33389399660 ps
CPU time 52.42 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 191868 kb
Host smart-7f90e18f-99ad-4791-b4bd-790e0dbc79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952758561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1952758561
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3172871749
Short name T212
Test name
Test status
Simulation time 546510284 ps
CPU time 0.79 seconds
Started Aug 05 05:48:10 PM PDT 24
Finished Aug 05 05:48:10 PM PDT 24
Peak memory 191824 kb
Host smart-ffb73031-fb3a-42f3-bdb4-32b61aae1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172871749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3172871749
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.422689024
Short name T54
Test name
Test status
Simulation time 497381089 ps
CPU time 0.69 seconds
Started Aug 05 05:47:37 PM PDT 24
Finished Aug 05 05:47:37 PM PDT 24
Peak memory 196724 kb
Host smart-67900c41-e9c9-4b7a-a923-31b527f85d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422689024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.422689024
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1122705163
Short name T275
Test name
Test status
Simulation time 32124986463 ps
CPU time 19.98 seconds
Started Aug 05 05:47:36 PM PDT 24
Finished Aug 05 05:47:56 PM PDT 24
Peak memory 191888 kb
Host smart-bff7ed4e-482f-40f2-8741-3d5cf9208a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122705163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1122705163
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3310693376
Short name T280
Test name
Test status
Simulation time 471855838 ps
CPU time 0.77 seconds
Started Aug 05 05:47:35 PM PDT 24
Finished Aug 05 05:47:36 PM PDT 24
Peak memory 191824 kb
Host smart-7a50ac52-93b0-4182-82de-e01deacbd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310693376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3310693376
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2964859595
Short name T220
Test name
Test status
Simulation time 5252340778 ps
CPU time 8.95 seconds
Started Aug 05 05:47:41 PM PDT 24
Finished Aug 05 05:47:50 PM PDT 24
Peak memory 191888 kb
Host smart-5c0cdeb3-de9c-4095-be1a-650c4e1db8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964859595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2964859595
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2848533306
Short name T209
Test name
Test status
Simulation time 480713501 ps
CPU time 1.18 seconds
Started Aug 05 05:47:54 PM PDT 24
Finished Aug 05 05:47:55 PM PDT 24
Peak memory 191836 kb
Host smart-2ad3fcf1-b00d-47d3-9989-09083ab9811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848533306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2848533306
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1223513490
Short name T202
Test name
Test status
Simulation time 6665551481 ps
CPU time 5.63 seconds
Started Aug 05 05:47:55 PM PDT 24
Finished Aug 05 05:48:00 PM PDT 24
Peak memory 196880 kb
Host smart-567ef957-2b69-4b97-a741-2609e0b2b4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223513490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1223513490
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.634456576
Short name T6
Test name
Test status
Simulation time 527659447 ps
CPU time 1 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 191836 kb
Host smart-1d174e9b-03db-47e4-8c0f-2bb9028dc317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634456576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.634456576
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3205620657
Short name T179
Test name
Test status
Simulation time 392343246 ps
CPU time 1.11 seconds
Started Aug 05 05:47:57 PM PDT 24
Finished Aug 05 05:47:58 PM PDT 24
Peak memory 196584 kb
Host smart-8fbaad91-6748-46dd-a972-03dc877b1cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205620657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3205620657
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2263068
Short name T269
Test name
Test status
Simulation time 29016051483 ps
CPU time 35.72 seconds
Started Aug 05 05:47:50 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 196924 kb
Host smart-1147f2c1-1c00-4f5b-93bc-bba79ccb711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2263068
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4105771116
Short name T259
Test name
Test status
Simulation time 446868451 ps
CPU time 0.94 seconds
Started Aug 05 05:48:01 PM PDT 24
Finished Aug 05 05:48:02 PM PDT 24
Peak memory 191832 kb
Host smart-1d9a94bb-7f8c-4311-860d-6a0bab6ee1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105771116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4105771116
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3568276838
Short name T233
Test name
Test status
Simulation time 39703177348 ps
CPU time 59.82 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 191888 kb
Host smart-54fcc231-333a-4852-bfbc-b1522dc6f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568276838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3568276838
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3451914025
Short name T7
Test name
Test status
Simulation time 706395477 ps
CPU time 0.63 seconds
Started Aug 05 05:48:00 PM PDT 24
Finished Aug 05 05:48:01 PM PDT 24
Peak memory 191784 kb
Host smart-bd4282ee-0237-4a18-9a25-bf3400ec7481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451914025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3451914025
Directory /workspace/9.aon_timer_smoke/latest
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