Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	32001	1		T1	10		T2	192		T3	12
bark[1]	329	1		T125	21		T51	47		T108	21
bark[2]	380	1		T35	21		T36	77		T171	30
bark[3]	698	1		T8	14		T14	21		T112	30
bark[4]	327	1		T48	21		T97	217		T163	14
bark[5]	606	1		T106	21		T48	31		T145	64
bark[6]	309	1		T48	7		T111	21		T108	26
bark[7]	684	1		T6	14		T15	21		T34	21
bark[8]	347	1		T139	21		T125	21		T51	35
bark[9]	332	1		T19	26		T36	43		T46	21
bark[10]	435	1		T92	40		T46	241		T112	21
bark[11]	239	1		T116	64		T108	21		T131	21
bark[12]	838	1		T48	24		T57	26		T132	220
bark[13]	439	1		T14	26		T106	21		T129	14
bark[14]	632	1		T35	35		T140	14		T112	21
bark[15]	722	1		T4	14		T19	21		T47	26
bark[16]	435	1		T5	21		T148	14		T133	60
bark[17]	307	1		T2	21		T35	21		T171	104
bark[18]	259	1		T14	45		T16	21		T152	26
bark[19]	755	1		T152	21		T169	14		T125	21
bark[20]	616	1		T17	14		T34	42		T35	26
bark[21]	681	1		T18	14		T34	14		T107	40
bark[22]	277	1		T19	21		T139	38		T99	35
bark[23]	421	1		T16	21		T133	21		T60	21
bark[24]	407	1		T2	30		T47	21		T151	21
bark[25]	832	1		T5	21		T14	21		T92	81
bark[26]	568	1		T16	21		T34	21		T160	102
bark[27]	386	1		T45	21		T152	66		T57	72
bark[28]	486	1		T35	26		T19	21		T94	14
bark[29]	396	1		T2	14		T45	14		T46	21
bark[30]	433	1		T19	135		T46	26		T49	86
bark[31]	428	1		T151	47		T181	14		T31	51
bark_0	4603	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	31298	1		T1	9		T2	243		T3	11
bite[1]	621	1		T16	21		T35	26		T171	104
bite[2]	1619	1		T14	21		T36	300		T49	85
bite[3]	178	1		T35	21		T112	30		T27	51
bite[4]	411	1		T106	21		T115	21		T97	216
bite[5]	533	1		T2	13		T4	13		T34	21
bite[6]	450	1		T47	21		T151	21		T112	21
bite[7]	441	1		T50	30		T125	21		T159	91
bite[8]	528	1		T16	21		T19	21		T152	21
bite[9]	345	1		T34	13		T35	26		T129	13
bite[10]	1008	1		T194	13		T51	210		T54	13
bite[11]	434	1		T34	21		T92	50		T46	21
bite[12]	670	1		T45	21		T152	40		T181	13
bite[13]	436	1		T34	21		T35	21		T19	21
bite[14]	73	1		T14	26		T125	21		T182	13
bite[15]	1019	1		T14	21		T48	31		T152	26
bite[16]	389	1		T19	25		T51	46		T103	270
bite[17]	335	1		T18	13		T144	13		T98	25
bite[18]	354	1		T15	42		T111	26		T99	35
bite[19]	390	1		T35	34		T106	21		T36	76
bite[20]	439	1		T19	134		T155	195		T99	21
bite[21]	442	1		T5	21		T45	13		T48	6
bite[22]	305	1		T16	22		T36	42		T193	13
bite[23]	273	1		T19	21		T57	21		T111	37
bite[24]	310	1		T94	13		T140	13		T48	21
bite[25]	453	1		T34	21		T46	240		T152	26
bite[26]	635	1		T16	21		T92	21		T171	30
bite[27]	338	1		T19	6		T46	25		T48	23
bite[28]	595	1		T6	13		T145	21		T51	42
bite[29]	258	1		T151	47		T167	66		T115	44
bite[30]	448	1		T8	13		T106	21		T107	40
bite[31]	478	1		T14	45		T47	25		T112	21
bite_0	5102	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43571	1		T1	17		T2	264		T3	19
auto[1]	8037	1		T14	53		T16	39		T34	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	995	1		T14	28		T15	2		T36	57
prescale[1]	640	1		T5	9		T19	19		T106	23
prescale[2]	1020	1		T15	53		T19	152		T36	45
prescale[3]	1206	1		T13	9		T19	71		T106	28
prescale[4]	820	1		T34	23		T19	40		T45	106
prescale[5]	798	1		T14	45		T19	23		T36	45
prescale[6]	756	1		T5	40		T107	33		T36	83
prescale[7]	671	1		T5	127		T36	36		T92	33
prescale[8]	1134	1		T11	9		T15	20		T36	19
prescale[9]	814	1		T9	9		T35	36		T107	42
prescale[10]	739	1		T16	19		T46	19		T47	165
prescale[11]	1445	1		T5	19		T15	41		T16	36
prescale[12]	1045	1		T14	23		T15	84		T35	49
prescale[13]	892	1		T5	2		T14	24		T36	55
prescale[14]	1128	1		T19	2		T36	219		T45	36
prescale[15]	573	1		T5	36		T19	19		T36	131
prescale[16]	723	1		T106	23		T36	9		T46	20
prescale[17]	713	1		T36	64		T45	57		T47	64
prescale[18]	723	1		T34	23		T45	33		T48	24
prescale[19]	670	1		T15	96		T36	57		T92	40
prescale[20]	1241	1		T2	28		T15	2		T36	55
prescale[21]	859	1		T19	40		T107	66		T47	312
prescale[22]	1454	1		T5	109		T15	104		T107	19
prescale[23]	958	1		T2	28		T36	59		T92	19
prescale[24]	656	1		T19	26		T45	98		T151	19
prescale[25]	731	1		T15	53		T34	28		T19	2
prescale[26]	490	1		T5	2		T34	41		T35	28
prescale[27]	518	1		T19	19		T36	19		T152	48
prescale[28]	574	1		T19	2		T107	19		T36	2
prescale[29]	935	1		T5	40		T16	37		T36	24
prescale[30]	565	1		T35	40		T107	19		T92	24
prescale[31]	900	1		T2	41		T3	9		T5	23
prescale_0	24222	1		T1	17		T2	167		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38416	1		T1	17		T2	179		T3	9
auto[1]	13192	1		T2	85		T3	10		T5	144

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51608	1		T1	17		T2	264		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30724	1		T1	12		T2	172		T3	14
wkup[1]	197	1		T19	42		T49	21		T112	21
wkup[2]	294	1		T34	15		T35	26		T45	21
wkup[3]	240	1		T36	21		T159	21		T163	15
wkup[4]	216	1		T36	21		T46	21		T57	30
wkup[5]	488	1		T48	21		T51	40		T155	21
wkup[6]	209	1		T36	42		T139	21		T99	6
wkup[7]	201	1		T48	35		T50	26		T171	21
wkup[8]	404	1		T16	24		T92	21		T46	21
wkup[9]	176	1		T106	21		T155	21		T26	51
wkup[10]	262	1		T15	21		T19	21		T46	21
wkup[11]	305	1		T47	21		T57	21		T60	21
wkup[12]	462	1		T19	21		T92	31		T48	21
wkup[13]	238	1		T17	15		T107	21		T92	21
wkup[14]	292	1		T34	21		T107	21		T36	42
wkup[15]	264	1		T14	21		T47	21		T50	30
wkup[16]	253	1		T15	33		T16	21		T36	21
wkup[17]	144	1		T45	30		T48	21		T171	21
wkup[18]	273	1		T35	26		T36	21		T45	21
wkup[19]	183	1		T6	15		T111	21		T26	21
wkup[20]	385	1		T19	21		T45	30		T49	31
wkup[21]	347	1		T48	21		T60	21		T155	8
wkup[22]	241	1		T19	21		T48	21		T116	21
wkup[23]	339	1		T36	21		T47	21		T48	42
wkup[24]	427	1		T14	26		T16	21		T19	29
wkup[25]	244	1		T2	21		T19	21		T171	21
wkup[26]	281	1		T15	31		T46	21		T112	30
wkup[27]	352	1		T19	8		T48	21		T50	30
wkup[28]	192	1		T169	15		T132	42		T26	21
wkup[29]	331	1		T36	21		T97	77		T57	26
wkup[30]	282	1		T5	8		T45	26		T48	21
wkup[31]	220	1		T36	21		T140	15		T48	60
wkup[32]	194	1		T19	21		T112	21		T115	20
wkup[33]	160	1		T48	26		T127	15		T132	26
wkup[34]	161	1		T2	30		T36	26		T151	21
wkup[35]	323	1		T35	15		T46	21		T50	15
wkup[36]	248	1		T2	15		T36	21		T47	21
wkup[37]	273	1		T36	21		T48	47		T125	21
wkup[38]	260	1		T34	21		T106	21		T45	21
wkup[39]	324	1		T47	21		T49	21		T98	21
wkup[40]	361	1		T16	21		T106	21		T36	30
wkup[41]	338	1		T35	21		T46	21		T48	21
wkup[42]	363	1		T46	42		T152	21		T167	21
wkup[43]	214	1		T19	21		T47	21		T160	15
wkup[44]	128	1		T167	21		T133	15		T27	21
wkup[45]	173	1		T152	21		T26	39		T138	26
wkup[46]	360	1		T47	21		T167	26		T49	21
wkup[47]	175	1		T19	21		T46	21		T159	21
wkup[48]	240	1		T5	21		T99	30		T166	30
wkup[49]	249	1		T45	8		T47	21		T48	42
wkup[50]	280	1		T49	21		T51	63		T164	30
wkup[51]	241	1		T5	15		T50	26		T132	15
wkup[52]	234	1		T14	21		T18	15		T46	21
wkup[53]	125	1		T2	21		T5	21		T35	21
wkup[54]	304	1		T92	21		T48	21		T50	21
wkup[55]	247	1		T35	21		T46	21		T47	26
wkup[56]	176	1		T116	21		T51	21		T59	21
wkup[57]	297	1		T5	21		T14	21		T48	42
wkup[58]	381	1		T8	15		T36	21		T46	21
wkup[59]	391	1		T4	15		T34	21		T36	21
wkup[60]	335	1		T15	42		T46	29		T47	42
wkup[61]	374	1		T19	30		T47	21		T48	21
wkup[62]	291	1		T5	21		T36	21		T47	30
wkup[63]	336	1		T47	21		T49	52		T57	21
wkup_0	3586	1		T1	5		T2	5		T3	5