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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.13 99.33 93.67 100.00 98.40 99.51 49.86


Total test records in report: 418
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T279 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.143945198 Aug 06 07:02:22 PM PDT 24 Aug 06 07:02:23 PM PDT 24 516324209 ps
T38 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4208756530 Aug 06 07:02:17 PM PDT 24 Aug 06 07:02:20 PM PDT 24 8896582940 ps
T280 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2723346387 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:25 PM PDT 24 466048677 ps
T39 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.66033637 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:34 PM PDT 24 512869229 ps
T44 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2290324549 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:43 PM PDT 24 1946181095 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3214066664 Aug 06 07:02:09 PM PDT 24 Aug 06 07:02:11 PM PDT 24 522089793 ps
T200 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2511883987 Aug 06 07:02:22 PM PDT 24 Aug 06 07:02:23 PM PDT 24 482902290 ps
T281 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2465205627 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 298901401 ps
T282 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1916465396 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 319875720 ps
T283 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3695198233 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:34 PM PDT 24 328609599 ps
T284 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1415596276 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:26 PM PDT 24 453884967 ps
T40 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1036813439 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:30 PM PDT 24 9062478070 ps
T285 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1243790873 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:34 PM PDT 24 442264302 ps
T286 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.298220861 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:25 PM PDT 24 443125848 ps
T287 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.854435290 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 441630583 ps
T288 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.304366382 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 284837846 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.707356749 Aug 06 07:02:19 PM PDT 24 Aug 06 07:02:20 PM PDT 24 305250376 ps
T84 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2203585892 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:34 PM PDT 24 1710063312 ps
T85 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1815899028 Aug 06 07:02:43 PM PDT 24 Aug 06 07:02:45 PM PDT 24 1252987155 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3961788283 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:32 PM PDT 24 440049739 ps
T291 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.183731956 Aug 06 07:02:38 PM PDT 24 Aug 06 07:02:39 PM PDT 24 501700176 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1483554236 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:28 PM PDT 24 439677128 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2242242852 Aug 06 07:02:14 PM PDT 24 Aug 06 07:02:15 PM PDT 24 306048809 ps
T64 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2357292236 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 488634801 ps
T86 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2781624936 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:27 PM PDT 24 2285577849 ps
T65 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1457541929 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:28 PM PDT 24 403888292 ps
T87 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1141869772 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:33 PM PDT 24 2015232109 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2537563352 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:25 PM PDT 24 428891641 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3289414516 Aug 06 07:02:13 PM PDT 24 Aug 06 07:02:14 PM PDT 24 509714257 ps
T294 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1016184942 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:24 PM PDT 24 536273114 ps
T295 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1646619718 Aug 06 07:02:17 PM PDT 24 Aug 06 07:02:18 PM PDT 24 523582586 ps
T296 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2691152994 Aug 06 07:02:39 PM PDT 24 Aug 06 07:02:40 PM PDT 24 438490447 ps
T297 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2371784473 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 351846880 ps
T41 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.504572360 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:43 PM PDT 24 8068342664 ps
T199 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2554364499 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:45 PM PDT 24 7937292789 ps
T298 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2024830211 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:34 PM PDT 24 324485574 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4253504497 Aug 06 07:02:12 PM PDT 24 Aug 06 07:02:13 PM PDT 24 627758550 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3925867309 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 311520056 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2203915894 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:35 PM PDT 24 416221313 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3507243381 Aug 06 07:02:14 PM PDT 24 Aug 06 07:02:15 PM PDT 24 1357770775 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.729593 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:32 PM PDT 24 517261041 ps
T304 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4281755964 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:29 PM PDT 24 384843379 ps
T305 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1718489103 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:36 PM PDT 24 394259625 ps
T306 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.540148798 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:32 PM PDT 24 350583871 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1559388683 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 353480214 ps
T308 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1946969133 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:31 PM PDT 24 824235818 ps
T309 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.442686412 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:35 PM PDT 24 4450895154 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2365899796 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 418244020 ps
T67 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3766919483 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:16 PM PDT 24 360099934 ps
T311 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.938748549 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:32 PM PDT 24 456674791 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3979850140 Aug 06 07:02:19 PM PDT 24 Aug 06 07:02:21 PM PDT 24 448197444 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3462264814 Aug 06 07:02:14 PM PDT 24 Aug 06 07:02:15 PM PDT 24 414281893 ps
T88 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2341689302 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 2301386709 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3137964611 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:16 PM PDT 24 392525088 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.723664651 Aug 06 07:02:28 PM PDT 24 Aug 06 07:02:29 PM PDT 24 608890363 ps
T315 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2101729202 Aug 06 07:02:20 PM PDT 24 Aug 06 07:02:22 PM PDT 24 428636495 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.327888258 Aug 06 07:02:13 PM PDT 24 Aug 06 07:02:13 PM PDT 24 438742599 ps
T197 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1860409806 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:36 PM PDT 24 8291512097 ps
T317 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1542638990 Aug 06 07:02:19 PM PDT 24 Aug 06 07:02:21 PM PDT 24 560083529 ps
T318 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1714136975 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 431819281 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4205036814 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:26 PM PDT 24 561214343 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2449004880 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:26 PM PDT 24 1326822045 ps
T321 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2076052018 Aug 06 07:02:12 PM PDT 24 Aug 06 07:02:13 PM PDT 24 285676284 ps
T69 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1834916762 Aug 06 07:02:21 PM PDT 24 Aug 06 07:02:23 PM PDT 24 467001033 ps
T322 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1933454707 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 326409785 ps
T89 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3881716449 Aug 06 07:02:26 PM PDT 24 Aug 06 07:02:28 PM PDT 24 1116216251 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2256655708 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 646234893 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1283000882 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:20 PM PDT 24 7270423141 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3531915089 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 543148038 ps
T325 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1855783395 Aug 06 07:02:28 PM PDT 24 Aug 06 07:02:29 PM PDT 24 497298072 ps
T71 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1590352135 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:28 PM PDT 24 292441875 ps
T326 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2262708050 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:33 PM PDT 24 415104560 ps
T327 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.441224212 Aug 06 07:02:21 PM PDT 24 Aug 06 07:02:27 PM PDT 24 7985998815 ps
T328 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3855754360 Aug 06 07:02:43 PM PDT 24 Aug 06 07:02:44 PM PDT 24 483179077 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3058555468 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 630140296 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4131038751 Aug 06 07:02:19 PM PDT 24 Aug 06 07:02:20 PM PDT 24 436406483 ps
T331 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.12627629 Aug 06 07:02:20 PM PDT 24 Aug 06 07:02:21 PM PDT 24 2642308385 ps
T332 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1617626176 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:34 PM PDT 24 2631540981 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4062557718 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:34 PM PDT 24 1485523350 ps
T334 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.91585245 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:35 PM PDT 24 489705646 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1968680591 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:33 PM PDT 24 1042472341 ps
T336 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.440579270 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:37 PM PDT 24 419195950 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.405207874 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:30 PM PDT 24 8800692950 ps
T338 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2195853559 Aug 06 07:02:42 PM PDT 24 Aug 06 07:02:44 PM PDT 24 438478435 ps
T339 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2684208384 Aug 06 07:02:26 PM PDT 24 Aug 06 07:02:28 PM PDT 24 450559068 ps
T340 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3965541707 Aug 06 07:02:40 PM PDT 24 Aug 06 07:02:42 PM PDT 24 428523324 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4204365146 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:17 PM PDT 24 467397003 ps
T342 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2112871970 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 509877907 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.761508431 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:24 PM PDT 24 579430482 ps
T344 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3677472952 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 383190487 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1659092846 Aug 06 07:02:22 PM PDT 24 Aug 06 07:02:25 PM PDT 24 515608243 ps
T346 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1038854701 Aug 06 07:02:38 PM PDT 24 Aug 06 07:02:39 PM PDT 24 335363095 ps
T347 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3953210329 Aug 06 07:02:26 PM PDT 24 Aug 06 07:02:27 PM PDT 24 407379713 ps
T348 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2603341474 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:19 PM PDT 24 1272346585 ps
T349 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3732392259 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:25 PM PDT 24 2392445929 ps
T350 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1484923294 Aug 06 07:02:22 PM PDT 24 Aug 06 07:02:23 PM PDT 24 363779286 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2949921777 Aug 06 07:02:21 PM PDT 24 Aug 06 07:02:24 PM PDT 24 688509407 ps
T74 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2330581232 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:29 PM PDT 24 7251637758 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2649941346 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:27 PM PDT 24 585924115 ps
T72 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1871310 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:26 PM PDT 24 408238662 ps
T353 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.591317021 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:32 PM PDT 24 367744137 ps
T354 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3014272987 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 485219722 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.786444272 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 416710514 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3451722404 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:26 PM PDT 24 529755394 ps
T357 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1831610418 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:35 PM PDT 24 2755606130 ps
T358 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3208076168 Aug 06 07:02:38 PM PDT 24 Aug 06 07:02:39 PM PDT 24 301603425 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.298942949 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:17 PM PDT 24 555737908 ps
T360 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3011777493 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:32 PM PDT 24 331485043 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1535597444 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:29 PM PDT 24 338213114 ps
T198 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.849415412 Aug 06 07:02:34 PM PDT 24 Aug 06 07:02:45 PM PDT 24 7523179739 ps
T362 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.427042620 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:32 PM PDT 24 495213709 ps
T363 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.97587346 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:32 PM PDT 24 415810407 ps
T364 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2200365609 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 338426707 ps
T365 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3141254856 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:30 PM PDT 24 442121332 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3276062070 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:24 PM PDT 24 426189166 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1875913319 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:25 PM PDT 24 531710952 ps
T368 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1946940373 Aug 06 07:02:24 PM PDT 24 Aug 06 07:02:28 PM PDT 24 8234060355 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2365364388 Aug 06 07:02:18 PM PDT 24 Aug 06 07:02:19 PM PDT 24 492100858 ps
T370 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1490668194 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:40 PM PDT 24 8121825833 ps
T371 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2497512640 Aug 06 07:02:31 PM PDT 24 Aug 06 07:02:33 PM PDT 24 1622334186 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4023933629 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:40 PM PDT 24 11489549224 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.525204722 Aug 06 07:02:17 PM PDT 24 Aug 06 07:02:21 PM PDT 24 8318753507 ps
T374 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1748422071 Aug 06 07:02:09 PM PDT 24 Aug 06 07:02:10 PM PDT 24 477007467 ps
T375 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4110789151 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 475508073 ps
T376 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1950763582 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:24 PM PDT 24 324493100 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1114487017 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:15 PM PDT 24 834299457 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1983357313 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:24 PM PDT 24 959583669 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4165928588 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 392837560 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2994356723 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:30 PM PDT 24 360598113 ps
T381 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1492379305 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 340513846 ps
T382 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.930041855 Aug 06 07:02:19 PM PDT 24 Aug 06 07:02:21 PM PDT 24 554779665 ps
T383 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4097086911 Aug 06 07:02:27 PM PDT 24 Aug 06 07:02:29 PM PDT 24 645961498 ps
T384 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3094473706 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:40 PM PDT 24 462840931 ps
T385 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1109145925 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 484396431 ps
T386 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2815659383 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 343688512 ps
T387 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3007349190 Aug 06 07:02:22 PM PDT 24 Aug 06 07:02:25 PM PDT 24 321440173 ps
T388 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.607118351 Aug 06 07:02:16 PM PDT 24 Aug 06 07:02:19 PM PDT 24 2430810238 ps
T73 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1440339959 Aug 06 07:02:28 PM PDT 24 Aug 06 07:02:29 PM PDT 24 305066782 ps
T389 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.799046210 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 445133370 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4210355390 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:22 PM PDT 24 4471510041 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2394072314 Aug 06 07:02:43 PM PDT 24 Aug 06 07:02:45 PM PDT 24 498645559 ps
T392 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3091822211 Aug 06 07:02:34 PM PDT 24 Aug 06 07:02:46 PM PDT 24 7632751550 ps
T393 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1016286309 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:34 PM PDT 24 352833524 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3078945914 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:16 PM PDT 24 445440217 ps
T395 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4111037605 Aug 06 07:02:39 PM PDT 24 Aug 06 07:02:40 PM PDT 24 520165986 ps
T396 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2921132673 Aug 06 07:02:28 PM PDT 24 Aug 06 07:02:29 PM PDT 24 507607682 ps
T397 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3188702748 Aug 06 07:02:34 PM PDT 24 Aug 06 07:02:35 PM PDT 24 318878604 ps
T398 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.576195721 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:17 PM PDT 24 2205668637 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3738554214 Aug 06 07:02:15 PM PDT 24 Aug 06 07:02:18 PM PDT 24 13847318736 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.847084866 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:38 PM PDT 24 7913313785 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1329012643 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:41 PM PDT 24 2295024625 ps
T402 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1727288015 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:30 PM PDT 24 365318558 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1918615105 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:48 PM PDT 24 13805068497 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3422706785 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:26 PM PDT 24 514680741 ps
T405 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.938177842 Aug 06 07:02:25 PM PDT 24 Aug 06 07:02:32 PM PDT 24 4378437551 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1640375130 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:47 PM PDT 24 8425796171 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2143681222 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 555522748 ps
T408 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.448222202 Aug 06 07:02:35 PM PDT 24 Aug 06 07:02:41 PM PDT 24 4091104321 ps
T409 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.705236919 Aug 06 07:02:33 PM PDT 24 Aug 06 07:02:34 PM PDT 24 498652521 ps
T410 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.843550750 Aug 06 07:02:23 PM PDT 24 Aug 06 07:02:31 PM PDT 24 4435766968 ps
T411 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2383207778 Aug 06 07:02:37 PM PDT 24 Aug 06 07:02:38 PM PDT 24 403930319 ps
T412 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2798700991 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:31 PM PDT 24 4306331591 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.244749671 Aug 06 07:02:10 PM PDT 24 Aug 06 07:02:18 PM PDT 24 2333901620 ps
T414 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1206024401 Aug 06 07:02:30 PM PDT 24 Aug 06 07:02:31 PM PDT 24 436225438 ps
T415 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.745512613 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:34 PM PDT 24 523537153 ps
T416 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3174040150 Aug 06 07:02:32 PM PDT 24 Aug 06 07:02:33 PM PDT 24 481321253 ps
T417 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.959793653 Aug 06 07:02:28 PM PDT 24 Aug 06 07:02:29 PM PDT 24 1134853131 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2696962979 Aug 06 07:02:29 PM PDT 24 Aug 06 07:02:30 PM PDT 24 454724773 ps

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2413761890
Short name T5
Test name
Test status
Simulation time 38392357527 ps
CPU time 161.9 seconds
Started Aug 06 07:01:44 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 214148 kb
Host smart-5f2be700-8a41-461f-ab63-7481b454f7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413761890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2413761890
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3617505181
Short name T15
Test name
Test status
Simulation time 30803175682 ps
CPU time 226.06 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:06:10 PM PDT 24
Peak memory 198948 kb
Host smart-862eefaf-f5fc-489f-884e-7cf5d4a11ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617505181 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3617505181
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4208756530
Short name T38
Test name
Test status
Simulation time 8896582940 ps
CPU time 3.33 seconds
Started Aug 06 07:02:17 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 198428 kb
Host smart-8ce293c5-c050-4d0b-be21-9924ad78de00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208756530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.4208756530
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3670435351
Short name T51
Test name
Test status
Simulation time 213985046535 ps
CPU time 323.96 seconds
Started Aug 06 07:01:51 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 209820 kb
Host smart-124e1326-7337-46d3-84b4-0d3b05f72421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670435351 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3670435351
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1152607374
Short name T48
Test name
Test status
Simulation time 1304885320897 ps
CPU time 503.76 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:10:35 PM PDT 24
Peak memory 204316 kb
Host smart-ec596674-9540-49b9-9726-d7b3d7c0c90e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152607374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1152607374
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2333846063
Short name T2
Test name
Test status
Simulation time 133943147001 ps
CPU time 96.59 seconds
Started Aug 06 07:02:10 PM PDT 24
Finished Aug 06 07:03:47 PM PDT 24
Peak memory 193204 kb
Host smart-94d5c64a-fa94-4dbe-977d-1fb5d835ba30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333846063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2333846063
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2568670508
Short name T81
Test name
Test status
Simulation time 190492746496 ps
CPU time 372.63 seconds
Started Aug 06 07:01:55 PM PDT 24
Finished Aug 06 07:08:08 PM PDT 24
Peak memory 210884 kb
Host smart-0bd7d129-c1b5-4a73-99dc-d5119cc04eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568670508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2568670508
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1662050230
Short name T36
Test name
Test status
Simulation time 1250010234132 ps
CPU time 559.66 seconds
Started Aug 06 07:01:54 PM PDT 24
Finished Aug 06 07:11:14 PM PDT 24
Peak memory 204416 kb
Host smart-a375d0f9-3296-4b93-9b8d-3ece1b774b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662050230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1662050230
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1229337280
Short name T104
Test name
Test status
Simulation time 50989911985 ps
CPU time 348.03 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 208004 kb
Host smart-b1e9566a-5208-4ca8-a7bd-627c9a41f992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229337280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1229337280
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1954476939
Short name T132
Test name
Test status
Simulation time 54182986950 ps
CPU time 127.31 seconds
Started Aug 06 07:01:46 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 198776 kb
Host smart-b0a801c2-92d4-43ec-b9a3-c4b24e803aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954476939 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1954476939
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4007344260
Short name T99
Test name
Test status
Simulation time 108332527951 ps
CPU time 950.88 seconds
Started Aug 06 07:01:48 PM PDT 24
Finished Aug 06 07:17:39 PM PDT 24
Peak memory 208976 kb
Host smart-67bbda82-9188-41d3-972f-52c509a5f890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007344260 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4007344260
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3142628382
Short name T22
Test name
Test status
Simulation time 8073632225 ps
CPU time 6.15 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:01:32 PM PDT 24
Peak memory 215768 kb
Host smart-e09afc7a-d1ae-49d3-9f31-439fb5a3acf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142628382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3142628382
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.185875391
Short name T142
Test name
Test status
Simulation time 321812621604 ps
CPU time 660.39 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:13:04 PM PDT 24
Peak memory 214380 kb
Host smart-aa63b2cb-8f87-4364-857b-1c236fe1a3ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185875391 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.185875391
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1481392416
Short name T121
Test name
Test status
Simulation time 44761293044 ps
CPU time 33.96 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:36 PM PDT 24
Peak memory 193248 kb
Host smart-7b8d7123-9f69-4e45-98af-1c64826e38fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481392416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1481392416
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.319412698
Short name T109
Test name
Test status
Simulation time 80458521606 ps
CPU time 25.82 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:56 PM PDT 24
Peak memory 193288 kb
Host smart-00a4df4a-3f24-433b-9a16-b84872f8f4e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319412698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.319412698
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3288202408
Short name T26
Test name
Test status
Simulation time 229394871129 ps
CPU time 347.46 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:08:12 PM PDT 24
Peak memory 210540 kb
Host smart-13215eba-7a8c-4002-93d9-928cac649aee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288202408 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3288202408
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.727934452
Short name T102
Test name
Test status
Simulation time 17836378504 ps
CPU time 133.91 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:04:13 PM PDT 24
Peak memory 198808 kb
Host smart-4dc7e4fa-3553-4b75-ba7e-994809db18a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727934452 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.727934452
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1457541929
Short name T65
Test name
Test status
Simulation time 403888292 ps
CPU time 0.73 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 193220 kb
Host smart-aa2ecf2e-cefd-4467-881e-9fe89c15ffc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457541929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1457541929
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3806894023
Short name T19
Test name
Test status
Simulation time 301319511046 ps
CPU time 565.1 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:11:49 PM PDT 24
Peak memory 213112 kb
Host smart-08db5569-b46e-442d-9462-b229d3d6bc94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806894023 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3806894023
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2506298949
Short name T111
Test name
Test status
Simulation time 39411717911 ps
CPU time 15.17 seconds
Started Aug 06 07:01:48 PM PDT 24
Finished Aug 06 07:02:04 PM PDT 24
Peak memory 198528 kb
Host smart-b62398f1-1fc7-44f1-8d53-0a014f4a11e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506298949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2506298949
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3825973323
Short name T146
Test name
Test status
Simulation time 110587746064 ps
CPU time 39.79 seconds
Started Aug 06 07:02:21 PM PDT 24
Finished Aug 06 07:03:01 PM PDT 24
Peak memory 198596 kb
Host smart-cab01789-b76b-4968-92ed-6897a7d7f196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825973323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3825973323
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1793528858
Short name T98
Test name
Test status
Simulation time 74168968858 ps
CPU time 286.02 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:06:45 PM PDT 24
Peak memory 198808 kb
Host smart-96a4d4a6-8be4-433b-b09d-0be4e61d69c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793528858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1793528858
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2638591830
Short name T123
Test name
Test status
Simulation time 158919272130 ps
CPU time 252.2 seconds
Started Aug 06 07:02:07 PM PDT 24
Finished Aug 06 07:06:19 PM PDT 24
Peak memory 201492 kb
Host smart-1c602380-dc62-4935-97b2-69148830c657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638591830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2638591830
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.742932643
Short name T46
Test name
Test status
Simulation time 32310562245 ps
CPU time 354.1 seconds
Started Aug 06 07:01:34 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 206800 kb
Host smart-5debe0d2-998d-4e2c-9878-3333b5fafb06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742932643 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.742932643
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2721479504
Short name T115
Test name
Test status
Simulation time 224242041377 ps
CPU time 314.5 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:07:11 PM PDT 24
Peak memory 192100 kb
Host smart-fcc731a4-0489-4fac-abfe-453da6502260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721479504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2721479504
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2157918736
Short name T45
Test name
Test status
Simulation time 566066294804 ps
CPU time 390.23 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:08:20 PM PDT 24
Peak memory 214868 kb
Host smart-3856a13b-dd15-47b2-960a-4d90a6dd5e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157918736 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2157918736
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.563528461
Short name T122
Test name
Test status
Simulation time 221546521176 ps
CPU time 154.71 seconds
Started Aug 06 07:02:08 PM PDT 24
Finished Aug 06 07:04:43 PM PDT 24
Peak memory 193184 kb
Host smart-329521c6-662c-4e08-8a9a-3c01a6041df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563528461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.563528461
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2301973842
Short name T150
Test name
Test status
Simulation time 91719039502 ps
CPU time 138.91 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 192744 kb
Host smart-09375dc6-1b24-4d06-84c5-ab31cca75a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301973842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2301973842
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3694193944
Short name T133
Test name
Test status
Simulation time 120838491300 ps
CPU time 180.16 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 192188 kb
Host smart-b290c008-52f7-4bc2-a329-704e7790b1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694193944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3694193944
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1332095384
Short name T110
Test name
Test status
Simulation time 67995094742 ps
CPU time 7.12 seconds
Started Aug 06 07:02:02 PM PDT 24
Finished Aug 06 07:02:09 PM PDT 24
Peak memory 184736 kb
Host smart-93d6cb93-8937-4041-a585-34ccc12556d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332095384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1332095384
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4229640422
Short name T100
Test name
Test status
Simulation time 64084366025 ps
CPU time 604.26 seconds
Started Aug 06 07:01:34 PM PDT 24
Finished Aug 06 07:11:39 PM PDT 24
Peak memory 203984 kb
Host smart-d967f540-dbb2-419a-91e0-22242ff40452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229640422 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4229640422
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2826969304
Short name T34
Test name
Test status
Simulation time 132691273250 ps
CPU time 51.86 seconds
Started Aug 06 07:01:31 PM PDT 24
Finished Aug 06 07:02:23 PM PDT 24
Peak memory 198500 kb
Host smart-482a919c-41fa-45c6-bb7f-38f677b012ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826969304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2826969304
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.349705279
Short name T120
Test name
Test status
Simulation time 73927698790 ps
CPU time 147.09 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:04:43 PM PDT 24
Peak memory 199044 kb
Host smart-f56adf8a-f6d5-4d99-92b0-b86fb4204144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349705279 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.349705279
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2540294383
Short name T35
Test name
Test status
Simulation time 212206461834 ps
CPU time 167.68 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:04:44 PM PDT 24
Peak memory 193316 kb
Host smart-293c842c-6571-4477-9b9f-8a61e554ba30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540294383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2540294383
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4151733929
Short name T161
Test name
Test status
Simulation time 389070268191 ps
CPU time 796.94 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:15:14 PM PDT 24
Peak memory 215140 kb
Host smart-f208d2fc-1459-4d4b-ad18-e8c65e21f946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151733929 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4151733929
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1224585413
Short name T116
Test name
Test status
Simulation time 357774084002 ps
CPU time 115.03 seconds
Started Aug 06 07:02:06 PM PDT 24
Finished Aug 06 07:04:01 PM PDT 24
Peak memory 198468 kb
Host smart-bd1b90ac-26da-41af-85e8-5f1eabef5db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224585413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1224585413
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.126727665
Short name T125
Test name
Test status
Simulation time 130364736070 ps
CPU time 49.11 seconds
Started Aug 06 07:01:28 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 193192 kb
Host smart-414f7134-1a42-4457-bac2-70f0b523703b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126727665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.126727665
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2183802636
Short name T47
Test name
Test status
Simulation time 347924981887 ps
CPU time 632.64 seconds
Started Aug 06 07:01:49 PM PDT 24
Finished Aug 06 07:12:21 PM PDT 24
Peak memory 214132 kb
Host smart-2be1cb6f-b994-446f-9298-63db18406e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183802636 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2183802636
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2713952669
Short name T128
Test name
Test status
Simulation time 218374299227 ps
CPU time 399.78 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:08:36 PM PDT 24
Peak memory 211484 kb
Host smart-314d6120-f651-405f-85f3-b496d4867f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713952669 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2713952669
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2776852037
Short name T103
Test name
Test status
Simulation time 59596782229 ps
CPU time 441.7 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:08:47 PM PDT 24
Peak memory 201524 kb
Host smart-41c5e16a-be28-430f-95ff-12d1849aa01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776852037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2776852037
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2206200816
Short name T138
Test name
Test status
Simulation time 169335028797 ps
CPU time 266.09 seconds
Started Aug 06 07:02:07 PM PDT 24
Finished Aug 06 07:06:33 PM PDT 24
Peak memory 198516 kb
Host smart-99965c82-daa6-4f72-9f67-19efd0a5e178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206200816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2206200816
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.206716131
Short name T118
Test name
Test status
Simulation time 67053039906 ps
CPU time 92.02 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:03:28 PM PDT 24
Peak memory 193200 kb
Host smart-ff77cbf3-6be2-4914-9ebb-a2f85da582b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206716131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.206716131
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4151573196
Short name T137
Test name
Test status
Simulation time 93483151083 ps
CPU time 54.27 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:03:10 PM PDT 24
Peak memory 198448 kb
Host smart-21ef7bbb-bdb3-4854-977d-527ab28f9396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151573196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4151573196
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2271450856
Short name T126
Test name
Test status
Simulation time 318691643507 ps
CPU time 107.56 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 193208 kb
Host smart-eb3731fc-98d5-4844-8531-4067374430b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271450856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2271450856
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1693106432
Short name T155
Test name
Test status
Simulation time 15951962620 ps
CPU time 121.96 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:03:59 PM PDT 24
Peak memory 198668 kb
Host smart-5b3583a3-db7d-470a-9a20-d1107f36388e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693106432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1693106432
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2293325568
Short name T170
Test name
Test status
Simulation time 61984061275 ps
CPU time 642.79 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:12:59 PM PDT 24
Peak memory 214748 kb
Host smart-bad539ad-307c-4860-9f54-02fbc46a768d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293325568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2293325568
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1190972624
Short name T113
Test name
Test status
Simulation time 86407718731 ps
CPU time 162.71 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:04:30 PM PDT 24
Peak memory 200012 kb
Host smart-0f7fbe33-3efd-44ab-8d77-ab12f18d7509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190972624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1190972624
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3519256706
Short name T108
Test name
Test status
Simulation time 202772587266 ps
CPU time 273.02 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:06:31 PM PDT 24
Peak memory 198512 kb
Host smart-226a81d1-56ab-4063-a542-70a4139e0d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519256706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3519256706
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3967948953
Short name T114
Test name
Test status
Simulation time 226868481061 ps
CPU time 300.32 seconds
Started Aug 06 07:02:04 PM PDT 24
Finished Aug 06 07:07:04 PM PDT 24
Peak memory 198580 kb
Host smart-5fe2b20d-1870-4e33-ac45-9bde4e048ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967948953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3967948953
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1584321122
Short name T134
Test name
Test status
Simulation time 92328757111 ps
CPU time 617.73 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:12:29 PM PDT 24
Peak memory 205768 kb
Host smart-c5cdc4e7-34be-4ae8-9468-1b1041f244b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584321122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1584321122
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1203010857
Short name T50
Test name
Test status
Simulation time 61803016134 ps
CPU time 281.59 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:06:31 PM PDT 24
Peak memory 198776 kb
Host smart-ad057dee-9fef-4813-87e5-9632e5f16cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203010857 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1203010857
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.575052549
Short name T57
Test name
Test status
Simulation time 151395345770 ps
CPU time 111.34 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 192200 kb
Host smart-4b9b708b-07e9-4db0-88df-b53560229da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575052549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.575052549
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3262012706
Short name T60
Test name
Test status
Simulation time 50874673247 ps
CPU time 19.16 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 193268 kb
Host smart-a5fa897a-2683-4766-9d12-322febe9742e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262012706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3262012706
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2325883930
Short name T27
Test name
Test status
Simulation time 291625871401 ps
CPU time 468.57 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:09:42 PM PDT 24
Peak memory 193460 kb
Host smart-e27117a1-55e8-4989-8c03-a8f70e356ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325883930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2325883930
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.222229607
Short name T165
Test name
Test status
Simulation time 41067852112 ps
CPU time 298.63 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:07:08 PM PDT 24
Peak memory 206928 kb
Host smart-ea2042d0-4392-4764-ba21-1db092a2d69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222229607 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.222229607
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2245231451
Short name T151
Test name
Test status
Simulation time 328123278712 ps
CPU time 454.62 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:09:34 PM PDT 24
Peak memory 192992 kb
Host smart-632dfeca-2084-4f33-80e2-ac40936ef652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245231451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2245231451
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3300386434
Short name T145
Test name
Test status
Simulation time 27539577114 ps
CPU time 287 seconds
Started Aug 06 07:01:45 PM PDT 24
Finished Aug 06 07:06:32 PM PDT 24
Peak memory 207032 kb
Host smart-4e914add-2408-4439-87a4-7f1fda1cf96e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300386434 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3300386434
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2499184839
Short name T168
Test name
Test status
Simulation time 52462250740 ps
CPU time 393.11 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:08:47 PM PDT 24
Peak memory 208672 kb
Host smart-564cd45e-73f3-404d-82a3-0f4a74d80a2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499184839 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2499184839
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1169796322
Short name T59
Test name
Test status
Simulation time 103595654445 ps
CPU time 215.23 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:05:33 PM PDT 24
Peak memory 208628 kb
Host smart-44bb6f68-4056-4c05-bf68-39e80ce6973c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169796322 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1169796322
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1085827253
Short name T49
Test name
Test status
Simulation time 100808020207 ps
CPU time 247.44 seconds
Started Aug 06 07:01:44 PM PDT 24
Finished Aug 06 07:05:51 PM PDT 24
Peak memory 201272 kb
Host smart-74d5c877-4cbd-437f-aa73-6e63f4c9a618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085827253 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1085827253
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2191649817
Short name T61
Test name
Test status
Simulation time 127618703896 ps
CPU time 308.47 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:07:05 PM PDT 24
Peak memory 212452 kb
Host smart-b1f85844-8036-49c0-9497-cc1fac4ccf5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191649817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2191649817
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1705287218
Short name T112
Test name
Test status
Simulation time 66602385896 ps
CPU time 138.69 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:04:16 PM PDT 24
Peak memory 206844 kb
Host smart-cda2d744-da7d-44e1-a669-6c2ef669db41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705287218 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1705287218
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.646805819
Short name T131
Test name
Test status
Simulation time 126016867295 ps
CPU time 197.86 seconds
Started Aug 06 07:01:54 PM PDT 24
Finished Aug 06 07:05:12 PM PDT 24
Peak memory 193468 kb
Host smart-1a5fb14d-2ef3-4086-abd8-ff6f9fa61b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646805819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.646805819
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2354752710
Short name T166
Test name
Test status
Simulation time 79192805639 ps
CPU time 224.42 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:05:56 PM PDT 24
Peak memory 200312 kb
Host smart-1cf361f8-ade0-49e6-9517-c154d0bc4f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354752710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2354752710
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3189266421
Short name T92
Test name
Test status
Simulation time 213552093200 ps
CPU time 148.4 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:04:16 PM PDT 24
Peak memory 198564 kb
Host smart-273f68ed-f9fa-4a16-813b-1523d874bbe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189266421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3189266421
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3496752193
Short name T124
Test name
Test status
Simulation time 582831544 ps
CPU time 1.35 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:01:55 PM PDT 24
Peak memory 197144 kb
Host smart-87081e1b-5429-4e98-b74f-af725db560bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496752193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3496752193
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1089964146
Short name T158
Test name
Test status
Simulation time 404853783662 ps
CPU time 750.31 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:14:45 PM PDT 24
Peak memory 215180 kb
Host smart-7b931bf2-a2fc-4828-8181-69068994f5e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089964146 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1089964146
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1735324382
Short name T176
Test name
Test status
Simulation time 674954919397 ps
CPU time 914.27 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:17:11 PM PDT 24
Peak memory 193188 kb
Host smart-e0e60f17-cc30-413b-994e-e7c268017ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735324382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1735324382
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3273106986
Short name T149
Test name
Test status
Simulation time 38105418294 ps
CPU time 53.59 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:03:20 PM PDT 24
Peak memory 192184 kb
Host smart-becb6b13-75ab-49eb-aa60-71ae75b049b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273106986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3273106986
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3908375679
Short name T130
Test name
Test status
Simulation time 527337065 ps
CPU time 1.46 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 196948 kb
Host smart-c7eaf074-bbe5-4339-a9f7-fcbeefc8c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908375679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3908375679
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1097866394
Short name T144
Test name
Test status
Simulation time 479007563 ps
CPU time 0.75 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:01:47 PM PDT 24
Peak memory 196948 kb
Host smart-0e6b0e39-5ef5-42b5-a4a9-4c6a6b54a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097866394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1097866394
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2122810949
Short name T101
Test name
Test status
Simulation time 87984116482 ps
CPU time 758.77 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:14:04 PM PDT 24
Peak memory 207152 kb
Host smart-e8f6a0b4-f240-49cd-8b28-60db4484edb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122810949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2122810949
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1182194493
Short name T152
Test name
Test status
Simulation time 142685274797 ps
CPU time 186.7 seconds
Started Aug 06 07:01:51 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 192184 kb
Host smart-43ef20e1-877b-4137-9d06-cd2e979165de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182194493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1182194493
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1847684363
Short name T97
Test name
Test status
Simulation time 24780009032 ps
CPU time 161.83 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:05:05 PM PDT 24
Peak memory 206984 kb
Host smart-d3f14ee4-6c5b-44f8-9168-f6776b880d10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847684363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1847684363
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1840455651
Short name T106
Test name
Test status
Simulation time 48281705784 ps
CPU time 19.2 seconds
Started Aug 06 07:02:13 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 198516 kb
Host smart-11c4aa19-c861-4507-b283-2c38dc192958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840455651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1840455651
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2351605477
Short name T28
Test name
Test status
Simulation time 389276087 ps
CPU time 0.74 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 197028 kb
Host smart-9c9f80c2-66f7-4186-b3f8-9f9d20a24260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351605477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2351605477
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2928129556
Short name T80
Test name
Test status
Simulation time 402161203 ps
CPU time 1.21 seconds
Started Aug 06 07:01:49 PM PDT 24
Finished Aug 06 07:01:51 PM PDT 24
Peak memory 196936 kb
Host smart-90eb3534-e8b5-4a2d-b3aa-bb75d34cdf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928129556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2928129556
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1543657054
Short name T136
Test name
Test status
Simulation time 113724523403 ps
CPU time 182.27 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 206844 kb
Host smart-aa162efd-0c3e-4db1-b4dc-1e237c7ce8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543657054 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1543657054
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1349149760
Short name T117
Test name
Test status
Simulation time 533321286 ps
CPU time 1.34 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 197044 kb
Host smart-3d1f84a6-f3ea-49fa-b52f-b93b07200a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349149760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1349149760
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3138795966
Short name T127
Test name
Test status
Simulation time 429190214 ps
CPU time 1.22 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 197036 kb
Host smart-a08f19b2-e17e-406f-9398-62f6b3fe24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138795966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3138795966
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.153059237
Short name T139
Test name
Test status
Simulation time 179743373422 ps
CPU time 284.78 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:06:59 PM PDT 24
Peak memory 184840 kb
Host smart-2063ece7-6a4f-4ac5-bfdc-53a5aa3711bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153059237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.153059237
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1627875739
Short name T140
Test name
Test status
Simulation time 479925172 ps
CPU time 0.78 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 196980 kb
Host smart-2eb386d1-7e1c-43d2-8844-f91575604c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627875739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1627875739
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.916397106
Short name T156
Test name
Test status
Simulation time 535704319 ps
CPU time 1.03 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 196900 kb
Host smart-8d58d8e9-925b-4e25-982b-ce26a0b72b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916397106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.916397106
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1816537159
Short name T16
Test name
Test status
Simulation time 145709527054 ps
CPU time 224.79 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:05:41 PM PDT 24
Peak memory 198552 kb
Host smart-2a84ac93-ba52-4ae3-87b0-51d2ef6cd922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816537159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1816537159
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3584278625
Short name T17
Test name
Test status
Simulation time 594913558 ps
CPU time 0.83 seconds
Started Aug 06 07:02:04 PM PDT 24
Finished Aug 06 07:02:05 PM PDT 24
Peak memory 196976 kb
Host smart-5d307f70-a2ff-4c1b-81a6-93032be09439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584278625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3584278625
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2574907529
Short name T179
Test name
Test status
Simulation time 329027755959 ps
CPU time 229.62 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:05:53 PM PDT 24
Peak memory 198476 kb
Host smart-2b1e501f-99ed-4730-9dd1-c9c1638e91b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574907529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2574907529
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.35235403
Short name T159
Test name
Test status
Simulation time 110891134046 ps
CPU time 160.25 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 198596 kb
Host smart-e99ce781-16a6-49dd-b59a-accdf5b68c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35235403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_al
l.35235403
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2004783937
Short name T129
Test name
Test status
Simulation time 384669876 ps
CPU time 1.25 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 196788 kb
Host smart-3aa1e814-d5c4-4fe3-adef-00d9b68ef142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004783937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2004783937
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3254141801
Short name T147
Test name
Test status
Simulation time 32526275222 ps
CPU time 167.15 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:05:03 PM PDT 24
Peak memory 206848 kb
Host smart-22a5cecf-c03a-49f5-974a-f5f164eff71e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254141801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3254141801
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.633707474
Short name T94
Test name
Test status
Simulation time 485431531 ps
CPU time 0.94 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 196984 kb
Host smart-dfae96d2-28ab-43ee-b6b2-5d6c23123729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633707474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.633707474
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1839887778
Short name T30
Test name
Test status
Simulation time 469378630 ps
CPU time 1.22 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 197024 kb
Host smart-5a1a32b0-d70e-4b8e-bce9-95c47b02221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839887778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1839887778
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.70820368
Short name T148
Test name
Test status
Simulation time 400939437 ps
CPU time 0.9 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:14 PM PDT 24
Peak memory 197024 kb
Host smart-4233a1f5-cd49-4c3c-af9f-108686780b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70820368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.70820368
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1235053504
Short name T175
Test name
Test status
Simulation time 110516283225 ps
CPU time 164.92 seconds
Started Aug 06 07:01:48 PM PDT 24
Finished Aug 06 07:04:33 PM PDT 24
Peak memory 198448 kb
Host smart-ec832075-66c3-4524-8612-9192f51d6baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235053504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1235053504
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2072680172
Short name T14
Test name
Test status
Simulation time 74062893564 ps
CPU time 17.64 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 198280 kb
Host smart-dd68e220-e84c-4534-a104-c00e11dc32c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072680172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2072680172
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.356950943
Short name T171
Test name
Test status
Simulation time 141061460311 ps
CPU time 55.73 seconds
Started Aug 06 07:01:54 PM PDT 24
Finished Aug 06 07:02:50 PM PDT 24
Peak memory 192188 kb
Host smart-918a09ad-b936-48ca-91f9-558f7389f058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356950943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.356950943
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3291969454
Short name T6
Test name
Test status
Simulation time 595751930 ps
CPU time 0.87 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 196892 kb
Host smart-4664bbdc-9990-43d1-ad56-41153ab49b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291969454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3291969454
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.289819705
Short name T31
Test name
Test status
Simulation time 175337975917 ps
CPU time 123.9 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:04:01 PM PDT 24
Peak memory 192052 kb
Host smart-28df797f-c2bd-4898-a32e-c982cbdc8dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289819705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.289819705
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3606288889
Short name T75
Test name
Test status
Simulation time 134761638855 ps
CPU time 11.55 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 192164 kb
Host smart-ed87e82a-1a49-4d1e-88e7-2db1d67e4802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606288889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3606288889
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2053470170
Short name T188
Test name
Test status
Simulation time 1042498014386 ps
CPU time 834.43 seconds
Started Aug 06 07:02:05 PM PDT 24
Finished Aug 06 07:16:00 PM PDT 24
Peak memory 198532 kb
Host smart-1aa77920-9fc7-4f92-b3ea-33842f4e8918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053470170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2053470170
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1366385707
Short name T54
Test name
Test status
Simulation time 574929486 ps
CPU time 1.49 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 196852 kb
Host smart-83a5cc29-b996-4e3e-8eb8-02693e3008f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366385707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1366385707
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2474847620
Short name T160
Test name
Test status
Simulation time 975641695759 ps
CPU time 1457.15 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:26:40 PM PDT 24
Peak memory 198500 kb
Host smart-214d75e1-a3e3-448f-8e29-92e70e86f9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474847620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2474847620
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3979492483
Short name T143
Test name
Test status
Simulation time 529226500 ps
CPU time 0.7 seconds
Started Aug 06 07:01:34 PM PDT 24
Finished Aug 06 07:01:35 PM PDT 24
Peak memory 196696 kb
Host smart-2d23f397-1392-4d75-927a-94d4eea52057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979492483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3979492483
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1733246563
Short name T154
Test name
Test status
Simulation time 475078217 ps
CPU time 0.74 seconds
Started Aug 06 07:01:33 PM PDT 24
Finished Aug 06 07:01:34 PM PDT 24
Peak memory 196116 kb
Host smart-3aba510c-bf7f-4ee1-a343-81834b6680ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733246563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1733246563
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2925918277
Short name T107
Test name
Test status
Simulation time 325944367283 ps
CPU time 152.63 seconds
Started Aug 06 07:01:30 PM PDT 24
Finished Aug 06 07:04:02 PM PDT 24
Peak memory 198496 kb
Host smart-495bbbac-28b2-4e88-ab87-3bc1df09ade2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925918277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2925918277
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1446378960
Short name T4
Test name
Test status
Simulation time 545127331 ps
CPU time 0.75 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:01:50 PM PDT 24
Peak memory 196896 kb
Host smart-0c21bd81-2fca-416d-bf2b-97c04e826bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446378960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1446378960
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3236215740
Short name T189
Test name
Test status
Simulation time 575065116 ps
CPU time 0.82 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:02:12 PM PDT 24
Peak memory 196880 kb
Host smart-3432a3f0-4942-43b6-acd0-310f85aec5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236215740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3236215740
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.669309114
Short name T141
Test name
Test status
Simulation time 406122712891 ps
CPU time 616.39 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:12:19 PM PDT 24
Peak memory 193208 kb
Host smart-bec4bf03-e851-4de0-b620-cb202879c3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669309114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.669309114
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1155403369
Short name T194
Test name
Test status
Simulation time 521045744 ps
CPU time 1.13 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:01:59 PM PDT 24
Peak memory 196924 kb
Host smart-343ede93-5671-4f46-861a-77cabb913fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155403369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1155403369
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1458558914
Short name T119
Test name
Test status
Simulation time 585164822 ps
CPU time 1.32 seconds
Started Aug 06 07:01:22 PM PDT 24
Finished Aug 06 07:01:24 PM PDT 24
Peak memory 196940 kb
Host smart-487624de-cb96-4820-b1b1-c44c71065356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458558914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1458558914
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.150667962
Short name T187
Test name
Test status
Simulation time 470884753 ps
CPU time 0.94 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 197032 kb
Host smart-a30b2ffd-89f1-4ddd-ba48-80bcf90d3be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150667962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.150667962
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1998900700
Short name T193
Test name
Test status
Simulation time 539720509 ps
CPU time 0.79 seconds
Started Aug 06 07:02:07 PM PDT 24
Finished Aug 06 07:02:08 PM PDT 24
Peak memory 197016 kb
Host smart-213af6a2-73a4-48e1-b393-eb42585c13fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998900700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1998900700
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.756571980
Short name T167
Test name
Test status
Simulation time 465865005194 ps
CPU time 322.83 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:07:32 PM PDT 24
Peak memory 192196 kb
Host smart-88d6d390-1cbc-42a3-a56f-0cb36fd68bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756571980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.756571980
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1833122661
Short name T164
Test name
Test status
Simulation time 195100963107 ps
CPU time 296.44 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 193064 kb
Host smart-fa18ead7-ff7f-40e7-9f30-e50ae7290419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833122661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1833122661
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.328742796
Short name T162
Test name
Test status
Simulation time 21817358931 ps
CPU time 124.97 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:03:57 PM PDT 24
Peak memory 206996 kb
Host smart-930e2b57-d8cb-4233-acd6-806e54dfde97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328742796 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.328742796
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4098141570
Short name T190
Test name
Test status
Simulation time 565356686 ps
CPU time 0.82 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:01:31 PM PDT 24
Peak memory 196972 kb
Host smart-18f53c53-14ad-4e38-82a9-18b0fd3be025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098141570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4098141570
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3002836485
Short name T196
Test name
Test status
Simulation time 542694335 ps
CPU time 0.83 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 197028 kb
Host smart-37ffb5da-7197-4e51-b1d6-0af0d07fc549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002836485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3002836485
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2772348886
Short name T32
Test name
Test status
Simulation time 504899000 ps
CPU time 1.23 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:02:00 PM PDT 24
Peak memory 196920 kb
Host smart-5d40d976-4942-4bbe-a61d-5b3dca133b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772348886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2772348886
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1469921994
Short name T18
Test name
Test status
Simulation time 390458104 ps
CPU time 1.25 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 196908 kb
Host smart-04a25bcb-d757-4cb7-8fe9-943d42d97eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469921994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1469921994
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2469780761
Short name T135
Test name
Test status
Simulation time 593530405 ps
CPU time 1.45 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 196936 kb
Host smart-55c348a7-e65c-471e-9a41-a78f169da079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469780761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2469780761
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.528978584
Short name T56
Test name
Test status
Simulation time 394175849 ps
CPU time 0.72 seconds
Started Aug 06 07:01:33 PM PDT 24
Finished Aug 06 07:01:34 PM PDT 24
Peak memory 196884 kb
Host smart-d77525a7-c041-4728-918b-3cc597af16f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528978584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.528978584
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.405207874
Short name T337
Test name
Test status
Simulation time 8800692950 ps
CPU time 13.48 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 198376 kb
Host smart-1025df3d-cef4-4809-a4d4-c35396c52190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405207874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.405207874
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2627138393
Short name T178
Test name
Test status
Simulation time 163801620567 ps
CPU time 59.3 seconds
Started Aug 06 07:01:24 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 192128 kb
Host smart-0320a7c5-47f9-43eb-96bb-b8057d680c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627138393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2627138393
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1825018237
Short name T183
Test name
Test status
Simulation time 579433394 ps
CPU time 1.04 seconds
Started Aug 06 07:01:28 PM PDT 24
Finished Aug 06 07:01:29 PM PDT 24
Peak memory 196920 kb
Host smart-7075757e-65fc-49ca-9052-5c230e9bf14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825018237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1825018237
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.800995457
Short name T153
Test name
Test status
Simulation time 544230422 ps
CPU time 0.76 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 196984 kb
Host smart-c5396b2b-994c-40a1-8986-3e611637f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800995457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.800995457
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1552334524
Short name T185
Test name
Test status
Simulation time 410188862 ps
CPU time 0.73 seconds
Started Aug 06 07:01:33 PM PDT 24
Finished Aug 06 07:01:34 PM PDT 24
Peak memory 195980 kb
Host smart-1b271908-8840-4901-969a-91c4cd0487d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552334524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1552334524
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.307698637
Short name T186
Test name
Test status
Simulation time 388054556 ps
CPU time 1.12 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:01 PM PDT 24
Peak memory 196928 kb
Host smart-83e41a3d-8836-487f-b16b-4c32cc57564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307698637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.307698637
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1573633026
Short name T184
Test name
Test status
Simulation time 527311983 ps
CPU time 0.77 seconds
Started Aug 06 07:02:02 PM PDT 24
Finished Aug 06 07:02:03 PM PDT 24
Peak memory 196924 kb
Host smart-33edd38e-7d00-4358-9243-854f94f71804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573633026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1573633026
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4207756905
Short name T163
Test name
Test status
Simulation time 393897035 ps
CPU time 0.8 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:01 PM PDT 24
Peak memory 197196 kb
Host smart-18a81a37-7705-43d7-9799-7cbbcb776fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207756905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4207756905
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1619953561
Short name T173
Test name
Test status
Simulation time 604996987 ps
CPU time 0.78 seconds
Started Aug 06 07:01:30 PM PDT 24
Finished Aug 06 07:01:31 PM PDT 24
Peak memory 196964 kb
Host smart-50ce489c-075e-44bf-a857-5f8d7dd1d76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619953561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1619953561
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3803668621
Short name T8
Test name
Test status
Simulation time 564123346 ps
CPU time 1.46 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:03 PM PDT 24
Peak memory 196988 kb
Host smart-7ac79ba0-4d1d-49c4-a896-74c69e22dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803668621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3803668621
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1830352986
Short name T78
Test name
Test status
Simulation time 543332525 ps
CPU time 1.33 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:53 PM PDT 24
Peak memory 196900 kb
Host smart-eac43e13-5f83-435e-90a6-ab0c4a34494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830352986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1830352986
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.432690911
Short name T169
Test name
Test status
Simulation time 440358249 ps
CPU time 1.31 seconds
Started Aug 06 07:02:08 PM PDT 24
Finished Aug 06 07:02:09 PM PDT 24
Peak memory 196888 kb
Host smart-9e7b94aa-3921-4367-a803-2d96a57f09ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432690911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.432690911
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2449877189
Short name T191
Test name
Test status
Simulation time 523978490 ps
CPU time 1.07 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 196932 kb
Host smart-d07c06cd-c0f4-4c9d-ac2a-a531a35c6ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449877189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2449877189
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1452280634
Short name T174
Test name
Test status
Simulation time 520103039 ps
CPU time 1.42 seconds
Started Aug 06 07:01:46 PM PDT 24
Finished Aug 06 07:01:47 PM PDT 24
Peak memory 196912 kb
Host smart-7625087d-4c39-4e6e-a544-c4e6bb9ae81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452280634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1452280634
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3058555468
Short name T329
Test name
Test status
Simulation time 630140296 ps
CPU time 1.63 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 194308 kb
Host smart-9699fb33-9cfb-426f-aba4-e5b20c4d33dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058555468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3058555468
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1283000882
Short name T323
Test name
Test status
Simulation time 7270423141 ps
CPU time 3.99 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 192236 kb
Host smart-54407c14-5578-4a3e-811e-2a5d21d1962b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283000882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1283000882
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1983357313
Short name T378
Test name
Test status
Simulation time 959583669 ps
CPU time 0.94 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 193004 kb
Host smart-919022d0-1534-4833-acac-f4274195e054
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983357313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1983357313
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3925867309
Short name T300
Test name
Test status
Simulation time 311520056 ps
CPU time 0.88 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 195076 kb
Host smart-d30a2734-f02c-4997-9747-faddcabb3d76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925867309 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3925867309
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3137964611
Short name T68
Test name
Test status
Simulation time 392525088 ps
CPU time 0.77 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 194012 kb
Host smart-f41c12e9-b228-4c2d-9595-71d7aad83c29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137964611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3137964611
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1916465396
Short name T282
Test name
Test status
Simulation time 319875720 ps
CPU time 0.66 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 183788 kb
Host smart-1c50b9fb-f24f-47dd-a605-a11c5a3dea40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916465396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1916465396
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2365899796
Short name T310
Test name
Test status
Simulation time 418244020 ps
CPU time 1.05 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 183684 kb
Host smart-7a1c41cc-4c05-4f6b-8c77-9c62eed62cf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365899796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2365899796
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2723346387
Short name T280
Test name
Test status
Simulation time 466048677 ps
CPU time 0.6 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 183680 kb
Host smart-dcfbc719-2ca0-4335-80f4-06f60cc1d8e9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723346387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2723346387
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.607118351
Short name T388
Test name
Test status
Simulation time 2430810238 ps
CPU time 3.12 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 193884 kb
Host smart-183cd12e-10f0-428d-83e4-c18fd1402c77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607118351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.607118351
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1415596276
Short name T284
Test name
Test status
Simulation time 453884967 ps
CPU time 1.96 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 198604 kb
Host smart-09abaacc-b5c3-4697-8cb5-026b8af8dcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415596276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1415596276
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1875913319
Short name T367
Test name
Test status
Simulation time 531710952 ps
CPU time 1.25 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 194244 kb
Host smart-f6dd830c-8a3a-4482-9fb1-51bd76ddf738
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875913319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1875913319
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1918615105
Short name T403
Test name
Test status
Simulation time 13805068497 ps
CPU time 18.08 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:48 PM PDT 24
Peak memory 192244 kb
Host smart-9c81bc62-ee71-4af3-adbf-c6eaa6ebce5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918615105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1918615105
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1567332488
Short name T42
Test name
Test status
Simulation time 799351263 ps
CPU time 1.68 seconds
Started Aug 06 07:02:21 PM PDT 24
Finished Aug 06 07:02:22 PM PDT 24
Peak memory 193128 kb
Host smart-6f1b3ad7-559f-4581-8a98-58de33ee1e14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567332488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1567332488
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1547303465
Short name T37
Test name
Test status
Simulation time 406349388 ps
CPU time 0.9 seconds
Started Aug 06 07:02:20 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 197168 kb
Host smart-4eaca020-dada-4bed-b8ec-74655edff1bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547303465 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1547303465
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.930041855
Short name T382
Test name
Test status
Simulation time 554779665 ps
CPU time 1.36 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 193984 kb
Host smart-5898d5b1-de79-443e-910b-2371deedaf3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930041855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.930041855
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1646619718
Short name T295
Test name
Test status
Simulation time 523582586 ps
CPU time 0.82 seconds
Started Aug 06 07:02:17 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 183748 kb
Host smart-2863e55f-f264-4d0a-9cf8-448ed0197b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646619718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1646619718
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.298220861
Short name T286
Test name
Test status
Simulation time 443125848 ps
CPU time 1.14 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 183692 kb
Host smart-54d21e58-8b1e-4a40-8a4e-a16000eea881
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298220861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.298220861
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2365364388
Short name T369
Test name
Test status
Simulation time 492100858 ps
CPU time 0.68 seconds
Started Aug 06 07:02:18 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 183652 kb
Host smart-da8fc612-05cb-42b3-8f8f-6915d9c15a1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365364388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2365364388
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2781624936
Short name T86
Test name
Test status
Simulation time 2285577849 ps
CPU time 1.94 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 195064 kb
Host smart-ad5e30fd-2012-4ea1-a955-7d79c30c8558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781624936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2781624936
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1659092846
Short name T345
Test name
Test status
Simulation time 515608243 ps
CPU time 2.2 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 198648 kb
Host smart-3573eb7d-a856-4a6e-9b5e-abc66aec371c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659092846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1659092846
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4210355390
Short name T390
Test name
Test status
Simulation time 4471510041 ps
CPU time 7.27 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:22 PM PDT 24
Peak memory 198160 kb
Host smart-8351b3dd-c5f4-4275-8f84-a19240e99179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210355390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4210355390
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3873693556
Short name T43
Test name
Test status
Simulation time 489127982 ps
CPU time 1.04 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 198424 kb
Host smart-798eb183-ba5e-48d6-8f25-0122442a1cfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873693556 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3873693556
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4165928588
Short name T379
Test name
Test status
Simulation time 392837560 ps
CPU time 1.15 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 192996 kb
Host smart-0da06853-aaf3-4e7f-9f7b-8298ab554654
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165928588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4165928588
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.761508431
Short name T343
Test name
Test status
Simulation time 579430482 ps
CPU time 0.6 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 193016 kb
Host smart-bbc34e20-fbf7-46a3-9dfe-ca70cc6e20a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761508431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.761508431
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2497512640
Short name T371
Test name
Test status
Simulation time 1622334186 ps
CPU time 2.6 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 193668 kb
Host smart-9f421156-55b7-4523-8c73-1ad0609d7b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497512640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2497512640
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.745512613
Short name T415
Test name
Test status
Simulation time 523537153 ps
CPU time 1.55 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 198596 kb
Host smart-8a746a09-44fb-4756-80f4-b834c9397ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745512613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.745512613
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.849415412
Short name T198
Test name
Test status
Simulation time 7523179739 ps
CPU time 11.78 seconds
Started Aug 06 07:02:34 PM PDT 24
Finished Aug 06 07:02:45 PM PDT 24
Peak memory 198340 kb
Host smart-58491271-2290-4783-9a0a-7e5e6c0332db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849415412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.849415412
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4205036814
Short name T319
Test name
Test status
Simulation time 561214343 ps
CPU time 1.56 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 196284 kb
Host smart-d1826975-336b-49c7-835d-32f434bb8290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205036814 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4205036814
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2143681222
Short name T407
Test name
Test status
Simulation time 555522748 ps
CPU time 0.76 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 192040 kb
Host smart-813c9e73-c788-4f1c-a008-cae4fd907ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143681222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2143681222
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1933454707
Short name T322
Test name
Test status
Simulation time 326409785 ps
CPU time 0.68 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 193016 kb
Host smart-6d2cadec-41cb-4a2c-92e7-415e84f9d22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933454707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1933454707
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3881716449
Short name T89
Test name
Test status
Simulation time 1116216251 ps
CPU time 1.9 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 194000 kb
Host smart-1d7d2133-b18a-406e-8647-4354785dee47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881716449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3881716449
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2815659383
Short name T386
Test name
Test status
Simulation time 343688512 ps
CPU time 1.28 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 198428 kb
Host smart-91024f09-1507-471e-991a-1a271963123c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815659383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2815659383
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3091822211
Short name T392
Test name
Test status
Simulation time 7632751550 ps
CPU time 12.69 seconds
Started Aug 06 07:02:34 PM PDT 24
Finished Aug 06 07:02:46 PM PDT 24
Peak memory 198148 kb
Host smart-cc4648bb-01ac-4df1-87be-13126160c0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091822211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3091822211
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1016286309
Short name T393
Test name
Test status
Simulation time 352833524 ps
CPU time 0.77 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 196168 kb
Host smart-a78ac96e-3c2a-4bd2-b02e-807c703d82e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016286309 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1016286309
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3011777493
Short name T360
Test name
Test status
Simulation time 331485043 ps
CPU time 0.65 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 192996 kb
Host smart-762758cd-b2de-4980-a560-c2b8b49aa9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011777493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3011777493
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1855783395
Short name T325
Test name
Test status
Simulation time 497298072 ps
CPU time 0.96 seconds
Started Aug 06 07:02:28 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 183748 kb
Host smart-b7288b10-2648-4c98-8c14-2ac9e8346357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855783395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1855783395
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4062557718
Short name T333
Test name
Test status
Simulation time 1485523350 ps
CPU time 1.44 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 193796 kb
Host smart-d5497727-6b6a-44b6-9c59-5091744806b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062557718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4062557718
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1718489103
Short name T305
Test name
Test status
Simulation time 394259625 ps
CPU time 2.84 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:36 PM PDT 24
Peak memory 198684 kb
Host smart-4a8abc43-a494-4b77-9500-4f13f281b9df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718489103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1718489103
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.938177842
Short name T405
Test name
Test status
Simulation time 4378437551 ps
CPU time 6.88 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 198092 kb
Host smart-eb20b9db-6674-4e26-b961-167fcea012f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938177842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.938177842
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2696962979
Short name T418
Test name
Test status
Simulation time 454724773 ps
CPU time 0.85 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 196296 kb
Host smart-7b27c2f3-1a75-4c6d-855a-ee83f0be80be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696962979 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2696962979
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1440339959
Short name T73
Test name
Test status
Simulation time 305066782 ps
CPU time 0.79 seconds
Started Aug 06 07:02:28 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 193300 kb
Host smart-e0b8028a-22e3-4a07-8a36-5f48ea77c732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440339959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1440339959
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1950763582
Short name T376
Test name
Test status
Simulation time 324493100 ps
CPU time 0.84 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 183740 kb
Host smart-fc76a22d-be42-42e3-9eab-90a89c15b48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950763582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1950763582
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1329012643
Short name T401
Test name
Test status
Simulation time 2295024625 ps
CPU time 7.99 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:41 PM PDT 24
Peak memory 195232 kb
Host smart-452ceacd-339c-49ec-bfaa-63994a700f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329012643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1329012643
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1946969133
Short name T308
Test name
Test status
Simulation time 824235818 ps
CPU time 1.74 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 198588 kb
Host smart-797c6342-58cd-438a-8d90-8add54b67bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946969133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1946969133
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1860409806
Short name T197
Test name
Test status
Simulation time 8291512097 ps
CPU time 3.03 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:36 PM PDT 24
Peak memory 198132 kb
Host smart-97e71b8e-c7b8-46ed-b5eb-9c507664758b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860409806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1860409806
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1016184942
Short name T294
Test name
Test status
Simulation time 536273114 ps
CPU time 0.91 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 198352 kb
Host smart-0fde901b-13cd-451c-821a-a83eb2966e2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016184942 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1016184942
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.786444272
Short name T355
Test name
Test status
Simulation time 416710514 ps
CPU time 0.9 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 193088 kb
Host smart-62726bbc-0908-4125-b91a-fb3288f73e0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786444272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.786444272
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4110789151
Short name T375
Test name
Test status
Simulation time 475508073 ps
CPU time 1.23 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 183700 kb
Host smart-6c25c7a2-54d7-42d7-b746-e80deef8c7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110789151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4110789151
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3732392259
Short name T349
Test name
Test status
Simulation time 2392445929 ps
CPU time 1.12 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 195176 kb
Host smart-87ccadcd-a50b-48d4-8542-86b0b93c3f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732392259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3732392259
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2203915894
Short name T301
Test name
Test status
Simulation time 416221313 ps
CPU time 2.55 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:35 PM PDT 24
Peak memory 198652 kb
Host smart-9786c5e6-1bf2-4a92-9f53-2db1068f0864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203915894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2203915894
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1946940373
Short name T368
Test name
Test status
Simulation time 8234060355 ps
CPU time 3.85 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 198276 kb
Host smart-64fc01cc-8f42-4c34-82a5-70d2662d15c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946940373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1946940373
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2994356723
Short name T380
Test name
Test status
Simulation time 360598113 ps
CPU time 0.86 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 197816 kb
Host smart-92c80c35-22cb-493f-bf5a-babc41dfde64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994356723 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2994356723
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1590352135
Short name T71
Test name
Test status
Simulation time 292441875 ps
CPU time 0.66 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 192992 kb
Host smart-893592a3-81c0-4911-8e00-253c88fffc33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590352135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1590352135
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.729593
Short name T303
Test name
Test status
Simulation time 517261041 ps
CPU time 0.62 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 183796 kb
Host smart-c5c6026d-d85e-403e-ac7d-bf3cf1cb136c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.729593
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1617626176
Short name T332
Test name
Test status
Simulation time 2631540981 ps
CPU time 4.29 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 191912 kb
Host smart-6069ecc9-fba8-4e37-89d3-5cb0fcdbd5fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617626176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1617626176
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1206024401
Short name T414
Test name
Test status
Simulation time 436225438 ps
CPU time 1.69 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 198392 kb
Host smart-88968648-cc33-4fc5-aa51-38c125efb35a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206024401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1206024401
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.504572360
Short name T41
Test name
Test status
Simulation time 8068342664 ps
CPU time 13.37 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:43 PM PDT 24
Peak memory 198188 kb
Host smart-38c106b6-61cc-436d-9068-66d220e20a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504572360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.504572360
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.705236919
Short name T409
Test name
Test status
Simulation time 498652521 ps
CPU time 0.86 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 195876 kb
Host smart-d2798aad-fb21-47f7-bdb4-e0f33961ccd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705236919 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.705236919
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.66033637
Short name T39
Test name
Test status
Simulation time 512869229 ps
CPU time 0.79 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 193104 kb
Host smart-43e0c98f-f0f4-4087-a03f-c4479078d3e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66033637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.66033637
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2024830211
Short name T298
Test name
Test status
Simulation time 324485574 ps
CPU time 0.62 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 183552 kb
Host smart-c1a5a1c2-fd0c-4b0b-81e6-e7563730a7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024830211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2024830211
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1968680591
Short name T335
Test name
Test status
Simulation time 1042472341 ps
CPU time 1.96 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183740 kb
Host smart-a0cb1da2-9450-4fc8-89cc-685b0e308f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968680591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1968680591
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.723664651
Short name T314
Test name
Test status
Simulation time 608890363 ps
CPU time 1.7 seconds
Started Aug 06 07:02:28 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 198680 kb
Host smart-3202747f-9d1e-4d89-a0a0-ddc3385a8b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723664651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.723664651
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.442686412
Short name T309
Test name
Test status
Simulation time 4450895154 ps
CPU time 3.53 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:35 PM PDT 24
Peak memory 197848 kb
Host smart-215bf465-2e36-42b0-8a12-c17b21b55c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442686412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.442686412
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4281755964
Short name T304
Test name
Test status
Simulation time 384843379 ps
CPU time 1.14 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 195800 kb
Host smart-c7c1476c-2359-400c-a557-d64ed82244cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281755964 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4281755964
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2357292236
Short name T64
Test name
Test status
Simulation time 488634801 ps
CPU time 1.19 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 192996 kb
Host smart-d3a9ad90-b027-4570-b7c0-cdab20baf6d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357292236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2357292236
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3677472952
Short name T344
Test name
Test status
Simulation time 383190487 ps
CPU time 1.11 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 193016 kb
Host smart-32370095-d94c-4035-a7cc-ea8146e6e9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677472952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3677472952
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2341689302
Short name T88
Test name
Test status
Simulation time 2301386709 ps
CPU time 1.44 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 194056 kb
Host smart-37f5245f-6bbe-4a41-a009-87bd11ccca5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341689302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2341689302
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3965541707
Short name T340
Test name
Test status
Simulation time 428523324 ps
CPU time 1.86 seconds
Started Aug 06 07:02:40 PM PDT 24
Finished Aug 06 07:02:42 PM PDT 24
Peak memory 198564 kb
Host smart-2066a7a5-eb4b-48d3-a799-ddf30e87e7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965541707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3965541707
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1490668194
Short name T370
Test name
Test status
Simulation time 8121825833 ps
CPU time 7.45 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 198388 kb
Host smart-3ef9225b-adaf-4638-a0bf-bdf29837081d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490668194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1490668194
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3174040150
Short name T416
Test name
Test status
Simulation time 481321253 ps
CPU time 1.13 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 196392 kb
Host smart-32e4b40f-c012-4e32-8712-ed589260046b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174040150 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3174040150
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.938748549
Short name T311
Test name
Test status
Simulation time 456674791 ps
CPU time 0.6 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 193024 kb
Host smart-bfd4a2a7-e6ef-43d3-af5f-c3f5668d5ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938748549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.938748549
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.799046210
Short name T389
Test name
Test status
Simulation time 445133370 ps
CPU time 0.88 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183756 kb
Host smart-2c49f437-37d7-4510-94c8-4dbecf3b9556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799046210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.799046210
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1815899028
Short name T85
Test name
Test status
Simulation time 1252987155 ps
CPU time 1.49 seconds
Started Aug 06 07:02:43 PM PDT 24
Finished Aug 06 07:02:45 PM PDT 24
Peak memory 193056 kb
Host smart-3c83611b-eef8-43ac-b8ad-e6b5ada16568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815899028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1815899028
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3094473706
Short name T384
Test name
Test status
Simulation time 462840931 ps
CPU time 2.43 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 198584 kb
Host smart-10c2fed6-5b20-4e22-b8b8-75864b1bdd55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094473706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3094473706
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2798700991
Short name T412
Test name
Test status
Simulation time 4306331591 ps
CPU time 1.93 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 197756 kb
Host smart-9f3c6981-4322-4cd9-a112-de341bb0fe4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798700991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2798700991
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.183731956
Short name T291
Test name
Test status
Simulation time 501700176 ps
CPU time 1.44 seconds
Started Aug 06 07:02:38 PM PDT 24
Finished Aug 06 07:02:39 PM PDT 24
Peak memory 196192 kb
Host smart-167baa88-fa69-4150-8f13-d82e6ea52cbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183731956 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.183731956
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2262708050
Short name T326
Test name
Test status
Simulation time 415104560 ps
CPU time 1.15 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 194000 kb
Host smart-5d160592-bb57-4c42-8719-20e80a4198d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262708050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2262708050
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1535597444
Short name T361
Test name
Test status
Simulation time 338213114 ps
CPU time 0.76 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 183800 kb
Host smart-f666fd44-14f1-4e3f-9350-d9a13a126415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535597444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1535597444
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2290324549
Short name T44
Test name
Test status
Simulation time 1946181095 ps
CPU time 5.17 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:43 PM PDT 24
Peak memory 195120 kb
Host smart-340b67b9-601f-4daa-8cb9-add4e62633d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290324549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2290324549
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2394072314
Short name T391
Test name
Test status
Simulation time 498645559 ps
CPU time 2.29 seconds
Started Aug 06 07:02:43 PM PDT 24
Finished Aug 06 07:02:45 PM PDT 24
Peak memory 198684 kb
Host smart-8bc09bd4-7a42-4e57-9364-c0c79ffba9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394072314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2394072314
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.448222202
Short name T408
Test name
Test status
Simulation time 4091104321 ps
CPU time 6.47 seconds
Started Aug 06 07:02:35 PM PDT 24
Finished Aug 06 07:02:41 PM PDT 24
Peak memory 196860 kb
Host smart-29e4335c-f0b3-4460-bccd-db3db173d216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448222202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.448222202
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2256655708
Short name T70
Test name
Test status
Simulation time 646234893 ps
CPU time 0.9 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 183740 kb
Host smart-95fa576e-7ca8-410e-a498-d79b657af3ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256655708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2256655708
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2330581232
Short name T74
Test name
Test status
Simulation time 7251637758 ps
CPU time 1.89 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 192264 kb
Host smart-62bb6379-e274-4127-98d1-05ddb3638943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330581232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2330581232
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3507243381
Short name T302
Test name
Test status
Simulation time 1357770775 ps
CPU time 0.68 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 193248 kb
Host smart-1585adde-1b3e-42ed-8152-ae78cd6912c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507243381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3507243381
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4253504497
Short name T299
Test name
Test status
Simulation time 627758550 ps
CPU time 0.81 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 197320 kb
Host smart-d7e38b21-3075-4162-bf48-526e31d05d03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253504497 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4253504497
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.707356749
Short name T289
Test name
Test status
Simulation time 305250376 ps
CPU time 0.66 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 192020 kb
Host smart-1859dcb6-0f3b-4623-b401-4a072794ec72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707356749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.707356749
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2242242852
Short name T292
Test name
Test status
Simulation time 306048809 ps
CPU time 0.82 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 192996 kb
Host smart-84f392e3-5c26-478c-9a62-d7ed5b8a5469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242242852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2242242852
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.143945198
Short name T279
Test name
Test status
Simulation time 516324209 ps
CPU time 0.71 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:23 PM PDT 24
Peak memory 183676 kb
Host smart-c4acd9ba-a6fa-4036-8c57-e43dbad94955
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143945198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.143945198
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4131038751
Short name T330
Test name
Test status
Simulation time 436406483 ps
CPU time 0.67 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 183652 kb
Host smart-dc2f0a25-7881-43ac-98bf-24021a0c247b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131038751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4131038751
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.576195721
Short name T398
Test name
Test status
Simulation time 2205668637 ps
CPU time 1.92 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 194352 kb
Host smart-33ce506b-ca09-43cb-a85e-ec2dd60326ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576195721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.576195721
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1146768705
Short name T277
Test name
Test status
Simulation time 1446091553 ps
CPU time 1.38 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 198612 kb
Host smart-2e32447a-32ab-43bf-8ed0-4cfb0eba7c2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146768705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1146768705
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1243790873
Short name T285
Test name
Test status
Simulation time 442264302 ps
CPU time 1.2 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 183796 kb
Host smart-577e1bd6-7bdd-4524-b1f7-75e348491273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243790873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1243790873
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.427042620
Short name T362
Test name
Test status
Simulation time 495213709 ps
CPU time 0.72 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 183768 kb
Host smart-25768b3d-ce95-45a0-8794-47760a049b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427042620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.427042620
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3855754360
Short name T328
Test name
Test status
Simulation time 483179077 ps
CPU time 0.72 seconds
Started Aug 06 07:02:43 PM PDT 24
Finished Aug 06 07:02:44 PM PDT 24
Peak memory 183848 kb
Host smart-549f3fa5-3abb-489d-b599-7828575ba30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855754360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3855754360
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3953210329
Short name T347
Test name
Test status
Simulation time 407379713 ps
CPU time 0.58 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 183780 kb
Host smart-1ea3d725-85b4-450a-8c74-56bef40759b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953210329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3953210329
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3208076168
Short name T358
Test name
Test status
Simulation time 301603425 ps
CPU time 0.62 seconds
Started Aug 06 07:02:38 PM PDT 24
Finished Aug 06 07:02:39 PM PDT 24
Peak memory 183848 kb
Host smart-1947117c-e238-41da-b257-e5a9cab3a9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208076168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3208076168
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1038854701
Short name T346
Test name
Test status
Simulation time 335363095 ps
CPU time 0.68 seconds
Started Aug 06 07:02:38 PM PDT 24
Finished Aug 06 07:02:39 PM PDT 24
Peak memory 183848 kb
Host smart-de51f0c4-21b1-4939-8a44-5a612530a6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038854701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1038854701
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2195853559
Short name T338
Test name
Test status
Simulation time 438478435 ps
CPU time 1.08 seconds
Started Aug 06 07:02:42 PM PDT 24
Finished Aug 06 07:02:44 PM PDT 24
Peak memory 183848 kb
Host smart-a4ef2598-ebd1-46ff-a26e-0e4a8fe54555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195853559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2195853559
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1714136975
Short name T318
Test name
Test status
Simulation time 431819281 ps
CPU time 1.23 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 193016 kb
Host smart-46e1adbb-e26a-4f0e-add5-01192d090400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714136975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1714136975
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4111037605
Short name T395
Test name
Test status
Simulation time 520165986 ps
CPU time 0.99 seconds
Started Aug 06 07:02:39 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 193016 kb
Host smart-f34b6dc6-a47c-4fce-9812-ff14671e0579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111037605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4111037605
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2691152994
Short name T296
Test name
Test status
Simulation time 438490447 ps
CPU time 0.87 seconds
Started Aug 06 07:02:39 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 193016 kb
Host smart-e960f883-ea0e-4efa-af0e-f4cd9e997020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691152994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2691152994
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3214066664
Short name T62
Test name
Test status
Simulation time 522089793 ps
CPU time 1.76 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 191964 kb
Host smart-a9350b94-16b7-475a-bdca-4a72d5fcfed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214066664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3214066664
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4023933629
Short name T372
Test name
Test status
Simulation time 11489549224 ps
CPU time 17.19 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 192332 kb
Host smart-8140e740-553c-4089-b2e2-1429059e25f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023933629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.4023933629
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2449004880
Short name T320
Test name
Test status
Simulation time 1326822045 ps
CPU time 0.87 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 194020 kb
Host smart-01335cbf-9e5d-44d5-a856-c8de3c8db008
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449004880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2449004880
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1748422071
Short name T374
Test name
Test status
Simulation time 477007467 ps
CPU time 0.83 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 196472 kb
Host smart-99726ca1-8f3a-4e53-8672-df33a510922e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748422071 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1748422071
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3289414516
Short name T293
Test name
Test status
Simulation time 509714257 ps
CPU time 0.72 seconds
Started Aug 06 07:02:13 PM PDT 24
Finished Aug 06 07:02:14 PM PDT 24
Peak memory 193080 kb
Host smart-747aa869-baf1-4287-95a5-bce9bddd42ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289414516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3289414516
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3422706785
Short name T404
Test name
Test status
Simulation time 514680741 ps
CPU time 0.85 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 193004 kb
Host smart-0e12bb1e-71fb-4142-ad95-4baef6d9f3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422706785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3422706785
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4204365146
Short name T341
Test name
Test status
Simulation time 467397003 ps
CPU time 1.25 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 183652 kb
Host smart-b31e60b4-7148-4b82-afbf-e1d444b2ad59
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204365146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4204365146
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3531915089
Short name T324
Test name
Test status
Simulation time 543148038 ps
CPU time 0.79 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 183596 kb
Host smart-06929066-1842-4cec-83c7-cf7064326a3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531915089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3531915089
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.244749671
Short name T413
Test name
Test status
Simulation time 2333901620 ps
CPU time 7.91 seconds
Started Aug 06 07:02:10 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 195096 kb
Host smart-3875e9ef-f3b4-484c-bc05-255011f0c5c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244749671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.244749671
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2649941346
Short name T352
Test name
Test status
Simulation time 585924115 ps
CPU time 1.17 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 198420 kb
Host smart-c7db0008-c911-431a-a65d-be78f2c13a28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649941346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2649941346
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1036813439
Short name T40
Test name
Test status
Simulation time 9062478070 ps
CPU time 14.59 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 198216 kb
Host smart-c52d6e9a-658b-4a22-b790-3324bb7e153c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036813439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1036813439
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.91585245
Short name T334
Test name
Test status
Simulation time 489705646 ps
CPU time 1.22 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:35 PM PDT 24
Peak memory 193008 kb
Host smart-6d7b1548-b514-45e8-b470-1c5a94848f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91585245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.91585245
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3014272987
Short name T354
Test name
Test status
Simulation time 485219722 ps
CPU time 0.68 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183784 kb
Host smart-5ad99040-5997-44d4-b23b-1f2f474f2148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014272987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3014272987
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1109145925
Short name T385
Test name
Test status
Simulation time 484396431 ps
CPU time 0.71 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183796 kb
Host smart-3b6796b5-ce92-46f4-ab57-4b4d2e727f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109145925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1109145925
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.256707723
Short name T275
Test name
Test status
Simulation time 397353870 ps
CPU time 1.11 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 183796 kb
Host smart-e9e3cd2f-b1bf-4994-9d76-5de9cf03ca9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256707723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.256707723
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2112871970
Short name T342
Test name
Test status
Simulation time 509877907 ps
CPU time 0.7 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 193016 kb
Host smart-465de6c8-47eb-4514-b03f-3f429556ccfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112871970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2112871970
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3141254856
Short name T365
Test name
Test status
Simulation time 442121332 ps
CPU time 0.82 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 183816 kb
Host smart-006fb10d-d298-46df-8c2a-81f1d1d410f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141254856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3141254856
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2200365609
Short name T364
Test name
Test status
Simulation time 338426707 ps
CPU time 1.06 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 183772 kb
Host smart-7c4aebce-bfab-4cba-98c0-a012e895c88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200365609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2200365609
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2465205627
Short name T281
Test name
Test status
Simulation time 298901401 ps
CPU time 0.71 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 193000 kb
Host smart-8bef84cf-3f10-4839-b63f-516112fa3850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465205627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2465205627
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.440579270
Short name T336
Test name
Test status
Simulation time 419195950 ps
CPU time 0.66 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:37 PM PDT 24
Peak memory 193016 kb
Host smart-20f05b76-e55c-474e-887d-ee364e81f05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440579270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.440579270
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2383207778
Short name T411
Test name
Test status
Simulation time 403930319 ps
CPU time 1.09 seconds
Started Aug 06 07:02:37 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 193016 kb
Host smart-54d27eb6-711b-4a40-b1d0-8345bce312bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383207778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2383207778
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2537563352
Short name T66
Test name
Test status
Simulation time 428891641 ps
CPU time 0.71 seconds
Started Aug 06 07:02:24 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 183956 kb
Host smart-21567d8a-2ba1-404a-a445-b754a425ae95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537563352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2537563352
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3738554214
Short name T399
Test name
Test status
Simulation time 13847318736 ps
CPU time 3.27 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 192292 kb
Host smart-ee34d89a-6c08-4b62-ade0-e187507128a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738554214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3738554214
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1114487017
Short name T377
Test name
Test status
Simulation time 834299457 ps
CPU time 0.79 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 193000 kb
Host smart-61596059-b9db-45e2-81ed-425278e9079c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114487017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1114487017
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3979850140
Short name T312
Test name
Test status
Simulation time 448197444 ps
CPU time 1.39 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 196100 kb
Host smart-2c0c1c6d-b7f9-448b-95e1-567204c4cb09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979850140 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3979850140
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.298942949
Short name T359
Test name
Test status
Simulation time 555737908 ps
CPU time 0.96 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 193316 kb
Host smart-a735b8e8-16f7-4d61-9cdf-b75d700dc165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298942949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.298942949
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.327888258
Short name T316
Test name
Test status
Simulation time 438742599 ps
CPU time 0.85 seconds
Started Aug 06 07:02:13 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 183760 kb
Host smart-7d9767e7-d875-41dc-a5fc-a25ac4d75d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327888258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.327888258
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3462264814
Short name T313
Test name
Test status
Simulation time 414281893 ps
CPU time 0.84 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 183684 kb
Host smart-53fb1ad3-1f6d-48aa-9f89-49f9c1ac07d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462264814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3462264814
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2076052018
Short name T321
Test name
Test status
Simulation time 285676284 ps
CPU time 0.8 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 183660 kb
Host smart-c9361ef8-06b0-4f28-bf7d-c69be7562cc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076052018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2076052018
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.12627629
Short name T331
Test name
Test status
Simulation time 2642308385 ps
CPU time 1.68 seconds
Started Aug 06 07:02:20 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 194124 kb
Host smart-b720b152-0d45-4394-872b-db2109db67c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_same_csr_outstanding.12627629
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2949921777
Short name T351
Test name
Test status
Simulation time 688509407 ps
CPU time 2.56 seconds
Started Aug 06 07:02:21 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 198608 kb
Host smart-6920c90c-1f6f-4842-a6cf-8b136a02cf95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949921777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2949921777
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.525204722
Short name T373
Test name
Test status
Simulation time 8318753507 ps
CPU time 4.24 seconds
Started Aug 06 07:02:17 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 198308 kb
Host smart-15e2d188-ebae-4cb0-9adb-23ffc6f643fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525204722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.525204722
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.388359114
Short name T276
Test name
Test status
Simulation time 387577085 ps
CPU time 1.09 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183756 kb
Host smart-011e80c3-16a8-4abe-8106-d1f463de0228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388359114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.388359114
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.97587346
Short name T363
Test name
Test status
Simulation time 415810407 ps
CPU time 0.65 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 192988 kb
Host smart-a90b8e86-9237-42d7-a7c9-d5ede5618cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97587346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.97587346
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1727288015
Short name T402
Test name
Test status
Simulation time 365318558 ps
CPU time 0.56 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 183816 kb
Host smart-af765381-8b87-4769-b2ed-cf826bf481af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727288015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1727288015
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.304366382
Short name T288
Test name
Test status
Simulation time 284837846 ps
CPU time 0.93 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 183816 kb
Host smart-3e53687e-2a64-4d3f-98e0-864f7c3fabfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304366382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.304366382
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3188702748
Short name T397
Test name
Test status
Simulation time 318878604 ps
CPU time 1.04 seconds
Started Aug 06 07:02:34 PM PDT 24
Finished Aug 06 07:02:35 PM PDT 24
Peak memory 183752 kb
Host smart-2a9e1a1b-7961-4727-a146-b74e6ef56f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188702748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3188702748
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.540148798
Short name T306
Test name
Test status
Simulation time 350583871 ps
CPU time 1.06 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 183816 kb
Host smart-9b4521dc-5fe8-4b94-a2f6-74e76c6d8761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540148798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.540148798
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.591317021
Short name T353
Test name
Test status
Simulation time 367744137 ps
CPU time 1.11 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 193036 kb
Host smart-8295a274-d484-4281-9fd5-fc7ac339da1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591317021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.591317021
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2371784473
Short name T297
Test name
Test status
Simulation time 351846880 ps
CPU time 0.65 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183756 kb
Host smart-ddee913b-ad23-4597-94f9-8bd37deb6e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371784473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2371784473
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.854435290
Short name T287
Test name
Test status
Simulation time 441630583 ps
CPU time 0.58 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 183760 kb
Host smart-af64314a-48f4-4b6d-ab53-df3395133642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854435290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.854435290
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2684208384
Short name T339
Test name
Test status
Simulation time 450559068 ps
CPU time 1.09 seconds
Started Aug 06 07:02:26 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 192972 kb
Host smart-18e05bf0-5de5-431d-b99e-d4fc17cd5969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684208384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2684208384
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1542638990
Short name T317
Test name
Test status
Simulation time 560083529 ps
CPU time 1.55 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:21 PM PDT 24
Peak memory 196344 kb
Host smart-587902ca-dbe7-4f8f-b63d-e8f687d0c689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542638990 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1542638990
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3766919483
Short name T67
Test name
Test status
Simulation time 360099934 ps
CPU time 1.19 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 194000 kb
Host smart-76bbf722-410e-4e88-90c1-e9a34d77ee5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766919483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3766919483
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3078945914
Short name T394
Test name
Test status
Simulation time 445440217 ps
CPU time 1.15 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 183768 kb
Host smart-c49c0396-ac7b-4407-97bb-b67a843bb47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078945914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3078945914
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2603341474
Short name T348
Test name
Test status
Simulation time 1272346585 ps
CPU time 3.73 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 191960 kb
Host smart-c4d50602-d47c-40ad-90a8-192f9f2a4537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603341474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2603341474
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3451722404
Short name T356
Test name
Test status
Simulation time 529755394 ps
CPU time 2.14 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 198644 kb
Host smart-703e9f92-53ef-4cf0-bedc-45d085c3bbaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451722404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3451722404
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.843550750
Short name T410
Test name
Test status
Simulation time 4435766968 ps
CPU time 8.05 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 198016 kb
Host smart-d19df516-90e6-4e79-b412-bf0bef61051d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843550750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.843550750
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3276062070
Short name T366
Test name
Test status
Simulation time 426189166 ps
CPU time 0.85 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:24 PM PDT 24
Peak memory 196520 kb
Host smart-a19627f5-7d8d-4a9d-97b8-6aeb572091f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276062070 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3276062070
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1871310
Short name T72
Test name
Test status
Simulation time 408238662 ps
CPU time 0.85 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 192968 kb
Host smart-4802cf60-046e-4d7f-a437-13a66eba748d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1871310
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1314470978
Short name T278
Test name
Test status
Simulation time 463103688 ps
CPU time 1.24 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 193012 kb
Host smart-ca2e70cb-0ec4-4511-a460-d077dcee8be0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314470978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1314470978
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1831610418
Short name T357
Test name
Test status
Simulation time 2755606130 ps
CPU time 3.02 seconds
Started Aug 06 07:02:31 PM PDT 24
Finished Aug 06 07:02:35 PM PDT 24
Peak memory 195280 kb
Host smart-56f08b38-0e92-4c5c-8bbc-41861e2c3604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831610418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1831610418
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3961788283
Short name T290
Test name
Test status
Simulation time 440049739 ps
CPU time 2.8 seconds
Started Aug 06 07:02:29 PM PDT 24
Finished Aug 06 07:02:32 PM PDT 24
Peak memory 198340 kb
Host smart-45711c53-facb-4413-99fa-b85f79d3ab93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961788283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3961788283
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1640375130
Short name T406
Test name
Test status
Simulation time 8425796171 ps
CPU time 14.06 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:47 PM PDT 24
Peak memory 198120 kb
Host smart-952c8d2c-28e1-40dc-b45c-05ffaf60514a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640375130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1640375130
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1492379305
Short name T381
Test name
Test status
Simulation time 340513846 ps
CPU time 0.97 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 197088 kb
Host smart-d8dac398-be88-4475-822c-d4b3c8e93636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492379305 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1492379305
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1834916762
Short name T69
Test name
Test status
Simulation time 467001033 ps
CPU time 1.24 seconds
Started Aug 06 07:02:21 PM PDT 24
Finished Aug 06 07:02:23 PM PDT 24
Peak memory 193316 kb
Host smart-d0c75db6-548c-456c-b69c-785b8bacb315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834916762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1834916762
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1484923294
Short name T350
Test name
Test status
Simulation time 363779286 ps
CPU time 0.75 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:23 PM PDT 24
Peak memory 193016 kb
Host smart-a9481a0a-b20a-4b6b-81b1-767f2103b5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484923294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1484923294
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2203585892
Short name T84
Test name
Test status
Simulation time 1710063312 ps
CPU time 2.35 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 191912 kb
Host smart-54b7b40e-22cb-439a-8db3-5b609be9bdda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203585892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2203585892
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3007349190
Short name T387
Test name
Test status
Simulation time 321440173 ps
CPU time 2.68 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 198532 kb
Host smart-dac67af8-e1be-471c-8a75-752b70708085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007349190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3007349190
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.441224212
Short name T327
Test name
Test status
Simulation time 7985998815 ps
CPU time 5.38 seconds
Started Aug 06 07:02:21 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 198344 kb
Host smart-386251a4-f975-46a1-8b86-1ce136b7f4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441224212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.441224212
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2511883987
Short name T200
Test name
Test status
Simulation time 482902290 ps
CPU time 1.19 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:23 PM PDT 24
Peak memory 195984 kb
Host smart-3f7a50b9-4cae-44a8-aad4-96228fb1ed79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511883987 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2511883987
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1483554236
Short name T63
Test name
Test status
Simulation time 439677128 ps
CPU time 1.21 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:28 PM PDT 24
Peak memory 192988 kb
Host smart-90ffaf88-f208-4434-82e8-424dc717ffba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483554236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1483554236
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3695198233
Short name T283
Test name
Test status
Simulation time 328609599 ps
CPU time 1.06 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:34 PM PDT 24
Peak memory 183764 kb
Host smart-ea9bf172-ad9d-4852-bc36-fcc29e3daf58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695198233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3695198233
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1141869772
Short name T87
Test name
Test status
Simulation time 2015232109 ps
CPU time 3.28 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 194736 kb
Host smart-dcfbcf5e-6b28-4ea3-90c2-95c75b2414c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141869772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1141869772
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4097086911
Short name T383
Test name
Test status
Simulation time 645961498 ps
CPU time 1.59 seconds
Started Aug 06 07:02:27 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 198628 kb
Host smart-6ba169b1-578d-4f0d-af0c-0b9afc277597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097086911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4097086911
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2554364499
Short name T199
Test name
Test status
Simulation time 7937292789 ps
CPU time 12.5 seconds
Started Aug 06 07:02:33 PM PDT 24
Finished Aug 06 07:02:45 PM PDT 24
Peak memory 198448 kb
Host smart-c296abb8-9cdf-43a7-8a88-1996f01e361f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554364499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2554364499
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1559388683
Short name T307
Test name
Test status
Simulation time 353480214 ps
CPU time 0.81 seconds
Started Aug 06 07:02:32 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 196208 kb
Host smart-3bd1d836-82aa-4c78-b004-2c72bb2c15fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559388683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1559388683
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2921132673
Short name T396
Test name
Test status
Simulation time 507607682 ps
CPU time 1.31 seconds
Started Aug 06 07:02:28 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 193048 kb
Host smart-58892cb7-47bc-44d2-8491-b5618cfcfa48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921132673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2921132673
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.959793653
Short name T417
Test name
Test status
Simulation time 1134853131 ps
CPU time 1.07 seconds
Started Aug 06 07:02:28 PM PDT 24
Finished Aug 06 07:02:29 PM PDT 24
Peak memory 193596 kb
Host smart-273a3025-45cd-4e16-b5ec-191e2d6aab8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959793653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.959793653
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2101729202
Short name T315
Test name
Test status
Simulation time 428636495 ps
CPU time 2.31 seconds
Started Aug 06 07:02:20 PM PDT 24
Finished Aug 06 07:02:22 PM PDT 24
Peak memory 198628 kb
Host smart-aca2fcca-7c0b-4e30-8123-084fb25ff37d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101729202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2101729202
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.847084866
Short name T400
Test name
Test status
Simulation time 7913313785 ps
CPU time 8.46 seconds
Started Aug 06 07:02:30 PM PDT 24
Finished Aug 06 07:02:38 PM PDT 24
Peak memory 198272 kb
Host smart-35f94de4-9f0f-42b4-8a27-1292226e72c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847084866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.847084866
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2787129057
Short name T222
Test name
Test status
Simulation time 33601986538 ps
CPU time 13.88 seconds
Started Aug 06 07:01:30 PM PDT 24
Finished Aug 06 07:01:44 PM PDT 24
Peak memory 192196 kb
Host smart-509d6d30-202f-4341-900a-c495b1465821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787129057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2787129057
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2491444510
Short name T234
Test name
Test status
Simulation time 499278853 ps
CPU time 0.69 seconds
Started Aug 06 07:01:30 PM PDT 24
Finished Aug 06 07:01:31 PM PDT 24
Peak memory 192128 kb
Host smart-4f203358-1555-41c7-84ad-f533e6afe156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491444510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2491444510
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2019274900
Short name T226
Test name
Test status
Simulation time 38740513685 ps
CPU time 5.62 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:01:30 PM PDT 24
Peak memory 192176 kb
Host smart-3c931dd0-b6b3-4d8a-9dbc-6400283c6589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019274900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2019274900
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3520029687
Short name T20
Test name
Test status
Simulation time 8185979835 ps
CPU time 2.45 seconds
Started Aug 06 07:01:26 PM PDT 24
Finished Aug 06 07:01:28 PM PDT 24
Peak memory 215860 kb
Host smart-1eef74d5-688f-4e7f-8bd7-432b9b9a714e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520029687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3520029687
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3565974828
Short name T212
Test name
Test status
Simulation time 494893846 ps
CPU time 1.33 seconds
Started Aug 06 07:01:34 PM PDT 24
Finished Aug 06 07:01:36 PM PDT 24
Peak memory 192056 kb
Host smart-b3ee2869-763f-4969-b25a-e20fb5962469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565974828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3565974828
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2114476232
Short name T262
Test name
Test status
Simulation time 11128250949 ps
CPU time 5.42 seconds
Started Aug 06 07:01:48 PM PDT 24
Finished Aug 06 07:01:54 PM PDT 24
Peak memory 197216 kb
Host smart-15b9e2bc-3c8f-4b5f-b710-34eb9521fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114476232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2114476232
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2020164068
Short name T232
Test name
Test status
Simulation time 380065404 ps
CPU time 0.83 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:53 PM PDT 24
Peak memory 192100 kb
Host smart-cbe6ba12-3dd1-44b5-a724-4b2665b1da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020164068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2020164068
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.543333808
Short name T224
Test name
Test status
Simulation time 14266677732 ps
CPU time 10.27 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 192172 kb
Host smart-3513a1d8-8f13-4898-adb5-0d363912ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543333808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.543333808
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1074837524
Short name T12
Test name
Test status
Simulation time 502576107 ps
CPU time 1.23 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:53 PM PDT 24
Peak memory 192096 kb
Host smart-3e9c388d-e769-494c-8707-dd01635e618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074837524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1074837524
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.334580333
Short name T211
Test name
Test status
Simulation time 11992665990 ps
CPU time 18.13 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 192164 kb
Host smart-3e79a3d2-aa50-4f48-9f52-efeb94551f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334580333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.334580333
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.828323669
Short name T261
Test name
Test status
Simulation time 437347661 ps
CPU time 0.62 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 192024 kb
Host smart-63d5cc97-76f3-4c12-8a26-a1537e61ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828323669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.828323669
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.400439430
Short name T227
Test name
Test status
Simulation time 38158655665 ps
CPU time 11.38 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:02:04 PM PDT 24
Peak memory 192164 kb
Host smart-b95a055a-4f21-4dc1-b171-49ad45954344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400439430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.400439430
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2641838640
Short name T206
Test name
Test status
Simulation time 566735828 ps
CPU time 0.75 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 196924 kb
Host smart-91a1155c-0cbb-4fad-8fae-208e26fa68d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641838640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2641838640
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3928860245
Short name T251
Test name
Test status
Simulation time 41253132378 ps
CPU time 55.98 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:02:48 PM PDT 24
Peak memory 192172 kb
Host smart-77473e2b-70e4-4f96-98de-c31cd7638f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928860245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3928860245
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2817210359
Short name T76
Test name
Test status
Simulation time 525531077 ps
CPU time 0.93 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:01:54 PM PDT 24
Peak memory 196964 kb
Host smart-fb11f037-c903-49b4-b948-ef701fa213ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817210359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2817210359
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1071782546
Short name T192
Test name
Test status
Simulation time 474433068 ps
CPU time 0.65 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:01:51 PM PDT 24
Peak memory 196888 kb
Host smart-1a0dbd5c-9ca8-4ac2-94cd-fa251665e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071782546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1071782546
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.956038744
Short name T203
Test name
Test status
Simulation time 28609647911 ps
CPU time 10.37 seconds
Started Aug 06 07:01:45 PM PDT 24
Finished Aug 06 07:01:55 PM PDT 24
Peak memory 192184 kb
Host smart-d563ca83-af46-478f-b301-b9e81b9db7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956038744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.956038744
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.124244651
Short name T52
Test name
Test status
Simulation time 378765004 ps
CPU time 1.11 seconds
Started Aug 06 07:02:05 PM PDT 24
Finished Aug 06 07:02:06 PM PDT 24
Peak memory 192108 kb
Host smart-57990af2-e3bb-49a6-af0f-1249a1b2d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124244651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.124244651
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3032193826
Short name T239
Test name
Test status
Simulation time 39256697576 ps
CPU time 29.89 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:02:27 PM PDT 24
Peak memory 191896 kb
Host smart-9d67b4c2-e0f2-45da-aa38-863b43bc91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032193826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3032193826
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4103957858
Short name T258
Test name
Test status
Simulation time 513640350 ps
CPU time 0.74 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:01:48 PM PDT 24
Peak memory 192008 kb
Host smart-fa2a8365-0779-4517-a542-57676cc0a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103957858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4103957858
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2898892538
Short name T13
Test name
Test status
Simulation time 4398590067 ps
CPU time 2.02 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:01:59 PM PDT 24
Peak memory 197044 kb
Host smart-472af4cc-7dcb-4e4e-8934-b5191df1b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898892538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2898892538
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1431399375
Short name T252
Test name
Test status
Simulation time 537925026 ps
CPU time 1.43 seconds
Started Aug 06 07:01:49 PM PDT 24
Finished Aug 06 07:01:50 PM PDT 24
Peak memory 192124 kb
Host smart-aac27281-d730-474b-8eca-7e51ffbbac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431399375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1431399375
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.909613026
Short name T90
Test name
Test status
Simulation time 43589879847 ps
CPU time 14.45 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 192188 kb
Host smart-1b31b368-390c-479e-b1cf-79f07a355fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909613026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.909613026
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3796407078
Short name T93
Test name
Test status
Simulation time 647271822 ps
CPU time 0.66 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 196920 kb
Host smart-d52b7766-05fc-4e96-bf2e-04bf971d40d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796407078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3796407078
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3216717440
Short name T245
Test name
Test status
Simulation time 3740528593 ps
CPU time 1.72 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:02:00 PM PDT 24
Peak memory 196860 kb
Host smart-ec13ace2-4dc1-4fa8-bf23-077898708c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216717440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3216717440
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2846464126
Short name T25
Test name
Test status
Simulation time 543015147 ps
CPU time 0.96 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:01:58 PM PDT 24
Peak memory 192008 kb
Host smart-0758da1f-236d-4ef2-a8ea-e53d75cee548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846464126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2846464126
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3046930551
Short name T208
Test name
Test status
Simulation time 8908613420 ps
CPU time 14.95 seconds
Started Aug 06 07:01:25 PM PDT 24
Finished Aug 06 07:01:40 PM PDT 24
Peak memory 197180 kb
Host smart-94973f0d-4fb4-4d78-8870-8f54ba5e1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046930551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3046930551
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4224599514
Short name T23
Test name
Test status
Simulation time 4106868673 ps
CPU time 4.04 seconds
Started Aug 06 07:01:36 PM PDT 24
Finished Aug 06 07:01:40 PM PDT 24
Peak memory 215520 kb
Host smart-4b430514-8f31-4887-aaa1-9b7d1eee95b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224599514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4224599514
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.89613780
Short name T10
Test name
Test status
Simulation time 576788265 ps
CPU time 0.93 seconds
Started Aug 06 07:01:34 PM PDT 24
Finished Aug 06 07:01:35 PM PDT 24
Peak memory 192112 kb
Host smart-674a5dd3-8383-4b6a-8ba0-340646126704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89613780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.89613780
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3075642747
Short name T255
Test name
Test status
Simulation time 30001406422 ps
CPU time 40.56 seconds
Started Aug 06 07:01:37 PM PDT 24
Finished Aug 06 07:02:18 PM PDT 24
Peak memory 192124 kb
Host smart-38e6a269-0579-4239-8e98-0b4efe5cb55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075642747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3075642747
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2685393787
Short name T230
Test name
Test status
Simulation time 552094578 ps
CPU time 1.38 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 192312 kb
Host smart-a918da30-f60d-45f2-a158-fb83a7ad6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685393787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2685393787
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1425168129
Short name T180
Test name
Test status
Simulation time 540214749 ps
CPU time 0.99 seconds
Started Aug 06 07:01:53 PM PDT 24
Finished Aug 06 07:01:54 PM PDT 24
Peak memory 197196 kb
Host smart-876c6510-25cb-4fab-bda8-2632ce313e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425168129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1425168129
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.317032616
Short name T218
Test name
Test status
Simulation time 16128114592 ps
CPU time 5.78 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:01:56 PM PDT 24
Peak memory 192392 kb
Host smart-7b766b06-c764-4cbf-b8ab-f370116f4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317032616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.317032616
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2028329592
Short name T204
Test name
Test status
Simulation time 605841689 ps
CPU time 1.5 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 192328 kb
Host smart-1cd8d106-00f0-4dc9-83d1-60860a557468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028329592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2028329592
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3141129968
Short name T246
Test name
Test status
Simulation time 14155886904 ps
CPU time 5.07 seconds
Started Aug 06 07:01:49 PM PDT 24
Finished Aug 06 07:01:54 PM PDT 24
Peak memory 197372 kb
Host smart-8d269664-a0ff-476e-b24e-4a39ef723ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141129968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3141129968
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1244152149
Short name T58
Test name
Test status
Simulation time 387631750 ps
CPU time 0.71 seconds
Started Aug 06 07:02:02 PM PDT 24
Finished Aug 06 07:02:03 PM PDT 24
Peak memory 196908 kb
Host smart-f7d6a491-ad15-4486-b9c2-ad2f98288fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244152149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1244152149
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2252583911
Short name T202
Test name
Test status
Simulation time 20227007337 ps
CPU time 14.33 seconds
Started Aug 06 07:01:54 PM PDT 24
Finished Aug 06 07:02:09 PM PDT 24
Peak memory 192384 kb
Host smart-c4d757ec-8713-4e5f-97a9-4ab891dfc664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252583911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2252583911
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3113425249
Short name T268
Test name
Test status
Simulation time 363496842 ps
CPU time 1.05 seconds
Started Aug 06 07:02:06 PM PDT 24
Finished Aug 06 07:02:07 PM PDT 24
Peak memory 192088 kb
Host smart-af1ed073-0100-4beb-8191-033cec792484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113425249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3113425249
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2861396193
Short name T83
Test name
Test status
Simulation time 24272406727 ps
CPU time 11.16 seconds
Started Aug 06 07:01:51 PM PDT 24
Finished Aug 06 07:02:03 PM PDT 24
Peak memory 197224 kb
Host smart-ee61eeb9-5a38-47cf-bbe0-3ddb1325588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861396193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2861396193
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1484103881
Short name T7
Test name
Test status
Simulation time 518823073 ps
CPU time 1.3 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:01 PM PDT 24
Peak memory 196932 kb
Host smart-e7859d1f-5505-43c4-9789-f23b6f092d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484103881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1484103881
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2160134919
Short name T205
Test name
Test status
Simulation time 16229542102 ps
CPU time 7.31 seconds
Started Aug 06 07:01:57 PM PDT 24
Finished Aug 06 07:02:04 PM PDT 24
Peak memory 192180 kb
Host smart-04acfb5f-cbdd-4de5-80c4-950c998ff243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160134919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2160134919
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.467384726
Short name T33
Test name
Test status
Simulation time 626719836 ps
CPU time 0.81 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:01:58 PM PDT 24
Peak memory 192096 kb
Host smart-47eaac2f-e13b-4689-bb81-7bd09d10e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467384726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.467384726
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2642538324
Short name T201
Test name
Test status
Simulation time 6959365578 ps
CPU time 10.22 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 197136 kb
Host smart-114c9a57-9e78-4158-9c43-440f42eb13d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642538324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2642538324
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1075415952
Short name T91
Test name
Test status
Simulation time 384095531 ps
CPU time 0.68 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:02:00 PM PDT 24
Peak memory 192144 kb
Host smart-d7dc29e0-5f8c-4167-ac39-f668996e275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075415952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1075415952
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2540672042
Short name T195
Test name
Test status
Simulation time 549391569 ps
CPU time 1.25 seconds
Started Aug 06 07:01:55 PM PDT 24
Finished Aug 06 07:01:56 PM PDT 24
Peak memory 196912 kb
Host smart-a11432d8-b897-4618-898e-49f8408b3db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540672042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2540672042
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.302232629
Short name T256
Test name
Test status
Simulation time 27516466736 ps
CPU time 34.91 seconds
Started Aug 06 07:02:07 PM PDT 24
Finished Aug 06 07:02:42 PM PDT 24
Peak memory 192248 kb
Host smart-23f17827-30a6-4d3d-b7c9-f3acdc12f7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302232629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.302232629
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2940448044
Short name T217
Test name
Test status
Simulation time 527964693 ps
CPU time 1.3 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:54 PM PDT 24
Peak memory 192112 kb
Host smart-7b780e7e-69fa-4f01-ad4e-c50dfb64a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940448044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2940448044
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.990827486
Short name T216
Test name
Test status
Simulation time 10760788017 ps
CPU time 8.18 seconds
Started Aug 06 07:02:04 PM PDT 24
Finished Aug 06 07:02:12 PM PDT 24
Peak memory 197160 kb
Host smart-8f79298d-5b35-4354-8e63-277944c1a8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990827486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.990827486
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4014140903
Short name T250
Test name
Test status
Simulation time 552953890 ps
CPU time 0.91 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 192088 kb
Host smart-15aa7300-cab2-4066-96f9-03c574b1414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014140903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4014140903
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.280033000
Short name T82
Test name
Test status
Simulation time 7608386479 ps
CPU time 2.23 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:55 PM PDT 24
Peak memory 192208 kb
Host smart-075223a5-abe2-4747-9566-e99bb0624602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280033000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.280033000
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.921123353
Short name T241
Test name
Test status
Simulation time 472782855 ps
CPU time 0.71 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:00 PM PDT 24
Peak memory 192076 kb
Host smart-2abd719e-abfe-417d-bd8e-dec24e2aa1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921123353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.921123353
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2661488753
Short name T96
Test name
Test status
Simulation time 4038800602 ps
CPU time 5.85 seconds
Started Aug 06 07:01:30 PM PDT 24
Finished Aug 06 07:01:36 PM PDT 24
Peak memory 192104 kb
Host smart-c7c6a53b-79d4-4cf5-9609-0024111087a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661488753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2661488753
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.342669146
Short name T21
Test name
Test status
Simulation time 7963402592 ps
CPU time 2.57 seconds
Started Aug 06 07:01:39 PM PDT 24
Finished Aug 06 07:01:41 PM PDT 24
Peak memory 215884 kb
Host smart-835c19f0-b089-4088-b66e-2659a705a202
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342669146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.342669146
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2623800122
Short name T244
Test name
Test status
Simulation time 455516196 ps
CPU time 1.06 seconds
Started Aug 06 07:01:37 PM PDT 24
Finished Aug 06 07:01:38 PM PDT 24
Peak memory 192100 kb
Host smart-bd80ea36-2057-4338-aea2-9b1db7495948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623800122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2623800122
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2272100247
Short name T55
Test name
Test status
Simulation time 5987536087 ps
CPU time 1.68 seconds
Started Aug 06 07:02:03 PM PDT 24
Finished Aug 06 07:02:04 PM PDT 24
Peak memory 197160 kb
Host smart-2e75fcd5-8e04-45f5-81d7-22056b1f135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272100247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2272100247
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3693485033
Short name T228
Test name
Test status
Simulation time 347606849 ps
CPU time 1.06 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:01:59 PM PDT 24
Peak memory 192080 kb
Host smart-8c16dce1-1790-4581-a6fc-8140bc9e85de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693485033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3693485033
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.83568958
Short name T3
Test name
Test status
Simulation time 41315717617 ps
CPU time 59.74 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:02:56 PM PDT 24
Peak memory 192192 kb
Host smart-9e763695-c919-46e0-b631-784709be5bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83568958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.83568958
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1579601333
Short name T220
Test name
Test status
Simulation time 567926914 ps
CPU time 0.81 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 192096 kb
Host smart-5d9c0a25-ff22-4a33-bbe9-ce0ee585abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579601333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1579601333
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1135831470
Short name T157
Test name
Test status
Simulation time 441542214 ps
CPU time 0.73 seconds
Started Aug 06 07:01:59 PM PDT 24
Finished Aug 06 07:02:00 PM PDT 24
Peak memory 196908 kb
Host smart-1e7fea68-6e8f-450f-9dce-ca9493f0df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135831470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1135831470
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.871081367
Short name T265
Test name
Test status
Simulation time 1584275898 ps
CPU time 1.61 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 192136 kb
Host smart-e0d770f0-f091-4324-8872-92683cb57f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871081367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.871081367
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.476828870
Short name T240
Test name
Test status
Simulation time 470239283 ps
CPU time 0.79 seconds
Started Aug 06 07:02:06 PM PDT 24
Finished Aug 06 07:02:06 PM PDT 24
Peak memory 192108 kb
Host smart-c55d02a4-82a1-4ca4-b5bc-f8ff4fcbe773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476828870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.476828870
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3419419931
Short name T267
Test name
Test status
Simulation time 20928980361 ps
CPU time 32.41 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:42 PM PDT 24
Peak memory 192128 kb
Host smart-494b8cc2-217d-4e7b-b488-adec3c21897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419419931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3419419931
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1057860277
Short name T210
Test name
Test status
Simulation time 567593637 ps
CPU time 1.48 seconds
Started Aug 06 07:02:04 PM PDT 24
Finished Aug 06 07:02:05 PM PDT 24
Peak memory 196948 kb
Host smart-76cc4e2e-3d11-4c06-8971-15acfe9ff4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057860277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1057860277
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.331033888
Short name T182
Test name
Test status
Simulation time 515725068 ps
CPU time 0.9 seconds
Started Aug 06 07:02:18 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 197000 kb
Host smart-7362e793-c4a8-445b-a163-809e3606ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331033888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.331033888
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2256481845
Short name T248
Test name
Test status
Simulation time 14327316711 ps
CPU time 10.57 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:33 PM PDT 24
Peak memory 192152 kb
Host smart-36b6c92b-0d36-4233-9076-f94555e68b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256481845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2256481845
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2774018999
Short name T269
Test name
Test status
Simulation time 469288379 ps
CPU time 0.83 seconds
Started Aug 06 07:02:08 PM PDT 24
Finished Aug 06 07:02:09 PM PDT 24
Peak memory 192040 kb
Host smart-3566989a-3c02-4724-aeb6-da158082f280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774018999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2774018999
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1924814016
Short name T9
Test name
Test status
Simulation time 18970701942 ps
CPU time 14.79 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:02:26 PM PDT 24
Peak memory 197196 kb
Host smart-52ad8413-6578-40e3-9e85-8de4cf3418a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924814016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1924814016
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3920248045
Short name T105
Test name
Test status
Simulation time 567572476 ps
CPU time 1.34 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:02:17 PM PDT 24
Peak memory 196912 kb
Host smart-aaf240f7-8e8b-47a0-848a-98c0fc4cada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920248045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3920248045
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2861957091
Short name T259
Test name
Test status
Simulation time 13833318890 ps
CPU time 19.31 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:02:30 PM PDT 24
Peak memory 192212 kb
Host smart-0148deb8-a787-4e5e-ab6d-61cbb7ac6535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861957091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2861957091
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2872063188
Short name T235
Test name
Test status
Simulation time 466276805 ps
CPU time 0.92 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 192080 kb
Host smart-397f9283-e66d-4401-9a3d-40fbdafb8845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872063188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2872063188
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1145827576
Short name T272
Test name
Test status
Simulation time 38431281300 ps
CPU time 30.22 seconds
Started Aug 06 07:02:10 PM PDT 24
Finished Aug 06 07:02:40 PM PDT 24
Peak memory 192188 kb
Host smart-ba09eb4c-6699-4532-83bb-0b18c0817bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145827576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1145827576
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1533193800
Short name T29
Test name
Test status
Simulation time 533566756 ps
CPU time 0.74 seconds
Started Aug 06 07:02:08 PM PDT 24
Finished Aug 06 07:02:09 PM PDT 24
Peak memory 192076 kb
Host smart-b778f846-c44d-4da9-b838-1c11c8c74631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533193800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1533193800
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3685176896
Short name T233
Test name
Test status
Simulation time 15417155385 ps
CPU time 21.02 seconds
Started Aug 06 07:02:22 PM PDT 24
Finished Aug 06 07:02:44 PM PDT 24
Peak memory 192132 kb
Host smart-18a66b00-ca70-447f-9c5c-6c91244bdcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685176896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3685176896
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1758777328
Short name T231
Test name
Test status
Simulation time 435152170 ps
CPU time 0.89 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:10 PM PDT 24
Peak memory 192044 kb
Host smart-7ced155c-214e-4d21-b16d-ea5d9105a398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758777328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1758777328
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3661912391
Short name T238
Test name
Test status
Simulation time 40222124083 ps
CPU time 56.4 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:03:08 PM PDT 24
Peak memory 197160 kb
Host smart-634cc2e6-c197-43bf-a053-cebcf1ae6dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661912391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3661912391
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1235998483
Short name T209
Test name
Test status
Simulation time 391722425 ps
CPU time 0.72 seconds
Started Aug 06 07:02:11 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 192136 kb
Host smart-71609bb5-157d-44ba-a8b4-57a2e52cabb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235998483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1235998483
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3755055280
Short name T253
Test name
Test status
Simulation time 5514561476 ps
CPU time 7.8 seconds
Started Aug 06 07:01:32 PM PDT 24
Finished Aug 06 07:01:39 PM PDT 24
Peak memory 192136 kb
Host smart-308bbf61-b138-4450-a42e-e7caa2ae8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755055280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3755055280
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2827042580
Short name T24
Test name
Test status
Simulation time 8715178294 ps
CPU time 1.42 seconds
Started Aug 06 07:01:56 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 215928 kb
Host smart-edbe431c-bfe2-435a-b4ae-2d6033e1987d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827042580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2827042580
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1842479900
Short name T1
Test name
Test status
Simulation time 577325122 ps
CPU time 1.31 seconds
Started Aug 06 07:01:31 PM PDT 24
Finished Aug 06 07:01:32 PM PDT 24
Peak memory 196840 kb
Host smart-5462847b-6409-432f-8e13-dc385ca84269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842479900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1842479900
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3404808226
Short name T270
Test name
Test status
Simulation time 57500913001 ps
CPU time 40.44 seconds
Started Aug 06 07:02:09 PM PDT 24
Finished Aug 06 07:02:49 PM PDT 24
Peak memory 197204 kb
Host smart-1387471e-8423-4007-8b5b-ff9b2e707ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404808226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3404808226
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.728522627
Short name T249
Test name
Test status
Simulation time 500825993 ps
CPU time 1.26 seconds
Started Aug 06 07:02:10 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 196972 kb
Host smart-8978ccfe-6e4b-467e-8f7e-b40b80dd1a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728522627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.728522627
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3578918294
Short name T223
Test name
Test status
Simulation time 38081153237 ps
CPU time 4.69 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 192196 kb
Host smart-4f1b70d2-92a4-4668-9a2e-19ac915a8aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578918294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3578918294
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3997278218
Short name T263
Test name
Test status
Simulation time 399060892 ps
CPU time 0.75 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 192088 kb
Host smart-233a9d7e-76bd-4242-94bc-cb74c8a4b16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997278218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3997278218
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1159795196
Short name T274
Test name
Test status
Simulation time 9955362508 ps
CPU time 2.76 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:14 PM PDT 24
Peak memory 197172 kb
Host smart-76b8c72a-cf2a-40f7-a49a-8910a8b7d954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159795196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1159795196
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1884067415
Short name T236
Test name
Test status
Simulation time 483780013 ps
CPU time 1.22 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 196928 kb
Host smart-f137deef-122b-42a8-a474-81ed00b6c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884067415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1884067415
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4269217412
Short name T242
Test name
Test status
Simulation time 33463398155 ps
CPU time 52.88 seconds
Started Aug 06 07:02:16 PM PDT 24
Finished Aug 06 07:03:09 PM PDT 24
Peak memory 197172 kb
Host smart-162c0ebd-3a6f-403b-89ad-47aa78b9fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269217412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4269217412
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.799653457
Short name T221
Test name
Test status
Simulation time 522043062 ps
CPU time 1.33 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 196912 kb
Host smart-6ab9541b-a64e-4a99-ad1d-2cf0eec89cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799653457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.799653457
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3947439246
Short name T229
Test name
Test status
Simulation time 23732976772 ps
CPU time 4.52 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 192132 kb
Host smart-cc45ace5-5f94-441d-ab81-792d924d8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947439246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3947439246
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3043106313
Short name T260
Test name
Test status
Simulation time 520032437 ps
CPU time 0.79 seconds
Started Aug 06 07:02:19 PM PDT 24
Finished Aug 06 07:02:20 PM PDT 24
Peak memory 192112 kb
Host smart-e42dee88-c10c-4304-ab42-9f9400281c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043106313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3043106313
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3560452643
Short name T264
Test name
Test status
Simulation time 4834988654 ps
CPU time 7.8 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 197152 kb
Host smart-11bcc43c-0cfa-419a-bf57-cbcdd9a28186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560452643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3560452643
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1669131087
Short name T271
Test name
Test status
Simulation time 412629235 ps
CPU time 1.23 seconds
Started Aug 06 07:02:15 PM PDT 24
Finished Aug 06 07:02:16 PM PDT 24
Peak memory 191968 kb
Host smart-ec6c8c07-7642-470a-bf0d-93867ef6cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669131087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1669131087
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3123503083
Short name T213
Test name
Test status
Simulation time 35013145957 ps
CPU time 27.79 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:51 PM PDT 24
Peak memory 197148 kb
Host smart-3f37296c-df9a-4f59-8977-2339a0243866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123503083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3123503083
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4019560087
Short name T237
Test name
Test status
Simulation time 431880071 ps
CPU time 0.73 seconds
Started Aug 06 07:02:18 PM PDT 24
Finished Aug 06 07:02:19 PM PDT 24
Peak memory 192108 kb
Host smart-9ae1cdfc-0ade-4d34-a976-c75117cf15cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019560087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4019560087
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3991548855
Short name T177
Test name
Test status
Simulation time 486709612 ps
CPU time 1.28 seconds
Started Aug 06 07:02:10 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 196912 kb
Host smart-85ccb8f0-273c-4747-9983-cbfa07701bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991548855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3991548855
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2272955893
Short name T79
Test name
Test status
Simulation time 26185973641 ps
CPU time 42.79 seconds
Started Aug 06 07:02:17 PM PDT 24
Finished Aug 06 07:03:00 PM PDT 24
Peak memory 197136 kb
Host smart-56d5e9ef-8721-4690-b946-1bdf4ab37f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272955893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2272955893
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2756197344
Short name T95
Test name
Test status
Simulation time 410554590 ps
CPU time 0.87 seconds
Started Aug 06 07:02:25 PM PDT 24
Finished Aug 06 07:02:25 PM PDT 24
Peak memory 192064 kb
Host smart-04e9806f-29fe-4c39-83ab-6d7797dbca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756197344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2756197344
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2114240818
Short name T273
Test name
Test status
Simulation time 947528949 ps
CPU time 0.96 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 192124 kb
Host smart-d8ad9443-7ef0-4ca9-9efa-1518090bd127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114240818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2114240818
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2809104731
Short name T254
Test name
Test status
Simulation time 551333074 ps
CPU time 0.77 seconds
Started Aug 06 07:02:14 PM PDT 24
Finished Aug 06 07:02:15 PM PDT 24
Peak memory 192136 kb
Host smart-5e473932-f965-48cf-b7b5-05187157266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809104731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2809104731
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.295465794
Short name T219
Test name
Test status
Simulation time 43764398137 ps
CPU time 27.92 seconds
Started Aug 06 07:02:23 PM PDT 24
Finished Aug 06 07:02:51 PM PDT 24
Peak memory 192160 kb
Host smart-dcee8372-6534-4dda-a33b-1212b235493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295465794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.295465794
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1686817002
Short name T77
Test name
Test status
Simulation time 406193047 ps
CPU time 0.84 seconds
Started Aug 06 07:02:12 PM PDT 24
Finished Aug 06 07:02:13 PM PDT 24
Peak memory 192112 kb
Host smart-9023dae4-0ada-4e22-9a3a-4f087142befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686817002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1686817002
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.525492762
Short name T181
Test name
Test status
Simulation time 487727903 ps
CPU time 0.9 seconds
Started Aug 06 07:01:41 PM PDT 24
Finished Aug 06 07:01:42 PM PDT 24
Peak memory 196944 kb
Host smart-c2d1d16c-1378-4964-b49b-2cc76a4a448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525492762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.525492762
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4163924678
Short name T266
Test name
Test status
Simulation time 703145818 ps
CPU time 1.59 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:01:49 PM PDT 24
Peak memory 196820 kb
Host smart-647cdd05-2d6d-455b-9a11-9ae300653447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163924678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4163924678
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2340546650
Short name T215
Test name
Test status
Simulation time 477032691 ps
CPU time 0.67 seconds
Started Aug 06 07:02:00 PM PDT 24
Finished Aug 06 07:02:01 PM PDT 24
Peak memory 192112 kb
Host smart-630feb3b-df50-4c91-9a7a-45a10227fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340546650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2340546650
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2830224302
Short name T53
Test name
Test status
Simulation time 12269195772 ps
CPU time 5.47 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:01:53 PM PDT 24
Peak memory 192192 kb
Host smart-c73bbac9-b8e6-47bc-8df7-0a7fb07080d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830224302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2830224302
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3873834669
Short name T225
Test name
Test status
Simulation time 515220293 ps
CPU time 1.35 seconds
Started Aug 06 07:01:51 PM PDT 24
Finished Aug 06 07:01:53 PM PDT 24
Peak memory 192104 kb
Host smart-43ffee99-9bcc-48f6-909d-344d0a6a4da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873834669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3873834669
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.524247833
Short name T11
Test name
Test status
Simulation time 16913507732 ps
CPU time 12.71 seconds
Started Aug 06 07:01:58 PM PDT 24
Finished Aug 06 07:02:11 PM PDT 24
Peak memory 192172 kb
Host smart-8ed3cd2f-3306-4ab5-b4d6-361873000e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524247833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.524247833
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2510255335
Short name T257
Test name
Test status
Simulation time 574092470 ps
CPU time 0.77 seconds
Started Aug 06 07:02:01 PM PDT 24
Finished Aug 06 07:02:02 PM PDT 24
Peak memory 192028 kb
Host smart-4d412333-c2ed-4ea9-9cbb-557387b0fe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510255335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2510255335
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.111215441
Short name T172
Test name
Test status
Simulation time 568712901 ps
CPU time 0.81 seconds
Started Aug 06 07:01:35 PM PDT 24
Finished Aug 06 07:01:36 PM PDT 24
Peak memory 196924 kb
Host smart-a0ab7ded-3a4c-4e8a-986f-e9c30cb802b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111215441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.111215441
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.35453584
Short name T247
Test name
Test status
Simulation time 27660008212 ps
CPU time 40.8 seconds
Started Aug 06 07:01:50 PM PDT 24
Finished Aug 06 07:02:31 PM PDT 24
Peak memory 192164 kb
Host smart-535078a9-eda0-4c9e-9365-6bd92920d01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35453584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.35453584
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1639213735
Short name T207
Test name
Test status
Simulation time 435973691 ps
CPU time 1.01 seconds
Started Aug 06 07:01:49 PM PDT 24
Finished Aug 06 07:01:50 PM PDT 24
Peak memory 196872 kb
Host smart-ef0335cb-a3ac-4f74-b35b-14331149b193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639213735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1639213735
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1915863917
Short name T214
Test name
Test status
Simulation time 35784967407 ps
CPU time 3.91 seconds
Started Aug 06 07:01:52 PM PDT 24
Finished Aug 06 07:01:57 PM PDT 24
Peak memory 192152 kb
Host smart-a3976f35-7af0-45f3-b7ce-5a7398664eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915863917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1915863917
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2623563538
Short name T243
Test name
Test status
Simulation time 509492920 ps
CPU time 1.27 seconds
Started Aug 06 07:01:47 PM PDT 24
Finished Aug 06 07:01:48 PM PDT 24
Peak memory 196968 kb
Host smart-872f27f5-8647-4031-9179-28e8dea80c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623563538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2623563538
Directory /workspace/9.aon_timer_smoke/latest
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