Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30544	1		T1	267		T2	62		T3	12
bark[1]	410	1		T16	26		T139	47		T137	21
bark[2]	758	1		T93	26		T118	21		T108	44
bark[3]	1079	1		T123	21		T125	21		T90	165
bark[4]	401	1		T5	26		T31	21		T16	21
bark[5]	354	1		T49	42		T111	21		T118	26
bark[6]	220	1		T7	14		T113	14		T118	21
bark[7]	326	1		T60	14		T92	26		T117	14
bark[8]	735	1		T175	14		T42	121		T67	21
bark[9]	543	1		T1	21		T6	73		T33	14
bark[10]	541	1		T5	66		T17	21		T46	21
bark[11]	265	1		T40	21		T46	40		T129	14
bark[12]	468	1		T131	14		T118	26		T186	220
bark[13]	760	1		T40	35		T46	21		T66	14
bark[14]	655	1		T8	246		T40	201		T41	21
bark[15]	210	1		T42	21		T43	28		T97	21
bark[16]	804	1		T40	21		T49	45		T21	21
bark[17]	662	1		T8	7		T18	21		T40	21
bark[18]	795	1		T31	65		T142	14		T139	21
bark[19]	138	1		T4	14		T164	21		T120	21
bark[20]	505	1		T5	56		T8	7		T41	26
bark[21]	852	1		T16	31		T17	14		T18	42
bark[22]	682	1		T5	65		T17	47		T107	21
bark[23]	278	1		T6	5		T107	21		T100	14
bark[24]	229	1		T41	48		T66	21		T67	38
bark[25]	224	1		T18	21		T130	14		T132	61
bark[26]	519	1		T91	14		T46	26		T192	14
bark[27]	465	1		T5	43		T18	21		T41	21
bark[28]	362	1		T18	61		T41	73		T171	14
bark[29]	593	1		T11	14		T46	21		T139	21
bark[30]	448	1		T6	21		T17	21		T41	26
bark[31]	374	1		T49	21		T149	14		T139	48
bark_0	4846	1		T1	7		T2	42		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30139	1		T1	266		T2	58		T3	11
bite[1]	429	1		T17	13		T18	21		T100	13
bite[2]	640	1		T67	21		T139	21		T97	21
bite[3]	486	1		T18	42		T107	21		T195	13
bite[4]	1144	1		T1	21		T5	65		T18	21
bite[5]	248	1		T46	26		T41	47		T142	13
bite[6]	193	1		T8	6		T33	13		T17	47
bite[7]	358	1		T31	64		T16	26		T40	21
bite[8]	1183	1		T5	64		T40	200		T118	309
bite[9]	150	1		T86	25		T164	57		T189	13
bite[10]	220	1		T5	55		T166	71		T21	25
bite[11]	486	1		T16	21		T107	21		T49	45
bite[12]	660	1		T41	97		T175	13		T42	44
bite[13]	360	1		T5	26		T46	40		T41	26
bite[14]	457	1		T31	21		T113	13		T161	13
bite[15]	1435	1		T7	13		T42	125		T66	21
bite[16]	208	1		T41	21		T67	21		T44	21
bite[17]	670	1		T5	42		T6	72		T91	13
bite[18]	469	1		T46	21		T44	21		T150	21
bite[19]	661	1		T8	245		T40	21		T49	21
bite[20]	510	1		T18	61		T63	13		T66	13
bite[21]	453	1		T18	21		T46	21		T60	13
bite[22]	656	1		T149	13		T92	25		T150	153
bite[23]	712	1		T6	21		T8	6		T46	21
bite[24]	399	1		T67	38		T118	21		T108	21
bite[25]	361	1		T6	4		T16	31		T40	21
bite[26]	194	1		T43	72		T93	46		T174	21
bite[27]	456	1		T17	42		T40	42		T192	13
bite[28]	219	1		T94	101		T88	21		T115	21
bite[29]	585	1		T49	21		T92	21		T167	6
bite[30]	441	1		T4	13		T11	13		T136	21
bite[31]	115	1		T40	35		T42	42		T164	21
bite_0	5348	1		T1	8		T2	46		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45170	1		T1	276		T2	104		T3	19
auto[1]	5875	1		T1	19		T12	7		T30	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	2	1		T186	2		-	-		-	-
prescale[0]	1454	1		T6	33		T8	19		T107	40
prescale[1]	1206	1		T16	65		T40	128		T66	19
prescale[2]	846	1		T5	19		T6	31		T40	19
prescale[3]	789	1		T45	9		T92	16		T93	24
prescale[4]	647	1		T2	2		T31	24		T18	9
prescale[5]	519	1		T1	19		T8	2		T40	44
prescale[6]	1088	1		T1	58		T5	2		T40	70
prescale[7]	960	1		T5	14		T6	2		T31	2
prescale[8]	669	1		T16	14		T107	38		T42	19
prescale[9]	1105	1		T6	2		T107	19		T136	19
prescale[10]	1112	1		T8	19		T18	19		T40	62
prescale[11]	908	1		T2	2		T31	2		T92	159
prescale[12]	834	1		T6	2		T111	24		T137	23
prescale[13]	770	1		T8	2		T10	9		T41	135
prescale[14]	726	1		T40	53		T41	2		T49	19
prescale[15]	563	1		T8	2		T40	23		T202	9
prescale[16]	794	1		T5	34		T107	57		T170	50
prescale[17]	828	1		T203	9		T92	54		T93	96
prescale[18]	1275	1		T5	19		T31	92		T49	23
prescale[19]	737	1		T1	143		T48	9		T41	2
prescale[20]	903	1		T40	161		T46	9		T43	2
prescale[21]	787	1		T5	2		T17	19		T18	40
prescale[22]	553	1		T5	4		T40	70		T47	9
prescale[23]	862	1		T2	2		T16	19		T40	2
prescale[24]	824	1		T8	4		T40	19		T92	2
prescale[25]	514	1		T5	46		T204	9		T66	23
prescale[26]	311	1		T8	2		T93	2		T166	36
prescale[27]	973	1		T5	40		T40	54		T41	23
prescale[28]	456	1		T40	96		T67	19		T205	9
prescale[29]	657	1		T3	9		T8	2		T17	32
prescale[30]	1136	1		T16	44		T18	24		T40	9
prescale[31]	620	1		T18	40		T40	30		T86	4
prescale_0	24619	1		T1	75		T2	98		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37977	1		T1	237		T2	60		T3	9
auto[1]	13068	1		T1	58		T2	44		T3	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51045	1		T1	295		T2	104		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30586	1		T1	196		T2	49		T3	14
wkup[1]	318	1		T93	21		T118	47		T94	21
wkup[2]	183	1		T7	15		T41	6		T87	63
wkup[3]	186	1		T6	21		T42	21		T118	21
wkup[4]	149	1		T92	42		T93	26		T140	15
wkup[5]	224	1		T46	21		T66	15		T44	21
wkup[6]	262	1		T8	8		T40	8		T113	15
wkup[7]	245	1		T40	21		T44	21		T86	21
wkup[8]	183	1		T40	21		T63	15		T93	21
wkup[9]	233	1		T40	30		T41	21		T164	21
wkup[10]	176	1		T40	21		T97	21		T29	21
wkup[11]	216	1		T40	21		T67	47		T139	21
wkup[12]	347	1		T1	31		T40	26		T41	26
wkup[13]	194	1		T87	44		T88	21		T125	21
wkup[14]	339	1		T5	39		T16	21		T40	35
wkup[15]	246	1		T5	21		T137	30		T138	15
wkup[16]	192	1		T8	21		T31	21		T118	21
wkup[17]	332	1		T31	21		T41	61		T42	21
wkup[18]	281	1		T8	21		T107	21		T46	21
wkup[19]	299	1		T17	30		T40	21		T41	21
wkup[20]	226	1		T170	26		T93	15		T118	30
wkup[21]	401	1		T6	42		T40	21		T42	21
wkup[22]	324	1		T1	21		T8	21		T16	21
wkup[23]	294	1		T6	21		T18	21		T60	15
wkup[24]	267	1		T6	6		T92	21		T191	15
wkup[25]	260	1		T41	26		T42	21		T43	21
wkup[26]	264	1		T18	21		T86	30		T118	21
wkup[27]	273	1		T8	35		T17	21		T46	26
wkup[28]	274	1		T100	15		T42	21		T137	21
wkup[29]	181	1		T175	15		T29	51		T89	21
wkup[30]	267	1		T87	21		T167	21		T89	42
wkup[31]	267	1		T18	21		T46	21		T92	21
wkup[32]	149	1		T41	8		T118	21		T88	21
wkup[33]	274	1		T6	21		T17	15		T107	26
wkup[34]	363	1		T8	26		T11	15		T31	39
wkup[35]	373	1		T40	21		T118	42		T166	21
wkup[36]	196	1		T2	21		T18	21		T43	8
wkup[37]	196	1		T44	15		T131	15		T88	24
wkup[38]	207	1		T107	21		T67	21		T118	39
wkup[39]	307	1		T5	26		T171	15		T43	21
wkup[40]	314	1		T1	21		T5	30		T40	21
wkup[41]	157	1		T5	21		T67	21		T139	21
wkup[42]	231	1		T40	15		T49	21		T94	21
wkup[43]	316	1		T8	8		T33	15		T41	42
wkup[44]	305	1		T66	21		T108	21		T87	21
wkup[45]	426	1		T5	21		T8	21		T91	15
wkup[46]	267	1		T40	8		T86	47		T93	21
wkup[47]	195	1		T149	15		T92	42		T118	21
wkup[48]	328	1		T40	21		T49	47		T92	21
wkup[49]	229	1		T18	21		T44	15		T114	42
wkup[50]	263	1		T5	21		T16	26		T17	21
wkup[51]	214	1		T6	21		T139	21		T150	26
wkup[52]	442	1		T1	21		T40	42		T195	15
wkup[53]	403	1		T18	21		T40	35		T46	21
wkup[54]	270	1		T41	21		T43	21		T170	21
wkup[55]	322	1		T6	26		T8	30		T31	21
wkup[56]	331	1		T5	21		T46	21		T41	21
wkup[57]	330	1		T5	21		T40	15		T137	26
wkup[58]	224	1		T139	21		T93	36		T118	21
wkup[59]	217	1		T4	15		T46	21		T136	15
wkup[60]	298	1		T6	21		T40	42		T66	21
wkup[61]	133	1		T18	21		T40	26		T129	15
wkup[62]	289	1		T16	31		T43	21		T92	26
wkup[63]	224	1		T41	21		T43	29		T136	21
wkup_0	3763	1		T1	5		T2	34		T3	5