Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.81 99.33 93.67 100.00 98.40 99.51 47.98


Total test records in report: 422
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T35 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1333098794 Aug 07 05:50:06 PM PDT 24 Aug 07 05:50:07 PM PDT 24 387439508 ps
T288 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1828219801 Aug 07 05:49:54 PM PDT 24 Aug 07 05:49:55 PM PDT 24 346014821 ps
T39 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4135236370 Aug 07 05:49:50 PM PDT 24 Aug 07 05:49:51 PM PDT 24 605653042 ps
T206 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.958636598 Aug 07 05:50:09 PM PDT 24 Aug 07 05:50:11 PM PDT 24 450103796 ps
T36 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2007649921 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:18 PM PDT 24 442821765 ps
T37 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3692427618 Aug 07 05:49:49 PM PDT 24 Aug 07 05:50:01 PM PDT 24 8512425223 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2729410451 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:19 PM PDT 24 1488135280 ps
T289 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.223200044 Aug 07 05:50:16 PM PDT 24 Aug 07 05:50:17 PM PDT 24 467756911 ps
T290 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2974513296 Aug 07 05:49:57 PM PDT 24 Aug 07 05:49:57 PM PDT 24 324021130 ps
T291 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.629968358 Aug 07 05:50:23 PM PDT 24 Aug 07 05:50:24 PM PDT 24 346494271 ps
T292 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3223315753 Aug 07 05:50:19 PM PDT 24 Aug 07 05:50:20 PM PDT 24 799584978 ps
T293 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1510830441 Aug 07 05:49:35 PM PDT 24 Aug 07 05:49:35 PM PDT 24 293394675 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.899409467 Aug 07 05:49:50 PM PDT 24 Aug 07 05:49:51 PM PDT 24 1424880721 ps
T295 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1392646530 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:08 PM PDT 24 330884920 ps
T296 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2732303839 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:21 PM PDT 24 474895970 ps
T297 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4053089460 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:00 PM PDT 24 468786833 ps
T298 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2793918010 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:19 PM PDT 24 360927243 ps
T78 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3897094847 Aug 07 05:50:13 PM PDT 24 Aug 07 05:50:14 PM PDT 24 403443991 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3692329318 Aug 07 05:49:36 PM PDT 24 Aug 07 05:49:40 PM PDT 24 2474514280 ps
T299 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1543136749 Aug 07 05:50:04 PM PDT 24 Aug 07 05:50:05 PM PDT 24 434376997 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4018373806 Aug 07 05:49:37 PM PDT 24 Aug 07 05:49:39 PM PDT 24 1093422967 ps
T38 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.713083546 Aug 07 05:49:55 PM PDT 24 Aug 07 05:50:01 PM PDT 24 7873439581 ps
T196 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3115425280 Aug 07 05:49:51 PM PDT 24 Aug 07 05:50:00 PM PDT 24 4740652636 ps
T53 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2290331185 Aug 07 05:50:06 PM PDT 24 Aug 07 05:50:07 PM PDT 24 332344307 ps
T301 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1462687674 Aug 07 05:50:18 PM PDT 24 Aug 07 05:50:31 PM PDT 24 8088735306 ps
T79 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.275000055 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:09 PM PDT 24 2975891258 ps
T54 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2146363871 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:18 PM PDT 24 312401397 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3404868238 Aug 07 05:49:49 PM PDT 24 Aug 07 05:49:50 PM PDT 24 510189547 ps
T303 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.736051669 Aug 07 05:50:00 PM PDT 24 Aug 07 05:50:02 PM PDT 24 411556852 ps
T201 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1152319313 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:05 PM PDT 24 4103352648 ps
T80 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1063808235 Aug 07 05:50:18 PM PDT 24 Aug 07 05:50:22 PM PDT 24 1801115898 ps
T200 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3220378562 Aug 07 05:50:12 PM PDT 24 Aug 07 05:50:24 PM PDT 24 8810978079 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.617429849 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:02 PM PDT 24 1253857038 ps
T81 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4265804726 Aug 07 05:49:57 PM PDT 24 Aug 07 05:50:00 PM PDT 24 2228826673 ps
T82 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.734689753 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:57 PM PDT 24 511604101 ps
T305 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2314784636 Aug 07 05:50:00 PM PDT 24 Aug 07 05:50:00 PM PDT 24 323645265 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4003222811 Aug 07 05:50:09 PM PDT 24 Aug 07 05:50:10 PM PDT 24 460033216 ps
T55 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2725196581 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:12 PM PDT 24 544288187 ps
T83 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3824988776 Aug 07 05:50:35 PM PDT 24 Aug 07 05:50:36 PM PDT 24 2107050325 ps
T307 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2732776474 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:25 PM PDT 24 522499323 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1639262011 Aug 07 05:49:34 PM PDT 24 Aug 07 05:49:35 PM PDT 24 523254663 ps
T308 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.685462676 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:08 PM PDT 24 458594208 ps
T309 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3400346729 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:22 PM PDT 24 522698263 ps
T57 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1655689317 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:08 PM PDT 24 538836422 ps
T84 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3239605456 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:09 PM PDT 24 2269037647 ps
T310 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1573422139 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:18 PM PDT 24 433838591 ps
T311 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1042178629 Aug 07 05:50:15 PM PDT 24 Aug 07 05:50:16 PM PDT 24 344622333 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1808921669 Aug 07 05:49:41 PM PDT 24 Aug 07 05:49:42 PM PDT 24 386163279 ps
T85 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1119631220 Aug 07 05:49:48 PM PDT 24 Aug 07 05:49:51 PM PDT 24 3142545517 ps
T313 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1372556196 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:19 PM PDT 24 396173444 ps
T314 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3426988830 Aug 07 05:50:23 PM PDT 24 Aug 07 05:50:23 PM PDT 24 456908580 ps
T315 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3083665008 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:22 PM PDT 24 446137957 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2582467248 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:10 PM PDT 24 4220779003 ps
T317 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1803965635 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:09 PM PDT 24 2515253437 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4264504227 Aug 07 05:49:48 PM PDT 24 Aug 07 05:49:49 PM PDT 24 562928847 ps
T197 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.847594547 Aug 07 05:50:01 PM PDT 24 Aug 07 05:50:03 PM PDT 24 9541534531 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1940515255 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:47 PM PDT 24 563201113 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.668346507 Aug 07 05:49:54 PM PDT 24 Aug 07 05:50:00 PM PDT 24 2380953881 ps
T320 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2655864904 Aug 07 05:50:18 PM PDT 24 Aug 07 05:50:19 PM PDT 24 421945829 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2397895871 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:57 PM PDT 24 580635290 ps
T69 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3836363612 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:47 PM PDT 24 708170992 ps
T322 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2365460991 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:09 PM PDT 24 304832037 ps
T323 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.385270581 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:23 PM PDT 24 367488984 ps
T70 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3843614997 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:04 PM PDT 24 308511281 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4117952748 Aug 07 05:50:16 PM PDT 24 Aug 07 05:50:18 PM PDT 24 672759794 ps
T325 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2555260854 Aug 07 05:50:06 PM PDT 24 Aug 07 05:50:07 PM PDT 24 403236596 ps
T326 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3290871137 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:22 PM PDT 24 484017925 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3255400763 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:01 PM PDT 24 1399947408 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.389120546 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:08 PM PDT 24 454961892 ps
T329 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1741742618 Aug 07 05:50:22 PM PDT 24 Aug 07 05:50:23 PM PDT 24 301274997 ps
T330 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1151910212 Aug 07 05:50:05 PM PDT 24 Aug 07 05:50:17 PM PDT 24 7503598204 ps
T331 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3336114239 Aug 07 05:49:51 PM PDT 24 Aug 07 05:49:53 PM PDT 24 477506202 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.906883652 Aug 07 05:49:39 PM PDT 24 Aug 07 05:49:41 PM PDT 24 767734192 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.976434679 Aug 07 05:49:51 PM PDT 24 Aug 07 05:49:52 PM PDT 24 555048411 ps
T333 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2556967744 Aug 07 05:50:10 PM PDT 24 Aug 07 05:50:11 PM PDT 24 315696821 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3969035353 Aug 07 05:50:10 PM PDT 24 Aug 07 05:50:14 PM PDT 24 2872040170 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.694561601 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:53 PM PDT 24 396889234 ps
T336 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3178189530 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:06 PM PDT 24 2099788101 ps
T72 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1248839431 Aug 07 05:49:41 PM PDT 24 Aug 07 05:49:43 PM PDT 24 854214607 ps
T337 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.764788236 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:00 PM PDT 24 365867776 ps
T338 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4097778806 Aug 07 05:50:13 PM PDT 24 Aug 07 05:50:15 PM PDT 24 1779470121 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2063855443 Aug 07 05:49:43 PM PDT 24 Aug 07 05:49:49 PM PDT 24 4094547879 ps
T198 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.842122812 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:18 PM PDT 24 4295687748 ps
T199 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3327423107 Aug 07 05:50:00 PM PDT 24 Aug 07 05:50:05 PM PDT 24 8362786053 ps
T340 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2596584729 Aug 07 05:50:12 PM PDT 24 Aug 07 05:50:13 PM PDT 24 456463846 ps
T341 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.450707803 Aug 07 05:50:08 PM PDT 24 Aug 07 05:50:09 PM PDT 24 310267391 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2052407162 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:46 PM PDT 24 320659334 ps
T343 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3608796629 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:58 PM PDT 24 553214754 ps
T344 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4076051632 Aug 07 05:50:20 PM PDT 24 Aug 07 05:50:21 PM PDT 24 296139592 ps
T76 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.508394204 Aug 07 05:49:38 PM PDT 24 Aug 07 05:49:39 PM PDT 24 569455717 ps
T345 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2980732026 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:24 PM PDT 24 484972523 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2738180005 Aug 07 05:49:40 PM PDT 24 Aug 07 05:49:41 PM PDT 24 457315490 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3611765528 Aug 07 05:49:41 PM PDT 24 Aug 07 05:49:49 PM PDT 24 4555530835 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2604533210 Aug 07 05:49:44 PM PDT 24 Aug 07 05:49:45 PM PDT 24 340857933 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1358318961 Aug 07 05:49:41 PM PDT 24 Aug 07 05:49:42 PM PDT 24 509552769 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1006142677 Aug 07 05:49:40 PM PDT 24 Aug 07 05:50:02 PM PDT 24 7801006119 ps
T350 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1962816637 Aug 07 05:50:10 PM PDT 24 Aug 07 05:50:11 PM PDT 24 344689993 ps
T351 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1549531997 Aug 07 05:50:23 PM PDT 24 Aug 07 05:50:24 PM PDT 24 407535736 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.425158134 Aug 07 05:50:06 PM PDT 24 Aug 07 05:50:08 PM PDT 24 417852733 ps
T353 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.450309758 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:25 PM PDT 24 316692776 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.810875536 Aug 07 05:49:38 PM PDT 24 Aug 07 05:49:39 PM PDT 24 427143778 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2251971540 Aug 07 05:49:36 PM PDT 24 Aug 07 05:49:36 PM PDT 24 524430516 ps
T356 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.859692225 Aug 07 05:49:57 PM PDT 24 Aug 07 05:50:01 PM PDT 24 4340710543 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1829060879 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:47 PM PDT 24 316558733 ps
T358 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2546153323 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:12 PM PDT 24 560970969 ps
T359 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.23741580 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:12 PM PDT 24 409162301 ps
T360 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2031795867 Aug 07 05:50:23 PM PDT 24 Aug 07 05:50:24 PM PDT 24 300689186 ps
T74 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.376153082 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:47 PM PDT 24 515356276 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2090305011 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:56 PM PDT 24 313277954 ps
T362 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3133012391 Aug 07 05:50:16 PM PDT 24 Aug 07 05:50:17 PM PDT 24 503592061 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2813122850 Aug 07 05:49:58 PM PDT 24 Aug 07 05:49:59 PM PDT 24 301010849 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1070667861 Aug 07 05:49:44 PM PDT 24 Aug 07 05:49:45 PM PDT 24 1088176316 ps
T364 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.666188015 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:13 PM PDT 24 491215831 ps
T365 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2044360303 Aug 07 05:49:54 PM PDT 24 Aug 07 05:49:58 PM PDT 24 2590922768 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2233271181 Aug 07 05:50:05 PM PDT 24 Aug 07 05:50:09 PM PDT 24 4246485237 ps
T367 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4207179939 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:25 PM PDT 24 339768065 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2402415119 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:52 PM PDT 24 281818715 ps
T369 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1672159964 Aug 07 05:50:25 PM PDT 24 Aug 07 05:50:25 PM PDT 24 400466504 ps
T370 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3031080709 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:25 PM PDT 24 487855274 ps
T371 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.714171826 Aug 07 05:50:01 PM PDT 24 Aug 07 05:50:04 PM PDT 24 1329631663 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.364633065 Aug 07 05:49:46 PM PDT 24 Aug 07 05:49:48 PM PDT 24 3138292721 ps
T372 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1532926460 Aug 07 05:50:21 PM PDT 24 Aug 07 05:50:22 PM PDT 24 388049137 ps
T373 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3714248835 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:04 PM PDT 24 384279131 ps
T374 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1394336636 Aug 07 05:50:02 PM PDT 24 Aug 07 05:50:03 PM PDT 24 516343724 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2066906920 Aug 07 05:50:13 PM PDT 24 Aug 07 05:50:16 PM PDT 24 593064869 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.467150775 Aug 07 05:49:53 PM PDT 24 Aug 07 05:49:57 PM PDT 24 2802218068 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.632474572 Aug 07 05:49:51 PM PDT 24 Aug 07 05:49:52 PM PDT 24 309134247 ps
T378 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1483749335 Aug 07 05:50:11 PM PDT 24 Aug 07 05:50:13 PM PDT 24 830967143 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1567440842 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:59 PM PDT 24 7973080754 ps
T380 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.638884204 Aug 07 05:50:16 PM PDT 24 Aug 07 05:50:16 PM PDT 24 310252844 ps
T381 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3709553709 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:18 PM PDT 24 517412321 ps
T382 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2193256348 Aug 07 05:50:25 PM PDT 24 Aug 07 05:50:25 PM PDT 24 356646088 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.116542546 Aug 07 05:50:12 PM PDT 24 Aug 07 05:50:13 PM PDT 24 412955431 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.769529896 Aug 07 05:49:45 PM PDT 24 Aug 07 05:50:17 PM PDT 24 11677013102 ps
T385 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1857811703 Aug 07 05:50:10 PM PDT 24 Aug 07 05:50:12 PM PDT 24 4668532161 ps
T386 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.594669592 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:01 PM PDT 24 468561610 ps
T387 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3888393806 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:55 PM PDT 24 524421729 ps
T388 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1815585365 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:52 PM PDT 24 531017920 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1462351178 Aug 07 05:50:12 PM PDT 24 Aug 07 05:50:14 PM PDT 24 317459438 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.991708052 Aug 07 05:50:07 PM PDT 24 Aug 07 05:50:11 PM PDT 24 2107445642 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1195685588 Aug 07 05:50:19 PM PDT 24 Aug 07 05:50:34 PM PDT 24 8130894269 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3108372460 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:54 PM PDT 24 506145971 ps
T393 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1051980266 Aug 07 05:50:20 PM PDT 24 Aug 07 05:50:21 PM PDT 24 484078466 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.93687221 Aug 07 05:49:56 PM PDT 24 Aug 07 05:49:57 PM PDT 24 540592259 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1471012508 Aug 07 05:49:42 PM PDT 24 Aug 07 05:49:47 PM PDT 24 2517936301 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3025205209 Aug 07 05:49:56 PM PDT 24 Aug 07 05:49:57 PM PDT 24 297254775 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.364870468 Aug 07 05:49:43 PM PDT 24 Aug 07 05:49:44 PM PDT 24 437371889 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2895257222 Aug 07 05:49:56 PM PDT 24 Aug 07 05:49:59 PM PDT 24 4567103805 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4027357127 Aug 07 05:49:43 PM PDT 24 Aug 07 05:49:44 PM PDT 24 461406045 ps
T400 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.459433011 Aug 07 05:50:15 PM PDT 24 Aug 07 05:50:17 PM PDT 24 1520501855 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3594553662 Aug 07 05:49:40 PM PDT 24 Aug 07 05:49:41 PM PDT 24 530016624 ps
T402 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2195870621 Aug 07 05:50:24 PM PDT 24 Aug 07 05:50:25 PM PDT 24 330312758 ps
T403 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.890332296 Aug 07 05:50:09 PM PDT 24 Aug 07 05:50:11 PM PDT 24 1129555804 ps
T404 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.145270309 Aug 07 05:50:19 PM PDT 24 Aug 07 05:50:21 PM PDT 24 495231166 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3509782375 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:53 PM PDT 24 413443174 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2966467498 Aug 07 05:49:55 PM PDT 24 Aug 07 05:49:56 PM PDT 24 469759325 ps
T407 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.723948022 Aug 07 05:50:19 PM PDT 24 Aug 07 05:50:19 PM PDT 24 343318761 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4202291042 Aug 07 05:49:49 PM PDT 24 Aug 07 05:49:50 PM PDT 24 318305308 ps
T409 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2615029592 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:18 PM PDT 24 495058061 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2574882698 Aug 07 05:49:34 PM PDT 24 Aug 07 05:49:39 PM PDT 24 8816059240 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1132104239 Aug 07 05:49:41 PM PDT 24 Aug 07 05:49:43 PM PDT 24 2384590619 ps
T412 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3445293847 Aug 07 05:50:05 PM PDT 24 Aug 07 05:50:08 PM PDT 24 344147980 ps
T413 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.217420148 Aug 07 05:49:59 PM PDT 24 Aug 07 05:50:01 PM PDT 24 417433676 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1852710722 Aug 07 05:49:37 PM PDT 24 Aug 07 05:49:39 PM PDT 24 2305719949 ps
T415 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.724196602 Aug 07 05:49:54 PM PDT 24 Aug 07 05:49:56 PM PDT 24 468970136 ps
T416 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.603732846 Aug 07 05:49:52 PM PDT 24 Aug 07 05:49:53 PM PDT 24 578060198 ps
T417 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.432167198 Aug 07 05:50:17 PM PDT 24 Aug 07 05:50:19 PM PDT 24 518077215 ps
T418 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1581159770 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:05 PM PDT 24 429919478 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.35475787 Aug 07 05:49:40 PM PDT 24 Aug 07 05:49:41 PM PDT 24 512217079 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1966387531 Aug 07 05:49:34 PM PDT 24 Aug 07 05:49:35 PM PDT 24 447896409 ps
T421 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3575626262 Aug 07 05:50:06 PM PDT 24 Aug 07 05:50:07 PM PDT 24 447754736 ps
T422 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.664748630 Aug 07 05:50:03 PM PDT 24 Aug 07 05:50:04 PM PDT 24 458282921 ps

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4274237279
Short name T8
Test name
Test status
Simulation time 67313049007 ps
CPU time 336.53 seconds
Started Aug 07 05:48:20 PM PDT 24
Finished Aug 07 05:53:57 PM PDT 24
Peak memory 206944 kb
Host smart-11a301ab-d5e3-4e0e-bb1b-2c3e76f49983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274237279 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4274237279
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1199664006
Short name T5
Test name
Test status
Simulation time 35358702626 ps
CPU time 197.33 seconds
Started Aug 07 05:48:48 PM PDT 24
Finished Aug 07 05:52:06 PM PDT 24
Peak memory 198748 kb
Host smart-07643d9c-9cab-44c1-96ed-adacb8ab9fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199664006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1199664006
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3040530486
Short name T46
Test name
Test status
Simulation time 123089419306 ps
CPU time 40.11 seconds
Started Aug 07 05:49:02 PM PDT 24
Finished Aug 07 05:49:42 PM PDT 24
Peak memory 184992 kb
Host smart-892452c4-fc5b-42aa-a031-c376ea1b942f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040530486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3040530486
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3692427618
Short name T37
Test name
Test status
Simulation time 8512425223 ps
CPU time 11.51 seconds
Started Aug 07 05:49:49 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 198380 kb
Host smart-7165b89c-dfbf-4fc2-8cb1-eacf09e7b427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692427618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3692427618
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3259282855
Short name T50
Test name
Test status
Simulation time 215413923240 ps
CPU time 647.43 seconds
Started Aug 07 05:49:05 PM PDT 24
Finished Aug 07 05:59:53 PM PDT 24
Peak memory 214752 kb
Host smart-0ed65199-6636-41d6-b1ac-5e79ddbf88fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259282855 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3259282855
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1484411128
Short name T40
Test name
Test status
Simulation time 360451025853 ps
CPU time 587.67 seconds
Started Aug 07 05:48:41 PM PDT 24
Finished Aug 07 05:58:29 PM PDT 24
Peak memory 213336 kb
Host smart-3f1e83a5-b35a-40af-8bee-60b776290a83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484411128 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1484411128
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.244729396
Short name T103
Test name
Test status
Simulation time 345323342010 ps
CPU time 1006.75 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 06:06:23 PM PDT 24
Peak memory 210644 kb
Host smart-0e07405a-1e26-438c-92d1-ca89f022bd57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244729396 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.244729396
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2419425684
Short name T88
Test name
Test status
Simulation time 451067938817 ps
CPU time 868.98 seconds
Started Aug 07 05:48:26 PM PDT 24
Finished Aug 07 06:02:55 PM PDT 24
Peak memory 215156 kb
Host smart-44eb1f55-0fb5-4cf1-b22e-93bc29174ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419425684 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2419425684
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3585290479
Short name T114
Test name
Test status
Simulation time 294664985153 ps
CPU time 657.98 seconds
Started Aug 07 05:49:10 PM PDT 24
Finished Aug 07 06:00:08 PM PDT 24
Peak memory 206024 kb
Host smart-fe1ecfba-ae5b-4923-aafb-c8169d315398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585290479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3585290479
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1031086181
Short name T92
Test name
Test status
Simulation time 251575769704 ps
CPU time 765.9 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 06:01:42 PM PDT 24
Peak memory 207196 kb
Host smart-af0ff9c4-bd12-4804-9f07-0697245348fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031086181 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1031086181
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3125039682
Short name T119
Test name
Test status
Simulation time 47987317171 ps
CPU time 8.41 seconds
Started Aug 07 05:49:08 PM PDT 24
Finished Aug 07 05:49:16 PM PDT 24
Peak memory 198528 kb
Host smart-640bdbba-18f2-4a12-8425-6875afb9ba9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125039682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3125039682
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2975583842
Short name T19
Test name
Test status
Simulation time 8488768374 ps
CPU time 11.13 seconds
Started Aug 07 05:48:13 PM PDT 24
Finished Aug 07 05:48:24 PM PDT 24
Peak memory 215828 kb
Host smart-b5f1f4d1-073b-4beb-8de2-c7e82e93bd78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975583842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2975583842
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3828828542
Short name T118
Test name
Test status
Simulation time 78399928782 ps
CPU time 841.8 seconds
Started Aug 07 05:48:21 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 215112 kb
Host smart-a2bdb509-ecb8-4cb0-ae6b-1b43236bbca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828828542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3828828542
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3876939934
Short name T41
Test name
Test status
Simulation time 28475421062 ps
CPU time 297.26 seconds
Started Aug 07 05:49:12 PM PDT 24
Finished Aug 07 05:54:09 PM PDT 24
Peak memory 206996 kb
Host smart-d728a530-27f8-4316-a870-30d74f35fafc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876939934 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3876939934
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1147332844
Short name T116
Test name
Test status
Simulation time 313365319850 ps
CPU time 735.02 seconds
Started Aug 07 05:49:31 PM PDT 24
Finished Aug 07 06:01:46 PM PDT 24
Peak memory 208012 kb
Host smart-8ca3805d-1c80-42dc-849c-8ca32a9c7513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147332844 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1147332844
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2308517155
Short name T152
Test name
Test status
Simulation time 51791637475 ps
CPU time 497.57 seconds
Started Aug 07 05:48:34 PM PDT 24
Finished Aug 07 05:56:52 PM PDT 24
Peak memory 202208 kb
Host smart-b151eb36-49e9-4e7f-90bd-4c46f5e9f410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308517155 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2308517155
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3841536338
Short name T1
Test name
Test status
Simulation time 378731343477 ps
CPU time 572.84 seconds
Started Aug 07 05:49:35 PM PDT 24
Finished Aug 07 05:59:08 PM PDT 24
Peak memory 193144 kb
Host smart-6a3969c6-603c-4f19-b38a-4f4236d43eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841536338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3841536338
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2424980153
Short name T29
Test name
Test status
Simulation time 126512351530 ps
CPU time 1283.4 seconds
Started Aug 07 05:49:26 PM PDT 24
Finished Aug 07 06:10:50 PM PDT 24
Peak memory 214672 kb
Host smart-748467b5-38af-4079-b3c0-267e156bf10f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424980153 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2424980153
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3340221406
Short name T143
Test name
Test status
Simulation time 14043115820 ps
CPU time 99.29 seconds
Started Aug 07 05:48:28 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 206848 kb
Host smart-2a9d5e1c-bc48-4634-b07a-73d4934e6511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340221406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3340221406
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.613552449
Short name T99
Test name
Test status
Simulation time 52695324377 ps
CPU time 202.17 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:52:19 PM PDT 24
Peak memory 198896 kb
Host smart-8b8b46d2-148f-4ee2-b8e8-da3f098b0933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613552449 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.613552449
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3846034378
Short name T98
Test name
Test status
Simulation time 91506097235 ps
CPU time 73.51 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:50:33 PM PDT 24
Peak memory 192164 kb
Host smart-b26c92ad-4b36-44b3-af4a-25c8878a02b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846034378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3846034378
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2686184086
Short name T133
Test name
Test status
Simulation time 254166995054 ps
CPU time 442.88 seconds
Started Aug 07 05:48:52 PM PDT 24
Finished Aug 07 05:56:15 PM PDT 24
Peak memory 215116 kb
Host smart-98b4015a-3702-4584-9168-f96b5d0f1afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686184086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2686184086
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1753118297
Short name T125
Test name
Test status
Simulation time 63318964231 ps
CPU time 505.42 seconds
Started Aug 07 05:49:05 PM PDT 24
Finished Aug 07 05:57:30 PM PDT 24
Peak memory 211092 kb
Host smart-9dd5efa7-90de-4502-9a95-574e817204a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753118297 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1753118297
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4120545131
Short name T106
Test name
Test status
Simulation time 82992762481 ps
CPU time 134.14 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 05:51:10 PM PDT 24
Peak memory 192148 kb
Host smart-87cfa4b4-9adb-43ed-b36a-ce04594830b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120545131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4120545131
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2354090893
Short name T86
Test name
Test status
Simulation time 142255099903 ps
CPU time 768.66 seconds
Started Aug 07 05:48:36 PM PDT 24
Finished Aug 07 06:01:25 PM PDT 24
Peak memory 215032 kb
Host smart-ac57ab9f-c526-4899-b0e6-01026d2ee59f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354090893 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2354090893
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1664185796
Short name T145
Test name
Test status
Simulation time 98049711321 ps
CPU time 254.8 seconds
Started Aug 07 05:48:41 PM PDT 24
Finished Aug 07 05:52:56 PM PDT 24
Peak memory 201360 kb
Host smart-45a54470-8423-4a5f-861f-4a7ab28a191e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664185796 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1664185796
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1143056962
Short name T156
Test name
Test status
Simulation time 108772263801 ps
CPU time 245.88 seconds
Started Aug 07 05:49:26 PM PDT 24
Finished Aug 07 05:53:32 PM PDT 24
Peak memory 214760 kb
Host smart-95536dd6-7172-489f-9cfe-32890b962069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143056962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1143056962
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3979980890
Short name T102
Test name
Test status
Simulation time 123170709601 ps
CPU time 124.06 seconds
Started Aug 07 05:49:31 PM PDT 24
Finished Aug 07 05:51:35 PM PDT 24
Peak memory 193220 kb
Host smart-fc8d7981-e435-4067-bfc9-bcd6d2f51410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979980890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3979980890
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2049223533
Short name T18
Test name
Test status
Simulation time 418118343832 ps
CPU time 511.16 seconds
Started Aug 07 05:49:26 PM PDT 24
Finished Aug 07 05:57:57 PM PDT 24
Peak memory 198440 kb
Host smart-c5c89fe6-9790-47b5-a743-c30f702e895b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049223533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2049223533
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2339683449
Short name T108
Test name
Test status
Simulation time 192833751575 ps
CPU time 72.25 seconds
Started Aug 07 05:49:27 PM PDT 24
Finished Aug 07 05:50:39 PM PDT 24
Peak memory 198560 kb
Host smart-113eec79-725f-4d52-9a4d-a4e98de9abcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339683449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2339683449
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2056784093
Short name T147
Test name
Test status
Simulation time 193463192000 ps
CPU time 51.27 seconds
Started Aug 07 05:48:40 PM PDT 24
Finished Aug 07 05:49:31 PM PDT 24
Peak memory 193192 kb
Host smart-6e760183-d4c5-44bd-94ba-a8530cb77407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056784093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2056784093
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.493642789
Short name T94
Test name
Test status
Simulation time 28085078509 ps
CPU time 210.17 seconds
Started Aug 07 05:49:32 PM PDT 24
Finished Aug 07 05:53:02 PM PDT 24
Peak memory 198740 kb
Host smart-66fe2197-cf17-4611-ae77-5f1daf513bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493642789 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.493642789
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2372576745
Short name T93
Test name
Test status
Simulation time 183179611815 ps
CPU time 355.91 seconds
Started Aug 07 05:49:00 PM PDT 24
Finished Aug 07 05:54:56 PM PDT 24
Peak memory 202032 kb
Host smart-efc06705-8b85-4710-9a75-a3727b85ffd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372576745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2372576745
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2058859395
Short name T137
Test name
Test status
Simulation time 84238899962 ps
CPU time 32.73 seconds
Started Aug 07 05:49:17 PM PDT 24
Finished Aug 07 05:49:50 PM PDT 24
Peak memory 193268 kb
Host smart-2d3603ed-5c15-463c-bb37-eb8d0fb0cd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058859395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2058859395
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2480913432
Short name T43
Test name
Test status
Simulation time 127696884511 ps
CPU time 205.06 seconds
Started Aug 07 05:49:34 PM PDT 24
Finished Aug 07 05:52:59 PM PDT 24
Peak memory 200304 kb
Host smart-4814472e-2832-41bc-a91d-cfc248daa34d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480913432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2480913432
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4102997520
Short name T120
Test name
Test status
Simulation time 177721923099 ps
CPU time 124.69 seconds
Started Aug 07 05:48:34 PM PDT 24
Finished Aug 07 05:50:39 PM PDT 24
Peak memory 192156 kb
Host smart-fcfa980d-242a-4df2-ad2d-6b5c5be91ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102997520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4102997520
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1162701085
Short name T66
Test name
Test status
Simulation time 71575653961 ps
CPU time 89.4 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:50:50 PM PDT 24
Peak memory 184908 kb
Host smart-44447bc0-027f-440b-aae7-02d61dc701cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162701085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1162701085
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2994203028
Short name T42
Test name
Test status
Simulation time 55749614200 ps
CPU time 202.02 seconds
Started Aug 07 05:48:29 PM PDT 24
Finished Aug 07 05:51:51 PM PDT 24
Peak memory 206900 kb
Host smart-393c7da8-aa14-4c6f-b904-fc45889f6e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994203028 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2994203028
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2278217816
Short name T139
Test name
Test status
Simulation time 39035230286 ps
CPU time 50.89 seconds
Started Aug 07 05:48:36 PM PDT 24
Finished Aug 07 05:49:27 PM PDT 24
Peak memory 193152 kb
Host smart-cd065dc7-df49-4154-9fa8-798ee64e7aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278217816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2278217816
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3019020687
Short name T136
Test name
Test status
Simulation time 100645316913 ps
CPU time 48.19 seconds
Started Aug 07 05:48:20 PM PDT 24
Finished Aug 07 05:49:08 PM PDT 24
Peak memory 193244 kb
Host smart-ddab25f0-ad6e-4237-a583-033630c50991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019020687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3019020687
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3049445605
Short name T115
Test name
Test status
Simulation time 350568796903 ps
CPU time 228.89 seconds
Started Aug 07 05:49:01 PM PDT 24
Finished Aug 07 05:52:50 PM PDT 24
Peak memory 193252 kb
Host smart-2229a663-87c9-4d49-96c1-d7119bb82e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049445605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3049445605
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.483863112
Short name T87
Test name
Test status
Simulation time 52432559828 ps
CPU time 430.09 seconds
Started Aug 07 05:48:44 PM PDT 24
Finished Aug 07 05:55:54 PM PDT 24
Peak memory 214180 kb
Host smart-68f62823-5109-4950-b615-fb09dbe21a43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483863112 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.483863112
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3297605210
Short name T135
Test name
Test status
Simulation time 24998642060 ps
CPU time 250.81 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:53:31 PM PDT 24
Peak memory 198788 kb
Host smart-64ce3d96-e1f3-4ab7-95cc-ae68ca54eb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297605210 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3297605210
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3043154858
Short name T49
Test name
Test status
Simulation time 143169324678 ps
CPU time 190.36 seconds
Started Aug 07 05:49:31 PM PDT 24
Finished Aug 07 05:52:42 PM PDT 24
Peak memory 193108 kb
Host smart-94134b7e-81e8-4daf-9063-32117d3e44b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043154858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3043154858
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.382648109
Short name T157
Test name
Test status
Simulation time 67874835247 ps
CPU time 491.97 seconds
Started Aug 07 05:49:33 PM PDT 24
Finished Aug 07 05:57:45 PM PDT 24
Peak memory 202252 kb
Host smart-4460c837-1d60-4549-acc5-3d1a8941ea56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382648109 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.382648109
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.231564696
Short name T44
Test name
Test status
Simulation time 10688972219 ps
CPU time 78.55 seconds
Started Aug 07 05:48:52 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 214216 kb
Host smart-40e76e47-a056-4726-9171-7def747f6978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231564696 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.231564696
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1570504246
Short name T148
Test name
Test status
Simulation time 153205099631 ps
CPU time 356.91 seconds
Started Aug 07 05:49:01 PM PDT 24
Finished Aug 07 05:54:58 PM PDT 24
Peak memory 210492 kb
Host smart-1ac2491a-1820-4aae-8434-f7dd1eda9e7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570504246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1570504246
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.716687161
Short name T128
Test name
Test status
Simulation time 273757318701 ps
CPU time 86.24 seconds
Started Aug 07 05:49:10 PM PDT 24
Finished Aug 07 05:50:36 PM PDT 24
Peak memory 192820 kb
Host smart-28a880fc-a192-4ef9-a979-d1b30ff4b7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716687161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.716687161
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.905775979
Short name T127
Test name
Test status
Simulation time 143563261455 ps
CPU time 51.77 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:50:14 PM PDT 24
Peak memory 193276 kb
Host smart-0aa5e4f2-7434-4e8b-97e3-3b32a60606c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905775979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.905775979
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2994615453
Short name T169
Test name
Test status
Simulation time 27103407149 ps
CPU time 283.85 seconds
Started Aug 07 05:48:17 PM PDT 24
Finished Aug 07 05:53:01 PM PDT 24
Peak memory 198732 kb
Host smart-d0d23b78-bb0e-4872-a204-ca49fee18628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994615453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2994615453
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2938599731
Short name T67
Test name
Test status
Simulation time 76052093065 ps
CPU time 105.64 seconds
Started Aug 07 05:48:38 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 184756 kb
Host smart-6d038f1f-2369-481c-913a-10eb37515deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938599731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2938599731
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1479727489
Short name T16
Test name
Test status
Simulation time 115550602788 ps
CPU time 159.21 seconds
Started Aug 07 05:48:36 PM PDT 24
Finished Aug 07 05:51:16 PM PDT 24
Peak memory 192880 kb
Host smart-6a4ba35a-35ad-4612-8624-2b307b4f3192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479727489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1479727489
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1446450849
Short name T155
Test name
Test status
Simulation time 326534984779 ps
CPU time 413.29 seconds
Started Aug 07 05:48:37 PM PDT 24
Finished Aug 07 05:55:30 PM PDT 24
Peak memory 192124 kb
Host smart-d5d68e9b-9d60-4f84-9979-df00ca304e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446450849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1446450849
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3692329318
Short name T52
Test name
Test status
Simulation time 2474514280 ps
CPU time 3.43 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 05:49:40 PM PDT 24
Peak memory 192280 kb
Host smart-5be993d1-6683-4df8-8159-a9e9310feaad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692329318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3692329318
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3239605456
Short name T84
Test name
Test status
Simulation time 2269037647 ps
CPU time 1.76 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 195416 kb
Host smart-14520748-5640-467e-9af7-6daf552fef28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239605456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3239605456
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3757220677
Short name T97
Test name
Test status
Simulation time 4704805793 ps
CPU time 1.94 seconds
Started Aug 07 05:49:05 PM PDT 24
Finished Aug 07 05:49:07 PM PDT 24
Peak memory 192152 kb
Host smart-a8024afe-ac3a-4872-b1b3-e7a5a8e739f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757220677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3757220677
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.4092411780
Short name T167
Test name
Test status
Simulation time 59463207333 ps
CPU time 151.93 seconds
Started Aug 07 05:48:23 PM PDT 24
Finished Aug 07 05:50:55 PM PDT 24
Peak memory 198772 kb
Host smart-0d5f9198-83be-4e86-90ad-8cbff9f5506f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092411780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.4092411780
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.295866209
Short name T107
Test name
Test status
Simulation time 211023270183 ps
CPU time 174.33 seconds
Started Aug 07 05:48:16 PM PDT 24
Finished Aug 07 05:51:11 PM PDT 24
Peak memory 193224 kb
Host smart-5532fda5-995e-4c02-939f-aef16119e2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295866209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.295866209
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1202542391
Short name T90
Test name
Test status
Simulation time 45206106642 ps
CPU time 213.83 seconds
Started Aug 07 05:48:51 PM PDT 24
Finished Aug 07 05:52:25 PM PDT 24
Peak memory 206928 kb
Host smart-6d5935b7-ac9b-4b1f-9aea-3c8c5169faac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202542391 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1202542391
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2392041627
Short name T130
Test name
Test status
Simulation time 189144483463 ps
CPU time 271.15 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 05:53:27 PM PDT 24
Peak memory 198384 kb
Host smart-26990218-47db-4128-9e5e-7a85be6d7152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392041627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2392041627
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4208154831
Short name T160
Test name
Test status
Simulation time 892964189892 ps
CPU time 540.15 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:58:21 PM PDT 24
Peak memory 212652 kb
Host smart-f5964d8c-61ef-4fda-9306-e6fba1201c40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208154831 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4208154831
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.286814401
Short name T6
Test name
Test status
Simulation time 52552106734 ps
CPU time 413.93 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:56:14 PM PDT 24
Peak memory 215344 kb
Host smart-46fd1bf6-cae3-4b3e-831b-18b134f350f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286814401 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.286814401
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.717151542
Short name T31
Test name
Test status
Simulation time 40965111352 ps
CPU time 231.75 seconds
Started Aug 07 05:49:08 PM PDT 24
Finished Aug 07 05:53:00 PM PDT 24
Peak memory 214212 kb
Host smart-0f64b1b8-4d11-433e-abbb-acaafde63633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717151542 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.717151542
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1429230988
Short name T89
Test name
Test status
Simulation time 75895243145 ps
CPU time 426.46 seconds
Started Aug 07 05:49:12 PM PDT 24
Finished Aug 07 05:56:19 PM PDT 24
Peak memory 206924 kb
Host smart-34ea4c57-53ff-4ded-a93e-2ce9d22cb8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429230988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1429230988
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.537187747
Short name T105
Test name
Test status
Simulation time 53810602964 ps
CPU time 367.09 seconds
Started Aug 07 05:48:43 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 207816 kb
Host smart-5d28867f-8f6c-472c-97fa-de6e686829c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537187747 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.537187747
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1120462418
Short name T166
Test name
Test status
Simulation time 538924411602 ps
CPU time 213.44 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:52:29 PM PDT 24
Peak memory 192060 kb
Host smart-64031171-a7d2-4b88-8e54-543732eff1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120462418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1120462418
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3827922165
Short name T96
Test name
Test status
Simulation time 210079183679 ps
CPU time 370.21 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:55:06 PM PDT 24
Peak memory 210368 kb
Host smart-afafbe0e-9556-4bf0-9f33-44fa9c6138fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827922165 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3827922165
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1540768232
Short name T122
Test name
Test status
Simulation time 26223088889 ps
CPU time 190.03 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:52:07 PM PDT 24
Peak memory 206940 kb
Host smart-f5a30dc1-5e5c-45f4-83b1-def1789ca1d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540768232 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1540768232
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.204570226
Short name T126
Test name
Test status
Simulation time 610607384 ps
CPU time 0.83 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:48:56 PM PDT 24
Peak memory 196948 kb
Host smart-548609fb-0fd3-461f-bfbf-4bd82b04c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204570226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.204570226
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1194494382
Short name T131
Test name
Test status
Simulation time 346711274 ps
CPU time 1.14 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:49:21 PM PDT 24
Peak memory 196928 kb
Host smart-66b6e6e4-971a-44ba-87db-ec3175a16862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194494382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1194494382
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.252934619
Short name T100
Test name
Test status
Simulation time 487583722 ps
CPU time 1.31 seconds
Started Aug 07 05:49:30 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 196788 kb
Host smart-21522709-8bec-4b1f-bfcc-594b0625e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252934619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.252934619
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1375132656
Short name T146
Test name
Test status
Simulation time 90750420470 ps
CPU time 529.44 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:57:44 PM PDT 24
Peak memory 212424 kb
Host smart-8e075c84-f70c-4716-b243-646062e49694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375132656 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1375132656
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.786567802
Short name T63
Test name
Test status
Simulation time 466748266 ps
CPU time 0.74 seconds
Started Aug 07 05:48:22 PM PDT 24
Finished Aug 07 05:48:23 PM PDT 24
Peak memory 196912 kb
Host smart-8bcbdad5-9273-4766-9308-82e6e314709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786567802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.786567802
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3483834029
Short name T141
Test name
Test status
Simulation time 106068707187 ps
CPU time 125.94 seconds
Started Aug 07 05:49:09 PM PDT 24
Finished Aug 07 05:51:15 PM PDT 24
Peak memory 198376 kb
Host smart-61de55db-c081-4a7a-a5c9-5ad7cc8d4a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483834029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3483834029
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4113386121
Short name T110
Test name
Test status
Simulation time 517120232 ps
CPU time 1.26 seconds
Started Aug 07 05:49:16 PM PDT 24
Finished Aug 07 05:49:17 PM PDT 24
Peak memory 196896 kb
Host smart-91691235-ce98-4c96-b3fd-378428596e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113386121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4113386121
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3812554246
Short name T123
Test name
Test status
Simulation time 322998949874 ps
CPU time 50.3 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 192752 kb
Host smart-8487aadd-7313-4800-83aa-7e0a361b9239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812554246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3812554246
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.254406433
Short name T51
Test name
Test status
Simulation time 137447959571 ps
CPU time 934.57 seconds
Started Aug 07 05:48:25 PM PDT 24
Finished Aug 07 06:04:00 PM PDT 24
Peak memory 215104 kb
Host smart-7d761fd0-4eb4-4889-ad3d-c2e078ea8662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254406433 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.254406433
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2148479313
Short name T113
Test name
Test status
Simulation time 596120647 ps
CPU time 0.66 seconds
Started Aug 07 05:48:26 PM PDT 24
Finished Aug 07 05:48:26 PM PDT 24
Peak memory 196892 kb
Host smart-d26001c9-fe07-4a4b-b8b1-4814899ef38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148479313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2148479313
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2470792026
Short name T132
Test name
Test status
Simulation time 220086570306 ps
CPU time 70.71 seconds
Started Aug 07 05:48:24 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 192856 kb
Host smart-8c2cc4c7-f356-41bb-a20d-c8a1d5fe60b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470792026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2470792026
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2818744434
Short name T184
Test name
Test status
Simulation time 32675911155 ps
CPU time 43.27 seconds
Started Aug 07 05:48:51 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 198532 kb
Host smart-3251d920-b5dc-4174-9bd8-52ddaa0fcb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818744434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2818744434
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1863918256
Short name T144
Test name
Test status
Simulation time 490327542 ps
CPU time 1.32 seconds
Started Aug 07 05:49:03 PM PDT 24
Finished Aug 07 05:49:05 PM PDT 24
Peak memory 196924 kb
Host smart-f5ce8388-c62d-483b-a7e1-2a0bc62b90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863918256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1863918256
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2188828181
Short name T170
Test name
Test status
Simulation time 634375091737 ps
CPU time 875.05 seconds
Started Aug 07 05:49:11 PM PDT 24
Finished Aug 07 06:03:47 PM PDT 24
Peak memory 193324 kb
Host smart-b3fe3cff-4fa3-41ae-acc6-e8a3fb888e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188828181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2188828181
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1678889012
Short name T149
Test name
Test status
Simulation time 523232439 ps
CPU time 1.07 seconds
Started Aug 07 05:49:17 PM PDT 24
Finished Aug 07 05:49:19 PM PDT 24
Peak memory 196884 kb
Host smart-d29d248d-8a7f-4673-acd2-183bf62b033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678889012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1678889012
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.960608470
Short name T176
Test name
Test status
Simulation time 243273377664 ps
CPU time 377.62 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:55:37 PM PDT 24
Peak memory 193144 kb
Host smart-062ad679-6eff-4f35-902c-bff130733528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960608470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.960608470
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.858362560
Short name T17
Test name
Test status
Simulation time 102826717955 ps
CPU time 84.96 seconds
Started Aug 07 05:49:29 PM PDT 24
Finished Aug 07 05:50:54 PM PDT 24
Peak memory 192164 kb
Host smart-27765ffa-36ec-41f2-bcde-99cca3c00e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858362560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.858362560
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2068459846
Short name T109
Test name
Test status
Simulation time 414565877 ps
CPU time 1.17 seconds
Started Aug 07 05:49:32 PM PDT 24
Finished Aug 07 05:49:33 PM PDT 24
Peak memory 196976 kb
Host smart-d6a3b0c2-2039-4755-ba06-2be8e666c2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068459846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2068459846
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2235841570
Short name T142
Test name
Test status
Simulation time 369932035 ps
CPU time 1.11 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:48:40 PM PDT 24
Peak memory 196956 kb
Host smart-930f42e3-ceee-4f0f-aa56-d0c2c0a0498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235841570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2235841570
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.185866784
Short name T151
Test name
Test status
Simulation time 125063601306 ps
CPU time 62.64 seconds
Started Aug 07 05:48:46 PM PDT 24
Finished Aug 07 05:49:48 PM PDT 24
Peak memory 192928 kb
Host smart-c654df9c-499c-49fc-80e2-31a4464bdd78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185866784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.185866784
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.288939811
Short name T124
Test name
Test status
Simulation time 583567224 ps
CPU time 1.54 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 196932 kb
Host smart-709831af-92be-40cd-8bba-851d03676569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288939811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.288939811
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.319408035
Short name T117
Test name
Test status
Simulation time 491798454 ps
CPU time 0.8 seconds
Started Aug 07 05:48:58 PM PDT 24
Finished Aug 07 05:48:59 PM PDT 24
Peak memory 196872 kb
Host smart-6d623e0b-7aac-474c-a37e-1f1592339ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319408035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.319408035
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.480463400
Short name T150
Test name
Test status
Simulation time 169103071002 ps
CPU time 113.96 seconds
Started Aug 07 05:49:25 PM PDT 24
Finished Aug 07 05:51:20 PM PDT 24
Peak memory 193256 kb
Host smart-1be8a3a9-de8c-4406-a6cf-200fb12b34c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480463400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.480463400
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3429954850
Short name T4
Test name
Test status
Simulation time 438911497 ps
CPU time 0.96 seconds
Started Aug 07 05:49:33 PM PDT 24
Finished Aug 07 05:49:34 PM PDT 24
Peak memory 197208 kb
Host smart-345ccc96-14c9-45d8-9073-812328e4bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429954850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3429954850
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3410203634
Short name T134
Test name
Test status
Simulation time 382031270 ps
CPU time 0.7 seconds
Started Aug 07 05:49:30 PM PDT 24
Finished Aug 07 05:49:31 PM PDT 24
Peak memory 196944 kb
Host smart-804d5166-9a59-4129-adb4-5f1d3ab3684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410203634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3410203634
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2727149559
Short name T129
Test name
Test status
Simulation time 533243446 ps
CPU time 0.66 seconds
Started Aug 07 05:48:17 PM PDT 24
Finished Aug 07 05:48:18 PM PDT 24
Peak memory 196820 kb
Host smart-c5280ac8-c2ed-4e5b-a82d-867c4b775ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727149559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2727149559
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3036715749
Short name T11
Test name
Test status
Simulation time 456575015 ps
CPU time 0.73 seconds
Started Aug 07 05:48:52 PM PDT 24
Finished Aug 07 05:48:53 PM PDT 24
Peak memory 196928 kb
Host smart-8d342fae-171e-41ea-b018-f953f056b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036715749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3036715749
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.823829504
Short name T21
Test name
Test status
Simulation time 15522881618 ps
CPU time 122.82 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:51:21 PM PDT 24
Peak memory 214360 kb
Host smart-232d4949-29f6-4638-86f4-f34e18ba2dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823829504 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.823829504
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3950854484
Short name T164
Test name
Test status
Simulation time 126750039535 ps
CPU time 48.48 seconds
Started Aug 07 05:48:26 PM PDT 24
Finished Aug 07 05:49:14 PM PDT 24
Peak memory 193236 kb
Host smart-88306b07-de21-40e2-b255-6316deef29e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950854484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3950854484
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.150536058
Short name T186
Test name
Test status
Simulation time 17849353187 ps
CPU time 189.66 seconds
Started Aug 07 05:48:23 PM PDT 24
Finished Aug 07 05:51:33 PM PDT 24
Peak memory 206928 kb
Host smart-b2b24974-6f46-4dd9-ad0e-036557ad45ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150536058 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.150536058
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.468016513
Short name T60
Test name
Test status
Simulation time 383962375 ps
CPU time 0.92 seconds
Started Aug 07 05:48:34 PM PDT 24
Finished Aug 07 05:48:35 PM PDT 24
Peak memory 196908 kb
Host smart-80ff1731-dbf2-4108-be78-6cd8c752589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468016513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.468016513
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3199955087
Short name T159
Test name
Test status
Simulation time 84305147204 ps
CPU time 31.72 seconds
Started Aug 07 05:48:21 PM PDT 24
Finished Aug 07 05:48:53 PM PDT 24
Peak memory 198448 kb
Host smart-bfcdd5cb-2303-4c18-ba4a-208f7b2822b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199955087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3199955087
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1232226574
Short name T104
Test name
Test status
Simulation time 109011099485 ps
CPU time 152.05 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:51:12 PM PDT 24
Peak memory 192876 kb
Host smart-2e3c2aee-4210-4c06-8690-4de7b20dd5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232226574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1232226574
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.157160840
Short name T153
Test name
Test status
Simulation time 575670194 ps
CPU time 1.29 seconds
Started Aug 07 05:48:37 PM PDT 24
Finished Aug 07 05:48:39 PM PDT 24
Peak memory 196796 kb
Host smart-3d4eba15-d24c-4b8f-973c-8f6e4c83742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157160840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.157160840
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2115851600
Short name T175
Test name
Test status
Simulation time 408475147 ps
CPU time 0.87 seconds
Started Aug 07 05:48:18 PM PDT 24
Finished Aug 07 05:48:19 PM PDT 24
Peak memory 196864 kb
Host smart-108a9a31-43d3-4ac6-ac80-a46ffd32ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115851600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2115851600
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2120377561
Short name T138
Test name
Test status
Simulation time 573288910 ps
CPU time 0.66 seconds
Started Aug 07 05:48:49 PM PDT 24
Finished Aug 07 05:48:50 PM PDT 24
Peak memory 196852 kb
Host smart-3e6dedc5-0325-40ed-a012-1772813d9ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120377561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2120377561
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3588665627
Short name T168
Test name
Test status
Simulation time 121962325278 ps
CPU time 195.81 seconds
Started Aug 07 05:48:59 PM PDT 24
Finished Aug 07 05:52:15 PM PDT 24
Peak memory 184420 kb
Host smart-57295666-a66d-489c-94c8-88beae744d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588665627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3588665627
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.432071725
Short name T171
Test name
Test status
Simulation time 533555802 ps
CPU time 0.71 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 05:48:57 PM PDT 24
Peak memory 196852 kb
Host smart-cb2bbac5-870a-45ec-a3a3-9b06a4d53c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432071725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.432071725
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.411763275
Short name T193
Test name
Test status
Simulation time 447810874 ps
CPU time 0.73 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 05:48:57 PM PDT 24
Peak memory 196952 kb
Host smart-10019696-662d-45f6-b1cc-fffd79ecfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411763275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.411763275
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4170453744
Short name T121
Test name
Test status
Simulation time 463254264 ps
CPU time 1.3 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:48:59 PM PDT 24
Peak memory 196908 kb
Host smart-867dffee-0257-4212-adc3-40cbcb086884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170453744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4170453744
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3307833947
Short name T189
Test name
Test status
Simulation time 389385552 ps
CPU time 0.88 seconds
Started Aug 07 05:49:06 PM PDT 24
Finished Aug 07 05:49:07 PM PDT 24
Peak memory 196848 kb
Host smart-2f411ff8-4493-488b-b1f7-c974dbf38f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307833947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3307833947
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1063466478
Short name T7
Test name
Test status
Simulation time 431594696 ps
CPU time 0.66 seconds
Started Aug 07 05:49:26 PM PDT 24
Finished Aug 07 05:49:27 PM PDT 24
Peak memory 196940 kb
Host smart-5d31d95c-d78e-4d8b-b2be-a8c55c073338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063466478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1063466478
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2154628744
Short name T111
Test name
Test status
Simulation time 59133711448 ps
CPU time 42.32 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 192156 kb
Host smart-8273208f-63f0-46b0-a479-83ff83cf3dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154628744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2154628744
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3503005099
Short name T174
Test name
Test status
Simulation time 160922039367 ps
CPU time 226.12 seconds
Started Aug 07 05:49:37 PM PDT 24
Finished Aug 07 05:53:23 PM PDT 24
Peak memory 198492 kb
Host smart-70fce55c-6e5e-479e-a569-8cc4971164b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503005099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3503005099
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2529507301
Short name T173
Test name
Test status
Simulation time 516603991 ps
CPU time 1.39 seconds
Started Aug 07 05:48:26 PM PDT 24
Finished Aug 07 05:48:27 PM PDT 24
Peak memory 196824 kb
Host smart-46f5a4f3-ffa9-45df-b2d9-e0c8992f6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529507301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2529507301
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3327423107
Short name T199
Test name
Test status
Simulation time 8362786053 ps
CPU time 5 seconds
Started Aug 07 05:50:00 PM PDT 24
Finished Aug 07 05:50:05 PM PDT 24
Peak memory 198244 kb
Host smart-c876da29-2ffa-4a15-85ac-c3f6ee20eadc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327423107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3327423107
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.104509995
Short name T165
Test name
Test status
Simulation time 36360205692 ps
CPU time 413.49 seconds
Started Aug 07 05:48:36 PM PDT 24
Finished Aug 07 05:55:30 PM PDT 24
Peak memory 208120 kb
Host smart-6402dcbb-1e41-4f0e-b25e-f7b0b8cc9852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104509995 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.104509995
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1761994544
Short name T182
Test name
Test status
Simulation time 169060370225 ps
CPU time 50.6 seconds
Started Aug 07 05:48:37 PM PDT 24
Finished Aug 07 05:49:28 PM PDT 24
Peak memory 198560 kb
Host smart-969f97e2-8e62-4873-a96c-3833d10d487f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761994544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1761994544
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2849516367
Short name T101
Test name
Test status
Simulation time 450198105 ps
CPU time 1.1 seconds
Started Aug 07 05:48:41 PM PDT 24
Finished Aug 07 05:48:42 PM PDT 24
Peak memory 196976 kb
Host smart-448db833-2092-4bb0-aa67-258b8801d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849516367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2849516367
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3052562302
Short name T181
Test name
Test status
Simulation time 375278067 ps
CPU time 0.9 seconds
Started Aug 07 05:49:42 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 196816 kb
Host smart-d7394093-b71c-4c54-b59a-f0197e3b30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052562302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3052562302
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2712639588
Short name T178
Test name
Test status
Simulation time 621456231 ps
CPU time 0.78 seconds
Started Aug 07 05:49:44 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 196836 kb
Host smart-42e116db-249c-480c-8a2e-c16b44d6818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712639588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2712639588
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.25737074
Short name T177
Test name
Test status
Simulation time 484775384 ps
CPU time 0.87 seconds
Started Aug 07 05:48:30 PM PDT 24
Finished Aug 07 05:48:31 PM PDT 24
Peak memory 196912 kb
Host smart-75539f1a-619a-4be3-8d99-c3495a3df780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25737074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.25737074
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3540418144
Short name T2
Test name
Test status
Simulation time 41212218419 ps
CPU time 96 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:50:56 PM PDT 24
Peak memory 206908 kb
Host smart-e1fad534-4f41-4b41-adb8-a3954fe92da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540418144 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3540418144
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4252542230
Short name T179
Test name
Test status
Simulation time 388065945 ps
CPU time 1.11 seconds
Started Aug 07 05:49:25 PM PDT 24
Finished Aug 07 05:49:27 PM PDT 24
Peak memory 196904 kb
Host smart-0db769ff-0cae-4bd8-a47b-01f6fc7f13e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252542230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4252542230
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1948156741
Short name T161
Test name
Test status
Simulation time 340889418 ps
CPU time 1.12 seconds
Started Aug 07 05:49:28 PM PDT 24
Finished Aug 07 05:49:29 PM PDT 24
Peak memory 196880 kb
Host smart-bb7d8d13-a0e8-42fb-846d-e1a1844d5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948156741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1948156741
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3765705559
Short name T162
Test name
Test status
Simulation time 351989380 ps
CPU time 1.13 seconds
Started Aug 07 05:49:29 PM PDT 24
Finished Aug 07 05:49:30 PM PDT 24
Peak memory 196848 kb
Host smart-4d50db2c-d6f6-4d87-a4d5-8ffc5fd61f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765705559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3765705559
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2106505902
Short name T172
Test name
Test status
Simulation time 350680069 ps
CPU time 0.93 seconds
Started Aug 07 05:48:35 PM PDT 24
Finished Aug 07 05:48:36 PM PDT 24
Peak memory 196892 kb
Host smart-01efd099-70ff-4b41-bc4d-ba2cc788adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106505902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2106505902
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3292677670
Short name T158
Test name
Test status
Simulation time 368577059 ps
CPU time 1.09 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 197060 kb
Host smart-8c548ce0-bec4-4b09-9dbf-c61aa62bdcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292677670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3292677670
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.339030427
Short name T188
Test name
Test status
Simulation time 387291435 ps
CPU time 0.95 seconds
Started Aug 07 05:48:42 PM PDT 24
Finished Aug 07 05:48:43 PM PDT 24
Peak memory 196948 kb
Host smart-2dff5c8b-49f5-4c9b-8f3f-ca49f1e2bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339030427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.339030427
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2236033159
Short name T112
Test name
Test status
Simulation time 340422957 ps
CPU time 1.08 seconds
Started Aug 07 05:48:54 PM PDT 24
Finished Aug 07 05:48:55 PM PDT 24
Peak memory 196880 kb
Host smart-5afea245-c89d-4e81-a91c-8a13908171d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236033159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2236033159
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2563555374
Short name T190
Test name
Test status
Simulation time 600429219 ps
CPU time 1.38 seconds
Started Aug 07 05:49:02 PM PDT 24
Finished Aug 07 05:49:03 PM PDT 24
Peak memory 196932 kb
Host smart-4448fe63-ec58-4067-b954-30d16feb157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563555374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2563555374
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4001198081
Short name T185
Test name
Test status
Simulation time 130944842361 ps
CPU time 15.87 seconds
Started Aug 07 05:49:01 PM PDT 24
Finished Aug 07 05:49:16 PM PDT 24
Peak memory 192084 kb
Host smart-0cf471f2-ccee-4a33-bd31-2df5e3ab5e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001198081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4001198081
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1327145653
Short name T33
Test name
Test status
Simulation time 375002162 ps
CPU time 0.71 seconds
Started Aug 07 05:49:08 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 196904 kb
Host smart-87b43e74-813d-41f8-acc6-dbdfbf3028d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327145653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1327145653
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1026591402
Short name T91
Test name
Test status
Simulation time 513789058 ps
CPU time 0.62 seconds
Started Aug 07 05:49:10 PM PDT 24
Finished Aug 07 05:49:11 PM PDT 24
Peak memory 196836 kb
Host smart-d8c598d9-0897-4a69-ab5a-1e16453c44ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026591402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1026591402
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1391109836
Short name T195
Test name
Test status
Simulation time 556875847 ps
CPU time 1.38 seconds
Started Aug 07 05:49:17 PM PDT 24
Finished Aug 07 05:49:18 PM PDT 24
Peak memory 196956 kb
Host smart-80139cf3-b336-4784-9e10-044fd95637b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391109836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1391109836
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4158900939
Short name T192
Test name
Test status
Simulation time 591964990 ps
CPU time 0.94 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 196896 kb
Host smart-e3e064bc-f007-4ef7-839c-a7f566423d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158900939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4158900939
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3841547993
Short name T140
Test name
Test status
Simulation time 544194930 ps
CPU time 1.42 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 196876 kb
Host smart-61ee733f-1119-4f72-9e03-313784f9c725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841547993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3841547993
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.396966501
Short name T95
Test name
Test status
Simulation time 4967065459 ps
CPU time 32.6 seconds
Started Aug 07 05:49:25 PM PDT 24
Finished Aug 07 05:49:58 PM PDT 24
Peak memory 206952 kb
Host smart-fe455fc2-c089-4ba9-865e-cecbb8a23850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396966501 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.396966501
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4205942659
Short name T163
Test name
Test status
Simulation time 516379780 ps
CPU time 0.95 seconds
Started Aug 07 05:48:30 PM PDT 24
Finished Aug 07 05:48:31 PM PDT 24
Peak memory 196992 kb
Host smart-58898c22-ed47-4b21-b9e1-d68491aa041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205942659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4205942659
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.508394204
Short name T76
Test name
Test status
Simulation time 569455717 ps
CPU time 1.46 seconds
Started Aug 07 05:49:38 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 193212 kb
Host smart-aa70c117-7e3d-4b87-adb7-55ce2f305a50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508394204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.508394204
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4018373806
Short name T300
Test name
Test status
Simulation time 1093422967 ps
CPU time 2.27 seconds
Started Aug 07 05:49:37 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 193020 kb
Host smart-934bcde9-e209-4acf-bca3-b6f5c9b5b103
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018373806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4018373806
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2738180005
Short name T346
Test name
Test status
Simulation time 457315490 ps
CPU time 1.07 seconds
Started Aug 07 05:49:40 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 198416 kb
Host smart-e9c03436-2740-4590-b91c-eec9d7753d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738180005 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2738180005
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1639262011
Short name T56
Test name
Test status
Simulation time 523254663 ps
CPU time 0.75 seconds
Started Aug 07 05:49:34 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 192908 kb
Host smart-a2c1466f-e5fd-4952-8a9d-fe7e661bf9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639262011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1639262011
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1510830441
Short name T293
Test name
Test status
Simulation time 293394675 ps
CPU time 0.66 seconds
Started Aug 07 05:49:35 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 192972 kb
Host smart-719ddb81-3262-473f-85c6-9f13c3599eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510830441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1510830441
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1966387531
Short name T420
Test name
Test status
Simulation time 447896409 ps
CPU time 0.56 seconds
Started Aug 07 05:49:34 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 183612 kb
Host smart-2fdd6c20-8610-418e-9a4c-3a82378e86da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966387531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1966387531
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2251971540
Short name T355
Test name
Test status
Simulation time 524430516 ps
CPU time 0.69 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 05:49:36 PM PDT 24
Peak memory 183668 kb
Host smart-cb9e5217-204a-424c-a29b-31680d831741
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251971540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2251971540
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1471012508
Short name T395
Test name
Test status
Simulation time 2517936301 ps
CPU time 4.18 seconds
Started Aug 07 05:49:42 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 195240 kb
Host smart-9222c488-e036-44dc-aa3d-707c98c97f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471012508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1471012508
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1852710722
Short name T414
Test name
Test status
Simulation time 2305719949 ps
CPU time 2.2 seconds
Started Aug 07 05:49:37 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 198948 kb
Host smart-9bd6a7db-7d6d-4a18-9b00-6ae5d248057c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852710722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1852710722
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2574882698
Short name T410
Test name
Test status
Simulation time 8816059240 ps
CPU time 4.28 seconds
Started Aug 07 05:49:34 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 198300 kb
Host smart-4e4dee2c-0c0c-464e-a5d2-44e44e0f1be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574882698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2574882698
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.906883652
Short name T332
Test name
Test status
Simulation time 767734192 ps
CPU time 1.1 seconds
Started Aug 07 05:49:39 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 183928 kb
Host smart-29d07c33-7179-4316-9e26-b7746e92930b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906883652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.906883652
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1006142677
Short name T73
Test name
Test status
Simulation time 7801006119 ps
CPU time 21.09 seconds
Started Aug 07 05:49:40 PM PDT 24
Finished Aug 07 05:50:02 PM PDT 24
Peak memory 192296 kb
Host smart-aca737d2-8ed2-4c43-ad6d-d9cf14132f43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006142677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1006142677
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1248839431
Short name T72
Test name
Test status
Simulation time 854214607 ps
CPU time 1.21 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 183756 kb
Host smart-3ae4bacd-5095-4ff6-908b-45a7353d9547
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248839431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1248839431
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1808921669
Short name T312
Test name
Test status
Simulation time 386163279 ps
CPU time 0.79 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 05:49:42 PM PDT 24
Peak memory 196264 kb
Host smart-deb56d31-9325-4f22-a74d-23473b343712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808921669 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1808921669
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3594553662
Short name T401
Test name
Test status
Simulation time 530016624 ps
CPU time 0.77 seconds
Started Aug 07 05:49:40 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 193188 kb
Host smart-21ecfe39-222b-4376-aaf3-130cafd2f7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594553662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3594553662
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.810875536
Short name T354
Test name
Test status
Simulation time 427143778 ps
CPU time 0.75 seconds
Started Aug 07 05:49:38 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 192984 kb
Host smart-d7a01f11-d02e-42f3-8bd4-edb5c3ffecc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810875536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.810875536
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4027357127
Short name T399
Test name
Test status
Simulation time 461406045 ps
CPU time 0.66 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:49:44 PM PDT 24
Peak memory 183732 kb
Host smart-9e365fbb-4d1a-4e6b-b99c-295a482b2c40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027357127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4027357127
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.364870468
Short name T397
Test name
Test status
Simulation time 437371889 ps
CPU time 1.22 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:49:44 PM PDT 24
Peak memory 183684 kb
Host smart-7ba6dd09-1ba1-4c82-8487-a449cc880107
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364870468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.364870468
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1132104239
Short name T411
Test name
Test status
Simulation time 2384590619 ps
CPU time 1.19 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 184124 kb
Host smart-7c6fa2e4-c98e-4c70-a238-dc982ca80767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132104239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1132104239
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.35475787
Short name T419
Test name
Test status
Simulation time 512217079 ps
CPU time 1.34 seconds
Started Aug 07 05:49:40 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 198636 kb
Host smart-d122c506-adbc-46c6-92d3-2b0186a7d584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.35475787
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2063855443
Short name T339
Test name
Test status
Simulation time 4094547879 ps
CPU time 6.07 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:49:49 PM PDT 24
Peak memory 198160 kb
Host smart-489398fd-515c-48fa-ab82-38fbf60578d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063855443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2063855443
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1581159770
Short name T418
Test name
Test status
Simulation time 429919478 ps
CPU time 1.22 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:05 PM PDT 24
Peak memory 196072 kb
Host smart-20780ec0-8a0e-4ffc-9157-1bf03c34af3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581159770 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1581159770
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3714248835
Short name T373
Test name
Test status
Simulation time 384279131 ps
CPU time 0.75 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 193200 kb
Host smart-7cc52063-72ef-429d-aa8a-4cb6d4a65a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714248835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3714248835
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2314784636
Short name T305
Test name
Test status
Simulation time 323645265 ps
CPU time 0.64 seconds
Started Aug 07 05:50:00 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 183784 kb
Host smart-b913273d-f419-4e8e-bc1c-876e5808f6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314784636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2314784636
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3255400763
Short name T327
Test name
Test status
Simulation time 1399947408 ps
CPU time 1.11 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 192984 kb
Host smart-f2454960-82b5-4b93-81ff-dc60205b9944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255400763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3255400763
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.664748630
Short name T422
Test name
Test status
Simulation time 458282921 ps
CPU time 1.72 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 198432 kb
Host smart-d7806ac7-da44-4e12-bfea-824159f9627a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664748630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.664748630
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3575626262
Short name T421
Test name
Test status
Simulation time 447754736 ps
CPU time 0.71 seconds
Started Aug 07 05:50:06 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 195676 kb
Host smart-d2d0811f-e3c6-4714-9a05-f0f37b3aa355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575626262 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3575626262
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1392646530
Short name T295
Test name
Test status
Simulation time 330884920 ps
CPU time 0.73 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 194044 kb
Host smart-bdca1b5b-24a0-4449-9875-cd9422b859b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392646530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1392646530
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.450707803
Short name T341
Test name
Test status
Simulation time 310267391 ps
CPU time 0.79 seconds
Started Aug 07 05:50:08 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 183756 kb
Host smart-7e02cbab-155f-43f1-a540-1f8970128d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450707803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.450707803
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.991708052
Short name T390
Test name
Test status
Simulation time 2107445642 ps
CPU time 4.73 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 193928 kb
Host smart-acd97feb-47cc-4cd7-a232-6438ae479dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991708052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.991708052
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.617429849
Short name T304
Test name
Test status
Simulation time 1253857038 ps
CPU time 2.1 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:02 PM PDT 24
Peak memory 198660 kb
Host smart-7b619282-342e-4b79-8f32-a65d6c8587f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617429849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.617429849
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1152319313
Short name T201
Test name
Test status
Simulation time 4103352648 ps
CPU time 2.41 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:05 PM PDT 24
Peak memory 197556 kb
Host smart-b21863da-becb-44d0-9f78-0aacf19c3619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152319313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1152319313
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1333098794
Short name T35
Test name
Test status
Simulation time 387439508 ps
CPU time 1.22 seconds
Started Aug 07 05:50:06 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 197852 kb
Host smart-c953b5ca-274d-4250-a984-ccb9de1c1a34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333098794 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1333098794
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2290331185
Short name T53
Test name
Test status
Simulation time 332344307 ps
CPU time 0.68 seconds
Started Aug 07 05:50:06 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 193240 kb
Host smart-281b719b-b60e-4d99-a8e8-1811b2dd0f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290331185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2290331185
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2555260854
Short name T325
Test name
Test status
Simulation time 403236596 ps
CPU time 0.67 seconds
Started Aug 07 05:50:06 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 193000 kb
Host smart-1919dd69-1b29-46a5-b56f-0d0f78a52281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555260854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2555260854
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2365460991
Short name T322
Test name
Test status
Simulation time 304832037 ps
CPU time 1.4 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 198560 kb
Host smart-ef02160a-04f8-4bd5-89d5-dcf918d20c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365460991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2365460991
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2582467248
Short name T316
Test name
Test status
Simulation time 4220779003 ps
CPU time 3.51 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:10 PM PDT 24
Peak memory 197700 kb
Host smart-963732b9-859a-4a2b-855d-6b50496d5bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582467248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2582467248
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.389120546
Short name T328
Test name
Test status
Simulation time 454961892 ps
CPU time 0.85 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 196856 kb
Host smart-34d99c86-7210-403b-90ab-83e2a1a811c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389120546 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.389120546
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1655689317
Short name T57
Test name
Test status
Simulation time 538836422 ps
CPU time 1.41 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 193996 kb
Host smart-ceb24bc9-643e-4f60-ab45-e2cc8ce3a793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655689317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1655689317
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.685462676
Short name T308
Test name
Test status
Simulation time 458594208 ps
CPU time 1.25 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 193004 kb
Host smart-e151531c-b022-4082-95a9-958dda1560c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685462676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.685462676
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1803965635
Short name T317
Test name
Test status
Simulation time 2515253437 ps
CPU time 1.4 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 193984 kb
Host smart-d38b557f-05e5-4b80-be60-d9d3931c3020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803965635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1803965635
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.425158134
Short name T352
Test name
Test status
Simulation time 417852733 ps
CPU time 1.74 seconds
Started Aug 07 05:50:06 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 198600 kb
Host smart-c936468f-a763-4e39-94c6-2d461ec08f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425158134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.425158134
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1151910212
Short name T330
Test name
Test status
Simulation time 7503598204 ps
CPU time 11.49 seconds
Started Aug 07 05:50:05 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 198336 kb
Host smart-0558ce1b-15f3-41f2-b304-3a8aa66e922b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151910212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1151910212
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2596584729
Short name T340
Test name
Test status
Simulation time 456463846 ps
CPU time 0.84 seconds
Started Aug 07 05:50:12 PM PDT 24
Finished Aug 07 05:50:13 PM PDT 24
Peak memory 195604 kb
Host smart-1ff166e4-5cb7-4f37-9066-2a0e36b7aed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596584729 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2596584729
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1462351178
Short name T389
Test name
Test status
Simulation time 317459438 ps
CPU time 1 seconds
Started Aug 07 05:50:12 PM PDT 24
Finished Aug 07 05:50:14 PM PDT 24
Peak memory 193084 kb
Host smart-0083cc57-0c10-4c3b-91fe-c0a7094f9308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462351178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1462351178
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.666188015
Short name T364
Test name
Test status
Simulation time 491215831 ps
CPU time 1.28 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:13 PM PDT 24
Peak memory 193032 kb
Host smart-a5ba8b0c-f505-4ea1-93b7-694c6ee77ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666188015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.666188015
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4097778806
Short name T338
Test name
Test status
Simulation time 1779470121 ps
CPU time 1.4 seconds
Started Aug 07 05:50:13 PM PDT 24
Finished Aug 07 05:50:15 PM PDT 24
Peak memory 195236 kb
Host smart-b663b6dc-164f-431c-9426-27f91212ed60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097778806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.4097778806
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3445293847
Short name T412
Test name
Test status
Simulation time 344147980 ps
CPU time 2.77 seconds
Started Aug 07 05:50:05 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 198620 kb
Host smart-28613f1b-b006-42ef-8bc8-2e5ed40e9f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445293847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3445293847
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2233271181
Short name T366
Test name
Test status
Simulation time 4246485237 ps
CPU time 3.97 seconds
Started Aug 07 05:50:05 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 197964 kb
Host smart-16eed6d0-8afd-4b6c-9228-d20af725a025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233271181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2233271181
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1483749335
Short name T378
Test name
Test status
Simulation time 830967143 ps
CPU time 1.41 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:13 PM PDT 24
Peak memory 198636 kb
Host smart-23b3acc3-f5f5-493c-978c-de6f5ef40f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483749335 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1483749335
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2546153323
Short name T358
Test name
Test status
Simulation time 560970969 ps
CPU time 0.68 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:12 PM PDT 24
Peak memory 193940 kb
Host smart-cb14993a-68ad-42ce-b9e3-c058fd8a1331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546153323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2546153323
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4003222811
Short name T306
Test name
Test status
Simulation time 460033216 ps
CPU time 0.86 seconds
Started Aug 07 05:50:09 PM PDT 24
Finished Aug 07 05:50:10 PM PDT 24
Peak memory 183748 kb
Host smart-228d559a-5428-4ead-8941-0d8d0ace90bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003222811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4003222811
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3969035353
Short name T334
Test name
Test status
Simulation time 2872040170 ps
CPU time 4.09 seconds
Started Aug 07 05:50:10 PM PDT 24
Finished Aug 07 05:50:14 PM PDT 24
Peak memory 192076 kb
Host smart-1fadb8ee-7403-4c25-aff4-6dc9711e6a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969035353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3969035353
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2066906920
Short name T375
Test name
Test status
Simulation time 593064869 ps
CPU time 3.33 seconds
Started Aug 07 05:50:13 PM PDT 24
Finished Aug 07 05:50:16 PM PDT 24
Peak memory 198596 kb
Host smart-0c27e8fd-9d02-4818-8a7e-64e9fc4c038a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066906920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2066906920
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1857811703
Short name T385
Test name
Test status
Simulation time 4668532161 ps
CPU time 1.39 seconds
Started Aug 07 05:50:10 PM PDT 24
Finished Aug 07 05:50:12 PM PDT 24
Peak memory 196820 kb
Host smart-518db087-a301-4bae-97dc-6c3f7fa73215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857811703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1857811703
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.958636598
Short name T206
Test name
Test status
Simulation time 450103796 ps
CPU time 1.21 seconds
Started Aug 07 05:50:09 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 195680 kb
Host smart-b1a496ec-4fa6-4947-b1af-62b86bf4455a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958636598 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.958636598
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2725196581
Short name T55
Test name
Test status
Simulation time 544288187 ps
CPU time 0.78 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:12 PM PDT 24
Peak memory 193296 kb
Host smart-56729ebe-e776-4ee3-97cd-2f0eac8cb4d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725196581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2725196581
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2556967744
Short name T333
Test name
Test status
Simulation time 315696821 ps
CPU time 0.98 seconds
Started Aug 07 05:50:10 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 183792 kb
Host smart-128cc233-7902-4fbf-a4dc-4cae7eb03d79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556967744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2556967744
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.890332296
Short name T403
Test name
Test status
Simulation time 1129555804 ps
CPU time 1.91 seconds
Started Aug 07 05:50:09 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 192988 kb
Host smart-c4e1f614-da73-4885-a4fd-e942d9561bbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890332296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.890332296
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.23741580
Short name T359
Test name
Test status
Simulation time 409162301 ps
CPU time 1.08 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:12 PM PDT 24
Peak memory 198144 kb
Host smart-c6fbe045-84f5-4134-8280-95ec49758821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.23741580
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3220378562
Short name T200
Test name
Test status
Simulation time 8810978079 ps
CPU time 12.69 seconds
Started Aug 07 05:50:12 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 198432 kb
Host smart-1d7b0647-bf04-4a32-846d-81bfc334b44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220378562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3220378562
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.116542546
Short name T383
Test name
Test status
Simulation time 412955431 ps
CPU time 0.75 seconds
Started Aug 07 05:50:12 PM PDT 24
Finished Aug 07 05:50:13 PM PDT 24
Peak memory 195316 kb
Host smart-90317731-e697-4807-bf40-7fcbba05f53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116542546 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.116542546
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3897094847
Short name T78
Test name
Test status
Simulation time 403443991 ps
CPU time 1.14 seconds
Started Aug 07 05:50:13 PM PDT 24
Finished Aug 07 05:50:14 PM PDT 24
Peak memory 192016 kb
Host smart-3643a552-fa9c-4e8a-b4b3-629b39523706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897094847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3897094847
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1962816637
Short name T350
Test name
Test status
Simulation time 344689993 ps
CPU time 1.04 seconds
Started Aug 07 05:50:10 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 193032 kb
Host smart-905e7c9e-7ff2-428a-8107-92d12407b8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962816637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1962816637
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3824988776
Short name T83
Test name
Test status
Simulation time 2107050325 ps
CPU time 1.41 seconds
Started Aug 07 05:50:35 PM PDT 24
Finished Aug 07 05:50:36 PM PDT 24
Peak memory 195272 kb
Host smart-4c34f0fc-bb82-4d0c-aea5-68403c1d705a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824988776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3824988776
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.459433011
Short name T400
Test name
Test status
Simulation time 1520501855 ps
CPU time 1.99 seconds
Started Aug 07 05:50:15 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 198600 kb
Host smart-763c753a-0c36-4c89-8192-af7c9bc0157c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459433011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.459433011
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.842122812
Short name T198
Test name
Test status
Simulation time 4295687748 ps
CPU time 7.1 seconds
Started Aug 07 05:50:11 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 198228 kb
Host smart-b15a2582-1263-4e7a-8f7e-28d70d4ed85a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842122812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.842122812
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2793918010
Short name T298
Test name
Test status
Simulation time 360927243 ps
CPU time 1.17 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 195996 kb
Host smart-222a4dce-4cf5-4417-aaff-27a66e454bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793918010 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2793918010
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2146363871
Short name T54
Test name
Test status
Simulation time 312401397 ps
CPU time 0.97 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 192980 kb
Host smart-1026d8db-c715-4cee-931c-077f02a7db15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146363871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2146363871
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.638884204
Short name T380
Test name
Test status
Simulation time 310252844 ps
CPU time 0.63 seconds
Started Aug 07 05:50:16 PM PDT 24
Finished Aug 07 05:50:16 PM PDT 24
Peak memory 183752 kb
Host smart-56d542a4-ac19-4cf0-ae3c-f19261660cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638884204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.638884204
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1063808235
Short name T80
Test name
Test status
Simulation time 1801115898 ps
CPU time 3.66 seconds
Started Aug 07 05:50:18 PM PDT 24
Finished Aug 07 05:50:22 PM PDT 24
Peak memory 195224 kb
Host smart-1d03a87b-7b70-4e36-9bd5-d4e6a99713a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063808235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1063808235
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3223315753
Short name T292
Test name
Test status
Simulation time 799584978 ps
CPU time 1.32 seconds
Started Aug 07 05:50:19 PM PDT 24
Finished Aug 07 05:50:20 PM PDT 24
Peak memory 198652 kb
Host smart-c0b15198-57f4-4726-a88b-2f5bea8c59c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223315753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3223315753
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1462687674
Short name T301
Test name
Test status
Simulation time 8088735306 ps
CPU time 12.07 seconds
Started Aug 07 05:50:18 PM PDT 24
Finished Aug 07 05:50:31 PM PDT 24
Peak memory 198160 kb
Host smart-64a29848-ce40-4b79-9af8-59570b3125ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462687674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1462687674
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2007649921
Short name T36
Test name
Test status
Simulation time 442821765 ps
CPU time 1.33 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 196088 kb
Host smart-dda4ea0f-fce5-4650-aa2c-341989bcd164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007649921 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2007649921
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1372556196
Short name T313
Test name
Test status
Simulation time 396173444 ps
CPU time 1.24 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 193196 kb
Host smart-19541fb1-c460-4138-ac91-010568249f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372556196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1372556196
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2615029592
Short name T409
Test name
Test status
Simulation time 495058061 ps
CPU time 1.19 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 183776 kb
Host smart-947bfd26-b634-4885-98e8-de5b61bb18ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615029592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2615029592
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2729410451
Short name T77
Test name
Test status
Simulation time 1488135280 ps
CPU time 1.04 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 192976 kb
Host smart-cb9fb8a4-1c29-4d53-acf0-41125e451d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729410451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2729410451
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4117952748
Short name T324
Test name
Test status
Simulation time 672759794 ps
CPU time 2.03 seconds
Started Aug 07 05:50:16 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 198588 kb
Host smart-f327faba-96c2-4818-b077-104ed02e1245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117952748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4117952748
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1195685588
Short name T391
Test name
Test status
Simulation time 8130894269 ps
CPU time 14.79 seconds
Started Aug 07 05:50:19 PM PDT 24
Finished Aug 07 05:50:34 PM PDT 24
Peak memory 198416 kb
Host smart-b282c111-b7ed-411e-ae16-b87527cee391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195685588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1195685588
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.376153082
Short name T74
Test name
Test status
Simulation time 515356276 ps
CPU time 1.35 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 193312 kb
Host smart-5157afc1-4cea-4796-a800-19e05fa4228e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376153082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.376153082
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.769529896
Short name T384
Test name
Test status
Simulation time 11677013102 ps
CPU time 31.39 seconds
Started Aug 07 05:49:45 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 196268 kb
Host smart-db72aa48-b0bd-406e-84b5-a5856173c9ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769529896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.769529896
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3836363612
Short name T69
Test name
Test status
Simulation time 708170992 ps
CPU time 0.76 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 183792 kb
Host smart-8efe6708-6415-4e80-92ce-10a85746bbe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836363612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3836363612
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1829060879
Short name T357
Test name
Test status
Simulation time 316558733 ps
CPU time 0.73 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 196136 kb
Host smart-d64d01c0-23c4-4c1d-9939-f62b9ed6d80e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829060879 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1829060879
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1940515255
Short name T318
Test name
Test status
Simulation time 563201113 ps
CPU time 0.69 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 193020 kb
Host smart-84d71c1b-cb4b-415f-ab4e-04ce70d4676d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940515255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1940515255
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2604533210
Short name T348
Test name
Test status
Simulation time 340857933 ps
CPU time 1.03 seconds
Started Aug 07 05:49:44 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 183760 kb
Host smart-d57bd034-a491-42b0-b78d-3dc24d5948db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604533210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2604533210
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2052407162
Short name T342
Test name
Test status
Simulation time 320659334 ps
CPU time 0.62 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:46 PM PDT 24
Peak memory 183708 kb
Host smart-2e2dbfc9-e7cb-4808-ab19-a0855e27e4cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052407162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2052407162
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3509782375
Short name T405
Test name
Test status
Simulation time 413443174 ps
CPU time 0.66 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 183592 kb
Host smart-5dc79326-8351-48f5-8acc-37d8b796d034
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509782375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3509782375
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.467150775
Short name T376
Test name
Test status
Simulation time 2802218068 ps
CPU time 4.05 seconds
Started Aug 07 05:49:53 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 195096 kb
Host smart-6ed077d9-cf8e-4121-b7c7-396805ec3131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467150775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.467150775
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1358318961
Short name T349
Test name
Test status
Simulation time 509552769 ps
CPU time 1.78 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 05:49:42 PM PDT 24
Peak memory 198592 kb
Host smart-17230e9a-e6d0-494e-99dd-a43d1dd931d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358318961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1358318961
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3611765528
Short name T347
Test name
Test status
Simulation time 4555530835 ps
CPU time 7.67 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 05:49:49 PM PDT 24
Peak memory 197968 kb
Host smart-511889f7-c913-4d7f-9423-17b83da21e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611765528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3611765528
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2655864904
Short name T320
Test name
Test status
Simulation time 421945829 ps
CPU time 0.66 seconds
Started Aug 07 05:50:18 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 192904 kb
Host smart-e4e05432-2302-4573-a97f-dcfc5c1b14ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655864904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2655864904
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1042178629
Short name T311
Test name
Test status
Simulation time 344622333 ps
CPU time 0.78 seconds
Started Aug 07 05:50:15 PM PDT 24
Finished Aug 07 05:50:16 PM PDT 24
Peak memory 183796 kb
Host smart-d49d175d-e20d-431f-991f-9fa3a1a83b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042178629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1042178629
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.432167198
Short name T417
Test name
Test status
Simulation time 518077215 ps
CPU time 1.32 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 183764 kb
Host smart-0555af54-a55b-43f0-afd8-6f1a61c4c423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432167198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.432167198
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3133012391
Short name T362
Test name
Test status
Simulation time 503592061 ps
CPU time 1.26 seconds
Started Aug 07 05:50:16 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 183772 kb
Host smart-bb8e8a1a-fd3e-4c46-81ae-c2ef0ca1daa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133012391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3133012391
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3709553709
Short name T381
Test name
Test status
Simulation time 517412321 ps
CPU time 0.72 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 183784 kb
Host smart-5de9a4ce-0dfe-48b0-b8cb-a8843c3d5962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709553709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3709553709
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.223200044
Short name T289
Test name
Test status
Simulation time 467756911 ps
CPU time 0.72 seconds
Started Aug 07 05:50:16 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 183768 kb
Host smart-71256469-0244-4096-bad7-3425962a3a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223200044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.223200044
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2732303839
Short name T296
Test name
Test status
Simulation time 474895970 ps
CPU time 0.66 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:21 PM PDT 24
Peak memory 193216 kb
Host smart-7edb714a-e765-493d-a713-70f738f19d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732303839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2732303839
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.145270309
Short name T404
Test name
Test status
Simulation time 495231166 ps
CPU time 1.14 seconds
Started Aug 07 05:50:19 PM PDT 24
Finished Aug 07 05:50:21 PM PDT 24
Peak memory 192992 kb
Host smart-f593e08b-0dd0-40f9-adbd-f38a218ff6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145270309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.145270309
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1573422139
Short name T310
Test name
Test status
Simulation time 433838591 ps
CPU time 0.85 seconds
Started Aug 07 05:50:17 PM PDT 24
Finished Aug 07 05:50:18 PM PDT 24
Peak memory 183692 kb
Host smart-148d5f8d-9190-4410-894e-8bcb43dd7690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573422139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1573422139
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.723948022
Short name T407
Test name
Test status
Simulation time 343318761 ps
CPU time 0.69 seconds
Started Aug 07 05:50:19 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 183768 kb
Host smart-94b2f28d-a74f-4e66-82ad-f14dd8506e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723948022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.723948022
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4264504227
Short name T68
Test name
Test status
Simulation time 562928847 ps
CPU time 0.84 seconds
Started Aug 07 05:49:48 PM PDT 24
Finished Aug 07 05:49:49 PM PDT 24
Peak memory 183872 kb
Host smart-6aa86610-117d-4d44-b8fc-8ce2f4d2444e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264504227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4264504227
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.364633065
Short name T58
Test name
Test status
Simulation time 3138292721 ps
CPU time 2.12 seconds
Started Aug 07 05:49:46 PM PDT 24
Finished Aug 07 05:49:48 PM PDT 24
Peak memory 196600 kb
Host smart-65fec7bb-56be-4dd3-ae5d-48105d47b7ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364633065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.364633065
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1070667861
Short name T75
Test name
Test status
Simulation time 1088176316 ps
CPU time 0.96 seconds
Started Aug 07 05:49:44 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 193388 kb
Host smart-314df81c-d8f6-4c0c-9769-ce51beded83e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070667861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1070667861
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.694561601
Short name T335
Test name
Test status
Simulation time 396889234 ps
CPU time 1 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 196384 kb
Host smart-68a0ea74-6670-43c9-aa8d-49f2dfb7f663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694561601 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.694561601
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4202291042
Short name T408
Test name
Test status
Simulation time 318305308 ps
CPU time 0.97 seconds
Started Aug 07 05:49:49 PM PDT 24
Finished Aug 07 05:49:50 PM PDT 24
Peak memory 192880 kb
Host smart-fbdc62e4-8bd4-4a73-9ae7-636afc170d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202291042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4202291042
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1828219801
Short name T288
Test name
Test status
Simulation time 346014821 ps
CPU time 1.02 seconds
Started Aug 07 05:49:54 PM PDT 24
Finished Aug 07 05:49:55 PM PDT 24
Peak memory 193016 kb
Host smart-d4c6fed3-f39e-40bd-a498-3552c359a195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828219801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1828219801
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2402415119
Short name T368
Test name
Test status
Simulation time 281818715 ps
CPU time 0.75 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:52 PM PDT 24
Peak memory 183596 kb
Host smart-43a88450-f1ec-4651-8bd4-cae98a1b22b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402415119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2402415119
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.603732846
Short name T416
Test name
Test status
Simulation time 578060198 ps
CPU time 0.59 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 183592 kb
Host smart-81f70a0c-1a68-4915-90b7-349d0b3f3250
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603732846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.603732846
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1119631220
Short name T85
Test name
Test status
Simulation time 3142545517 ps
CPU time 2.86 seconds
Started Aug 07 05:49:48 PM PDT 24
Finished Aug 07 05:49:51 PM PDT 24
Peak memory 195472 kb
Host smart-1656c252-9b1c-4f28-875e-17817d8a0e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119631220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1119631220
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3108372460
Short name T392
Test name
Test status
Simulation time 506145971 ps
CPU time 2.12 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:54 PM PDT 24
Peak memory 198536 kb
Host smart-096ace0e-86b7-468e-9c0e-80d09c9bd6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108372460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3108372460
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3115425280
Short name T196
Test name
Test status
Simulation time 4740652636 ps
CPU time 8.32 seconds
Started Aug 07 05:49:51 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 197600 kb
Host smart-264c8c9a-2bf2-46b9-81d2-64fc3c738ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115425280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3115425280
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2195870621
Short name T402
Test name
Test status
Simulation time 330312758 ps
CPU time 0.77 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 193044 kb
Host smart-1420be9f-e2e5-4fc0-ae73-a8ce081dfde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195870621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2195870621
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1051980266
Short name T393
Test name
Test status
Simulation time 484078466 ps
CPU time 0.69 seconds
Started Aug 07 05:50:20 PM PDT 24
Finished Aug 07 05:50:21 PM PDT 24
Peak memory 183768 kb
Host smart-a199df10-185f-4585-a991-c43d0e1dc906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051980266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1051980266
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.629968358
Short name T291
Test name
Test status
Simulation time 346494271 ps
CPU time 0.66 seconds
Started Aug 07 05:50:23 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 183768 kb
Host smart-e11f8c59-b1f2-4594-9ded-a0af5d973561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629968358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.629968358
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2980732026
Short name T345
Test name
Test status
Simulation time 484972523 ps
CPU time 0.68 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 183768 kb
Host smart-5e66d0dd-55ef-458b-9470-df20eaca62b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980732026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2980732026
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1549531997
Short name T351
Test name
Test status
Simulation time 407535736 ps
CPU time 1.22 seconds
Started Aug 07 05:50:23 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 183996 kb
Host smart-96be0423-76c4-48b8-a024-1e529764d969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549531997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1549531997
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3290871137
Short name T326
Test name
Test status
Simulation time 484017925 ps
CPU time 1.14 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:22 PM PDT 24
Peak memory 183720 kb
Host smart-511c26ae-c1ca-45a4-a666-cb740ee63254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290871137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3290871137
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.450309758
Short name T353
Test name
Test status
Simulation time 316692776 ps
CPU time 0.77 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 183812 kb
Host smart-4055f7ff-a3fc-4189-b093-d79787830482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450309758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.450309758
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.385270581
Short name T323
Test name
Test status
Simulation time 367488984 ps
CPU time 1.11 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:23 PM PDT 24
Peak memory 183768 kb
Host smart-968a96ba-12c1-4fda-8ce6-38ce7508ce6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385270581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.385270581
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4076051632
Short name T344
Test name
Test status
Simulation time 296139592 ps
CPU time 0.65 seconds
Started Aug 07 05:50:20 PM PDT 24
Finished Aug 07 05:50:21 PM PDT 24
Peak memory 183748 kb
Host smart-a9dd6f05-b73e-4e0b-9588-493baf9cc924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076051632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4076051632
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2732776474
Short name T307
Test name
Test status
Simulation time 522499323 ps
CPU time 0.61 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 183704 kb
Host smart-c236ea91-1cca-4fa1-ac7b-78680ca05e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732776474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2732776474
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4135236370
Short name T39
Test name
Test status
Simulation time 605653042 ps
CPU time 0.82 seconds
Started Aug 07 05:49:50 PM PDT 24
Finished Aug 07 05:49:51 PM PDT 24
Peak memory 193200 kb
Host smart-04a81268-2c27-4f59-a697-35cd5a68e0ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135236370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4135236370
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2895257222
Short name T398
Test name
Test status
Simulation time 4567103805 ps
CPU time 2.84 seconds
Started Aug 07 05:49:56 PM PDT 24
Finished Aug 07 05:49:59 PM PDT 24
Peak memory 196164 kb
Host smart-fe000d76-6183-45ea-aaaa-2e6bc2089a73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895257222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2895257222
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.899409467
Short name T294
Test name
Test status
Simulation time 1424880721 ps
CPU time 1.1 seconds
Started Aug 07 05:49:50 PM PDT 24
Finished Aug 07 05:49:51 PM PDT 24
Peak memory 193336 kb
Host smart-1dc615ae-ef6e-4fbf-9609-88ff558bfed1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899409467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.899409467
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.736051669
Short name T303
Test name
Test status
Simulation time 411556852 ps
CPU time 1.26 seconds
Started Aug 07 05:50:00 PM PDT 24
Finished Aug 07 05:50:02 PM PDT 24
Peak memory 196292 kb
Host smart-d63bc928-6a94-4a1f-9287-8738a827b545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736051669 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.736051669
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.976434679
Short name T71
Test name
Test status
Simulation time 555048411 ps
CPU time 0.76 seconds
Started Aug 07 05:49:51 PM PDT 24
Finished Aug 07 05:49:52 PM PDT 24
Peak memory 193092 kb
Host smart-69463faf-9d41-49e9-bec2-c5cb2871a48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976434679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.976434679
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.632474572
Short name T377
Test name
Test status
Simulation time 309134247 ps
CPU time 0.98 seconds
Started Aug 07 05:49:51 PM PDT 24
Finished Aug 07 05:49:52 PM PDT 24
Peak memory 183724 kb
Host smart-7bb3712f-8dab-4844-89f6-65ab026185a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632474572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.632474572
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1815585365
Short name T388
Test name
Test status
Simulation time 531017920 ps
CPU time 0.69 seconds
Started Aug 07 05:49:52 PM PDT 24
Finished Aug 07 05:49:52 PM PDT 24
Peak memory 183736 kb
Host smart-7eeccb2d-3b8b-440b-909e-622182a92a19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815585365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1815585365
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3404868238
Short name T302
Test name
Test status
Simulation time 510189547 ps
CPU time 0.69 seconds
Started Aug 07 05:49:49 PM PDT 24
Finished Aug 07 05:49:50 PM PDT 24
Peak memory 183680 kb
Host smart-fc45cd77-9185-469c-81a2-3a1f8493f88d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404868238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3404868238
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4265804726
Short name T81
Test name
Test status
Simulation time 2228826673 ps
CPU time 2.18 seconds
Started Aug 07 05:49:57 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 194252 kb
Host smart-266ce640-e93c-4f4f-8974-5e2cc87a5394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265804726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4265804726
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3336114239
Short name T331
Test name
Test status
Simulation time 477506202 ps
CPU time 2.09 seconds
Started Aug 07 05:49:51 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 198492 kb
Host smart-9e17338f-b5b5-450f-a695-9dc1d98572f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336114239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3336114239
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4207179939
Short name T367
Test name
Test status
Simulation time 339768065 ps
CPU time 1.09 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 183824 kb
Host smart-2c507b98-0bad-45be-a04b-f193673ddb36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207179939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4207179939
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3426988830
Short name T314
Test name
Test status
Simulation time 456908580 ps
CPU time 0.72 seconds
Started Aug 07 05:50:23 PM PDT 24
Finished Aug 07 05:50:23 PM PDT 24
Peak memory 183776 kb
Host smart-fdc58467-d548-497c-ad7d-75c2a71bb754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426988830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3426988830
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3400346729
Short name T309
Test name
Test status
Simulation time 522698263 ps
CPU time 0.69 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:22 PM PDT 24
Peak memory 183780 kb
Host smart-3a57b0d3-0139-490d-9131-6ccd065f743f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400346729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3400346729
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1532926460
Short name T372
Test name
Test status
Simulation time 388049137 ps
CPU time 0.82 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:22 PM PDT 24
Peak memory 183800 kb
Host smart-2c12596b-b585-48b0-acc3-257cd306e27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532926460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1532926460
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1672159964
Short name T369
Test name
Test status
Simulation time 400466504 ps
CPU time 0.65 seconds
Started Aug 07 05:50:25 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 183816 kb
Host smart-c5fdb930-a9a5-4ab4-b335-b0eccb0831a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672159964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1672159964
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2193256348
Short name T382
Test name
Test status
Simulation time 356646088 ps
CPU time 0.8 seconds
Started Aug 07 05:50:25 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 183816 kb
Host smart-bbb7b604-ab17-48b6-803e-5f9f4995fda4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193256348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2193256348
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2031795867
Short name T360
Test name
Test status
Simulation time 300689186 ps
CPU time 0.68 seconds
Started Aug 07 05:50:23 PM PDT 24
Finished Aug 07 05:50:24 PM PDT 24
Peak memory 192940 kb
Host smart-f550cbe0-c2dd-4c18-b576-aaf58ee40ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031795867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2031795867
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1741742618
Short name T329
Test name
Test status
Simulation time 301274997 ps
CPU time 0.63 seconds
Started Aug 07 05:50:22 PM PDT 24
Finished Aug 07 05:50:23 PM PDT 24
Peak memory 183792 kb
Host smart-a1b75102-2081-44ae-a445-f93867d1ddec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741742618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1741742618
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3031080709
Short name T370
Test name
Test status
Simulation time 487855274 ps
CPU time 0.71 seconds
Started Aug 07 05:50:24 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 192924 kb
Host smart-d66f11a9-43b0-4624-af25-1ef8adad4acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031080709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3031080709
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3083665008
Short name T315
Test name
Test status
Simulation time 446137957 ps
CPU time 0.67 seconds
Started Aug 07 05:50:21 PM PDT 24
Finished Aug 07 05:50:22 PM PDT 24
Peak memory 183760 kb
Host smart-06ed75d1-01a2-4938-998f-35dc81955695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083665008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3083665008
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3025205209
Short name T396
Test name
Test status
Simulation time 297254775 ps
CPU time 0.98 seconds
Started Aug 07 05:49:56 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 195112 kb
Host smart-dbb409e7-0c09-4dc3-aad4-066e47ee47d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025205209 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3025205209
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.93687221
Short name T394
Test name
Test status
Simulation time 540592259 ps
CPU time 0.84 seconds
Started Aug 07 05:49:56 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 191960 kb
Host smart-019f7716-15f6-4318-9c94-bf68a01f89c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93687221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.93687221
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2974513296
Short name T290
Test name
Test status
Simulation time 324021130 ps
CPU time 0.73 seconds
Started Aug 07 05:49:57 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 183788 kb
Host smart-1eebe08f-1177-4477-b093-b239d7338492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974513296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2974513296
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2044360303
Short name T365
Test name
Test status
Simulation time 2590922768 ps
CPU time 3.42 seconds
Started Aug 07 05:49:54 PM PDT 24
Finished Aug 07 05:49:58 PM PDT 24
Peak memory 194140 kb
Host smart-876f0be5-645b-4478-9b32-79883f41a31a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044360303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2044360303
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3608796629
Short name T343
Test name
Test status
Simulation time 553214754 ps
CPU time 2.72 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:58 PM PDT 24
Peak memory 198628 kb
Host smart-9be00dfb-7167-4ae5-a0bb-57834cd8b7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608796629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3608796629
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.713083546
Short name T38
Test name
Test status
Simulation time 7873439581 ps
CPU time 6.42 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 198428 kb
Host smart-79d9b53f-fc83-44c6-b77d-3e50cb7f840d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713083546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.713083546
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4053089460
Short name T297
Test name
Test status
Simulation time 468786833 ps
CPU time 0.8 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 194996 kb
Host smart-45fbcb26-e13b-4a12-a6cd-9d121b1fb902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053089460 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4053089460
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2966467498
Short name T406
Test name
Test status
Simulation time 469759325 ps
CPU time 0.59 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 192956 kb
Host smart-128ac42e-12c1-41a1-89a6-97085dd1ed9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966467498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2966467498
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.724196602
Short name T415
Test name
Test status
Simulation time 468970136 ps
CPU time 1.27 seconds
Started Aug 07 05:49:54 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 193008 kb
Host smart-08aebcf3-00f7-4998-985d-b0d7c369daf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724196602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.724196602
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.668346507
Short name T319
Test name
Test status
Simulation time 2380953881 ps
CPU time 5.48 seconds
Started Aug 07 05:49:54 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 195104 kb
Host smart-c96ef71f-b72c-4280-a689-10290bd2cade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668346507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.668346507
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3490773211
Short name T287
Test name
Test status
Simulation time 415556651 ps
CPU time 2.35 seconds
Started Aug 07 05:49:58 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 198616 kb
Host smart-9862ac50-4ef7-48cf-aaf1-6dd8c4172526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490773211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3490773211
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2979365450
Short name T34
Test name
Test status
Simulation time 4414509570 ps
CPU time 6.38 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:06 PM PDT 24
Peak memory 197476 kb
Host smart-112bee23-d274-46b9-8c1a-8130645f5c08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979365450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2979365450
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2090305011
Short name T361
Test name
Test status
Simulation time 313277954 ps
CPU time 0.85 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 195168 kb
Host smart-24a745e4-97a0-4687-bf5e-9c87b4da166e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090305011 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2090305011
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.734689753
Short name T82
Test name
Test status
Simulation time 511604101 ps
CPU time 1.29 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 193020 kb
Host smart-b49b61cc-c280-414d-a7da-b89cb259abc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734689753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.734689753
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3888393806
Short name T387
Test name
Test status
Simulation time 524421729 ps
CPU time 0.8 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:55 PM PDT 24
Peak memory 183804 kb
Host smart-0321a31e-254f-4af0-9ae3-307471b0a867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888393806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3888393806
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.275000055
Short name T79
Test name
Test status
Simulation time 2975891258 ps
CPU time 1.68 seconds
Started Aug 07 05:50:07 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 195260 kb
Host smart-beec390e-ec6a-4995-a132-d81c6659a520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275000055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.275000055
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.217420148
Short name T413
Test name
Test status
Simulation time 417433676 ps
CPU time 1.63 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 198132 kb
Host smart-0d688c6a-62ec-4f50-aeb0-d90622c8ae18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217420148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.217420148
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1567440842
Short name T379
Test name
Test status
Simulation time 7973080754 ps
CPU time 3.99 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:59 PM PDT 24
Peak memory 198216 kb
Host smart-82ba7e60-8da3-4ab5-a441-18f5c22c8b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567440842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1567440842
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.764788236
Short name T337
Test name
Test status
Simulation time 365867776 ps
CPU time 1.14 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 196288 kb
Host smart-8867b215-2b6f-4166-a4b8-79ab4222a023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764788236 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.764788236
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1394336636
Short name T374
Test name
Test status
Simulation time 516343724 ps
CPU time 0.94 seconds
Started Aug 07 05:50:02 PM PDT 24
Finished Aug 07 05:50:03 PM PDT 24
Peak memory 193084 kb
Host smart-a16dd3fd-ef0f-4562-8ec9-6eacbe8e3fa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394336636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1394336636
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2813122850
Short name T363
Test name
Test status
Simulation time 301010849 ps
CPU time 0.99 seconds
Started Aug 07 05:49:58 PM PDT 24
Finished Aug 07 05:49:59 PM PDT 24
Peak memory 183988 kb
Host smart-e1b2101c-ade9-4ea1-bbfc-672aed07e9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813122850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2813122850
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3178189530
Short name T336
Test name
Test status
Simulation time 2099788101 ps
CPU time 2.91 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:06 PM PDT 24
Peak memory 183780 kb
Host smart-f41bad2e-a533-4615-9457-ba570e982d12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178189530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3178189530
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2397895871
Short name T321
Test name
Test status
Simulation time 580635290 ps
CPU time 2.23 seconds
Started Aug 07 05:49:55 PM PDT 24
Finished Aug 07 05:49:57 PM PDT 24
Peak memory 198648 kb
Host smart-24c35e9c-b2b3-45e1-8f6e-59ad2bad0118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397895871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2397895871
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.859692225
Short name T356
Test name
Test status
Simulation time 4340710543 ps
CPU time 4 seconds
Started Aug 07 05:49:57 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 197996 kb
Host smart-eaa6735f-4403-44e1-ba56-67e652803abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859692225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.859692225
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1543136749
Short name T299
Test name
Test status
Simulation time 434376997 ps
CPU time 0.91 seconds
Started Aug 07 05:50:04 PM PDT 24
Finished Aug 07 05:50:05 PM PDT 24
Peak memory 196800 kb
Host smart-7ce7e645-de78-49e6-bdfa-74ceab2a6f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543136749 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1543136749
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3843614997
Short name T70
Test name
Test status
Simulation time 308511281 ps
CPU time 0.66 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 192992 kb
Host smart-fd3c874a-b4d1-4edc-a2bc-1f4b8078cc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843614997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3843614997
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.594669592
Short name T386
Test name
Test status
Simulation time 468561610 ps
CPU time 1.24 seconds
Started Aug 07 05:49:59 PM PDT 24
Finished Aug 07 05:50:01 PM PDT 24
Peak memory 183760 kb
Host smart-dcec2659-29fe-4fb6-b780-77ffada657e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594669592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.594669592
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.714171826
Short name T371
Test name
Test status
Simulation time 1329631663 ps
CPU time 3.2 seconds
Started Aug 07 05:50:01 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 192040 kb
Host smart-1f08674c-db9e-49b7-b1eb-eb3efda77c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714171826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.714171826
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2841296654
Short name T286
Test name
Test status
Simulation time 427141756 ps
CPU time 2.04 seconds
Started Aug 07 05:50:03 PM PDT 24
Finished Aug 07 05:50:05 PM PDT 24
Peak memory 198648 kb
Host smart-8a8e996f-62eb-4784-bf0f-81554c64b070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841296654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2841296654
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.847594547
Short name T197
Test name
Test status
Simulation time 9541534531 ps
CPU time 1.85 seconds
Started Aug 07 05:50:01 PM PDT 24
Finished Aug 07 05:50:03 PM PDT 24
Peak memory 198356 kb
Host smart-657ce511-2692-421e-82aa-452e2c4f405e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847594547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.847594547
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3811725494
Short name T27
Test name
Test status
Simulation time 19087656439 ps
CPU time 7.66 seconds
Started Aug 07 05:48:16 PM PDT 24
Finished Aug 07 05:48:24 PM PDT 24
Peak memory 197184 kb
Host smart-7003761e-c987-4901-84be-055ba7803b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811725494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3811725494
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3967723565
Short name T23
Test name
Test status
Simulation time 595598539 ps
CPU time 0.94 seconds
Started Aug 07 05:48:18 PM PDT 24
Finished Aug 07 05:48:19 PM PDT 24
Peak memory 191992 kb
Host smart-863abf30-1c5c-41f0-afb7-bd461e0d976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967723565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3967723565
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2581966134
Short name T180
Test name
Test status
Simulation time 478314775 ps
CPU time 1.17 seconds
Started Aug 07 05:48:19 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 196848 kb
Host smart-0c8827e9-fdbd-41c7-bece-f3f2de2d0e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581966134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2581966134
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.508131263
Short name T28
Test name
Test status
Simulation time 12515079367 ps
CPU time 10.26 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:49:54 PM PDT 24
Peak memory 192124 kb
Host smart-e7b325eb-abf6-4902-9b31-bd7c84e2e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508131263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.508131263
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1798408904
Short name T20
Test name
Test status
Simulation time 4664212112 ps
CPU time 1.2 seconds
Started Aug 07 05:48:19 PM PDT 24
Finished Aug 07 05:48:20 PM PDT 24
Peak memory 215724 kb
Host smart-9e9cffcf-79ae-4cd8-a427-2f028f0a684c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798408904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1798408904
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2811001156
Short name T247
Test name
Test status
Simulation time 429524758 ps
CPU time 0.75 seconds
Started Aug 07 05:48:20 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 192116 kb
Host smart-ddd954de-b41f-4e6d-92c2-41c394f815dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811001156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2811001156
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.150435794
Short name T254
Test name
Test status
Simulation time 23865506939 ps
CPU time 36.13 seconds
Started Aug 07 05:48:35 PM PDT 24
Finished Aug 07 05:49:11 PM PDT 24
Peak memory 192076 kb
Host smart-7d164dc0-30fd-4163-b069-29ac4ffd9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150435794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.150435794
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.232369742
Short name T25
Test name
Test status
Simulation time 617068254 ps
CPU time 1.46 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:48:41 PM PDT 24
Peak memory 196924 kb
Host smart-6fc0b3e7-00a9-408c-8b8b-6d73ecb79c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232369742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.232369742
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.82690668
Short name T241
Test name
Test status
Simulation time 29551252760 ps
CPU time 9.93 seconds
Started Aug 07 05:48:37 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 197128 kb
Host smart-2ad664fc-1271-4f64-9201-a4335f6f6a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82690668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.82690668
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.683342969
Short name T216
Test name
Test status
Simulation time 518917769 ps
CPU time 0.74 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:48:40 PM PDT 24
Peak memory 196832 kb
Host smart-67c2d34d-1c59-41d4-a527-97058839a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683342969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.683342969
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1833201535
Short name T229
Test name
Test status
Simulation time 17871170753 ps
CPU time 29.31 seconds
Started Aug 07 05:48:38 PM PDT 24
Finished Aug 07 05:49:08 PM PDT 24
Peak memory 197128 kb
Host smart-4c3e9b78-8340-4b99-917b-a9ac9364151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833201535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1833201535
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1635486243
Short name T226
Test name
Test status
Simulation time 443566923 ps
CPU time 1.27 seconds
Started Aug 07 05:48:35 PM PDT 24
Finished Aug 07 05:48:36 PM PDT 24
Peak memory 191960 kb
Host smart-146daf8d-4e4d-47a2-a281-1b17fb5a2f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635486243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1635486243
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1263656716
Short name T267
Test name
Test status
Simulation time 972496316 ps
CPU time 1.93 seconds
Started Aug 07 05:48:42 PM PDT 24
Finished Aug 07 05:48:44 PM PDT 24
Peak memory 192124 kb
Host smart-3cb82c03-fd29-4d01-9d00-05f966a9d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263656716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1263656716
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2269058529
Short name T24
Test name
Test status
Simulation time 394216745 ps
CPU time 1.06 seconds
Started Aug 07 05:48:46 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 192144 kb
Host smart-443bc38c-9b9e-4f8a-a5d8-6f7a54afce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269058529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2269058529
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.810669887
Short name T237
Test name
Test status
Simulation time 7537033662 ps
CPU time 7.05 seconds
Started Aug 07 05:48:40 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 197096 kb
Host smart-aa0b1355-8b9f-4146-a381-9e0c0c23413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810669887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.810669887
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.646725005
Short name T62
Test name
Test status
Simulation time 400062687 ps
CPU time 0.72 seconds
Started Aug 07 05:48:46 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 192152 kb
Host smart-6963f70a-6cc2-4f6e-88fc-52549dbfa9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646725005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.646725005
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3211695654
Short name T10
Test name
Test status
Simulation time 17277548019 ps
CPU time 2.12 seconds
Started Aug 07 05:48:40 PM PDT 24
Finished Aug 07 05:48:42 PM PDT 24
Peak memory 192088 kb
Host smart-a5c88da7-0845-450d-93cc-ffdf46527661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211695654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3211695654
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.882323458
Short name T224
Test name
Test status
Simulation time 433608962 ps
CPU time 0.75 seconds
Started Aug 07 05:48:38 PM PDT 24
Finished Aug 07 05:48:39 PM PDT 24
Peak memory 196908 kb
Host smart-0852391b-8eb1-48e6-8bd3-0746a334d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882323458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.882323458
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3179964927
Short name T266
Test name
Test status
Simulation time 19105155526 ps
CPU time 29.66 seconds
Started Aug 07 05:48:42 PM PDT 24
Finished Aug 07 05:49:12 PM PDT 24
Peak memory 197148 kb
Host smart-302d0ade-3fe9-44a0-b1d5-fb0fe28e9704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179964927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3179964927
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1235263370
Short name T279
Test name
Test status
Simulation time 378316022 ps
CPU time 0.84 seconds
Started Aug 07 05:48:47 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 192016 kb
Host smart-acc80413-d0a4-4412-97c0-53272c6c890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235263370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1235263370
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4058511526
Short name T275
Test name
Test status
Simulation time 209556718150 ps
CPU time 75.1 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 192544 kb
Host smart-468201d1-a18b-49f7-9fb1-88cb18a78a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058511526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4058511526
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1701208974
Short name T22
Test name
Test status
Simulation time 423687107 ps
CPU time 1.09 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 196888 kb
Host smart-35b4e735-30cc-4226-a9cd-4f18a8e288d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701208974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1701208974
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1274897231
Short name T242
Test name
Test status
Simulation time 26471433931 ps
CPU time 39.93 seconds
Started Aug 07 05:48:47 PM PDT 24
Finished Aug 07 05:49:27 PM PDT 24
Peak memory 192140 kb
Host smart-bc271c8e-0608-4867-81aa-bd012226dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274897231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1274897231
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3498580571
Short name T30
Test name
Test status
Simulation time 423186273 ps
CPU time 1.21 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 192104 kb
Host smart-6f3769c8-d4be-4407-b592-0696fde96a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498580571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3498580571
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1161763425
Short name T280
Test name
Test status
Simulation time 24190716831 ps
CPU time 36.68 seconds
Started Aug 07 05:48:45 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 192164 kb
Host smart-d2d0c61c-94f4-4b3e-a673-31c689e8af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161763425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1161763425
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1838369233
Short name T248
Test name
Test status
Simulation time 413283251 ps
CPU time 0.76 seconds
Started Aug 07 05:48:48 PM PDT 24
Finished Aug 07 05:48:49 PM PDT 24
Peak memory 192148 kb
Host smart-0cd9f497-19c0-4c23-9a39-0152d5c4613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838369233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1838369233
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3834307055
Short name T258
Test name
Test status
Simulation time 6028529238 ps
CPU time 2.88 seconds
Started Aug 07 05:48:52 PM PDT 24
Finished Aug 07 05:48:55 PM PDT 24
Peak memory 197156 kb
Host smart-032c8ec6-2123-4394-a321-ef10da52134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834307055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3834307055
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2892590029
Short name T251
Test name
Test status
Simulation time 554050963 ps
CPU time 0.78 seconds
Started Aug 07 05:48:49 PM PDT 24
Finished Aug 07 05:48:50 PM PDT 24
Peak memory 192096 kb
Host smart-cfb5466b-4272-4a5a-9f9b-9e144198d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892590029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2892590029
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.327356665
Short name T228
Test name
Test status
Simulation time 31204387492 ps
CPU time 44.57 seconds
Started Aug 07 05:48:20 PM PDT 24
Finished Aug 07 05:49:04 PM PDT 24
Peak memory 192140 kb
Host smart-d9abee20-723f-4b0a-aa22-0981e833b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327356665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.327356665
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3823719433
Short name T14
Test name
Test status
Simulation time 4581520677 ps
CPU time 2.12 seconds
Started Aug 07 05:48:20 PM PDT 24
Finished Aug 07 05:48:22 PM PDT 24
Peak memory 215728 kb
Host smart-572c685b-d34f-4867-b005-149400602127
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823719433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3823719433
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4228314379
Short name T269
Test name
Test status
Simulation time 415705110 ps
CPU time 0.66 seconds
Started Aug 07 05:48:22 PM PDT 24
Finished Aug 07 05:48:23 PM PDT 24
Peak memory 192060 kb
Host smart-33d52179-b2a3-4ce0-8ff7-2bfb6582ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228314379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4228314379
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2123577612
Short name T211
Test name
Test status
Simulation time 13346358117 ps
CPU time 5.97 seconds
Started Aug 07 05:48:52 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 197180 kb
Host smart-fc20524c-b31d-4fde-8b52-48379719b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123577612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2123577612
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.490394236
Short name T250
Test name
Test status
Simulation time 465753699 ps
CPU time 0.65 seconds
Started Aug 07 05:48:53 PM PDT 24
Finished Aug 07 05:48:54 PM PDT 24
Peak memory 196776 kb
Host smart-d83a1734-9f03-49dd-9eac-7a7402118a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490394236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.490394236
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.544069482
Short name T187
Test name
Test status
Simulation time 467480186 ps
CPU time 0.76 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:48:56 PM PDT 24
Peak memory 196848 kb
Host smart-dd12a19d-5d33-4093-958d-a40ca2c16b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544069482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.544069482
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.808836671
Short name T219
Test name
Test status
Simulation time 24384160468 ps
CPU time 4.68 seconds
Started Aug 07 05:48:50 PM PDT 24
Finished Aug 07 05:48:54 PM PDT 24
Peak memory 192168 kb
Host smart-2775ab1f-7bce-45bd-880c-7556e608e9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808836671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.808836671
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3571074716
Short name T276
Test name
Test status
Simulation time 393662888 ps
CPU time 0.88 seconds
Started Aug 07 05:48:50 PM PDT 24
Finished Aug 07 05:48:51 PM PDT 24
Peak memory 196940 kb
Host smart-a4275654-55a6-4932-a7ee-59c1440069d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571074716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3571074716
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.303276399
Short name T3
Test name
Test status
Simulation time 37869382451 ps
CPU time 26.15 seconds
Started Aug 07 05:49:44 PM PDT 24
Finished Aug 07 05:50:10 PM PDT 24
Peak memory 192140 kb
Host smart-f6b68198-dfa2-436e-9958-9f7c05e668ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303276399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.303276399
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2194864323
Short name T259
Test name
Test status
Simulation time 355784492 ps
CPU time 1.06 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 192064 kb
Host smart-922ca559-9e16-4856-a90c-1b06d480c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194864323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2194864323
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.160377523
Short name T285
Test name
Test status
Simulation time 18121660758 ps
CPU time 14.03 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 197136 kb
Host smart-b30b82ee-9d23-468b-947f-317f4ba2382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160377523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.160377523
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2874827443
Short name T273
Test name
Test status
Simulation time 410242512 ps
CPU time 0.8 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 196828 kb
Host smart-ef7f2419-f9bc-4dbc-b69c-2a2d208f01ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874827443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2874827443
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.150507354
Short name T154
Test name
Test status
Simulation time 372349354700 ps
CPU time 583.78 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:58:41 PM PDT 24
Peak memory 192148 kb
Host smart-01547055-7dcc-4ac7-a1fc-12d589a98698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150507354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.150507354
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2850266680
Short name T284
Test name
Test status
Simulation time 13197197163 ps
CPU time 7.22 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:49:02 PM PDT 24
Peak memory 197124 kb
Host smart-c953505c-7678-4eb9-ae53-f73f00a69d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850266680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2850266680
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2768585267
Short name T253
Test name
Test status
Simulation time 570602358 ps
CPU time 0.76 seconds
Started Aug 07 05:48:56 PM PDT 24
Finished Aug 07 05:48:57 PM PDT 24
Peak memory 192016 kb
Host smart-457717f1-0159-4da6-bd6a-dcae833416ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768585267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2768585267
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3283708720
Short name T205
Test name
Test status
Simulation time 55148572070 ps
CPU time 72.15 seconds
Started Aug 07 05:48:59 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 192156 kb
Host smart-b96482bc-d038-436b-a18b-3a032e359d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283708720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3283708720
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1188212649
Short name T271
Test name
Test status
Simulation time 419380246 ps
CPU time 1.18 seconds
Started Aug 07 05:48:57 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 192060 kb
Host smart-9ec2573a-9851-4f3e-8461-7e1688fe8603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188212649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1188212649
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3877768477
Short name T223
Test name
Test status
Simulation time 35305065804 ps
CPU time 47.98 seconds
Started Aug 07 05:48:59 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 192188 kb
Host smart-f06b291d-198f-461c-94ce-bdfe4aef4a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877768477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3877768477
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1937339505
Short name T12
Test name
Test status
Simulation time 520829791 ps
CPU time 1.37 seconds
Started Aug 07 05:48:55 PM PDT 24
Finished Aug 07 05:48:56 PM PDT 24
Peak memory 192032 kb
Host smart-41329421-c8ee-4582-b057-f4521ed259ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937339505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1937339505
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.545466029
Short name T218
Test name
Test status
Simulation time 56771317537 ps
CPU time 40.32 seconds
Started Aug 07 05:49:01 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 192136 kb
Host smart-ae1e9e1f-d08e-47d2-839c-df06a944a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545466029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.545466029
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4072108177
Short name T274
Test name
Test status
Simulation time 600446829 ps
CPU time 1.24 seconds
Started Aug 07 05:49:03 PM PDT 24
Finished Aug 07 05:49:04 PM PDT 24
Peak memory 192092 kb
Host smart-3db34b2c-7189-45de-b525-9d3543323771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072108177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4072108177
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.550567709
Short name T202
Test name
Test status
Simulation time 30046872929 ps
CPU time 12.19 seconds
Started Aug 07 05:49:06 PM PDT 24
Finished Aug 07 05:49:18 PM PDT 24
Peak memory 192168 kb
Host smart-2db57d64-f73e-455a-9d3f-d896e8fa950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550567709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.550567709
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1837122251
Short name T215
Test name
Test status
Simulation time 531607131 ps
CPU time 0.95 seconds
Started Aug 07 05:49:03 PM PDT 24
Finished Aug 07 05:49:05 PM PDT 24
Peak memory 192108 kb
Host smart-9101f632-bd44-4498-900f-a05a1f893397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837122251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1837122251
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2834692223
Short name T260
Test name
Test status
Simulation time 40183086155 ps
CPU time 58.96 seconds
Started Aug 07 05:49:01 PM PDT 24
Finished Aug 07 05:50:00 PM PDT 24
Peak memory 192172 kb
Host smart-fa38a8e3-9b5c-4078-9586-159fe8f5ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834692223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2834692223
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.476916841
Short name T281
Test name
Test status
Simulation time 364230342 ps
CPU time 1.16 seconds
Started Aug 07 05:49:03 PM PDT 24
Finished Aug 07 05:49:04 PM PDT 24
Peak memory 191988 kb
Host smart-752603e9-3261-4f51-b38f-d112206cf098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476916841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.476916841
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3909796942
Short name T26
Test name
Test status
Simulation time 24450828617 ps
CPU time 18.78 seconds
Started Aug 07 05:48:33 PM PDT 24
Finished Aug 07 05:48:52 PM PDT 24
Peak memory 192136 kb
Host smart-7d9b767a-bd7f-4b63-ba14-96399ce21dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909796942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3909796942
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3605668972
Short name T15
Test name
Test status
Simulation time 4232131420 ps
CPU time 2.56 seconds
Started Aug 07 05:48:30 PM PDT 24
Finished Aug 07 05:48:33 PM PDT 24
Peak memory 215488 kb
Host smart-dd099ad0-cd83-454c-b562-b9f01eaccc6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605668972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3605668972
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3321103712
Short name T65
Test name
Test status
Simulation time 391393409 ps
CPU time 1.19 seconds
Started Aug 07 05:48:18 PM PDT 24
Finished Aug 07 05:48:20 PM PDT 24
Peak memory 192112 kb
Host smart-ea4e8e00-809f-4550-8f1f-66dbe0d16b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321103712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3321103712
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1897846919
Short name T240
Test name
Test status
Simulation time 27509334709 ps
CPU time 10.03 seconds
Started Aug 07 05:49:06 PM PDT 24
Finished Aug 07 05:49:16 PM PDT 24
Peak memory 192160 kb
Host smart-63ce8752-ca17-4b10-b61a-725a8b970c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897846919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1897846919
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3341757672
Short name T32
Test name
Test status
Simulation time 456428860 ps
CPU time 1.3 seconds
Started Aug 07 05:49:08 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 192096 kb
Host smart-495a2c2c-eaee-439c-8c21-addc0857c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341757672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3341757672
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.643312684
Short name T235
Test name
Test status
Simulation time 7507962701 ps
CPU time 10.7 seconds
Started Aug 07 05:49:04 PM PDT 24
Finished Aug 07 05:49:15 PM PDT 24
Peak memory 197136 kb
Host smart-b10e7488-db20-4997-81f2-ea0c6f1e1db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643312684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.643312684
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3730598743
Short name T213
Test name
Test status
Simulation time 491113929 ps
CPU time 1.38 seconds
Started Aug 07 05:49:06 PM PDT 24
Finished Aug 07 05:49:08 PM PDT 24
Peak memory 192076 kb
Host smart-b54a7cc7-5b82-41cc-8586-2783667b588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730598743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3730598743
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1346860023
Short name T268
Test name
Test status
Simulation time 1071993771 ps
CPU time 2.23 seconds
Started Aug 07 05:49:11 PM PDT 24
Finished Aug 07 05:49:13 PM PDT 24
Peak memory 196780 kb
Host smart-ca796c0e-2337-4356-ab67-eaf4414d1ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346860023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1346860023
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3988555240
Short name T261
Test name
Test status
Simulation time 593485109 ps
CPU time 0.96 seconds
Started Aug 07 05:49:16 PM PDT 24
Finished Aug 07 05:49:17 PM PDT 24
Peak memory 192092 kb
Host smart-21c63abd-86cd-45f1-bb31-31ad509127ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988555240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3988555240
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2223448246
Short name T227
Test name
Test status
Simulation time 10086226793 ps
CPU time 3.95 seconds
Started Aug 07 05:49:12 PM PDT 24
Finished Aug 07 05:49:16 PM PDT 24
Peak memory 192184 kb
Host smart-1192efa8-a19f-4ef6-b7b2-5e31a45e34fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223448246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2223448246
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3139403891
Short name T246
Test name
Test status
Simulation time 456280236 ps
CPU time 0.66 seconds
Started Aug 07 05:49:08 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 196924 kb
Host smart-05a3d452-2afb-4c89-9455-315cdfb93dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139403891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3139403891
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2150706097
Short name T252
Test name
Test status
Simulation time 40765922835 ps
CPU time 14.4 seconds
Started Aug 07 05:49:10 PM PDT 24
Finished Aug 07 05:49:25 PM PDT 24
Peak memory 192164 kb
Host smart-de2c1af4-6dfc-4f87-a1cc-3dbe0630daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150706097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2150706097
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2073909840
Short name T244
Test name
Test status
Simulation time 580543084 ps
CPU time 0.79 seconds
Started Aug 07 05:49:12 PM PDT 24
Finished Aug 07 05:49:13 PM PDT 24
Peak memory 192036 kb
Host smart-e8cf205a-cf82-4877-9c30-a32a4f2db127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073909840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2073909840
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1326335357
Short name T204
Test name
Test status
Simulation time 48764211771 ps
CPU time 32 seconds
Started Aug 07 05:49:18 PM PDT 24
Finished Aug 07 05:49:50 PM PDT 24
Peak memory 192096 kb
Host smart-acfcb234-4e22-4a2a-9caf-bd6e1ec17107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326335357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1326335357
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.626181637
Short name T220
Test name
Test status
Simulation time 509823530 ps
CPU time 0.78 seconds
Started Aug 07 05:49:16 PM PDT 24
Finished Aug 07 05:49:17 PM PDT 24
Peak memory 196896 kb
Host smart-9320b033-ba3a-455e-8f60-1afd887dc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626181637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.626181637
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3407631421
Short name T278
Test name
Test status
Simulation time 10943044951 ps
CPU time 4.87 seconds
Started Aug 07 05:49:16 PM PDT 24
Finished Aug 07 05:49:21 PM PDT 24
Peak memory 192088 kb
Host smart-4edb2a45-eba7-49c6-b4a7-a8538452c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407631421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3407631421
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2869525556
Short name T277
Test name
Test status
Simulation time 376577611 ps
CPU time 1.02 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 192092 kb
Host smart-221e8096-776e-44de-a2ab-4d3cc09dc8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869525556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2869525556
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1968701190
Short name T265
Test name
Test status
Simulation time 53233463957 ps
CPU time 20.04 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 192156 kb
Host smart-d7fd034a-f0e2-42aa-a955-079400ccd7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968701190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1968701190
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2555002416
Short name T217
Test name
Test status
Simulation time 397854990 ps
CPU time 0.7 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:49:20 PM PDT 24
Peak memory 192092 kb
Host smart-ee5a967a-8b92-4d1e-9fbc-db4351fcd489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555002416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2555002416
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4025951925
Short name T191
Test name
Test status
Simulation time 407134793 ps
CPU time 1.23 seconds
Started Aug 07 05:49:21 PM PDT 24
Finished Aug 07 05:49:23 PM PDT 24
Peak memory 197088 kb
Host smart-d983bb1e-d97d-42bd-b2d6-9b188da193d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025951925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4025951925
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.680594286
Short name T212
Test name
Test status
Simulation time 13865807139 ps
CPU time 6.5 seconds
Started Aug 07 05:49:18 PM PDT 24
Finished Aug 07 05:49:25 PM PDT 24
Peak memory 192144 kb
Host smart-99240a14-ef76-45f9-8a88-a6bde383862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680594286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.680594286
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1533713908
Short name T255
Test name
Test status
Simulation time 405286300 ps
CPU time 0.94 seconds
Started Aug 07 05:49:20 PM PDT 24
Finished Aug 07 05:49:21 PM PDT 24
Peak memory 196896 kb
Host smart-e8194d9c-ff02-4c0c-b6aa-c49bc8c281ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533713908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1533713908
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2817822257
Short name T194
Test name
Test status
Simulation time 487280044 ps
CPU time 1.3 seconds
Started Aug 07 05:49:23 PM PDT 24
Finished Aug 07 05:49:25 PM PDT 24
Peak memory 196908 kb
Host smart-33f40a5f-df62-423b-b712-056e6de13e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817822257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2817822257
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2913952176
Short name T263
Test name
Test status
Simulation time 18003740061 ps
CPU time 24.13 seconds
Started Aug 07 05:49:23 PM PDT 24
Finished Aug 07 05:49:48 PM PDT 24
Peak memory 192184 kb
Host smart-adade7e3-d6a7-474e-9132-0c18f9a29303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913952176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2913952176
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1046047818
Short name T221
Test name
Test status
Simulation time 481471357 ps
CPU time 0.74 seconds
Started Aug 07 05:49:22 PM PDT 24
Finished Aug 07 05:49:23 PM PDT 24
Peak memory 192092 kb
Host smart-90bc4423-8f38-428e-898f-adfd08d0903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046047818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1046047818
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3685874839
Short name T203
Test name
Test status
Simulation time 34497627635 ps
CPU time 56.55 seconds
Started Aug 07 05:48:25 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 192136 kb
Host smart-68214cec-3cae-4721-86fd-bedbff22519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685874839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3685874839
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4059302267
Short name T13
Test name
Test status
Simulation time 4398033808 ps
CPU time 7.18 seconds
Started Aug 07 05:48:26 PM PDT 24
Finished Aug 07 05:48:33 PM PDT 24
Peak memory 215700 kb
Host smart-73aa0aab-989d-4e80-9616-5ace4bb760d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059302267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4059302267
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1312820641
Short name T61
Test name
Test status
Simulation time 462007861 ps
CPU time 1.25 seconds
Started Aug 07 05:48:25 PM PDT 24
Finished Aug 07 05:48:27 PM PDT 24
Peak memory 192096 kb
Host smart-a4fc154e-c2db-4738-a61a-fb1e99ffa7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312820641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1312820641
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.379311838
Short name T239
Test name
Test status
Simulation time 50979683749 ps
CPU time 74.15 seconds
Started Aug 07 05:49:23 PM PDT 24
Finished Aug 07 05:50:38 PM PDT 24
Peak memory 192140 kb
Host smart-44e01e02-8f96-4db3-8bc8-a0a5046bbb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379311838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.379311838
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2297827185
Short name T208
Test name
Test status
Simulation time 474008209 ps
CPU time 0.74 seconds
Started Aug 07 05:49:19 PM PDT 24
Finished Aug 07 05:49:20 PM PDT 24
Peak memory 192072 kb
Host smart-7c1733a9-180c-4ade-8174-35a517f03e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297827185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2297827185
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3066854384
Short name T272
Test name
Test status
Simulation time 433551294265 ps
CPU time 124.29 seconds
Started Aug 07 05:49:18 PM PDT 24
Finished Aug 07 05:51:22 PM PDT 24
Peak memory 198324 kb
Host smart-e0c3c8b1-ba5e-483b-ada5-659db2ca311d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066854384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3066854384
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.733560969
Short name T48
Test name
Test status
Simulation time 37487040131 ps
CPU time 28.51 seconds
Started Aug 07 05:49:24 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 197160 kb
Host smart-8cdb0d37-84f2-4aa2-b619-344d67f39333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733560969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.733560969
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1862004897
Short name T257
Test name
Test status
Simulation time 484432019 ps
CPU time 1.33 seconds
Started Aug 07 05:49:22 PM PDT 24
Finished Aug 07 05:49:23 PM PDT 24
Peak memory 197000 kb
Host smart-a6bac4d0-e5ed-41e4-a33d-5a576b75a665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862004897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1862004897
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1651884279
Short name T231
Test name
Test status
Simulation time 25471294205 ps
CPU time 38.95 seconds
Started Aug 07 05:49:23 PM PDT 24
Finished Aug 07 05:50:02 PM PDT 24
Peak memory 192172 kb
Host smart-e8892bef-490c-424e-b98b-6090fb67cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651884279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1651884279
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.482649476
Short name T209
Test name
Test status
Simulation time 466152657 ps
CPU time 0.72 seconds
Started Aug 07 05:49:25 PM PDT 24
Finished Aug 07 05:49:25 PM PDT 24
Peak memory 196956 kb
Host smart-a82329d5-544b-41f1-bc2b-e6ae66b8dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482649476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.482649476
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3998935088
Short name T238
Test name
Test status
Simulation time 31331347726 ps
CPU time 10.54 seconds
Started Aug 07 05:49:26 PM PDT 24
Finished Aug 07 05:49:36 PM PDT 24
Peak memory 197164 kb
Host smart-b4610232-6cc3-4d13-8cf6-517779ab00f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998935088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3998935088
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2593972442
Short name T283
Test name
Test status
Simulation time 461542561 ps
CPU time 0.71 seconds
Started Aug 07 05:49:27 PM PDT 24
Finished Aug 07 05:49:28 PM PDT 24
Peak memory 196912 kb
Host smart-6738088e-52ad-4e91-b921-66c9c732595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593972442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2593972442
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2340794230
Short name T214
Test name
Test status
Simulation time 21761038629 ps
CPU time 33.39 seconds
Started Aug 07 05:49:24 PM PDT 24
Finished Aug 07 05:49:58 PM PDT 24
Peak memory 192216 kb
Host smart-9c25533a-eb69-4b7f-8537-bfea15b14dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340794230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2340794230
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3131678744
Short name T243
Test name
Test status
Simulation time 514282144 ps
CPU time 0.72 seconds
Started Aug 07 05:49:24 PM PDT 24
Finished Aug 07 05:49:25 PM PDT 24
Peak memory 192056 kb
Host smart-d228d9d1-9de9-451e-8e01-4a4108387af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131678744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3131678744
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.388188448
Short name T233
Test name
Test status
Simulation time 8883695451 ps
CPU time 13.98 seconds
Started Aug 07 05:49:30 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 192172 kb
Host smart-e2154d57-be66-4f34-89ad-0468d8be8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388188448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.388188448
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1861188360
Short name T9
Test name
Test status
Simulation time 517899945 ps
CPU time 0.74 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 05:49:37 PM PDT 24
Peak memory 192044 kb
Host smart-3cc18631-2ff6-43ce-8b10-591dbfd281e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861188360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1861188360
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2230514160
Short name T270
Test name
Test status
Simulation time 10808619531 ps
CPU time 4.78 seconds
Started Aug 07 05:49:34 PM PDT 24
Finished Aug 07 05:49:39 PM PDT 24
Peak memory 197112 kb
Host smart-ecbf071a-e7cc-4d9f-8900-95c51ae7ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230514160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2230514160
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3681168568
Short name T59
Test name
Test status
Simulation time 618509330 ps
CPU time 0.67 seconds
Started Aug 07 05:49:35 PM PDT 24
Finished Aug 07 05:49:36 PM PDT 24
Peak memory 196852 kb
Host smart-d0e61d3e-3496-4706-937d-47a9e2bd12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681168568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3681168568
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2607282992
Short name T232
Test name
Test status
Simulation time 15898521034 ps
CPU time 24.8 seconds
Started Aug 07 05:49:30 PM PDT 24
Finished Aug 07 05:49:55 PM PDT 24
Peak memory 192156 kb
Host smart-30403105-fe8e-46f6-a88d-006e14004b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607282992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2607282992
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1716115555
Short name T64
Test name
Test status
Simulation time 413047169 ps
CPU time 0.69 seconds
Started Aug 07 05:49:32 PM PDT 24
Finished Aug 07 05:49:33 PM PDT 24
Peak memory 192072 kb
Host smart-0bf0e332-9588-4946-b685-63e5ebb1a9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716115555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1716115555
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.320785655
Short name T245
Test name
Test status
Simulation time 15406032593 ps
CPU time 22.89 seconds
Started Aug 07 05:49:31 PM PDT 24
Finished Aug 07 05:49:54 PM PDT 24
Peak memory 192100 kb
Host smart-e65e63c4-7639-4776-b7ff-8685d156bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320785655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.320785655
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.777988693
Short name T264
Test name
Test status
Simulation time 501888550 ps
CPU time 0.96 seconds
Started Aug 07 05:49:30 PM PDT 24
Finished Aug 07 05:49:31 PM PDT 24
Peak memory 192092 kb
Host smart-00f71281-ad19-4bd7-8224-8f2471407955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777988693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.777988693
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2820180016
Short name T249
Test name
Test status
Simulation time 16959389167 ps
CPU time 5.76 seconds
Started Aug 07 05:49:35 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 192128 kb
Host smart-729a588d-34c8-4d09-88d2-d63351ce63c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820180016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2820180016
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1272583517
Short name T222
Test name
Test status
Simulation time 412592064 ps
CPU time 0.88 seconds
Started Aug 07 05:49:36 PM PDT 24
Finished Aug 07 05:49:37 PM PDT 24
Peak memory 192060 kb
Host smart-a430fdfa-b774-4d6b-bf0f-1ecc0d6903ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272583517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1272583517
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.876263468
Short name T282
Test name
Test status
Simulation time 27314028025 ps
CPU time 37.52 seconds
Started Aug 07 05:48:29 PM PDT 24
Finished Aug 07 05:49:06 PM PDT 24
Peak memory 197156 kb
Host smart-68dbfc56-1ea9-4419-8946-14fdedb5e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876263468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.876263468
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1296693642
Short name T256
Test name
Test status
Simulation time 393989168 ps
CPU time 0.91 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:49:44 PM PDT 24
Peak memory 192060 kb
Host smart-aa878c11-e3f9-48a7-bf47-9e213eaa92f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296693642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1296693642
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.98883998
Short name T225
Test name
Test status
Simulation time 96217774106 ps
CPU time 10.57 seconds
Started Aug 07 05:48:27 PM PDT 24
Finished Aug 07 05:48:38 PM PDT 24
Peak memory 198472 kb
Host smart-f47f23a9-6b35-4ea5-85a5-2a3b82af2da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98883998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all
.98883998
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4155415763
Short name T262
Test name
Test status
Simulation time 40534693848 ps
CPU time 51.26 seconds
Started Aug 07 05:48:25 PM PDT 24
Finished Aug 07 05:49:17 PM PDT 24
Peak memory 197148 kb
Host smart-06dcb91f-f2c4-4bbe-b921-febfb6232d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155415763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4155415763
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1970848197
Short name T230
Test name
Test status
Simulation time 338856130 ps
CPU time 0.79 seconds
Started Aug 07 05:48:25 PM PDT 24
Finished Aug 07 05:48:26 PM PDT 24
Peak memory 196888 kb
Host smart-bdff90a2-abfc-4939-a040-de9743328ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970848197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1970848197
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1686263289
Short name T234
Test name
Test status
Simulation time 1759502819 ps
CPU time 2.01 seconds
Started Aug 07 05:48:28 PM PDT 24
Finished Aug 07 05:48:30 PM PDT 24
Peak memory 192068 kb
Host smart-8f51a6b7-e11f-44c5-99d4-f49cba6af425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686263289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1686263289
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.726636384
Short name T210
Test name
Test status
Simulation time 483287357 ps
CPU time 0.9 seconds
Started Aug 07 05:48:24 PM PDT 24
Finished Aug 07 05:48:25 PM PDT 24
Peak memory 192088 kb
Host smart-835d98c1-6c45-4b46-9132-852d4453b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726636384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.726636384
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.345462563
Short name T47
Test name
Test status
Simulation time 28825249011 ps
CPU time 7.86 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:48:47 PM PDT 24
Peak memory 192188 kb
Host smart-0ba73381-ad9f-464d-a389-e9fb203edb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345462563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.345462563
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.621104875
Short name T236
Test name
Test status
Simulation time 547876150 ps
CPU time 0.62 seconds
Started Aug 07 05:48:40 PM PDT 24
Finished Aug 07 05:48:41 PM PDT 24
Peak memory 192308 kb
Host smart-845ee026-e5b2-4468-9dba-f506af4ada34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621104875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.621104875
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4236689208
Short name T183
Test name
Test status
Simulation time 480529738 ps
CPU time 0.82 seconds
Started Aug 07 05:48:34 PM PDT 24
Finished Aug 07 05:48:35 PM PDT 24
Peak memory 196864 kb
Host smart-56594003-2fa5-4f1c-aa54-837ad632ebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236689208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4236689208
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.758804745
Short name T45
Test name
Test status
Simulation time 5512953754 ps
CPU time 8.72 seconds
Started Aug 07 05:48:28 PM PDT 24
Finished Aug 07 05:48:37 PM PDT 24
Peak memory 192112 kb
Host smart-922402fb-e7b5-405a-ad09-0f74afadf76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758804745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.758804745
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2417412277
Short name T207
Test name
Test status
Simulation time 380745305 ps
CPU time 1.17 seconds
Started Aug 07 05:48:39 PM PDT 24
Finished Aug 07 05:48:41 PM PDT 24
Peak memory 197156 kb
Host smart-0d22edbb-62a8-4575-a2b9-3ede1496c6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417412277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2417412277
Directory /workspace/9.aon_timer_smoke/latest
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