Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 32362 1 T1 212 T2 12 T3 136
bark[1] 395 1 T1 14 T10 14 T11 21
bark[2] 463 1 T35 39 T180 14 T147 26
bark[3] 635 1 T7 54 T137 14 T20 5
bark[4] 432 1 T35 30 T92 21 T96 26
bark[5] 2438 1 T5 21 T7 21 T10 51
bark[6] 767 1 T103 21 T147 217 T72 107
bark[7] 955 1 T10 30 T20 331 T106 42
bark[8] 555 1 T4 107 T11 21 T26 21
bark[9] 358 1 T1 21 T36 26 T148 14
bark[10] 481 1 T11 21 T47 14 T36 141
bark[11] 219 1 T38 21 T77 21 T170 21
bark[12] 440 1 T40 30 T20 40 T113 21
bark[13] 318 1 T10 21 T26 173 T37 21
bark[14] 434 1 T4 21 T11 21 T186 14
bark[15] 1195 1 T7 21 T11 481 T96 21
bark[16] 241 1 T165 14 T78 21 T71 21
bark[17] 831 1 T4 218 T11 200 T36 26
bark[18] 1114 1 T3 26 T5 26 T7 26
bark[19] 576 1 T24 85 T72 30 T80 135
bark[20] 548 1 T1 21 T3 87 T26 68
bark[21] 588 1 T5 14 T9 14 T145 14
bark[22] 529 1 T1 30 T5 21 T183 14
bark[23] 361 1 T38 21 T140 21 T106 21
bark[24] 278 1 T147 21 T158 14 T76 69
bark[25] 514 1 T43 14 T124 21 T144 21
bark[26] 726 1 T10 30 T35 26 T77 7
bark[27] 282 1 T48 21 T78 21 T156 14
bark[28] 681 1 T5 244 T130 26 T173 14
bark[29] 295 1 T10 30 T36 21 T147 209
bark[30] 309 1 T7 35 T48 30 T38 77
bark[31] 1009 1 T10 26 T26 240 T96 21
bark_0 4856 1 T1 7 T2 7 T3 16


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 31943 1 T1 233 T2 11 T3 136
bite[1] 494 1 T26 172 T106 42 T124 21
bite[2] 2646 1 T36 25 T20 295 T128 50
bite[3] 1517 1 T11 480 T36 25 T72 821
bite[4] 288 1 T1 30 T39 25 T101 13
bite[5] 768 1 T4 106 T10 30 T71 21
bite[6] 360 1 T183 13 T186 13 T40 30
bite[7] 628 1 T4 21 T44 21 T148 35
bite[8] 707 1 T26 59 T22 21 T106 21
bite[9] 831 1 T10 43 T26 239 T36 140
bite[10] 589 1 T9 13 T11 21 T103 131
bite[11] 453 1 T10 26 T11 199 T38 21
bite[12] 273 1 T7 32 T10 30 T26 67
bite[13] 523 1 T77 6 T78 21 T24 84
bite[14] 207 1 T11 42 T92 21 T113 21
bite[15] 805 1 T4 217 T35 30 T113 21
bite[16] 651 1 T6 13 T77 34 T167 13
bite[17] 649 1 T5 21 T7 26 T11 21
bite[18] 581 1 T35 39 T38 76 T130 21
bite[19] 372 1 T3 26 T35 25 T136 13
bite[20] 252 1 T5 21 T7 56 T174 27
bite[21] 202 1 T43 13 T137 13 T77 21
bite[22] 508 1 T10 21 T48 21 T37 214
bite[23] 798 1 T11 139 T145 13 T147 216
bite[24] 810 1 T5 243 T7 21 T140 39
bite[25] 336 1 T10 21 T96 26 T112 21
bite[26] 471 1 T1 13 T39 63 T113 47
bite[27] 290 1 T1 21 T5 26 T7 21
bite[28] 632 1 T10 30 T11 21 T48 30
bite[29] 453 1 T3 47 T170 21 T20 4
bite[30] 137 1 T47 13 T128 40 T177 21
bite[31] 658 1 T3 39 T26 21 T36 21
bite_0 5353 1 T1 8 T2 8 T3 17


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 44814 1 T1 176 T2 19 T3 246
auto[1] 11371 1 T1 129 T3 19 T4 224


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1125 1 T5 140 T26 216 T37 2
prescale[1] 1181 1 T11 139 T35 74 T38 124
prescale[2] 1199 1 T26 52 T35 2 T36 50
prescale[3] 1002 1 T5 19 T140 19 T45 9
prescale[4] 1480 1 T5 363 T26 59 T37 2
prescale[5] 1080 1 T4 110 T5 72 T11 112
prescale[6] 932 1 T1 38 T4 2 T7 19
prescale[7] 861 1 T11 19 T35 24 T92 24
prescale[8] 1140 1 T11 118 T26 53 T36 2
prescale[9] 687 1 T5 23 T7 41 T11 19
prescale[10] 850 1 T4 19 T5 19 T11 95
prescale[11] 743 1 T26 49 T36 2 T24 19
prescale[12] 892 1 T11 173 T26 40 T36 2
prescale[13] 1135 1 T26 24 T36 19 T130 14
prescale[14] 676 1 T10 23 T11 19 T26 97
prescale[15] 1135 1 T1 28 T11 62 T46 9
prescale[16] 870 1 T5 181 T35 40 T37 45
prescale[17] 724 1 T5 9 T26 97 T103 2
prescale[18] 549 1 T1 49 T10 28 T37 2
prescale[19] 887 1 T3 49 T11 14 T35 90
prescale[20] 1071 1 T2 9 T5 24 T41 9
prescale[21] 1062 1 T4 86 T5 104 T7 9
prescale[22] 907 1 T26 4 T37 19 T78 138
prescale[23] 867 1 T4 21 T35 104 T37 2
prescale[24] 1102 1 T3 19 T4 71 T11 83
prescale[25] 446 1 T4 47 T5 19 T36 2
prescale[26] 550 1 T26 2 T35 41 T37 72
prescale[27] 719 1 T11 82 T26 19 T35 2
prescale[28] 827 1 T5 103 T7 23 T11 62
prescale[29] 1015 1 T4 117 T35 2 T37 76
prescale[30] 1118 1 T4 19 T5 36 T26 19
prescale[31] 817 1 T3 45 T5 40 T38 2
prescale_0 26536 1 T1 190 T2 10 T3 152


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42297 1 T1 169 T2 19 T3 165
auto[1] 13888 1 T1 136 T3 100 T4 114


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 56185 1 T1 305 T2 19 T3 265


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 33090 1 T1 157 T2 14 T3 137
wkup[1] 182 1 T35 21 T78 21 T73 21
wkup[2] 248 1 T5 21 T7 21 T10 30
wkup[3] 335 1 T5 21 T35 15 T38 21
wkup[4] 283 1 T5 21 T10 21 T11 21
wkup[5] 349 1 T4 21 T11 42 T38 26
wkup[6] 196 1 T5 72 T36 21 T78 21
wkup[7] 230 1 T11 47 T39 21 T147 21
wkup[8] 389 1 T3 21 T35 35 T77 21
wkup[9] 234 1 T4 21 T5 21 T78 26
wkup[10] 473 1 T5 35 T165 15 T37 21
wkup[11] 233 1 T26 21 T36 8 T78 21
wkup[12] 327 1 T3 26 T26 21 T36 21
wkup[13] 274 1 T11 21 T40 47 T78 21
wkup[14] 218 1 T4 21 T5 30 T36 21
wkup[15] 219 1 T4 21 T38 63 T160 21
wkup[16] 254 1 T5 21 T78 21 T20 21
wkup[17] 317 1 T5 21 T11 21 T37 42
wkup[18] 449 1 T5 26 T26 42 T48 21
wkup[19] 254 1 T4 42 T7 21 T35 42
wkup[20] 280 1 T5 21 T78 42 T170 21
wkup[21] 453 1 T4 39 T37 21 T38 21
wkup[22] 459 1 T4 21 T5 36 T96 21
wkup[23] 355 1 T4 24 T36 35 T20 42
wkup[24] 287 1 T5 21 T10 30 T11 21
wkup[25] 185 1 T103 39 T124 21 T80 15
wkup[26] 296 1 T92 21 T36 21 T77 21
wkup[27] 218 1 T35 21 T40 15 T103 30
wkup[28] 356 1 T11 44 T26 21 T48 21
wkup[29] 155 1 T5 15 T44 21 T78 21
wkup[30] 217 1 T124 21 T72 42 T109 26
wkup[31] 114 1 T5 21 T7 21 T26 21
wkup[32] 314 1 T4 51 T26 15 T77 21
wkup[33] 268 1 T5 21 T7 21 T137 15
wkup[34] 225 1 T5 26 T10 21 T26 31
wkup[35] 363 1 T11 21 T43 15 T40 21
wkup[36] 334 1 T10 30 T11 21 T44 44
wkup[37] 209 1 T11 44 T130 26 T103 26
wkup[38] 407 1 T37 15 T77 30 T101 15
wkup[39] 252 1 T4 26 T26 30 T96 21
wkup[40] 457 1 T1 30 T4 21 T11 47
wkup[41] 390 1 T5 21 T11 15 T26 21
wkup[42] 254 1 T5 26 T38 21 T77 21
wkup[43] 473 1 T26 35 T35 30 T39 21
wkup[44] 329 1 T3 20 T5 21 T38 42
wkup[45] 218 1 T5 42 T44 21 T147 21
wkup[46] 284 1 T3 21 T38 30 T22 21
wkup[47] 300 1 T11 42 T183 15 T113 21
wkup[48] 309 1 T1 21 T3 26 T11 42
wkup[49] 241 1 T1 26 T26 21 T78 21
wkup[50] 462 1 T5 42 T7 26 T26 21
wkup[51] 279 1 T5 21 T9 15 T35 26
wkup[52] 371 1 T4 21 T26 21 T36 39
wkup[53] 239 1 T92 42 T37 21 T38 8
wkup[54] 401 1 T1 30 T10 30 T26 21
wkup[55] 376 1 T5 34 T11 26 T44 26
wkup[56] 342 1 T11 21 T26 21 T96 26
wkup[57] 296 1 T1 21 T78 26 T132 26
wkup[58] 330 1 T11 21 T26 47 T38 21
wkup[59] 473 1 T6 15 T10 26 T26 62
wkup[60] 381 1 T1 15 T47 15 T48 45
wkup[61] 269 1 T11 21 T186 15 T20 15
wkup[62] 316 1 T4 21 T7 35 T37 26
wkup[63] 335 1 T4 21 T5 21 T10 15
wkup_0 3759 1 T1 5 T2 5 T3 14

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