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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.53 99.33 93.67 100.00 98.40 99.51 52.27


Total test records in report: 426
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T285 /workspace/coverage/default/38.aon_timer_prescaler.1260154206 Aug 08 05:16:38 PM PDT 24 Aug 08 05:16:45 PM PDT 24 34727837588 ps
T33 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2536234294 Aug 08 04:25:19 PM PDT 24 Aug 08 04:25:20 PM PDT 24 362540400 ps
T27 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3552284332 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:50 PM PDT 24 1377603889 ps
T286 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.876075692 Aug 08 04:22:32 PM PDT 24 Aug 08 04:22:32 PM PDT 24 367509938 ps
T287 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4059808216 Aug 08 04:26:53 PM PDT 24 Aug 08 04:26:54 PM PDT 24 290906859 ps
T34 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4068611905 Aug 08 04:24:22 PM PDT 24 Aug 08 04:24:24 PM PDT 24 950486233 ps
T288 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3405190607 Aug 08 04:23:52 PM PDT 24 Aug 08 04:23:53 PM PDT 24 296869916 ps
T289 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1708863644 Aug 08 04:26:05 PM PDT 24 Aug 08 04:26:05 PM PDT 24 339396036 ps
T28 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4001960436 Aug 08 04:26:20 PM PDT 24 Aug 08 04:26:21 PM PDT 24 530695238 ps
T63 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1675879067 Aug 08 04:26:45 PM PDT 24 Aug 08 04:26:46 PM PDT 24 476202472 ps
T29 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.854891274 Aug 08 04:27:06 PM PDT 24 Aug 08 04:27:07 PM PDT 24 433007867 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2278232756 Aug 08 04:24:37 PM PDT 24 Aug 08 04:24:38 PM PDT 24 404113221 ps
T30 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.591602422 Aug 08 04:23:21 PM PDT 24 Aug 08 04:23:29 PM PDT 24 4313721136 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.856650358 Aug 08 04:25:31 PM PDT 24 Aug 08 04:25:32 PM PDT 24 529326145 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4158234691 Aug 08 04:23:45 PM PDT 24 Aug 08 04:23:46 PM PDT 24 362102343 ps
T64 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1003600753 Aug 08 04:27:09 PM PDT 24 Aug 08 04:27:10 PM PDT 24 1426985781 ps
T196 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.349986344 Aug 08 04:26:54 PM PDT 24 Aug 08 04:26:56 PM PDT 24 385006197 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3569597097 Aug 08 04:23:54 PM PDT 24 Aug 08 04:23:55 PM PDT 24 439240467 ps
T294 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1906140665 Aug 08 04:24:03 PM PDT 24 Aug 08 04:24:04 PM PDT 24 456228686 ps
T51 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1800292888 Aug 08 04:24:25 PM PDT 24 Aug 08 04:24:26 PM PDT 24 362918655 ps
T31 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.337693238 Aug 08 04:26:11 PM PDT 24 Aug 08 04:26:22 PM PDT 24 8081212209 ps
T295 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3685287027 Aug 08 04:26:16 PM PDT 24 Aug 08 04:26:18 PM PDT 24 592158029 ps
T296 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3816280759 Aug 08 04:26:53 PM PDT 24 Aug 08 04:26:55 PM PDT 24 478205607 ps
T297 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4169248424 Aug 08 04:21:53 PM PDT 24 Aug 08 04:21:54 PM PDT 24 418509700 ps
T298 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3322545446 Aug 08 04:26:17 PM PDT 24 Aug 08 04:26:18 PM PDT 24 499239987 ps
T299 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2758469275 Aug 08 04:23:51 PM PDT 24 Aug 08 04:23:52 PM PDT 24 513267928 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.351849701 Aug 08 04:23:10 PM PDT 24 Aug 08 04:23:11 PM PDT 24 452248963 ps
T52 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3665022993 Aug 08 04:23:08 PM PDT 24 Aug 08 04:23:09 PM PDT 24 289233940 ps
T301 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.284752900 Aug 08 04:26:17 PM PDT 24 Aug 08 04:26:19 PM PDT 24 564707676 ps
T32 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2343749337 Aug 08 04:27:03 PM PDT 24 Aug 08 04:27:06 PM PDT 24 4036041626 ps
T53 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2384525076 Aug 08 04:22:37 PM PDT 24 Aug 08 04:22:53 PM PDT 24 10289338068 ps
T302 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4165842666 Aug 08 04:23:18 PM PDT 24 Aug 08 04:23:20 PM PDT 24 434020790 ps
T65 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.674777427 Aug 08 04:23:52 PM PDT 24 Aug 08 04:23:54 PM PDT 24 1472028393 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2532474973 Aug 08 04:26:04 PM PDT 24 Aug 08 04:26:05 PM PDT 24 570246741 ps
T304 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1036873406 Aug 08 04:23:11 PM PDT 24 Aug 08 04:23:13 PM PDT 24 607106127 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3293096336 Aug 08 04:23:45 PM PDT 24 Aug 08 04:23:49 PM PDT 24 605096265 ps
T306 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4126389197 Aug 08 04:22:12 PM PDT 24 Aug 08 04:22:13 PM PDT 24 596692496 ps
T191 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1282128449 Aug 08 04:23:21 PM PDT 24 Aug 08 04:23:28 PM PDT 24 8372452498 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1794973205 Aug 08 04:23:54 PM PDT 24 Aug 08 04:23:55 PM PDT 24 508309170 ps
T66 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1035113684 Aug 08 04:26:14 PM PDT 24 Aug 08 04:26:22 PM PDT 24 2768948509 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3936041174 Aug 08 04:21:38 PM PDT 24 Aug 08 04:21:40 PM PDT 24 389524754 ps
T309 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3170694978 Aug 08 04:26:47 PM PDT 24 Aug 08 04:26:48 PM PDT 24 316620394 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2435959319 Aug 08 04:21:57 PM PDT 24 Aug 08 04:21:58 PM PDT 24 408353795 ps
T311 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1275685038 Aug 08 04:26:20 PM PDT 24 Aug 08 04:26:21 PM PDT 24 294274730 ps
T67 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4051062812 Aug 08 04:25:08 PM PDT 24 Aug 08 04:25:09 PM PDT 24 345043935 ps
T192 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.302404545 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:38 PM PDT 24 7585157077 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2260760728 Aug 08 04:26:31 PM PDT 24 Aug 08 04:26:32 PM PDT 24 436654502 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.808997001 Aug 08 04:23:10 PM PDT 24 Aug 08 04:23:11 PM PDT 24 315859843 ps
T313 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.170388310 Aug 08 04:22:20 PM PDT 24 Aug 08 04:22:21 PM PDT 24 304466908 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1954628712 Aug 08 04:26:28 PM PDT 24 Aug 08 04:26:29 PM PDT 24 465742546 ps
T315 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1975236446 Aug 08 04:26:20 PM PDT 24 Aug 08 04:26:21 PM PDT 24 331906016 ps
T316 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2707332637 Aug 08 04:26:42 PM PDT 24 Aug 08 04:26:43 PM PDT 24 471347347 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1440971783 Aug 08 04:24:06 PM PDT 24 Aug 08 04:24:07 PM PDT 24 458542492 ps
T69 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3007988652 Aug 08 04:24:16 PM PDT 24 Aug 08 04:24:18 PM PDT 24 1327553381 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3021944681 Aug 08 04:27:07 PM PDT 24 Aug 08 04:27:08 PM PDT 24 1585904026 ps
T317 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2881312354 Aug 08 04:24:34 PM PDT 24 Aug 08 04:24:35 PM PDT 24 435500501 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1949850388 Aug 08 04:23:34 PM PDT 24 Aug 08 04:23:35 PM PDT 24 303989973 ps
T319 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.478788299 Aug 08 04:23:52 PM PDT 24 Aug 08 04:23:52 PM PDT 24 410250619 ps
T320 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4211727337 Aug 08 04:25:19 PM PDT 24 Aug 08 04:25:36 PM PDT 24 14061239736 ps
T321 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1218540187 Aug 08 04:27:40 PM PDT 24 Aug 08 04:27:41 PM PDT 24 370606655 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.714149715 Aug 08 04:24:12 PM PDT 24 Aug 08 04:24:13 PM PDT 24 409596967 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2756483231 Aug 08 04:21:38 PM PDT 24 Aug 08 04:21:58 PM PDT 24 7203599196 ps
T324 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3433911872 Aug 08 04:26:19 PM PDT 24 Aug 08 04:26:20 PM PDT 24 323280110 ps
T195 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2026406020 Aug 08 04:27:16 PM PDT 24 Aug 08 04:27:21 PM PDT 24 8451847026 ps
T325 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1598109133 Aug 08 04:27:09 PM PDT 24 Aug 08 04:27:12 PM PDT 24 593601146 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1892308401 Aug 08 04:21:37 PM PDT 24 Aug 08 04:21:41 PM PDT 24 8706554947 ps
T327 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1312903481 Aug 08 04:24:38 PM PDT 24 Aug 08 04:24:41 PM PDT 24 4448426968 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4085560452 Aug 08 04:26:52 PM PDT 24 Aug 08 04:26:53 PM PDT 24 490650097 ps
T329 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2102925940 Aug 08 04:23:00 PM PDT 24 Aug 08 04:23:06 PM PDT 24 1670295771 ps
T330 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.833613426 Aug 08 04:23:02 PM PDT 24 Aug 08 04:23:04 PM PDT 24 454858478 ps
T193 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.278872398 Aug 08 04:23:09 PM PDT 24 Aug 08 04:23:23 PM PDT 24 8418606413 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3876284682 Aug 08 04:26:33 PM PDT 24 Aug 08 04:26:33 PM PDT 24 390716688 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3336273542 Aug 08 04:22:11 PM PDT 24 Aug 08 04:22:13 PM PDT 24 391467749 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3931396659 Aug 08 04:24:37 PM PDT 24 Aug 08 04:24:39 PM PDT 24 325825695 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1256856319 Aug 08 04:27:02 PM PDT 24 Aug 08 04:27:06 PM PDT 24 445784441 ps
T335 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4020590264 Aug 08 04:24:56 PM PDT 24 Aug 08 04:25:03 PM PDT 24 4197888889 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1240897563 Aug 08 04:22:51 PM PDT 24 Aug 08 04:22:51 PM PDT 24 547878935 ps
T337 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2447161018 Aug 08 04:26:35 PM PDT 24 Aug 08 04:26:36 PM PDT 24 397765739 ps
T338 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3940662902 Aug 08 04:22:38 PM PDT 24 Aug 08 04:22:42 PM PDT 24 2046292334 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3883115171 Aug 08 04:23:41 PM PDT 24 Aug 08 04:23:41 PM PDT 24 369021899 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2191962388 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:57 PM PDT 24 7981468820 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2893772914 Aug 08 04:21:37 PM PDT 24 Aug 08 04:21:39 PM PDT 24 890604246 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3616469695 Aug 08 04:21:55 PM PDT 24 Aug 08 04:21:58 PM PDT 24 360611660 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2755493368 Aug 08 04:22:05 PM PDT 24 Aug 08 04:22:07 PM PDT 24 464674803 ps
T343 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3013084428 Aug 08 04:21:58 PM PDT 24 Aug 08 04:21:59 PM PDT 24 371361074 ps
T344 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.887273688 Aug 08 04:23:36 PM PDT 24 Aug 08 04:23:37 PM PDT 24 534581554 ps
T345 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2695873697 Aug 08 04:28:08 PM PDT 24 Aug 08 04:28:09 PM PDT 24 673925898 ps
T346 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.799966656 Aug 08 04:22:40 PM PDT 24 Aug 08 04:22:42 PM PDT 24 593171990 ps
T347 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3847500043 Aug 08 04:22:05 PM PDT 24 Aug 08 04:22:06 PM PDT 24 517541176 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1302336087 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:50 PM PDT 24 512970889 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1095744619 Aug 08 04:25:08 PM PDT 24 Aug 08 04:25:10 PM PDT 24 853262035 ps
T350 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.512046203 Aug 08 04:26:56 PM PDT 24 Aug 08 04:26:57 PM PDT 24 486671083 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.92371260 Aug 08 04:22:05 PM PDT 24 Aug 08 04:22:07 PM PDT 24 455703783 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2247208096 Aug 08 04:27:04 PM PDT 24 Aug 08 04:27:05 PM PDT 24 1758007112 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3864495084 Aug 08 04:22:34 PM PDT 24 Aug 08 04:22:35 PM PDT 24 461606152 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.692271457 Aug 08 04:23:42 PM PDT 24 Aug 08 04:23:43 PM PDT 24 508397520 ps
T354 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1876198048 Aug 08 04:22:55 PM PDT 24 Aug 08 04:22:59 PM PDT 24 9196950804 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4111123520 Aug 08 04:23:22 PM PDT 24 Aug 08 04:23:24 PM PDT 24 690649714 ps
T356 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2675907477 Aug 08 04:25:09 PM PDT 24 Aug 08 04:25:10 PM PDT 24 505987193 ps
T357 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.119077437 Aug 08 04:27:58 PM PDT 24 Aug 08 04:27:59 PM PDT 24 473914516 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3607949300 Aug 08 04:24:33 PM PDT 24 Aug 08 04:24:35 PM PDT 24 486410555 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.691772890 Aug 08 04:27:16 PM PDT 24 Aug 08 04:27:20 PM PDT 24 4352475728 ps
T360 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2858946546 Aug 08 04:23:36 PM PDT 24 Aug 08 04:23:39 PM PDT 24 2486087148 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2403011381 Aug 08 04:26:05 PM PDT 24 Aug 08 04:26:06 PM PDT 24 517915827 ps
T362 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.763028912 Aug 08 04:26:18 PM PDT 24 Aug 08 04:26:20 PM PDT 24 509865833 ps
T363 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.481791727 Aug 08 04:22:31 PM PDT 24 Aug 08 04:22:32 PM PDT 24 401151883 ps
T58 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2343087039 Aug 08 04:24:46 PM PDT 24 Aug 08 04:24:47 PM PDT 24 405069443 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3182655766 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:50 PM PDT 24 364322154 ps
T365 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2938777025 Aug 08 04:21:45 PM PDT 24 Aug 08 04:21:49 PM PDT 24 4132493377 ps
T366 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.414535196 Aug 08 04:25:16 PM PDT 24 Aug 08 04:25:17 PM PDT 24 1078089068 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.188524747 Aug 08 04:24:51 PM PDT 24 Aug 08 04:24:52 PM PDT 24 475498026 ps
T368 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2388909779 Aug 08 04:22:30 PM PDT 24 Aug 08 04:22:31 PM PDT 24 370948394 ps
T369 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3666128649 Aug 08 04:23:44 PM PDT 24 Aug 08 04:23:47 PM PDT 24 466823707 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1489451053 Aug 08 04:26:20 PM PDT 24 Aug 08 04:26:55 PM PDT 24 13876205008 ps
T370 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.534444719 Aug 08 04:25:16 PM PDT 24 Aug 08 04:25:17 PM PDT 24 459523635 ps
T371 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2416758488 Aug 08 04:27:02 PM PDT 24 Aug 08 04:27:05 PM PDT 24 459031829 ps
T372 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3197254364 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:17 PM PDT 24 469397605 ps
T373 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.640925504 Aug 08 04:22:28 PM PDT 24 Aug 08 04:22:29 PM PDT 24 350440348 ps
T374 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2606892600 Aug 08 04:22:59 PM PDT 24 Aug 08 04:23:01 PM PDT 24 487739276 ps
T60 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1174117346 Aug 08 04:26:05 PM PDT 24 Aug 08 04:26:06 PM PDT 24 543369244 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2039312912 Aug 08 04:26:54 PM PDT 24 Aug 08 04:26:58 PM PDT 24 2795708101 ps
T56 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.725513667 Aug 08 04:24:54 PM PDT 24 Aug 08 04:24:55 PM PDT 24 481013929 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2017690399 Aug 08 04:25:43 PM PDT 24 Aug 08 04:25:43 PM PDT 24 369311502 ps
T377 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2738312889 Aug 08 04:21:43 PM PDT 24 Aug 08 04:21:44 PM PDT 24 1130958358 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3645703960 Aug 08 04:23:08 PM PDT 24 Aug 08 04:23:09 PM PDT 24 370728498 ps
T379 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4054065604 Aug 08 04:26:41 PM PDT 24 Aug 08 04:26:43 PM PDT 24 4987951213 ps
T380 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3742816750 Aug 08 04:26:55 PM PDT 24 Aug 08 04:26:56 PM PDT 24 1923827138 ps
T381 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1219930270 Aug 08 04:24:30 PM PDT 24 Aug 08 04:24:38 PM PDT 24 4431553888 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1671802898 Aug 08 04:21:41 PM PDT 24 Aug 08 04:21:42 PM PDT 24 476271558 ps
T383 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3774926782 Aug 08 04:26:17 PM PDT 24 Aug 08 04:26:19 PM PDT 24 434877006 ps
T384 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1426268332 Aug 08 04:22:28 PM PDT 24 Aug 08 04:22:29 PM PDT 24 388680654 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3005327063 Aug 08 04:28:09 PM PDT 24 Aug 08 04:28:10 PM PDT 24 1793409776 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.86418099 Aug 08 04:21:32 PM PDT 24 Aug 08 04:21:34 PM PDT 24 567923865 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2976395037 Aug 08 04:22:56 PM PDT 24 Aug 08 04:22:57 PM PDT 24 332835922 ps
T388 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3137895081 Aug 08 04:21:45 PM PDT 24 Aug 08 04:21:46 PM PDT 24 1269351202 ps
T389 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.907309689 Aug 08 04:23:01 PM PDT 24 Aug 08 04:23:02 PM PDT 24 685517658 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.361122478 Aug 08 04:22:51 PM PDT 24 Aug 08 04:22:52 PM PDT 24 648994407 ps
T391 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.140532762 Aug 08 04:23:19 PM PDT 24 Aug 08 04:23:20 PM PDT 24 312385436 ps
T392 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2403100589 Aug 08 04:23:02 PM PDT 24 Aug 08 04:23:03 PM PDT 24 609742102 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2187708524 Aug 08 04:27:03 PM PDT 24 Aug 08 04:27:15 PM PDT 24 8090874798 ps
T394 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.475822898 Aug 08 04:22:06 PM PDT 24 Aug 08 04:22:08 PM PDT 24 531905441 ps
T395 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.272660976 Aug 08 04:22:27 PM PDT 24 Aug 08 04:22:28 PM PDT 24 303188487 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1923694151 Aug 08 04:25:13 PM PDT 24 Aug 08 04:25:15 PM PDT 24 435474914 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2727010609 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:51 PM PDT 24 390530521 ps
T397 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1206952828 Aug 08 04:27:39 PM PDT 24 Aug 08 04:27:41 PM PDT 24 373871233 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2765501317 Aug 08 04:25:00 PM PDT 24 Aug 08 04:25:01 PM PDT 24 623295363 ps
T398 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2982385478 Aug 08 04:26:17 PM PDT 24 Aug 08 04:26:19 PM PDT 24 1296953674 ps
T399 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.417376688 Aug 08 04:23:54 PM PDT 24 Aug 08 04:23:55 PM PDT 24 776285908 ps
T400 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3528563830 Aug 08 04:22:26 PM PDT 24 Aug 08 04:22:27 PM PDT 24 286923537 ps
T401 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.27945592 Aug 08 04:22:32 PM PDT 24 Aug 08 04:22:33 PM PDT 24 350100522 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4085447894 Aug 08 04:24:06 PM PDT 24 Aug 08 04:24:07 PM PDT 24 1212832378 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1437570954 Aug 08 04:26:08 PM PDT 24 Aug 08 04:26:09 PM PDT 24 375912853 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2827451702 Aug 08 04:22:33 PM PDT 24 Aug 08 04:22:35 PM PDT 24 444015482 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1019338199 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:28 PM PDT 24 460996253 ps
T406 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1488758587 Aug 08 04:25:13 PM PDT 24 Aug 08 04:25:16 PM PDT 24 593223910 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2109656416 Aug 08 04:21:32 PM PDT 24 Aug 08 04:21:35 PM PDT 24 1837497923 ps
T408 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3974571997 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:19 PM PDT 24 464967486 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1923350933 Aug 08 04:24:44 PM PDT 24 Aug 08 04:24:45 PM PDT 24 351405233 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1598537091 Aug 08 04:21:56 PM PDT 24 Aug 08 04:21:57 PM PDT 24 549686648 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1331773637 Aug 08 04:24:48 PM PDT 24 Aug 08 04:24:50 PM PDT 24 1442210302 ps
T412 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3014064284 Aug 08 04:23:08 PM PDT 24 Aug 08 04:23:09 PM PDT 24 418979167 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1457326489 Aug 08 04:26:54 PM PDT 24 Aug 08 04:27:10 PM PDT 24 7241748212 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2598585209 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:34 PM PDT 24 474075059 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1523194223 Aug 08 04:27:00 PM PDT 24 Aug 08 04:27:01 PM PDT 24 1423453308 ps
T416 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1469952710 Aug 08 04:22:37 PM PDT 24 Aug 08 04:22:39 PM PDT 24 549302666 ps
T417 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2903145866 Aug 08 04:25:10 PM PDT 24 Aug 08 04:25:12 PM PDT 24 796758804 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4181525082 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:30 PM PDT 24 4276232888 ps
T419 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3733433629 Aug 08 04:21:52 PM PDT 24 Aug 08 04:21:53 PM PDT 24 473310712 ps
T420 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2721348587 Aug 08 04:22:26 PM PDT 24 Aug 08 04:22:27 PM PDT 24 392165489 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3837055339 Aug 08 04:21:39 PM PDT 24 Aug 08 04:21:41 PM PDT 24 670605210 ps
T422 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.850297394 Aug 08 04:23:45 PM PDT 24 Aug 08 04:23:46 PM PDT 24 395888695 ps
T423 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2303729756 Aug 08 04:22:23 PM PDT 24 Aug 08 04:22:26 PM PDT 24 8609085422 ps
T424 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2486862288 Aug 08 04:22:11 PM PDT 24 Aug 08 04:22:12 PM PDT 24 340979146 ps
T194 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3433068208 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:28 PM PDT 24 7935882702 ps
T425 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1594498601 Aug 08 04:25:04 PM PDT 24 Aug 08 04:25:04 PM PDT 24 518979462 ps
T426 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1894022650 Aug 08 04:24:58 PM PDT 24 Aug 08 04:25:01 PM PDT 24 2993450063 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.130679028
Short name T5
Test name
Test status
Simulation time 53654845350 ps
CPU time 335.52 seconds
Started Aug 08 05:16:10 PM PDT 24
Finished Aug 08 05:21:46 PM PDT 24
Peak memory 214520 kb
Host smart-c6d35525-f5a5-4ac1-b1d7-7c065a4db06d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130679028 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.130679028
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.865024511
Short name T7
Test name
Test status
Simulation time 93667704199 ps
CPU time 129.39 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:18:16 PM PDT 24
Peak memory 198388 kb
Host smart-06c4d3c4-793d-4e1d-b1f4-61639f0885c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865024511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.865024511
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.591602422
Short name T30
Test name
Test status
Simulation time 4313721136 ps
CPU time 7.49 seconds
Started Aug 08 04:23:21 PM PDT 24
Finished Aug 08 04:23:29 PM PDT 24
Peak memory 198336 kb
Host smart-a737f8c9-128f-49ba-bdae-6c52340e9db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591602422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.591602422
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2398642020
Short name T26
Test name
Test status
Simulation time 168456103167 ps
CPU time 319.89 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:21:47 PM PDT 24
Peak memory 210016 kb
Host smart-dce0c311-9650-4d3e-8cb6-96b4c76871c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398642020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2398642020
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3215500248
Short name T11
Test name
Test status
Simulation time 388307152357 ps
CPU time 955.73 seconds
Started Aug 08 05:16:48 PM PDT 24
Finished Aug 08 05:32:45 PM PDT 24
Peak memory 214992 kb
Host smart-c4ac3d78-851a-40e1-ba25-ba0ab4fdf17e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215500248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3215500248
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1596508137
Short name T72
Test name
Test status
Simulation time 49789199218 ps
CPU time 388.76 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:22:34 PM PDT 24
Peak memory 200092 kb
Host smart-a3c978e0-48b6-4954-a01a-27255c876a0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596508137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1596508137
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3601210611
Short name T79
Test name
Test status
Simulation time 146480897264 ps
CPU time 1120.67 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:35:13 PM PDT 24
Peak memory 215100 kb
Host smart-ff29e5d7-31a0-4cd0-b09f-28df789925a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601210611 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3601210611
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4080948578
Short name T154
Test name
Test status
Simulation time 34942049167 ps
CPU time 307.51 seconds
Started Aug 08 05:16:26 PM PDT 24
Finished Aug 08 05:21:34 PM PDT 24
Peak memory 212856 kb
Host smart-552afea8-29ee-4348-a3b9-08104afa9c67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080948578 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4080948578
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3056191523
Short name T82
Test name
Test status
Simulation time 589548775363 ps
CPU time 265.63 seconds
Started Aug 08 05:16:51 PM PDT 24
Finished Aug 08 05:21:17 PM PDT 24
Peak memory 201312 kb
Host smart-8636a192-23f9-4ca8-bb73-44fab6e916e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056191523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3056191523
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4131852374
Short name T10
Test name
Test status
Simulation time 55805501881 ps
CPU time 86.21 seconds
Started Aug 08 05:16:47 PM PDT 24
Finished Aug 08 05:18:13 PM PDT 24
Peak memory 192940 kb
Host smart-bb8ce320-57e5-4b00-bb7f-a2c25c14ba13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131852374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4131852374
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.4133624395
Short name T20
Test name
Test status
Simulation time 129891941949 ps
CPU time 641.99 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:27:19 PM PDT 24
Peak memory 214544 kb
Host smart-36a3906e-604c-47df-9d87-1e587c07477c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133624395 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.4133624395
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.374906339
Short name T78
Test name
Test status
Simulation time 70924401455 ps
CPU time 264.31 seconds
Started Aug 08 05:16:41 PM PDT 24
Finished Aug 08 05:21:05 PM PDT 24
Peak memory 207948 kb
Host smart-8bc62188-79e3-43b4-8052-685c524cca32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374906339 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.374906339
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4080037349
Short name T14
Test name
Test status
Simulation time 8479963943 ps
CPU time 3.43 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 215768 kb
Host smart-33be5e50-c77b-480d-b003-9bd53cd8b9a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080037349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4080037349
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3903433729
Short name T90
Test name
Test status
Simulation time 587020031623 ps
CPU time 1160.56 seconds
Started Aug 08 05:16:49 PM PDT 24
Finished Aug 08 05:36:11 PM PDT 24
Peak memory 211468 kb
Host smart-1ce331cc-7e34-4e29-b365-588427979083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903433729 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3903433729
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4198961657
Short name T103
Test name
Test status
Simulation time 154666665942 ps
CPU time 412.64 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:23:01 PM PDT 24
Peak memory 211660 kb
Host smart-415fa04b-a80b-470b-967f-6dca66c87107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198961657 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4198961657
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2207378363
Short name T100
Test name
Test status
Simulation time 37223299322 ps
CPU time 395.61 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:22:48 PM PDT 24
Peak memory 206992 kb
Host smart-be002489-714f-4885-8438-b33dfed6613e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207378363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2207378363
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.311095790
Short name T49
Test name
Test status
Simulation time 83114589174 ps
CPU time 701.92 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:27:54 PM PDT 24
Peak memory 212184 kb
Host smart-0b3aa2d3-7464-473f-9022-d28876ca5347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311095790 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.311095790
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1785461542
Short name T138
Test name
Test status
Simulation time 137020320372 ps
CPU time 392.54 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:23:05 PM PDT 24
Peak memory 203160 kb
Host smart-eb21f153-1ba5-4b90-9697-9051d13c9c51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785461542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1785461542
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.780323496
Short name T4
Test name
Test status
Simulation time 39618052708 ps
CPU time 304.78 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:21:06 PM PDT 24
Peak memory 206968 kb
Host smart-cdd28824-773d-4418-a829-0a095107309b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780323496 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.780323496
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1376635949
Short name T94
Test name
Test status
Simulation time 201883000830 ps
CPU time 163.06 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:18:51 PM PDT 24
Peak memory 198412 kb
Host smart-bc9edfe1-99f1-4fcf-ba3f-9811c166c04b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376635949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1376635949
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2297030845
Short name T87
Test name
Test status
Simulation time 198790773555 ps
CPU time 66.27 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:17:13 PM PDT 24
Peak memory 193044 kb
Host smart-dd4c1a5d-4e52-42f8-a471-a33c98ee1c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297030845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2297030845
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2976150426
Short name T38
Test name
Test status
Simulation time 825100391308 ps
CPU time 651.35 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:26:56 PM PDT 24
Peak memory 206028 kb
Host smart-047ef53a-ce19-4ae2-8ded-2140a828c6dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976150426 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2976150426
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.864561194
Short name T147
Test name
Test status
Simulation time 105212031510 ps
CPU time 314.63 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:21:32 PM PDT 24
Peak memory 201968 kb
Host smart-0d209efc-24a5-45cb-a027-3a96268b9440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864561194 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.864561194
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1443335202
Short name T81
Test name
Test status
Simulation time 155722342155 ps
CPU time 611.29 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:26:17 PM PDT 24
Peak memory 205208 kb
Host smart-a02db012-8f33-4d2f-bab6-b2265e3a2a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443335202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1443335202
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2868208237
Short name T124
Test name
Test status
Simulation time 133306219227 ps
CPU time 213.16 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:19:44 PM PDT 24
Peak memory 193192 kb
Host smart-cd1f1326-8427-4252-8050-f259c1465022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868208237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2868208237
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3139103597
Short name T118
Test name
Test status
Simulation time 49058251868 ps
CPU time 70.24 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:17:46 PM PDT 24
Peak memory 193244 kb
Host smart-84027479-4d5f-4e70-bbb7-df66365bf8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139103597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3139103597
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1001934903
Short name T112
Test name
Test status
Simulation time 99733608549 ps
CPU time 145.86 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:18:58 PM PDT 24
Peak memory 192060 kb
Host smart-dbe6dd9a-1f51-472e-aaee-cffcd5557223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001934903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1001934903
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1697470928
Short name T144
Test name
Test status
Simulation time 263462606465 ps
CPU time 376.2 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:22:44 PM PDT 24
Peak memory 198436 kb
Host smart-76b19739-5f1d-4ac8-aa5c-c8313c6b8276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697470928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1697470928
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.134948585
Short name T1
Test name
Test status
Simulation time 133214286048 ps
CPU time 87.66 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:17:32 PM PDT 24
Peak memory 193200 kb
Host smart-1cf1fe3a-9e38-4c4e-9b8e-050345479b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134948585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.134948585
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2473199136
Short name T36
Test name
Test status
Simulation time 123737924847 ps
CPU time 746.32 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:28:37 PM PDT 24
Peak memory 206104 kb
Host smart-3e3ff93a-2d99-4007-ba30-6920d17b3bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473199136 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2473199136
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1054985638
Short name T84
Test name
Test status
Simulation time 62783246208 ps
CPU time 547.86 seconds
Started Aug 08 05:16:20 PM PDT 24
Finished Aug 08 05:25:28 PM PDT 24
Peak memory 210576 kb
Host smart-3f1742c5-37e5-4524-8a70-c34f4c5cead0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054985638 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1054985638
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2163627472
Short name T114
Test name
Test status
Simulation time 70863271085 ps
CPU time 55.93 seconds
Started Aug 08 05:16:24 PM PDT 24
Finished Aug 08 05:17:20 PM PDT 24
Peak memory 192668 kb
Host smart-338c92ad-8e22-4dc3-bc17-284a76b9520d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163627472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2163627472
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2664804278
Short name T96
Test name
Test status
Simulation time 43357707085 ps
CPU time 63.06 seconds
Started Aug 08 05:16:33 PM PDT 24
Finished Aug 08 05:17:36 PM PDT 24
Peak memory 192172 kb
Host smart-aa710425-977a-4c62-a536-1ae59572e9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664804278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2664804278
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2738216955
Short name T108
Test name
Test status
Simulation time 92521468154 ps
CPU time 136.69 seconds
Started Aug 08 05:16:46 PM PDT 24
Finished Aug 08 05:19:03 PM PDT 24
Peak memory 198480 kb
Host smart-310ff7dd-b9af-4378-a521-11c1d705d580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738216955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2738216955
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1497365606
Short name T89
Test name
Test status
Simulation time 125902017538 ps
CPU time 47.28 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:48 PM PDT 24
Peak memory 192148 kb
Host smart-363bb63c-5e69-4219-b18a-a233290ac02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497365606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1497365606
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.41424849
Short name T113
Test name
Test status
Simulation time 158114092964 ps
CPU time 334 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:21:49 PM PDT 24
Peak memory 201748 kb
Host smart-fbdfd348-c328-4cdd-bf27-a0393a18b5a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41424849 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.41424849
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3302889313
Short name T132
Test name
Test status
Simulation time 22648941117 ps
CPU time 34.99 seconds
Started Aug 08 05:16:31 PM PDT 24
Finished Aug 08 05:17:06 PM PDT 24
Peak memory 192060 kb
Host smart-3e7aa888-be9b-410d-a71e-618b503c8df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302889313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3302889313
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3145216498
Short name T116
Test name
Test status
Simulation time 99458709932 ps
CPU time 230.55 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:20:00 PM PDT 24
Peak memory 208952 kb
Host smart-8cbd70e2-350a-4cef-9891-96e87984c767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145216498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3145216498
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4062070766
Short name T88
Test name
Test status
Simulation time 132143749471 ps
CPU time 88.1 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:17:42 PM PDT 24
Peak memory 193176 kb
Host smart-b519638c-35bb-47e5-9e39-bfd1f3adfa21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062070766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4062070766
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3114712539
Short name T75
Test name
Test status
Simulation time 121920825402 ps
CPU time 190.78 seconds
Started Aug 08 05:16:46 PM PDT 24
Finished Aug 08 05:19:57 PM PDT 24
Peak memory 206912 kb
Host smart-75715c32-3d22-40da-b49b-ac830477e9f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114712539 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3114712539
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2424705624
Short name T152
Test name
Test status
Simulation time 222938046437 ps
CPU time 84.18 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:18:03 PM PDT 24
Peak memory 184372 kb
Host smart-8ec49471-8017-407b-8d03-cbced4e1c157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424705624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2424705624
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2027048902
Short name T85
Test name
Test status
Simulation time 60249402436 ps
CPU time 25.52 seconds
Started Aug 08 05:16:50 PM PDT 24
Finished Aug 08 05:17:17 PM PDT 24
Peak memory 192796 kb
Host smart-6e83df4e-a156-49ca-9ff5-bac120f68eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027048902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2027048902
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2990190191
Short name T73
Test name
Test status
Simulation time 26328520947 ps
CPU time 268.29 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:20:40 PM PDT 24
Peak memory 198884 kb
Host smart-2190544f-f93b-4fd9-a20e-a9ecb64e1127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990190191 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2990190191
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2928304808
Short name T99
Test name
Test status
Simulation time 156453783765 ps
CPU time 126.51 seconds
Started Aug 08 05:16:38 PM PDT 24
Finished Aug 08 05:18:45 PM PDT 24
Peak memory 193088 kb
Host smart-3cae9a5a-7be0-48f6-a0f7-6ab5b787363a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928304808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2928304808
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2333667196
Short name T119
Test name
Test status
Simulation time 70029981293 ps
CPU time 27.16 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:16:54 PM PDT 24
Peak memory 198404 kb
Host smart-77c3f30c-5f70-488b-8396-f0c7b5b3b3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333667196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2333667196
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1581516522
Short name T123
Test name
Test status
Simulation time 28492876730 ps
CPU time 252.46 seconds
Started Aug 08 05:16:49 PM PDT 24
Finished Aug 08 05:21:02 PM PDT 24
Peak memory 206988 kb
Host smart-6921334b-e78e-49d5-9832-5ea2c21dcf52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581516522 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1581516522
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3212144901
Short name T3
Test name
Test status
Simulation time 159124238965 ps
CPU time 22.43 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 192180 kb
Host smart-eba5ad3a-7570-40b5-b3b1-07495e70bd92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212144901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3212144901
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3171627642
Short name T111
Test name
Test status
Simulation time 177526718960 ps
CPU time 69.83 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:17:16 PM PDT 24
Peak memory 192840 kb
Host smart-6d32b33a-44da-4084-9c37-53f02075c253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171627642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3171627642
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1665290975
Short name T37
Test name
Test status
Simulation time 31482737670 ps
CPU time 324.98 seconds
Started Aug 08 05:16:31 PM PDT 24
Finished Aug 08 05:21:56 PM PDT 24
Peak memory 206968 kb
Host smart-6edd33fa-bcf7-47c5-a1fc-b77f74c860a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665290975 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1665290975
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2150759794
Short name T104
Test name
Test status
Simulation time 12209799576 ps
CPU time 121.37 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:18:06 PM PDT 24
Peak memory 214624 kb
Host smart-80aa7c39-4900-4622-94e2-d3b2f2fecd5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150759794 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2150759794
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2623088010
Short name T106
Test name
Test status
Simulation time 112864735906 ps
CPU time 41.44 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:16:57 PM PDT 24
Peak memory 192100 kb
Host smart-4eb1a546-b3dd-4579-91da-4dd79231ce45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623088010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2623088010
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2992706369
Short name T122
Test name
Test status
Simulation time 42880007679 ps
CPU time 66.71 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:17:12 PM PDT 24
Peak memory 198380 kb
Host smart-4cd3385f-17b6-40b0-a4e4-79a5744ea1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992706369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2992706369
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2964828168
Short name T95
Test name
Test status
Simulation time 25149416115 ps
CPU time 39.28 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:51 PM PDT 24
Peak memory 192072 kb
Host smart-3a7fae0b-25fb-4dce-b813-fadb9a75d465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964828168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2964828168
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3016396709
Short name T50
Test name
Test status
Simulation time 159436098856 ps
CPU time 414.55 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:23:12 PM PDT 24
Peak memory 203420 kb
Host smart-d6797fbe-2fed-425b-8b02-3439b8f29ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016396709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3016396709
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2384525076
Short name T53
Test name
Test status
Simulation time 10289338068 ps
CPU time 15.57 seconds
Started Aug 08 04:22:37 PM PDT 24
Finished Aug 08 04:22:53 PM PDT 24
Peak memory 195968 kb
Host smart-b338b5da-f3f4-4b28-b601-863c73d7f6db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384525076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2384525076
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.552977065
Short name T131
Test name
Test status
Simulation time 113288296626 ps
CPU time 172.08 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:18:57 PM PDT 24
Peak memory 193268 kb
Host smart-d7190b2e-5843-47a0-a06d-ce71a5680403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552977065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.552977065
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3665022993
Short name T52
Test name
Test status
Simulation time 289233940 ps
CPU time 0.74 seconds
Started Aug 08 04:23:08 PM PDT 24
Finished Aug 08 04:23:09 PM PDT 24
Peak memory 193212 kb
Host smart-3fd03aa4-f4ba-4ed4-a427-6aa102638241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665022993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3665022993
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2845633357
Short name T115
Test name
Test status
Simulation time 98039915099 ps
CPU time 72.37 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:17:30 PM PDT 24
Peak memory 193148 kb
Host smart-ddd90177-d109-4190-81bf-06dc033a5020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845633357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2845633357
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2502283695
Short name T107
Test name
Test status
Simulation time 58106474119 ps
CPU time 41.95 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:17:09 PM PDT 24
Peak memory 198444 kb
Host smart-56bf685a-4a89-4c6a-9bd6-0a243116fe59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502283695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2502283695
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.4258326687
Short name T80
Test name
Test status
Simulation time 114723366571 ps
CPU time 159.03 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:19:23 PM PDT 24
Peak memory 207808 kb
Host smart-59405eb0-1c76-4005-b7b4-fa5a227bd233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258326687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.4258326687
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1485367263
Short name T35
Test name
Test status
Simulation time 237373023278 ps
CPU time 556.75 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:25:53 PM PDT 24
Peak memory 213156 kb
Host smart-d79ce40a-aefb-44fc-acd6-a2b0b5928cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485367263 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1485367263
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3823998365
Short name T150
Test name
Test status
Simulation time 26248697729 ps
CPU time 41.23 seconds
Started Aug 08 05:16:35 PM PDT 24
Finished Aug 08 05:17:16 PM PDT 24
Peak memory 193136 kb
Host smart-5bb1d9d6-8097-422b-afb4-3c45479ca68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823998365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3823998365
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.295394024
Short name T168
Test name
Test status
Simulation time 16785203595 ps
CPU time 186.04 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:19:42 PM PDT 24
Peak memory 206844 kb
Host smart-e2e5dc56-7431-4f24-82a3-caf365e38cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295394024 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.295394024
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4171659230
Short name T92
Test name
Test status
Simulation time 110900351712 ps
CPU time 39.67 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:16:55 PM PDT 24
Peak memory 193200 kb
Host smart-06884389-f87b-42a1-b8fb-1cf27595cd8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171659230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4171659230
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.624989920
Short name T44
Test name
Test status
Simulation time 238245331085 ps
CPU time 378.12 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:22:29 PM PDT 24
Peak memory 198420 kb
Host smart-01951870-972b-47df-bc14-309fce7499ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624989920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.624989920
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.589308552
Short name T126
Test name
Test status
Simulation time 149122247098 ps
CPU time 151.05 seconds
Started Aug 08 05:16:31 PM PDT 24
Finished Aug 08 05:19:02 PM PDT 24
Peak memory 192108 kb
Host smart-8496773e-4ecd-4576-aa78-35cd22c0f727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589308552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.589308552
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3391900113
Short name T128
Test name
Test status
Simulation time 432837035175 ps
CPU time 634.72 seconds
Started Aug 08 05:16:34 PM PDT 24
Finished Aug 08 05:27:09 PM PDT 24
Peak memory 198524 kb
Host smart-233f8a6c-d586-4f98-94ed-87395c5761cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391900113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3391900113
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2649048359
Short name T148
Test name
Test status
Simulation time 169760377015 ps
CPU time 251.17 seconds
Started Aug 08 05:16:38 PM PDT 24
Finished Aug 08 05:20:49 PM PDT 24
Peak memory 198400 kb
Host smart-cd24a3cc-bef8-493f-bd25-c02e0484cabc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649048359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2649048359
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3007183822
Short name T48
Test name
Test status
Simulation time 18977337343 ps
CPU time 3.45 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:48 PM PDT 24
Peak memory 192168 kb
Host smart-f7944617-ddaa-48fc-bd19-fc36c9174171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007183822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3007183822
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2478474912
Short name T140
Test name
Test status
Simulation time 151045731479 ps
CPU time 90.99 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:17:31 PM PDT 24
Peak memory 192060 kb
Host smart-0217b7d1-14a8-47f5-a1d6-14ece5167292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478474912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2478474912
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2398440108
Short name T157
Test name
Test status
Simulation time 64794259397 ps
CPU time 589.12 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:25:57 PM PDT 24
Peak memory 212148 kb
Host smart-e91eff6d-ab66-4fc7-a64b-027d85d3bee9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398440108 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2398440108
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.443844450
Short name T146
Test name
Test status
Simulation time 560706108 ps
CPU time 1.04 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:13 PM PDT 24
Peak memory 196872 kb
Host smart-aac831af-13e8-4192-ab55-58f4b12851a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443844450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.443844450
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.884544207
Short name T153
Test name
Test status
Simulation time 600437495 ps
CPU time 0.81 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 196904 kb
Host smart-dce3e7ec-2b39-4bbc-8bd0-48a3b78e27a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884544207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.884544207
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1908754159
Short name T74
Test name
Test status
Simulation time 318312908901 ps
CPU time 651.95 seconds
Started Aug 08 05:16:40 PM PDT 24
Finished Aug 08 05:27:32 PM PDT 24
Peak memory 214296 kb
Host smart-7356d575-d858-4d0a-9f1f-b0786a38410e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908754159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1908754159
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.519886494
Short name T43
Test name
Test status
Simulation time 427860003 ps
CPU time 0.75 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 196804 kb
Host smart-afc3e5ce-af11-400a-b456-17786a8008d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519886494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.519886494
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1678012020
Short name T102
Test name
Test status
Simulation time 19643178353 ps
CPU time 217.54 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:19:43 PM PDT 24
Peak memory 214292 kb
Host smart-bfe38136-27a1-4498-b677-5fcf4e213206
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678012020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1678012020
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1252169548
Short name T121
Test name
Test status
Simulation time 545199622 ps
CPU time 0.79 seconds
Started Aug 08 05:16:16 PM PDT 24
Finished Aug 08 05:16:17 PM PDT 24
Peak memory 196800 kb
Host smart-64598ea7-4eb8-49c8-920a-f8c78573c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252169548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1252169548
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.809129409
Short name T109
Test name
Test status
Simulation time 76297727932 ps
CPU time 26.42 seconds
Started Aug 08 05:16:16 PM PDT 24
Finished Aug 08 05:16:43 PM PDT 24
Peak memory 192132 kb
Host smart-740c3696-8fe9-4cc8-b322-99ce6f29e276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809129409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.809129409
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3576751344
Short name T24
Test name
Test status
Simulation time 116031830785 ps
CPU time 514.81 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:24:50 PM PDT 24
Peak memory 211988 kb
Host smart-d90c1e45-fa48-4d1c-b5be-364f0a7dcff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576751344 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3576751344
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3101403907
Short name T162
Test name
Test status
Simulation time 389864177962 ps
CPU time 91.04 seconds
Started Aug 08 05:16:21 PM PDT 24
Finished Aug 08 05:17:52 PM PDT 24
Peak memory 192612 kb
Host smart-c4393397-e232-4c0e-af53-aa1854dff416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101403907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3101403907
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4267623088
Short name T22
Test name
Test status
Simulation time 236750295806 ps
CPU time 51.35 seconds
Started Aug 08 05:16:18 PM PDT 24
Finished Aug 08 05:17:10 PM PDT 24
Peak memory 192112 kb
Host smart-51bc3f64-34b7-41cc-9fe7-b86ac94ad063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267623088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4267623088
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3765595010
Short name T117
Test name
Test status
Simulation time 584195298334 ps
CPU time 232.97 seconds
Started Aug 08 05:16:38 PM PDT 24
Finished Aug 08 05:20:31 PM PDT 24
Peak memory 193176 kb
Host smart-085c742c-a0d5-48a1-8f71-10022811588e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765595010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3765595010
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2214039390
Short name T91
Test name
Test status
Simulation time 363866705 ps
CPU time 0.96 seconds
Started Aug 08 05:16:46 PM PDT 24
Finished Aug 08 05:16:47 PM PDT 24
Peak memory 196880 kb
Host smart-da907345-4228-46a5-9f71-d7d7a8902707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214039390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2214039390
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.772830182
Short name T83
Test name
Test status
Simulation time 51638935453 ps
CPU time 147.18 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:18:31 PM PDT 24
Peak memory 199352 kb
Host smart-7157bdb5-5cba-4231-a63f-5559381ae2c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772830182 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.772830182
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.513900302
Short name T134
Test name
Test status
Simulation time 552386361 ps
CPU time 1.01 seconds
Started Aug 08 05:16:25 PM PDT 24
Finished Aug 08 05:16:26 PM PDT 24
Peak memory 196836 kb
Host smart-98b79ca9-0da6-43bd-a3fe-26313db48167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513900302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.513900302
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1981578029
Short name T130
Test name
Test status
Simulation time 304753802775 ps
CPU time 497.17 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:24:30 PM PDT 24
Peak memory 193120 kb
Host smart-03cac86b-d2e1-40f3-a7f3-c85c5f25ef57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981578029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1981578029
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3275351439
Short name T169
Test name
Test status
Simulation time 25208466715 ps
CPU time 15.08 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:17 PM PDT 24
Peak memory 191996 kb
Host smart-5fa6a4dd-e442-4188-bad0-9ae70bb3b325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275351439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3275351439
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4051612224
Short name T97
Test name
Test status
Simulation time 76624363716 ps
CPU time 418.93 seconds
Started Aug 08 05:16:26 PM PDT 24
Finished Aug 08 05:23:25 PM PDT 24
Peak memory 211268 kb
Host smart-ffe35786-8b85-49d6-8c0d-c00b7d57ddaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051612224 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4051612224
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.217735822
Short name T145
Test name
Test status
Simulation time 452388802 ps
CPU time 1.05 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196956 kb
Host smart-1ca312e0-8681-4fde-89f4-395914bb8ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217735822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.217735822
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2613710620
Short name T175
Test name
Test status
Simulation time 78600407248 ps
CPU time 552.47 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:25:17 PM PDT 24
Peak memory 215108 kb
Host smart-14c1a1f2-a302-40bc-94f2-448ee54a8127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613710620 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2613710620
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.462349374
Short name T136
Test name
Test status
Simulation time 448541153 ps
CPU time 0.64 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:16:14 PM PDT 24
Peak memory 196944 kb
Host smart-0d5e66ee-995b-4a45-807f-6c7962c11da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462349374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.462349374
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2104455244
Short name T93
Test name
Test status
Simulation time 81798229303 ps
CPU time 108.06 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:18:01 PM PDT 24
Peak memory 192020 kb
Host smart-266e1e4a-bb0f-41cb-a07a-7799a981317d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104455244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2104455244
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.212146339
Short name T47
Test name
Test status
Simulation time 386520482 ps
CPU time 1.17 seconds
Started Aug 08 05:16:03 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 196844 kb
Host smart-02f18a5f-46cb-4f6f-9de4-09442a9540c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212146339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.212146339
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2588891018
Short name T71
Test name
Test status
Simulation time 45241478456 ps
CPU time 126.22 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:18:43 PM PDT 24
Peak memory 214272 kb
Host smart-e507b522-68d7-474c-9914-cf92b8447770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588891018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2588891018
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.862270511
Short name T129
Test name
Test status
Simulation time 89451846259 ps
CPU time 134.62 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:18:53 PM PDT 24
Peak memory 192024 kb
Host smart-810f800d-d335-4aa8-be78-c5df4f6cf58e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862270511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.862270511
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.550459343
Short name T149
Test name
Test status
Simulation time 553267733 ps
CPU time 0.71 seconds
Started Aug 08 05:16:45 PM PDT 24
Finished Aug 08 05:16:46 PM PDT 24
Peak memory 196820 kb
Host smart-fdd77c0f-c8ed-4a94-b9c6-483aaf4135da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550459343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.550459343
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2513715993
Short name T77
Test name
Test status
Simulation time 125024761773 ps
CPU time 500.97 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:24:28 PM PDT 24
Peak memory 214180 kb
Host smart-7664f1ae-d78b-446b-a560-92d0d15b0575
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513715993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2513715993
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.149862895
Short name T141
Test name
Test status
Simulation time 419065874 ps
CPU time 0.66 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 196860 kb
Host smart-fea98d21-2d79-4001-bcac-d933184c7156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149862895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.149862895
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2785093307
Short name T160
Test name
Test status
Simulation time 32321466904 ps
CPU time 257.93 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:20:29 PM PDT 24
Peak memory 198716 kb
Host smart-b10bb1ce-00c1-48c2-b189-039536a53d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785093307 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2785093307
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4033242896
Short name T139
Test name
Test status
Simulation time 530245612 ps
CPU time 1.16 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 196832 kb
Host smart-c5c47bc6-0a5c-41b7-b620-95dbbc7cee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033242896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4033242896
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.4115774012
Short name T101
Test name
Test status
Simulation time 587900497 ps
CPU time 0.84 seconds
Started Aug 08 05:16:21 PM PDT 24
Finished Aug 08 05:16:22 PM PDT 24
Peak memory 196832 kb
Host smart-d869cd25-ff32-47c0-b1bd-df74c2c968f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115774012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.4115774012
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1418215781
Short name T6
Test name
Test status
Simulation time 501058004 ps
CPU time 0.77 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 196920 kb
Host smart-b8eb6e12-1bd8-4a5c-a0af-5524682742f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418215781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1418215781
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2837298951
Short name T133
Test name
Test status
Simulation time 504375897 ps
CPU time 1.23 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196956 kb
Host smart-74755a8d-9284-4ba1-b154-1c0c6f35792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837298951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2837298951
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1010049976
Short name T110
Test name
Test status
Simulation time 500371094 ps
CPU time 1.12 seconds
Started Aug 08 05:16:45 PM PDT 24
Finished Aug 08 05:16:46 PM PDT 24
Peak memory 196896 kb
Host smart-052aab58-c026-46e9-a77a-14196d3f1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010049976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1010049976
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1678408641
Short name T98
Test name
Test status
Simulation time 170735152823 ps
CPU time 208.95 seconds
Started Aug 08 05:16:43 PM PDT 24
Finished Aug 08 05:20:12 PM PDT 24
Peak memory 198392 kb
Host smart-4236b42b-ac4b-4d21-a4ed-2823003e15fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678408641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1678408641
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3955385718
Short name T76
Test name
Test status
Simulation time 209569428469 ps
CPU time 274.64 seconds
Started Aug 08 05:16:50 PM PDT 24
Finished Aug 08 05:21:25 PM PDT 24
Peak memory 206908 kb
Host smart-3f4cd770-277b-4d1d-ad58-cc4385bb68f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955385718 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3955385718
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3650166028
Short name T105
Test name
Test status
Simulation time 59950750179 ps
CPU time 527.92 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:24:53 PM PDT 24
Peak memory 215152 kb
Host smart-85972486-e578-4fab-a820-d58364a57b86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650166028 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3650166028
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2239958563
Short name T185
Test name
Test status
Simulation time 69753934672 ps
CPU time 28.69 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:16:34 PM PDT 24
Peak memory 192092 kb
Host smart-f26b6908-0196-466f-b55b-4a4f1ee7a881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239958563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2239958563
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.205591020
Short name T151
Test name
Test status
Simulation time 539897879 ps
CPU time 1.47 seconds
Started Aug 08 05:16:24 PM PDT 24
Finished Aug 08 05:16:26 PM PDT 24
Peak memory 196928 kb
Host smart-b7f1d378-93d3-4c49-bcd5-22ff919dd4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205591020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.205591020
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3566668782
Short name T135
Test name
Test status
Simulation time 525549867 ps
CPU time 1.34 seconds
Started Aug 08 05:16:30 PM PDT 24
Finished Aug 08 05:16:31 PM PDT 24
Peak memory 196836 kb
Host smart-d2b5fb18-11e7-47e7-bb45-d6f3e0f13d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566668782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3566668782
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1766142784
Short name T173
Test name
Test status
Simulation time 564607782 ps
CPU time 1.01 seconds
Started Aug 08 05:16:34 PM PDT 24
Finished Aug 08 05:16:35 PM PDT 24
Peak memory 196864 kb
Host smart-c3adc118-49c3-4439-ab52-be2db3df6d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766142784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1766142784
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1708116070
Short name T166
Test name
Test status
Simulation time 367948676 ps
CPU time 0.8 seconds
Started Aug 08 05:16:43 PM PDT 24
Finished Aug 08 05:16:44 PM PDT 24
Peak memory 196928 kb
Host smart-2f0421d5-5f23-4057-b655-cab84dbbcbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708116070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1708116070
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3007006947
Short name T86
Test name
Test status
Simulation time 393340527 ps
CPU time 1 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196992 kb
Host smart-35ba11c2-6739-4074-9077-4f2a289cc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007006947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3007006947
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2448417276
Short name T40
Test name
Test status
Simulation time 138010433197 ps
CPU time 327.94 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:21:45 PM PDT 24
Peak memory 210264 kb
Host smart-06231dcc-653f-4d61-bcd7-ceae6852003d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448417276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2448417276
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.892125752
Short name T181
Test name
Test status
Simulation time 515080478 ps
CPU time 0.84 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 196796 kb
Host smart-73efba1c-92b7-4a53-b113-e90945eaf024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892125752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.892125752
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2702662446
Short name T163
Test name
Test status
Simulation time 389083255 ps
CPU time 0.75 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 196868 kb
Host smart-770fe51e-e818-4037-a1a6-374481083d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702662446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2702662446
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2976564568
Short name T174
Test name
Test status
Simulation time 16838019929 ps
CPU time 6.51 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 192672 kb
Host smart-ede1a324-42a0-411a-a0bc-963b7d937950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976564568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2976564568
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2380744897
Short name T142
Test name
Test status
Simulation time 573076586 ps
CPU time 0.79 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 196904 kb
Host smart-a6917e0a-6f29-49f2-aece-9420a9640b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380744897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2380744897
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3078799228
Short name T170
Test name
Test status
Simulation time 101289158151 ps
CPU time 77.79 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:17:30 PM PDT 24
Peak memory 193264 kb
Host smart-faac9bf8-a518-48c5-a98f-bd30eca55e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078799228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3078799228
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2325802508
Short name T127
Test name
Test status
Simulation time 522886394 ps
CPU time 0.77 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:16:13 PM PDT 24
Peak memory 196900 kb
Host smart-aa8ab6f6-4322-4f83-af8f-4046ee432cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325802508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2325802508
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1527485984
Short name T39
Test name
Test status
Simulation time 23538758527 ps
CPU time 202.31 seconds
Started Aug 08 05:16:18 PM PDT 24
Finished Aug 08 05:19:41 PM PDT 24
Peak memory 198680 kb
Host smart-6dfa2787-7b62-4f20-b5a8-f597cbdc3346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527485984 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1527485984
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1167567383
Short name T187
Test name
Test status
Simulation time 422035978 ps
CPU time 1.14 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 195376 kb
Host smart-27d11e44-d4cd-4585-ac2d-bb153f4d2e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167567383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1167567383
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2567471207
Short name T184
Test name
Test status
Simulation time 29222245152 ps
CPU time 222.24 seconds
Started Aug 08 05:16:22 PM PDT 24
Finished Aug 08 05:20:04 PM PDT 24
Peak memory 197424 kb
Host smart-38fc249d-6e03-4349-949d-970b3a694bfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567471207 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2567471207
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2154652210
Short name T156
Test name
Test status
Simulation time 513533305 ps
CPU time 1.29 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:29 PM PDT 24
Peak memory 196760 kb
Host smart-5de95801-9ab8-4b07-92b6-0666886001aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154652210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2154652210
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2984996879
Short name T158
Test name
Test status
Simulation time 575289202 ps
CPU time 0.83 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:16:28 PM PDT 24
Peak memory 196948 kb
Host smart-477f0421-b6dc-46c2-8e2f-1f6c7a7b7397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984996879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2984996879
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2843214799
Short name T171
Test name
Test status
Simulation time 86954025605 ps
CPU time 236.49 seconds
Started Aug 08 05:16:30 PM PDT 24
Finished Aug 08 05:20:27 PM PDT 24
Peak memory 209272 kb
Host smart-9bcdd2a7-a6f3-48df-a85a-44a244421b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843214799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2843214799
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2782155069
Short name T183
Test name
Test status
Simulation time 470259728 ps
CPU time 0.8 seconds
Started Aug 08 05:16:29 PM PDT 24
Finished Aug 08 05:16:30 PM PDT 24
Peak memory 196852 kb
Host smart-4e072831-faec-422d-8659-69edaaf95269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782155069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2782155069
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1886497559
Short name T164
Test name
Test status
Simulation time 482272516 ps
CPU time 1.28 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 196872 kb
Host smart-0d72ac81-bb39-4075-b0a3-4961d45429cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886497559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1886497559
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.413615718
Short name T178
Test name
Test status
Simulation time 533585656 ps
CPU time 0.74 seconds
Started Aug 08 05:16:03 PM PDT 24
Finished Aug 08 05:16:04 PM PDT 24
Peak memory 196824 kb
Host smart-42d9b542-d43b-484b-89f8-3666849e0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413615718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.413615718
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.335800451
Short name T176
Test name
Test status
Simulation time 521230513 ps
CPU time 0.78 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 196808 kb
Host smart-7b27f8a4-1ccb-4455-847d-688af13cfad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335800451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.335800451
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2026406020
Short name T195
Test name
Test status
Simulation time 8451847026 ps
CPU time 4.37 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:27:21 PM PDT 24
Peak memory 197928 kb
Host smart-139df35f-61da-49a3-9d25-29c300dd38a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026406020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2026406020
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3433068208
Short name T194
Test name
Test status
Simulation time 7935882702 ps
CPU time 12.54 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:28 PM PDT 24
Peak memory 198256 kb
Host smart-f097c85e-efa5-44b5-bfe3-5d2c2c573140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433068208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3433068208
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1851832568
Short name T190
Test name
Test status
Simulation time 583771715 ps
CPU time 1.04 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:16:05 PM PDT 24
Peak memory 196876 kb
Host smart-4fe44297-a776-41e6-87c2-64c12caefb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851832568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1851832568
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1329170717
Short name T155
Test name
Test status
Simulation time 436910816 ps
CPU time 0.76 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 196816 kb
Host smart-0bbe8c2b-855d-4626-afaf-68d68956c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329170717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1329170717
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2627399561
Short name T143
Test name
Test status
Simulation time 523126035 ps
CPU time 1.39 seconds
Started Aug 08 05:16:29 PM PDT 24
Finished Aug 08 05:16:31 PM PDT 24
Peak memory 196852 kb
Host smart-045716bc-8b60-4734-aee6-03a154087967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627399561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2627399561
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3263171500
Short name T180
Test name
Test status
Simulation time 493123691 ps
CPU time 1.28 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:16:28 PM PDT 24
Peak memory 196824 kb
Host smart-b79992ea-c0f1-49b3-a204-f2afb32d2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263171500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3263171500
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.361122478
Short name T390
Test name
Test status
Simulation time 648994407 ps
CPU time 1 seconds
Started Aug 08 04:22:51 PM PDT 24
Finished Aug 08 04:22:52 PM PDT 24
Peak memory 191824 kb
Host smart-e75f023e-cc34-460e-93e0-ced2410506d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361122478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.361122478
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2756483231
Short name T323
Test name
Test status
Simulation time 7203599196 ps
CPU time 18.88 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:58 PM PDT 24
Peak memory 184304 kb
Host smart-9e30b27e-9e9f-478c-bb0e-78ca26338d50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756483231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2756483231
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3552284332
Short name T27
Test name
Test status
Simulation time 1377603889 ps
CPU time 0.88 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:50 PM PDT 24
Peak memory 192836 kb
Host smart-f156cc5e-9377-4ce4-b2f5-100c09296fd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552284332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3552284332
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2827451702
Short name T404
Test name
Test status
Simulation time 444015482 ps
CPU time 0.86 seconds
Started Aug 08 04:22:33 PM PDT 24
Finished Aug 08 04:22:35 PM PDT 24
Peak memory 194708 kb
Host smart-825acaf7-0ffa-478c-b16d-94b0546b729c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827451702 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2827451702
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1240897563
Short name T336
Test name
Test status
Simulation time 547878935 ps
CPU time 0.77 seconds
Started Aug 08 04:22:51 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 193348 kb
Host smart-86266671-62bc-4302-8791-414e1a2d53bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240897563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1240897563
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3936041174
Short name T308
Test name
Test status
Simulation time 389524754 ps
CPU time 0.76 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:40 PM PDT 24
Peak memory 193224 kb
Host smart-fc33263e-fbe9-4827-880e-11570ce9c120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936041174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3936041174
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1019338199
Short name T405
Test name
Test status
Simulation time 460996253 ps
CPU time 1.35 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:28 PM PDT 24
Peak memory 182564 kb
Host smart-3ab180bc-a6e0-43be-9881-362de4f8e86b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019338199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1019338199
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2435959319
Short name T310
Test name
Test status
Simulation time 408353795 ps
CPU time 0.87 seconds
Started Aug 08 04:21:57 PM PDT 24
Finished Aug 08 04:21:58 PM PDT 24
Peak memory 183564 kb
Host smart-22b31a21-8302-4c6b-8b6c-d08b540ee221
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435959319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2435959319
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3940662902
Short name T338
Test name
Test status
Simulation time 2046292334 ps
CPU time 3.48 seconds
Started Aug 08 04:22:38 PM PDT 24
Finished Aug 08 04:22:42 PM PDT 24
Peak memory 194740 kb
Host smart-0fe0280c-24b7-4cf6-874c-992db4d5ba6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940662902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3940662902
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2598585209
Short name T414
Test name
Test status
Simulation time 474075059 ps
CPU time 2.55 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:34 PM PDT 24
Peak memory 197712 kb
Host smart-4a2e02b2-6fd4-474e-8960-7b9f71ee7074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598585209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2598585209
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4181525082
Short name T418
Test name
Test status
Simulation time 4276232888 ps
CPU time 4.2 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:30 PM PDT 24
Peak memory 197320 kb
Host smart-f3923aa8-32c1-4d0c-b59e-7bd007808a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181525082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4181525082
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.86418099
Short name T386
Test name
Test status
Simulation time 567923865 ps
CPU time 1.98 seconds
Started Aug 08 04:21:32 PM PDT 24
Finished Aug 08 04:21:34 PM PDT 24
Peak memory 194556 kb
Host smart-65046bf2-70d5-4c95-ab42-3e157c060a7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86418099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_ali
asing.86418099
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2893772914
Short name T55
Test name
Test status
Simulation time 890604246 ps
CPU time 1.29 seconds
Started Aug 08 04:21:37 PM PDT 24
Finished Aug 08 04:21:39 PM PDT 24
Peak memory 183992 kb
Host smart-daaf439e-d714-4e5c-bc00-4dac474c58df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893772914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2893772914
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1598537091
Short name T410
Test name
Test status
Simulation time 549686648 ps
CPU time 0.89 seconds
Started Aug 08 04:21:56 PM PDT 24
Finished Aug 08 04:21:57 PM PDT 24
Peak memory 195468 kb
Host smart-c5be02b3-536d-4d29-ba32-fd9d011e14ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598537091 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1598537091
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1440971783
Short name T54
Test name
Test status
Simulation time 458542492 ps
CPU time 0.79 seconds
Started Aug 08 04:24:06 PM PDT 24
Finished Aug 08 04:24:07 PM PDT 24
Peak memory 193880 kb
Host smart-a061fd59-73ab-4dc4-bffa-2b7fe0d714c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440971783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1440971783
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2727010609
Short name T396
Test name
Test status
Simulation time 390530521 ps
CPU time 1.08 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 192824 kb
Host smart-22d978b0-afcf-4c87-9dc9-ba03f78c4253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727010609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2727010609
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1302336087
Short name T348
Test name
Test status
Simulation time 512970889 ps
CPU time 0.67 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:50 PM PDT 24
Peak memory 183548 kb
Host smart-b95bf7bf-a956-4f43-90a4-6579e16d390f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302336087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1302336087
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3182655766
Short name T364
Test name
Test status
Simulation time 364322154 ps
CPU time 0.55 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:50 PM PDT 24
Peak memory 183536 kb
Host smart-8d01e17c-b9ae-4aaf-bd0d-8ca49d1ce645
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182655766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3182655766
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2109656416
Short name T407
Test name
Test status
Simulation time 1837497923 ps
CPU time 2.5 seconds
Started Aug 08 04:21:32 PM PDT 24
Finished Aug 08 04:21:35 PM PDT 24
Peak memory 194716 kb
Host smart-0ddd294c-8aff-4b2b-a8f4-40e4b0ee3f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109656416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2109656416
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1469952710
Short name T416
Test name
Test status
Simulation time 549302666 ps
CPU time 1.9 seconds
Started Aug 08 04:22:37 PM PDT 24
Finished Aug 08 04:22:39 PM PDT 24
Peak memory 197608 kb
Host smart-65e0dcb2-6c63-46c6-8e57-5e967cf264f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469952710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1469952710
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2191962388
Short name T340
Test name
Test status
Simulation time 7981468820 ps
CPU time 7.53 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:57 PM PDT 24
Peak memory 198060 kb
Host smart-c31d348f-7b1e-473f-963b-14adf2e89841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191962388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2191962388
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3645703960
Short name T378
Test name
Test status
Simulation time 370728498 ps
CPU time 0.9 seconds
Started Aug 08 04:23:08 PM PDT 24
Finished Aug 08 04:23:09 PM PDT 24
Peak memory 196248 kb
Host smart-e15b54d2-c0b5-41c3-a920-559776b455cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645703960 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3645703960
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1174117346
Short name T60
Test name
Test status
Simulation time 543369244 ps
CPU time 0.75 seconds
Started Aug 08 04:26:05 PM PDT 24
Finished Aug 08 04:26:06 PM PDT 24
Peak memory 193128 kb
Host smart-0ea95fc9-5eee-49b0-91dc-5904edc4bfcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174117346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1174117346
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2403011381
Short name T361
Test name
Test status
Simulation time 517915827 ps
CPU time 0.69 seconds
Started Aug 08 04:26:05 PM PDT 24
Finished Aug 08 04:26:06 PM PDT 24
Peak memory 183592 kb
Host smart-497e126d-ea2c-427a-a944-8f21998cb444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403011381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2403011381
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2858946546
Short name T360
Test name
Test status
Simulation time 2486087148 ps
CPU time 3.48 seconds
Started Aug 08 04:23:36 PM PDT 24
Finished Aug 08 04:23:39 PM PDT 24
Peak memory 195188 kb
Host smart-0010441c-596a-47c2-932b-33f1cef3a336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858946546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2858946546
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1256856319
Short name T334
Test name
Test status
Simulation time 445784441 ps
CPU time 2.44 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 04:27:06 PM PDT 24
Peak memory 197040 kb
Host smart-950cb1f4-f987-451f-9893-952922544483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256856319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1256856319
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4001960436
Short name T28
Test name
Test status
Simulation time 530695238 ps
CPU time 1.47 seconds
Started Aug 08 04:26:20 PM PDT 24
Finished Aug 08 04:26:21 PM PDT 24
Peak memory 196048 kb
Host smart-93f3554f-d622-4114-bf88-8f3919c6b00a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001960436 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4001960436
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1437570954
Short name T403
Test name
Test status
Simulation time 375912853 ps
CPU time 0.7 seconds
Started Aug 08 04:26:08 PM PDT 24
Finished Aug 08 04:26:09 PM PDT 24
Peak memory 192776 kb
Host smart-8639fb93-f8f0-4aea-b612-46778300b77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437570954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1437570954
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2982385478
Short name T398
Test name
Test status
Simulation time 1296953674 ps
CPU time 2.46 seconds
Started Aug 08 04:26:17 PM PDT 24
Finished Aug 08 04:26:19 PM PDT 24
Peak memory 183752 kb
Host smart-41fcc3be-2352-4823-8003-0bfdcca4a810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982385478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2982385478
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2976395037
Short name T387
Test name
Test status
Simulation time 332835922 ps
CPU time 0.91 seconds
Started Aug 08 04:22:56 PM PDT 24
Finished Aug 08 04:22:57 PM PDT 24
Peak memory 196172 kb
Host smart-db14c6fc-46a8-4392-ab55-c5a15e6ca756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976395037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2976395037
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4020590264
Short name T335
Test name
Test status
Simulation time 4197888889 ps
CPU time 6.72 seconds
Started Aug 08 04:24:56 PM PDT 24
Finished Aug 08 04:25:03 PM PDT 24
Peak memory 197936 kb
Host smart-8f1726b1-08c5-482d-bc53-7628990f4671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020590264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4020590264
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3816280759
Short name T296
Test name
Test status
Simulation time 478205607 ps
CPU time 1.43 seconds
Started Aug 08 04:26:53 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 195024 kb
Host smart-d26f5c36-3daa-4623-9d28-38b159158c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816280759 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3816280759
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.475822898
Short name T394
Test name
Test status
Simulation time 531905441 ps
CPU time 1.4 seconds
Started Aug 08 04:22:06 PM PDT 24
Finished Aug 08 04:22:08 PM PDT 24
Peak memory 193056 kb
Host smart-49f3ec14-1ae1-4398-90ca-59b9c13ba6f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475822898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.475822898
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.478788299
Short name T319
Test name
Test status
Simulation time 410250619 ps
CPU time 0.63 seconds
Started Aug 08 04:23:52 PM PDT 24
Finished Aug 08 04:23:52 PM PDT 24
Peak memory 183632 kb
Host smart-24313589-760b-49e2-8a6a-348eeab60a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478788299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.478788299
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1523194223
Short name T415
Test name
Test status
Simulation time 1423453308 ps
CPU time 1.3 seconds
Started Aug 08 04:27:00 PM PDT 24
Finished Aug 08 04:27:01 PM PDT 24
Peak memory 183180 kb
Host smart-51647e24-3e7d-40b3-acd3-2fe6b42dea71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523194223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1523194223
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2695873697
Short name T345
Test name
Test status
Simulation time 673925898 ps
CPU time 1.7 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:28:09 PM PDT 24
Peak memory 198484 kb
Host smart-d5cc4e11-66ab-4e50-96a9-dbb90b0bee93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695873697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2695873697
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2303729756
Short name T423
Test name
Test status
Simulation time 8609085422 ps
CPU time 2.95 seconds
Started Aug 08 04:22:23 PM PDT 24
Finished Aug 08 04:22:26 PM PDT 24
Peak memory 198268 kb
Host smart-36a041b4-f458-4d52-b1d5-27d744f91006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303729756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2303729756
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.534444719
Short name T370
Test name
Test status
Simulation time 459523635 ps
CPU time 1.31 seconds
Started Aug 08 04:25:16 PM PDT 24
Finished Aug 08 04:25:17 PM PDT 24
Peak memory 195680 kb
Host smart-a04d432d-f251-4148-b952-2662ec436548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534444719 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.534444719
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4085560452
Short name T328
Test name
Test status
Simulation time 490650097 ps
CPU time 0.82 seconds
Started Aug 08 04:26:52 PM PDT 24
Finished Aug 08 04:26:53 PM PDT 24
Peak memory 192440 kb
Host smart-25b285d2-16b1-43b7-b251-b945b9ffd3b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085560452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4085560452
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4059808216
Short name T287
Test name
Test status
Simulation time 290906859 ps
CPU time 0.96 seconds
Started Aug 08 04:26:53 PM PDT 24
Finished Aug 08 04:26:54 PM PDT 24
Peak memory 182052 kb
Host smart-bc259cc0-430a-48da-ae18-6e6c530fa25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059808216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4059808216
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3742816750
Short name T380
Test name
Test status
Simulation time 1923827138 ps
CPU time 1.13 seconds
Started Aug 08 04:26:55 PM PDT 24
Finished Aug 08 04:26:56 PM PDT 24
Peak memory 194372 kb
Host smart-33971952-9103-466b-89dc-9790820d2ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742816750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3742816750
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2606892600
Short name T374
Test name
Test status
Simulation time 487739276 ps
CPU time 2.51 seconds
Started Aug 08 04:22:59 PM PDT 24
Finished Aug 08 04:23:01 PM PDT 24
Peak memory 198440 kb
Host smart-62ceee82-d20b-4266-890a-c7c2cdec245b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606892600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2606892600
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.349986344
Short name T196
Test name
Test status
Simulation time 385006197 ps
CPU time 1.2 seconds
Started Aug 08 04:26:54 PM PDT 24
Finished Aug 08 04:26:56 PM PDT 24
Peak memory 195188 kb
Host smart-5d1d6d06-f823-4b4b-8d3e-6ca70400706d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349986344 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.349986344
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2343087039
Short name T58
Test name
Test status
Simulation time 405069443 ps
CPU time 0.91 seconds
Started Aug 08 04:24:46 PM PDT 24
Finished Aug 08 04:24:47 PM PDT 24
Peak memory 192076 kb
Host smart-7e74ebbc-3eb6-4703-bb77-aaa34293f771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343087039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2343087039
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.856650358
Short name T291
Test name
Test status
Simulation time 529326145 ps
CPU time 0.77 seconds
Started Aug 08 04:25:31 PM PDT 24
Finished Aug 08 04:25:32 PM PDT 24
Peak memory 183632 kb
Host smart-11399880-2df0-4326-8db3-7a2f312108f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856650358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.856650358
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3007988652
Short name T69
Test name
Test status
Simulation time 1327553381 ps
CPU time 2.24 seconds
Started Aug 08 04:24:16 PM PDT 24
Finished Aug 08 04:24:18 PM PDT 24
Peak memory 183596 kb
Host smart-c3a3ec1c-5815-44d0-b50a-1b4f908383eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007988652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3007988652
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4165842666
Short name T302
Test name
Test status
Simulation time 434020790 ps
CPU time 2.25 seconds
Started Aug 08 04:23:18 PM PDT 24
Finished Aug 08 04:23:20 PM PDT 24
Peak memory 198500 kb
Host smart-9da71d74-a8df-4950-ba72-9f7a848f8d42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165842666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4165842666
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1312903481
Short name T327
Test name
Test status
Simulation time 4448426968 ps
CPU time 2.63 seconds
Started Aug 08 04:24:38 PM PDT 24
Finished Aug 08 04:24:41 PM PDT 24
Peak memory 197860 kb
Host smart-99ffa865-6065-456a-9afd-b9bde5c87d80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312903481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1312903481
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3931396659
Short name T333
Test name
Test status
Simulation time 325825695 ps
CPU time 1.16 seconds
Started Aug 08 04:24:37 PM PDT 24
Finished Aug 08 04:24:39 PM PDT 24
Peak memory 195952 kb
Host smart-94ad194c-8db7-4e46-a17f-685c157ec52c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931396659 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3931396659
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2486862288
Short name T424
Test name
Test status
Simulation time 340979146 ps
CPU time 0.79 seconds
Started Aug 08 04:22:11 PM PDT 24
Finished Aug 08 04:22:12 PM PDT 24
Peak memory 193116 kb
Host smart-bf3a1b35-f7c2-4fd0-9fe3-da15d83dfce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486862288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2486862288
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2017690399
Short name T376
Test name
Test status
Simulation time 369311502 ps
CPU time 0.64 seconds
Started Aug 08 04:25:43 PM PDT 24
Finished Aug 08 04:25:43 PM PDT 24
Peak memory 183652 kb
Host smart-429cfa72-1d1f-4ad7-a4eb-aff91b6ee343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017690399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2017690399
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2039312912
Short name T375
Test name
Test status
Simulation time 2795708101 ps
CPU time 3.71 seconds
Started Aug 08 04:26:54 PM PDT 24
Finished Aug 08 04:26:58 PM PDT 24
Peak memory 193056 kb
Host smart-d51bb5e4-f2c4-4dec-90ad-7ec66d15e0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039312912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2039312912
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3293096336
Short name T305
Test name
Test status
Simulation time 605096265 ps
CPU time 3.37 seconds
Started Aug 08 04:23:45 PM PDT 24
Finished Aug 08 04:23:49 PM PDT 24
Peak memory 198488 kb
Host smart-6b1d2728-a69e-4649-8f75-9aed9b503c92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293096336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3293096336
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2707332637
Short name T316
Test name
Test status
Simulation time 471347347 ps
CPU time 0.9 seconds
Started Aug 08 04:26:42 PM PDT 24
Finished Aug 08 04:26:43 PM PDT 24
Peak memory 198168 kb
Host smart-6d209fca-e36c-4276-9e9a-0b01047c2c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707332637 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2707332637
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4051062812
Short name T67
Test name
Test status
Simulation time 345043935 ps
CPU time 1.17 seconds
Started Aug 08 04:25:08 PM PDT 24
Finished Aug 08 04:25:09 PM PDT 24
Peak memory 193104 kb
Host smart-65a7bdf4-6df6-4ad8-9094-5d833f7450f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051062812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4051062812
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1708863644
Short name T289
Test name
Test status
Simulation time 339396036 ps
CPU time 0.66 seconds
Started Aug 08 04:26:05 PM PDT 24
Finished Aug 08 04:26:05 PM PDT 24
Peak memory 192868 kb
Host smart-2ff7f3e3-d0e2-4d3e-a598-2c0c25ceb34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708863644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1708863644
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1035113684
Short name T66
Test name
Test status
Simulation time 2768948509 ps
CPU time 7.92 seconds
Started Aug 08 04:26:14 PM PDT 24
Finished Aug 08 04:26:22 PM PDT 24
Peak memory 194136 kb
Host smart-692aa5bc-6e36-4f24-adb3-8af0afc3690d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035113684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1035113684
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1598109133
Short name T325
Test name
Test status
Simulation time 593601146 ps
CPU time 2.84 seconds
Started Aug 08 04:27:09 PM PDT 24
Finished Aug 08 04:27:12 PM PDT 24
Peak memory 198380 kb
Host smart-32890809-b6c2-4848-8ca4-21cbc87badcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598109133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1598109133
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4054065604
Short name T379
Test name
Test status
Simulation time 4987951213 ps
CPU time 1.19 seconds
Started Aug 08 04:26:41 PM PDT 24
Finished Aug 08 04:26:43 PM PDT 24
Peak memory 196464 kb
Host smart-3e9856db-70ab-46a6-8b5f-be9145b8ab86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054065604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4054065604
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1949850388
Short name T318
Test name
Test status
Simulation time 303989973 ps
CPU time 0.86 seconds
Started Aug 08 04:23:34 PM PDT 24
Finished Aug 08 04:23:35 PM PDT 24
Peak memory 195404 kb
Host smart-020826e4-9710-44fc-8c7e-1d006c330471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949850388 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1949850388
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1671802898
Short name T382
Test name
Test status
Simulation time 476271558 ps
CPU time 0.83 seconds
Started Aug 08 04:21:41 PM PDT 24
Finished Aug 08 04:21:42 PM PDT 24
Peak memory 193852 kb
Host smart-b2e49df4-52fe-44ae-b6bf-26336d0fb6c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671802898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1671802898
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2675907477
Short name T356
Test name
Test status
Simulation time 505987193 ps
CPU time 0.6 seconds
Started Aug 08 04:25:09 PM PDT 24
Finished Aug 08 04:25:10 PM PDT 24
Peak memory 182900 kb
Host smart-60b89ccf-249c-422e-b26d-fb92c0a9ec68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675907477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2675907477
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3137895081
Short name T388
Test name
Test status
Simulation time 1269351202 ps
CPU time 1.27 seconds
Started Aug 08 04:21:45 PM PDT 24
Finished Aug 08 04:21:46 PM PDT 24
Peak memory 193460 kb
Host smart-090e5c5b-ebab-47c9-a703-e84d8d02ff03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137895081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3137895081
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3685287027
Short name T295
Test name
Test status
Simulation time 592158029 ps
CPU time 1.65 seconds
Started Aug 08 04:26:16 PM PDT 24
Finished Aug 08 04:26:18 PM PDT 24
Peak memory 198436 kb
Host smart-f5613eec-2fe2-49a7-a340-28d8261b1ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685287027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3685287027
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2938777025
Short name T365
Test name
Test status
Simulation time 4132493377 ps
CPU time 3.83 seconds
Started Aug 08 04:21:45 PM PDT 24
Finished Aug 08 04:21:49 PM PDT 24
Peak memory 197796 kb
Host smart-8c6c93a6-f1ba-4ae1-a27d-cbc3213034b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938777025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2938777025
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2532474973
Short name T303
Test name
Test status
Simulation time 570246741 ps
CPU time 0.94 seconds
Started Aug 08 04:26:04 PM PDT 24
Finished Aug 08 04:26:05 PM PDT 24
Peak memory 196816 kb
Host smart-7faf696f-1ff9-49f7-abd6-5195a591d498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532474973 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2532474973
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1675879067
Short name T63
Test name
Test status
Simulation time 476202472 ps
CPU time 1.19 seconds
Started Aug 08 04:26:45 PM PDT 24
Finished Aug 08 04:26:46 PM PDT 24
Peak memory 191408 kb
Host smart-904e5ce9-3065-467d-a9bd-715953719e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675879067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1675879067
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2416758488
Short name T371
Test name
Test status
Simulation time 459031829 ps
CPU time 1.16 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 04:27:05 PM PDT 24
Peak memory 182184 kb
Host smart-cc8bd82b-25e7-4ddf-9677-256679baf9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416758488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2416758488
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2247208096
Short name T352
Test name
Test status
Simulation time 1758007112 ps
CPU time 1.04 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:27:05 PM PDT 24
Peak memory 192052 kb
Host smart-fde46c1d-5bb6-4fe1-a551-f381dee4d8fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247208096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2247208096
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3616469695
Short name T341
Test name
Test status
Simulation time 360611660 ps
CPU time 2.3 seconds
Started Aug 08 04:21:55 PM PDT 24
Finished Aug 08 04:21:58 PM PDT 24
Peak memory 198488 kb
Host smart-7f7315ae-2bd4-48f5-be80-8729cb425fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616469695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3616469695
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1876198048
Short name T354
Test name
Test status
Simulation time 9196950804 ps
CPU time 4.13 seconds
Started Aug 08 04:22:55 PM PDT 24
Finished Aug 08 04:22:59 PM PDT 24
Peak memory 197988 kb
Host smart-56f9070b-e206-4018-8e92-0e2497ca08e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876198048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1876198048
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.284752900
Short name T301
Test name
Test status
Simulation time 564707676 ps
CPU time 1.37 seconds
Started Aug 08 04:26:17 PM PDT 24
Finished Aug 08 04:26:19 PM PDT 24
Peak memory 197184 kb
Host smart-d621c3b0-c64b-4541-9a37-40a1369a0167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284752900 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.284752900
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2755493368
Short name T342
Test name
Test status
Simulation time 464674803 ps
CPU time 1.33 seconds
Started Aug 08 04:22:05 PM PDT 24
Finished Aug 08 04:22:07 PM PDT 24
Peak memory 192896 kb
Host smart-122bceed-0312-4305-bc32-ed7f726ff797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755493368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2755493368
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3014064284
Short name T412
Test name
Test status
Simulation time 418979167 ps
CPU time 1.09 seconds
Started Aug 08 04:23:08 PM PDT 24
Finished Aug 08 04:23:09 PM PDT 24
Peak memory 192844 kb
Host smart-37d7e559-57fe-47ce-acb1-02bf7633162a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014064284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3014064284
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.674777427
Short name T65
Test name
Test status
Simulation time 1472028393 ps
CPU time 1.22 seconds
Started Aug 08 04:23:52 PM PDT 24
Finished Aug 08 04:23:54 PM PDT 24
Peak memory 193896 kb
Host smart-3f369579-3265-48a9-ba06-3c48c620a223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674777427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.674777427
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.833613426
Short name T330
Test name
Test status
Simulation time 454858478 ps
CPU time 1.41 seconds
Started Aug 08 04:23:02 PM PDT 24
Finished Aug 08 04:23:04 PM PDT 24
Peak memory 198464 kb
Host smart-740e5b3d-7046-4fc0-b2fe-5f3c1cda5813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833613426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.833613426
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1219930270
Short name T381
Test name
Test status
Simulation time 4431553888 ps
CPU time 7.87 seconds
Started Aug 08 04:24:30 PM PDT 24
Finished Aug 08 04:24:38 PM PDT 24
Peak memory 197788 kb
Host smart-49d529c1-be76-402f-ab55-399873ad810d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219930270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1219930270
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2765501317
Short name T62
Test name
Test status
Simulation time 623295363 ps
CPU time 1.02 seconds
Started Aug 08 04:25:00 PM PDT 24
Finished Aug 08 04:25:01 PM PDT 24
Peak memory 183740 kb
Host smart-f234e0f9-2298-4703-b28e-ca8d3776764a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765501317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2765501317
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1489451053
Short name T59
Test name
Test status
Simulation time 13876205008 ps
CPU time 34.14 seconds
Started Aug 08 04:26:20 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 195192 kb
Host smart-d47a7f1e-ef2b-4f16-8866-bccc7943a9a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489451053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1489451053
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1095744619
Short name T349
Test name
Test status
Simulation time 853262035 ps
CPU time 1.85 seconds
Started Aug 08 04:25:08 PM PDT 24
Finished Aug 08 04:25:10 PM PDT 24
Peak memory 192004 kb
Host smart-a1192532-3ac1-4d6e-b25a-661de33f7ed9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095744619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1095744619
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1794973205
Short name T307
Test name
Test status
Simulation time 508309170 ps
CPU time 1.41 seconds
Started Aug 08 04:23:54 PM PDT 24
Finished Aug 08 04:23:55 PM PDT 24
Peak memory 195976 kb
Host smart-4869df0a-9b66-44f9-8d14-ee8bffe6c0d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794973205 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1794973205
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1800292888
Short name T51
Test name
Test status
Simulation time 362918655 ps
CPU time 0.74 seconds
Started Aug 08 04:24:25 PM PDT 24
Finished Aug 08 04:24:26 PM PDT 24
Peak memory 193000 kb
Host smart-475e6c6a-4a4a-42a3-a961-8702b46f5ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800292888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1800292888
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.92371260
Short name T351
Test name
Test status
Simulation time 455703783 ps
CPU time 1.17 seconds
Started Aug 08 04:22:05 PM PDT 24
Finished Aug 08 04:22:07 PM PDT 24
Peak memory 192560 kb
Host smart-4e4f0e6c-f3ad-419b-82c2-ddc585bdf9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92371260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.92371260
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4158234691
Short name T292
Test name
Test status
Simulation time 362102343 ps
CPU time 0.63 seconds
Started Aug 08 04:23:45 PM PDT 24
Finished Aug 08 04:23:46 PM PDT 24
Peak memory 182784 kb
Host smart-48c1983c-cec6-411c-ac4f-6621e2898c34
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158234691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4158234691
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3883115171
Short name T339
Test name
Test status
Simulation time 369021899 ps
CPU time 0.65 seconds
Started Aug 08 04:23:41 PM PDT 24
Finished Aug 08 04:23:41 PM PDT 24
Peak memory 183528 kb
Host smart-216d553d-ee91-4b69-917a-10f54c1b3b58
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883115171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3883115171
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1331773637
Short name T411
Test name
Test status
Simulation time 1442210302 ps
CPU time 1.09 seconds
Started Aug 08 04:24:48 PM PDT 24
Finished Aug 08 04:24:50 PM PDT 24
Peak memory 193544 kb
Host smart-dc520a86-2ea6-46e1-af8b-4126c40ef038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331773637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1331773637
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3837055339
Short name T421
Test name
Test status
Simulation time 670605210 ps
CPU time 1.69 seconds
Started Aug 08 04:21:39 PM PDT 24
Finished Aug 08 04:21:41 PM PDT 24
Peak memory 198452 kb
Host smart-2a7629ba-4350-4b74-b6d2-5a55fcf90c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837055339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3837055339
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1892308401
Short name T326
Test name
Test status
Simulation time 8706554947 ps
CPU time 4.23 seconds
Started Aug 08 04:21:37 PM PDT 24
Finished Aug 08 04:21:41 PM PDT 24
Peak memory 198244 kb
Host smart-beee3514-c4b7-4580-860f-15dbe5827589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892308401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1892308401
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.119077437
Short name T357
Test name
Test status
Simulation time 473914516 ps
CPU time 0.88 seconds
Started Aug 08 04:27:58 PM PDT 24
Finished Aug 08 04:27:59 PM PDT 24
Peak memory 192460 kb
Host smart-f47e79c1-9480-44dd-b8fd-fcc86ee468cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119077437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.119077437
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1975236446
Short name T315
Test name
Test status
Simulation time 331906016 ps
CPU time 0.75 seconds
Started Aug 08 04:26:20 PM PDT 24
Finished Aug 08 04:26:21 PM PDT 24
Peak memory 183540 kb
Host smart-3146f29a-d5b1-4374-9205-56011ab37c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975236446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1975236446
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3847500043
Short name T347
Test name
Test status
Simulation time 517541176 ps
CPU time 0.78 seconds
Started Aug 08 04:22:05 PM PDT 24
Finished Aug 08 04:22:06 PM PDT 24
Peak memory 192120 kb
Host smart-2d4b9786-553a-4b0f-adbb-71850fd6be6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847500043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3847500043
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3405190607
Short name T288
Test name
Test status
Simulation time 296869916 ps
CPU time 0.68 seconds
Started Aug 08 04:23:52 PM PDT 24
Finished Aug 08 04:23:53 PM PDT 24
Peak memory 183656 kb
Host smart-ac533d1f-8c5a-4f17-8380-7af72a68111d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405190607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3405190607
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1906140665
Short name T294
Test name
Test status
Simulation time 456228686 ps
CPU time 0.74 seconds
Started Aug 08 04:24:03 PM PDT 24
Finished Aug 08 04:24:04 PM PDT 24
Peak memory 183632 kb
Host smart-02344269-8491-4507-bf16-b23765a732a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906140665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1906140665
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2388909779
Short name T368
Test name
Test status
Simulation time 370948394 ps
CPU time 0.62 seconds
Started Aug 08 04:22:30 PM PDT 24
Finished Aug 08 04:22:31 PM PDT 24
Peak memory 183648 kb
Host smart-973f4f0f-bd21-4529-a04f-081c2099f96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388909779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2388909779
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3733433629
Short name T419
Test name
Test status
Simulation time 473310712 ps
CPU time 0.63 seconds
Started Aug 08 04:21:52 PM PDT 24
Finished Aug 08 04:21:53 PM PDT 24
Peak memory 183656 kb
Host smart-2b2dc377-0ede-4279-98c1-265f139b3ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733433629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3733433629
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.27945592
Short name T401
Test name
Test status
Simulation time 350100522 ps
CPU time 0.65 seconds
Started Aug 08 04:22:32 PM PDT 24
Finished Aug 08 04:22:33 PM PDT 24
Peak memory 183636 kb
Host smart-564eeec9-ed1b-471c-ad39-f4f1c246a31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27945592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.27945592
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4169248424
Short name T297
Test name
Test status
Simulation time 418509700 ps
CPU time 0.69 seconds
Started Aug 08 04:21:53 PM PDT 24
Finished Aug 08 04:21:54 PM PDT 24
Peak memory 192844 kb
Host smart-cf9c604c-b297-4b4b-b7d1-466db6017597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169248424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4169248424
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2881312354
Short name T317
Test name
Test status
Simulation time 435500501 ps
CPU time 0.62 seconds
Started Aug 08 04:24:34 PM PDT 24
Finished Aug 08 04:24:35 PM PDT 24
Peak memory 183648 kb
Host smart-4e851a2e-0fdb-406d-860c-244e68070a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881312354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2881312354
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.417376688
Short name T399
Test name
Test status
Simulation time 776285908 ps
CPU time 0.92 seconds
Started Aug 08 04:23:54 PM PDT 24
Finished Aug 08 04:23:55 PM PDT 24
Peak memory 183988 kb
Host smart-7029c42e-a626-4eda-b0df-d1bf1131e5cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417376688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.417376688
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1457326489
Short name T413
Test name
Test status
Simulation time 7241748212 ps
CPU time 15.37 seconds
Started Aug 08 04:26:54 PM PDT 24
Finished Aug 08 04:27:10 PM PDT 24
Peak memory 191064 kb
Host smart-68f8b7f9-63f1-4619-b587-8140bf87f48a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457326489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1457326489
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4085447894
Short name T402
Test name
Test status
Simulation time 1212832378 ps
CPU time 0.87 seconds
Started Aug 08 04:24:06 PM PDT 24
Finished Aug 08 04:24:07 PM PDT 24
Peak memory 183636 kb
Host smart-b9c3830b-5c75-4507-8b29-c7fa9be9f341
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085447894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4085447894
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1923350933
Short name T409
Test name
Test status
Simulation time 351405233 ps
CPU time 0.84 seconds
Started Aug 08 04:24:44 PM PDT 24
Finished Aug 08 04:24:45 PM PDT 24
Peak memory 194324 kb
Host smart-fa444fe2-c32e-4e8b-8c6c-db38eaaae15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923350933 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1923350933
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2536234294
Short name T33
Test name
Test status
Simulation time 362540400 ps
CPU time 0.81 seconds
Started Aug 08 04:25:19 PM PDT 24
Finished Aug 08 04:25:20 PM PDT 24
Peak memory 192272 kb
Host smart-0be50481-ac77-4af4-a47d-2c382aa29c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536234294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2536234294
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2260760728
Short name T312
Test name
Test status
Simulation time 436654502 ps
CPU time 0.71 seconds
Started Aug 08 04:26:31 PM PDT 24
Finished Aug 08 04:26:32 PM PDT 24
Peak memory 192480 kb
Host smart-cfa70dc5-d59d-4915-a4ee-534c5b2110d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260760728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2260760728
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2278232756
Short name T290
Test name
Test status
Simulation time 404113221 ps
CPU time 0.58 seconds
Started Aug 08 04:24:37 PM PDT 24
Finished Aug 08 04:24:38 PM PDT 24
Peak memory 183540 kb
Host smart-58f1e42d-b6a6-4ba3-91b8-eaeac0147bdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278232756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2278232756
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1954628712
Short name T314
Test name
Test status
Simulation time 465742546 ps
CPU time 1.19 seconds
Started Aug 08 04:26:28 PM PDT 24
Finished Aug 08 04:26:29 PM PDT 24
Peak memory 183544 kb
Host smart-859c719a-48c5-4715-b400-a19054e61d78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954628712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1954628712
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3005327063
Short name T385
Test name
Test status
Simulation time 1793409776 ps
CPU time 1.18 seconds
Started Aug 08 04:28:09 PM PDT 24
Finished Aug 08 04:28:10 PM PDT 24
Peak memory 192852 kb
Host smart-2ea6da02-f4a4-4ca4-b9b5-89707f4092d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005327063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3005327063
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1036873406
Short name T304
Test name
Test status
Simulation time 607106127 ps
CPU time 1.62 seconds
Started Aug 08 04:23:11 PM PDT 24
Finished Aug 08 04:23:13 PM PDT 24
Peak memory 198464 kb
Host smart-e1480cc5-e2b5-4aa0-80e3-6efdf9005dab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036873406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1036873406
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.302404545
Short name T192
Test name
Test status
Simulation time 7585157077 ps
CPU time 6.07 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:38 PM PDT 24
Peak memory 198120 kb
Host smart-01f50a8f-7fec-4777-922c-5a5213e6d4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302404545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.302404545
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3876284682
Short name T331
Test name
Test status
Simulation time 390716688 ps
CPU time 0.57 seconds
Started Aug 08 04:26:33 PM PDT 24
Finished Aug 08 04:26:33 PM PDT 24
Peak memory 192760 kb
Host smart-109e07dd-b505-49ff-bdc0-b8b2b487c56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876284682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3876284682
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1275685038
Short name T311
Test name
Test status
Simulation time 294274730 ps
CPU time 0.65 seconds
Started Aug 08 04:26:20 PM PDT 24
Finished Aug 08 04:26:21 PM PDT 24
Peak memory 183540 kb
Host smart-53a42db2-27e2-4848-8ee4-24d5fd74697f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275685038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1275685038
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.876075692
Short name T286
Test name
Test status
Simulation time 367509938 ps
CPU time 0.78 seconds
Started Aug 08 04:22:32 PM PDT 24
Finished Aug 08 04:22:32 PM PDT 24
Peak memory 183604 kb
Host smart-e0805ac5-857f-489d-ac52-818c9c4e7930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876075692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.876075692
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3528563830
Short name T400
Test name
Test status
Simulation time 286923537 ps
CPU time 0.94 seconds
Started Aug 08 04:22:26 PM PDT 24
Finished Aug 08 04:22:27 PM PDT 24
Peak memory 183624 kb
Host smart-d3961d96-8f0b-4207-ac32-952134eb70a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528563830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3528563830
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2403100589
Short name T392
Test name
Test status
Simulation time 609742102 ps
CPU time 0.65 seconds
Started Aug 08 04:23:02 PM PDT 24
Finished Aug 08 04:23:03 PM PDT 24
Peak memory 183648 kb
Host smart-4a18e544-3b36-4bb3-9ca5-e180e7285d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403100589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2403100589
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1426268332
Short name T384
Test name
Test status
Simulation time 388680654 ps
CPU time 0.59 seconds
Started Aug 08 04:22:28 PM PDT 24
Finished Aug 08 04:22:29 PM PDT 24
Peak memory 183624 kb
Host smart-a0054d82-0ea1-48bd-ac19-03804e170cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426268332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1426268332
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2758469275
Short name T299
Test name
Test status
Simulation time 513267928 ps
CPU time 0.75 seconds
Started Aug 08 04:23:51 PM PDT 24
Finished Aug 08 04:23:52 PM PDT 24
Peak memory 192852 kb
Host smart-a6bbe3bd-66ee-4ece-92f6-af6d18c9630e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758469275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2758469275
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3322545446
Short name T298
Test name
Test status
Simulation time 499239987 ps
CPU time 0.76 seconds
Started Aug 08 04:26:17 PM PDT 24
Finished Aug 08 04:26:18 PM PDT 24
Peak memory 183556 kb
Host smart-ac7cfc5f-2e2f-4a0b-ab8b-a662cd738997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322545446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3322545446
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.763028912
Short name T362
Test name
Test status
Simulation time 509865833 ps
CPU time 0.98 seconds
Started Aug 08 04:26:18 PM PDT 24
Finished Aug 08 04:26:20 PM PDT 24
Peak memory 192024 kb
Host smart-2f59d9e9-9fae-4d3e-8403-dd14427fd129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763028912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.763028912
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3197254364
Short name T372
Test name
Test status
Simulation time 469397605 ps
CPU time 1.19 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:17 PM PDT 24
Peak memory 183684 kb
Host smart-952dc853-c262-444d-a602-49b8198fd4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197254364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3197254364
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3864495084
Short name T57
Test name
Test status
Simulation time 461606152 ps
CPU time 0.75 seconds
Started Aug 08 04:22:34 PM PDT 24
Finished Aug 08 04:22:35 PM PDT 24
Peak memory 192936 kb
Host smart-5b455a2b-0bf6-41e3-bf41-5ccfce986b31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864495084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3864495084
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4211727337
Short name T320
Test name
Test status
Simulation time 14061239736 ps
CPU time 16.24 seconds
Started Aug 08 04:25:19 PM PDT 24
Finished Aug 08 04:25:36 PM PDT 24
Peak memory 192180 kb
Host smart-ef8fa08d-b51f-4b21-9ca5-032c140e4d47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211727337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4211727337
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4068611905
Short name T34
Test name
Test status
Simulation time 950486233 ps
CPU time 1.88 seconds
Started Aug 08 04:24:22 PM PDT 24
Finished Aug 08 04:24:24 PM PDT 24
Peak memory 192084 kb
Host smart-2b7f7f7d-5043-4e6b-b212-cf2de72d7959
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068611905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4068611905
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3607949300
Short name T358
Test name
Test status
Simulation time 486410555 ps
CPU time 1.11 seconds
Started Aug 08 04:24:33 PM PDT 24
Finished Aug 08 04:24:35 PM PDT 24
Peak memory 198280 kb
Host smart-ef98b137-f10d-483a-b2cd-225331de3d93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607949300 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3607949300
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1923694151
Short name T61
Test name
Test status
Simulation time 435474914 ps
CPU time 1.25 seconds
Started Aug 08 04:25:13 PM PDT 24
Finished Aug 08 04:25:15 PM PDT 24
Peak memory 193000 kb
Host smart-fab07645-7549-4b58-87b4-10db0281c04a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923694151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1923694151
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.692271457
Short name T353
Test name
Test status
Simulation time 508397520 ps
CPU time 1.29 seconds
Started Aug 08 04:23:42 PM PDT 24
Finished Aug 08 04:23:43 PM PDT 24
Peak memory 192820 kb
Host smart-0858e396-45fb-4f36-b22f-87fabea355fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692271457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.692271457
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.714149715
Short name T322
Test name
Test status
Simulation time 409596967 ps
CPU time 0.8 seconds
Started Aug 08 04:24:12 PM PDT 24
Finished Aug 08 04:24:13 PM PDT 24
Peak memory 183912 kb
Host smart-aa3fde17-e92c-46e1-865a-ff594839ae71
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714149715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.714149715
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3569597097
Short name T293
Test name
Test status
Simulation time 439240467 ps
CPU time 0.72 seconds
Started Aug 08 04:23:54 PM PDT 24
Finished Aug 08 04:23:55 PM PDT 24
Peak memory 183900 kb
Host smart-c9bde10d-2490-4ffe-be75-fd8635c6268d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569597097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3569597097
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3021944681
Short name T70
Test name
Test status
Simulation time 1585904026 ps
CPU time 1.42 seconds
Started Aug 08 04:27:07 PM PDT 24
Finished Aug 08 04:27:08 PM PDT 24
Peak memory 192804 kb
Host smart-be89e08b-8c53-4e98-93fa-703f8284241a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021944681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3021944681
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4126389197
Short name T306
Test name
Test status
Simulation time 596692496 ps
CPU time 1.46 seconds
Started Aug 08 04:22:12 PM PDT 24
Finished Aug 08 04:22:13 PM PDT 24
Peak memory 198444 kb
Host smart-ee5006a4-b30c-4e45-97ce-39738f6c7391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126389197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4126389197
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1282128449
Short name T191
Test name
Test status
Simulation time 8372452498 ps
CPU time 7.07 seconds
Started Aug 08 04:23:21 PM PDT 24
Finished Aug 08 04:23:28 PM PDT 24
Peak memory 198048 kb
Host smart-8601258e-25ba-4be9-9bb4-63bf689803b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282128449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1282128449
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.481791727
Short name T363
Test name
Test status
Simulation time 401151883 ps
CPU time 0.69 seconds
Started Aug 08 04:22:31 PM PDT 24
Finished Aug 08 04:22:32 PM PDT 24
Peak memory 183648 kb
Host smart-0d57db20-789f-40ec-9d53-97449b88bd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481791727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.481791727
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2721348587
Short name T420
Test name
Test status
Simulation time 392165489 ps
CPU time 0.83 seconds
Started Aug 08 04:22:26 PM PDT 24
Finished Aug 08 04:22:27 PM PDT 24
Peak memory 183624 kb
Host smart-fe619c9b-1255-4c93-a796-14204321110f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721348587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2721348587
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3974571997
Short name T408
Test name
Test status
Simulation time 464967486 ps
CPU time 1.24 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:19 PM PDT 24
Peak memory 192868 kb
Host smart-fe33ea00-3a75-4844-9348-e77103f0c59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974571997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3974571997
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.170388310
Short name T313
Test name
Test status
Simulation time 304466908 ps
CPU time 0.65 seconds
Started Aug 08 04:22:20 PM PDT 24
Finished Aug 08 04:22:21 PM PDT 24
Peak memory 192824 kb
Host smart-f6b9bc5a-2348-4179-ac76-ee4fbedaada4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170388310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.170388310
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.512046203
Short name T350
Test name
Test status
Simulation time 486671083 ps
CPU time 1.21 seconds
Started Aug 08 04:26:56 PM PDT 24
Finished Aug 08 04:26:57 PM PDT 24
Peak memory 192004 kb
Host smart-cd05b453-74c9-4509-93c5-aac24a2db697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512046203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.512046203
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.640925504
Short name T373
Test name
Test status
Simulation time 350440348 ps
CPU time 0.66 seconds
Started Aug 08 04:22:28 PM PDT 24
Finished Aug 08 04:22:29 PM PDT 24
Peak memory 184000 kb
Host smart-2f328040-a93d-442d-87e6-4815a0a9b320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640925504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.640925504
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1206952828
Short name T397
Test name
Test status
Simulation time 373871233 ps
CPU time 1.16 seconds
Started Aug 08 04:27:39 PM PDT 24
Finished Aug 08 04:27:41 PM PDT 24
Peak memory 182824 kb
Host smart-3456746b-88a1-470b-a168-5da709b854f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206952828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1206952828
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1218540187
Short name T321
Test name
Test status
Simulation time 370606655 ps
CPU time 1.03 seconds
Started Aug 08 04:27:40 PM PDT 24
Finished Aug 08 04:27:41 PM PDT 24
Peak memory 192724 kb
Host smart-d9a59a5a-3e22-45a6-9c9b-2e3ab5281729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218540187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1218540187
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3013084428
Short name T343
Test name
Test status
Simulation time 371361074 ps
CPU time 1.21 seconds
Started Aug 08 04:21:58 PM PDT 24
Finished Aug 08 04:21:59 PM PDT 24
Peak memory 192904 kb
Host smart-c430d71d-2f7f-4b12-8da1-f27919892a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013084428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3013084428
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2447161018
Short name T337
Test name
Test status
Simulation time 397765739 ps
CPU time 0.61 seconds
Started Aug 08 04:26:35 PM PDT 24
Finished Aug 08 04:26:36 PM PDT 24
Peak memory 183656 kb
Host smart-6cf86f0d-1711-4217-8761-a8e87a7b7677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447161018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2447161018
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.850297394
Short name T422
Test name
Test status
Simulation time 395888695 ps
CPU time 1.06 seconds
Started Aug 08 04:23:45 PM PDT 24
Finished Aug 08 04:23:46 PM PDT 24
Peak memory 197044 kb
Host smart-0c62009b-d453-4712-8da1-3eacc857a67d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850297394 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.850297394
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.725513667
Short name T56
Test name
Test status
Simulation time 481013929 ps
CPU time 1.19 seconds
Started Aug 08 04:24:54 PM PDT 24
Finished Aug 08 04:24:55 PM PDT 24
Peak memory 193144 kb
Host smart-d6ddd792-3f34-4c40-8710-66201a9d6369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725513667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.725513667
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.140532762
Short name T391
Test name
Test status
Simulation time 312385436 ps
CPU time 0.72 seconds
Started Aug 08 04:23:19 PM PDT 24
Finished Aug 08 04:23:20 PM PDT 24
Peak memory 183604 kb
Host smart-e674f091-4f09-4ed7-b4f6-9f2a159eb358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140532762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.140532762
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.414535196
Short name T366
Test name
Test status
Simulation time 1078089068 ps
CPU time 1.28 seconds
Started Aug 08 04:25:16 PM PDT 24
Finished Aug 08 04:25:17 PM PDT 24
Peak memory 193356 kb
Host smart-0866d4fe-7752-4bf2-94f4-d59209b7379e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414535196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.414535196
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1488758587
Short name T406
Test name
Test status
Simulation time 593223910 ps
CPU time 3.12 seconds
Started Aug 08 04:25:13 PM PDT 24
Finished Aug 08 04:25:16 PM PDT 24
Peak memory 198412 kb
Host smart-db19c9b8-5e26-48f6-b6d7-d437ed1e4447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488758587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1488758587
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.278872398
Short name T193
Test name
Test status
Simulation time 8418606413 ps
CPU time 14.18 seconds
Started Aug 08 04:23:09 PM PDT 24
Finished Aug 08 04:23:23 PM PDT 24
Peak memory 198192 kb
Host smart-dbc703ac-7b7a-46b2-8735-d9ffc60a4dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278872398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.278872398
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.907309689
Short name T389
Test name
Test status
Simulation time 685517658 ps
CPU time 0.76 seconds
Started Aug 08 04:23:01 PM PDT 24
Finished Aug 08 04:23:02 PM PDT 24
Peak memory 196420 kb
Host smart-8e58979b-8357-41f6-9d17-75398758d148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907309689 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.907309689
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.808997001
Short name T68
Test name
Test status
Simulation time 315859843 ps
CPU time 0.84 seconds
Started Aug 08 04:23:10 PM PDT 24
Finished Aug 08 04:23:11 PM PDT 24
Peak memory 191908 kb
Host smart-5387dbc6-01bf-4321-ad9c-80fe42cf53a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808997001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.808997001
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.351849701
Short name T300
Test name
Test status
Simulation time 452248963 ps
CPU time 0.62 seconds
Started Aug 08 04:23:10 PM PDT 24
Finished Aug 08 04:23:11 PM PDT 24
Peak memory 184004 kb
Host smart-09bff8d0-1f96-4cf3-a447-7eef194990a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351849701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.351849701
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1894022650
Short name T426
Test name
Test status
Simulation time 2993450063 ps
CPU time 2.99 seconds
Started Aug 08 04:24:58 PM PDT 24
Finished Aug 08 04:25:01 PM PDT 24
Peak memory 194016 kb
Host smart-295a28a8-323d-458f-ada0-cc6db7f9bac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894022650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1894022650
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3666128649
Short name T369
Test name
Test status
Simulation time 466823707 ps
CPU time 2.59 seconds
Started Aug 08 04:23:44 PM PDT 24
Finished Aug 08 04:23:47 PM PDT 24
Peak memory 197776 kb
Host smart-535a7fc4-9b84-437b-ad42-a67bf8f4f378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666128649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3666128649
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2187708524
Short name T393
Test name
Test status
Simulation time 8090874798 ps
CPU time 11.81 seconds
Started Aug 08 04:27:03 PM PDT 24
Finished Aug 08 04:27:15 PM PDT 24
Peak memory 198076 kb
Host smart-19482bfb-c970-4199-9c0d-34c4a6dd9711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187708524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2187708524
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.272660976
Short name T395
Test name
Test status
Simulation time 303188487 ps
CPU time 1.07 seconds
Started Aug 08 04:22:27 PM PDT 24
Finished Aug 08 04:22:28 PM PDT 24
Peak memory 195836 kb
Host smart-2f95f1a2-e5a1-4eb4-b5c0-8d76d1e77beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272660976 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.272660976
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3170694978
Short name T309
Test name
Test status
Simulation time 316620394 ps
CPU time 0.94 seconds
Started Aug 08 04:26:47 PM PDT 24
Finished Aug 08 04:26:48 PM PDT 24
Peak memory 193832 kb
Host smart-2410e6b1-c60b-4726-b40b-392e99048acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170694978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3170694978
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3336273542
Short name T332
Test name
Test status
Simulation time 391467749 ps
CPU time 1.15 seconds
Started Aug 08 04:22:11 PM PDT 24
Finished Aug 08 04:22:13 PM PDT 24
Peak memory 183620 kb
Host smart-18948f31-3f16-44c7-916c-0aeb98a35dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336273542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3336273542
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2738312889
Short name T377
Test name
Test status
Simulation time 1130958358 ps
CPU time 0.94 seconds
Started Aug 08 04:21:43 PM PDT 24
Finished Aug 08 04:21:44 PM PDT 24
Peak memory 192848 kb
Host smart-e8ec3ba9-aea3-4081-8c1b-4e623cf668ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738312889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2738312889
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4111123520
Short name T355
Test name
Test status
Simulation time 690649714 ps
CPU time 2.13 seconds
Started Aug 08 04:23:22 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 198508 kb
Host smart-fbda0597-3d92-405a-aa80-54004b8e4cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111123520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4111123520
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2343749337
Short name T32
Test name
Test status
Simulation time 4036041626 ps
CPU time 2.61 seconds
Started Aug 08 04:27:03 PM PDT 24
Finished Aug 08 04:27:06 PM PDT 24
Peak memory 196388 kb
Host smart-3a0c5d0f-3486-4280-860a-20644b6ab3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343749337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2343749337
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3774926782
Short name T383
Test name
Test status
Simulation time 434877006 ps
CPU time 1.38 seconds
Started Aug 08 04:26:17 PM PDT 24
Finished Aug 08 04:26:19 PM PDT 24
Peak memory 195792 kb
Host smart-91e8134a-a590-4379-b423-f8ebc7320462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774926782 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3774926782
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.887273688
Short name T344
Test name
Test status
Simulation time 534581554 ps
CPU time 0.98 seconds
Started Aug 08 04:23:36 PM PDT 24
Finished Aug 08 04:23:37 PM PDT 24
Peak memory 192832 kb
Host smart-94e6351d-b064-41e7-9c97-df3e6cc02892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887273688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.887273688
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1594498601
Short name T425
Test name
Test status
Simulation time 518979462 ps
CPU time 0.72 seconds
Started Aug 08 04:25:04 PM PDT 24
Finished Aug 08 04:25:04 PM PDT 24
Peak memory 183596 kb
Host smart-999cd050-ffec-49dc-b547-885b26514ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594498601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1594498601
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1003600753
Short name T64
Test name
Test status
Simulation time 1426985781 ps
CPU time 1.13 seconds
Started Aug 08 04:27:09 PM PDT 24
Finished Aug 08 04:27:10 PM PDT 24
Peak memory 192380 kb
Host smart-5689fc98-fc22-4f1e-a506-f40c34d793c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003600753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1003600753
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2903145866
Short name T417
Test name
Test status
Simulation time 796758804 ps
CPU time 1.99 seconds
Started Aug 08 04:25:10 PM PDT 24
Finished Aug 08 04:25:12 PM PDT 24
Peak memory 198456 kb
Host smart-a12af385-43c5-40ad-aa51-8d331c81a7da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903145866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2903145866
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.337693238
Short name T31
Test name
Test status
Simulation time 8081212209 ps
CPU time 11.56 seconds
Started Aug 08 04:26:11 PM PDT 24
Finished Aug 08 04:26:22 PM PDT 24
Peak memory 197392 kb
Host smart-c206f214-980e-4bee-87c1-a568f01b00be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337693238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.337693238
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.854891274
Short name T29
Test name
Test status
Simulation time 433007867 ps
CPU time 1.18 seconds
Started Aug 08 04:27:06 PM PDT 24
Finished Aug 08 04:27:07 PM PDT 24
Peak memory 198212 kb
Host smart-80dee7ec-0875-4abe-90da-7b288856b733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854891274 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.854891274
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3433911872
Short name T324
Test name
Test status
Simulation time 323280110 ps
CPU time 0.98 seconds
Started Aug 08 04:26:19 PM PDT 24
Finished Aug 08 04:26:20 PM PDT 24
Peak memory 192508 kb
Host smart-7d97c6d8-061d-4d3d-b89e-3e355bc56284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433911872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3433911872
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.188524747
Short name T367
Test name
Test status
Simulation time 475498026 ps
CPU time 1.29 seconds
Started Aug 08 04:24:51 PM PDT 24
Finished Aug 08 04:24:52 PM PDT 24
Peak memory 192872 kb
Host smart-f55a9834-8f04-4283-acd4-21cd909f87c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188524747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.188524747
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2102925940
Short name T329
Test name
Test status
Simulation time 1670295771 ps
CPU time 5.94 seconds
Started Aug 08 04:23:00 PM PDT 24
Finished Aug 08 04:23:06 PM PDT 24
Peak memory 193960 kb
Host smart-5bb49979-9779-4c05-bc37-2551bd2ddc7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102925940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2102925940
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.799966656
Short name T346
Test name
Test status
Simulation time 593171990 ps
CPU time 1.5 seconds
Started Aug 08 04:22:40 PM PDT 24
Finished Aug 08 04:22:42 PM PDT 24
Peak memory 198852 kb
Host smart-2e08077a-81ee-43cf-9c06-fc00c9926b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799966656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.799966656
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.691772890
Short name T359
Test name
Test status
Simulation time 4352475728 ps
CPU time 3.93 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:27:20 PM PDT 24
Peak memory 197792 kb
Host smart-7753dfbd-e2b2-49a9-9fe8-eddf33d99864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691772890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.691772890
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1101223836
Short name T41
Test name
Test status
Simulation time 26530079858 ps
CPU time 40.89 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:16:42 PM PDT 24
Peak memory 192160 kb
Host smart-b6dbac5a-8267-4b7d-b4b7-d1302b4b5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101223836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1101223836
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.56447721
Short name T240
Test name
Test status
Simulation time 477039135 ps
CPU time 1.28 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:16:14 PM PDT 24
Peak memory 196948 kb
Host smart-1dc70900-606c-4b1d-acce-672ef1ecf05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56447721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.56447721
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3437221213
Short name T212
Test name
Test status
Simulation time 47166057048 ps
CPU time 16.49 seconds
Started Aug 08 05:16:16 PM PDT 24
Finished Aug 08 05:16:32 PM PDT 24
Peak memory 192004 kb
Host smart-2abdfec9-89fd-49d1-a9db-78e9cf9f111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437221213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3437221213
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2344013540
Short name T17
Test name
Test status
Simulation time 7203715435 ps
CPU time 10.38 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 215712 kb
Host smart-31efd088-1d1e-4c1a-9176-ebcaca665cf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344013540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2344013540
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1273544464
Short name T215
Test name
Test status
Simulation time 402875717 ps
CPU time 1.31 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 192036 kb
Host smart-a4e7f38e-75af-4589-aea4-71f28da007a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273544464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1273544464
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2074553014
Short name T249
Test name
Test status
Simulation time 24780481880 ps
CPU time 5.42 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:16:07 PM PDT 24
Peak memory 192140 kb
Host smart-c4bf3eb1-7ab2-4be1-a0b7-a56853bf3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074553014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2074553014
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2945513647
Short name T197
Test name
Test status
Simulation time 589838240 ps
CPU time 1.37 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 192044 kb
Host smart-6149c2e3-cb4e-48ad-b580-98c8543eb1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945513647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2945513647
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.760372413
Short name T188
Test name
Test status
Simulation time 542418038 ps
CPU time 0.79 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:16:06 PM PDT 24
Peak memory 196852 kb
Host smart-d3c6c143-b5ff-4b63-9044-954ee0e6b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760372413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.760372413
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4205986146
Short name T231
Test name
Test status
Simulation time 36198942455 ps
CPU time 49.78 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:57 PM PDT 24
Peak memory 192020 kb
Host smart-2036e318-8445-45f0-8fbd-33ef4fba44d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205986146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4205986146
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3873447344
Short name T13
Test name
Test status
Simulation time 576575556 ps
CPU time 0.78 seconds
Started Aug 08 05:16:01 PM PDT 24
Finished Aug 08 05:16:02 PM PDT 24
Peak memory 192084 kb
Host smart-8c31177c-7d06-44cf-92d9-30dba703aa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873447344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3873447344
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1955888449
Short name T172
Test name
Test status
Simulation time 560370168 ps
CPU time 0.79 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:01 PM PDT 24
Peak memory 197096 kb
Host smart-98759e68-5d74-48b1-9e25-b04351cf281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955888449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1955888449
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3992963414
Short name T2
Test name
Test status
Simulation time 27103688219 ps
CPU time 21.8 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:16:27 PM PDT 24
Peak memory 197136 kb
Host smart-42e6598c-aefc-4421-9ddb-cd18134a58b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992963414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3992963414
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1899466311
Short name T257
Test name
Test status
Simulation time 392652733 ps
CPU time 1.11 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 192316 kb
Host smart-0706aa00-5f58-4490-a100-659bbeca2323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899466311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1899466311
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.262669756
Short name T177
Test name
Test status
Simulation time 304368291122 ps
CPU time 114.25 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:18:02 PM PDT 24
Peak memory 198460 kb
Host smart-66576928-bb61-4969-885b-33f0340af8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262669756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.262669756
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.723088361
Short name T226
Test name
Test status
Simulation time 47724588712 ps
CPU time 78.25 seconds
Started Aug 08 05:16:04 PM PDT 24
Finished Aug 08 05:17:22 PM PDT 24
Peak memory 197024 kb
Host smart-76e0682a-5677-473f-8cea-e4b5140d6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723088361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.723088361
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.972192154
Short name T279
Test name
Test status
Simulation time 640024557 ps
CPU time 0.72 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 192116 kb
Host smart-2aac4694-8163-4b6f-ac21-ac25f09c6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972192154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.972192154
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2935848244
Short name T247
Test name
Test status
Simulation time 49471790162 ps
CPU time 16.55 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:27 PM PDT 24
Peak memory 197092 kb
Host smart-c05939ce-da72-4f83-935e-987e1ebfb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935848244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2935848244
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.110002996
Short name T250
Test name
Test status
Simulation time 417211064 ps
CPU time 0.93 seconds
Started Aug 08 05:16:05 PM PDT 24
Finished Aug 08 05:16:06 PM PDT 24
Peak memory 196940 kb
Host smart-914d64c9-c990-4966-8354-b0aacdf2268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110002996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.110002996
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1426391759
Short name T213
Test name
Test status
Simulation time 33032465650 ps
CPU time 25.76 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:16:41 PM PDT 24
Peak memory 197004 kb
Host smart-688f3cb6-21b9-4992-b227-aabbfb710c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426391759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1426391759
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2234400085
Short name T8
Test name
Test status
Simulation time 403367499 ps
CPU time 1.16 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 196836 kb
Host smart-3e608dda-edc0-49fa-b066-8a4aa22502fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234400085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2234400085
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3194477706
Short name T206
Test name
Test status
Simulation time 58737190741 ps
CPU time 45.73 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:54 PM PDT 24
Peak memory 192080 kb
Host smart-2881dacb-a818-42b5-b049-dbb8bf942cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194477706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3194477706
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2805409737
Short name T284
Test name
Test status
Simulation time 411791377 ps
CPU time 0.73 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 192024 kb
Host smart-1ba347e2-4347-4bc6-8285-47611717b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805409737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2805409737
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3638632108
Short name T23
Test name
Test status
Simulation time 537652576 ps
CPU time 1.04 seconds
Started Aug 08 05:16:10 PM PDT 24
Finished Aug 08 05:16:11 PM PDT 24
Peak memory 196816 kb
Host smart-897602a8-9274-42d4-8b56-d80cc039c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638632108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3638632108
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3924212430
Short name T259
Test name
Test status
Simulation time 23419900207 ps
CPU time 15.06 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:16:27 PM PDT 24
Peak memory 192020 kb
Host smart-1fa3729b-a7b9-4835-b241-cd279974f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924212430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3924212430
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3126637396
Short name T200
Test name
Test status
Simulation time 466321168 ps
CPU time 1.24 seconds
Started Aug 08 05:16:10 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 192060 kb
Host smart-d321db16-93e7-43f2-a94b-149ee50e1e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126637396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3126637396
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3146009385
Short name T218
Test name
Test status
Simulation time 38956132737 ps
CPU time 53.21 seconds
Started Aug 08 05:16:12 PM PDT 24
Finished Aug 08 05:17:05 PM PDT 24
Peak memory 192024 kb
Host smart-544b18f7-f693-47c9-9ff4-b8e071d23569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146009385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3146009385
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1710491305
Short name T253
Test name
Test status
Simulation time 538096050 ps
CPU time 0.67 seconds
Started Aug 08 05:16:06 PM PDT 24
Finished Aug 08 05:16:07 PM PDT 24
Peak memory 191944 kb
Host smart-f84fa598-48ec-4ca9-92c3-d48964412196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710491305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1710491305
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3183242795
Short name T242
Test name
Test status
Simulation time 24001136633 ps
CPU time 9.12 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:20 PM PDT 24
Peak memory 192124 kb
Host smart-057f39b8-2f0a-4be1-a784-5fc0da516188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183242795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3183242795
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.39180973
Short name T262
Test name
Test status
Simulation time 545336720 ps
CPU time 0.95 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 192024 kb
Host smart-05fb2115-7a3c-4cf1-b94d-242ba8454896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39180973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.39180973
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2216734684
Short name T280
Test name
Test status
Simulation time 28668887066 ps
CPU time 41.62 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:44 PM PDT 24
Peak memory 197144 kb
Host smart-1988ce2c-159a-4a34-b8a2-3e4dbd0865b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216734684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2216734684
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.341109197
Short name T16
Test name
Test status
Simulation time 4255077628 ps
CPU time 3.4 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 215316 kb
Host smart-3100300d-d365-45bf-ab1d-a1695aa205c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341109197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.341109197
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4126265949
Short name T244
Test name
Test status
Simulation time 520191817 ps
CPU time 0.82 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 191968 kb
Host smart-c1fb223e-31a1-4dbd-b779-837ac6625ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126265949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4126265949
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2543877296
Short name T159
Test name
Test status
Simulation time 410111158 ps
CPU time 1.15 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:29 PM PDT 24
Peak memory 196796 kb
Host smart-b72969fe-997f-4381-83d5-01d480b3af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543877296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2543877296
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2691073603
Short name T274
Test name
Test status
Simulation time 3444113944 ps
CPU time 2.21 seconds
Started Aug 08 05:16:29 PM PDT 24
Finished Aug 08 05:16:31 PM PDT 24
Peak memory 192132 kb
Host smart-296bb0b9-b22d-4cb4-a1b6-ad765e89a127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691073603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2691073603
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1849956842
Short name T203
Test name
Test status
Simulation time 464211212 ps
CPU time 0.77 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 192076 kb
Host smart-c65a0c55-03ee-40a8-b9b3-faf8a2136ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849956842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1849956842
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3323618221
Short name T189
Test name
Test status
Simulation time 405951055 ps
CPU time 1.12 seconds
Started Aug 08 05:16:10 PM PDT 24
Finished Aug 08 05:16:11 PM PDT 24
Peak memory 196860 kb
Host smart-9aca69b6-aa84-4d26-b6af-18551fbc8da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323618221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3323618221
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4230972463
Short name T12
Test name
Test status
Simulation time 18657569663 ps
CPU time 7.56 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 197056 kb
Host smart-87659959-8f63-4c90-b1cc-6c3ca711326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230972463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4230972463
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3203071456
Short name T214
Test name
Test status
Simulation time 492496486 ps
CPU time 1.02 seconds
Started Aug 08 05:16:21 PM PDT 24
Finished Aug 08 05:16:22 PM PDT 24
Peak memory 191984 kb
Host smart-6a11cb2c-5424-4d5e-97ed-023c295fe6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203071456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3203071456
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2211069477
Short name T221
Test name
Test status
Simulation time 31910554289 ps
CPU time 12.07 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:23 PM PDT 24
Peak memory 197196 kb
Host smart-19c00f82-e839-4824-96b7-b7d53f6be1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211069477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2211069477
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.160178289
Short name T277
Test name
Test status
Simulation time 418305767 ps
CPU time 0.71 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 196944 kb
Host smart-e47fdaa6-e220-479b-9701-a8ce9506f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160178289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.160178289
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1149347380
Short name T219
Test name
Test status
Simulation time 15717430780 ps
CPU time 6.13 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:16:23 PM PDT 24
Peak memory 192088 kb
Host smart-e71dd820-399c-4ad8-9f4b-be5dc4d6146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149347380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1149347380
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3642340446
Short name T232
Test name
Test status
Simulation time 563017414 ps
CPU time 1.48 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:16:28 PM PDT 24
Peak memory 196876 kb
Host smart-341ab0f5-cfe8-449d-9004-88ae299b18e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642340446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3642340446
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3735715902
Short name T125
Test name
Test status
Simulation time 104528923953 ps
CPU time 80.82 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:17:38 PM PDT 24
Peak memory 192116 kb
Host smart-c1feacc8-4f7b-49b3-93c3-86bbb9538c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735715902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3735715902
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1188752562
Short name T42
Test name
Test status
Simulation time 27757166633 ps
CPU time 40.32 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:16:57 PM PDT 24
Peak memory 192044 kb
Host smart-9c95ab7b-e0a3-4d8b-be85-b16f6ba91770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188752562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1188752562
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1846921999
Short name T201
Test name
Test status
Simulation time 370746338 ps
CPU time 0.83 seconds
Started Aug 08 05:16:16 PM PDT 24
Finished Aug 08 05:16:17 PM PDT 24
Peak memory 191972 kb
Host smart-cff42727-aef1-4adb-8d40-faa11eb01d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846921999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1846921999
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2015676460
Short name T186
Test name
Test status
Simulation time 412687387 ps
CPU time 1.12 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:29 PM PDT 24
Peak memory 196772 kb
Host smart-ed50d30f-d845-4786-b0f3-698cc386a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015676460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2015676460
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3324832327
Short name T268
Test name
Test status
Simulation time 10702864095 ps
CPU time 4.28 seconds
Started Aug 08 05:16:22 PM PDT 24
Finished Aug 08 05:16:26 PM PDT 24
Peak memory 190904 kb
Host smart-33c53e97-3d8f-4707-a83b-389a70224f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324832327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3324832327
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3476610119
Short name T25
Test name
Test status
Simulation time 535892257 ps
CPU time 0.9 seconds
Started Aug 08 05:16:22 PM PDT 24
Finished Aug 08 05:16:23 PM PDT 24
Peak memory 192072 kb
Host smart-5947410f-b3c7-45c8-80da-4f10c9e49af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476610119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3476610119
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.754013427
Short name T224
Test name
Test status
Simulation time 19201044313 ps
CPU time 2.54 seconds
Started Aug 08 05:16:14 PM PDT 24
Finished Aug 08 05:16:17 PM PDT 24
Peak memory 197076 kb
Host smart-df0227d8-d974-495d-98e8-f2198ea41192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754013427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.754013427
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4231228369
Short name T21
Test name
Test status
Simulation time 603946690 ps
CPU time 0.99 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 192088 kb
Host smart-bf1f1bcb-090a-48aa-aa6e-ca927469e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231228369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4231228369
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3628780401
Short name T238
Test name
Test status
Simulation time 16803387386 ps
CPU time 6.41 seconds
Started Aug 08 05:16:18 PM PDT 24
Finished Aug 08 05:16:25 PM PDT 24
Peak memory 192072 kb
Host smart-da844f87-4db7-480d-abc1-5905fc25b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628780401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3628780401
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3139980121
Short name T235
Test name
Test status
Simulation time 402635015 ps
CPU time 0.66 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 192028 kb
Host smart-5ce6d008-7cbf-4d8b-a096-0633a5ea7ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139980121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3139980121
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1530637569
Short name T243
Test name
Test status
Simulation time 12658711070 ps
CPU time 18.86 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:16:32 PM PDT 24
Peak memory 192088 kb
Host smart-4b2cf797-01c9-4bab-ac9e-7c65c973d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530637569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1530637569
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3494776413
Short name T205
Test name
Test status
Simulation time 559099124 ps
CPU time 1.36 seconds
Started Aug 08 05:16:17 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 192068 kb
Host smart-6a56f80a-3aff-42f9-8b0a-80b049aa61a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494776413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3494776413
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2560920651
Short name T120
Test name
Test status
Simulation time 509160212 ps
CPU time 1.31 seconds
Started Aug 08 05:16:25 PM PDT 24
Finished Aug 08 05:16:26 PM PDT 24
Peak memory 196824 kb
Host smart-f36ef3e6-bf6a-41ab-bcce-5a22ce4637d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560920651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2560920651
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1921957723
Short name T229
Test name
Test status
Simulation time 7671200499 ps
CPU time 11.57 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:39 PM PDT 24
Peak memory 191988 kb
Host smart-29c17de6-e26c-49b1-a423-c5ba82ca1f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921957723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1921957723
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2032277441
Short name T207
Test name
Test status
Simulation time 413661310 ps
CPU time 1.21 seconds
Started Aug 08 05:16:19 PM PDT 24
Finished Aug 08 05:16:20 PM PDT 24
Peak memory 192024 kb
Host smart-ee15b49a-fc67-4ae3-adeb-3d5564a2b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032277441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2032277441
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.57166785
Short name T236
Test name
Test status
Simulation time 27732102371 ps
CPU time 21.23 seconds
Started Aug 08 05:16:15 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 192100 kb
Host smart-2026bcc9-9df3-46d7-af1f-6dbfc26f5e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57166785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.57166785
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.758306419
Short name T18
Test name
Test status
Simulation time 3813771084 ps
CPU time 5.98 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 215344 kb
Host smart-bce20131-b3c4-43c0-8b7d-bc29a5fc0115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758306419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.758306419
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3638295367
Short name T220
Test name
Test status
Simulation time 468751825 ps
CPU time 0.65 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:03 PM PDT 24
Peak memory 196924 kb
Host smart-354a5224-0d6b-4d8f-817d-a17ceb3586ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638295367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3638295367
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.258325354
Short name T258
Test name
Test status
Simulation time 14377757205 ps
CPU time 16.23 seconds
Started Aug 08 05:16:30 PM PDT 24
Finished Aug 08 05:16:46 PM PDT 24
Peak memory 192036 kb
Host smart-fff753ff-ea10-49c6-9fe4-f0983a8ecd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258325354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.258325354
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1048012620
Short name T241
Test name
Test status
Simulation time 585472669 ps
CPU time 1.01 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 196820 kb
Host smart-ac63fe25-1ae8-487d-acdf-529fa57832af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048012620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1048012620
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3634531925
Short name T45
Test name
Test status
Simulation time 7907301040 ps
CPU time 4.03 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 197060 kb
Host smart-f5100679-0d98-442a-b034-97dae7285293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634531925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3634531925
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4259904057
Short name T265
Test name
Test status
Simulation time 590176169 ps
CPU time 0.74 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:29 PM PDT 24
Peak memory 192004 kb
Host smart-7f12cd3b-e2e3-44b7-9472-47b0f7638ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259904057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4259904057
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2025855932
Short name T165
Test name
Test status
Simulation time 553005039 ps
CPU time 0.82 seconds
Started Aug 08 05:16:31 PM PDT 24
Finished Aug 08 05:16:31 PM PDT 24
Peak memory 196880 kb
Host smart-3bb803d9-df20-41ce-a33f-071b2482b6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025855932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2025855932
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1677347613
Short name T237
Test name
Test status
Simulation time 9296825300 ps
CPU time 12.37 seconds
Started Aug 08 05:16:27 PM PDT 24
Finished Aug 08 05:16:40 PM PDT 24
Peak memory 192092 kb
Host smart-e0677f83-965f-4605-a3c7-9b06e49169a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677347613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1677347613
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3812912737
Short name T282
Test name
Test status
Simulation time 371562874 ps
CPU time 0.89 seconds
Started Aug 08 05:16:34 PM PDT 24
Finished Aug 08 05:16:35 PM PDT 24
Peak memory 191972 kb
Host smart-6ace088b-6d40-4f59-8525-8a76384dce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812912737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3812912737
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2835984203
Short name T260
Test name
Test status
Simulation time 35109832651 ps
CPU time 11.68 seconds
Started Aug 08 05:16:29 PM PDT 24
Finished Aug 08 05:16:41 PM PDT 24
Peak memory 192012 kb
Host smart-af3e10b6-df37-4f66-92a0-ba0e7d48d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835984203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2835984203
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.949093009
Short name T245
Test name
Test status
Simulation time 610001770 ps
CPU time 0.78 seconds
Started Aug 08 05:16:31 PM PDT 24
Finished Aug 08 05:16:32 PM PDT 24
Peak memory 191988 kb
Host smart-e1e8513e-74b2-4dc8-a3cd-7ed1601657d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949093009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.949093009
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.289718083
Short name T210
Test name
Test status
Simulation time 58664908831 ps
CPU time 64.17 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:17:37 PM PDT 24
Peak memory 192048 kb
Host smart-bcc2a721-5099-46df-a729-9ccf6bf510d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289718083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.289718083
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.899462449
Short name T225
Test name
Test status
Simulation time 508015711 ps
CPU time 0.94 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:16:33 PM PDT 24
Peak memory 196800 kb
Host smart-d4e349d8-46b1-47a4-8469-8abf2eeec93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899462449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.899462449
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1281215853
Short name T9
Test name
Test status
Simulation time 539860028 ps
CPU time 1.53 seconds
Started Aug 08 05:16:33 PM PDT 24
Finished Aug 08 05:16:34 PM PDT 24
Peak memory 196896 kb
Host smart-10e492b2-5d8d-4868-a8f4-d13758908012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281215853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1281215853
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1834541256
Short name T217
Test name
Test status
Simulation time 2162011994 ps
CPU time 3.13 seconds
Started Aug 08 05:16:28 PM PDT 24
Finished Aug 08 05:16:32 PM PDT 24
Peak memory 192076 kb
Host smart-0e74239c-d90c-4cee-a26d-045d1dd0a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834541256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1834541256
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1404494617
Short name T246
Test name
Test status
Simulation time 438025476 ps
CPU time 0.74 seconds
Started Aug 08 05:16:29 PM PDT 24
Finished Aug 08 05:16:30 PM PDT 24
Peak memory 191968 kb
Host smart-dc52a414-52b8-4277-b485-e87b69ee3195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404494617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1404494617
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2987844186
Short name T19
Test name
Test status
Simulation time 7918534359 ps
CPU time 11.05 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:16:50 PM PDT 24
Peak memory 192100 kb
Host smart-99a7f805-1da1-4ffa-8017-76c151ac53dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987844186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2987844186
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.379176583
Short name T261
Test name
Test status
Simulation time 559097604 ps
CPU time 0.82 seconds
Started Aug 08 05:16:33 PM PDT 24
Finished Aug 08 05:16:34 PM PDT 24
Peak memory 196884 kb
Host smart-80a155b1-e792-47bc-a96d-659b516edec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379176583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.379176583
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1157762360
Short name T209
Test name
Test status
Simulation time 10816716667 ps
CPU time 12.51 seconds
Started Aug 08 05:16:35 PM PDT 24
Finished Aug 08 05:16:48 PM PDT 24
Peak memory 192032 kb
Host smart-e9e4b507-c665-4fdc-a0ad-bb6f5e960a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157762360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1157762360
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1575782725
Short name T256
Test name
Test status
Simulation time 598770945 ps
CPU time 0.68 seconds
Started Aug 08 05:16:35 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 192016 kb
Host smart-d2b0dd72-f1b0-4cb3-b911-d0bc21fd5e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575782725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1575782725
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1260154206
Short name T285
Test name
Test status
Simulation time 34727837588 ps
CPU time 6.83 seconds
Started Aug 08 05:16:38 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 192160 kb
Host smart-97f9b7cf-5945-48f6-b189-e905d249e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260154206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1260154206
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1291272344
Short name T273
Test name
Test status
Simulation time 632992352 ps
CPU time 0.79 seconds
Started Aug 08 05:16:37 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 192016 kb
Host smart-201c79fe-d725-4fde-b09a-ce2bff34a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291272344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1291272344
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2500022238
Short name T179
Test name
Test status
Simulation time 377682620 ps
CPU time 1.21 seconds
Started Aug 08 05:16:33 PM PDT 24
Finished Aug 08 05:16:35 PM PDT 24
Peak memory 196880 kb
Host smart-050ba5b2-7f2b-4109-a97f-a6e73445f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500022238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2500022238
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1551185051
Short name T199
Test name
Test status
Simulation time 28675567116 ps
CPU time 44.6 seconds
Started Aug 08 05:16:33 PM PDT 24
Finished Aug 08 05:17:18 PM PDT 24
Peak memory 197012 kb
Host smart-aeafe6f7-a49a-4951-8667-196a8864c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551185051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1551185051
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.459430440
Short name T208
Test name
Test status
Simulation time 393367225 ps
CPU time 0.73 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:16:40 PM PDT 24
Peak memory 196872 kb
Host smart-0897d9b3-a410-405c-9914-47e81cd424ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459430440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.459430440
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1387161071
Short name T263
Test name
Test status
Simulation time 54660584016 ps
CPU time 18.81 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:16:32 PM PDT 24
Peak memory 192084 kb
Host smart-446f3575-0739-4834-9ec1-fa04a145a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387161071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1387161071
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2401780867
Short name T15
Test name
Test status
Simulation time 3577459632 ps
CPU time 5.99 seconds
Started Aug 08 05:16:09 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 215412 kb
Host smart-df15f217-656b-40b2-89de-b5a77f179f6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401780867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2401780867
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3038480740
Short name T276
Test name
Test status
Simulation time 450261363 ps
CPU time 1.24 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:10 PM PDT 24
Peak memory 191976 kb
Host smart-b2a31300-9b23-4d15-bb7f-4face0407ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038480740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3038480740
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2484708984
Short name T167
Test name
Test status
Simulation time 597325029 ps
CPU time 0.77 seconds
Started Aug 08 05:16:32 PM PDT 24
Finished Aug 08 05:16:33 PM PDT 24
Peak memory 196836 kb
Host smart-91edc8a2-f416-4c79-b147-35fb4bd5c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484708984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2484708984
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.153767968
Short name T223
Test name
Test status
Simulation time 10074620479 ps
CPU time 2.62 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:16:41 PM PDT 24
Peak memory 192072 kb
Host smart-021c5f6d-fab5-4826-a83e-08480676d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153767968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.153767968
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3505801631
Short name T198
Test name
Test status
Simulation time 542540377 ps
CPU time 0.97 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:16:37 PM PDT 24
Peak memory 196916 kb
Host smart-a307df2d-2202-442e-a142-b935fc94a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505801631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3505801631
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3891542242
Short name T216
Test name
Test status
Simulation time 31586643801 ps
CPU time 30.16 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:17:06 PM PDT 24
Peak memory 192136 kb
Host smart-baf17290-d687-4db5-bd2d-42f83c9c5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891542242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3891542242
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.958991849
Short name T204
Test name
Test status
Simulation time 398947043 ps
CPU time 0.83 seconds
Started Aug 08 05:16:41 PM PDT 24
Finished Aug 08 05:16:42 PM PDT 24
Peak memory 192008 kb
Host smart-8c6b85a3-980b-4dc1-add6-d5584b7d8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958991849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.958991849
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1860013151
Short name T252
Test name
Test status
Simulation time 26601665802 ps
CPU time 43.34 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:17:19 PM PDT 24
Peak memory 192132 kb
Host smart-e4737b98-5c0b-4471-b5e7-b420fd1e9380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860013151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1860013151
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3770574921
Short name T251
Test name
Test status
Simulation time 495005895 ps
CPU time 0.76 seconds
Started Aug 08 05:16:36 PM PDT 24
Finished Aug 08 05:16:36 PM PDT 24
Peak memory 192048 kb
Host smart-1f733606-ff41-496b-b14e-f288912d61bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770574921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3770574921
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1589516413
Short name T222
Test name
Test status
Simulation time 12530050548 ps
CPU time 9.84 seconds
Started Aug 08 05:16:39 PM PDT 24
Finished Aug 08 05:16:49 PM PDT 24
Peak memory 197216 kb
Host smart-afcd53dc-e605-4d40-b12c-75bba431366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589516413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1589516413
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3292418732
Short name T269
Test name
Test status
Simulation time 451210746 ps
CPU time 0.77 seconds
Started Aug 08 05:16:40 PM PDT 24
Finished Aug 08 05:16:40 PM PDT 24
Peak memory 192028 kb
Host smart-27cb15cd-67e0-466c-858e-8d427dbd8272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292418732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3292418732
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.333441645
Short name T46
Test name
Test status
Simulation time 19806137277 ps
CPU time 14.84 seconds
Started Aug 08 05:16:43 PM PDT 24
Finished Aug 08 05:16:58 PM PDT 24
Peak memory 192100 kb
Host smart-df30f649-ae0c-4f69-afb5-3cce48fc16c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333441645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.333441645
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.556437941
Short name T227
Test name
Test status
Simulation time 457488970 ps
CPU time 0.65 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196800 kb
Host smart-0b5982db-945c-4942-a94f-7f139815f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556437941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.556437941
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2208035453
Short name T137
Test name
Test status
Simulation time 545727371 ps
CPU time 1.35 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196896 kb
Host smart-0668ba1a-2ec8-437b-bd7c-b95d0e12dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208035453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2208035453
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3086364271
Short name T271
Test name
Test status
Simulation time 28941327872 ps
CPU time 9.83 seconds
Started Aug 08 05:16:50 PM PDT 24
Finished Aug 08 05:17:01 PM PDT 24
Peak memory 192144 kb
Host smart-7453dc7c-7217-45db-85c5-db30696fd108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086364271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3086364271
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2871402035
Short name T202
Test name
Test status
Simulation time 467226195 ps
CPU time 0.75 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:45 PM PDT 24
Peak memory 196936 kb
Host smart-fe1fb0a3-0aef-42b6-92b7-a506e89a87be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871402035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2871402035
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1148055955
Short name T254
Test name
Test status
Simulation time 23737883623 ps
CPU time 3.99 seconds
Started Aug 08 05:16:44 PM PDT 24
Finished Aug 08 05:16:48 PM PDT 24
Peak memory 197068 kb
Host smart-1cbf3a3b-ad38-4b50-8b48-d4dcd0f2feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148055955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1148055955
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1541198065
Short name T281
Test name
Test status
Simulation time 516741839 ps
CPU time 0.75 seconds
Started Aug 08 05:16:46 PM PDT 24
Finished Aug 08 05:16:47 PM PDT 24
Peak memory 192080 kb
Host smart-d5667ab7-c91b-4e70-8ae5-9ea47eb03216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541198065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1541198065
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.391772992
Short name T230
Test name
Test status
Simulation time 36522459590 ps
CPU time 42.86 seconds
Started Aug 08 05:16:43 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 197028 kb
Host smart-fb16fe7a-495c-496e-a055-17380dd1e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391772992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.391772992
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3244079875
Short name T267
Test name
Test status
Simulation time 543046870 ps
CPU time 1 seconds
Started Aug 08 05:16:51 PM PDT 24
Finished Aug 08 05:16:52 PM PDT 24
Peak memory 196924 kb
Host smart-2ffa6262-42a5-415a-971d-89a4d3c48b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244079875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3244079875
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3070720046
Short name T272
Test name
Test status
Simulation time 7815413484 ps
CPU time 11.02 seconds
Started Aug 08 05:16:45 PM PDT 24
Finished Aug 08 05:16:56 PM PDT 24
Peak memory 192148 kb
Host smart-ddda6636-053d-47b0-9429-36142f55d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070720046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3070720046
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.903701019
Short name T283
Test name
Test status
Simulation time 438269911 ps
CPU time 0.82 seconds
Started Aug 08 05:16:46 PM PDT 24
Finished Aug 08 05:16:47 PM PDT 24
Peak memory 192040 kb
Host smart-d2383556-df5b-4938-acbb-df4f3192066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903701019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.903701019
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1607460360
Short name T233
Test name
Test status
Simulation time 3393477074 ps
CPU time 1.68 seconds
Started Aug 08 05:16:45 PM PDT 24
Finished Aug 08 05:16:46 PM PDT 24
Peak memory 192068 kb
Host smart-b4e66e95-df76-4121-b3f0-98bbb74d4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607460360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1607460360
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.775258130
Short name T234
Test name
Test status
Simulation time 445639895 ps
CPU time 1.21 seconds
Started Aug 08 05:16:50 PM PDT 24
Finished Aug 08 05:16:52 PM PDT 24
Peak memory 192080 kb
Host smart-d8aa070a-55fc-4a56-8b16-43a0b40b248f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775258130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.775258130
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2062756850
Short name T266
Test name
Test status
Simulation time 35230858951 ps
CPU time 50.51 seconds
Started Aug 08 05:16:00 PM PDT 24
Finished Aug 08 05:16:50 PM PDT 24
Peak memory 197032 kb
Host smart-26f21904-72b0-42cb-b463-44f3f0acba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062756850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2062756850
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2164055718
Short name T211
Test name
Test status
Simulation time 553364768 ps
CPU time 1.31 seconds
Started Aug 08 05:16:13 PM PDT 24
Finished Aug 08 05:16:15 PM PDT 24
Peak memory 192096 kb
Host smart-41c4ed7a-1e2a-4dec-a0ba-7f0312edf0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164055718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2164055718
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3154773316
Short name T161
Test name
Test status
Simulation time 419553553 ps
CPU time 1.22 seconds
Started Aug 08 05:16:16 PM PDT 24
Finished Aug 08 05:16:18 PM PDT 24
Peak memory 196820 kb
Host smart-74704985-493b-46da-943f-6fa989923b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154773316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3154773316
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2836635125
Short name T239
Test name
Test status
Simulation time 19088936039 ps
CPU time 30.35 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:38 PM PDT 24
Peak memory 192092 kb
Host smart-214b10e7-ac25-4bb4-a3d7-0df0b7b06aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836635125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2836635125
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.908341542
Short name T228
Test name
Test status
Simulation time 393610790 ps
CPU time 1.03 seconds
Started Aug 08 05:16:07 PM PDT 24
Finished Aug 08 05:16:08 PM PDT 24
Peak memory 191992 kb
Host smart-650dbfdb-726c-4dec-ba20-08a03b5c86d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908341542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.908341542
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1585114108
Short name T275
Test name
Test status
Simulation time 52862069655 ps
CPU time 82.87 seconds
Started Aug 08 05:16:03 PM PDT 24
Finished Aug 08 05:17:26 PM PDT 24
Peak memory 192032 kb
Host smart-27ad37d6-91ef-4caa-b349-d94c1dccd079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585114108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1585114108
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3299802736
Short name T248
Test name
Test status
Simulation time 451027179 ps
CPU time 0.92 seconds
Started Aug 08 05:16:11 PM PDT 24
Finished Aug 08 05:16:12 PM PDT 24
Peak memory 191968 kb
Host smart-a8ae3582-9c39-472f-87da-09abe5f8bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299802736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3299802736
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2811078068
Short name T182
Test name
Test status
Simulation time 527507589 ps
CPU time 1 seconds
Started Aug 08 05:15:59 PM PDT 24
Finished Aug 08 05:16:00 PM PDT 24
Peak memory 196876 kb
Host smart-57c4e296-5285-44a0-98e2-ad842932e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811078068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2811078068
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.63206481
Short name T270
Test name
Test status
Simulation time 50338987599 ps
CPU time 18.86 seconds
Started Aug 08 05:16:02 PM PDT 24
Finished Aug 08 05:16:21 PM PDT 24
Peak memory 192092 kb
Host smart-78052721-2753-4048-b325-bb4f654c49f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63206481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.63206481
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1401767901
Short name T278
Test name
Test status
Simulation time 528639788 ps
CPU time 1.36 seconds
Started Aug 08 05:16:03 PM PDT 24
Finished Aug 08 05:16:04 PM PDT 24
Peak memory 192112 kb
Host smart-ca39635c-73fb-41c2-881a-3951c1192dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401767901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1401767901
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.717008484
Short name T255
Test name
Test status
Simulation time 6477183264 ps
CPU time 5.6 seconds
Started Aug 08 05:16:08 PM PDT 24
Finished Aug 08 05:16:14 PM PDT 24
Peak memory 192100 kb
Host smart-cf04ce3b-91fb-4fc8-a2ae-40f659334932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717008484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.717008484
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3462370690
Short name T264
Test name
Test status
Simulation time 378803972 ps
CPU time 0.83 seconds
Started Aug 08 05:16:03 PM PDT 24
Finished Aug 08 05:16:04 PM PDT 24
Peak memory 192064 kb
Host smart-f502bc15-7c96-4014-af0c-4d8f7d0ab0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462370690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3462370690
Directory /workspace/9.aon_timer_smoke/latest
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