Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26216	1		T1	11		T2	12		T3	135
bark[1]	807	1		T39	254		T87	26		T137	21
bark[2]	515	1		T26	21		T37	21		T70	65
bark[3]	692	1		T8	21		T10	21		T13	42
bark[4]	538	1		T12	35		T41	26		T71	213
bark[5]	774	1		T82	51		T39	7		T110	21
bark[6]	445	1		T43	21		T110	58		T91	134
bark[7]	486	1		T11	21		T12	21		T82	21
bark[8]	402	1		T26	31		T35	30		T36	60
bark[9]	552	1		T27	14		T14	21		T25	51
bark[10]	452	1		T25	14		T36	190		T85	21
bark[11]	222	1		T13	21		T35	21		T43	21
bark[12]	769	1		T8	5		T21	21		T35	21
bark[13]	916	1		T8	26		T21	21		T38	14
bark[14]	422	1		T3	21		T12	21		T21	87
bark[15]	379	1		T14	5		T37	21		T85	39
bark[16]	345	1		T8	30		T127	14		T82	81
bark[17]	261	1		T39	60		T167	14		T73	21
bark[18]	276	1		T26	26		T41	57		T131	61
bark[19]	284	1		T7	14		T41	21		T35	21
bark[20]	184	1		T3	91		T40	30		T113	21
bark[21]	193	1		T35	67		T78	14		T84	21
bark[22]	533	1		T8	220		T13	19		T25	21
bark[23]	275	1		T12	66		T42	21		T158	19
bark[24]	514	1		T42	21		T37	227		T80	14
bark[25]	582	1		T110	208		T91	83		T112	42
bark[26]	841	1		T38	47		T110	81		T91	265
bark[27]	308	1		T8	21		T35	21		T36	14
bark[28]	507	1		T25	21		T110	216		T158	30
bark[29]	380	1		T3	30		T26	21		T90	40
bark[30]	1769	1		T9	14		T10	100		T11	21
bark[31]	429	1		T70	14		T157	21		T124	14
bark_0	4310	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26190	1		T1	10		T2	11		T3	134
bite[1]	295	1		T12	21		T26	21		T167	13
bite[2]	675	1		T44	13		T79	64		T82	51
bite[3]	472	1		T12	21		T25	30		T41	21
bite[4]	474	1		T35	66		T71	26		T112	21
bite[5]	816	1		T12	51		T13	21		T26	31
bite[6]	286	1		T8	30		T14	21		T100	13
bite[7]	89	1		T12	13		T35	21		T139	13
bite[8]	461	1		T8	21		T26	26		T79	21
bite[9]	574	1		T42	38		T39	6		T85	39
bite[10]	211	1		T7	13		T8	25		T71	21
bite[11]	364	1		T11	21		T39	253		T87	26
bite[12]	661	1		T3	21		T40	30		T71	200
bite[13]	230	1		T13	38		T36	21		T78	13
bite[14]	630	1		T37	133		T158	18		T159	108
bite[15]	251	1		T13	21		T41	13		T35	21
bite[16]	467	1		T110	217		T71	31		T117	21
bite[17]	551	1		T13	18		T42	21		T36	13
bite[18]	212	1		T21	21		T35	21		T43	21
bite[19]	774	1		T26	21		T35	181		T37	21
bite[20]	772	1		T3	30		T12	21		T127	13
bite[21]	657	1		T14	4		T35	21		T110	80
bite[22]	426	1		T10	100		T40	63		T137	21
bite[23]	295	1		T12	35		T13	21		T25	21
bite[24]	564	1		T27	13		T25	42		T80	13
bite[25]	1162	1		T8	219		T9	13		T11	21
bite[26]	403	1		T21	21		T41	57		T36	189
bite[27]	586	1		T39	258		T93	21		T141	21
bite[28]	168	1		T8	21		T82	21		T85	21
bite[29]	731	1		T8	4		T73	25		T141	21
bite[30]	448	1		T25	13		T41	26		T85	21
bite[31]	852	1		T3	91		T10	21		T37	205
bite_0	4831	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37905	1		T1	18		T2	19		T3	266
auto[1]	8673	1		T3	18		T8	134		T13	59

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1033	1		T3	19		T8	40		T25	32
prescale[1]	1078	1		T36	23		T37	206		T39	36
prescale[2]	610	1		T13	19		T25	19		T36	19
prescale[3]	714	1		T12	40		T35	19		T43	49
prescale[4]	586	1		T26	36		T35	4		T36	2
prescale[5]	604	1		T3	28		T13	28		T21	19
prescale[6]	691	1		T11	19		T41	61		T43	19
prescale[7]	612	1		T5	9		T36	33		T82	19
prescale[8]	627	1		T11	9		T41	23		T35	119
prescale[9]	439	1		T26	9		T36	2		T110	75
prescale[10]	603	1		T24	9		T43	33		T37	76
prescale[11]	975	1		T40	227		T110	26		T71	62
prescale[12]	442	1		T14	9		T37	84		T87	120
prescale[13]	416	1		T6	9		T8	9		T11	24
prescale[14]	1119	1		T13	19		T36	44		T43	9
prescale[15]	657	1		T8	19		T26	19		T35	47
prescale[16]	690	1		T26	19		T35	59		T43	19
prescale[17]	572	1		T11	19		T14	2		T35	204
prescale[18]	937	1		T21	24		T35	2		T37	104
prescale[19]	383	1		T8	2		T21	9		T26	2
prescale[20]	863	1		T8	2		T11	40		T12	243
prescale[21]	640	1		T8	40		T12	16		T42	44
prescale[22]	374	1		T8	19		T35	38		T43	19
prescale[23]	579	1		T10	23		T12	2		T82	23
prescale[24]	656	1		T3	23		T26	118		T42	28
prescale[25]	587	1		T10	14		T12	2		T13	53
prescale[26]	487	1		T12	2		T21	37		T37	78
prescale[27]	1005	1		T12	195		T25	87		T35	21
prescale[28]	662	1		T2	9		T26	19		T35	19
prescale[29]	509	1		T37	37		T40	98		T70	4
prescale[30]	846	1		T8	58		T14	4		T35	14
prescale[31]	605	1		T3	28		T10	37		T12	4
prescale_0	24977	1		T1	18		T2	10		T3	186

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34021	1		T1	9		T2	9		T3	154
auto[1]	12557	1		T1	9		T2	10		T3	130

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	46578	1		T1	18		T2	19		T3	284

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27010	1		T1	13		T2	14		T3	165
wkup[1]	235	1		T26	31		T37	21		T39	21
wkup[2]	254	1		T21	21		T26	26		T35	21
wkup[3]	198	1		T26	21		T35	21		T158	21
wkup[4]	499	1		T3	21		T26	26		T41	26
wkup[5]	229	1		T12	21		T40	47		T91	42
wkup[6]	108	1		T26	30		T35	21		T38	21
wkup[7]	259	1		T14	35		T35	21		T158	20
wkup[8]	269	1		T36	15		T110	21		T117	21
wkup[9]	175	1		T12	42		T25	26		T148	15
wkup[10]	197	1		T37	21		T38	26		T40	30
wkup[11]	180	1		T13	30		T25	30		T110	36
wkup[12]	162	1		T25	21		T110	21		T172	15
wkup[13]	357	1		T8	21		T10	21		T40	30
wkup[14]	314	1		T36	8		T40	63		T110	21
wkup[15]	239	1		T12	21		T13	21		T37	15
wkup[16]	306	1		T35	21		T37	21		T112	21
wkup[17]	224	1		T162	15		T73	21		T113	21
wkup[18]	336	1		T9	15		T10	30		T12	21
wkup[19]	191	1		T13	21		T37	21		T38	15
wkup[20]	263	1		T8	21		T42	21		T112	21
wkup[21]	342	1		T14	21		T79	21		T110	21
wkup[22]	323	1		T8	26		T21	30		T14	30
wkup[23]	402	1		T14	6		T26	21		T36	21
wkup[24]	286	1		T35	21		T43	21		T40	21
wkup[25]	264	1		T39	21		T158	21		T159	21
wkup[26]	308	1		T3	30		T110	50		T93	21
wkup[27]	211	1		T39	42		T85	39		T71	21
wkup[28]	157	1		T8	30		T37	21		T180	15
wkup[29]	167	1		T25	21		T44	15		T71	42
wkup[30]	236	1		T21	21		T110	21		T71	21
wkup[31]	332	1		T12	21		T13	21		T41	21
wkup[32]	329	1		T37	21		T40	21		T71	21
wkup[33]	247	1		T39	30		T71	21		T91	29
wkup[34]	252	1		T8	6		T26	21		T36	26
wkup[35]	159	1		T36	21		T37	30		T91	21
wkup[36]	335	1		T12	21		T26	21		T41	15
wkup[37]	268	1		T8	21		T25	21		T41	21
wkup[38]	227	1		T35	21		T39	8		T40	26
wkup[39]	240	1		T3	21		T39	21		T73	21
wkup[40]	227	1		T12	15		T35	21		T80	15
wkup[41]	267	1		T3	21		T42	21		T40	47
wkup[42]	247	1		T12	56		T25	21		T37	42
wkup[43]	284	1		T8	6		T11	21		T41	21
wkup[44]	328	1		T7	15		T13	20		T26	21
wkup[45]	258	1		T37	30		T82	21		T87	26
wkup[46]	196	1		T36	45		T39	21		T85	21
wkup[47]	364	1		T8	21		T27	15		T21	21
wkup[48]	297	1		T12	56		T41	21		T82	30
wkup[49]	187	1		T12	21		T40	30		T71	31
wkup[50]	212	1		T8	21		T39	21		T40	30
wkup[51]	105	1		T35	42		T140	21		T76	21
wkup[52]	155	1		T13	21		T37	21		T40	21
wkup[53]	326	1		T3	21		T36	29		T37	21
wkup[54]	204	1		T36	21		T78	15		T158	21
wkup[55]	215	1		T82	21		T73	26		T137	21
wkup[56]	344	1		T35	30		T39	21		T40	63
wkup[57]	108	1		T37	30		T85	21		T75	21
wkup[58]	317	1		T12	21		T25	15		T35	21
wkup[59]	271	1		T11	21		T35	21		T37	21
wkup[60]	258	1		T12	21		T40	21		T110	21
wkup[61]	280	1		T12	26		T35	15		T110	21
wkup[62]	249	1		T35	8		T42	21		T43	21
wkup[63]	402	1		T8	42		T14	21		T37	20
wkup_0	3387	1		T1	5		T2	5		T3	5