Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.23 99.33 93.67 100.00 98.40 99.51 50.48


Total test records in report: 417
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T282 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2678838303 Aug 09 04:28:12 PM PDT 24 Aug 09 04:28:13 PM PDT 24 513882244 ps
T283 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2186423880 Aug 09 04:25:05 PM PDT 24 Aug 09 04:25:06 PM PDT 24 275296766 ps
T34 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2294873195 Aug 09 04:27:54 PM PDT 24 Aug 09 04:27:54 PM PDT 24 414234230 ps
T284 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.764861843 Aug 09 04:28:09 PM PDT 24 Aug 09 04:28:12 PM PDT 24 668055585 ps
T285 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1215172870 Aug 09 04:28:07 PM PDT 24 Aug 09 04:28:08 PM PDT 24 352720403 ps
T29 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.102566227 Aug 09 04:25:12 PM PDT 24 Aug 09 04:25:20 PM PDT 24 4701536650 ps
T286 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4255847544 Aug 09 04:21:15 PM PDT 24 Aug 09 04:21:15 PM PDT 24 537810304 ps
T287 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1675387638 Aug 09 04:24:31 PM PDT 24 Aug 09 04:24:32 PM PDT 24 371640184 ps
T45 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2236480961 Aug 09 04:20:49 PM PDT 24 Aug 09 04:21:09 PM PDT 24 6076232496 ps
T288 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.726534584 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 461622176 ps
T289 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2430417363 Aug 09 04:27:55 PM PDT 24 Aug 09 04:27:56 PM PDT 24 295224742 ps
T30 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1714364341 Aug 09 04:25:33 PM PDT 24 Aug 09 04:25:34 PM PDT 24 1560759018 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3740086265 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 336841886 ps
T290 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.316992644 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 421701740 ps
T46 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2001345848 Aug 09 04:23:42 PM PDT 24 Aug 09 04:23:45 PM PDT 24 7119166777 ps
T291 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.188874246 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:07 PM PDT 24 407073913 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2819648683 Aug 09 04:28:10 PM PDT 24 Aug 09 04:28:15 PM PDT 24 1947289864 ps
T60 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2606915661 Aug 09 04:28:02 PM PDT 24 Aug 09 04:28:03 PM PDT 24 1024873442 ps
T31 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2885237494 Aug 09 04:28:09 PM PDT 24 Aug 09 04:28:22 PM PDT 24 8266468444 ps
T292 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2735982687 Aug 09 04:28:16 PM PDT 24 Aug 09 04:28:17 PM PDT 24 319788141 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2539578791 Aug 09 04:25:58 PM PDT 24 Aug 09 04:26:01 PM PDT 24 1264872784 ps
T62 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4168060389 Aug 09 04:27:59 PM PDT 24 Aug 09 04:28:00 PM PDT 24 1142162872 ps
T293 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.11990432 Aug 09 04:27:55 PM PDT 24 Aug 09 04:27:56 PM PDT 24 425180529 ps
T47 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3635030336 Aug 09 04:25:32 PM PDT 24 Aug 09 04:25:34 PM PDT 24 1192404847 ps
T185 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.406138697 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:59 PM PDT 24 532442665 ps
T48 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2169796199 Aug 09 04:20:42 PM PDT 24 Aug 09 04:20:44 PM PDT 24 661245816 ps
T294 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2141518298 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 445215664 ps
T295 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3197572374 Aug 09 04:28:22 PM PDT 24 Aug 09 04:28:23 PM PDT 24 381105261 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1694626832 Aug 09 04:21:04 PM PDT 24 Aug 09 04:21:05 PM PDT 24 465126881 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2535904612 Aug 09 04:28:07 PM PDT 24 Aug 09 04:28:08 PM PDT 24 379758024 ps
T298 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3004442929 Aug 09 04:28:16 PM PDT 24 Aug 09 04:28:18 PM PDT 24 614310453 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.294303212 Aug 09 04:25:24 PM PDT 24 Aug 09 04:25:26 PM PDT 24 409477991 ps
T32 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3767956178 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:04 PM PDT 24 4946944543 ps
T300 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1136966900 Aug 09 04:28:16 PM PDT 24 Aug 09 04:28:16 PM PDT 24 492764881 ps
T301 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4173098044 Aug 09 04:27:53 PM PDT 24 Aug 09 04:27:54 PM PDT 24 372210183 ps
T302 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1303732487 Aug 09 04:28:20 PM PDT 24 Aug 09 04:28:21 PM PDT 24 431364010 ps
T303 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2437442343 Aug 09 04:27:56 PM PDT 24 Aug 09 04:27:57 PM PDT 24 399314736 ps
T304 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1713300602 Aug 09 04:28:15 PM PDT 24 Aug 09 04:28:16 PM PDT 24 527797817 ps
T305 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.257228051 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:09 PM PDT 24 4929226208 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1526066101 Aug 09 04:25:12 PM PDT 24 Aug 09 04:25:13 PM PDT 24 501064985 ps
T181 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3150524558 Aug 09 04:27:57 PM PDT 24 Aug 09 04:28:11 PM PDT 24 8280093949 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1009969151 Aug 09 04:27:49 PM PDT 24 Aug 09 04:27:50 PM PDT 24 376981642 ps
T64 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1134443552 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:06 PM PDT 24 3051781281 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4043522111 Aug 09 04:27:49 PM PDT 24 Aug 09 04:27:49 PM PDT 24 324531531 ps
T308 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1487213146 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:59 PM PDT 24 414095667 ps
T309 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3292297451 Aug 09 04:27:55 PM PDT 24 Aug 09 04:27:56 PM PDT 24 450334678 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.865819652 Aug 09 04:24:12 PM PDT 24 Aug 09 04:24:13 PM PDT 24 963665239 ps
T49 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.661460267 Aug 09 04:27:58 PM PDT 24 Aug 09 04:28:25 PM PDT 24 11570542245 ps
T65 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.997156941 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:02 PM PDT 24 1658539686 ps
T311 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.773515860 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:03 PM PDT 24 442616625 ps
T312 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3822169788 Aug 09 04:28:03 PM PDT 24 Aug 09 04:28:04 PM PDT 24 545339411 ps
T313 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4069993390 Aug 09 04:27:55 PM PDT 24 Aug 09 04:28:00 PM PDT 24 2475037814 ps
T314 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.937628143 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:08 PM PDT 24 425067235 ps
T182 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.611709286 Aug 09 04:25:44 PM PDT 24 Aug 09 04:25:48 PM PDT 24 8185651641 ps
T50 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2641808087 Aug 09 04:20:49 PM PDT 24 Aug 09 04:20:50 PM PDT 24 511352746 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1786930772 Aug 09 04:28:11 PM PDT 24 Aug 09 04:28:12 PM PDT 24 507668629 ps
T316 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2070418724 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 366833277 ps
T317 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2110258698 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:03 PM PDT 24 526846267 ps
T318 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.641139388 Aug 09 04:27:50 PM PDT 24 Aug 09 04:27:52 PM PDT 24 565055758 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.110404091 Aug 09 04:26:43 PM PDT 24 Aug 09 04:26:55 PM PDT 24 8420435353 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1007756956 Aug 09 04:24:18 PM PDT 24 Aug 09 04:24:19 PM PDT 24 481202428 ps
T321 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2144607135 Aug 09 04:28:12 PM PDT 24 Aug 09 04:28:12 PM PDT 24 525097542 ps
T51 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1669899540 Aug 09 04:27:52 PM PDT 24 Aug 09 04:27:53 PM PDT 24 396243477 ps
T322 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2185228980 Aug 09 04:28:38 PM PDT 24 Aug 09 04:28:39 PM PDT 24 445553198 ps
T323 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2671815207 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 467948092 ps
T324 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4111574549 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:08 PM PDT 24 4284760623 ps
T325 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1938913856 Aug 09 04:27:54 PM PDT 24 Aug 09 04:27:55 PM PDT 24 2540912094 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4062763381 Aug 09 04:28:23 PM PDT 24 Aug 09 04:28:25 PM PDT 24 1779494779 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3556626640 Aug 09 04:20:49 PM PDT 24 Aug 09 04:20:55 PM PDT 24 3441564358 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1286359664 Aug 09 04:25:27 PM PDT 24 Aug 09 04:25:28 PM PDT 24 516030018 ps
T328 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2173870466 Aug 09 04:28:13 PM PDT 24 Aug 09 04:28:14 PM PDT 24 335774473 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.510447898 Aug 09 04:21:19 PM PDT 24 Aug 09 04:21:20 PM PDT 24 471260042 ps
T330 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1275992584 Aug 09 04:28:05 PM PDT 24 Aug 09 04:28:06 PM PDT 24 411992185 ps
T54 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.773803491 Aug 09 04:27:59 PM PDT 24 Aug 09 04:28:00 PM PDT 24 542542936 ps
T331 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.800934449 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 551398750 ps
T332 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1980836112 Aug 09 04:28:10 PM PDT 24 Aug 09 04:28:11 PM PDT 24 501414022 ps
T53 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1309733165 Aug 09 04:23:29 PM PDT 24 Aug 09 04:23:30 PM PDT 24 500072845 ps
T333 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1539570869 Aug 09 04:28:03 PM PDT 24 Aug 09 04:28:04 PM PDT 24 417456540 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2695470990 Aug 09 04:25:32 PM PDT 24 Aug 09 04:25:33 PM PDT 24 590890323 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.29174885 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:04 PM PDT 24 2442599066 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3081751954 Aug 09 04:26:10 PM PDT 24 Aug 09 04:26:12 PM PDT 24 409145570 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1836722643 Aug 09 04:27:55 PM PDT 24 Aug 09 04:27:56 PM PDT 24 1127463564 ps
T57 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3404916335 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:59 PM PDT 24 479880914 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.185288264 Aug 09 04:27:58 PM PDT 24 Aug 09 04:27:59 PM PDT 24 501111144 ps
T183 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.436733220 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:12 PM PDT 24 8133629932 ps
T339 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3352600235 Aug 09 04:28:04 PM PDT 24 Aug 09 04:28:05 PM PDT 24 324037180 ps
T340 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3274927609 Aug 09 04:28:02 PM PDT 24 Aug 09 04:28:03 PM PDT 24 462177180 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2952623278 Aug 09 04:27:56 PM PDT 24 Aug 09 04:27:59 PM PDT 24 9305142472 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1428367514 Aug 09 04:24:16 PM PDT 24 Aug 09 04:24:18 PM PDT 24 4645434728 ps
T343 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.546003688 Aug 09 04:27:56 PM PDT 24 Aug 09 04:27:57 PM PDT 24 339956122 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.825873636 Aug 09 04:22:46 PM PDT 24 Aug 09 04:22:47 PM PDT 24 513896309 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3774195224 Aug 09 04:25:18 PM PDT 24 Aug 09 04:25:19 PM PDT 24 433556282 ps
T346 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3470102257 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 319311018 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3489180018 Aug 09 04:26:21 PM PDT 24 Aug 09 04:26:24 PM PDT 24 579364033 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1799766515 Aug 09 04:25:11 PM PDT 24 Aug 09 04:25:13 PM PDT 24 1348219292 ps
T348 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.445754702 Aug 09 04:28:05 PM PDT 24 Aug 09 04:28:19 PM PDT 24 8549028758 ps
T349 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3399738511 Aug 09 04:28:10 PM PDT 24 Aug 09 04:28:12 PM PDT 24 477034255 ps
T350 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4006858773 Aug 09 04:22:33 PM PDT 24 Aug 09 04:22:34 PM PDT 24 575014921 ps
T351 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3672245637 Aug 09 04:27:49 PM PDT 24 Aug 09 04:27:50 PM PDT 24 1202032740 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1665374310 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 396523315 ps
T353 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3075808913 Aug 09 04:28:05 PM PDT 24 Aug 09 04:28:06 PM PDT 24 310838171 ps
T354 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1773248094 Aug 09 04:28:18 PM PDT 24 Aug 09 04:28:19 PM PDT 24 469975954 ps
T355 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3234765882 Aug 09 04:27:49 PM PDT 24 Aug 09 04:27:50 PM PDT 24 452044786 ps
T356 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.318299268 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 493555486 ps
T357 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1257430766 Aug 09 04:28:10 PM PDT 24 Aug 09 04:28:14 PM PDT 24 1586742887 ps
T358 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2691453436 Aug 09 04:27:59 PM PDT 24 Aug 09 04:28:01 PM PDT 24 474237239 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3488934169 Aug 09 04:26:21 PM PDT 24 Aug 09 04:26:22 PM PDT 24 318557157 ps
T360 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3920747818 Aug 09 04:27:48 PM PDT 24 Aug 09 04:27:48 PM PDT 24 400775803 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1718595952 Aug 09 04:27:55 PM PDT 24 Aug 09 04:27:57 PM PDT 24 1344554737 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3326370740 Aug 09 04:25:04 PM PDT 24 Aug 09 04:25:08 PM PDT 24 7876957103 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1903645707 Aug 09 04:26:21 PM PDT 24 Aug 09 04:26:23 PM PDT 24 510657794 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.835997272 Aug 09 04:20:56 PM PDT 24 Aug 09 04:21:00 PM PDT 24 2872951534 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1788940605 Aug 09 04:27:50 PM PDT 24 Aug 09 04:27:52 PM PDT 24 447389631 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.280106730 Aug 09 04:27:58 PM PDT 24 Aug 09 04:28:00 PM PDT 24 495160493 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3931852043 Aug 09 04:23:33 PM PDT 24 Aug 09 04:23:34 PM PDT 24 479018863 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3460802379 Aug 09 04:27:58 PM PDT 24 Aug 09 04:27:59 PM PDT 24 481246675 ps
T369 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.789216160 Aug 09 04:22:19 PM PDT 24 Aug 09 04:22:20 PM PDT 24 625466116 ps
T370 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2768842513 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:05 PM PDT 24 2520383418 ps
T371 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.340194791 Aug 09 04:27:48 PM PDT 24 Aug 09 04:27:49 PM PDT 24 290224923 ps
T372 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2007986905 Aug 09 04:27:48 PM PDT 24 Aug 09 04:27:59 PM PDT 24 361597497 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4099446599 Aug 09 04:28:16 PM PDT 24 Aug 09 04:28:17 PM PDT 24 306080601 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2378720275 Aug 09 04:25:11 PM PDT 24 Aug 09 04:25:12 PM PDT 24 452208624 ps
T375 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1808640947 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:07 PM PDT 24 314196281 ps
T376 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3252490973 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:01 PM PDT 24 393031770 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1107285074 Aug 09 04:27:49 PM PDT 24 Aug 09 04:27:50 PM PDT 24 469655165 ps
T378 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2399237280 Aug 09 04:28:00 PM PDT 24 Aug 09 04:28:02 PM PDT 24 351636017 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4195248550 Aug 09 04:25:24 PM PDT 24 Aug 09 04:25:28 PM PDT 24 1406237309 ps
T380 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.405327538 Aug 09 04:28:05 PM PDT 24 Aug 09 04:28:06 PM PDT 24 466933949 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4174898587 Aug 09 04:28:07 PM PDT 24 Aug 09 04:28:08 PM PDT 24 372186286 ps
T382 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.289636447 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 516874501 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4098098941 Aug 09 04:25:11 PM PDT 24 Aug 09 04:25:12 PM PDT 24 515132412 ps
T384 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1323772365 Aug 09 04:27:56 PM PDT 24 Aug 09 04:27:57 PM PDT 24 330817117 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2371370650 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:58 PM PDT 24 473981416 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3994285326 Aug 09 04:28:23 PM PDT 24 Aug 09 04:28:26 PM PDT 24 8204382572 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.996229208 Aug 09 04:22:32 PM PDT 24 Aug 09 04:22:42 PM PDT 24 6997810845 ps
T388 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3033341893 Aug 09 04:28:20 PM PDT 24 Aug 09 04:28:21 PM PDT 24 291025728 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1042924993 Aug 09 04:27:56 PM PDT 24 Aug 09 04:27:57 PM PDT 24 521559254 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1692542599 Aug 09 04:22:23 PM PDT 24 Aug 09 04:22:26 PM PDT 24 1529944252 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1332120685 Aug 09 04:27:51 PM PDT 24 Aug 09 04:27:57 PM PDT 24 4263869104 ps
T392 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3585698823 Aug 09 04:27:53 PM PDT 24 Aug 09 04:27:57 PM PDT 24 2232905367 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.721203685 Aug 09 04:25:05 PM PDT 24 Aug 09 04:25:07 PM PDT 24 780249923 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4195284590 Aug 09 04:22:30 PM PDT 24 Aug 09 04:22:33 PM PDT 24 1230177132 ps
T395 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2464371532 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:58 PM PDT 24 504043015 ps
T396 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.536650531 Aug 09 04:27:57 PM PDT 24 Aug 09 04:27:59 PM PDT 24 3902849793 ps
T397 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1369158791 Aug 09 04:28:28 PM PDT 24 Aug 09 04:28:28 PM PDT 24 427921706 ps
T398 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4187024798 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:08 PM PDT 24 540483583 ps
T399 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1063546504 Aug 09 04:27:50 PM PDT 24 Aug 09 04:27:55 PM PDT 24 8136577284 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3835670328 Aug 09 04:25:23 PM PDT 24 Aug 09 04:25:25 PM PDT 24 409541738 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2026164624 Aug 09 04:22:40 PM PDT 24 Aug 09 04:22:40 PM PDT 24 560931290 ps
T184 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.758950204 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:13 PM PDT 24 8108515288 ps
T401 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2595989339 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 514827745 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3419617339 Aug 09 04:27:59 PM PDT 24 Aug 09 04:28:01 PM PDT 24 430260985 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4044229317 Aug 09 04:28:05 PM PDT 24 Aug 09 04:28:07 PM PDT 24 562602008 ps
T404 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.614434407 Aug 09 04:27:52 PM PDT 24 Aug 09 04:27:54 PM PDT 24 2414233712 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1055058893 Aug 09 04:26:10 PM PDT 24 Aug 09 04:26:12 PM PDT 24 678292660 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1025447339 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 484207356 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1734633511 Aug 09 04:28:10 PM PDT 24 Aug 09 04:28:13 PM PDT 24 362669801 ps
T408 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.661415048 Aug 09 04:28:06 PM PDT 24 Aug 09 04:28:07 PM PDT 24 406415030 ps
T409 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.163633516 Aug 09 04:28:07 PM PDT 24 Aug 09 04:28:08 PM PDT 24 381401286 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4224934045 Aug 09 04:28:01 PM PDT 24 Aug 09 04:28:02 PM PDT 24 1562914350 ps
T411 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2979141006 Aug 09 04:27:53 PM PDT 24 Aug 09 04:27:54 PM PDT 24 357388019 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1276476617 Aug 09 04:27:54 PM PDT 24 Aug 09 04:27:56 PM PDT 24 534388722 ps
T413 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1251057676 Aug 09 04:28:12 PM PDT 24 Aug 09 04:28:17 PM PDT 24 7742989929 ps
T414 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.193140917 Aug 09 04:28:08 PM PDT 24 Aug 09 04:28:10 PM PDT 24 522194156 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2609292319 Aug 09 04:27:58 PM PDT 24 Aug 09 04:28:00 PM PDT 24 4495601461 ps
T416 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.8681586 Aug 09 04:28:08 PM PDT 24 Aug 09 04:28:09 PM PDT 24 464526683 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3693177036 Aug 09 04:21:44 PM PDT 24 Aug 09 04:21:46 PM PDT 24 517652032 ps

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.389526243
Short name T8
Test name
Test status
Simulation time 23084681812 ps
CPU time 172.94 seconds
Started Aug 09 04:26:29 PM PDT 24
Finished Aug 09 04:29:22 PM PDT 24
Peak memory 198492 kb
Host smart-5c4622d6-27eb-41ba-9169-526fad91fdfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389526243 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.389526243
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2333493226
Short name T12
Test name
Test status
Simulation time 49262415915 ps
CPU time 479.47 seconds
Started Aug 09 04:24:53 PM PDT 24
Finished Aug 09 04:32:53 PM PDT 24
Peak memory 201568 kb
Host smart-9374fba1-4e32-4c1b-9011-0bb69354a622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333493226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2333493226
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2413273461
Short name T71
Test name
Test status
Simulation time 2329208983933 ps
CPU time 883.17 seconds
Started Aug 09 04:26:13 PM PDT 24
Finished Aug 09 04:40:57 PM PDT 24
Peak memory 208288 kb
Host smart-3f91374b-c483-4beb-941d-8ba38809549a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413273461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2413273461
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.102566227
Short name T29
Test name
Test status
Simulation time 4701536650 ps
CPU time 8.18 seconds
Started Aug 09 04:25:12 PM PDT 24
Finished Aug 09 04:25:20 PM PDT 24
Peak memory 196096 kb
Host smart-afa905cb-1943-470f-8263-73a1fe88b724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102566227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.102566227
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1990958158
Short name T3
Test name
Test status
Simulation time 99335896556 ps
CPU time 153.92 seconds
Started Aug 09 04:23:11 PM PDT 24
Finished Aug 09 04:25:45 PM PDT 24
Peak memory 193484 kb
Host smart-13298f27-88e1-41c9-acb1-0d39ca988de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990958158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1990958158
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4147292140
Short name T91
Test name
Test status
Simulation time 1086141042175 ps
CPU time 620.55 seconds
Started Aug 09 04:23:02 PM PDT 24
Finished Aug 09 04:33:23 PM PDT 24
Peak memory 206032 kb
Host smart-5f50dce8-8f1e-42cf-be9a-a6e0dbbbf519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147292140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4147292140
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2862757961
Short name T94
Test name
Test status
Simulation time 54988615234 ps
CPU time 538.6 seconds
Started Aug 09 04:26:18 PM PDT 24
Finished Aug 09 04:35:18 PM PDT 24
Peak memory 203092 kb
Host smart-94e5c021-345b-483a-81e5-a489f54c3356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862757961 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2862757961
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3497889202
Short name T37
Test name
Test status
Simulation time 100240538630 ps
CPU time 412.98 seconds
Started Aug 09 04:25:18 PM PDT 24
Finished Aug 09 04:32:11 PM PDT 24
Peak memory 203048 kb
Host smart-6fb72cae-7cf2-4ffd-bbb9-0b91a2fb7bd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497889202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3497889202
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4219281366
Short name T88
Test name
Test status
Simulation time 45755022692 ps
CPU time 469.03 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:33:13 PM PDT 24
Peak memory 205896 kb
Host smart-82e4599c-74ce-4e94-8593-e8902a3e6002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219281366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4219281366
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1140556870
Short name T73
Test name
Test status
Simulation time 27422274157 ps
CPU time 200.54 seconds
Started Aug 09 04:23:09 PM PDT 24
Finished Aug 09 04:26:30 PM PDT 24
Peak memory 206808 kb
Host smart-0377292d-bedd-4343-83c9-e173fbec9691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140556870 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1140556870
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.240324590
Short name T35
Test name
Test status
Simulation time 117290551766 ps
CPU time 958.97 seconds
Started Aug 09 04:24:58 PM PDT 24
Finished Aug 09 04:40:57 PM PDT 24
Peak memory 207888 kb
Host smart-4169a25e-aa45-40e1-bde3-09c502aac9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240324590 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.240324590
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.913658224
Short name T89
Test name
Test status
Simulation time 28858428238 ps
CPU time 9.55 seconds
Started Aug 09 04:26:23 PM PDT 24
Finished Aug 09 04:26:32 PM PDT 24
Peak memory 193068 kb
Host smart-9f7bf51f-d450-46bb-adb8-c84d67452cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913658224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.913658224
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3984548794
Short name T15
Test name
Test status
Simulation time 8249668589 ps
CPU time 4.18 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 214680 kb
Host smart-f9ebe560-8a7a-4e06-9b01-726ec5454f5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984548794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3984548794
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1142807529
Short name T110
Test name
Test status
Simulation time 125254368251 ps
CPU time 1410.58 seconds
Started Aug 09 04:23:25 PM PDT 24
Finished Aug 09 04:46:56 PM PDT 24
Peak memory 215400 kb
Host smart-df54c433-d135-445f-962c-3b13a7c3eac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142807529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1142807529
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3758850668
Short name T99
Test name
Test status
Simulation time 50179119780 ps
CPU time 539.54 seconds
Started Aug 09 04:26:28 PM PDT 24
Finished Aug 09 04:35:28 PM PDT 24
Peak memory 202256 kb
Host smart-0b68ffe8-91bd-4ebd-9ff7-94d52ecf6169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758850668 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3758850668
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.148387447
Short name T97
Test name
Test status
Simulation time 32941214692 ps
CPU time 345.07 seconds
Started Aug 09 04:25:15 PM PDT 24
Finished Aug 09 04:31:00 PM PDT 24
Peak memory 205924 kb
Host smart-b7d1ffb8-90bb-45ba-b796-1950cca1fc6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148387447 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.148387447
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.354979817
Short name T104
Test name
Test status
Simulation time 114244632862 ps
CPU time 174.87 seconds
Started Aug 09 04:24:58 PM PDT 24
Finished Aug 09 04:27:53 PM PDT 24
Peak memory 198296 kb
Host smart-440adeac-4414-4641-ac3c-938e698cdbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354979817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.354979817
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3228345148
Short name T108
Test name
Test status
Simulation time 34368623057 ps
CPU time 26.69 seconds
Started Aug 09 04:25:37 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 191196 kb
Host smart-fa793b76-26a3-4f6a-8b2b-f0a503f48cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228345148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3228345148
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3992952643
Short name T95
Test name
Test status
Simulation time 342080394370 ps
CPU time 476.91 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:34:00 PM PDT 24
Peak memory 198096 kb
Host smart-b22d1806-3f54-4b81-a136-3ec97fe6774c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992952643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3992952643
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1613030373
Short name T75
Test name
Test status
Simulation time 170915058532 ps
CPU time 673.39 seconds
Started Aug 09 04:21:38 PM PDT 24
Finished Aug 09 04:32:51 PM PDT 24
Peak memory 214984 kb
Host smart-7d981370-0fb3-4f68-bfdd-7e72ce1a569d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613030373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1613030373
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.18468973
Short name T118
Test name
Test status
Simulation time 98806870417 ps
CPU time 47.09 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:26:08 PM PDT 24
Peak memory 192780 kb
Host smart-b0e5d3de-71d3-4ec5-b418-a6a4dcd6ff14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18468973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_al
l.18468973
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2455088169
Short name T25
Test name
Test status
Simulation time 363214878362 ps
CPU time 264.8 seconds
Started Aug 09 04:20:47 PM PDT 24
Finished Aug 09 04:25:12 PM PDT 24
Peak memory 193100 kb
Host smart-e0bb699a-c83a-4453-8c55-d6441bbc7c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455088169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2455088169
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1671724664
Short name T112
Test name
Test status
Simulation time 74764342261 ps
CPU time 29.23 seconds
Started Aug 09 04:25:08 PM PDT 24
Finished Aug 09 04:25:37 PM PDT 24
Peak memory 191020 kb
Host smart-2a15dcc6-fdfe-4609-936e-ef09f225a57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671724664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1671724664
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.696077342
Short name T40
Test name
Test status
Simulation time 41709045071 ps
CPU time 144.56 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:27:49 PM PDT 24
Peak memory 206720 kb
Host smart-2082312e-8e27-4eba-8225-406027268624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696077342 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.696077342
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3310601603
Short name T39
Test name
Test status
Simulation time 44266344501 ps
CPU time 447.1 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:32:47 PM PDT 24
Peak memory 211924 kb
Host smart-4d7fade0-fa5f-4e84-8b92-4a864a3578aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310601603 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3310601603
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2944592769
Short name T111
Test name
Test status
Simulation time 42912770036 ps
CPU time 337.03 seconds
Started Aug 09 04:24:25 PM PDT 24
Finished Aug 09 04:30:02 PM PDT 24
Peak memory 206792 kb
Host smart-a6183b51-e3aa-4387-a039-0cf7cdeea3a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944592769 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2944592769
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4006922425
Short name T13
Test name
Test status
Simulation time 188705639945 ps
CPU time 138.71 seconds
Started Aug 09 04:25:27 PM PDT 24
Finished Aug 09 04:27:46 PM PDT 24
Peak memory 193096 kb
Host smart-10358ec6-2b1b-4a71-adec-33d275f89da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006922425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4006922425
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3280350469
Short name T143
Test name
Test status
Simulation time 221694987084 ps
CPU time 997.68 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:42:50 PM PDT 24
Peak memory 214756 kb
Host smart-57fc2459-1968-4770-8e0c-512755412e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280350469 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3280350469
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1256318141
Short name T141
Test name
Test status
Simulation time 166096186862 ps
CPU time 17.4 seconds
Started Aug 09 04:25:54 PM PDT 24
Finished Aug 09 04:26:11 PM PDT 24
Peak memory 191932 kb
Host smart-aeaedbf7-f64c-41ef-9fd6-84fa64015d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256318141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1256318141
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2830741154
Short name T119
Test name
Test status
Simulation time 365183016037 ps
CPU time 466.81 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:33:07 PM PDT 24
Peak memory 190764 kb
Host smart-38f4f9e9-6a2e-41bd-b51f-f51db5bfa368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830741154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2830741154
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1670162523
Short name T76
Test name
Test status
Simulation time 71358593906 ps
CPU time 263.68 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:30:03 PM PDT 24
Peak memory 207588 kb
Host smart-d67a420e-ca3f-40e5-94bb-76460a6c4024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670162523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1670162523
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3278137131
Short name T137
Test name
Test status
Simulation time 72421108796 ps
CPU time 102.88 seconds
Started Aug 09 04:24:47 PM PDT 24
Finished Aug 09 04:26:30 PM PDT 24
Peak memory 198348 kb
Host smart-1183495f-4006-4630-8701-b87fc3ccea15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278137131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3278137131
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.907499071
Short name T84
Test name
Test status
Simulation time 74730863263 ps
CPU time 27.87 seconds
Started Aug 09 04:25:05 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 191420 kb
Host smart-05df3503-117e-49af-a3bf-6a6cb3b45aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907499071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.907499071
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1118117869
Short name T136
Test name
Test status
Simulation time 19313032189 ps
CPU time 214.8 seconds
Started Aug 09 04:24:54 PM PDT 24
Finished Aug 09 04:28:28 PM PDT 24
Peak memory 198620 kb
Host smart-574d3f3a-d6f7-4290-86cd-1a7806243576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118117869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1118117869
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1985943528
Short name T82
Test name
Test status
Simulation time 193789980886 ps
CPU time 226.57 seconds
Started Aug 09 04:26:26 PM PDT 24
Finished Aug 09 04:30:13 PM PDT 24
Peak memory 192688 kb
Host smart-c0669cb4-c892-431b-94c0-976016182bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985943528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1985943528
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2091498522
Short name T96
Test name
Test status
Simulation time 167213547675 ps
CPU time 418.38 seconds
Started Aug 09 04:26:31 PM PDT 24
Finished Aug 09 04:33:29 PM PDT 24
Peak memory 203460 kb
Host smart-054f87e9-7f4d-43dd-ada0-6627c6db0193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091498522 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2091498522
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1682626077
Short name T101
Test name
Test status
Simulation time 135213735027 ps
CPU time 87.38 seconds
Started Aug 09 04:25:37 PM PDT 24
Finished Aug 09 04:27:05 PM PDT 24
Peak memory 182776 kb
Host smart-4bc0b0da-3a3f-4b0b-b3af-29ff7e60cfcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682626077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1682626077
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2268369501
Short name T132
Test name
Test status
Simulation time 213333350626 ps
CPU time 81.36 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:26:41 PM PDT 24
Peak memory 189760 kb
Host smart-28d507be-e0c5-4723-95c4-fbea740cf5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268369501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2268369501
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2039319552
Short name T121
Test name
Test status
Simulation time 34901207833 ps
CPU time 24.75 seconds
Started Aug 09 04:26:16 PM PDT 24
Finished Aug 09 04:26:41 PM PDT 24
Peak memory 191780 kb
Host smart-276de042-b3bf-4611-b89d-f9994d3f4349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039319552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2039319552
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.946698212
Short name T128
Test name
Test status
Simulation time 98673227061 ps
CPU time 743.58 seconds
Started Aug 09 04:26:24 PM PDT 24
Finished Aug 09 04:38:47 PM PDT 24
Peak memory 214704 kb
Host smart-6c3f23af-bcc6-4df6-91f3-b8282b960e11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946698212 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.946698212
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1258270247
Short name T74
Test name
Test status
Simulation time 7276037529 ps
CPU time 49.06 seconds
Started Aug 09 04:21:34 PM PDT 24
Finished Aug 09 04:22:23 PM PDT 24
Peak memory 198212 kb
Host smart-40232a75-1f2b-43f9-851d-7a03b111ed03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258270247 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1258270247
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2658261098
Short name T126
Test name
Test status
Simulation time 97882214815 ps
CPU time 38.16 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 198244 kb
Host smart-3ef9330b-3be4-4676-8ad0-37b06e7fce76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658261098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2658261098
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3611776330
Short name T66
Test name
Test status
Simulation time 40651783173 ps
CPU time 401.65 seconds
Started Aug 09 04:23:03 PM PDT 24
Finished Aug 09 04:29:45 PM PDT 24
Peak memory 214772 kb
Host smart-b9a560f3-5418-49a9-9d53-fd32e5be8dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611776330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3611776330
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.980125066
Short name T103
Test name
Test status
Simulation time 272552099708 ps
CPU time 388.08 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:32:40 PM PDT 24
Peak memory 192764 kb
Host smart-3edaa6f4-0d3e-49e8-85d9-ae7a6e1c8ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980125066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.980125066
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1189547354
Short name T36
Test name
Test status
Simulation time 63896195120 ps
CPU time 117.8 seconds
Started Aug 09 04:25:22 PM PDT 24
Finished Aug 09 04:27:20 PM PDT 24
Peak memory 206928 kb
Host smart-13cfe7a1-9646-41f2-8699-fc890f66472f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189547354 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1189547354
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3132131716
Short name T102
Test name
Test status
Simulation time 506215283987 ps
CPU time 383.17 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:31:34 PM PDT 24
Peak memory 191792 kb
Host smart-e110003a-77bb-433f-aa87-695f14220a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132131716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3132131716
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2368172913
Short name T26
Test name
Test status
Simulation time 596004879323 ps
CPU time 486.89 seconds
Started Aug 09 04:24:44 PM PDT 24
Finished Aug 09 04:32:51 PM PDT 24
Peak memory 212120 kb
Host smart-35448930-72ee-463d-92e1-4591feb17022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368172913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2368172913
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3962739070
Short name T93
Test name
Test status
Simulation time 265790575281 ps
CPU time 213.32 seconds
Started Aug 09 04:25:15 PM PDT 24
Finished Aug 09 04:28:49 PM PDT 24
Peak memory 192692 kb
Host smart-629ac458-f02c-4b49-b85c-88bfb35b9461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962739070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3962739070
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3196065493
Short name T113
Test name
Test status
Simulation time 141882151022 ps
CPU time 88.97 seconds
Started Aug 09 04:23:05 PM PDT 24
Finished Aug 09 04:24:34 PM PDT 24
Peak memory 190692 kb
Host smart-cac79802-f17c-4141-b9b7-454c7b0f9cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196065493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3196065493
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2660835364
Short name T21
Test name
Test status
Simulation time 106369777897 ps
CPU time 173.17 seconds
Started Aug 09 04:25:26 PM PDT 24
Finished Aug 09 04:28:19 PM PDT 24
Peak memory 198460 kb
Host smart-c34efad5-f1dc-4c1f-8103-f1ad40d4590e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660835364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2660835364
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2665098133
Short name T138
Test name
Test status
Simulation time 502053126444 ps
CPU time 285.22 seconds
Started Aug 09 04:26:18 PM PDT 24
Finished Aug 09 04:31:03 PM PDT 24
Peak memory 191928 kb
Host smart-de27adc8-cdac-440f-9cd0-06fb3b2ce7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665098133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2665098133
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1743139504
Short name T158
Test name
Test status
Simulation time 117171687785 ps
CPU time 19.76 seconds
Started Aug 09 04:24:34 PM PDT 24
Finished Aug 09 04:24:54 PM PDT 24
Peak memory 193484 kb
Host smart-8eac0d42-4be4-4d4b-bf10-ab86a73b740c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743139504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1743139504
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.93683285
Short name T151
Test name
Test status
Simulation time 74918497998 ps
CPU time 150.53 seconds
Started Aug 09 04:24:26 PM PDT 24
Finished Aug 09 04:26:57 PM PDT 24
Peak memory 214360 kb
Host smart-0c5b9501-39c0-4437-b6f4-a9df05e1c8c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93683285 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.93683285
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2946742593
Short name T77
Test name
Test status
Simulation time 44038899891 ps
CPU time 333.04 seconds
Started Aug 09 04:24:25 PM PDT 24
Finished Aug 09 04:29:58 PM PDT 24
Peak memory 207216 kb
Host smart-7252d404-1322-4e4c-aecf-65d0f11ce2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946742593 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2946742593
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2236480961
Short name T45
Test name
Test status
Simulation time 6076232496 ps
CPU time 20.39 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:21:09 PM PDT 24
Peak memory 195732 kb
Host smart-3c12552f-2374-4a3a-84b9-5308acbd74ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236480961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2236480961
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3851885899
Short name T115
Test name
Test status
Simulation time 131751963200 ps
CPU time 195.43 seconds
Started Aug 09 04:22:03 PM PDT 24
Finished Aug 09 04:25:19 PM PDT 24
Peak memory 193080 kb
Host smart-88f41afc-10c3-4eac-948d-26070f963411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851885899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3851885899
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3591618561
Short name T85
Test name
Test status
Simulation time 76772109799 ps
CPU time 117.22 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:27:16 PM PDT 24
Peak memory 191680 kb
Host smart-441469aa-b7ca-4276-95ac-c73e80971d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591618561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3591618561
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.4159484074
Short name T140
Test name
Test status
Simulation time 8704379988 ps
CPU time 6.47 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:26:25 PM PDT 24
Peak memory 189616 kb
Host smart-15f07d9a-7ab0-45f2-9109-ca1e51bb2abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159484074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.4159484074
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1714364341
Short name T30
Test name
Test status
Simulation time 1560759018 ps
CPU time 1.06 seconds
Started Aug 09 04:25:33 PM PDT 24
Finished Aug 09 04:25:34 PM PDT 24
Peak memory 183388 kb
Host smart-0af88c14-1013-4468-b0d5-30fd799170dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714364341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1714364341
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2132630396
Short name T41
Test name
Test status
Simulation time 111738618097 ps
CPU time 158.68 seconds
Started Aug 09 04:24:34 PM PDT 24
Finished Aug 09 04:27:13 PM PDT 24
Peak memory 192388 kb
Host smart-83e980aa-bb19-428e-80de-14aff739c95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132630396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2132630396
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.738807176
Short name T98
Test name
Test status
Simulation time 142333444251 ps
CPU time 224.98 seconds
Started Aug 09 04:25:02 PM PDT 24
Finished Aug 09 04:28:47 PM PDT 24
Peak memory 193088 kb
Host smart-5cbbb045-6176-4f3b-be94-aba2f6417252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738807176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.738807176
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3343596509
Short name T87
Test name
Test status
Simulation time 158019523055 ps
CPU time 21.09 seconds
Started Aug 09 04:25:40 PM PDT 24
Finished Aug 09 04:26:02 PM PDT 24
Peak memory 193004 kb
Host smart-c6c85e7d-9dbe-438a-bc08-9b327ca57d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343596509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3343596509
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2627129292
Short name T67
Test name
Test status
Simulation time 24547169288 ps
CPU time 134.38 seconds
Started Aug 09 04:25:04 PM PDT 24
Finished Aug 09 04:27:19 PM PDT 24
Peak memory 213496 kb
Host smart-2547006b-3b0c-4317-a39f-0359e244bf4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627129292 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2627129292
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3693620089
Short name T116
Test name
Test status
Simulation time 250739603950 ps
CPU time 94.03 seconds
Started Aug 09 04:25:57 PM PDT 24
Finished Aug 09 04:27:31 PM PDT 24
Peak memory 192840 kb
Host smart-35c94811-2a92-4cfc-bf57-6a7aac5387d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693620089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3693620089
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3969373181
Short name T86
Test name
Test status
Simulation time 498841369 ps
CPU time 1.39 seconds
Started Aug 09 04:25:23 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 195796 kb
Host smart-598cdbb9-afc9-46cd-8afc-f05d4bae8b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969373181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3969373181
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2934799044
Short name T68
Test name
Test status
Simulation time 28017079046 ps
CPU time 153.94 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:27:54 PM PDT 24
Peak memory 211268 kb
Host smart-6832884d-0ca0-45ed-9898-404debbe71b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934799044 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2934799044
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.685355994
Short name T144
Test name
Test status
Simulation time 445086232239 ps
CPU time 533.95 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:34:26 PM PDT 24
Peak memory 212424 kb
Host smart-e3f30be7-26bd-4284-99fd-03295cb4f50a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685355994 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.685355994
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.4029923536
Short name T145
Test name
Test status
Simulation time 125482337021 ps
CPU time 187.6 seconds
Started Aug 09 04:25:49 PM PDT 24
Finished Aug 09 04:28:57 PM PDT 24
Peak memory 191304 kb
Host smart-667acbde-42c4-410a-a5b6-81e3525c8a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029923536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.4029923536
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.10870397
Short name T131
Test name
Test status
Simulation time 426653256143 ps
CPU time 597.98 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:36:15 PM PDT 24
Peak memory 191972 kb
Host smart-9462a36a-0567-4f3c-b710-d47aac8ac426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_al
l.10870397
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1338028172
Short name T150
Test name
Test status
Simulation time 45646469427 ps
CPU time 357.56 seconds
Started Aug 09 04:26:34 PM PDT 24
Finished Aug 09 04:32:32 PM PDT 24
Peak memory 207512 kb
Host smart-99af32eb-af6f-4b7f-9732-614f75b8394f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338028172 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1338028172
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3624686036
Short name T69
Test name
Test status
Simulation time 182672631688 ps
CPU time 224.7 seconds
Started Aug 09 04:23:50 PM PDT 24
Finished Aug 09 04:27:35 PM PDT 24
Peak memory 214076 kb
Host smart-c2fbefe0-84ef-4ad5-9909-d250747145c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624686036 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3624686036
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3158809580
Short name T124
Test name
Test status
Simulation time 452901433 ps
CPU time 1.13 seconds
Started Aug 09 04:25:31 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 196060 kb
Host smart-e2b4050d-ff4f-431c-b5cf-9084f212818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158809580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3158809580
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4057158282
Short name T10
Test name
Test status
Simulation time 74062666005 ps
CPU time 107.05 seconds
Started Aug 09 04:25:21 PM PDT 24
Finished Aug 09 04:27:08 PM PDT 24
Peak memory 191960 kb
Host smart-2b91430e-56ca-4982-bad0-0b590613b560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057158282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4057158282
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2060869861
Short name T134
Test name
Test status
Simulation time 414225345 ps
CPU time 1.22 seconds
Started Aug 09 04:25:33 PM PDT 24
Finished Aug 09 04:25:35 PM PDT 24
Peak memory 196648 kb
Host smart-c892829a-551b-4951-b63b-05be2cc6059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060869861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2060869861
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.476566775
Short name T42
Test name
Test status
Simulation time 137506259721 ps
CPU time 95.06 seconds
Started Aug 09 04:25:26 PM PDT 24
Finished Aug 09 04:27:02 PM PDT 24
Peak memory 191152 kb
Host smart-ad358a59-4661-4d0b-9abe-273fcc324503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476566775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.476566775
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1240363405
Short name T171
Test name
Test status
Simulation time 429821479173 ps
CPU time 640.52 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:36:05 PM PDT 24
Peak memory 191816 kb
Host smart-1ab33d5b-f759-4a1c-93c1-971ab0bceff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240363405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1240363405
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1604162660
Short name T129
Test name
Test status
Simulation time 382096785 ps
CPU time 0.9 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:22 PM PDT 24
Peak memory 196400 kb
Host smart-92385f07-1785-4234-8ccf-c9934f1ed59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604162660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1604162660
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3915292764
Short name T83
Test name
Test status
Simulation time 38470251032 ps
CPU time 82.3 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:26:42 PM PDT 24
Peak memory 198000 kb
Host smart-d2dadfa7-32c5-4e8a-b8cf-90416628a774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915292764 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3915292764
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3330851619
Short name T135
Test name
Test status
Simulation time 371562017 ps
CPU time 1.14 seconds
Started Aug 09 04:24:30 PM PDT 24
Finished Aug 09 04:24:31 PM PDT 24
Peak memory 196708 kb
Host smart-457c5a8f-1ab0-4658-aa12-bec44afed9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330851619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3330851619
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1833439790
Short name T78
Test name
Test status
Simulation time 411878728 ps
CPU time 0.78 seconds
Started Aug 09 04:24:29 PM PDT 24
Finished Aug 09 04:24:30 PM PDT 24
Peak memory 196712 kb
Host smart-072da7d5-1cf2-43c3-aef9-63bcd8826fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833439790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1833439790
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3059236788
Short name T159
Test name
Test status
Simulation time 22225933671 ps
CPU time 122.08 seconds
Started Aug 09 04:24:55 PM PDT 24
Finished Aug 09 04:26:57 PM PDT 24
Peak memory 206908 kb
Host smart-5c360b47-a007-43f1-a140-206b96b0a113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059236788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3059236788
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.8695203
Short name T38
Test name
Test status
Simulation time 54230671163 ps
CPU time 110.32 seconds
Started Aug 09 04:25:07 PM PDT 24
Finished Aug 09 04:26:57 PM PDT 24
Peak memory 198756 kb
Host smart-2ebf662c-1233-4c65-9eaf-6103dfa01f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8695203 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.8695203
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.912441593
Short name T79
Test name
Test status
Simulation time 505298266622 ps
CPU time 158.36 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 198268 kb
Host smart-c5b99c5c-8ce4-42cc-ba20-ddee98fef198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912441593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.912441593
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1937022853
Short name T90
Test name
Test status
Simulation time 352899520917 ps
CPU time 506.6 seconds
Started Aug 09 04:25:44 PM PDT 24
Finished Aug 09 04:34:11 PM PDT 24
Peak memory 198292 kb
Host smart-b910526c-b225-4399-90d5-9a2ebbe6a9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937022853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1937022853
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3795300487
Short name T142
Test name
Test status
Simulation time 562851245 ps
CPU time 0.75 seconds
Started Aug 09 04:25:40 PM PDT 24
Finished Aug 09 04:25:41 PM PDT 24
Peak memory 196532 kb
Host smart-c546b4c8-cfbb-4f07-b08e-58669cb4db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795300487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3795300487
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4203358603
Short name T117
Test name
Test status
Simulation time 123174677832 ps
CPU time 187.24 seconds
Started Aug 09 04:26:21 PM PDT 24
Finished Aug 09 04:29:29 PM PDT 24
Peak memory 191972 kb
Host smart-1838c0c8-a917-4645-a00e-ad0256860897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203358603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4203358603
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1042219133
Short name T92
Test name
Test status
Simulation time 396852166 ps
CPU time 0.72 seconds
Started Aug 09 04:25:10 PM PDT 24
Finished Aug 09 04:25:11 PM PDT 24
Peak memory 195704 kb
Host smart-88645f20-5a30-4cc9-89d0-12db9e81dd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042219133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1042219133
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.193231945
Short name T120
Test name
Test status
Simulation time 591191906 ps
CPU time 1.01 seconds
Started Aug 09 04:25:58 PM PDT 24
Finished Aug 09 04:25:59 PM PDT 24
Peak memory 196480 kb
Host smart-9e90da98-73d7-4520-abc6-07615d867bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193231945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.193231945
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3290837938
Short name T123
Test name
Test status
Simulation time 545376125 ps
CPU time 0.95 seconds
Started Aug 09 04:24:46 PM PDT 24
Finished Aug 09 04:24:47 PM PDT 24
Peak memory 196704 kb
Host smart-30f8c45a-e581-4d07-8fba-10e11ef5c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290837938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3290837938
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2622363517
Short name T130
Test name
Test status
Simulation time 553266072 ps
CPU time 0.81 seconds
Started Aug 09 04:24:56 PM PDT 24
Finished Aug 09 04:24:57 PM PDT 24
Peak memory 196820 kb
Host smart-ef3f8e1c-f73d-47b6-a193-54ef32825939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622363517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2622363517
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3649005957
Short name T157
Test name
Test status
Simulation time 338397721143 ps
CPU time 527.18 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:34:50 PM PDT 24
Peak memory 198008 kb
Host smart-de8f08a4-41b3-4360-8cc3-4b759ccbbbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649005957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3649005957
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.500877519
Short name T149
Test name
Test status
Simulation time 114043743791 ps
CPU time 47.42 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:27:00 PM PDT 24
Peak memory 190960 kb
Host smart-634c4086-2980-48cd-80e1-b1819ff78382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500877519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.500877519
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.45999997
Short name T147
Test name
Test status
Simulation time 539306302 ps
CPU time 1.44 seconds
Started Aug 09 04:24:22 PM PDT 24
Finished Aug 09 04:24:24 PM PDT 24
Peak memory 196752 kb
Host smart-d5fbb2b2-2453-4e01-94a8-6b3d4fc1d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45999997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.45999997
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3710397898
Short name T139
Test name
Test status
Simulation time 466507229 ps
CPU time 1.17 seconds
Started Aug 09 04:25:41 PM PDT 24
Finished Aug 09 04:25:42 PM PDT 24
Peak memory 196636 kb
Host smart-391c87b4-ce08-4dc3-a307-5d99cc0f2d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710397898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3710397898
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2650928045
Short name T146
Test name
Test status
Simulation time 567494649 ps
CPU time 0.78 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 196712 kb
Host smart-093060aa-713e-4c2f-8393-f34aee11c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650928045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2650928045
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3717782502
Short name T107
Test name
Test status
Simulation time 21059956519 ps
CPU time 7.35 seconds
Started Aug 09 04:24:22 PM PDT 24
Finished Aug 09 04:24:29 PM PDT 24
Peak memory 198448 kb
Host smart-7e303c7e-9622-498c-91c1-5c188b2f7b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717782502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3717782502
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2529712974
Short name T125
Test name
Test status
Simulation time 369650013 ps
CPU time 0.89 seconds
Started Aug 09 04:21:48 PM PDT 24
Finished Aug 09 04:21:49 PM PDT 24
Peak memory 196736 kb
Host smart-8a4a6b01-4e48-487e-b026-1d3afa97884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529712974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2529712974
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1461756897
Short name T106
Test name
Test status
Simulation time 562727879 ps
CPU time 1.44 seconds
Started Aug 09 04:23:12 PM PDT 24
Finished Aug 09 04:23:14 PM PDT 24
Peak memory 196964 kb
Host smart-8cbc876d-62e6-4a09-9904-7fd639fbaed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461756897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1461756897
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2938047143
Short name T114
Test name
Test status
Simulation time 571861854 ps
CPU time 1.51 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:20:51 PM PDT 24
Peak memory 196668 kb
Host smart-c3423f50-c3b9-417f-a0b1-51c558efa8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938047143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2938047143
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3076308468
Short name T127
Test name
Test status
Simulation time 442556186 ps
CPU time 0.88 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 196440 kb
Host smart-1a6de8f2-3930-411d-ab2e-70971ab1c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076308468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3076308468
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.511806871
Short name T164
Test name
Test status
Simulation time 55081468162 ps
CPU time 7.19 seconds
Started Aug 09 04:24:39 PM PDT 24
Finished Aug 09 04:24:47 PM PDT 24
Peak memory 192400 kb
Host smart-bd0cf6ac-07dc-49df-8b30-19b9c888c7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511806871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.511806871
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2474369457
Short name T43
Test name
Test status
Simulation time 142030372564 ps
CPU time 218.46 seconds
Started Aug 09 04:25:22 PM PDT 24
Finished Aug 09 04:29:00 PM PDT 24
Peak memory 198268 kb
Host smart-e78a4b76-1aaf-4598-8941-d6ccc5ff4c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474369457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2474369457
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1952093835
Short name T133
Test name
Test status
Simulation time 506072577 ps
CPU time 1.4 seconds
Started Aug 09 04:21:13 PM PDT 24
Finished Aug 09 04:21:15 PM PDT 24
Peak memory 196796 kb
Host smart-b50b9fd7-eaf9-49f0-8850-3c3d1f673725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952093835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1952093835
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2885237494
Short name T31
Test name
Test status
Simulation time 8266468444 ps
CPU time 12.55 seconds
Started Aug 09 04:28:09 PM PDT 24
Finished Aug 09 04:28:22 PM PDT 24
Peak memory 198072 kb
Host smart-467cc8cc-c8ce-4d71-baa8-50bff35afa6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885237494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2885237494
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2706348174
Short name T109
Test name
Test status
Simulation time 420818753 ps
CPU time 0.83 seconds
Started Aug 09 04:23:43 PM PDT 24
Finished Aug 09 04:23:44 PM PDT 24
Peak memory 196724 kb
Host smart-23cef971-b21d-430b-a81d-c5a150534157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706348174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2706348174
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3753092924
Short name T105
Test name
Test status
Simulation time 599027256 ps
CPU time 0.87 seconds
Started Aug 09 04:23:05 PM PDT 24
Finished Aug 09 04:23:06 PM PDT 24
Peak memory 195484 kb
Host smart-84c73f80-f23d-49ce-b7cb-af612f3ceb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753092924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3753092924
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.179658931
Short name T122
Test name
Test status
Simulation time 616898098 ps
CPU time 0.64 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:25:56 PM PDT 24
Peak memory 196716 kb
Host smart-254f8fae-bcfb-48b9-850c-48a400b7e471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179658931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.179658931
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3041626898
Short name T9
Test name
Test status
Simulation time 493993043 ps
CPU time 1.27 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:22 PM PDT 24
Peak memory 196668 kb
Host smart-17619b47-90a3-48f7-b810-e19d1c80ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041626898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3041626898
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2384078497
Short name T44
Test name
Test status
Simulation time 524948146 ps
CPU time 1.34 seconds
Started Aug 09 04:25:18 PM PDT 24
Finished Aug 09 04:25:19 PM PDT 24
Peak memory 196664 kb
Host smart-44f86256-64a1-4f5b-84d4-c375dad965cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384078497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2384078497
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3344728511
Short name T27
Test name
Test status
Simulation time 464171490 ps
CPU time 0.88 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 195456 kb
Host smart-c46c1921-5f05-4f1d-b497-e5486f76f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344728511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3344728511
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1272696626
Short name T70
Test name
Test status
Simulation time 2456076912 ps
CPU time 15.33 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:26:19 PM PDT 24
Peak memory 198340 kb
Host smart-3d815a87-c910-4b39-834a-5a6b206752f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272696626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1272696626
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2716200820
Short name T14
Test name
Test status
Simulation time 78118598352 ps
CPU time 309.21 seconds
Started Aug 09 04:25:38 PM PDT 24
Finished Aug 09 04:30:48 PM PDT 24
Peak memory 208684 kb
Host smart-953bd85d-ce07-4a96-a12a-175152a6d5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716200820 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2716200820
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.274144164
Short name T173
Test name
Test status
Simulation time 200532929849 ps
CPU time 274.22 seconds
Started Aug 09 04:26:15 PM PDT 24
Finished Aug 09 04:30:50 PM PDT 24
Peak memory 191668 kb
Host smart-fe4815b5-53ac-4aa3-9ed4-50d2eab00cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274144164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.274144164
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1674112546
Short name T169
Test name
Test status
Simulation time 174560042349 ps
CPU time 111.73 seconds
Started Aug 09 04:25:26 PM PDT 24
Finished Aug 09 04:27:18 PM PDT 24
Peak memory 197256 kb
Host smart-9f9033eb-0129-49bb-822e-5263acd349f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674112546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1674112546
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3766251982
Short name T180
Test name
Test status
Simulation time 580755755 ps
CPU time 0.74 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:25:56 PM PDT 24
Peak memory 196760 kb
Host smart-a947e329-3578-4f0b-8083-124110f4fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766251982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3766251982
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2657122812
Short name T11
Test name
Test status
Simulation time 239755081406 ps
CPU time 181.68 seconds
Started Aug 09 04:25:08 PM PDT 24
Finished Aug 09 04:28:10 PM PDT 24
Peak memory 183620 kb
Host smart-b2323d43-9fe2-4dc3-af18-420b07dd1544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657122812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2657122812
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1362615313
Short name T175
Test name
Test status
Simulation time 513198159 ps
CPU time 0.73 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:26:19 PM PDT 24
Peak memory 194984 kb
Host smart-86899dfd-bb27-44c2-bf36-0790ddd75954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362615313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1362615313
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1943133634
Short name T170
Test name
Test status
Simulation time 352413413 ps
CPU time 0.87 seconds
Started Aug 09 04:25:09 PM PDT 24
Finished Aug 09 04:25:10 PM PDT 24
Peak memory 195700 kb
Host smart-0031bcaf-ab25-455b-8f2b-32a72cff822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943133634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1943133634
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1705237361
Short name T72
Test name
Test status
Simulation time 24773957020 ps
CPU time 154.04 seconds
Started Aug 09 04:23:57 PM PDT 24
Finished Aug 09 04:26:31 PM PDT 24
Peak memory 214896 kb
Host smart-be349ac6-77ce-4f4e-addb-bb63ce0b9a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705237361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1705237361
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2632591459
Short name T148
Test name
Test status
Simulation time 413552263 ps
CPU time 0.96 seconds
Started Aug 09 04:24:41 PM PDT 24
Finished Aug 09 04:24:42 PM PDT 24
Peak memory 196736 kb
Host smart-701e50eb-f0d5-4f6c-8993-ac7caa4d9934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632591459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2632591459
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2934488960
Short name T176
Test name
Test status
Simulation time 571932948 ps
CPU time 0.8 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:16 PM PDT 24
Peak memory 196136 kb
Host smart-7181aa45-2634-4fae-abb6-f8199f3b7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934488960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2934488960
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1919283999
Short name T155
Test name
Test status
Simulation time 564286140 ps
CPU time 1.29 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:15 PM PDT 24
Peak memory 196368 kb
Host smart-296b50b4-5c5e-43e1-bec2-6375d7423b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919283999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1919283999
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2024072760
Short name T154
Test name
Test status
Simulation time 462142063 ps
CPU time 1.26 seconds
Started Aug 09 04:24:44 PM PDT 24
Finished Aug 09 04:24:45 PM PDT 24
Peak memory 197180 kb
Host smart-8b403cd2-7b31-4715-8857-e189b9b734dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024072760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2024072760
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.959723493
Short name T178
Test name
Test status
Simulation time 411175726 ps
CPU time 0.93 seconds
Started Aug 09 04:24:53 PM PDT 24
Finished Aug 09 04:24:54 PM PDT 24
Peak memory 196732 kb
Host smart-aa968bfc-ba23-4854-9748-05bebe611538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959723493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.959723493
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2067089240
Short name T161
Test name
Test status
Simulation time 536595852 ps
CPU time 0.72 seconds
Started Aug 09 04:25:06 PM PDT 24
Finished Aug 09 04:25:07 PM PDT 24
Peak memory 196780 kb
Host smart-7b70e0b9-c1c2-4aa7-aded-3e7ce0fad72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067089240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2067089240
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.677844160
Short name T80
Test name
Test status
Simulation time 571624283 ps
CPU time 0.99 seconds
Started Aug 09 04:26:29 PM PDT 24
Finished Aug 09 04:26:30 PM PDT 24
Peak memory 196616 kb
Host smart-38cfcdcb-9bf7-4bca-a2a9-d65e0fcd05c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677844160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.677844160
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2179510714
Short name T167
Test name
Test status
Simulation time 464225250 ps
CPU time 0.67 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:26:20 PM PDT 24
Peak memory 196668 kb
Host smart-6aebaf92-56db-44f2-a008-6dc7ca22f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179510714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2179510714
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3115548156
Short name T152
Test name
Test status
Simulation time 490670438 ps
CPU time 0.72 seconds
Started Aug 09 04:26:37 PM PDT 24
Finished Aug 09 04:26:38 PM PDT 24
Peak memory 196604 kb
Host smart-b5c6a6e1-155f-45a5-a554-bad9bf21f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115548156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3115548156
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.769961977
Short name T174
Test name
Test status
Simulation time 282976004572 ps
CPU time 384.33 seconds
Started Aug 09 04:25:05 PM PDT 24
Finished Aug 09 04:31:30 PM PDT 24
Peak memory 191792 kb
Host smart-d736a33c-7451-4844-8fe5-88fb220808fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769961977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.769961977
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3711280057
Short name T100
Test name
Test status
Simulation time 502402638 ps
CPU time 0.8 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 195156 kb
Host smart-63a1c329-9118-4619-b80e-6585d196555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711280057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3711280057
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3701585909
Short name T156
Test name
Test status
Simulation time 560094663 ps
CPU time 0.71 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 196344 kb
Host smart-917cd105-81f6-4db8-9e2f-8e353fbe39c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701585909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3701585909
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1504966338
Short name T160
Test name
Test status
Simulation time 412693276 ps
CPU time 1.12 seconds
Started Aug 09 04:24:28 PM PDT 24
Finished Aug 09 04:24:29 PM PDT 24
Peak memory 196832 kb
Host smart-a535e7d6-1ef1-41de-9468-314061cf9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504966338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1504966338
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.751471798
Short name T177
Test name
Test status
Simulation time 602615503 ps
CPU time 0.68 seconds
Started Aug 09 04:25:03 PM PDT 24
Finished Aug 09 04:25:04 PM PDT 24
Peak memory 196784 kb
Host smart-c6a1ec2a-d189-44f2-8c97-a46b01cd6bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751471798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.751471798
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1055058893
Short name T405
Test name
Test status
Simulation time 678292660 ps
CPU time 1.68 seconds
Started Aug 09 04:26:10 PM PDT 24
Finished Aug 09 04:26:12 PM PDT 24
Peak memory 190872 kb
Host smart-61e6fc31-9b1b-4579-99fe-cf07ce7a6666
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055058893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1055058893
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.996229208
Short name T387
Test name
Test status
Simulation time 6997810845 ps
CPU time 10.09 seconds
Started Aug 09 04:22:32 PM PDT 24
Finished Aug 09 04:22:42 PM PDT 24
Peak memory 191460 kb
Host smart-b01f2097-4ec1-43d5-bdf8-da2a4ea81a19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996229208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.996229208
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.865819652
Short name T310
Test name
Test status
Simulation time 963665239 ps
CPU time 0.78 seconds
Started Aug 09 04:24:12 PM PDT 24
Finished Aug 09 04:24:13 PM PDT 24
Peak memory 192844 kb
Host smart-fa681c98-6754-469c-9848-a7ac894e6c39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865819652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.865819652
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1526066101
Short name T306
Test name
Test status
Simulation time 501064985 ps
CPU time 0.95 seconds
Started Aug 09 04:25:12 PM PDT 24
Finished Aug 09 04:25:13 PM PDT 24
Peak memory 195828 kb
Host smart-64cc43db-5a3a-4295-9969-1ac435fa2478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526066101 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1526066101
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2378720275
Short name T374
Test name
Test status
Simulation time 452208624 ps
CPU time 0.58 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:25:12 PM PDT 24
Peak memory 192440 kb
Host smart-26453a33-669c-4489-9b07-6e1ab477443f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378720275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2378720275
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2451558088
Short name T276
Test name
Test status
Simulation time 473873442 ps
CPU time 1.18 seconds
Started Aug 09 04:22:24 PM PDT 24
Finished Aug 09 04:22:25 PM PDT 24
Peak memory 183676 kb
Host smart-88d0f031-ee88-47fb-9ddc-ec2db6fd0fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451558088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2451558088
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.294303212
Short name T299
Test name
Test status
Simulation time 409477991 ps
CPU time 0.67 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:26 PM PDT 24
Peak memory 182004 kb
Host smart-f7b86f7b-d32c-43b8-bad9-7c726e42d763
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294303212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.294303212
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1694626832
Short name T296
Test name
Test status
Simulation time 465126881 ps
CPU time 1.16 seconds
Started Aug 09 04:21:04 PM PDT 24
Finished Aug 09 04:21:05 PM PDT 24
Peak memory 183372 kb
Host smart-49368a92-2735-4a4b-a5cf-aeb5579ad580
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694626832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1694626832
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.835997272
Short name T364
Test name
Test status
Simulation time 2872951534 ps
CPU time 4.1 seconds
Started Aug 09 04:20:56 PM PDT 24
Finished Aug 09 04:21:00 PM PDT 24
Peak memory 193776 kb
Host smart-26e9d487-fd13-4ae1-a0a9-7e6448617504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835997272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.835997272
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4195248550
Short name T379
Test name
Test status
Simulation time 1406237309 ps
CPU time 2.66 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:28 PM PDT 24
Peak memory 196808 kb
Host smart-ef1fbcf0-0cb0-4c95-a68c-d76c507d42d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195248550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4195248550
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.611709286
Short name T182
Test name
Test status
Simulation time 8185651641 ps
CPU time 4.61 seconds
Started Aug 09 04:25:44 PM PDT 24
Finished Aug 09 04:25:48 PM PDT 24
Peak memory 198128 kb
Host smart-188c777f-0da4-4f2d-bbfc-8ac5039419ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611709286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.611709286
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2026164624
Short name T56
Test name
Test status
Simulation time 560931290 ps
CPU time 0.81 seconds
Started Aug 09 04:22:40 PM PDT 24
Finished Aug 09 04:22:40 PM PDT 24
Peak memory 192992 kb
Host smart-9520b32d-ddb5-45c1-8466-e37d012067bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026164624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2026164624
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3174762964
Short name T33
Test name
Test status
Simulation time 1172452651 ps
CPU time 2.49 seconds
Started Aug 09 04:23:15 PM PDT 24
Finished Aug 09 04:23:17 PM PDT 24
Peak memory 193468 kb
Host smart-2866eb9f-2031-4775-bcc0-5881fb727ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174762964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3174762964
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4006858773
Short name T350
Test name
Test status
Simulation time 575014921 ps
CPU time 0.91 seconds
Started Aug 09 04:22:33 PM PDT 24
Finished Aug 09 04:22:34 PM PDT 24
Peak memory 197644 kb
Host smart-3bbc3873-6836-4531-ad6a-423ebdbdaa14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006858773 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4006858773
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.825873636
Short name T344
Test name
Test status
Simulation time 513896309 ps
CPU time 0.87 seconds
Started Aug 09 04:22:46 PM PDT 24
Finished Aug 09 04:22:47 PM PDT 24
Peak memory 192872 kb
Host smart-04fb220a-cf44-4034-9cb1-9c88e697d1a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825873636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.825873636
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1903645707
Short name T363
Test name
Test status
Simulation time 510657794 ps
CPU time 1.27 seconds
Started Aug 09 04:26:21 PM PDT 24
Finished Aug 09 04:26:23 PM PDT 24
Peak memory 183600 kb
Host smart-7c24360a-6e0e-465d-ab26-48159c067978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903645707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1903645707
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3488934169
Short name T359
Test name
Test status
Simulation time 318557157 ps
CPU time 0.61 seconds
Started Aug 09 04:26:21 PM PDT 24
Finished Aug 09 04:26:22 PM PDT 24
Peak memory 183396 kb
Host smart-228b29d0-8329-4e72-820b-d0694c4443a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488934169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3488934169
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4098098941
Short name T383
Test name
Test status
Simulation time 515132412 ps
CPU time 0.62 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:25:12 PM PDT 24
Peak memory 183164 kb
Host smart-9ed1027b-7483-4790-9858-811a800c1f0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098098941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4098098941
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3489180018
Short name T347
Test name
Test status
Simulation time 579364033 ps
CPU time 2.56 seconds
Started Aug 09 04:26:21 PM PDT 24
Finished Aug 09 04:26:24 PM PDT 24
Peak memory 198448 kb
Host smart-9726f2e6-ce14-4065-b6ba-a6ad8b9be931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489180018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3489180018
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1788940605
Short name T365
Test name
Test status
Simulation time 447389631 ps
CPU time 1.1 seconds
Started Aug 09 04:27:50 PM PDT 24
Finished Aug 09 04:27:52 PM PDT 24
Peak memory 198180 kb
Host smart-052fd2cb-24e9-40cf-b621-238a676d5790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788940605 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1788940605
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.8681586
Short name T416
Test name
Test status
Simulation time 464526683 ps
CPU time 0.72 seconds
Started Aug 09 04:28:08 PM PDT 24
Finished Aug 09 04:28:09 PM PDT 24
Peak memory 193140 kb
Host smart-d8385bf2-23ae-41c1-baf1-948f8317eaad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8681586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.8681586
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1042924993
Short name T389
Test name
Test status
Simulation time 521559254 ps
CPU time 0.71 seconds
Started Aug 09 04:27:56 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 183560 kb
Host smart-c880f346-e359-4e53-b496-01ad20b277c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042924993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1042924993
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3585698823
Short name T392
Test name
Test status
Simulation time 2232905367 ps
CPU time 3.97 seconds
Started Aug 09 04:27:53 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 191972 kb
Host smart-f93f3c34-472e-465c-8abc-09ac488d9e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585698823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3585698823
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2691453436
Short name T358
Test name
Test status
Simulation time 474237239 ps
CPU time 1.59 seconds
Started Aug 09 04:27:59 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 198416 kb
Host smart-fdab513e-afca-4b9b-9848-c467090eea25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691453436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2691453436
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1332120685
Short name T391
Test name
Test status
Simulation time 4263869104 ps
CPU time 5.9 seconds
Started Aug 09 04:27:51 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 197820 kb
Host smart-b9dd0aa1-a697-45e4-bb13-b0e9d8b2bada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332120685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1332120685
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4044229317
Short name T403
Test name
Test status
Simulation time 562602008 ps
CPU time 1.51 seconds
Started Aug 09 04:28:05 PM PDT 24
Finished Aug 09 04:28:07 PM PDT 24
Peak memory 196292 kb
Host smart-64850e49-41ad-4b6d-a299-5d861d8d2fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044229317 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4044229317
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4110024985
Short name T28
Test name
Test status
Simulation time 545810197 ps
CPU time 0.8 seconds
Started Aug 09 04:27:50 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 193368 kb
Host smart-c07a4fe1-860f-4eac-a807-73b80b590a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110024985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4110024985
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2144607135
Short name T321
Test name
Test status
Simulation time 525097542 ps
CPU time 0.7 seconds
Started Aug 09 04:28:12 PM PDT 24
Finished Aug 09 04:28:12 PM PDT 24
Peak memory 192824 kb
Host smart-5b873536-fe94-4582-bd1a-fa595def5c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144607135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2144607135
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4224934045
Short name T410
Test name
Test status
Simulation time 1562914350 ps
CPU time 1.63 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 193624 kb
Host smart-7a6d1401-fe85-473f-88cf-3702f764a631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224934045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4224934045
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.764861843
Short name T284
Test name
Test status
Simulation time 668055585 ps
CPU time 2.12 seconds
Started Aug 09 04:28:09 PM PDT 24
Finished Aug 09 04:28:12 PM PDT 24
Peak memory 198456 kb
Host smart-468e7fad-474b-4f02-954c-a2f771d73a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764861843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.764861843
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.257228051
Short name T305
Test name
Test status
Simulation time 4929226208 ps
CPU time 8.16 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:09 PM PDT 24
Peak memory 198356 kb
Host smart-1d4284e6-a9f3-4784-a86b-434f2ad6531e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257228051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.257228051
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4187024798
Short name T398
Test name
Test status
Simulation time 540483583 ps
CPU time 1.31 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 195728 kb
Host smart-22cf77bd-831a-459e-b941-a956671dbe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187024798 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4187024798
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3740086265
Short name T58
Test name
Test status
Simulation time 336841886 ps
CPU time 1.11 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 193844 kb
Host smart-532db78e-5c01-4c0c-9377-4c341745de0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740086265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3740086265
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1665374310
Short name T352
Test name
Test status
Simulation time 396523315 ps
CPU time 0.8 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 183620 kb
Host smart-cfc69038-cbfa-4523-89d7-0f4db3d22023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665374310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1665374310
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2768842513
Short name T370
Test name
Test status
Simulation time 2520383418 ps
CPU time 4.01 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:05 PM PDT 24
Peak memory 194252 kb
Host smart-d7d00c8c-312c-4ee8-9dce-374230a43395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768842513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2768842513
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.937628143
Short name T314
Test name
Test status
Simulation time 425067235 ps
CPU time 1.84 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 198432 kb
Host smart-b2008e16-c035-49fd-b8e4-1ca7adf3bff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937628143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.937628143
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2609292319
Short name T415
Test name
Test status
Simulation time 4495601461 ps
CPU time 1.48 seconds
Started Aug 09 04:27:58 PM PDT 24
Finished Aug 09 04:28:00 PM PDT 24
Peak memory 196504 kb
Host smart-b04d48b6-0512-489a-8fe2-668e492b4d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609292319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2609292319
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.800934449
Short name T331
Test name
Test status
Simulation time 551398750 ps
CPU time 1.05 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 195988 kb
Host smart-97ed8270-84f2-43e8-9139-814fee4eaf69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800934449 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.800934449
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4099446599
Short name T373
Test name
Test status
Simulation time 306080601 ps
CPU time 1.04 seconds
Started Aug 09 04:28:16 PM PDT 24
Finished Aug 09 04:28:17 PM PDT 24
Peak memory 192984 kb
Host smart-005bfa8e-81c7-4f28-af12-11a9c9283516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099446599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4099446599
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1323772365
Short name T384
Test name
Test status
Simulation time 330817117 ps
CPU time 1.03 seconds
Started Aug 09 04:27:56 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 183636 kb
Host smart-44790ccc-b468-4ec8-805e-07311f307a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323772365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1323772365
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1134443552
Short name T64
Test name
Test status
Simulation time 3051781281 ps
CPU time 4.69 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:06 PM PDT 24
Peak memory 195372 kb
Host smart-7edaed42-5233-4890-958d-13fbbbe69be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134443552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1134443552
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3004442929
Short name T298
Test name
Test status
Simulation time 614310453 ps
CPU time 1.58 seconds
Started Aug 09 04:28:16 PM PDT 24
Finished Aug 09 04:28:18 PM PDT 24
Peak memory 198476 kb
Host smart-13be0304-d5be-457a-9f17-aacd0b86be58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004442929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3004442929
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1063546504
Short name T399
Test name
Test status
Simulation time 8136577284 ps
CPU time 4.14 seconds
Started Aug 09 04:27:50 PM PDT 24
Finished Aug 09 04:27:55 PM PDT 24
Peak memory 197996 kb
Host smart-2dcfdc37-799f-4477-bb3b-74b62a95cc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063546504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1063546504
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3822169788
Short name T312
Test name
Test status
Simulation time 545339411 ps
CPU time 1.28 seconds
Started Aug 09 04:28:03 PM PDT 24
Finished Aug 09 04:28:04 PM PDT 24
Peak memory 195696 kb
Host smart-b7e79f15-2890-41a9-b756-643ab68b5f7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822169788 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3822169788
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.661415048
Short name T408
Test name
Test status
Simulation time 406415030 ps
CPU time 1.18 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:07 PM PDT 24
Peak memory 193112 kb
Host smart-6adc9f39-81f8-4e91-9157-4a1eee419e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661415048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.661415048
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2535904612
Short name T297
Test name
Test status
Simulation time 379758024 ps
CPU time 1.04 seconds
Started Aug 09 04:28:07 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 192804 kb
Host smart-6a809aa0-a06b-4f7d-b7dc-fb3b37a3101b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535904612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2535904612
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2819648683
Short name T59
Test name
Test status
Simulation time 1947289864 ps
CPU time 4.32 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:15 PM PDT 24
Peak memory 193872 kb
Host smart-2cf2df66-154c-43a7-aa52-1df194f1c621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819648683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2819648683
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2276231367
Short name T279
Test name
Test status
Simulation time 884398173 ps
CPU time 2.37 seconds
Started Aug 09 04:27:50 PM PDT 24
Finished Aug 09 04:27:58 PM PDT 24
Peak memory 198408 kb
Host smart-04d14de9-b52d-4b59-be91-f1cd6976c59b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276231367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2276231367
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.536650531
Short name T396
Test name
Test status
Simulation time 3902849793 ps
CPU time 2.27 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 197720 kb
Host smart-fcbe397c-e2df-4c07-b3e3-923480cf0723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536650531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.536650531
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4174898587
Short name T381
Test name
Test status
Simulation time 372186286 ps
CPU time 0.92 seconds
Started Aug 09 04:28:07 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 196544 kb
Host smart-3313f0a1-bc4b-4bdb-87ad-28232b346049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174898587 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4174898587
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.193140917
Short name T414
Test name
Test status
Simulation time 522194156 ps
CPU time 1.19 seconds
Started Aug 09 04:28:08 PM PDT 24
Finished Aug 09 04:28:10 PM PDT 24
Peak memory 191828 kb
Host smart-5264285f-ad68-493e-a66c-83458fa0742b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193140917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.193140917
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3460802379
Short name T368
Test name
Test status
Simulation time 481246675 ps
CPU time 0.73 seconds
Started Aug 09 04:27:58 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 183572 kb
Host smart-90b345f2-80e5-4ac8-bde8-9d4ebcf60482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460802379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3460802379
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2606915661
Short name T60
Test name
Test status
Simulation time 1024873442 ps
CPU time 1.34 seconds
Started Aug 09 04:28:02 PM PDT 24
Finished Aug 09 04:28:03 PM PDT 24
Peak memory 193876 kb
Host smart-875d08f9-422a-43a3-ab80-6bfe5056362a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606915661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2606915661
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1276476617
Short name T412
Test name
Test status
Simulation time 534388722 ps
CPU time 2.21 seconds
Started Aug 09 04:27:54 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 198832 kb
Host smart-9444acc2-b312-4395-a279-0b8effc689ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276476617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1276476617
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2371370650
Short name T385
Test name
Test status
Simulation time 473981416 ps
CPU time 1.07 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:58 PM PDT 24
Peak memory 195868 kb
Host smart-7e7b36e3-b2ca-40c5-8a59-9e7657f4dbcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371370650 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2371370650
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3075808913
Short name T353
Test name
Test status
Simulation time 310838171 ps
CPU time 0.66 seconds
Started Aug 09 04:28:05 PM PDT 24
Finished Aug 09 04:28:06 PM PDT 24
Peak memory 191824 kb
Host smart-dfda9b10-25bf-4222-9dff-1989e12c187d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075808913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3075808913
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1215172870
Short name T285
Test name
Test status
Simulation time 352720403 ps
CPU time 0.98 seconds
Started Aug 09 04:28:07 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 183608 kb
Host smart-263ca85a-c40b-4091-bcc2-690a046492d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215172870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1215172870
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.29174885
Short name T335
Test name
Test status
Simulation time 2442599066 ps
CPU time 3.56 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:04 PM PDT 24
Peak memory 193956 kb
Host smart-f68a0ae7-0253-4bb9-95d7-db7e383c0456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29174885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_
timer_same_csr_outstanding.29174885
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2979141006
Short name T411
Test name
Test status
Simulation time 357388019 ps
CPU time 1.45 seconds
Started Aug 09 04:27:53 PM PDT 24
Finished Aug 09 04:27:54 PM PDT 24
Peak memory 198340 kb
Host smart-5a5e35b2-b45f-404e-b036-c8db4bc24dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979141006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2979141006
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.758950204
Short name T184
Test name
Test status
Simulation time 8108515288 ps
CPU time 12.6 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:13 PM PDT 24
Peak memory 198276 kb
Host smart-e3eaa293-99db-4cfe-85f3-a6579115de2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758950204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.758950204
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3234765882
Short name T355
Test name
Test status
Simulation time 452044786 ps
CPU time 1.32 seconds
Started Aug 09 04:27:49 PM PDT 24
Finished Aug 09 04:27:50 PM PDT 24
Peak memory 196496 kb
Host smart-e177533a-0ab4-463c-969c-3aeba575bceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234765882 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3234765882
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.340194791
Short name T371
Test name
Test status
Simulation time 290224923 ps
CPU time 0.92 seconds
Started Aug 09 04:27:48 PM PDT 24
Finished Aug 09 04:27:49 PM PDT 24
Peak memory 192824 kb
Host smart-50e973e8-a59b-4f09-a7a1-97f06f3e89f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340194791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.340194791
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2141518298
Short name T294
Test name
Test status
Simulation time 445215664 ps
CPU time 0.66 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 183588 kb
Host smart-4728519b-e540-4f03-adda-3019d0f2dd8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141518298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2141518298
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.997156941
Short name T65
Test name
Test status
Simulation time 1658539686 ps
CPU time 1.87 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 193272 kb
Host smart-8b9c57d3-7f44-436e-a049-dc687c6b03af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997156941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.997156941
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2110258698
Short name T317
Test name
Test status
Simulation time 526846267 ps
CPU time 2.86 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:03 PM PDT 24
Peak memory 198452 kb
Host smart-10031b76-2a1e-4244-9006-b5cddfb130c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110258698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2110258698
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1251057676
Short name T413
Test name
Test status
Simulation time 7742989929 ps
CPU time 4.89 seconds
Started Aug 09 04:28:12 PM PDT 24
Finished Aug 09 04:28:17 PM PDT 24
Peak memory 198008 kb
Host smart-597ae010-544a-4d36-b071-18dc943f3785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251057676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1251057676
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.773515860
Short name T311
Test name
Test status
Simulation time 442616625 ps
CPU time 1.22 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:03 PM PDT 24
Peak memory 195888 kb
Host smart-1eb51181-2fc7-46da-b125-96472d37aecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773515860 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.773515860
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.163633516
Short name T409
Test name
Test status
Simulation time 381401286 ps
CPU time 0.83 seconds
Started Aug 09 04:28:07 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 193856 kb
Host smart-b5aad4d5-97c1-4830-91cc-4f326b492365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163633516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.163633516
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3499498287
Short name T277
Test name
Test status
Simulation time 500346020 ps
CPU time 0.71 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:11 PM PDT 24
Peak memory 192808 kb
Host smart-be421f55-46a9-4458-a1aa-f380015ebe86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499498287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3499498287
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1836722643
Short name T337
Test name
Test status
Simulation time 1127463564 ps
CPU time 0.9 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 193532 kb
Host smart-1fbb0fe4-f84c-4c3c-aad6-ec0cb3b40ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836722643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1836722643
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1487213146
Short name T308
Test name
Test status
Simulation time 414095667 ps
CPU time 2.09 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 198464 kb
Host smart-24553383-0c8a-4ef3-a74d-e6f80f787f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487213146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1487213146
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3150524558
Short name T181
Test name
Test status
Simulation time 8280093949 ps
CPU time 13.13 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:28:11 PM PDT 24
Peak memory 198220 kb
Host smart-2bf00b6f-b307-4dff-9dad-a5930cbde5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150524558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3150524558
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2595989339
Short name T401
Test name
Test status
Simulation time 514827745 ps
CPU time 1.35 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 195620 kb
Host smart-ec1ff7d2-45eb-47ad-abdd-f2be6b404066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595989339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2595989339
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.773803491
Short name T54
Test name
Test status
Simulation time 542542936 ps
CPU time 0.72 seconds
Started Aug 09 04:27:59 PM PDT 24
Finished Aug 09 04:28:00 PM PDT 24
Peak memory 191872 kb
Host smart-853fa23d-fbda-4b5a-a2db-7178a4c23b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773803491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.773803491
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3125520645
Short name T281
Test name
Test status
Simulation time 278993824 ps
CPU time 0.68 seconds
Started Aug 09 04:27:52 PM PDT 24
Finished Aug 09 04:27:53 PM PDT 24
Peak memory 192836 kb
Host smart-27ac6d34-4473-4639-bc32-f8773bc5dbf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125520645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3125520645
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1257430766
Short name T357
Test name
Test status
Simulation time 1586742887 ps
CPU time 4.37 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:14 PM PDT 24
Peak memory 192840 kb
Host smart-699429af-d345-4513-bfe4-4cc631ed2c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257430766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1257430766
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1718595952
Short name T361
Test name
Test status
Simulation time 1344554737 ps
CPU time 1.61 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 198440 kb
Host smart-9005af31-334f-4f2a-8800-4e253a5d44e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718595952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1718595952
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.445754702
Short name T348
Test name
Test status
Simulation time 8549028758 ps
CPU time 13.9 seconds
Started Aug 09 04:28:05 PM PDT 24
Finished Aug 09 04:28:19 PM PDT 24
Peak memory 197888 kb
Host smart-5960cb12-9051-4611-a387-5faf3f1ddf99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445754702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.445754702
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.789216160
Short name T369
Test name
Test status
Simulation time 625466116 ps
CPU time 1.52 seconds
Started Aug 09 04:22:19 PM PDT 24
Finished Aug 09 04:22:20 PM PDT 24
Peak memory 183824 kb
Host smart-76263270-21ce-45b9-9a5d-3367f83c90de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789216160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.789216160
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3556626640
Short name T52
Test name
Test status
Simulation time 3441564358 ps
CPU time 4.99 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:20:55 PM PDT 24
Peak memory 192020 kb
Host smart-7cb6c672-8ebf-4e99-9fe6-f9b5219d5ef1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556626640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3556626640
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3635030336
Short name T47
Test name
Test status
Simulation time 1192404847 ps
CPU time 1.44 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:25:34 PM PDT 24
Peak memory 182492 kb
Host smart-af66e57b-5d8f-49bb-87cd-682ec36085eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635030336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3635030336
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1007756956
Short name T320
Test name
Test status
Simulation time 481202428 ps
CPU time 1.33 seconds
Started Aug 09 04:24:18 PM PDT 24
Finished Aug 09 04:24:19 PM PDT 24
Peak memory 195392 kb
Host smart-c15aba2b-779f-4254-b924-5a7ab3bda15d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007756956 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1007756956
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1309733165
Short name T53
Test name
Test status
Simulation time 500072845 ps
CPU time 1.23 seconds
Started Aug 09 04:23:29 PM PDT 24
Finished Aug 09 04:23:30 PM PDT 24
Peak memory 192872 kb
Host smart-f5b4efae-cfa6-4d40-8fcc-97e81b9d180f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309733165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1309733165
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.510447898
Short name T329
Test name
Test status
Simulation time 471260042 ps
CPU time 0.58 seconds
Started Aug 09 04:21:19 PM PDT 24
Finished Aug 09 04:21:20 PM PDT 24
Peak memory 183620 kb
Host smart-9b00c7b4-e67a-4a35-96ec-aad33a89a2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510447898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.510447898
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3835670328
Short name T400
Test name
Test status
Simulation time 409541738 ps
CPU time 1.07 seconds
Started Aug 09 04:25:23 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 182436 kb
Host smart-43324b0d-69f7-4a2c-8199-13fca8e60101
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835670328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3835670328
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3774195224
Short name T345
Test name
Test status
Simulation time 433556282 ps
CPU time 0.68 seconds
Started Aug 09 04:25:18 PM PDT 24
Finished Aug 09 04:25:19 PM PDT 24
Peak memory 183440 kb
Host smart-7cc40244-b5ba-4a69-876e-8db310e47da8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774195224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3774195224
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1692542599
Short name T390
Test name
Test status
Simulation time 1529944252 ps
CPU time 2.62 seconds
Started Aug 09 04:22:23 PM PDT 24
Finished Aug 09 04:22:26 PM PDT 24
Peak memory 193720 kb
Host smart-a2a529d2-0dc7-4c85-9fa0-81c5cb33b92e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692542599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1692542599
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3693177036
Short name T417
Test name
Test status
Simulation time 517652032 ps
CPU time 2.05 seconds
Started Aug 09 04:21:44 PM PDT 24
Finished Aug 09 04:21:46 PM PDT 24
Peak memory 198480 kb
Host smart-efcd160b-37d8-43eb-8fab-68f29c3e59f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693177036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3693177036
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3326370740
Short name T362
Test name
Test status
Simulation time 7876957103 ps
CPU time 2.88 seconds
Started Aug 09 04:25:04 PM PDT 24
Finished Aug 09 04:25:08 PM PDT 24
Peak memory 197188 kb
Host smart-585b67d9-8bf1-4df6-98a6-c1fa9cd05056
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326370740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3326370740
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.289636447
Short name T382
Test name
Test status
Simulation time 516874501 ps
CPU time 0.79 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 183636 kb
Host smart-d68d3a0e-a415-488a-b12c-cc6bf05975a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289636447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.289636447
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.316992644
Short name T290
Test name
Test status
Simulation time 421701740 ps
CPU time 1.22 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 192856 kb
Host smart-0f36f147-e480-4565-9c71-bc0ad09531bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316992644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.316992644
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1980836112
Short name T332
Test name
Test status
Simulation time 501414022 ps
CPU time 1.27 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:11 PM PDT 24
Peak memory 183576 kb
Host smart-257227ed-d55e-4d20-833e-9cc6c92997ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980836112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1980836112
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1136966900
Short name T300
Test name
Test status
Simulation time 492764881 ps
CPU time 0.55 seconds
Started Aug 09 04:28:16 PM PDT 24
Finished Aug 09 04:28:16 PM PDT 24
Peak memory 183656 kb
Host smart-8ed33ea0-152f-490a-b44e-ad91d35c93f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136966900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1136966900
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1539570869
Short name T333
Test name
Test status
Simulation time 417456540 ps
CPU time 0.85 seconds
Started Aug 09 04:28:03 PM PDT 24
Finished Aug 09 04:28:04 PM PDT 24
Peak memory 192812 kb
Host smart-ef8ad3e4-f66b-451f-8529-681378e358ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539570869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1539570869
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1275992584
Short name T330
Test name
Test status
Simulation time 411992185 ps
CPU time 0.67 seconds
Started Aug 09 04:28:05 PM PDT 24
Finished Aug 09 04:28:06 PM PDT 24
Peak memory 192828 kb
Host smart-d1ab2151-b045-4aad-a437-b1868502d94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275992584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1275992584
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.546003688
Short name T343
Test name
Test status
Simulation time 339956122 ps
CPU time 1.06 seconds
Started Aug 09 04:27:56 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 183636 kb
Host smart-10039f6b-cfcf-42b1-870c-167bc6a70676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546003688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.546003688
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3033341893
Short name T388
Test name
Test status
Simulation time 291025728 ps
CPU time 0.9 seconds
Started Aug 09 04:28:20 PM PDT 24
Finished Aug 09 04:28:21 PM PDT 24
Peak memory 183620 kb
Host smart-a7bd9e74-b792-42e9-abef-5347ae658b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033341893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3033341893
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3352600235
Short name T339
Test name
Test status
Simulation time 324037180 ps
CPU time 0.65 seconds
Started Aug 09 04:28:04 PM PDT 24
Finished Aug 09 04:28:05 PM PDT 24
Peak memory 183576 kb
Host smart-9b41aa5f-0447-4c36-821d-b0803dea4795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352600235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3352600235
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3470102257
Short name T346
Test name
Test status
Simulation time 319311018 ps
CPU time 0.6 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 183604 kb
Host smart-a0674b21-0f24-4cf6-a829-168ecd9c47c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470102257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3470102257
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2169796199
Short name T48
Test name
Test status
Simulation time 661245816 ps
CPU time 1.26 seconds
Started Aug 09 04:20:42 PM PDT 24
Finished Aug 09 04:20:44 PM PDT 24
Peak memory 194776 kb
Host smart-77c2a4d2-7ee4-43b6-8be5-44177e8d2eca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169796199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2169796199
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2001345848
Short name T46
Test name
Test status
Simulation time 7119166777 ps
CPU time 2.6 seconds
Started Aug 09 04:23:42 PM PDT 24
Finished Aug 09 04:23:45 PM PDT 24
Peak memory 192156 kb
Host smart-2721fc48-3dfc-46cd-9549-f6fa34e3a3ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001345848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2001345848
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4195284590
Short name T394
Test name
Test status
Simulation time 1230177132 ps
CPU time 2.46 seconds
Started Aug 09 04:22:30 PM PDT 24
Finished Aug 09 04:22:33 PM PDT 24
Peak memory 184000 kb
Host smart-059ff117-9c0e-4313-96af-4d556dec8ae5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195284590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4195284590
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2695470990
Short name T334
Test name
Test status
Simulation time 590890323 ps
CPU time 1.16 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 197132 kb
Host smart-4d277dec-4d8a-4960-99cd-4368887a7ccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695470990 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2695470990
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2641808087
Short name T50
Test name
Test status
Simulation time 511352746 ps
CPU time 1.29 seconds
Started Aug 09 04:20:49 PM PDT 24
Finished Aug 09 04:20:50 PM PDT 24
Peak memory 192828 kb
Host smart-91be92b7-d089-42f7-9226-b89ecca7d3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641808087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2641808087
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1675387638
Short name T287
Test name
Test status
Simulation time 371640184 ps
CPU time 0.78 seconds
Started Aug 09 04:24:31 PM PDT 24
Finished Aug 09 04:24:32 PM PDT 24
Peak memory 183628 kb
Host smart-31699b1e-741c-4d39-9446-e1b08e8ce320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675387638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1675387638
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1286359664
Short name T327
Test name
Test status
Simulation time 516030018 ps
CPU time 1.23 seconds
Started Aug 09 04:25:27 PM PDT 24
Finished Aug 09 04:25:28 PM PDT 24
Peak memory 183544 kb
Host smart-3002b8d5-83e3-476a-b977-53808b9bf138
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286359664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1286359664
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4255847544
Short name T286
Test name
Test status
Simulation time 537810304 ps
CPU time 0.58 seconds
Started Aug 09 04:21:15 PM PDT 24
Finished Aug 09 04:21:15 PM PDT 24
Peak memory 183536 kb
Host smart-33edfe34-0bc6-4644-b318-cf6174cb82b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255847544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4255847544
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2539578791
Short name T61
Test name
Test status
Simulation time 1264872784 ps
CPU time 2.98 seconds
Started Aug 09 04:25:58 PM PDT 24
Finished Aug 09 04:26:01 PM PDT 24
Peak memory 182792 kb
Host smart-7d14278b-14c4-4eab-afa3-da8e4b81381d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539578791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2539578791
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3081751954
Short name T336
Test name
Test status
Simulation time 409145570 ps
CPU time 1.56 seconds
Started Aug 09 04:26:10 PM PDT 24
Finished Aug 09 04:26:12 PM PDT 24
Peak memory 197436 kb
Host smart-0e5655e2-7b5f-46bf-b2e5-34ca8763af18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081751954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3081751954
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1428367514
Short name T342
Test name
Test status
Simulation time 4645434728 ps
CPU time 2.48 seconds
Started Aug 09 04:24:16 PM PDT 24
Finished Aug 09 04:24:18 PM PDT 24
Peak memory 196740 kb
Host smart-8cc651a2-557f-449e-a1e8-77cca45c98bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428367514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1428367514
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1303732487
Short name T302
Test name
Test status
Simulation time 431364010 ps
CPU time 0.67 seconds
Started Aug 09 04:28:20 PM PDT 24
Finished Aug 09 04:28:21 PM PDT 24
Peak memory 183700 kb
Host smart-c9d0e2ed-5273-45c4-8213-20ec11643ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303732487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1303732487
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2185228980
Short name T322
Test name
Test status
Simulation time 445553198 ps
CPU time 1.06 seconds
Started Aug 09 04:28:38 PM PDT 24
Finished Aug 09 04:28:39 PM PDT 24
Peak memory 183620 kb
Host smart-dd540d68-128c-49d9-aa69-9be6518e7ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185228980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2185228980
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.318299268
Short name T356
Test name
Test status
Simulation time 493555486 ps
CPU time 1.1 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 192828 kb
Host smart-baad18ba-bb54-4fc6-87bb-1ec12e15dc0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318299268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.318299268
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3399738511
Short name T349
Test name
Test status
Simulation time 477034255 ps
CPU time 1.23 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:12 PM PDT 24
Peak memory 192876 kb
Host smart-c3764612-6fcf-4adb-af96-9d5a6c0a1362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399738511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3399738511
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.188874246
Short name T291
Test name
Test status
Simulation time 407073913 ps
CPU time 0.63 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:07 PM PDT 24
Peak memory 183604 kb
Host smart-542446c2-6e21-4f75-8fe3-de2409397c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188874246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.188874246
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3894078452
Short name T278
Test name
Test status
Simulation time 506775678 ps
CPU time 0.71 seconds
Started Aug 09 04:28:04 PM PDT 24
Finished Aug 09 04:28:06 PM PDT 24
Peak memory 183652 kb
Host smart-bd5b60df-924d-45b4-99ca-e13cc4da4f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894078452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3894078452
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3252490973
Short name T376
Test name
Test status
Simulation time 393031770 ps
CPU time 0.67 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 183624 kb
Host smart-34e80412-a8aa-4be5-9c7a-67b190513e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252490973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3252490973
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1369158791
Short name T397
Test name
Test status
Simulation time 427921706 ps
CPU time 0.71 seconds
Started Aug 09 04:28:28 PM PDT 24
Finished Aug 09 04:28:28 PM PDT 24
Peak memory 183588 kb
Host smart-47a1ffca-12fe-4e9d-83c9-6b9aeea3a8db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369158791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1369158791
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.405327538
Short name T380
Test name
Test status
Simulation time 466933949 ps
CPU time 0.69 seconds
Started Aug 09 04:28:05 PM PDT 24
Finished Aug 09 04:28:06 PM PDT 24
Peak memory 192760 kb
Host smart-4b96d99a-9214-4dbc-9d95-b859d860ec07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405327538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.405327538
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2678838303
Short name T282
Test name
Test status
Simulation time 513882244 ps
CPU time 0.71 seconds
Started Aug 09 04:28:12 PM PDT 24
Finished Aug 09 04:28:13 PM PDT 24
Peak memory 192844 kb
Host smart-adb51fe0-9327-41eb-8013-babeecbcb3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678838303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2678838303
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2294873195
Short name T34
Test name
Test status
Simulation time 414234230 ps
CPU time 0.88 seconds
Started Aug 09 04:27:54 PM PDT 24
Finished Aug 09 04:27:54 PM PDT 24
Peak memory 183648 kb
Host smart-aaff2860-085e-4d09-bbd5-941bf3e5b885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294873195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2294873195
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.661460267
Short name T49
Test name
Test status
Simulation time 11570542245 ps
CPU time 26.34 seconds
Started Aug 09 04:27:58 PM PDT 24
Finished Aug 09 04:28:25 PM PDT 24
Peak memory 183932 kb
Host smart-1ded14c0-0006-47d9-845a-af512daa6a20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661460267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.661460267
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1799766515
Short name T55
Test name
Test status
Simulation time 1348219292 ps
CPU time 1.15 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:25:13 PM PDT 24
Peak memory 182800 kb
Host smart-a766809e-419b-4d0f-8661-99d85278de9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799766515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1799766515
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4173098044
Short name T301
Test name
Test status
Simulation time 372210183 ps
CPU time 1.21 seconds
Started Aug 09 04:27:53 PM PDT 24
Finished Aug 09 04:27:54 PM PDT 24
Peak memory 196092 kb
Host smart-a3cfbb32-7ca1-43c7-bc78-993dabacd721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173098044 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4173098044
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1786930772
Short name T315
Test name
Test status
Simulation time 507668629 ps
CPU time 1.21 seconds
Started Aug 09 04:28:11 PM PDT 24
Finished Aug 09 04:28:12 PM PDT 24
Peak memory 192824 kb
Host smart-24f92254-ae2c-46c5-9b6c-6f6b2b4feca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786930772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1786930772
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4138143954
Short name T280
Test name
Test status
Simulation time 338759422 ps
CPU time 0.75 seconds
Started Aug 09 04:25:33 PM PDT 24
Finished Aug 09 04:25:34 PM PDT 24
Peak memory 192580 kb
Host smart-56627a07-32d5-441c-94fb-ede276ee5a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138143954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4138143954
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3931852043
Short name T367
Test name
Test status
Simulation time 479018863 ps
CPU time 1.25 seconds
Started Aug 09 04:23:33 PM PDT 24
Finished Aug 09 04:23:34 PM PDT 24
Peak memory 183536 kb
Host smart-4fd1eb4d-3fe4-43c4-8a34-0c144ec358dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931852043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3931852043
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2186423880
Short name T283
Test name
Test status
Simulation time 275296766 ps
CPU time 0.91 seconds
Started Aug 09 04:25:05 PM PDT 24
Finished Aug 09 04:25:06 PM PDT 24
Peak memory 181716 kb
Host smart-3f610921-000a-4dc2-bd65-c9e7e97c37d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186423880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2186423880
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4062763381
Short name T326
Test name
Test status
Simulation time 1779494779 ps
CPU time 2.36 seconds
Started Aug 09 04:28:23 PM PDT 24
Finished Aug 09 04:28:25 PM PDT 24
Peak memory 193760 kb
Host smart-51a5b7d7-3239-472a-8771-139d0c5b4539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062763381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4062763381
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.721203685
Short name T393
Test name
Test status
Simulation time 780249923 ps
CPU time 2.01 seconds
Started Aug 09 04:25:05 PM PDT 24
Finished Aug 09 04:25:07 PM PDT 24
Peak memory 197900 kb
Host smart-9d33635e-d869-4251-a5ea-126614bd55e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721203685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.721203685
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.110404091
Short name T319
Test name
Test status
Simulation time 8420435353 ps
CPU time 12.57 seconds
Started Aug 09 04:26:43 PM PDT 24
Finished Aug 09 04:26:55 PM PDT 24
Peak memory 198140 kb
Host smart-dc55e81f-6ff3-440c-8247-66f6b960d023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110404091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.110404091
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2671815207
Short name T323
Test name
Test status
Simulation time 467948092 ps
CPU time 0.66 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 192872 kb
Host smart-37deb593-c491-4e38-aaa3-d5cb49df5877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671815207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2671815207
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2173870466
Short name T328
Test name
Test status
Simulation time 335774473 ps
CPU time 1.06 seconds
Started Aug 09 04:28:13 PM PDT 24
Finished Aug 09 04:28:14 PM PDT 24
Peak memory 183576 kb
Host smart-4712e468-b83b-40ce-b209-229e7dcaafbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173870466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2173870466
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2430417363
Short name T289
Test name
Test status
Simulation time 295224742 ps
CPU time 1.05 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 183620 kb
Host smart-cc593e03-0382-463d-98a9-884a1f68d010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430417363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2430417363
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3292297451
Short name T309
Test name
Test status
Simulation time 450334678 ps
CPU time 0.83 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 183608 kb
Host smart-1e151049-da06-4126-86f9-76b3769f632b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292297451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3292297451
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3197572374
Short name T295
Test name
Test status
Simulation time 381105261 ps
CPU time 1.03 seconds
Started Aug 09 04:28:22 PM PDT 24
Finished Aug 09 04:28:23 PM PDT 24
Peak memory 183636 kb
Host smart-51a2d48a-941d-42ad-bcdd-86838f5e03a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197572374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3197572374
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1713300602
Short name T304
Test name
Test status
Simulation time 527797817 ps
CPU time 0.73 seconds
Started Aug 09 04:28:15 PM PDT 24
Finished Aug 09 04:28:16 PM PDT 24
Peak memory 183668 kb
Host smart-8949b51c-12ee-4538-af14-baadbb6a4eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713300602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1713300602
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.726534584
Short name T288
Test name
Test status
Simulation time 461622176 ps
CPU time 1.2 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 183612 kb
Host smart-b9e2026b-3475-4be0-b9f1-0b4109eab853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726534584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.726534584
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3274927609
Short name T340
Test name
Test status
Simulation time 462177180 ps
CPU time 0.92 seconds
Started Aug 09 04:28:02 PM PDT 24
Finished Aug 09 04:28:03 PM PDT 24
Peak memory 192792 kb
Host smart-617c02b2-ce4d-40e5-80c1-9d3103a438e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274927609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3274927609
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1773248094
Short name T354
Test name
Test status
Simulation time 469975954 ps
CPU time 0.73 seconds
Started Aug 09 04:28:18 PM PDT 24
Finished Aug 09 04:28:19 PM PDT 24
Peak memory 183616 kb
Host smart-2c5be47b-01b8-4c8b-af8e-2d1bedda0b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773248094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1773248094
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2735982687
Short name T292
Test name
Test status
Simulation time 319788141 ps
CPU time 0.73 seconds
Started Aug 09 04:28:16 PM PDT 24
Finished Aug 09 04:28:17 PM PDT 24
Peak memory 192832 kb
Host smart-5a0165fd-5613-4e05-a7f4-4312911b1e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735982687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2735982687
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1107285074
Short name T377
Test name
Test status
Simulation time 469655165 ps
CPU time 1.11 seconds
Started Aug 09 04:27:49 PM PDT 24
Finished Aug 09 04:27:50 PM PDT 24
Peak memory 196088 kb
Host smart-723151eb-9c51-4749-9aa5-10a591760bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107285074 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1107285074
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3404916335
Short name T57
Test name
Test status
Simulation time 479880914 ps
CPU time 1.33 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 193272 kb
Host smart-04840027-32f5-4ef0-9669-f08b87eab7ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404916335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3404916335
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3920747818
Short name T360
Test name
Test status
Simulation time 400775803 ps
CPU time 0.66 seconds
Started Aug 09 04:27:48 PM PDT 24
Finished Aug 09 04:27:48 PM PDT 24
Peak memory 192848 kb
Host smart-641da10f-1dfa-45e7-9592-35bfcb0c8fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920747818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3920747818
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4069993390
Short name T313
Test name
Test status
Simulation time 2475037814 ps
CPU time 5.5 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:28:00 PM PDT 24
Peak memory 193912 kb
Host smart-6fa7c0dc-0626-4713-b655-b4ec89132193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069993390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4069993390
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3419617339
Short name T402
Test name
Test status
Simulation time 430260985 ps
CPU time 2.12 seconds
Started Aug 09 04:27:59 PM PDT 24
Finished Aug 09 04:28:01 PM PDT 24
Peak memory 198484 kb
Host smart-5918cefb-ce88-4e3f-bacd-ea3b8dd06b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419617339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3419617339
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4111574549
Short name T324
Test name
Test status
Simulation time 4284760623 ps
CPU time 2.53 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:08 PM PDT 24
Peak memory 197800 kb
Host smart-3c29ec72-35b3-4719-a607-80f7ae316bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111574549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.4111574549
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.406138697
Short name T185
Test name
Test status
Simulation time 532442665 ps
CPU time 1.5 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 196064 kb
Host smart-ddf8f7ff-b9fc-4ad1-baf5-379ae0860c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406138697 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.406138697
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1808640947
Short name T375
Test name
Test status
Simulation time 314196281 ps
CPU time 0.66 seconds
Started Aug 09 04:28:06 PM PDT 24
Finished Aug 09 04:28:07 PM PDT 24
Peak memory 191876 kb
Host smart-d144a1a3-32cc-45ac-99a4-9cccaf2b7635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808640947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1808640947
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4043522111
Short name T307
Test name
Test status
Simulation time 324531531 ps
CPU time 0.63 seconds
Started Aug 09 04:27:49 PM PDT 24
Finished Aug 09 04:27:49 PM PDT 24
Peak memory 183596 kb
Host smart-6e85203d-2a17-4d0f-942f-94f06b42dd2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043522111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4043522111
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3672245637
Short name T351
Test name
Test status
Simulation time 1202032740 ps
CPU time 0.96 seconds
Started Aug 09 04:27:49 PM PDT 24
Finished Aug 09 04:27:50 PM PDT 24
Peak memory 192808 kb
Host smart-b32109fb-98d7-47de-9d22-bf2bd11ea13f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672245637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3672245637
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.280106730
Short name T366
Test name
Test status
Simulation time 495160493 ps
CPU time 2.09 seconds
Started Aug 09 04:27:58 PM PDT 24
Finished Aug 09 04:28:00 PM PDT 24
Peak memory 198484 kb
Host smart-6ee1507f-575d-4eb5-b36f-383c115178be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280106730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.280106730
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3994285326
Short name T386
Test name
Test status
Simulation time 8204382572 ps
CPU time 2.3 seconds
Started Aug 09 04:28:23 PM PDT 24
Finished Aug 09 04:28:26 PM PDT 24
Peak memory 198196 kb
Host smart-250f972f-1ce1-4b51-9a2c-dbaa9d5bdc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994285326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3994285326
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2437442343
Short name T303
Test name
Test status
Simulation time 399314736 ps
CPU time 0.78 seconds
Started Aug 09 04:27:56 PM PDT 24
Finished Aug 09 04:27:57 PM PDT 24
Peak memory 196260 kb
Host smart-f5b1c7de-4212-44c7-b256-fe741337e6b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437442343 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2437442343
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1669899540
Short name T51
Test name
Test status
Simulation time 396243477 ps
CPU time 0.83 seconds
Started Aug 09 04:27:52 PM PDT 24
Finished Aug 09 04:27:53 PM PDT 24
Peak memory 193120 kb
Host smart-8d186ecb-4e69-47f0-bb9f-9957df607301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669899540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1669899540
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2070418724
Short name T316
Test name
Test status
Simulation time 366833277 ps
CPU time 1.03 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 183616 kb
Host smart-d81dc90c-f71e-480b-8439-500f301b8eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070418724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2070418724
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.614434407
Short name T404
Test name
Test status
Simulation time 2414233712 ps
CPU time 1.52 seconds
Started Aug 09 04:27:52 PM PDT 24
Finished Aug 09 04:27:54 PM PDT 24
Peak memory 195144 kb
Host smart-f78c9401-5023-490f-93ea-7d80c0fc8ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614434407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.614434407
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1734633511
Short name T407
Test name
Test status
Simulation time 362669801 ps
CPU time 2.67 seconds
Started Aug 09 04:28:10 PM PDT 24
Finished Aug 09 04:28:13 PM PDT 24
Peak memory 198444 kb
Host smart-7faa1cf5-5dc6-4e5b-a622-cc87641057e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734633511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1734633511
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.436733220
Short name T183
Test name
Test status
Simulation time 8133629932 ps
CPU time 12.01 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:12 PM PDT 24
Peak memory 198284 kb
Host smart-bc55aba3-0475-485d-ae45-2f4adb522348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436733220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.436733220
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2464371532
Short name T395
Test name
Test status
Simulation time 504043015 ps
CPU time 0.99 seconds
Started Aug 09 04:27:57 PM PDT 24
Finished Aug 09 04:27:58 PM PDT 24
Peak memory 195468 kb
Host smart-3859f8a6-fae0-406f-b0f9-d2c52f666c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464371532 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2464371532
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1009969151
Short name T63
Test name
Test status
Simulation time 376981642 ps
CPU time 0.74 seconds
Started Aug 09 04:27:49 PM PDT 24
Finished Aug 09 04:27:50 PM PDT 24
Peak memory 192784 kb
Host smart-3d538318-84f6-4183-a5d9-e3f42bff23c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009969151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1009969151
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.185288264
Short name T338
Test name
Test status
Simulation time 501111144 ps
CPU time 0.58 seconds
Started Aug 09 04:27:58 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 183564 kb
Host smart-87bd99c4-ffe0-451d-8581-56faec691e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185288264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.185288264
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1938913856
Short name T325
Test name
Test status
Simulation time 2540912094 ps
CPU time 1.52 seconds
Started Aug 09 04:27:54 PM PDT 24
Finished Aug 09 04:27:55 PM PDT 24
Peak memory 194828 kb
Host smart-6ab8a7ee-45e9-4b5d-849f-2441c7855baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938913856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1938913856
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2399237280
Short name T378
Test name
Test status
Simulation time 351636017 ps
CPU time 1.29 seconds
Started Aug 09 04:28:00 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 198204 kb
Host smart-90d5e618-a0dc-4368-899f-fb8757392431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399237280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2399237280
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2952623278
Short name T341
Test name
Test status
Simulation time 9305142472 ps
CPU time 2.54 seconds
Started Aug 09 04:27:56 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 198120 kb
Host smart-c567f6bd-0cec-4957-b5ea-784ea3b0a133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952623278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2952623278
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1025447339
Short name T406
Test name
Test status
Simulation time 484207356 ps
CPU time 1.33 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:02 PM PDT 24
Peak memory 196612 kb
Host smart-a96ead9e-72ca-4921-84c8-4c1dbd017065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025447339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1025447339
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2007986905
Short name T372
Test name
Test status
Simulation time 361597497 ps
CPU time 0.7 seconds
Started Aug 09 04:27:48 PM PDT 24
Finished Aug 09 04:27:59 PM PDT 24
Peak memory 192920 kb
Host smart-e2aee096-549a-4739-a608-089b3ee1e36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007986905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2007986905
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.11990432
Short name T293
Test name
Test status
Simulation time 425180529 ps
CPU time 0.56 seconds
Started Aug 09 04:27:55 PM PDT 24
Finished Aug 09 04:27:56 PM PDT 24
Peak memory 183648 kb
Host smart-7c04434e-5786-4ca6-837e-fa4fa95dc280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11990432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.11990432
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4168060389
Short name T62
Test name
Test status
Simulation time 1142162872 ps
CPU time 1 seconds
Started Aug 09 04:27:59 PM PDT 24
Finished Aug 09 04:28:00 PM PDT 24
Peak memory 192788 kb
Host smart-5a298517-e4e6-4eef-a9bc-ff88105b5d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168060389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4168060389
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.641139388
Short name T318
Test name
Test status
Simulation time 565055758 ps
CPU time 1.18 seconds
Started Aug 09 04:27:50 PM PDT 24
Finished Aug 09 04:27:52 PM PDT 24
Peak memory 198224 kb
Host smart-f600605f-880e-4456-a09c-1fd491988913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641139388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.641139388
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3767956178
Short name T32
Test name
Test status
Simulation time 4946944543 ps
CPU time 2.26 seconds
Started Aug 09 04:28:01 PM PDT 24
Finished Aug 09 04:28:04 PM PDT 24
Peak memory 197648 kb
Host smart-feab52cd-83bb-4970-a008-0f8a8902cb4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767956178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3767956178
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.573687234
Short name T208
Test name
Test status
Simulation time 11610073033 ps
CPU time 5.27 seconds
Started Aug 09 04:22:31 PM PDT 24
Finished Aug 09 04:22:36 PM PDT 24
Peak memory 192400 kb
Host smart-70bc62b2-6d68-4806-9838-6b6d164a0abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573687234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.573687234
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1269230080
Short name T233
Test name
Test status
Simulation time 370975824 ps
CPU time 0.76 seconds
Started Aug 09 04:21:34 PM PDT 24
Finished Aug 09 04:21:35 PM PDT 24
Peak memory 196732 kb
Host smart-3491e311-6d64-4f77-a0f7-c0f529584dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269230080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1269230080
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3049387111
Short name T216
Test name
Test status
Simulation time 39301873338 ps
CPU time 16.51 seconds
Started Aug 09 04:22:18 PM PDT 24
Finished Aug 09 04:22:35 PM PDT 24
Peak memory 191984 kb
Host smart-7b9280db-ad43-420f-ac76-f41b35439705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049387111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3049387111
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1845983117
Short name T19
Test name
Test status
Simulation time 4525147407 ps
CPU time 3.94 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:26:17 PM PDT 24
Peak memory 214488 kb
Host smart-62fed42d-f42e-4274-81a2-1273ca5c37d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845983117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1845983117
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2847594653
Short name T262
Test name
Test status
Simulation time 459127724 ps
CPU time 1.18 seconds
Started Aug 09 04:21:46 PM PDT 24
Finished Aug 09 04:21:48 PM PDT 24
Peak memory 191916 kb
Host smart-0ed92db7-a8a4-4e17-a41b-c9de4d6cddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847594653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2847594653
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.507676464
Short name T168
Test name
Test status
Simulation time 461788594 ps
CPU time 1.03 seconds
Started Aug 09 04:25:05 PM PDT 24
Finished Aug 09 04:25:06 PM PDT 24
Peak memory 195236 kb
Host smart-8e4beb7d-244c-4234-8a4b-51185bebdc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507676464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.507676464
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2692007391
Short name T210
Test name
Test status
Simulation time 5919547015 ps
CPU time 2.66 seconds
Started Aug 09 04:23:01 PM PDT 24
Finished Aug 09 04:23:04 PM PDT 24
Peak memory 191968 kb
Host smart-b999d07b-0066-48a1-b308-45de68ab1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692007391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2692007391
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1068650407
Short name T242
Test name
Test status
Simulation time 496022404 ps
CPU time 0.67 seconds
Started Aug 09 04:23:19 PM PDT 24
Finished Aug 09 04:23:20 PM PDT 24
Peak memory 191928 kb
Host smart-e4111df5-cdde-4aae-a2a5-bba756a0bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068650407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1068650407
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1147819993
Short name T172
Test name
Test status
Simulation time 688414992 ps
CPU time 0.68 seconds
Started Aug 09 04:22:57 PM PDT 24
Finished Aug 09 04:22:58 PM PDT 24
Peak memory 196680 kb
Host smart-e7ef3f7f-a500-4874-89c4-662c657592a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147819993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1147819993
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3370172112
Short name T252
Test name
Test status
Simulation time 27219351618 ps
CPU time 31.12 seconds
Started Aug 09 04:23:04 PM PDT 24
Finished Aug 09 04:23:35 PM PDT 24
Peak memory 191984 kb
Host smart-27b5552b-b9a4-4325-865c-633d5c2d3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370172112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3370172112
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3320628800
Short name T260
Test name
Test status
Simulation time 545498998 ps
CPU time 1.44 seconds
Started Aug 09 04:26:15 PM PDT 24
Finished Aug 09 04:26:18 PM PDT 24
Peak memory 190128 kb
Host smart-135f34fa-8208-4809-8854-38f9815c8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320628800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3320628800
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3173592286
Short name T191
Test name
Test status
Simulation time 9229623792 ps
CPU time 3.62 seconds
Started Aug 09 04:23:12 PM PDT 24
Finished Aug 09 04:23:15 PM PDT 24
Peak memory 192376 kb
Host smart-1331f465-11a2-44bf-bf3f-e5efeefbc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173592286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3173592286
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.996753970
Short name T257
Test name
Test status
Simulation time 380645802 ps
CPU time 1.05 seconds
Started Aug 09 04:24:54 PM PDT 24
Finished Aug 09 04:24:55 PM PDT 24
Peak memory 192052 kb
Host smart-023a9c0c-ef65-4a7a-86f5-09506cf11393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996753970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.996753970
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.354306753
Short name T2
Test name
Test status
Simulation time 36334283360 ps
CPU time 52.63 seconds
Started Aug 09 04:25:44 PM PDT 24
Finished Aug 09 04:26:37 PM PDT 24
Peak memory 196172 kb
Host smart-a8f580a1-007a-4dc0-aa5c-9230b13b6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354306753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.354306753
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.878709493
Short name T269
Test name
Test status
Simulation time 409872195 ps
CPU time 1.2 seconds
Started Aug 09 04:23:06 PM PDT 24
Finished Aug 09 04:23:07 PM PDT 24
Peak memory 191912 kb
Host smart-d9941b3f-c04e-456b-a2f0-718d210993be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878709493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.878709493
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3056123601
Short name T238
Test name
Test status
Simulation time 39766366637 ps
CPU time 29.51 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:25:41 PM PDT 24
Peak memory 191304 kb
Host smart-b12c7189-0801-4fb0-885c-747035fa3de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056123601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3056123601
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.930576896
Short name T266
Test name
Test status
Simulation time 566057712 ps
CPU time 1.33 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:26:14 PM PDT 24
Peak memory 191680 kb
Host smart-eaa5fcf5-c848-44f1-9206-02f5ccd2bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930576896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.930576896
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2931890597
Short name T261
Test name
Test status
Simulation time 33582572793 ps
CPU time 3.3 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:25:58 PM PDT 24
Peak memory 196932 kb
Host smart-aaa6e20d-1ac2-4df6-a310-d2ffeb75efd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931890597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2931890597
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1546939271
Short name T188
Test name
Test status
Simulation time 415979670 ps
CPU time 0.85 seconds
Started Aug 09 04:25:44 PM PDT 24
Finished Aug 09 04:25:45 PM PDT 24
Peak memory 191052 kb
Host smart-548db88e-0924-4ff7-8595-c2f10d7329d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546939271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1546939271
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4143909218
Short name T206
Test name
Test status
Simulation time 53312989402 ps
CPU time 80.11 seconds
Started Aug 09 04:23:17 PM PDT 24
Finished Aug 09 04:24:37 PM PDT 24
Peak memory 197000 kb
Host smart-4770a81e-ddb9-487c-8046-0997df933b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143909218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4143909218
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3565466216
Short name T4
Test name
Test status
Simulation time 420008488 ps
CPU time 0.63 seconds
Started Aug 09 04:25:45 PM PDT 24
Finished Aug 09 04:25:46 PM PDT 24
Peak memory 191892 kb
Host smart-4f293302-e0e7-4411-a10f-c2e600d6f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565466216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3565466216
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2372281827
Short name T254
Test name
Test status
Simulation time 20457041115 ps
CPU time 29.36 seconds
Started Aug 09 04:25:55 PM PDT 24
Finished Aug 09 04:26:25 PM PDT 24
Peak memory 196960 kb
Host smart-5db3f17a-f3a4-4847-ae9b-7563eccc817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372281827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2372281827
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.810216797
Short name T189
Test name
Test status
Simulation time 513180130 ps
CPU time 1.37 seconds
Started Aug 09 04:23:15 PM PDT 24
Finished Aug 09 04:23:16 PM PDT 24
Peak memory 196764 kb
Host smart-0ad01910-8f9b-4af2-8817-140929f1c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810216797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.810216797
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.801831402
Short name T218
Test name
Test status
Simulation time 23657223582 ps
CPU time 19.46 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:25:39 PM PDT 24
Peak memory 190472 kb
Host smart-8bfd47d1-bd66-4cee-b585-880bc5192c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801831402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.801831402
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2751144119
Short name T23
Test name
Test status
Simulation time 564670734 ps
CPU time 0.65 seconds
Started Aug 09 04:24:18 PM PDT 24
Finished Aug 09 04:24:19 PM PDT 24
Peak memory 192052 kb
Host smart-ab850f0a-bed2-4965-ab4b-7cc4682e1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751144119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2751144119
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3013973697
Short name T196
Test name
Test status
Simulation time 3330354145 ps
CPU time 1.74 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 190624 kb
Host smart-5f5b8a8b-24e4-4cbd-8788-a2c75b57aa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013973697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3013973697
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.315527651
Short name T20
Test name
Test status
Simulation time 377983548 ps
CPU time 0.73 seconds
Started Aug 09 04:25:08 PM PDT 24
Finished Aug 09 04:25:09 PM PDT 24
Peak memory 196232 kb
Host smart-b153679c-13ab-47f3-8c76-8096163cf173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315527651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.315527651
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2379564607
Short name T204
Test name
Test status
Simulation time 19918453227 ps
CPU time 16.34 seconds
Started Aug 09 04:26:34 PM PDT 24
Finished Aug 09 04:26:50 PM PDT 24
Peak memory 196976 kb
Host smart-b4feadb2-d328-4da2-b09d-f317d22308c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379564607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2379564607
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2380913489
Short name T17
Test name
Test status
Simulation time 8197478889 ps
CPU time 11.43 seconds
Started Aug 09 04:20:58 PM PDT 24
Finished Aug 09 04:21:10 PM PDT 24
Peak memory 216080 kb
Host smart-49b35a34-61bc-4a8b-964c-a5f5fa838c18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380913489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2380913489
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2653434797
Short name T203
Test name
Test status
Simulation time 465094556 ps
CPU time 0.75 seconds
Started Aug 09 04:25:29 PM PDT 24
Finished Aug 09 04:25:30 PM PDT 24
Peak memory 191136 kb
Host smart-e59fc919-e4ef-4ea2-91af-adaff1026075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653434797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2653434797
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.464407034
Short name T198
Test name
Test status
Simulation time 44522292513 ps
CPU time 14.77 seconds
Started Aug 09 04:25:26 PM PDT 24
Finished Aug 09 04:25:41 PM PDT 24
Peak memory 190276 kb
Host smart-f0e5bda6-a84e-4aa8-a581-9c8b4c016d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464407034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.464407034
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1276855927
Short name T199
Test name
Test status
Simulation time 606383501 ps
CPU time 1.43 seconds
Started Aug 09 04:25:22 PM PDT 24
Finished Aug 09 04:25:24 PM PDT 24
Peak memory 191684 kb
Host smart-a90c5545-4c76-4401-a948-b6b664f4053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276855927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1276855927
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.529860038
Short name T179
Test name
Test status
Simulation time 630618923 ps
CPU time 0.7 seconds
Started Aug 09 04:23:35 PM PDT 24
Finished Aug 09 04:23:36 PM PDT 24
Peak memory 196752 kb
Host smart-78bb5411-2df7-41d9-bfe4-055079059ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529860038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.529860038
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1484139842
Short name T5
Test name
Test status
Simulation time 10265977494 ps
CPU time 3.83 seconds
Started Aug 09 04:26:33 PM PDT 24
Finished Aug 09 04:26:37 PM PDT 24
Peak memory 191876 kb
Host smart-3101f37d-e3b8-4fe6-b74d-15be28e06d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484139842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1484139842
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.804237028
Short name T220
Test name
Test status
Simulation time 404316564 ps
CPU time 1.1 seconds
Started Aug 09 04:23:35 PM PDT 24
Finished Aug 09 04:23:37 PM PDT 24
Peak memory 196712 kb
Host smart-03c4191c-3d8d-4064-898f-9be988f6dac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804237028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.804237028
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2742308770
Short name T246
Test name
Test status
Simulation time 34194063232 ps
CPU time 26.13 seconds
Started Aug 09 04:25:37 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 190952 kb
Host smart-60ce6b70-9e81-4a5c-ba4a-b017373d75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742308770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2742308770
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2366019108
Short name T272
Test name
Test status
Simulation time 510386381 ps
CPU time 0.76 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 191920 kb
Host smart-0eb8f18b-32a9-4363-bc63-f5990fba9dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366019108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2366019108
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3891482771
Short name T165
Test name
Test status
Simulation time 355522961 ps
CPU time 0.85 seconds
Started Aug 09 04:23:39 PM PDT 24
Finished Aug 09 04:23:41 PM PDT 24
Peak memory 196848 kb
Host smart-567ff902-7c10-4a52-8d97-32d0b246f84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891482771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3891482771
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.864730175
Short name T267
Test name
Test status
Simulation time 16291957397 ps
CPU time 22.56 seconds
Started Aug 09 04:23:45 PM PDT 24
Finished Aug 09 04:24:08 PM PDT 24
Peak memory 191968 kb
Host smart-24626522-4069-403c-b0a9-52a489f70638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864730175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.864730175
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1775365862
Short name T274
Test name
Test status
Simulation time 590915142 ps
CPU time 1.5 seconds
Started Aug 09 04:23:40 PM PDT 24
Finished Aug 09 04:23:42 PM PDT 24
Peak memory 196756 kb
Host smart-b39e1b51-34e2-4cac-a3fb-5f64bfa323ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775365862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1775365862
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2613177242
Short name T222
Test name
Test status
Simulation time 17528923780 ps
CPU time 14.73 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:26:33 PM PDT 24
Peak memory 189940 kb
Host smart-c2390940-00f4-4bc6-ab13-593dbb7bd995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613177242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2613177242
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.319299421
Short name T226
Test name
Test status
Simulation time 427633899 ps
CPU time 0.76 seconds
Started Aug 09 04:26:33 PM PDT 24
Finished Aug 09 04:26:34 PM PDT 24
Peak memory 191224 kb
Host smart-bb2b837a-a0bf-4535-89dd-e5393f269e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319299421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.319299421
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.140461865
Short name T207
Test name
Test status
Simulation time 12825784827 ps
CPU time 16.86 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:26:36 PM PDT 24
Peak memory 191168 kb
Host smart-d4eebf76-3af7-45e8-99b4-e00a972b61c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140461865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.140461865
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4103951942
Short name T250
Test name
Test status
Simulation time 404709436 ps
CPU time 0.87 seconds
Started Aug 09 04:24:34 PM PDT 24
Finished Aug 09 04:24:35 PM PDT 24
Peak memory 192316 kb
Host smart-f8085c4c-b07f-462d-8571-d4a42ac6e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103951942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4103951942
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3360821878
Short name T166
Test name
Test status
Simulation time 544738155 ps
CPU time 0.84 seconds
Started Aug 09 04:23:43 PM PDT 24
Finished Aug 09 04:23:44 PM PDT 24
Peak memory 196700 kb
Host smart-41715b91-4efb-4109-9780-97515f0aefc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360821878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3360821878
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.925420448
Short name T193
Test name
Test status
Simulation time 55192418187 ps
CPU time 85.95 seconds
Started Aug 09 04:26:17 PM PDT 24
Finished Aug 09 04:27:44 PM PDT 24
Peak memory 189924 kb
Host smart-9498d86a-d4f0-4ab8-96d2-a8ed6ea29e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925420448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.925420448
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4065943517
Short name T234
Test name
Test status
Simulation time 447520790 ps
CPU time 0.72 seconds
Started Aug 09 04:26:19 PM PDT 24
Finished Aug 09 04:26:20 PM PDT 24
Peak memory 191760 kb
Host smart-648a2c1c-e8de-4200-b746-71e84201e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065943517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4065943517
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2863652852
Short name T6
Test name
Test status
Simulation time 26134904253 ps
CPU time 9.27 seconds
Started Aug 09 04:23:49 PM PDT 24
Finished Aug 09 04:23:59 PM PDT 24
Peak memory 192152 kb
Host smart-53660c24-d52c-41ca-b2c8-7c081ddff5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863652852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2863652852
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1662920799
Short name T192
Test name
Test status
Simulation time 517057513 ps
CPU time 0.65 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:25:26 PM PDT 24
Peak memory 191852 kb
Host smart-f877d86b-45be-4520-be3d-4c7e8132d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662920799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1662920799
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.409714680
Short name T205
Test name
Test status
Simulation time 27951633175 ps
CPU time 41.2 seconds
Started Aug 09 04:25:10 PM PDT 24
Finished Aug 09 04:25:52 PM PDT 24
Peak memory 196592 kb
Host smart-481e4e02-9491-458d-a18e-90ef928ddb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409714680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.409714680
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3000865750
Short name T236
Test name
Test status
Simulation time 394814399 ps
CPU time 0.66 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 191748 kb
Host smart-6e8fe002-9e6c-4048-8a30-8ec0c977761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000865750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3000865750
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2235547707
Short name T7
Test name
Test status
Simulation time 456091038 ps
CPU time 1.3 seconds
Started Aug 09 04:25:10 PM PDT 24
Finished Aug 09 04:25:12 PM PDT 24
Peak memory 195756 kb
Host smart-b6d5f5a6-6a3d-4793-98d2-6c4ec5af2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235547707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2235547707
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.854568708
Short name T224
Test name
Test status
Simulation time 21978426825 ps
CPU time 7.37 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:32 PM PDT 24
Peak memory 191876 kb
Host smart-73c6fcea-2ba9-4f33-8747-ba5d5e5045ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854568708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.854568708
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2528913376
Short name T273
Test name
Test status
Simulation time 356769311 ps
CPU time 1.04 seconds
Started Aug 09 04:25:11 PM PDT 24
Finished Aug 09 04:25:12 PM PDT 24
Peak memory 191556 kb
Host smart-e4493f55-1f31-478e-846d-cdc266ba8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528913376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2528913376
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.325333940
Short name T248
Test name
Test status
Simulation time 4689329741 ps
CPU time 2.36 seconds
Started Aug 09 04:23:29 PM PDT 24
Finished Aug 09 04:23:31 PM PDT 24
Peak memory 192000 kb
Host smart-bf51d258-eb60-45f3-98ed-2325d3e6c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325333940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.325333940
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2109946947
Short name T18
Test name
Test status
Simulation time 3964083129 ps
CPU time 3.61 seconds
Started Aug 09 04:22:59 PM PDT 24
Finished Aug 09 04:23:02 PM PDT 24
Peak memory 215264 kb
Host smart-ef738628-d4c0-4c9c-b2e7-8bb5304e85c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109946947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2109946947
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.761350878
Short name T245
Test name
Test status
Simulation time 497370606 ps
CPU time 0.78 seconds
Started Aug 09 04:21:53 PM PDT 24
Finished Aug 09 04:21:54 PM PDT 24
Peak memory 191892 kb
Host smart-c5064791-100a-4586-b2a8-42f53319cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761350878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.761350878
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1170910033
Short name T237
Test name
Test status
Simulation time 57329575133 ps
CPU time 18.22 seconds
Started Aug 09 04:25:21 PM PDT 24
Finished Aug 09 04:25:39 PM PDT 24
Peak memory 196940 kb
Host smart-7e9ead3b-91e9-4f51-83d4-164712fa3a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170910033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1170910033
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3222806842
Short name T256
Test name
Test status
Simulation time 558352100 ps
CPU time 0.76 seconds
Started Aug 09 04:25:18 PM PDT 24
Finished Aug 09 04:25:18 PM PDT 24
Peak memory 191900 kb
Host smart-c3acd91b-bbc7-4e8c-bd58-b5211c5ea649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222806842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3222806842
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3299934470
Short name T190
Test name
Test status
Simulation time 61053677575 ps
CPU time 49.58 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:26:15 PM PDT 24
Peak memory 191904 kb
Host smart-53bcb44c-01bf-4672-ae3c-d410cff8ba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299934470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3299934470
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.61255382
Short name T186
Test name
Test status
Simulation time 464990988 ps
CPU time 0.7 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 191852 kb
Host smart-e8606af3-a0f1-456e-8e86-709f9776a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61255382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.61255382
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.477217021
Short name T194
Test name
Test status
Simulation time 51141441440 ps
CPU time 70.65 seconds
Started Aug 09 04:25:25 PM PDT 24
Finished Aug 09 04:26:36 PM PDT 24
Peak memory 191928 kb
Host smart-87390918-4913-4491-ab6c-a7f5e2b97a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477217021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.477217021
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1382670916
Short name T265
Test name
Test status
Simulation time 430687942 ps
CPU time 1.12 seconds
Started Aug 09 04:25:09 PM PDT 24
Finished Aug 09 04:25:10 PM PDT 24
Peak memory 191016 kb
Host smart-0832cfe0-eda2-40e2-88ef-8cc024e04969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382670916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1382670916
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1781212929
Short name T24
Test name
Test status
Simulation time 20372338987 ps
CPU time 16.92 seconds
Started Aug 09 04:25:20 PM PDT 24
Finished Aug 09 04:25:37 PM PDT 24
Peak memory 190456 kb
Host smart-31dfb5f0-0db5-42a8-8733-0df651b44ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781212929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1781212929
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2405593118
Short name T223
Test name
Test status
Simulation time 427242331 ps
CPU time 0.77 seconds
Started Aug 09 04:25:19 PM PDT 24
Finished Aug 09 04:25:21 PM PDT 24
Peak memory 189576 kb
Host smart-5c76217a-007a-4d8e-9f2f-7c0f07647f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405593118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2405593118
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.771451113
Short name T259
Test name
Test status
Simulation time 14840021378 ps
CPU time 21.15 seconds
Started Aug 09 04:24:13 PM PDT 24
Finished Aug 09 04:24:35 PM PDT 24
Peak memory 192000 kb
Host smart-b71e4c61-ab14-4b0e-b4c2-405a7eb09012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771451113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.771451113
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3077498314
Short name T200
Test name
Test status
Simulation time 652742981 ps
CPU time 0.75 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:40 PM PDT 24
Peak memory 191892 kb
Host smart-d314558a-3a35-4dc8-8844-fca4262460f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077498314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3077498314
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4273239921
Short name T213
Test name
Test status
Simulation time 59372559339 ps
CPU time 86.44 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:27:12 PM PDT 24
Peak memory 191944 kb
Host smart-ea75cfda-21df-41c7-8e47-394a90d95b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273239921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4273239921
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2636698017
Short name T227
Test name
Test status
Simulation time 561182744 ps
CPU time 0.76 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:25:47 PM PDT 24
Peak memory 196716 kb
Host smart-be2694fc-c0e2-4763-8e07-f74b5502aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636698017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2636698017
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1145344102
Short name T162
Test name
Test status
Simulation time 604750176 ps
CPU time 0.99 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:25:47 PM PDT 24
Peak memory 196688 kb
Host smart-ff19deee-352f-41ee-8a96-b3b36b14364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145344102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1145344102
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.249429204
Short name T255
Test name
Test status
Simulation time 24969267060 ps
CPU time 9.62 seconds
Started Aug 09 04:24:28 PM PDT 24
Finished Aug 09 04:24:38 PM PDT 24
Peak memory 197008 kb
Host smart-cfd4f745-83eb-420e-bc91-b3c43f49b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249429204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.249429204
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.884138266
Short name T197
Test name
Test status
Simulation time 459306779 ps
CPU time 0.64 seconds
Started Aug 09 04:25:32 PM PDT 24
Finished Aug 09 04:25:33 PM PDT 24
Peak memory 191504 kb
Host smart-1ff99bdf-8e21-49d9-859d-29682f431340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884138266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.884138266
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2155010976
Short name T202
Test name
Test status
Simulation time 50460630637 ps
CPU time 38.32 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:26:24 PM PDT 24
Peak memory 196948 kb
Host smart-ed076ddf-51ec-4033-a177-4bb9e0f1357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155010976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2155010976
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2657179287
Short name T247
Test name
Test status
Simulation time 582572099 ps
CPU time 1.43 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:26 PM PDT 24
Peak memory 190992 kb
Host smart-b126fec1-30c8-4e70-bbba-97b3c5160105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657179287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2657179287
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1348621909
Short name T81
Test name
Test status
Simulation time 40802487424 ps
CPU time 60.07 seconds
Started Aug 09 04:24:27 PM PDT 24
Finished Aug 09 04:25:27 PM PDT 24
Peak memory 196992 kb
Host smart-4a3413d9-93b9-4915-b22c-0345157e5d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348621909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1348621909
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3997017267
Short name T235
Test name
Test status
Simulation time 616299070 ps
CPU time 1.02 seconds
Started Aug 09 04:24:25 PM PDT 24
Finished Aug 09 04:24:26 PM PDT 24
Peak memory 190656 kb
Host smart-ac43dd50-0cb2-4c32-8aa8-4dd872d3abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997017267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3997017267
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.785078074
Short name T163
Test name
Test status
Simulation time 480881884 ps
CPU time 1.48 seconds
Started Aug 09 04:24:29 PM PDT 24
Finished Aug 09 04:24:31 PM PDT 24
Peak memory 196680 kb
Host smart-1b573b47-3b1d-482d-8fa6-d4eacb87b783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785078074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.785078074
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2836378610
Short name T232
Test name
Test status
Simulation time 21256340366 ps
CPU time 4.87 seconds
Started Aug 09 04:25:39 PM PDT 24
Finished Aug 09 04:25:44 PM PDT 24
Peak memory 191740 kb
Host smart-cfdafd9c-6a86-4fc8-96ee-a45dd6acab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836378610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2836378610
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.864416970
Short name T249
Test name
Test status
Simulation time 494377603 ps
CPU time 0.75 seconds
Started Aug 09 04:24:27 PM PDT 24
Finished Aug 09 04:24:28 PM PDT 24
Peak memory 191924 kb
Host smart-71c03c8f-5b0b-4ed5-8045-985dc772b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864416970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.864416970
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1667116572
Short name T239
Test name
Test status
Simulation time 23171423618 ps
CPU time 17.11 seconds
Started Aug 09 04:22:26 PM PDT 24
Finished Aug 09 04:22:43 PM PDT 24
Peak memory 191988 kb
Host smart-3ae4db1c-c726-491b-8468-9de659eb8d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667116572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1667116572
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2203705366
Short name T16
Test name
Test status
Simulation time 4176871097 ps
CPU time 4.02 seconds
Started Aug 09 04:25:12 PM PDT 24
Finished Aug 09 04:25:16 PM PDT 24
Peak memory 215020 kb
Host smart-04c8e25d-02f9-4414-a96f-6a312ccef75e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203705366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2203705366
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3666466615
Short name T201
Test name
Test status
Simulation time 583264910 ps
CPU time 0.82 seconds
Started Aug 09 04:21:53 PM PDT 24
Finished Aug 09 04:21:54 PM PDT 24
Peak memory 196720 kb
Host smart-4eab5afd-a267-450d-84c3-34233bd5310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666466615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3666466615
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3178288906
Short name T219
Test name
Test status
Simulation time 48139878961 ps
CPU time 17.31 seconds
Started Aug 09 04:24:29 PM PDT 24
Finished Aug 09 04:24:47 PM PDT 24
Peak memory 191984 kb
Host smart-80ffe396-7e7b-4564-9317-d5ec5b76e3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178288906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3178288906
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.658952914
Short name T1
Test name
Test status
Simulation time 574945046 ps
CPU time 1.44 seconds
Started Aug 09 04:24:33 PM PDT 24
Finished Aug 09 04:24:35 PM PDT 24
Peak memory 191916 kb
Host smart-5e0d84b0-4632-4de9-8f22-95dd788b6ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658952914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.658952914
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2722435659
Short name T229
Test name
Test status
Simulation time 28100082847 ps
CPU time 11.9 seconds
Started Aug 09 04:24:41 PM PDT 24
Finished Aug 09 04:24:53 PM PDT 24
Peak memory 197400 kb
Host smart-3224252f-1129-4fd1-abda-2dbfb113e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722435659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2722435659
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2010292121
Short name T211
Test name
Test status
Simulation time 450874810 ps
CPU time 0.81 seconds
Started Aug 09 04:24:40 PM PDT 24
Finished Aug 09 04:24:41 PM PDT 24
Peak memory 192328 kb
Host smart-17cc063f-a7db-46b9-87c3-c9ccb07f0f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010292121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2010292121
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1881701430
Short name T275
Test name
Test status
Simulation time 34952735802 ps
CPU time 27.73 seconds
Started Aug 09 04:26:16 PM PDT 24
Finished Aug 09 04:26:44 PM PDT 24
Peak memory 190800 kb
Host smart-5f7fca3e-f881-4cc1-ad58-d58e1c9d0134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881701430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1881701430
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1888593617
Short name T268
Test name
Test status
Simulation time 462186829 ps
CPU time 0.72 seconds
Started Aug 09 04:24:37 PM PDT 24
Finished Aug 09 04:24:38 PM PDT 24
Peak memory 192056 kb
Host smart-756efbcb-949e-42bb-8a16-62b85ea46070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888593617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1888593617
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.353628146
Short name T225
Test name
Test status
Simulation time 15660304778 ps
CPU time 24.51 seconds
Started Aug 09 04:26:15 PM PDT 24
Finished Aug 09 04:26:41 PM PDT 24
Peak memory 195408 kb
Host smart-572061db-3a94-444d-aa16-cf2f65f94398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353628146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.353628146
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.574086213
Short name T22
Test name
Test status
Simulation time 552228366 ps
CPU time 1.52 seconds
Started Aug 09 04:24:40 PM PDT 24
Finished Aug 09 04:24:42 PM PDT 24
Peak memory 196780 kb
Host smart-7729c990-98b6-4f77-80dc-baca4a162b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574086213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.574086213
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1170035452
Short name T243
Test name
Test status
Simulation time 3178217018 ps
CPU time 2.89 seconds
Started Aug 09 04:24:41 PM PDT 24
Finished Aug 09 04:24:44 PM PDT 24
Peak memory 192148 kb
Host smart-8ea2c1ca-4020-4f7c-833a-f838815cf73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170035452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1170035452
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.987243761
Short name T240
Test name
Test status
Simulation time 605328382 ps
CPU time 0.63 seconds
Started Aug 09 04:26:14 PM PDT 24
Finished Aug 09 04:26:15 PM PDT 24
Peak memory 196560 kb
Host smart-02a27cd9-8107-4d10-abfc-51a8ec2933d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987243761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.987243761
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1641634011
Short name T230
Test name
Test status
Simulation time 32004736382 ps
CPU time 9.06 seconds
Started Aug 09 04:26:26 PM PDT 24
Finished Aug 09 04:26:35 PM PDT 24
Peak memory 197076 kb
Host smart-d0874950-fee5-4c8f-a630-d848f3e7b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641634011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1641634011
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2267440464
Short name T214
Test name
Test status
Simulation time 465586222 ps
CPU time 1.17 seconds
Started Aug 09 04:26:29 PM PDT 24
Finished Aug 09 04:26:31 PM PDT 24
Peak memory 196720 kb
Host smart-9c1bf4a3-6591-4ab1-9d69-069d37b8fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267440464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2267440464
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2955142406
Short name T270
Test name
Test status
Simulation time 32493942016 ps
CPU time 44.14 seconds
Started Aug 09 04:24:58 PM PDT 24
Finished Aug 09 04:25:42 PM PDT 24
Peak memory 192036 kb
Host smart-5742b614-c22b-4643-acf3-5a2aa84c0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955142406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2955142406
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3756866278
Short name T195
Test name
Test status
Simulation time 484734466 ps
CPU time 1.24 seconds
Started Aug 09 04:26:18 PM PDT 24
Finished Aug 09 04:26:19 PM PDT 24
Peak memory 191908 kb
Host smart-6309bfb6-51c0-45ef-b7b4-3cf5e28fc3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756866278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3756866278
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1177579671
Short name T212
Test name
Test status
Simulation time 20618112655 ps
CPU time 15.1 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:26:18 PM PDT 24
Peak memory 190604 kb
Host smart-f5fb497e-986f-4748-9c29-e94e7b94f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177579671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1177579671
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2337788131
Short name T271
Test name
Test status
Simulation time 395376216 ps
CPU time 1.19 seconds
Started Aug 09 04:26:03 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 195840 kb
Host smart-c07851aa-695d-48d2-a288-62481a07a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337788131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2337788131
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1556242696
Short name T251
Test name
Test status
Simulation time 22403911702 ps
CPU time 35.13 seconds
Started Aug 09 04:24:59 PM PDT 24
Finished Aug 09 04:25:34 PM PDT 24
Peak memory 191984 kb
Host smart-451d2c89-ff2c-402b-b101-d6f4f51e1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556242696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1556242696
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3402628069
Short name T228
Test name
Test status
Simulation time 393118307 ps
CPU time 1.13 seconds
Started Aug 09 04:24:58 PM PDT 24
Finished Aug 09 04:24:59 PM PDT 24
Peak memory 196764 kb
Host smart-6b6d5c62-63a2-4206-b910-62d6e57d8e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402628069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3402628069
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3896158904
Short name T215
Test name
Test status
Simulation time 19736445332 ps
CPU time 13.96 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:26:26 PM PDT 24
Peak memory 190900 kb
Host smart-685ddf38-4dd7-4fc5-a699-0dbf235d23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896158904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3896158904
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.905388413
Short name T231
Test name
Test status
Simulation time 365521979 ps
CPU time 0.68 seconds
Started Aug 09 04:26:12 PM PDT 24
Finished Aug 09 04:26:13 PM PDT 24
Peak memory 196440 kb
Host smart-597126ab-80be-46f3-8a59-6bc6ba183599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905388413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.905388413
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2073824538
Short name T241
Test name
Test status
Simulation time 33646367563 ps
CPU time 21.99 seconds
Started Aug 09 04:23:27 PM PDT 24
Finished Aug 09 04:23:50 PM PDT 24
Peak memory 191984 kb
Host smart-3e10ae8f-c608-4094-9f68-5fd67cf472bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073824538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2073824538
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1937888002
Short name T258
Test name
Test status
Simulation time 405867280 ps
CPU time 1.12 seconds
Started Aug 09 04:21:55 PM PDT 24
Finished Aug 09 04:21:56 PM PDT 24
Peak memory 191900 kb
Host smart-5d011e3b-84cc-4ad4-a7e3-5fdf544dcd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937888002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1937888002
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.71821500
Short name T264
Test name
Test status
Simulation time 16084470909 ps
CPU time 4.2 seconds
Started Aug 09 04:23:27 PM PDT 24
Finished Aug 09 04:23:32 PM PDT 24
Peak memory 191988 kb
Host smart-f4d42f3d-6454-448c-8ace-5510606ee08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71821500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.71821500
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.58507144
Short name T244
Test name
Test status
Simulation time 562767232 ps
CPU time 1.25 seconds
Started Aug 09 04:25:24 PM PDT 24
Finished Aug 09 04:25:25 PM PDT 24
Peak memory 196688 kb
Host smart-73f9e68f-b574-4021-b0fc-571fe08036ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58507144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.58507144
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2513552895
Short name T153
Test name
Test status
Simulation time 444588246 ps
CPU time 1.19 seconds
Started Aug 09 04:25:26 PM PDT 24
Finished Aug 09 04:25:28 PM PDT 24
Peak memory 196024 kb
Host smart-706ee3f9-c746-4672-869a-6b9fb73c2035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513552895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2513552895
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1310772550
Short name T263
Test name
Test status
Simulation time 17177560962 ps
CPU time 7.02 seconds
Started Aug 09 04:25:27 PM PDT 24
Finished Aug 09 04:25:34 PM PDT 24
Peak memory 191688 kb
Host smart-63314fa9-8195-4691-a7ae-2d2eafbe2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310772550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1310772550
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1111638022
Short name T253
Test name
Test status
Simulation time 467277466 ps
CPU time 0.61 seconds
Started Aug 09 04:21:13 PM PDT 24
Finished Aug 09 04:21:14 PM PDT 24
Peak memory 196728 kb
Host smart-03ffb501-3443-41c2-a1c1-5b3e66ec840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111638022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1111638022
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2221261746
Short name T217
Test name
Test status
Simulation time 3211493130 ps
CPU time 1.83 seconds
Started Aug 09 04:25:46 PM PDT 24
Finished Aug 09 04:25:48 PM PDT 24
Peak memory 196744 kb
Host smart-12698a28-a984-4c4f-995d-1d6679a80fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221261746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2221261746
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3461410214
Short name T187
Test name
Test status
Simulation time 477058750 ps
CPU time 1.3 seconds
Started Aug 09 04:22:17 PM PDT 24
Finished Aug 09 04:22:18 PM PDT 24
Peak memory 191940 kb
Host smart-ea6c33e6-2648-47ff-bc6a-373cbad765c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461410214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3461410214
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3878687054
Short name T221
Test name
Test status
Simulation time 30458646912 ps
CPU time 48.72 seconds
Started Aug 09 04:25:15 PM PDT 24
Finished Aug 09 04:26:04 PM PDT 24
Peak memory 196112 kb
Host smart-9daee3ba-384b-4242-b5b6-d17226a62a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878687054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3878687054
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2667795898
Short name T209
Test name
Test status
Simulation time 617152820 ps
CPU time 0.8 seconds
Started Aug 09 04:21:31 PM PDT 24
Finished Aug 09 04:21:32 PM PDT 24
Peak memory 196712 kb
Host smart-85f8731d-f87f-49f9-8864-8607c31ccd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667795898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2667795898
Directory /workspace/9.aon_timer_smoke/latest
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