Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26990	1		T1	10		T2	130		T3	108
bark[1]	667	1		T32	242		T93	21		T163	7
bark[2]	630	1		T37	14		T33	69		T174	14
bark[3]	380	1		T5	14		T9	80		T35	35
bark[4]	355	1		T16	42		T148	26		T82	54
bark[5]	296	1		T6	30		T11	14		T12	21
bark[6]	1145	1		T2	62		T9	21		T25	231
bark[7]	495	1		T146	21		T34	21		T35	21
bark[8]	451	1		T16	21		T121	40		T111	21
bark[9]	178	1		T35	47		T36	21		T82	21
bark[10]	565	1		T6	21		T146	21		T34	21
bark[11]	374	1		T25	113		T93	57		T104	14
bark[12]	196	1		T121	21		T36	7		T82	39
bark[13]	1024	1		T2	21		T24	21		T32	31
bark[14]	323	1		T38	14		T33	21		T163	7
bark[15]	462	1		T159	195		T114	21		T153	14
bark[16]	197	1		T2	30		T12	57		T98	21
bark[17]	130	1		T121	26		T91	14		T88	24
bark[18]	316	1		T3	43		T148	21		T182	14
bark[19]	284	1		T16	21		T35	21		T77	94
bark[20]	183	1		T2	26		T12	21		T161	38
bark[21]	657	1		T140	21		T159	21		T75	57
bark[22]	261	1		T33	26		T106	38		T144	14
bark[23]	656	1		T23	14		T25	102		T34	21
bark[24]	397	1		T111	21		T106	61		T75	30
bark[25]	768	1		T12	51		T178	14		T142	21
bark[26]	327	1		T12	21		T121	30		T148	138
bark[27]	1176	1		T39	14		T34	320		T36	170
bark[28]	457	1		T39	21		T159	231		T75	26
bark[29]	344	1		T16	47		T98	21		T129	21
bark[30]	736	1		T10	14		T25	73		T24	30
bark[31]	386	1		T24	14		T34	26		T76	26
bark_0	4687	1		T1	7		T2	7		T3	53

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26814	1		T1	9		T2	129		T3	104
bite[1]	695	1		T5	13		T16	46		T25	200
bite[2]	159	1		T148	13		T163	6		T96	21
bite[3]	426	1		T16	21		T98	21		T100	13
bite[4]	927	1		T98	21		T33	30		T121	40
bite[5]	663	1		T37	13		T148	138		T36	6
bite[6]	343	1		T25	72		T109	21		T83	76
bite[7]	1094	1		T12	57		T25	101		T24	43
bite[8]	433	1		T6	30		T33	25		T82	39
bite[9]	328	1		T15	21		T140	21		T106	61
bite[10]	144	1		T146	21		T33	21		T35	21
bite[11]	431	1		T2	26		T12	21		T121	51
bite[12]	130	1		T3	42		T123	13		T110	21
bite[13]	406	1		T12	21		T16	21		T111	21
bite[14]	841	1		T33	68		T34	319		T111	26
bite[15]	346	1		T12	51		T174	13		T34	21
bite[16]	838	1		T2	30		T111	21		T106	30
bite[17]	269	1		T9	101		T36	21		T129	4
bite[18]	127	1		T6	21		T135	21		T97	21
bite[19]	587	1		T121	26		T159	194		T165	25
bite[20]	687	1		T2	62		T25	30		T36	14
bite[21]	740	1		T39	21		T155	13		T141	13
bite[22]	214	1		T11	13		T23	13		T38	13
bite[23]	667	1		T16	21		T25	112		T24	21
bite[24]	1005	1		T32	30		T148	26		T35	35
bite[25]	397	1		T180	13		T35	21		T82	21
bite[26]	352	1		T32	241		T148	21		T35	46
bite[27]	346	1		T12	21		T39	13		T142	21
bite[28]	398	1		T2	21		T121	21		T82	42
bite[29]	192	1		T10	13		T146	21		T159	21
bite[30]	215	1		T16	21		T34	21		T111	21
bite[31]	143	1		T34	25		T118	55		T143	42
bite_0	5136	1		T1	8		T2	8		T3	58

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38898	1		T1	17		T2	276		T3	204
auto[1]	7595	1		T6	290		T7	7		T14	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	907	1		T12	9		T13	9		T15	45
prescale[1]	1334	1		T2	62		T3	2		T6	2
prescale[2]	827	1		T6	27		T34	19		T176	19
prescale[3]	924	1		T32	66		T33	11		T34	19
prescale[4]	902	1		T3	2		T24	19		T33	64
prescale[5]	420	1		T3	40		T12	19		T16	2
prescale[6]	828	1		T16	23		T35	95		T93	19
prescale[7]	666	1		T3	33		T6	21		T16	19
prescale[8]	998	1		T2	23		T6	90		T16	153
prescale[9]	553	1		T9	19		T16	79		T24	2
prescale[10]	734	1		T16	143		T32	2		T34	93
prescale[11]	929	1		T24	19		T33	19		T140	19
prescale[12]	576	1		T16	80		T39	40		T25	24
prescale[13]	420	1		T3	2		T6	2		T98	19
prescale[14]	709	1		T15	19		T16	195		T121	23
prescale[15]	646	1		T25	14		T196	9		T176	19
prescale[16]	393	1		T16	62		T39	42		T32	2
prescale[17]	1054	1		T6	2		T15	19		T16	68
prescale[18]	753	1		T6	52		T12	40		T39	19
prescale[19]	345	1		T12	19		T16	28		T34	2
prescale[20]	968	1		T15	9		T16	19		T39	19
prescale[21]	486	1		T6	2		T16	24		T24	2
prescale[22]	498	1		T16	19		T39	61		T35	2
prescale[23]	695	1		T3	2		T16	74		T32	2
prescale[24]	561	1		T6	68		T12	44		T24	2
prescale[25]	784	1		T2	28		T98	66		T34	36
prescale[26]	466	1		T6	19		T9	40		T33	52
prescale[27]	661	1		T6	2		T8	9		T25	4
prescale[28]	774	1		T74	9		T197	9		T33	24
prescale[29]	531	1		T15	19		T198	9		T34	36
prescale[30]	874	1		T146	28		T199	9		T176	49
prescale[31]	948	1		T6	19		T15	37		T16	97
prescale_0	23329	1		T1	17		T2	163		T3	123

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34554	1		T1	17		T2	233		T3	144
auto[1]	11939	1		T2	43		T3	60		T6	186

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	46493	1		T1	17		T2	276		T3	204

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27041	1		T1	12		T2	152		T3	119
wkup[1]	357	1		T2	30		T32	26		T35	21
wkup[2]	250	1		T39	21		T24	21		T33	30
wkup[3]	347	1		T25	31		T174	15		T148	21
wkup[4]	298	1		T12	21		T25	26		T34	30
wkup[5]	163	1		T129	6		T104	47		T80	21
wkup[6]	247	1		T25	21		T33	21		T35	21
wkup[7]	201	1		T12	21		T98	26		T33	8
wkup[8]	350	1		T3	21		T121	21		T83	26
wkup[9]	116	1		T119	21		T107	21		T147	8
wkup[10]	278	1		T140	30		T82	15		T163	21
wkup[11]	217	1		T6	30		T32	21		T34	21
wkup[12]	343	1		T16	21		T36	51		T82	21
wkup[13]	226	1		T6	21		T24	30		T33	21
wkup[14]	433	1		T12	21		T39	21		T121	30
wkup[15]	140	1		T25	21		T82	26		T83	21
wkup[16]	317	1		T25	21		T34	42		T35	21
wkup[17]	217	1		T32	21		T75	30		T104	26
wkup[18]	256	1		T12	21		T32	42		T36	21
wkup[19]	333	1		T2	21		T34	21		T82	26
wkup[20]	269	1		T2	21		T11	15		T16	21
wkup[21]	213	1		T16	26		T106	56		T77	21
wkup[22]	252	1		T12	21		T16	8		T93	30
wkup[23]	191	1		T36	21		T159	26		T163	21
wkup[24]	331	1		T25	42		T33	21		T82	26
wkup[25]	213	1		T6	21		T35	21		T123	15
wkup[26]	294	1		T16	21		T121	21		T34	21
wkup[27]	213	1		T146	21		T159	21		T84	21
wkup[28]	128	1		T3	21		T25	21		T75	21
wkup[29]	323	1		T16	21		T148	21		T36	29
wkup[30]	279	1		T2	21		T39	21		T24	21
wkup[31]	226	1		T35	26		T82	42		T153	15
wkup[32]	277	1		T2	26		T16	21		T34	21
wkup[33]	311	1		T6	30		T9	21		T16	21
wkup[34]	198	1		T5	15		T9	21		T35	21
wkup[35]	321	1		T35	21		T82	30		T165	57
wkup[36]	308	1		T6	21		T25	30		T32	21
wkup[37]	264	1		T140	21		T35	35		T36	20
wkup[38]	175	1		T93	21		T131	15		T104	15
wkup[39]	284	1		T12	21		T16	31		T33	30
wkup[40]	193	1		T82	21		T106	21		T151	26
wkup[41]	173	1		T35	21		T75	26		T77	21
wkup[42]	272	1		T98	21		T161	21		T83	21
wkup[43]	246	1		T34	21		T82	21		T111	21
wkup[44]	187	1		T33	21		T148	21		T34	21
wkup[45]	187	1		T32	24		T109	21		T75	21
wkup[46]	131	1		T25	30		T36	30		T82	21
wkup[47]	261	1		T9	21		T12	30		T16	41
wkup[48]	198	1		T146	21		T34	26		T36	21
wkup[49]	296	1		T6	21		T16	21		T180	15
wkup[50]	290	1		T37	15		T38	15		T146	21
wkup[51]	203	1		T34	21		T35	21		T82	35
wkup[52]	235	1		T25	21		T33	47		T121	21
wkup[53]	156	1		T23	15		T148	21		T34	21
wkup[54]	341	1		T16	21		T34	63		T83	51
wkup[55]	321	1		T16	21		T33	15		T34	21
wkup[56]	202	1		T33	48		T148	15		T34	21
wkup[57]	224	1		T32	21		T36	21		T104	48
wkup[58]	228	1		T16	42		T24	21		T35	21
wkup[59]	247	1		T25	21		T36	21		T159	21
wkup[60]	226	1		T10	15		T176	30		T129	29
wkup[61]	237	1		T16	21		T82	60		T139	21
wkup[62]	209	1		T15	21		T39	15		T24	15
wkup[63]	367	1		T34	21		T36	21		T159	31
wkup_0	3663	1		T1	5		T2	5		T3	43