Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.78 99.33 93.67 100.00 98.40 99.51 47.76


Total test records in report: 422
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T27 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.965940732 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 468993432 ps
T284 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2943667018 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 724391938 ps
T285 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.929926226 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:39 PM PDT 24 464213032 ps
T28 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3076353989 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:40 PM PDT 24 8119554543 ps
T286 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.785091047 Aug 10 04:41:28 PM PDT 24 Aug 10 04:41:29 PM PDT 24 343627216 ps
T200 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1698892258 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:40 PM PDT 24 471007548 ps
T201 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3995393344 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:45 PM PDT 24 438786590 ps
T50 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3011913953 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:35 PM PDT 24 537605645 ps
T287 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.656898830 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 372966283 ps
T65 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3747305177 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:41 PM PDT 24 1426041892 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2773933912 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:40 PM PDT 24 481730141 ps
T289 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2478016530 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:45 PM PDT 24 469579689 ps
T66 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4118416751 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 521051149 ps
T290 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2152252876 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 481990150 ps
T51 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4275547869 Aug 10 04:41:43 PM PDT 24 Aug 10 04:41:44 PM PDT 24 315103029 ps
T291 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1422954003 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:48 PM PDT 24 491946013 ps
T292 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4144038673 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 582627430 ps
T293 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3913993052 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:57 PM PDT 24 318923606 ps
T29 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.330078571 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:48 PM PDT 24 4248222272 ps
T294 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.552133698 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:43 PM PDT 24 8679309288 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2489789316 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:38 PM PDT 24 378071890 ps
T296 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2122921819 Aug 10 04:41:43 PM PDT 24 Aug 10 04:41:44 PM PDT 24 536839849 ps
T191 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.574991046 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:46 PM PDT 24 4250284695 ps
T297 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2657720593 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:47 PM PDT 24 588438694 ps
T67 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3319387418 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:48 PM PDT 24 2030630452 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3055478082 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:28 PM PDT 24 560439018 ps
T299 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2797082918 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:54 PM PDT 24 458736641 ps
T300 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3956373067 Aug 10 04:41:51 PM PDT 24 Aug 10 04:41:52 PM PDT 24 296952670 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1659208604 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 405346879 ps
T302 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3535611740 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:57 PM PDT 24 440101361 ps
T303 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.994713917 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:38 PM PDT 24 365473238 ps
T194 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.745179367 Aug 10 04:41:57 PM PDT 24 Aug 10 04:42:04 PM PDT 24 8945295475 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1304820035 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:48 PM PDT 24 1296445459 ps
T304 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.145081551 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:57 PM PDT 24 406419360 ps
T305 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3147208235 Aug 10 04:41:57 PM PDT 24 Aug 10 04:41:58 PM PDT 24 458190353 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2103021946 Aug 10 04:41:48 PM PDT 24 Aug 10 04:41:49 PM PDT 24 447808950 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4143104493 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:27 PM PDT 24 409622391 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3294156181 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:41 PM PDT 24 9695043755 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1288488003 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:25 PM PDT 24 272262291 ps
T53 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2470761568 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 463343189 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1726146143 Aug 10 04:41:39 PM PDT 24 Aug 10 04:41:44 PM PDT 24 8732043469 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3460008574 Aug 10 04:41:42 PM PDT 24 Aug 10 04:41:43 PM PDT 24 393338421 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.108178592 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:29 PM PDT 24 6946382756 ps
T311 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.296117416 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:54 PM PDT 24 338984110 ps
T69 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.923901267 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:49 PM PDT 24 1374749925 ps
T312 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1726017117 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:48 PM PDT 24 4255675364 ps
T313 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4046519978 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 420907276 ps
T314 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4019759354 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:56 PM PDT 24 421718564 ps
T70 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4263754294 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:41 PM PDT 24 2520574400 ps
T315 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2663144936 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:37 PM PDT 24 436384164 ps
T316 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.332599203 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 415412481 ps
T317 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2740938646 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:49 PM PDT 24 390191167 ps
T318 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1998953317 Aug 10 04:41:50 PM PDT 24 Aug 10 04:41:51 PM PDT 24 513066758 ps
T319 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1723932746 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:54 PM PDT 24 389239648 ps
T320 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3329988053 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 689044343 ps
T321 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1869482012 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:47 PM PDT 24 310966506 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1769288543 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:27 PM PDT 24 372588289 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1625047171 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:48 PM PDT 24 498971930 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1172849265 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:28 PM PDT 24 340246607 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4227256852 Aug 10 04:41:27 PM PDT 24 Aug 10 04:41:27 PM PDT 24 805409786 ps
T325 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3743929297 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 555897778 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.408335226 Aug 10 04:41:27 PM PDT 24 Aug 10 04:41:28 PM PDT 24 431980213 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1477213634 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:37 PM PDT 24 8847553962 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3742728042 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:27 PM PDT 24 493822502 ps
T72 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2771355021 Aug 10 04:41:39 PM PDT 24 Aug 10 04:41:40 PM PDT 24 1038200620 ps
T56 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3225635576 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:38 PM PDT 24 417970697 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3462978748 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:27 PM PDT 24 2390434582 ps
T329 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1112127331 Aug 10 04:41:50 PM PDT 24 Aug 10 04:41:54 PM PDT 24 2468423195 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3866794513 Aug 10 04:41:23 PM PDT 24 Aug 10 04:41:25 PM PDT 24 445482613 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2400831320 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:48 PM PDT 24 1037907980 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.774201104 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 524570981 ps
T332 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2005316783 Aug 10 04:41:51 PM PDT 24 Aug 10 04:41:52 PM PDT 24 512117426 ps
T333 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2517979721 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:36 PM PDT 24 340836667 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1788603855 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 412106053 ps
T335 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2895337092 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:48 PM PDT 24 315749034 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2033160220 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:36 PM PDT 24 304490799 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1192669985 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 620347961 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.427137152 Aug 10 04:41:40 PM PDT 24 Aug 10 04:41:41 PM PDT 24 330655147 ps
T192 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2519361408 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:27 PM PDT 24 4480734491 ps
T193 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4163357007 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:39 PM PDT 24 8907152912 ps
T338 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3730535264 Aug 10 04:41:55 PM PDT 24 Aug 10 04:41:56 PM PDT 24 385611443 ps
T195 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.824152715 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:50 PM PDT 24 4592811485 ps
T339 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1378294755 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 440433732 ps
T340 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3746102992 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:45 PM PDT 24 884871301 ps
T341 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4004475352 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:45 PM PDT 24 336909489 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1518462190 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:38 PM PDT 24 1523886291 ps
T343 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4251476318 Aug 10 04:41:39 PM PDT 24 Aug 10 04:41:40 PM PDT 24 444250479 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3287592113 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:39 PM PDT 24 374272419 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1421058360 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:27 PM PDT 24 480610202 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.478692226 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 418191860 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2570775198 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:28 PM PDT 24 1126146269 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3913536162 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:46 PM PDT 24 4876743334 ps
T349 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2962626798 Aug 10 04:41:55 PM PDT 24 Aug 10 04:41:56 PM PDT 24 439846848 ps
T350 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3635134971 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:38 PM PDT 24 1676628368 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.93527541 Aug 10 04:41:40 PM PDT 24 Aug 10 04:41:41 PM PDT 24 342467622 ps
T352 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1596704316 Aug 10 04:41:55 PM PDT 24 Aug 10 04:41:56 PM PDT 24 362432213 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1793821251 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:36 PM PDT 24 533438892 ps
T354 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2596789254 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:36 PM PDT 24 1153386298 ps
T355 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4266646278 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:54 PM PDT 24 360631820 ps
T356 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1762659618 Aug 10 04:41:57 PM PDT 24 Aug 10 04:41:58 PM PDT 24 366008663 ps
T357 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3379673316 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:38 PM PDT 24 342707589 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.586731954 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:38 PM PDT 24 413255258 ps
T359 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3989281044 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:40 PM PDT 24 583276000 ps
T360 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2863467981 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:56 PM PDT 24 547190894 ps
T361 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1175058703 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 326735789 ps
T362 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.796561100 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:54 PM PDT 24 314263545 ps
T363 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3906768412 Aug 10 04:41:55 PM PDT 24 Aug 10 04:41:56 PM PDT 24 348357670 ps
T364 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3275500611 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:48 PM PDT 24 328328443 ps
T365 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1565958336 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:48 PM PDT 24 876695617 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1962777133 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:37 PM PDT 24 343836297 ps
T367 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3069505805 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:35 PM PDT 24 414705972 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3135608540 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:40 PM PDT 24 8197186537 ps
T369 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3382970119 Aug 10 04:41:39 PM PDT 24 Aug 10 04:41:40 PM PDT 24 476837181 ps
T370 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3944105861 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:59 PM PDT 24 8310697861 ps
T371 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3368577879 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:55 PM PDT 24 1168986782 ps
T372 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.254551913 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 401443574 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1946954225 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:39 PM PDT 24 298704394 ps
T374 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2306427077 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:47 PM PDT 24 443771876 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1036502102 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:47 PM PDT 24 492352828 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2198824537 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:39 PM PDT 24 408487085 ps
T377 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1118403670 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:25 PM PDT 24 379616902 ps
T378 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.273635035 Aug 10 04:41:57 PM PDT 24 Aug 10 04:41:58 PM PDT 24 459048960 ps
T379 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1028950075 Aug 10 04:41:43 PM PDT 24 Aug 10 04:41:46 PM PDT 24 4211717148 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1711222402 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:27 PM PDT 24 397181951 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3206736909 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:38 PM PDT 24 337364718 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3841048736 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:26 PM PDT 24 901828972 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.577677723 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:26 PM PDT 24 523951050 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3644397000 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:30 PM PDT 24 6948700597 ps
T383 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.495121526 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 467522002 ps
T384 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2108838006 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:39 PM PDT 24 497615027 ps
T385 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.820831473 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:36 PM PDT 24 443606693 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3843552985 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:25 PM PDT 24 368855411 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.218155278 Aug 10 04:41:36 PM PDT 24 Aug 10 04:41:37 PM PDT 24 446249844 ps
T63 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1293702619 Aug 10 04:41:47 PM PDT 24 Aug 10 04:41:48 PM PDT 24 546212649 ps
T388 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.331519122 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 443008140 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3418369962 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:26 PM PDT 24 443999463 ps
T390 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1010330152 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:47 PM PDT 24 747554478 ps
T391 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3219748313 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:53 PM PDT 24 386705174 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3295890011 Aug 10 04:41:40 PM PDT 24 Aug 10 04:41:41 PM PDT 24 601262214 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1796401883 Aug 10 04:41:50 PM PDT 24 Aug 10 04:41:52 PM PDT 24 482139840 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1001085634 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 452022894 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3904234766 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 428354912 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1453099648 Aug 10 04:41:37 PM PDT 24 Aug 10 04:41:39 PM PDT 24 912974308 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3299187714 Aug 10 04:41:24 PM PDT 24 Aug 10 04:41:26 PM PDT 24 1296621072 ps
T398 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2981455794 Aug 10 04:41:56 PM PDT 24 Aug 10 04:41:57 PM PDT 24 473461527 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3118543284 Aug 10 04:41:25 PM PDT 24 Aug 10 04:41:28 PM PDT 24 4269699432 ps
T400 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4123468096 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:46 PM PDT 24 4291206109 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.722253754 Aug 10 04:41:35 PM PDT 24 Aug 10 04:41:37 PM PDT 24 337008067 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3382729307 Aug 10 04:41:26 PM PDT 24 Aug 10 04:41:26 PM PDT 24 818024365 ps
T403 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2551302834 Aug 10 04:41:55 PM PDT 24 Aug 10 04:41:56 PM PDT 24 463654200 ps
T404 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3971959704 Aug 10 04:41:53 PM PDT 24 Aug 10 04:41:54 PM PDT 24 320143562 ps
T58 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3540763230 Aug 10 04:41:44 PM PDT 24 Aug 10 04:41:45 PM PDT 24 506095756 ps
T405 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1571201382 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 472104960 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.452109982 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:40 PM PDT 24 1141653937 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.411235459 Aug 10 04:41:39 PM PDT 24 Aug 10 04:41:42 PM PDT 24 1288116286 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1845364536 Aug 10 04:41:23 PM PDT 24 Aug 10 04:41:27 PM PDT 24 2400195216 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3990524542 Aug 10 04:41:50 PM PDT 24 Aug 10 04:41:51 PM PDT 24 1803108115 ps
T64 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.680169225 Aug 10 04:41:48 PM PDT 24 Aug 10 04:41:48 PM PDT 24 571793961 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.771247518 Aug 10 04:41:34 PM PDT 24 Aug 10 04:41:34 PM PDT 24 590450853 ps
T410 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1924817169 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 508070495 ps
T411 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2079793160 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:53 PM PDT 24 8454622905 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.186562755 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:47 PM PDT 24 293224720 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.513819994 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 1480430184 ps
T414 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2179876715 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:46 PM PDT 24 510110296 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.866168372 Aug 10 04:41:45 PM PDT 24 Aug 10 04:41:47 PM PDT 24 490346670 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.126276285 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:46 PM PDT 24 4382108680 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1042035003 Aug 10 04:41:38 PM PDT 24 Aug 10 04:41:40 PM PDT 24 1296320917 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2460903304 Aug 10 04:41:23 PM PDT 24 Aug 10 04:41:51 PM PDT 24 13492588981 ps
T419 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3814381501 Aug 10 04:41:46 PM PDT 24 Aug 10 04:41:59 PM PDT 24 8142479584 ps
T420 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1975570765 Aug 10 04:41:54 PM PDT 24 Aug 10 04:41:55 PM PDT 24 445430984 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3399767101 Aug 10 04:41:28 PM PDT 24 Aug 10 04:41:30 PM PDT 24 500710605 ps
T422 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2486630071 Aug 10 04:41:50 PM PDT 24 Aug 10 04:41:51 PM PDT 24 514334514 ps

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1276148251
Short name T6
Test name
Test status
Simulation time 131327036678 ps
CPU time 969.85 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:42:56 PM PDT 24
Peak memory 209084 kb
Host smart-56868059-7573-4ab1-af7b-d64ee0c4792d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276148251 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1276148251
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3084579160
Short name T4
Test name
Test status
Simulation time 7321742511 ps
CPU time 9.98 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:26:17 PM PDT 24
Peak memory 215760 kb
Host smart-7f05158a-d0c6-4bd4-af3b-96ed0a4e9e42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084579160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3084579160
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.842973325
Short name T16
Test name
Test status
Simulation time 355622077672 ps
CPU time 590.46 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:36:11 PM PDT 24
Peak memory 204412 kb
Host smart-768be0dc-ac7d-4f60-80fc-ee30e296b40e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842973325 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.842973325
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2870586240
Short name T12
Test name
Test status
Simulation time 215326233751 ps
CPU time 323.66 seconds
Started Aug 10 04:26:12 PM PDT 24
Finished Aug 10 04:31:36 PM PDT 24
Peak memory 192776 kb
Host smart-bca79aac-788c-42bb-a56f-e20b9d856b92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870586240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2870586240
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3011913953
Short name T50
Test name
Test status
Simulation time 537605645 ps
CPU time 0.66 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:35 PM PDT 24
Peak memory 192896 kb
Host smart-b8fb811e-5ca8-4403-974e-c848429dffac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011913953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3011913953
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3945471639
Short name T82
Test name
Test status
Simulation time 87724673790 ps
CPU time 315.71 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:32:12 PM PDT 24
Peak memory 214032 kb
Host smart-21c7d869-e0c1-409c-9aae-52939812cd8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945471639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3945471639
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.515684179
Short name T104
Test name
Test status
Simulation time 115786000913 ps
CPU time 227.31 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:30:31 PM PDT 24
Peak memory 206808 kb
Host smart-dea18684-c084-49fe-88dd-53be752ce552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515684179 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.515684179
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.296126006
Short name T88
Test name
Test status
Simulation time 287911300297 ps
CPU time 561.31 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:35:53 PM PDT 24
Peak memory 204824 kb
Host smart-a73b8523-e7aa-4918-be6b-ab38de057ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296126006 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.296126006
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2043828242
Short name T77
Test name
Test status
Simulation time 42305468846 ps
CPU time 398.01 seconds
Started Aug 10 04:26:19 PM PDT 24
Finished Aug 10 04:32:57 PM PDT 24
Peak memory 200236 kb
Host smart-bc14978d-7e2b-45e5-9cb1-b4e6c634f807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043828242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2043828242
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4046383562
Short name T103
Test name
Test status
Simulation time 177902994614 ps
CPU time 256.24 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:30:54 PM PDT 24
Peak memory 191984 kb
Host smart-acc77f18-ad8b-4841-980c-ea5a58f8abdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046383562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4046383562
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2958567315
Short name T75
Test name
Test status
Simulation time 74878655498 ps
CPU time 469.73 seconds
Started Aug 10 04:26:09 PM PDT 24
Finished Aug 10 04:33:59 PM PDT 24
Peak memory 203488 kb
Host smart-7b584826-371a-4c7a-9907-6843202c2f33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958567315 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2958567315
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1453862166
Short name T105
Test name
Test status
Simulation time 139898040792 ps
CPU time 240.12 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:30:06 PM PDT 24
Peak memory 215088 kb
Host smart-88c9b004-cfc6-4732-b54f-af10b0c9c8fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453862166 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1453862166
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4003593069
Short name T33
Test name
Test status
Simulation time 95676288368 ps
CPU time 494.3 seconds
Started Aug 10 04:26:37 PM PDT 24
Finished Aug 10 04:34:52 PM PDT 24
Peak memory 212480 kb
Host smart-f01c0d00-0c47-41f7-a622-817c7e58d382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003593069 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4003593069
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2211993524
Short name T111
Test name
Test status
Simulation time 135343977413 ps
CPU time 42.18 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:26:48 PM PDT 24
Peak memory 198352 kb
Host smart-b2c0a2ba-b44d-4364-b4fc-c62839fccf04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211993524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2211993524
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2360390056
Short name T80
Test name
Test status
Simulation time 59435107195 ps
CPU time 480.61 seconds
Started Aug 10 04:26:10 PM PDT 24
Finished Aug 10 04:34:11 PM PDT 24
Peak memory 210332 kb
Host smart-cf5ea43e-ae5c-4436-b09d-a1593f9ca007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360390056 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2360390056
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2503602668
Short name T121
Test name
Test status
Simulation time 30630498725 ps
CPU time 48.46 seconds
Started Aug 10 04:26:32 PM PDT 24
Finished Aug 10 04:27:20 PM PDT 24
Peak memory 192124 kb
Host smart-10395f7d-c196-4245-97ca-d4a0ba538406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503602668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2503602668
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1183057125
Short name T35
Test name
Test status
Simulation time 38663993697 ps
CPU time 397.13 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:33:35 PM PDT 24
Peak memory 200184 kb
Host smart-e3f8b6cb-1b87-40d2-9732-23f9fa294b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183057125 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1183057125
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2215076505
Short name T25
Test name
Test status
Simulation time 113382051126 ps
CPU time 307.64 seconds
Started Aug 10 04:26:11 PM PDT 24
Finished Aug 10 04:31:19 PM PDT 24
Peak memory 206880 kb
Host smart-3b4d2f4f-1ae7-456d-beb1-642e3d4cf8a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215076505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2215076505
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1598746672
Short name T99
Test name
Test status
Simulation time 126525002643 ps
CPU time 38.58 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 198392 kb
Host smart-a4f95944-2f5f-4f14-be51-d5a4f8ac4145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598746672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1598746672
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3525923250
Short name T132
Test name
Test status
Simulation time 18830191297 ps
CPU time 146 seconds
Started Aug 10 04:26:32 PM PDT 24
Finished Aug 10 04:28:58 PM PDT 24
Peak memory 206836 kb
Host smart-018ebd48-54d3-4b80-88a6-69c63e723a74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525923250 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3525923250
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.330078571
Short name T29
Test name
Test status
Simulation time 4248222272 ps
CPU time 2.56 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 197788 kb
Host smart-7c3a8604-b19e-498f-b1ac-6bcafd7f6728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330078571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.330078571
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3087570364
Short name T112
Test name
Test status
Simulation time 83826152394 ps
CPU time 238.64 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:30:05 PM PDT 24
Peak memory 214096 kb
Host smart-2807995a-df7a-4148-a24f-8d44c9065019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087570364 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3087570364
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2608771259
Short name T156
Test name
Test status
Simulation time 146129067264 ps
CPU time 113.79 seconds
Started Aug 10 04:26:44 PM PDT 24
Finished Aug 10 04:28:38 PM PDT 24
Peak memory 198376 kb
Host smart-727cdac8-7221-4abc-83be-ce9f2e5bc141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608771259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2608771259
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3345271048
Short name T148
Test name
Test status
Simulation time 321235878769 ps
CPU time 104.99 seconds
Started Aug 10 04:26:52 PM PDT 24
Finished Aug 10 04:28:37 PM PDT 24
Peak memory 198328 kb
Host smart-f9624d6d-90f8-4bc1-bfa9-a3e333dab6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345271048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3345271048
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3480133591
Short name T90
Test name
Test status
Simulation time 78112503298 ps
CPU time 24.46 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:26:48 PM PDT 24
Peak memory 192016 kb
Host smart-c4aaa75f-48d0-4d1e-8a56-a01fab926ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480133591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3480133591
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1017341863
Short name T124
Test name
Test status
Simulation time 50852465308 ps
CPU time 20.4 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:26:44 PM PDT 24
Peak memory 198300 kb
Host smart-f71edeee-13f5-45ed-9bbd-89592fdc4e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017341863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1017341863
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2973707888
Short name T110
Test name
Test status
Simulation time 78457839745 ps
CPU time 8.29 seconds
Started Aug 10 04:26:08 PM PDT 24
Finished Aug 10 04:26:16 PM PDT 24
Peak memory 191996 kb
Host smart-de6c832d-717d-46e5-860f-666c93eb553a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973707888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2973707888
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2662909663
Short name T159
Test name
Test status
Simulation time 22237138207 ps
CPU time 95.56 seconds
Started Aug 10 04:26:40 PM PDT 24
Finished Aug 10 04:28:16 PM PDT 24
Peak memory 206712 kb
Host smart-d411bf0c-0309-4662-b151-12736f239e0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662909663 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2662909663
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2489562469
Short name T106
Test name
Test status
Simulation time 113966025785 ps
CPU time 181.71 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:29:22 PM PDT 24
Peak memory 192580 kb
Host smart-8b427db0-14e2-41a2-9940-0a476dae0522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489562469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2489562469
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2378251812
Short name T89
Test name
Test status
Simulation time 75943083666 ps
CPU time 55.81 seconds
Started Aug 10 04:26:48 PM PDT 24
Finished Aug 10 04:27:44 PM PDT 24
Peak memory 192036 kb
Host smart-fcc83b59-1565-4ae4-8c46-19e13475ef97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378251812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2378251812
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4275547869
Short name T51
Test name
Test status
Simulation time 315103029 ps
CPU time 0.81 seconds
Started Aug 10 04:41:43 PM PDT 24
Finished Aug 10 04:41:44 PM PDT 24
Peak memory 193500 kb
Host smart-17fde1a0-168c-4eab-afc2-9cc2703915d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275547869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4275547869
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4270057833
Short name T125
Test name
Test status
Simulation time 391520104691 ps
CPU time 296.49 seconds
Started Aug 10 04:26:09 PM PDT 24
Finished Aug 10 04:31:06 PM PDT 24
Peak memory 209868 kb
Host smart-3b3e2e46-9368-4943-b890-2b043970c12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270057833 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4270057833
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4171870226
Short name T36
Test name
Test status
Simulation time 294432031673 ps
CPU time 347.37 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:32:13 PM PDT 24
Peak memory 214400 kb
Host smart-3f14224b-6a86-419d-89cb-7ee975a1df28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171870226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4171870226
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2506006094
Short name T143
Test name
Test status
Simulation time 10984012809 ps
CPU time 115.59 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:28:52 PM PDT 24
Peak memory 198576 kb
Host smart-423cdf42-78c2-4455-9a52-f783ceb4667b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506006094 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2506006094
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3824361416
Short name T127
Test name
Test status
Simulation time 100070352830 ps
CPU time 33.55 seconds
Started Aug 10 04:26:07 PM PDT 24
Finished Aug 10 04:26:41 PM PDT 24
Peak memory 192052 kb
Host smart-90354960-70bb-49e0-be5c-e105d81a5d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824361416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3824361416
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2373068329
Short name T24
Test name
Test status
Simulation time 55291924322 ps
CPU time 571.31 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:36:09 PM PDT 24
Peak memory 206752 kb
Host smart-9bf2edda-bc8d-41f7-87e9-a253173d55c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373068329 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2373068329
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.721315726
Short name T83
Test name
Test status
Simulation time 180140022227 ps
CPU time 517.99 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:34:58 PM PDT 24
Peak memory 212440 kb
Host smart-00a5a8eb-c1ec-4d79-9537-23d90553c35c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721315726 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.721315726
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3370854794
Short name T94
Test name
Test status
Simulation time 42756217987 ps
CPU time 15.7 seconds
Started Aug 10 04:26:29 PM PDT 24
Finished Aug 10 04:26:45 PM PDT 24
Peak memory 198404 kb
Host smart-9e681df5-b01c-4767-bc49-661f22fb56ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370854794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3370854794
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2796706175
Short name T102
Test name
Test status
Simulation time 256666583928 ps
CPU time 182.85 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 04:30:05 PM PDT 24
Peak memory 192000 kb
Host smart-8e997d7f-2de3-4ea8-b598-2666d1edd026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796706175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2796706175
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2426388739
Short name T154
Test name
Test status
Simulation time 73962672752 ps
CPU time 109.56 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:28:23 PM PDT 24
Peak memory 184776 kb
Host smart-4c541b56-fe2e-42cb-9054-49ca0f59beee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426388739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2426388739
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1014239555
Short name T113
Test name
Test status
Simulation time 181357961899 ps
CPU time 240.17 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:31:00 PM PDT 24
Peak memory 193112 kb
Host smart-45b83a46-cb2a-4341-89aa-5aa7a1e09787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014239555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1014239555
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3752540267
Short name T34
Test name
Test status
Simulation time 22441618483 ps
CPU time 152.72 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:29:10 PM PDT 24
Peak memory 206804 kb
Host smart-4f99f7b6-a336-415f-9f4d-7700a9473554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752540267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3752540267
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1520069282
Short name T147
Test name
Test status
Simulation time 52801417409 ps
CPU time 112.91 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:28:36 PM PDT 24
Peak memory 214340 kb
Host smart-6aba610f-6d96-4f92-93f6-1360eb1eef8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520069282 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1520069282
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3414871108
Short name T109
Test name
Test status
Simulation time 555930079088 ps
CPU time 211.52 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:29:51 PM PDT 24
Peak memory 198368 kb
Host smart-d36d2d11-bfa9-41be-9c5b-7d0c3cf7304e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414871108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3414871108
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3413171877
Short name T40
Test name
Test status
Simulation time 222029971720 ps
CPU time 270.94 seconds
Started Aug 10 04:26:19 PM PDT 24
Finished Aug 10 04:30:50 PM PDT 24
Peak memory 199044 kb
Host smart-2bd485a9-6139-4748-b5c2-177304c22f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413171877 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3413171877
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3310180581
Short name T135
Test name
Test status
Simulation time 101443996346 ps
CPU time 152.6 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:29:28 PM PDT 24
Peak memory 198292 kb
Host smart-b45f9d3c-a079-4fa1-a63d-2cdc3c9a3ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310180581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3310180581
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3124161724
Short name T142
Test name
Test status
Simulation time 409383572669 ps
CPU time 272.18 seconds
Started Aug 10 04:26:19 PM PDT 24
Finished Aug 10 04:30:52 PM PDT 24
Peak memory 191980 kb
Host smart-14b780ea-09b8-405e-9f05-f52cfa6ad55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124161724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3124161724
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2726276464
Short name T39
Test name
Test status
Simulation time 243475076463 ps
CPU time 45.11 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 04:27:39 PM PDT 24
Peak memory 198336 kb
Host smart-2e2cba60-8415-4394-a19d-989e7f39b912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726276464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2726276464
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3648541982
Short name T9
Test name
Test status
Simulation time 82490462422 ps
CPU time 45.52 seconds
Started Aug 10 04:26:22 PM PDT 24
Finished Aug 10 04:27:07 PM PDT 24
Peak memory 191968 kb
Host smart-d3aa08db-b523-40ec-8971-fd4804ad230b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648541982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3648541982
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.370327978
Short name T161
Test name
Test status
Simulation time 229979696109 ps
CPU time 306.37 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:31:31 PM PDT 24
Peak memory 193100 kb
Host smart-56a8db59-1d2e-47b4-8614-aa88cd0d0307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370327978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.370327978
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1063508026
Short name T81
Test name
Test status
Simulation time 116391256797 ps
CPU time 373.84 seconds
Started Aug 10 04:26:36 PM PDT 24
Finished Aug 10 04:32:50 PM PDT 24
Peak memory 206872 kb
Host smart-515d0d14-aac3-425a-8839-6e58f12874d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063508026 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1063508026
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.257628049
Short name T118
Test name
Test status
Simulation time 212395224894 ps
CPU time 341.53 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:32:07 PM PDT 24
Peak memory 191996 kb
Host smart-61dc2208-7b6c-4ced-85f6-9e3d4e1195a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257628049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.257628049
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3978510374
Short name T107
Test name
Test status
Simulation time 390124193386 ps
CPU time 202.5 seconds
Started Aug 10 04:26:51 PM PDT 24
Finished Aug 10 04:30:13 PM PDT 24
Peak memory 206848 kb
Host smart-c819d396-8b46-49d3-b063-c3bc9baeda8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978510374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3978510374
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3403669693
Short name T151
Test name
Test status
Simulation time 61648650394 ps
CPU time 114.98 seconds
Started Aug 10 04:26:41 PM PDT 24
Finished Aug 10 04:28:36 PM PDT 24
Peak memory 206764 kb
Host smart-1a951c07-7b01-45aa-9b36-c329e25062b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403669693 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3403669693
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.609501042
Short name T129
Test name
Test status
Simulation time 53131309271 ps
CPU time 557.98 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:35:54 PM PDT 24
Peak memory 214292 kb
Host smart-22959801-f9e1-440a-bf25-9001548e2ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609501042 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.609501042
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.68439108
Short name T84
Test name
Test status
Simulation time 39981320578 ps
CPU time 257.16 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:31:03 PM PDT 24
Peak memory 206820 kb
Host smart-92c7bbd5-82b5-4ce4-a436-01be4ddc1729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68439108 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.68439108
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2684130649
Short name T145
Test name
Test status
Simulation time 47802422824 ps
CPU time 19.29 seconds
Started Aug 10 04:26:17 PM PDT 24
Finished Aug 10 04:26:37 PM PDT 24
Peak memory 191932 kb
Host smart-51b4335a-6985-4c15-963b-8de64e9e55b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684130649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2684130649
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1422357724
Short name T114
Test name
Test status
Simulation time 83302339590 ps
CPU time 58.96 seconds
Started Aug 10 04:27:01 PM PDT 24
Finished Aug 10 04:28:00 PM PDT 24
Peak memory 198264 kb
Host smart-57a716c0-959e-4301-ae2d-4218527929a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422357724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1422357724
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1755475942
Short name T164
Test name
Test status
Simulation time 120474648125 ps
CPU time 179.01 seconds
Started Aug 10 04:26:41 PM PDT 24
Finished Aug 10 04:29:40 PM PDT 24
Peak memory 184300 kb
Host smart-0c426dc1-5421-436c-ac22-5315702e18e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755475942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1755475942
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2628603026
Short name T163
Test name
Test status
Simulation time 409474715014 ps
CPU time 419.49 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:33:20 PM PDT 24
Peak memory 203028 kb
Host smart-5f03bd93-3533-4fa5-be20-2ce9533e5451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628603026 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2628603026
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1493770326
Short name T117
Test name
Test status
Simulation time 164032820028 ps
CPU time 250.33 seconds
Started Aug 10 04:26:45 PM PDT 24
Finished Aug 10 04:30:55 PM PDT 24
Peak memory 192304 kb
Host smart-3021bc53-4676-4070-8fa4-93b2bc28ab87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493770326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1493770326
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3931288802
Short name T126
Test name
Test status
Simulation time 55691082661 ps
CPU time 83.9 seconds
Started Aug 10 04:26:52 PM PDT 24
Finished Aug 10 04:28:16 PM PDT 24
Peak memory 192040 kb
Host smart-f2ad664b-0632-49b7-a3ee-cc1c7a0720e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931288802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3931288802
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3170025816
Short name T128
Test name
Test status
Simulation time 461194242 ps
CPU time 0.76 seconds
Started Aug 10 04:26:23 PM PDT 24
Finished Aug 10 04:26:24 PM PDT 24
Peak memory 196836 kb
Host smart-d0a5d783-4771-4a27-bb50-77e2155cec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170025816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3170025816
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4245426470
Short name T141
Test name
Test status
Simulation time 518160722 ps
CPU time 0.79 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:26:57 PM PDT 24
Peak memory 197012 kb
Host smart-05eec6e0-2cbf-49cd-8253-36b37ade8db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245426470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4245426470
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1145871277
Short name T95
Test name
Test status
Simulation time 421407852 ps
CPU time 1.19 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 196828 kb
Host smart-b3a193a6-96d8-4e2f-ba32-99b958ce8700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145871277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1145871277
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1631967091
Short name T97
Test name
Test status
Simulation time 25801362756 ps
CPU time 195.53 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:29:39 PM PDT 24
Peak memory 198632 kb
Host smart-d3e348f8-c636-4eeb-8d03-2e13ed9e9192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631967091 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1631967091
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3792353295
Short name T45
Test name
Test status
Simulation time 508918590 ps
CPU time 0.72 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:26:22 PM PDT 24
Peak memory 196764 kb
Host smart-eda5fd16-0b64-4c2e-baac-084d4c56f980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792353295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3792353295
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1360225312
Short name T136
Test name
Test status
Simulation time 492905056 ps
CPU time 0.73 seconds
Started Aug 10 04:26:07 PM PDT 24
Finished Aug 10 04:26:07 PM PDT 24
Peak memory 196720 kb
Host smart-825f0d10-01af-4175-ab5a-a8ccac4e50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360225312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1360225312
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.67480191
Short name T91
Test name
Test status
Simulation time 437703000 ps
CPU time 1.03 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:35 PM PDT 24
Peak memory 196864 kb
Host smart-22c19cda-b3b8-46ff-8db3-8aa2765c3570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67480191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.67480191
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.837534786
Short name T152
Test name
Test status
Simulation time 125045023101 ps
CPU time 41.84 seconds
Started Aug 10 04:26:47 PM PDT 24
Finished Aug 10 04:27:29 PM PDT 24
Peak memory 192012 kb
Host smart-e69bbf0d-3fbf-4eca-b84f-7a6e73829b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837534786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.837534786
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3757917314
Short name T130
Test name
Test status
Simulation time 381779811061 ps
CPU time 150.33 seconds
Started Aug 10 04:27:09 PM PDT 24
Finished Aug 10 04:29:39 PM PDT 24
Peak memory 192040 kb
Host smart-f5e0876f-05f5-4c62-8ab3-e6fc57add3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757917314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3757917314
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.97954571
Short name T123
Test name
Test status
Simulation time 577096166 ps
CPU time 0.74 seconds
Started Aug 10 04:26:05 PM PDT 24
Finished Aug 10 04:26:06 PM PDT 24
Peak memory 196828 kb
Host smart-b9a8e284-f59b-43fa-a97a-8a044305ec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97954571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.97954571
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2891724749
Short name T158
Test name
Test status
Simulation time 353623074 ps
CPU time 0.84 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:26:47 PM PDT 24
Peak memory 196836 kb
Host smart-898190f0-674b-425c-bdb5-468b8b73eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891724749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2891724749
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1987065686
Short name T98
Test name
Test status
Simulation time 282421907292 ps
CPU time 202.62 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:30:12 PM PDT 24
Peak memory 198340 kb
Host smart-e1586134-5dbd-4a1d-8fcd-69b69245ad81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987065686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1987065686
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3632241523
Short name T138
Test name
Test status
Simulation time 208073664706 ps
CPU time 532.43 seconds
Started Aug 10 04:26:39 PM PDT 24
Finished Aug 10 04:35:32 PM PDT 24
Peak memory 213432 kb
Host smart-2540f2ab-8aa7-41ed-a916-f1b0e3c727fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632241523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3632241523
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1040332334
Short name T166
Test name
Test status
Simulation time 609309320072 ps
CPU time 209.54 seconds
Started Aug 10 04:26:41 PM PDT 24
Finished Aug 10 04:30:11 PM PDT 24
Peak memory 191928 kb
Host smart-1e45cd7b-05e6-485c-bba6-71c4ab4f82c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040332334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1040332334
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.609524903
Short name T133
Test name
Test status
Simulation time 435777135 ps
CPU time 1.25 seconds
Started Aug 10 04:26:54 PM PDT 24
Finished Aug 10 04:26:55 PM PDT 24
Peak memory 196724 kb
Host smart-24628b08-8469-44b8-8a49-a3937edeaaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609524903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.609524903
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2888008690
Short name T119
Test name
Test status
Simulation time 93980443806 ps
CPU time 32.27 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:27:29 PM PDT 24
Peak memory 198364 kb
Host smart-b2673586-e4ef-4748-9f41-5bd5e3a03e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888008690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2888008690
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.450616731
Short name T2
Test name
Test status
Simulation time 71667410792 ps
CPU time 109.24 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:28:47 PM PDT 24
Peak memory 191992 kb
Host smart-4961ca74-c9ac-452f-976f-9c49a4e335c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450616731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.450616731
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2681597022
Short name T108
Test name
Test status
Simulation time 104498963801 ps
CPU time 961.25 seconds
Started Aug 10 04:26:26 PM PDT 24
Finished Aug 10 04:42:27 PM PDT 24
Peak memory 215024 kb
Host smart-ea1df9ac-22d2-46af-abe3-82f533054cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681597022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2681597022
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3858744268
Short name T144
Test name
Test status
Simulation time 557774950 ps
CPU time 1.28 seconds
Started Aug 10 04:26:27 PM PDT 24
Finished Aug 10 04:26:28 PM PDT 24
Peak memory 196752 kb
Host smart-38b00a13-64b0-4344-a97a-b3a0bfece96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858744268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3858744268
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2929593645
Short name T139
Test name
Test status
Simulation time 54058071207 ps
CPU time 34.46 seconds
Started Aug 10 04:26:17 PM PDT 24
Finished Aug 10 04:26:52 PM PDT 24
Peak memory 191956 kb
Host smart-6816b8cf-04e8-40d0-b0f5-72cf8a6265d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929593645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2929593645
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.591025309
Short name T140
Test name
Test status
Simulation time 71490925703 ps
CPU time 21.31 seconds
Started Aug 10 04:26:29 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 198324 kb
Host smart-1afba44f-f3a7-4104-8a52-ac3d404ad7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591025309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.591025309
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4161976802
Short name T146
Test name
Test status
Simulation time 98433630320 ps
CPU time 69.82 seconds
Started Aug 10 04:26:04 PM PDT 24
Finished Aug 10 04:27:14 PM PDT 24
Peak memory 184384 kb
Host smart-0bc4623e-573a-409a-ab6d-d8513c11f50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161976802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4161976802
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.865547676
Short name T157
Test name
Test status
Simulation time 36247962912 ps
CPU time 13.96 seconds
Started Aug 10 04:26:36 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 193068 kb
Host smart-acdcf346-66e6-489f-ae7e-402d4e5a059a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865547676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.865547676
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1498329343
Short name T115
Test name
Test status
Simulation time 140230745881 ps
CPU time 186.25 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:30:07 PM PDT 24
Peak memory 191988 kb
Host smart-404f44eb-84fc-45ed-aa81-d6f193795deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498329343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1498329343
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1667289065
Short name T86
Test name
Test status
Simulation time 63454420954 ps
CPU time 119.63 seconds
Started Aug 10 04:26:45 PM PDT 24
Finished Aug 10 04:28:45 PM PDT 24
Peak memory 198620 kb
Host smart-380ae19b-8f0d-4753-87fe-771b09f4cb41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667289065 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1667289065
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1586194270
Short name T137
Test name
Test status
Simulation time 511091867 ps
CPU time 0.99 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:26:47 PM PDT 24
Peak memory 196744 kb
Host smart-42d72ce4-a462-43dd-9159-2a15b73c9de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586194270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1586194270
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2119046944
Short name T150
Test name
Test status
Simulation time 595162409 ps
CPU time 0.69 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 196740 kb
Host smart-3ef2ba99-b58f-4ca8-aa6d-82dc7235786e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119046944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2119046944
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3142082533
Short name T93
Test name
Test status
Simulation time 73455352892 ps
CPU time 26.97 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:27:13 PM PDT 24
Peak memory 192028 kb
Host smart-f0e49cd0-f447-4b20-a365-c145a9e02aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142082533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3142082533
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.794489261
Short name T120
Test name
Test status
Simulation time 490039471 ps
CPU time 0.79 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 196848 kb
Host smart-bb45b818-bd5d-4324-ab62-ce8c23d5b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794489261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.794489261
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.379505537
Short name T32
Test name
Test status
Simulation time 25968638034 ps
CPU time 137.49 seconds
Started Aug 10 04:27:10 PM PDT 24
Finished Aug 10 04:29:28 PM PDT 24
Peak memory 198680 kb
Host smart-b399aa29-d6a0-405c-9d18-3e3c96e29aba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379505537 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.379505537
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2621840955
Short name T100
Test name
Test status
Simulation time 421538994 ps
CPU time 1.14 seconds
Started Aug 10 04:26:11 PM PDT 24
Finished Aug 10 04:26:12 PM PDT 24
Peak memory 196688 kb
Host smart-784a3a51-4615-4714-a78d-a056f75fbd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621840955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2621840955
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2237466732
Short name T101
Test name
Test status
Simulation time 525788069 ps
CPU time 0.72 seconds
Started Aug 10 04:26:17 PM PDT 24
Finished Aug 10 04:26:18 PM PDT 24
Peak memory 196848 kb
Host smart-e9b9ba11-f3bd-4522-ad29-5159df64aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237466732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2237466732
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.4029922028
Short name T37
Test name
Test status
Simulation time 536090503 ps
CPU time 0.77 seconds
Started Aug 10 04:26:23 PM PDT 24
Finished Aug 10 04:26:24 PM PDT 24
Peak memory 196808 kb
Host smart-d784326a-8be0-4523-a195-35f6da83b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029922028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4029922028
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2664173989
Short name T23
Test name
Test status
Simulation time 445034729 ps
CPU time 0.91 seconds
Started Aug 10 04:26:33 PM PDT 24
Finished Aug 10 04:26:34 PM PDT 24
Peak memory 196800 kb
Host smart-f2ce1dcc-9902-481f-a1fd-4e2484785b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664173989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2664173989
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3674813764
Short name T43
Test name
Test status
Simulation time 413392735 ps
CPU time 0.9 seconds
Started Aug 10 04:26:22 PM PDT 24
Finished Aug 10 04:26:23 PM PDT 24
Peak memory 196764 kb
Host smart-98ce4288-a971-4c74-8a29-4bbf6ccd8154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674813764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3674813764
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4159829837
Short name T153
Test name
Test status
Simulation time 578688103 ps
CPU time 0.76 seconds
Started Aug 10 04:26:44 PM PDT 24
Finished Aug 10 04:26:45 PM PDT 24
Peak memory 196760 kb
Host smart-8c904250-daa5-4d67-85d8-0caec95b645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159829837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4159829837
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4126120927
Short name T122
Test name
Test status
Simulation time 732768262 ps
CPU time 0.63 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:26:59 PM PDT 24
Peak memory 196720 kb
Host smart-545dcfc9-f751-477c-b40d-ab4641783195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126120927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4126120927
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3600032918
Short name T92
Test name
Test status
Simulation time 227157262536 ps
CPU time 132.49 seconds
Started Aug 10 04:26:52 PM PDT 24
Finished Aug 10 04:29:05 PM PDT 24
Peak memory 192088 kb
Host smart-e81cdafc-99fb-492f-9aaf-3a9c1c352e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600032918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3600032918
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1081724281
Short name T177
Test name
Test status
Simulation time 170617195207 ps
CPU time 250 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:30:53 PM PDT 24
Peak memory 193060 kb
Host smart-1de24f2c-601a-4ae3-8d5c-0effe94601d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081724281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1081724281
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.695576334
Short name T134
Test name
Test status
Simulation time 32185798272 ps
CPU time 208.84 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 04:30:22 PM PDT 24
Peak memory 206824 kb
Host smart-2f3bacb4-9e41-474f-a006-8a33943188e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695576334 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.695576334
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3363565803
Short name T165
Test name
Test status
Simulation time 70245491167 ps
CPU time 293.95 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:31:53 PM PDT 24
Peak memory 206796 kb
Host smart-60c9964d-47f5-4a86-97cd-2df5f9fa0ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363565803 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3363565803
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.798202587
Short name T96
Test name
Test status
Simulation time 88838615674 ps
CPU time 180.63 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 04:29:54 PM PDT 24
Peak memory 200016 kb
Host smart-ecd4791a-6896-4597-bacf-c0915c9203f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798202587 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.798202587
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3592010909
Short name T171
Test name
Test status
Simulation time 212426174135 ps
CPU time 141.03 seconds
Started Aug 10 04:26:30 PM PDT 24
Finished Aug 10 04:28:51 PM PDT 24
Peak memory 193076 kb
Host smart-6a7fb324-31f0-460d-926f-5ad198e84c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592010909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3592010909
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.551638852
Short name T183
Test name
Test status
Simulation time 532653712 ps
CPU time 0.79 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 196724 kb
Host smart-5de89003-9cd2-4dda-aeef-65e957d41a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551638852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.551638852
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3935663991
Short name T188
Test name
Test status
Simulation time 361062443 ps
CPU time 0.83 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196716 kb
Host smart-e203c588-641e-437e-8313-56b445b5b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935663991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3935663991
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1486171955
Short name T78
Test name
Test status
Simulation time 19169650427 ps
CPU time 174.14 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:29:25 PM PDT 24
Peak memory 198784 kb
Host smart-8c706ea4-45fa-40f4-8373-503f652a1f51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486171955 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1486171955
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2265520774
Short name T160
Test name
Test status
Simulation time 431721958 ps
CPU time 0.74 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 196828 kb
Host smart-b84edd96-56d9-493a-8205-0ee88db95e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265520774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2265520774
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.746909083
Short name T155
Test name
Test status
Simulation time 443488117 ps
CPU time 0.71 seconds
Started Aug 10 04:26:41 PM PDT 24
Finished Aug 10 04:26:42 PM PDT 24
Peak memory 196764 kb
Host smart-2be57cee-f4ed-4eb1-953f-6a8080308f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746909083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.746909083
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3539045976
Short name T182
Test name
Test status
Simulation time 485956836 ps
CPU time 0.8 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:26:44 PM PDT 24
Peak memory 196740 kb
Host smart-da4dad29-ddc8-4590-be52-0dff8706b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539045976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3539045976
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.655046624
Short name T149
Test name
Test status
Simulation time 399277114 ps
CPU time 0.74 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 04:26:54 PM PDT 24
Peak memory 197012 kb
Host smart-6bcad567-3692-4a7c-933c-4211ec205455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655046624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.655046624
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3833013209
Short name T116
Test name
Test status
Simulation time 576167575 ps
CPU time 0.65 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 04:27:08 PM PDT 24
Peak memory 196884 kb
Host smart-0adae42f-8eb7-4127-aa74-a732c19eeb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833013209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3833013209
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2905973684
Short name T38
Test name
Test status
Simulation time 583399111 ps
CPU time 0.8 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 196760 kb
Host smart-64dd4ebe-5efd-4bf1-a99d-b5bfdfebf0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905973684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2905973684
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3487225251
Short name T178
Test name
Test status
Simulation time 456312729 ps
CPU time 0.66 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:26:59 PM PDT 24
Peak memory 196736 kb
Host smart-3c2751ea-dc9a-4a11-b151-4e85d9034dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487225251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3487225251
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2721830979
Short name T175
Test name
Test status
Simulation time 493171076 ps
CPU time 1.35 seconds
Started Aug 10 04:26:08 PM PDT 24
Finished Aug 10 04:26:10 PM PDT 24
Peak memory 196716 kb
Host smart-a5739eb5-6839-43de-a885-6fd5fb75eb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721830979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2721830979
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3866793367
Short name T173
Test name
Test status
Simulation time 55848075159 ps
CPU time 290 seconds
Started Aug 10 04:26:19 PM PDT 24
Finished Aug 10 04:31:09 PM PDT 24
Peak memory 207916 kb
Host smart-b6b18726-00c8-4128-9527-a797b466e533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866793367 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3866793367
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.698580477
Short name T46
Test name
Test status
Simulation time 365239190 ps
CPU time 1.18 seconds
Started Aug 10 04:26:16 PM PDT 24
Finished Aug 10 04:26:18 PM PDT 24
Peak memory 196808 kb
Host smart-cc185cd9-3b83-4903-86da-802245bc5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698580477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.698580477
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.684905118
Short name T169
Test name
Test status
Simulation time 445973646 ps
CPU time 1.15 seconds
Started Aug 10 04:26:18 PM PDT 24
Finished Aug 10 04:26:19 PM PDT 24
Peak memory 196832 kb
Host smart-3116b56d-86e8-4dcd-ad13-14bbfb853764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684905118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.684905118
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2550123303
Short name T181
Test name
Test status
Simulation time 674335985 ps
CPU time 0.65 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 196668 kb
Host smart-96a04874-837a-4ede-8427-20780406126c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550123303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2550123303
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2655401890
Short name T167
Test name
Test status
Simulation time 514581215 ps
CPU time 1.12 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 196724 kb
Host smart-4794ca10-2172-45c5-9e81-68fc81b577cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655401890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2655401890
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3422693932
Short name T172
Test name
Test status
Simulation time 536534370 ps
CPU time 0.67 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:26:39 PM PDT 24
Peak memory 196820 kb
Host smart-8572652c-9818-4c18-81e3-ea5ad90586d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422693932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3422693932
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.484175892
Short name T187
Test name
Test status
Simulation time 532546392 ps
CPU time 0.63 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:26:44 PM PDT 24
Peak memory 196812 kb
Host smart-5d618b05-e272-41a3-887b-b2aee684c904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484175892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.484175892
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2223643976
Short name T184
Test name
Test status
Simulation time 505173276 ps
CPU time 0.88 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:35 PM PDT 24
Peak memory 196680 kb
Host smart-6092eefa-c9fd-4b01-9219-414842491709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223643976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2223643976
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.646752034
Short name T87
Test name
Test status
Simulation time 75748547769 ps
CPU time 574.41 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:36:30 PM PDT 24
Peak memory 211544 kb
Host smart-9d277076-f8c3-44fb-b99b-b9db03b0956c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646752034 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.646752034
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4026792127
Short name T186
Test name
Test status
Simulation time 410540566 ps
CPU time 1.21 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:26:57 PM PDT 24
Peak memory 196688 kb
Host smart-7a93f0fe-bec8-4a08-994c-280e9cf8caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026792127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4026792127
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2485125178
Short name T131
Test name
Test status
Simulation time 492483111 ps
CPU time 0.72 seconds
Started Aug 10 04:26:23 PM PDT 24
Finished Aug 10 04:26:24 PM PDT 24
Peak memory 196808 kb
Host smart-292a6e46-78bf-4d55-a0e4-5f8d5b9099e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485125178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2485125178
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.798916704
Short name T174
Test name
Test status
Simulation time 406669964 ps
CPU time 0.66 seconds
Started Aug 10 04:26:30 PM PDT 24
Finished Aug 10 04:26:31 PM PDT 24
Peak memory 196840 kb
Host smart-23c5403d-e389-41ce-94a0-8c46ee0b1fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798916704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.798916704
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2519361408
Short name T192
Test name
Test status
Simulation time 4480734491 ps
CPU time 2.68 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 197972 kb
Host smart-e0a44763-b05b-462c-8113-e74126e76f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519361408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2519361408
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2845313040
Short name T5
Test name
Test status
Simulation time 634162061 ps
CPU time 0.7 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196808 kb
Host smart-f0ca2edc-5dff-46da-9a34-aabd1faee865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845313040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2845313040
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2629653345
Short name T79
Test name
Test status
Simulation time 139331811753 ps
CPU time 340.64 seconds
Started Aug 10 04:26:10 PM PDT 24
Finished Aug 10 04:31:51 PM PDT 24
Peak memory 214020 kb
Host smart-a3838c26-7c9a-49db-97eb-1cdeef658f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629653345 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2629653345
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2232258239
Short name T185
Test name
Test status
Simulation time 362445988 ps
CPU time 0.82 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:32 PM PDT 24
Peak memory 196564 kb
Host smart-27b2c498-ddf4-407f-8a1b-84adaa2ffeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232258239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2232258239
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2634097444
Short name T44
Test name
Test status
Simulation time 405927016 ps
CPU time 0.87 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 196856 kb
Host smart-79394d29-0548-4739-a0b0-46cf245eff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634097444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2634097444
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1621917694
Short name T11
Test name
Test status
Simulation time 447632738 ps
CPU time 1.2 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 196652 kb
Host smart-a9a42936-70d5-4c1f-ab83-b158272766f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621917694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1621917694
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3039854174
Short name T170
Test name
Test status
Simulation time 478165730 ps
CPU time 1.2 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 196744 kb
Host smart-40dc2393-c8b0-4b93-b013-faad90aff03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039854174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3039854174
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.774201104
Short name T331
Test name
Test status
Simulation time 524570981 ps
CPU time 1.4 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 194536 kb
Host smart-ef33149d-5255-42e4-a7ea-17a978c4eb83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774201104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.774201104
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.108178592
Short name T310
Test name
Test status
Simulation time 6946382756 ps
CPU time 3.7 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:29 PM PDT 24
Peak memory 192192 kb
Host smart-1cffabbc-f525-4953-b6f1-bf0e25fc3a6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108178592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.108178592
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3382729307
Short name T402
Test name
Test status
Simulation time 818024365 ps
CPU time 0.69 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 192912 kb
Host smart-3cdb899f-88bc-4a84-8aee-3bf0ab006591
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382729307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3382729307
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1711222402
Short name T380
Test name
Test status
Simulation time 397181951 ps
CPU time 1.09 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 198352 kb
Host smart-6e0c8794-df44-4948-94e6-62276c6ac7a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711222402 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1711222402
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3904234766
Short name T395
Test name
Test status
Simulation time 428354912 ps
CPU time 1.19 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 193156 kb
Host smart-b8afcc82-94ea-44ba-8b4d-a8f3c53f4be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904234766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3904234766
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.478692226
Short name T346
Test name
Test status
Simulation time 418191860 ps
CPU time 1.15 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 183624 kb
Host smart-154f9676-647c-43aa-8c31-c0dbf94d52ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478692226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.478692226
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1288488003
Short name T308
Test name
Test status
Simulation time 272262291 ps
CPU time 0.96 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:25 PM PDT 24
Peak memory 183580 kb
Host smart-53d17761-d249-42f9-b960-833c10ecb3bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288488003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1288488003
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.785091047
Short name T286
Test name
Test status
Simulation time 343627216 ps
CPU time 0.9 seconds
Started Aug 10 04:41:28 PM PDT 24
Finished Aug 10 04:41:29 PM PDT 24
Peak memory 183620 kb
Host smart-3f46016b-abec-4fdf-89d7-24bd5c3834c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785091047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.785091047
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1845364536
Short name T408
Test name
Test status
Simulation time 2400195216 ps
CPU time 3.24 seconds
Started Aug 10 04:41:23 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 195140 kb
Host smart-ca515590-06ae-4dab-9e68-aee6e66edb5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845364536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1845364536
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3055478082
Short name T298
Test name
Test status
Simulation time 560439018 ps
CPU time 1.49 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:28 PM PDT 24
Peak memory 198500 kb
Host smart-641be7cb-ba2c-4109-bc58-70ca2433259b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055478082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3055478082
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1477213634
Short name T326
Test name
Test status
Simulation time 8847553962 ps
CPU time 12.49 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 198352 kb
Host smart-9eddb00f-f24f-4e17-bd42-b26e8e4f183c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477213634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1477213634
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4227256852
Short name T55
Test name
Test status
Simulation time 805409786 ps
CPU time 0.81 seconds
Started Aug 10 04:41:27 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 183912 kb
Host smart-4e69e890-5b06-4700-bd84-53ef576f37e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227256852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4227256852
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3644397000
Short name T62
Test name
Test status
Simulation time 6948700597 ps
CPU time 4.8 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:30 PM PDT 24
Peak memory 195652 kb
Host smart-9271c827-842f-41c8-aa33-00dfc13b51e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644397000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3644397000
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3299187714
Short name T397
Test name
Test status
Simulation time 1296621072 ps
CPU time 1.62 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 192964 kb
Host smart-435f8c3c-997c-4d78-abce-351e50767aa9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299187714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3299187714
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3843552985
Short name T386
Test name
Test status
Simulation time 368855411 ps
CPU time 1.09 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:25 PM PDT 24
Peak memory 195252 kb
Host smart-2c535ac3-6a3a-4c56-b739-a86f3c489963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843552985 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3843552985
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3866794513
Short name T57
Test name
Test status
Simulation time 445482613 ps
CPU time 1.23 seconds
Started Aug 10 04:41:23 PM PDT 24
Finished Aug 10 04:41:25 PM PDT 24
Peak memory 192096 kb
Host smart-2d352891-9e18-49bd-9693-e59df35b2019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866794513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3866794513
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1788603855
Short name T334
Test name
Test status
Simulation time 412106053 ps
CPU time 1.05 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 183668 kb
Host smart-4f3be975-a807-4c6f-8b9d-dd0473b611b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788603855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1788603855
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3418369962
Short name T389
Test name
Test status
Simulation time 443999463 ps
CPU time 0.68 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 183592 kb
Host smart-0c28e965-fd08-4683-9d4a-831e73c70931
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418369962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3418369962
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1421058360
Short name T345
Test name
Test status
Simulation time 480610202 ps
CPU time 1.16 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 183644 kb
Host smart-5a8bb7cc-9a09-4b09-967e-88aa34eb8a4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421058360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1421058360
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3462978748
Short name T328
Test name
Test status
Simulation time 2390434582 ps
CPU time 2.72 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 184064 kb
Host smart-5749bed1-a156-4bbe-8bd6-4cb3a741eb00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462978748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3462978748
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2943667018
Short name T284
Test name
Test status
Simulation time 724391938 ps
CPU time 2.17 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 198504 kb
Host smart-a6962e24-524d-40d7-9dd7-3143a570f199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943667018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2943667018
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1422954003
Short name T291
Test name
Test status
Simulation time 491946013 ps
CPU time 0.85 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 197216 kb
Host smart-2b818ad5-5f1a-49b7-a526-053b0da49b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422954003 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1422954003
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4118416751
Short name T66
Test name
Test status
Simulation time 521051149 ps
CPU time 0.93 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 193268 kb
Host smart-2c0fdf14-9d3b-4da8-8638-3bf961a76e01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118416751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4118416751
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.427137152
Short name T337
Test name
Test status
Simulation time 330655147 ps
CPU time 0.67 seconds
Started Aug 10 04:41:40 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 192920 kb
Host smart-588b9963-5ebd-49b8-8194-ca4c1463783a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427137152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.427137152
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.411235459
Short name T407
Test name
Test status
Simulation time 1288116286 ps
CPU time 2.99 seconds
Started Aug 10 04:41:39 PM PDT 24
Finished Aug 10 04:41:42 PM PDT 24
Peak memory 183928 kb
Host smart-b51c48b4-d98a-445a-a826-b68650619a47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411235459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.411235459
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3382970119
Short name T369
Test name
Test status
Simulation time 476837181 ps
CPU time 1.72 seconds
Started Aug 10 04:41:39 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 198508 kb
Host smart-d34afe91-bddf-43c1-89de-e751b2d827de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382970119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3382970119
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4123468096
Short name T400
Test name
Test status
Simulation time 4291206109 ps
CPU time 7.2 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 197476 kb
Host smart-5bd12a25-7624-4d21-9bea-bc85d8491d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123468096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.4123468096
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4046519978
Short name T313
Test name
Test status
Simulation time 420907276 ps
CPU time 1.1 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 196164 kb
Host smart-b3b0d518-a8e8-4cf3-9089-267f1a84d20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046519978 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4046519978
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2103021946
Short name T306
Test name
Test status
Simulation time 447808950 ps
CPU time 1.15 seconds
Started Aug 10 04:41:48 PM PDT 24
Finished Aug 10 04:41:49 PM PDT 24
Peak memory 183620 kb
Host smart-4c59813c-316e-4ec4-9390-4c3d7d30cac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103021946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2103021946
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2400831320
Short name T330
Test name
Test status
Simulation time 1037907980 ps
CPU time 0.94 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 192832 kb
Host smart-fde761be-d9fe-470b-ae45-92dab12fedbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400831320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2400831320
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3329988053
Short name T320
Test name
Test status
Simulation time 689044343 ps
CPU time 1.3 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 198428 kb
Host smart-915e4b4b-19ff-4122-bbd9-6676635e3dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329988053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3329988053
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1726017117
Short name T312
Test name
Test status
Simulation time 4255675364 ps
CPU time 2.49 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 196844 kb
Host smart-6c3c988e-86a0-4e97-8b36-44816f7356e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726017117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1726017117
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3275500611
Short name T364
Test name
Test status
Simulation time 328328443 ps
CPU time 0.94 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 195932 kb
Host smart-8b8e97b5-87ac-4fd0-b8d9-aa5a497d45ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275500611 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3275500611
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2179876715
Short name T414
Test name
Test status
Simulation time 510110296 ps
CPU time 0.78 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 193996 kb
Host smart-e9f168ee-7089-4e71-bde5-e4cdba17b324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179876715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2179876715
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2478016530
Short name T289
Test name
Test status
Simulation time 469579689 ps
CPU time 1.11 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 183684 kb
Host smart-50fe7c12-0ca8-4f0a-b06f-7d76b8d713fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478016530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2478016530
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.513819994
Short name T413
Test name
Test status
Simulation time 1480430184 ps
CPU time 1.17 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 193188 kb
Host smart-52e325a5-1439-446c-872d-c5be70d32f9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513819994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.513819994
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2306427077
Short name T374
Test name
Test status
Simulation time 443771876 ps
CPU time 2.47 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 198428 kb
Host smart-859f4ea6-a9c3-468c-9ec9-f6d4cc4c679c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306427077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2306427077
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1028950075
Short name T379
Test name
Test status
Simulation time 4211717148 ps
CPU time 1.93 seconds
Started Aug 10 04:41:43 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 196832 kb
Host smart-c41f1879-57d6-42ee-b2d0-b789eda46fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028950075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1028950075
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2740938646
Short name T317
Test name
Test status
Simulation time 390191167 ps
CPU time 1.31 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:49 PM PDT 24
Peak memory 197308 kb
Host smart-fdd04e83-f30b-405a-a2d7-bdc21e663c6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740938646 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2740938646
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.680169225
Short name T64
Test name
Test status
Simulation time 571793961 ps
CPU time 0.63 seconds
Started Aug 10 04:41:48 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 193852 kb
Host smart-7fe5a157-7d2a-4a04-b984-4b9afe5d43a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680169225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.680169225
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1998953317
Short name T318
Test name
Test status
Simulation time 513066758 ps
CPU time 0.6 seconds
Started Aug 10 04:41:50 PM PDT 24
Finished Aug 10 04:41:51 PM PDT 24
Peak memory 183776 kb
Host smart-83d79476-bbfa-4a70-956b-a26eb7df6a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998953317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1998953317
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.923901267
Short name T69
Test name
Test status
Simulation time 1374749925 ps
CPU time 3.01 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:49 PM PDT 24
Peak memory 183704 kb
Host smart-bd975532-8626-45e5-98d5-9a41cb4ac5b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923901267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.923901267
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1010330152
Short name T390
Test name
Test status
Simulation time 747554478 ps
CPU time 3 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 198496 kb
Host smart-bfe2cba0-e602-4124-bc23-48c6ee106a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010330152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1010330152
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.824152715
Short name T195
Test name
Test status
Simulation time 4592811485 ps
CPU time 2.62 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:50 PM PDT 24
Peak memory 197616 kb
Host smart-c4973ab9-dfe1-4bbe-b2d2-f99d652180df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824152715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.824152715
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3743929297
Short name T325
Test name
Test status
Simulation time 555897778 ps
CPU time 1.03 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 198296 kb
Host smart-dfe0837b-33ca-4711-bb37-4c1cf6c973de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743929297 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3743929297
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4004475352
Short name T341
Test name
Test status
Simulation time 336909489 ps
CPU time 0.64 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 191912 kb
Host smart-0e507e15-8f7b-4a1d-bf75-47fd8876b6d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004475352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4004475352
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1659208604
Short name T301
Test name
Test status
Simulation time 405346879 ps
CPU time 0.8 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 183768 kb
Host smart-d970cc13-bb54-4c36-a06b-fe077a372cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659208604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1659208604
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1304820035
Short name T68
Test name
Test status
Simulation time 1296445459 ps
CPU time 2.4 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 194036 kb
Host smart-f81d341b-5b76-4cce-9fb7-77b5a866a9ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304820035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1304820035
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.866168372
Short name T415
Test name
Test status
Simulation time 490346670 ps
CPU time 1.81 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 198408 kb
Host smart-a54ce0cf-3eb0-4de1-9a1f-671cb1c0b427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866168372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.866168372
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3913536162
Short name T348
Test name
Test status
Simulation time 4876743334 ps
CPU time 2.36 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 197968 kb
Host smart-daddb3ff-dda5-4cfc-aa8e-1f995705e776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913536162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3913536162
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1625047171
Short name T323
Test name
Test status
Simulation time 498971930 ps
CPU time 0.87 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 195920 kb
Host smart-c480c03e-b63a-46f2-8466-b6cde10b7c46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625047171 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1625047171
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1293702619
Short name T63
Test name
Test status
Simulation time 546212649 ps
CPU time 1.41 seconds
Started Aug 10 04:41:47 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 193440 kb
Host smart-a3bdcef8-457b-4580-844d-54e99b070867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293702619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1293702619
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.186562755
Short name T412
Test name
Test status
Simulation time 293224720 ps
CPU time 0.65 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 183712 kb
Host smart-c12e2c4f-a15e-44b1-a119-f9bc0126be09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186562755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.186562755
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3746102992
Short name T340
Test name
Test status
Simulation time 884871301 ps
CPU time 0.95 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 192900 kb
Host smart-73b72b1f-d19c-42a8-9ac7-852be6ae5ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746102992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3746102992
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1036502102
Short name T375
Test name
Test status
Simulation time 492352828 ps
CPU time 1.61 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 198636 kb
Host smart-80005ea3-8810-4af2-bc37-34d8b70fd75c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036502102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1036502102
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.495121526
Short name T383
Test name
Test status
Simulation time 467522002 ps
CPU time 0.99 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 198304 kb
Host smart-05be9c12-df7d-4bd4-9747-5668c9f9b4e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495121526 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.495121526
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3540763230
Short name T58
Test name
Test status
Simulation time 506095756 ps
CPU time 0.95 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 191896 kb
Host smart-d3af1f96-89a7-4b9b-a619-56483a24c109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540763230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3540763230
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2486630071
Short name T422
Test name
Test status
Simulation time 514334514 ps
CPU time 0.98 seconds
Started Aug 10 04:41:50 PM PDT 24
Finished Aug 10 04:41:51 PM PDT 24
Peak memory 192996 kb
Host smart-45e71057-4cd6-4e56-a72b-f67dd4c0ce3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486630071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2486630071
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1112127331
Short name T329
Test name
Test status
Simulation time 2468423195 ps
CPU time 3.68 seconds
Started Aug 10 04:41:50 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 195072 kb
Host smart-9d2c6ff5-658a-4abd-b21f-5e8a0b98650b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112127331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1112127331
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1565958336
Short name T365
Test name
Test status
Simulation time 876695617 ps
CPU time 2.43 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 198536 kb
Host smart-4db0a8ad-21a4-4985-a152-c94135b8d4a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565958336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1565958336
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2079793160
Short name T411
Test name
Test status
Simulation time 8454622905 ps
CPU time 6.89 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:53 PM PDT 24
Peak memory 198348 kb
Host smart-8e2e650f-82cb-489d-b264-35f97f86e916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079793160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2079793160
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3995393344
Short name T201
Test name
Test status
Simulation time 438786590 ps
CPU time 1.29 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 195824 kb
Host smart-59789f9c-ec9c-4831-ab08-31cb1c506f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995393344 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3995393344
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2584761125
Short name T30
Test name
Test status
Simulation time 452401787 ps
CPU time 0.84 seconds
Started Aug 10 04:41:44 PM PDT 24
Finished Aug 10 04:41:45 PM PDT 24
Peak memory 192960 kb
Host smart-822d9a61-c909-4f3a-9709-e3d9f1990d61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584761125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2584761125
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3460008574
Short name T309
Test name
Test status
Simulation time 393338421 ps
CPU time 1.13 seconds
Started Aug 10 04:41:42 PM PDT 24
Finished Aug 10 04:41:43 PM PDT 24
Peak memory 183684 kb
Host smart-82f45af9-327e-4950-addc-8790c69fe900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460008574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3460008574
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3990524542
Short name T409
Test name
Test status
Simulation time 1803108115 ps
CPU time 1.27 seconds
Started Aug 10 04:41:50 PM PDT 24
Finished Aug 10 04:41:51 PM PDT 24
Peak memory 193780 kb
Host smart-1d526c88-734e-4106-bbcb-1387c5258030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990524542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3990524542
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2657720593
Short name T297
Test name
Test status
Simulation time 588438694 ps
CPU time 1.81 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 198624 kb
Host smart-33f35165-8b03-442f-ad22-0d3ba4971f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657720593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2657720593
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3944105861
Short name T370
Test name
Test status
Simulation time 8310697861 ps
CPU time 13.32 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:59 PM PDT 24
Peak memory 198292 kb
Host smart-b2e2bd3f-4b1f-4b2d-8c1a-14e6594a4379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944105861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3944105861
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2122921819
Short name T296
Test name
Test status
Simulation time 536839849 ps
CPU time 0.91 seconds
Started Aug 10 04:41:43 PM PDT 24
Finished Aug 10 04:41:44 PM PDT 24
Peak memory 196084 kb
Host smart-7b12a67e-3577-42f9-ad97-0687d92a0d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122921819 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2122921819
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1796401883
Short name T393
Test name
Test status
Simulation time 482139840 ps
CPU time 1.3 seconds
Started Aug 10 04:41:50 PM PDT 24
Finished Aug 10 04:41:52 PM PDT 24
Peak memory 192984 kb
Host smart-c2146117-d3ec-4345-b590-b5e9e758b4d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796401883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1796401883
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1869482012
Short name T321
Test name
Test status
Simulation time 310966506 ps
CPU time 0.58 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:47 PM PDT 24
Peak memory 192932 kb
Host smart-200f08dd-0f34-431e-a3f0-bd8ece946453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869482012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1869482012
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3319387418
Short name T67
Test name
Test status
Simulation time 2030630452 ps
CPU time 2.75 seconds
Started Aug 10 04:41:45 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 191840 kb
Host smart-64838e0f-b076-4d33-8dec-ae91d79fdefb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319387418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3319387418
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2895337092
Short name T335
Test name
Test status
Simulation time 315749034 ps
CPU time 1.3 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 198548 kb
Host smart-e3671aa7-d405-4de3-83ed-97482981173b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895337092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2895337092
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3814381501
Short name T419
Test name
Test status
Simulation time 8142479584 ps
CPU time 12.89 seconds
Started Aug 10 04:41:46 PM PDT 24
Finished Aug 10 04:41:59 PM PDT 24
Peak memory 198232 kb
Host smart-27c053a4-1b42-4e7b-a43e-6578e2b2aa5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814381501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3814381501
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.656898830
Short name T287
Test name
Test status
Simulation time 372966283 ps
CPU time 1.23 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 195556 kb
Host smart-e7d60424-6b59-4936-94e4-f14a00b0e83d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656898830 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.656898830
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1698176873
Short name T31
Test name
Test status
Simulation time 307907513 ps
CPU time 0.65 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 192888 kb
Host smart-d7224a67-fd6d-45b1-b246-80b902d69f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698176873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1698176873
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3913993052
Short name T293
Test name
Test status
Simulation time 318923606 ps
CPU time 0.8 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:57 PM PDT 24
Peak memory 183620 kb
Host smart-ed3cbd3b-b265-419a-a83a-0192ab65e72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913993052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3913993052
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3368577879
Short name T371
Test name
Test status
Simulation time 1168986782 ps
CPU time 2.03 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 194116 kb
Host smart-a1f69e26-79de-4f6e-893f-ed4e7c600128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368577879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3368577879
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2863467981
Short name T360
Test name
Test status
Simulation time 547190894 ps
CPU time 2.22 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 198640 kb
Host smart-ad87c428-a9d0-4061-b9c5-ec6751474c99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863467981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2863467981
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.745179367
Short name T194
Test name
Test status
Simulation time 8945295475 ps
CPU time 6.77 seconds
Started Aug 10 04:41:57 PM PDT 24
Finished Aug 10 04:42:04 PM PDT 24
Peak memory 198284 kb
Host smart-2fef0b11-bba5-408c-8400-de772188a62f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745179367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.745179367
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.577677723
Short name T61
Test name
Test status
Simulation time 523951050 ps
CPU time 1.37 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 183696 kb
Host smart-b764f014-ea71-4cd3-aaa4-7f7f9586eff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577677723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.577677723
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2460903304
Short name T418
Test name
Test status
Simulation time 13492588981 ps
CPU time 27.49 seconds
Started Aug 10 04:41:23 PM PDT 24
Finished Aug 10 04:41:51 PM PDT 24
Peak memory 196092 kb
Host smart-4b423e93-9e1b-4e09-bf3e-f260a374fa3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460903304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2460903304
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3841048736
Short name T382
Test name
Test status
Simulation time 901828972 ps
CPU time 0.66 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 192876 kb
Host smart-56e755ee-0901-4c46-93c0-96620d4fab94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841048736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3841048736
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1118403670
Short name T377
Test name
Test status
Simulation time 379616902 ps
CPU time 0.75 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:25 PM PDT 24
Peak memory 195568 kb
Host smart-840f4a72-2050-4d20-928b-d08768965999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118403670 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1118403670
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.408335226
Short name T71
Test name
Test status
Simulation time 431980213 ps
CPU time 0.7 seconds
Started Aug 10 04:41:27 PM PDT 24
Finished Aug 10 04:41:28 PM PDT 24
Peak memory 192936 kb
Host smart-d10b89eb-2791-4a55-9825-5dfb7dd91f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408335226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.408335226
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3742728042
Short name T327
Test name
Test status
Simulation time 493822502 ps
CPU time 0.91 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 192992 kb
Host smart-1339d1b2-afa8-4295-b2e7-14091b94f8e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742728042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3742728042
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3399767101
Short name T421
Test name
Test status
Simulation time 500710605 ps
CPU time 1.19 seconds
Started Aug 10 04:41:28 PM PDT 24
Finished Aug 10 04:41:30 PM PDT 24
Peak memory 183624 kb
Host smart-87bed260-da13-474f-9f17-d885f08d6b46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399767101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3399767101
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1769288543
Short name T322
Test name
Test status
Simulation time 372588289 ps
CPU time 1.03 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 183548 kb
Host smart-39f3a2b8-6461-4e96-8fe3-ca22feb332f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769288543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1769288543
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2570775198
Short name T347
Test name
Test status
Simulation time 1126146269 ps
CPU time 2.06 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:28 PM PDT 24
Peak memory 193968 kb
Host smart-398ed191-231c-4f04-aebb-edd936bbbdda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570775198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2570775198
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4143104493
Short name T307
Test name
Test status
Simulation time 409622391 ps
CPU time 2.17 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 198532 kb
Host smart-8adef622-581d-471e-96cf-20284b4977a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143104493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4143104493
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3118543284
Short name T399
Test name
Test status
Simulation time 4269699432 ps
CPU time 2.62 seconds
Started Aug 10 04:41:25 PM PDT 24
Finished Aug 10 04:41:28 PM PDT 24
Peak memory 197764 kb
Host smart-4ca051c3-eb2c-4d94-916f-13e74e5e13a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118543284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3118543284
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3971959704
Short name T404
Test name
Test status
Simulation time 320143562 ps
CPU time 1.02 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 183656 kb
Host smart-a077dd34-0e38-4e2f-8028-abbf05299c3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971959704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3971959704
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1596704316
Short name T352
Test name
Test status
Simulation time 362432213 ps
CPU time 0.73 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 192884 kb
Host smart-dce64399-b2da-4d32-9403-9e165cd2f0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596704316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1596704316
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2551302834
Short name T403
Test name
Test status
Simulation time 463654200 ps
CPU time 0.63 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 192884 kb
Host smart-b1264880-f5e1-4fec-bcae-8c550ad7adb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551302834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2551302834
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.332599203
Short name T316
Test name
Test status
Simulation time 415412481 ps
CPU time 1.11 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183704 kb
Host smart-7f0d4dc0-2b40-474c-b6b0-aa0269158efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332599203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.332599203
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4144038673
Short name T292
Test name
Test status
Simulation time 582627430 ps
CPU time 0.62 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183640 kb
Host smart-0d308769-b3a7-4c1e-88a4-0332d5e7388b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144038673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4144038673
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2962626798
Short name T349
Test name
Test status
Simulation time 439846848 ps
CPU time 0.88 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 183700 kb
Host smart-14af5a10-78d9-41e1-b40d-b90d91e85bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962626798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2962626798
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1571201382
Short name T405
Test name
Test status
Simulation time 472104960 ps
CPU time 1.35 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183736 kb
Host smart-713ac3ca-5806-494b-a4c2-5d4e029c9fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571201382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1571201382
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2005316783
Short name T332
Test name
Test status
Simulation time 512117426 ps
CPU time 0.89 seconds
Started Aug 10 04:41:51 PM PDT 24
Finished Aug 10 04:41:52 PM PDT 24
Peak memory 183700 kb
Host smart-302b26a6-157c-45b5-96e6-7c0bc91a81f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005316783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2005316783
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3956373067
Short name T300
Test name
Test status
Simulation time 296952670 ps
CPU time 1.02 seconds
Started Aug 10 04:41:51 PM PDT 24
Finished Aug 10 04:41:52 PM PDT 24
Peak memory 183664 kb
Host smart-3460f669-8192-4106-b0b2-09fa1d7bb254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956373067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3956373067
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3219748313
Short name T391
Test name
Test status
Simulation time 386705174 ps
CPU time 0.69 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:53 PM PDT 24
Peak memory 183952 kb
Host smart-8023047c-ae3a-4ae6-9d9e-78a0996c5a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219748313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3219748313
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1192669985
Short name T60
Test name
Test status
Simulation time 620347961 ps
CPU time 0.83 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 193128 kb
Host smart-706093d7-3d45-4a17-adea-bbc6b44975f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192669985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1192669985
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1726146143
Short name T54
Test name
Test status
Simulation time 8732043469 ps
CPU time 5.2 seconds
Started Aug 10 04:41:39 PM PDT 24
Finished Aug 10 04:41:44 PM PDT 24
Peak memory 192152 kb
Host smart-7b4bd7d8-5af4-4535-8193-f09e65f156a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726146143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1726146143
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1042035003
Short name T417
Test name
Test status
Simulation time 1296320917 ps
CPU time 2.55 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 192856 kb
Host smart-1c2d16a4-e5a7-4702-9c63-3f4441433dd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042035003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1042035003
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2198824537
Short name T376
Test name
Test status
Simulation time 408487085 ps
CPU time 1.11 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 195128 kb
Host smart-04d39ce0-3afb-4a95-927c-4a9515730f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198824537 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2198824537
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1793821251
Short name T353
Test name
Test status
Simulation time 533438892 ps
CPU time 1.43 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:36 PM PDT 24
Peak memory 192880 kb
Host smart-93626fc1-275c-4156-b16c-cf8372593580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793821251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1793821251
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1001085634
Short name T394
Test name
Test status
Simulation time 452022894 ps
CPU time 1.22 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:26 PM PDT 24
Peak memory 192892 kb
Host smart-caa7079c-dc19-4981-9908-d33c20868b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001085634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1001085634
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.218155278
Short name T387
Test name
Test status
Simulation time 446249844 ps
CPU time 0.76 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 183612 kb
Host smart-20a5f68c-7874-49f0-beac-b95716cac147
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218155278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.218155278
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1946954225
Short name T373
Test name
Test status
Simulation time 298704394 ps
CPU time 0.94 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 183548 kb
Host smart-2d6503d1-d485-4ba3-adfd-78fe06e1e348
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946954225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1946954225
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1518462190
Short name T342
Test name
Test status
Simulation time 1523886291 ps
CPU time 2.75 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 193816 kb
Host smart-4b5a27a7-79eb-41f7-a84f-d2c8c35f3a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518462190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1518462190
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1172849265
Short name T324
Test name
Test status
Simulation time 340246607 ps
CPU time 1.36 seconds
Started Aug 10 04:41:26 PM PDT 24
Finished Aug 10 04:41:28 PM PDT 24
Peak memory 198512 kb
Host smart-3d593e4e-a812-4c18-a748-6fab14a3b2ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172849265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1172849265
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4163357007
Short name T193
Test name
Test status
Simulation time 8907152912 ps
CPU time 15.2 seconds
Started Aug 10 04:41:24 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 198264 kb
Host smart-c003092d-6381-4f39-b220-318a837e06bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163357007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4163357007
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3535611740
Short name T302
Test name
Test status
Simulation time 440101361 ps
CPU time 1.38 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:57 PM PDT 24
Peak memory 183688 kb
Host smart-9a8073db-bbe7-4bf0-a8c6-4fa30daa3cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535611740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3535611740
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.145081551
Short name T304
Test name
Test status
Simulation time 406419360 ps
CPU time 0.88 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:57 PM PDT 24
Peak memory 183616 kb
Host smart-a461e0b6-b099-4f5b-a9dd-329bdf28093d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145081551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.145081551
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3147208235
Short name T305
Test name
Test status
Simulation time 458190353 ps
CPU time 0.76 seconds
Started Aug 10 04:41:57 PM PDT 24
Finished Aug 10 04:41:58 PM PDT 24
Peak memory 183716 kb
Host smart-e075021d-365a-4f62-854a-be4cae0265ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147208235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3147208235
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1175058703
Short name T361
Test name
Test status
Simulation time 326735789 ps
CPU time 1.01 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183636 kb
Host smart-adf06095-c63e-4ef4-b731-5ae8ccbab136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175058703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1175058703
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2152252876
Short name T290
Test name
Test status
Simulation time 481990150 ps
CPU time 0.74 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183704 kb
Host smart-4bbcd2c7-8a95-4f40-b38d-1db5e4ac280c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152252876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2152252876
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.796561100
Short name T362
Test name
Test status
Simulation time 314263545 ps
CPU time 0.68 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 183636 kb
Host smart-376b8496-453e-46b4-8dac-482575f76f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796561100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.796561100
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1762659618
Short name T356
Test name
Test status
Simulation time 366008663 ps
CPU time 0.65 seconds
Started Aug 10 04:41:57 PM PDT 24
Finished Aug 10 04:41:58 PM PDT 24
Peak memory 192836 kb
Host smart-46caa966-34d8-4b46-86de-db940df217cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762659618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1762659618
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3906768412
Short name T363
Test name
Test status
Simulation time 348357670 ps
CPU time 0.64 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 183688 kb
Host smart-c8aab02c-131e-453c-93f9-91b860fbfa46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906768412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3906768412
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1975570765
Short name T420
Test name
Test status
Simulation time 445430984 ps
CPU time 1.34 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183688 kb
Host smart-5971febe-e144-465f-a49b-b5a1ad57071f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975570765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1975570765
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.331519122
Short name T388
Test name
Test status
Simulation time 443008140 ps
CPU time 0.69 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183768 kb
Host smart-9c85c679-69be-41a9-84aa-b645b2488fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331519122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.331519122
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3295890011
Short name T392
Test name
Test status
Simulation time 601262214 ps
CPU time 0.88 seconds
Started Aug 10 04:41:40 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 193340 kb
Host smart-be55a0a0-d9cc-40cb-90bf-3b029ca6eff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295890011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3295890011
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3294156181
Short name T52
Test name
Test status
Simulation time 9695043755 ps
CPU time 3.34 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 192144 kb
Host smart-460ba725-7ace-41b8-ba27-2f3a1845ae42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294156181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3294156181
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2596789254
Short name T354
Test name
Test status
Simulation time 1153386298 ps
CPU time 1.02 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:36 PM PDT 24
Peak memory 193044 kb
Host smart-f4b78c40-4cdf-4c2d-9e95-d135fdaef5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596789254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2596789254
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2489789316
Short name T295
Test name
Test status
Simulation time 378071890 ps
CPU time 1.23 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 196116 kb
Host smart-9c1ac76e-aa58-4d79-9692-5ddc9d1aa300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489789316 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2489789316
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.771247518
Short name T59
Test name
Test status
Simulation time 590450853 ps
CPU time 0.7 seconds
Started Aug 10 04:41:34 PM PDT 24
Finished Aug 10 04:41:34 PM PDT 24
Peak memory 192920 kb
Host smart-1213980f-f03a-40fb-85a2-236af67a0737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771247518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.771247518
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.93527541
Short name T351
Test name
Test status
Simulation time 342467622 ps
CPU time 0.69 seconds
Started Aug 10 04:41:40 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 183692 kb
Host smart-42f0063e-a1f2-435e-bac0-e4075017b2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93527541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.93527541
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1962777133
Short name T366
Test name
Test status
Simulation time 343836297 ps
CPU time 0.63 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 183560 kb
Host smart-b563d3c9-5866-4e7b-a362-c9345e4d4757
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962777133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1962777133
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2517979721
Short name T333
Test name
Test status
Simulation time 340836667 ps
CPU time 1 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:36 PM PDT 24
Peak memory 183588 kb
Host smart-dbb83d87-30be-449c-b015-9a53ea952114
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517979721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2517979721
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.452109982
Short name T406
Test name
Test status
Simulation time 1141653937 ps
CPU time 1.92 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 193440 kb
Host smart-07d7ce03-2863-43c0-9eb4-4e105ba21fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452109982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.452109982
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2773933912
Short name T288
Test name
Test status
Simulation time 481730141 ps
CPU time 1.39 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 198496 kb
Host smart-b183b01d-92fb-4f52-babf-22de0eac2708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773933912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2773933912
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3135608540
Short name T368
Test name
Test status
Simulation time 8197186537 ps
CPU time 3.91 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 198124 kb
Host smart-e0681baa-05f8-403f-8528-19caeec14be7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135608540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3135608540
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4019759354
Short name T314
Test name
Test status
Simulation time 421718564 ps
CPU time 0.7 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 183636 kb
Host smart-21614427-506b-4df1-8bc0-bb08194806dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019759354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4019759354
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1924817169
Short name T410
Test name
Test status
Simulation time 508070495 ps
CPU time 0.79 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 183680 kb
Host smart-77844c59-1b12-4ae8-aa2e-868bad41fd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924817169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1924817169
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1723932746
Short name T319
Test name
Test status
Simulation time 389239648 ps
CPU time 0.69 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 183736 kb
Host smart-be9201d1-b619-4209-bf51-537efd3bbc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723932746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1723932746
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.296117416
Short name T311
Test name
Test status
Simulation time 338984110 ps
CPU time 1.08 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 192816 kb
Host smart-5ed3a5b6-85a2-4171-acbf-83961ede6f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296117416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.296117416
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4266646278
Short name T355
Test name
Test status
Simulation time 360631820 ps
CPU time 0.74 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 183668 kb
Host smart-55106ee3-2731-4911-8b97-d27372bf0e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266646278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4266646278
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.254551913
Short name T372
Test name
Test status
Simulation time 401443574 ps
CPU time 1.15 seconds
Started Aug 10 04:41:54 PM PDT 24
Finished Aug 10 04:41:55 PM PDT 24
Peak memory 192884 kb
Host smart-6365ad40-8ed8-43f2-84fc-09074be67bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254551913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.254551913
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2981455794
Short name T398
Test name
Test status
Simulation time 473461527 ps
CPU time 0.77 seconds
Started Aug 10 04:41:56 PM PDT 24
Finished Aug 10 04:41:57 PM PDT 24
Peak memory 183608 kb
Host smart-0033b2ac-2855-453a-9384-fd64c2d62f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981455794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2981455794
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2797082918
Short name T299
Test name
Test status
Simulation time 458736641 ps
CPU time 1.14 seconds
Started Aug 10 04:41:53 PM PDT 24
Finished Aug 10 04:41:54 PM PDT 24
Peak memory 192908 kb
Host smart-0c98ca9b-7470-4257-81ec-dc049c7e7f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797082918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2797082918
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3730535264
Short name T338
Test name
Test status
Simulation time 385611443 ps
CPU time 0.69 seconds
Started Aug 10 04:41:55 PM PDT 24
Finished Aug 10 04:41:56 PM PDT 24
Peak memory 183636 kb
Host smart-3c0efe06-cc55-4c2f-8197-3c130dbd8ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730535264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3730535264
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.273635035
Short name T378
Test name
Test status
Simulation time 459048960 ps
CPU time 0.71 seconds
Started Aug 10 04:41:57 PM PDT 24
Finished Aug 10 04:41:58 PM PDT 24
Peak memory 183616 kb
Host smart-2d1b13ea-f575-4845-954b-92d06aa9476c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273635035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.273635035
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1698892258
Short name T200
Test name
Test status
Simulation time 471007548 ps
CPU time 1.41 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 196224 kb
Host smart-109efa13-1bf9-465a-951b-6814178e89b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698892258 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1698892258
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.820831473
Short name T385
Test name
Test status
Simulation time 443606693 ps
CPU time 0.69 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:36 PM PDT 24
Peak memory 183760 kb
Host smart-04d1e6d5-0cc8-4487-9fab-3a350a30ffeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820831473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.820831473
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1453099648
Short name T396
Test name
Test status
Simulation time 912974308 ps
CPU time 1.76 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 192968 kb
Host smart-7cc20b33-fd96-4f1b-ace6-fc67d6d119f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453099648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1453099648
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3379673316
Short name T357
Test name
Test status
Simulation time 342707589 ps
CPU time 1.61 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 198512 kb
Host smart-da000674-74f5-4a7f-b9ee-753bf04c5817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379673316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3379673316
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.574991046
Short name T191
Test name
Test status
Simulation time 4250284695 ps
CPU time 7.88 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 197768 kb
Host smart-9e99f7f2-e057-4c27-ae18-11a45791e76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574991046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.574991046
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.965940732
Short name T27
Test name
Test status
Simulation time 468993432 ps
CPU time 0.99 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 198256 kb
Host smart-e7037843-511f-40c4-a91c-9f81bc72e73e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965940732 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.965940732
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3225635576
Short name T56
Test name
Test status
Simulation time 417970697 ps
CPU time 0.87 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 192872 kb
Host smart-f81e79c7-3b9b-4f97-ae1c-1d4ac047f7f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225635576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3225635576
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3069505805
Short name T367
Test name
Test status
Simulation time 414705972 ps
CPU time 0.7 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:35 PM PDT 24
Peak memory 183676 kb
Host smart-36fe970f-8eef-47a9-9a2b-9e50be4db544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069505805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3069505805
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3635134971
Short name T350
Test name
Test status
Simulation time 1676628368 ps
CPU time 1.77 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 183820 kb
Host smart-9bbc6e88-21bc-4522-9965-9b445dae5547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635134971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3635134971
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3287592113
Short name T344
Test name
Test status
Simulation time 374272419 ps
CPU time 1.64 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 198504 kb
Host smart-53880a1d-6577-48e8-b79c-daee9eab7b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287592113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3287592113
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3273071833
Short name T26
Test name
Test status
Simulation time 4579508565 ps
CPU time 3.98 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 197900 kb
Host smart-80812c76-a313-4883-b4b0-d2e78191e2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273071833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3273071833
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.586731954
Short name T358
Test name
Test status
Simulation time 413255258 ps
CPU time 1.26 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 195684 kb
Host smart-7bfb25fe-e0a9-49c5-9921-1ede4e9455d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586731954 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.586731954
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2470761568
Short name T53
Test name
Test status
Simulation time 463343189 ps
CPU time 0.73 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 193108 kb
Host smart-ae9c834c-3d6e-447f-9678-ab78deea388d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470761568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2470761568
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2033160220
Short name T336
Test name
Test status
Simulation time 304490799 ps
CPU time 0.75 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:36 PM PDT 24
Peak memory 183676 kb
Host smart-a8d0b8a2-757c-4f0e-9027-6ae1c67aaf43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033160220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2033160220
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4263754294
Short name T70
Test name
Test status
Simulation time 2520574400 ps
CPU time 3.31 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 193832 kb
Host smart-9b06484b-5c99-45f0-9d0d-e293fce22dbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263754294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4263754294
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2108838006
Short name T384
Test name
Test status
Simulation time 497615027 ps
CPU time 2.73 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 198604 kb
Host smart-8401872c-88d3-413b-8748-83ef5a37e2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108838006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2108838006
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.552133698
Short name T294
Test name
Test status
Simulation time 8679309288 ps
CPU time 4.7 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:43 PM PDT 24
Peak memory 198576 kb
Host smart-9f858064-e30f-49b9-a711-aca1fdd0e0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552133698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.552133698
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3206736909
Short name T381
Test name
Test status
Simulation time 337364718 ps
CPU time 1.18 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 195876 kb
Host smart-50b53e79-9e2e-4721-b401-0a16df49e6a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206736909 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3206736909
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.994713917
Short name T303
Test name
Test status
Simulation time 365473238 ps
CPU time 1.11 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 191924 kb
Host smart-1431e42c-cabc-4aac-8020-143ffec5b64d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994713917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.994713917
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.929926226
Short name T285
Test name
Test status
Simulation time 464213032 ps
CPU time 0.72 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:39 PM PDT 24
Peak memory 183688 kb
Host smart-da75d2ea-58b1-406f-affa-00052a15bce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929926226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.929926226
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2771355021
Short name T72
Test name
Test status
Simulation time 1038200620 ps
CPU time 1 seconds
Started Aug 10 04:41:39 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 183836 kb
Host smart-b6a57bb6-8ebf-45e7-a1e1-708bfb83524b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771355021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2771355021
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3989281044
Short name T359
Test name
Test status
Simulation time 583276000 ps
CPU time 2.65 seconds
Started Aug 10 04:41:37 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 198472 kb
Host smart-925f2982-b271-49c1-a1be-d487765ae798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989281044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3989281044
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3076353989
Short name T28
Test name
Test status
Simulation time 8119554543 ps
CPU time 4.34 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 198068 kb
Host smart-76832247-1e87-46af-9ede-2876a75e3c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076353989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3076353989
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.722253754
Short name T401
Test name
Test status
Simulation time 337008067 ps
CPU time 1.23 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 196428 kb
Host smart-7fa7cc4f-2aff-4a61-af62-a4fac8fce21a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722253754 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.722253754
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4251476318
Short name T343
Test name
Test status
Simulation time 444250479 ps
CPU time 0.92 seconds
Started Aug 10 04:41:39 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 192872 kb
Host smart-14952fac-ad69-4766-8ba7-3fafbc6eca35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251476318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4251476318
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1378294755
Short name T339
Test name
Test status
Simulation time 440433732 ps
CPU time 0.71 seconds
Started Aug 10 04:41:36 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 192888 kb
Host smart-84618c17-dfbd-4d2b-ac2d-f4e36f5e8333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378294755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1378294755
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3747305177
Short name T65
Test name
Test status
Simulation time 1426041892 ps
CPU time 5.03 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:41 PM PDT 24
Peak memory 193492 kb
Host smart-2c8333f3-be41-47d9-98f9-eed4e7a2f405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747305177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3747305177
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2663144936
Short name T315
Test name
Test status
Simulation time 436384164 ps
CPU time 1.78 seconds
Started Aug 10 04:41:35 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 198512 kb
Host smart-dde8a620-c914-4c74-a8cf-b3a4d589e7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663144936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2663144936
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.126276285
Short name T416
Test name
Test status
Simulation time 4382108680 ps
CPU time 7.41 seconds
Started Aug 10 04:41:38 PM PDT 24
Finished Aug 10 04:41:46 PM PDT 24
Peak memory 196476 kb
Host smart-49764146-0e63-4b98-8581-db9d8586ecc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126276285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.126276285
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3492116
Short name T242
Test name
Test status
Simulation time 38016182105 ps
CPU time 14.21 seconds
Started Aug 10 04:26:05 PM PDT 24
Finished Aug 10 04:26:19 PM PDT 24
Peak memory 197008 kb
Host smart-a1874ace-4416-471b-9bf8-b467da4665c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3492116
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2611326091
Short name T18
Test name
Test status
Simulation time 4320154982 ps
CPU time 3.63 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:29 PM PDT 24
Peak memory 215516 kb
Host smart-4f424d8f-b8d3-47b8-895b-6a2d799e60bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611326091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2611326091
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1132188274
Short name T7
Test name
Test status
Simulation time 419484445 ps
CPU time 0.88 seconds
Started Aug 10 04:26:07 PM PDT 24
Finished Aug 10 04:26:08 PM PDT 24
Peak memory 196780 kb
Host smart-2f198df4-4f9c-4561-b6c0-136bec324491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132188274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1132188274
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2366570530
Short name T274
Test name
Test status
Simulation time 188453001065 ps
CPU time 37.08 seconds
Started Aug 10 04:26:15 PM PDT 24
Finished Aug 10 04:26:52 PM PDT 24
Peak memory 192032 kb
Host smart-f405d04d-fd83-4299-b286-22747470ab82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366570530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2366570530
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1014136494
Short name T76
Test name
Test status
Simulation time 317753632557 ps
CPU time 557.91 seconds
Started Aug 10 04:26:08 PM PDT 24
Finished Aug 10 04:35:26 PM PDT 24
Peak memory 212724 kb
Host smart-bd21a8b1-1078-4895-86aa-cea34af7bcff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014136494 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1014136494
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.210354356
Short name T42
Test name
Test status
Simulation time 53428636162 ps
CPU time 17.69 seconds
Started Aug 10 04:26:26 PM PDT 24
Finished Aug 10 04:26:43 PM PDT 24
Peak memory 192032 kb
Host smart-a623c9b0-1969-4ffd-a451-353b05cf8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210354356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.210354356
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1860353819
Short name T20
Test name
Test status
Simulation time 4237512775 ps
CPU time 1.82 seconds
Started Aug 10 04:26:05 PM PDT 24
Finished Aug 10 04:26:07 PM PDT 24
Peak memory 215376 kb
Host smart-66adb70f-393e-4c06-916e-c311e00ad4b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860353819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1860353819
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.700845649
Short name T204
Test name
Test status
Simulation time 546574436 ps
CPU time 1.05 seconds
Started Aug 10 04:26:11 PM PDT 24
Finished Aug 10 04:26:12 PM PDT 24
Peak memory 191940 kb
Host smart-6380dac8-3502-4065-adfa-27cf4279705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700845649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.700845649
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1414502813
Short name T168
Test name
Test status
Simulation time 651052326 ps
CPU time 0.69 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196776 kb
Host smart-855304f1-93d7-4cd3-97bf-8db5c618a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414502813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1414502813
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3429716368
Short name T231
Test name
Test status
Simulation time 5226721581 ps
CPU time 2.56 seconds
Started Aug 10 04:26:12 PM PDT 24
Finished Aug 10 04:26:20 PM PDT 24
Peak memory 192004 kb
Host smart-ab6fe27e-035a-4018-81dc-003d1eefe10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429716368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3429716368
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.21767371
Short name T217
Test name
Test status
Simulation time 611731006 ps
CPU time 0.78 seconds
Started Aug 10 04:26:28 PM PDT 24
Finished Aug 10 04:26:29 PM PDT 24
Peak memory 191948 kb
Host smart-94c3cc0b-7cfd-4608-b841-3a8c839a2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21767371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.21767371
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.148880254
Short name T223
Test name
Test status
Simulation time 42245839374 ps
CPU time 62.05 seconds
Started Aug 10 04:26:11 PM PDT 24
Finished Aug 10 04:27:13 PM PDT 24
Peak memory 196944 kb
Host smart-35dd0128-e0ea-4020-9579-a118bec22dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148880254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.148880254
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.675970850
Short name T244
Test name
Test status
Simulation time 345928190 ps
CPU time 1.02 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196776 kb
Host smart-d8b74721-e806-4a05-bdf0-84d7a46fc0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675970850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.675970850
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4121201404
Short name T189
Test name
Test status
Simulation time 189321157689 ps
CPU time 69.57 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:27:33 PM PDT 24
Peak memory 198388 kb
Host smart-e47dd6eb-914b-4537-b5f9-0d0def8d59db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121201404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4121201404
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1102515654
Short name T249
Test name
Test status
Simulation time 21133135563 ps
CPU time 28.11 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:27:03 PM PDT 24
Peak memory 191996 kb
Host smart-1bf39fcd-6743-4197-ab0b-3945234e3272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102515654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1102515654
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1219570852
Short name T228
Test name
Test status
Simulation time 452804946 ps
CPU time 0.77 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:26:21 PM PDT 24
Peak memory 191880 kb
Host smart-f449d60e-e2d6-47c2-a8b4-11cc4ebd0c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219570852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1219570852
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3332971404
Short name T279
Test name
Test status
Simulation time 28273393467 ps
CPU time 34.61 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 196940 kb
Host smart-563b7b52-5753-4dfc-a131-73b3428e6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332971404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3332971404
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.4053444354
Short name T232
Test name
Test status
Simulation time 641884307 ps
CPU time 0.73 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:26:38 PM PDT 24
Peak memory 192048 kb
Host smart-35dab887-7c23-42f0-a86e-f6526e8ac2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053444354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4053444354
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.727338361
Short name T264
Test name
Test status
Simulation time 43667950549 ps
CPU time 15.36 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 191972 kb
Host smart-ea4b786d-d33a-4bdb-9030-958f82423609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727338361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.727338361
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3552919685
Short name T254
Test name
Test status
Simulation time 377306350 ps
CPU time 0.72 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:35 PM PDT 24
Peak memory 196860 kb
Host smart-29f40a8c-31eb-4707-8c3e-8d57f9ee6591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552919685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3552919685
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1576506352
Short name T190
Test name
Test status
Simulation time 593409799 ps
CPU time 1.11 seconds
Started Aug 10 04:26:27 PM PDT 24
Finished Aug 10 04:26:29 PM PDT 24
Peak memory 196644 kb
Host smart-7bf0eb52-4685-4f18-9c31-8ff8626de43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576506352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1576506352
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1027034505
Short name T222
Test name
Test status
Simulation time 57880189576 ps
CPU time 7.75 seconds
Started Aug 10 04:26:10 PM PDT 24
Finished Aug 10 04:26:18 PM PDT 24
Peak memory 192040 kb
Host smart-9abcdfa3-af5b-4007-8d87-941d9ccc8a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027034505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1027034505
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2419099454
Short name T259
Test name
Test status
Simulation time 421415876 ps
CPU time 1.15 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196724 kb
Host smart-e3b12862-0232-4c8b-b010-eeea5410955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419099454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2419099454
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2402648108
Short name T283
Test name
Test status
Simulation time 18571862791 ps
CPU time 27.84 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:53 PM PDT 24
Peak memory 196972 kb
Host smart-94cd6020-2245-43fe-b8d5-50b9666fc952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402648108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2402648108
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2215845457
Short name T275
Test name
Test status
Simulation time 526339015 ps
CPU time 1.23 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:26:25 PM PDT 24
Peak memory 196772 kb
Host smart-ee1228cd-9338-4d8f-b47e-d310d7d16288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215845457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2215845457
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.534715048
Short name T214
Test name
Test status
Simulation time 15180343945 ps
CPU time 11.69 seconds
Started Aug 10 04:26:10 PM PDT 24
Finished Aug 10 04:26:22 PM PDT 24
Peak memory 197004 kb
Host smart-fc3ee81f-5e21-4459-9c47-69c35cc73dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534715048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.534715048
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3615785660
Short name T276
Test name
Test status
Simulation time 598817304 ps
CPU time 0.76 seconds
Started Aug 10 04:26:09 PM PDT 24
Finished Aug 10 04:26:10 PM PDT 24
Peak memory 191884 kb
Host smart-e65ea5b4-6c18-4967-aa74-f0cf44cfcdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615785660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3615785660
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1378121748
Short name T13
Test name
Test status
Simulation time 2098475721 ps
CPU time 3.49 seconds
Started Aug 10 04:26:23 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 191932 kb
Host smart-f891b512-afd6-484b-b7f9-b73b0e010adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378121748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1378121748
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1315104350
Short name T218
Test name
Test status
Simulation time 622024091 ps
CPU time 0.68 seconds
Started Aug 10 04:26:26 PM PDT 24
Finished Aug 10 04:26:27 PM PDT 24
Peak memory 196776 kb
Host smart-45dad905-b279-48c1-8602-82e05b2912ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315104350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1315104350
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2068855787
Short name T270
Test name
Test status
Simulation time 54482657621 ps
CPU time 21.49 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:53 PM PDT 24
Peak memory 196944 kb
Host smart-9af52245-b9e5-4470-9cc9-16dc627d42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068855787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2068855787
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.72647877
Short name T213
Test name
Test status
Simulation time 589710453 ps
CPU time 0.94 seconds
Started Aug 10 04:26:09 PM PDT 24
Finished Aug 10 04:26:10 PM PDT 24
Peak memory 192016 kb
Host smart-7916129d-ccb7-40ba-a664-a00089766f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72647877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.72647877
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.667170911
Short name T8
Test name
Test status
Simulation time 52541839846 ps
CPU time 80.62 seconds
Started Aug 10 04:26:11 PM PDT 24
Finished Aug 10 04:27:32 PM PDT 24
Peak memory 192008 kb
Host smart-2fc8daab-06c3-47fe-874f-d96722147597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667170911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.667170911
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3810727539
Short name T17
Test name
Test status
Simulation time 4264859568 ps
CPU time 4.15 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:26:10 PM PDT 24
Peak memory 215352 kb
Host smart-00fc4bbe-7225-42f7-81dd-b51dd56c5b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810727539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3810727539
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2552061072
Short name T278
Test name
Test status
Simulation time 584506510 ps
CPU time 0.72 seconds
Started Aug 10 04:26:08 PM PDT 24
Finished Aug 10 04:26:09 PM PDT 24
Peak memory 192040 kb
Host smart-5f336f7d-1b32-4b1f-b687-bdaaab174895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552061072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2552061072
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1134769818
Short name T198
Test name
Test status
Simulation time 55808334254 ps
CPU time 79.86 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:27:51 PM PDT 24
Peak memory 192008 kb
Host smart-eeae6dd7-00a2-4d5d-a668-1b24f3797871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134769818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1134769818
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.533698618
Short name T211
Test name
Test status
Simulation time 577292199 ps
CPU time 1.02 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:26:44 PM PDT 24
Peak memory 197028 kb
Host smart-f236170f-36f6-4c58-bf3d-5f0843d1509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533698618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.533698618
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3310177924
Short name T241
Test name
Test status
Simulation time 51546306525 ps
CPU time 18.57 seconds
Started Aug 10 04:26:36 PM PDT 24
Finished Aug 10 04:26:54 PM PDT 24
Peak memory 192028 kb
Host smart-2f873e17-651d-4a87-a0b8-05039bad0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310177924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3310177924
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4289081285
Short name T252
Test name
Test status
Simulation time 396721149 ps
CPU time 0.85 seconds
Started Aug 10 04:26:27 PM PDT 24
Finished Aug 10 04:26:28 PM PDT 24
Peak memory 196768 kb
Host smart-35735098-3f3f-47cd-ac2d-e54efef05cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289081285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4289081285
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4265333589
Short name T179
Test name
Test status
Simulation time 524299705 ps
CPU time 1.36 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:32 PM PDT 24
Peak memory 196616 kb
Host smart-99608f4b-7640-4913-ae18-c8abdf209f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265333589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4265333589
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2778985697
Short name T273
Test name
Test status
Simulation time 8319982974 ps
CPU time 3.82 seconds
Started Aug 10 04:26:30 PM PDT 24
Finished Aug 10 04:26:34 PM PDT 24
Peak memory 197052 kb
Host smart-7817572e-94b9-4b57-8931-3e2c60487c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778985697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2778985697
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.155778963
Short name T247
Test name
Test status
Simulation time 551037884 ps
CPU time 0.65 seconds
Started Aug 10 04:26:54 PM PDT 24
Finished Aug 10 04:26:54 PM PDT 24
Peak memory 191920 kb
Host smart-898cc478-be67-48bc-8a23-b0a441b1e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155778963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.155778963
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.581950011
Short name T238
Test name
Test status
Simulation time 12065446771 ps
CPU time 7.97 seconds
Started Aug 10 04:26:15 PM PDT 24
Finished Aug 10 04:26:24 PM PDT 24
Peak memory 191932 kb
Host smart-f123df0b-4351-4448-b409-5e69eb85859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581950011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.581950011
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.478616707
Short name T235
Test name
Test status
Simulation time 525015678 ps
CPU time 1.3 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:36 PM PDT 24
Peak memory 196760 kb
Host smart-50cd18c2-7297-4fb1-9134-54cf7f2a9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478616707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.478616707
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2599532836
Short name T176
Test name
Test status
Simulation time 483996313167 ps
CPU time 347.84 seconds
Started Aug 10 04:26:32 PM PDT 24
Finished Aug 10 04:32:20 PM PDT 24
Peak memory 193064 kb
Host smart-d4ef08ae-21b8-40d0-9902-a7cfc9b5d81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599532836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2599532836
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1330972035
Short name T10
Test name
Test status
Simulation time 559200373 ps
CPU time 0.67 seconds
Started Aug 10 04:26:33 PM PDT 24
Finished Aug 10 04:26:34 PM PDT 24
Peak memory 196924 kb
Host smart-7355ccac-cd4f-4733-bbd8-933882e6573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330972035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1330972035
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2246579908
Short name T210
Test name
Test status
Simulation time 16882342592 ps
CPU time 4.09 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:26:54 PM PDT 24
Peak memory 196992 kb
Host smart-11258900-71d5-48e5-8e1e-679622381ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246579908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2246579908
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1785319710
Short name T225
Test name
Test status
Simulation time 586173654 ps
CPU time 0.83 seconds
Started Aug 10 04:26:30 PM PDT 24
Finished Aug 10 04:26:31 PM PDT 24
Peak memory 196584 kb
Host smart-259b77d3-0577-4539-a119-02cdd7b20efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785319710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1785319710
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3481065379
Short name T41
Test name
Test status
Simulation time 54753848859 ps
CPU time 82.05 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:28:05 PM PDT 24
Peak memory 191976 kb
Host smart-65055764-ca76-4669-a9ce-4290f44433ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481065379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3481065379
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.72555640
Short name T256
Test name
Test status
Simulation time 441381871 ps
CPU time 1.19 seconds
Started Aug 10 04:26:44 PM PDT 24
Finished Aug 10 04:26:45 PM PDT 24
Peak memory 191840 kb
Host smart-9a631b25-34ec-4b30-9957-d55712b7f1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72555640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.72555640
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1321719295
Short name T237
Test name
Test status
Simulation time 21350630359 ps
CPU time 6.22 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:37 PM PDT 24
Peak memory 191920 kb
Host smart-375f29f6-0bcb-4015-ad89-6e8163bbb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321719295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1321719295
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2548585513
Short name T212
Test name
Test status
Simulation time 577093469 ps
CPU time 0.71 seconds
Started Aug 10 04:26:20 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 191984 kb
Host smart-123f9246-5e4a-4e53-9e2c-31fc09ab882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548585513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2548585513
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.766944915
Short name T251
Test name
Test status
Simulation time 25733461697 ps
CPU time 17.53 seconds
Started Aug 10 04:26:35 PM PDT 24
Finished Aug 10 04:26:53 PM PDT 24
Peak memory 191964 kb
Host smart-9c1e3cb7-0465-4c55-86e5-dd4421ee2b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766944915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.766944915
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.421252448
Short name T240
Test name
Test status
Simulation time 434921031 ps
CPU time 0.63 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:31 PM PDT 24
Peak memory 191960 kb
Host smart-04a547b7-05b4-46d8-a66b-997de2e8fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421252448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.421252448
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3450714691
Short name T49
Test name
Test status
Simulation time 15220564806 ps
CPU time 2.5 seconds
Started Aug 10 04:26:32 PM PDT 24
Finished Aug 10 04:26:35 PM PDT 24
Peak memory 191976 kb
Host smart-809aed97-656f-4e3b-830b-c67e60e48985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450714691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3450714691
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.310242306
Short name T21
Test name
Test status
Simulation time 557799360 ps
CPU time 0.8 seconds
Started Aug 10 04:26:18 PM PDT 24
Finished Aug 10 04:26:19 PM PDT 24
Peak memory 191864 kb
Host smart-8c0685a7-c8d0-44f0-a5c3-d080c92753a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310242306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.310242306
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2331294359
Short name T74
Test name
Test status
Simulation time 36887684709 ps
CPU time 24.73 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:27:14 PM PDT 24
Peak memory 192032 kb
Host smart-5ab3c658-0adf-48f4-9ee6-c0af5eab433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331294359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2331294359
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3964383899
Short name T73
Test name
Test status
Simulation time 402481414 ps
CPU time 1.1 seconds
Started Aug 10 04:26:43 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 191892 kb
Host smart-b1d96ccf-2b4f-48cc-88ad-b9a1ca703d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964383899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3964383899
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2668792713
Short name T216
Test name
Test status
Simulation time 39397865645 ps
CPU time 57.63 seconds
Started Aug 10 04:26:14 PM PDT 24
Finished Aug 10 04:27:12 PM PDT 24
Peak memory 191924 kb
Host smart-9c2992df-9792-4d0b-891a-f3c0d03bf6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668792713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2668792713
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3156384445
Short name T19
Test name
Test status
Simulation time 8037477346 ps
CPU time 12.43 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:26:33 PM PDT 24
Peak memory 215548 kb
Host smart-f3a36940-6c8a-40b6-8371-d0e9ca16485c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156384445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3156384445
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2465857868
Short name T220
Test name
Test status
Simulation time 566544896 ps
CPU time 1.56 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:27 PM PDT 24
Peak memory 191952 kb
Host smart-59cac28b-36ed-44d1-9287-5f87a63c79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465857868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2465857868
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1296746308
Short name T257
Test name
Test status
Simulation time 60613336380 ps
CPU time 82.48 seconds
Started Aug 10 04:26:45 PM PDT 24
Finished Aug 10 04:28:08 PM PDT 24
Peak memory 192024 kb
Host smart-480d3025-011d-46b1-8dfb-60924a06b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296746308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1296746308
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.397173307
Short name T245
Test name
Test status
Simulation time 431607849 ps
CPU time 0.73 seconds
Started Aug 10 04:26:50 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 191928 kb
Host smart-89076ea0-fcfe-4a1a-857d-488ea3a8716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397173307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.397173307
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3189545148
Short name T205
Test name
Test status
Simulation time 646049463 ps
CPU time 1.45 seconds
Started Aug 10 04:26:53 PM PDT 24
Finished Aug 10 04:26:55 PM PDT 24
Peak memory 192060 kb
Host smart-8fceb5cc-cb4b-49bc-b19a-7689b7534705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189545148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3189545148
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3963727227
Short name T22
Test name
Test status
Simulation time 595383857 ps
CPU time 0.59 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 191912 kb
Host smart-fac4c2c8-0fd1-47ba-99b1-53fe3af089bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963727227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3963727227
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3747060456
Short name T197
Test name
Test status
Simulation time 36257716866 ps
CPU time 3.56 seconds
Started Aug 10 04:26:51 PM PDT 24
Finished Aug 10 04:26:55 PM PDT 24
Peak memory 191964 kb
Host smart-9fdf3198-e6e3-4d5c-baf1-dee1d91a2b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747060456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3747060456
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.374010593
Short name T267
Test name
Test status
Simulation time 505269200 ps
CPU time 0.8 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 191908 kb
Host smart-1f3ccdfa-f476-48b3-9cfa-bcedd5b5762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374010593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.374010593
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.645951056
Short name T269
Test name
Test status
Simulation time 1127474878 ps
CPU time 1.47 seconds
Started Aug 10 04:26:45 PM PDT 24
Finished Aug 10 04:26:46 PM PDT 24
Peak memory 196632 kb
Host smart-2b0005cd-da53-4cfc-92de-9d0ab24fcbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645951056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.645951056
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.757279544
Short name T162
Test name
Test status
Simulation time 380456389 ps
CPU time 0.77 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:26:47 PM PDT 24
Peak memory 196848 kb
Host smart-b8ad8d05-8242-4d70-93e8-49bea8216b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757279544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.757279544
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3387219004
Short name T208
Test name
Test status
Simulation time 29849585828 ps
CPU time 12.12 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:27:02 PM PDT 24
Peak memory 191964 kb
Host smart-57d3adf0-65a6-4e84-8b33-e9178065e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387219004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3387219004
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4182281754
Short name T230
Test name
Test status
Simulation time 554080351 ps
CPU time 1.51 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 196756 kb
Host smart-184c84ae-1a3e-47ce-b4d0-8e7b6849c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182281754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4182281754
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2255771510
Short name T209
Test name
Test status
Simulation time 2543286204 ps
CPU time 2.28 seconds
Started Aug 10 04:26:46 PM PDT 24
Finished Aug 10 04:26:48 PM PDT 24
Peak memory 192032 kb
Host smart-7e0f84b7-ade5-4c59-a5d7-8da45a7cb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255771510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2255771510
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2830909229
Short name T224
Test name
Test status
Simulation time 519464734 ps
CPU time 1.39 seconds
Started Aug 10 04:26:51 PM PDT 24
Finished Aug 10 04:26:53 PM PDT 24
Peak memory 191904 kb
Host smart-9a82f57a-5f70-4477-911e-052d2b56f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830909229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2830909229
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2213833804
Short name T280
Test name
Test status
Simulation time 45085384593 ps
CPU time 63.24 seconds
Started Aug 10 04:26:39 PM PDT 24
Finished Aug 10 04:27:43 PM PDT 24
Peak memory 196976 kb
Host smart-99feb99f-8b9e-42ff-8b3f-651ffad2df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213833804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2213833804
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2765573926
Short name T258
Test name
Test status
Simulation time 551841006 ps
CPU time 1.4 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 191968 kb
Host smart-27fbc4c0-1a20-4652-82dc-ae632f5b3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765573926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2765573926
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.851774390
Short name T266
Test name
Test status
Simulation time 15364185831 ps
CPU time 6.37 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:26:55 PM PDT 24
Peak memory 192016 kb
Host smart-3c0e125c-6032-4ed7-9059-cf882911be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851774390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.851774390
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3114371443
Short name T1
Test name
Test status
Simulation time 607940344 ps
CPU time 1.38 seconds
Started Aug 10 04:26:50 PM PDT 24
Finished Aug 10 04:26:52 PM PDT 24
Peak memory 196724 kb
Host smart-f1b2107d-ef4c-4be9-94bc-4bb4bb3a51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114371443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3114371443
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2809210100
Short name T250
Test name
Test status
Simulation time 36316404827 ps
CPU time 51.79 seconds
Started Aug 10 04:26:54 PM PDT 24
Finished Aug 10 04:27:46 PM PDT 24
Peak memory 197040 kb
Host smart-7201261e-1f47-4cdf-8864-ad406ee52ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809210100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2809210100
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2634559142
Short name T253
Test name
Test status
Simulation time 565230766 ps
CPU time 1.3 seconds
Started Aug 10 04:26:50 PM PDT 24
Finished Aug 10 04:26:51 PM PDT 24
Peak memory 191968 kb
Host smart-781f12e6-7db5-4425-aee3-3aab4707897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634559142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2634559142
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4725607
Short name T243
Test name
Test status
Simulation time 4301511898 ps
CPU time 2.1 seconds
Started Aug 10 04:26:38 PM PDT 24
Finished Aug 10 04:26:40 PM PDT 24
Peak memory 192028 kb
Host smart-169c1e16-1418-4692-9b62-ef02eba64e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4725607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4725607
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4036670043
Short name T229
Test name
Test status
Simulation time 375745360 ps
CPU time 0.86 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 191896 kb
Host smart-e570a555-4543-48be-8ff9-558973936c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036670043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4036670043
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3828717114
Short name T196
Test name
Test status
Simulation time 29488147372 ps
CPU time 11.46 seconds
Started Aug 10 04:26:14 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 192024 kb
Host smart-9ae4901e-7e20-4b3e-9fa4-6e9c71966c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828717114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3828717114
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2957782805
Short name T260
Test name
Test status
Simulation time 610915905 ps
CPU time 0.77 seconds
Started Aug 10 04:26:06 PM PDT 24
Finished Aug 10 04:26:07 PM PDT 24
Peak memory 196872 kb
Host smart-13b1b23e-8488-4473-888b-a59b1ac05480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957782805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2957782805
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1958010877
Short name T15
Test name
Test status
Simulation time 210135543128 ps
CPU time 119.43 seconds
Started Aug 10 04:26:27 PM PDT 24
Finished Aug 10 04:28:26 PM PDT 24
Peak memory 198428 kb
Host smart-8c26d717-c241-42ef-a1d5-f5089da1ef7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958010877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1958010877
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1260337751
Short name T246
Test name
Test status
Simulation time 23638665088 ps
CPU time 9.3 seconds
Started Aug 10 04:26:47 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 191936 kb
Host smart-8e8a5f2c-2b4a-442f-8dce-2b984aae0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260337751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1260337751
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3153721954
Short name T48
Test name
Test status
Simulation time 400942431 ps
CPU time 0.69 seconds
Started Aug 10 04:26:48 PM PDT 24
Finished Aug 10 04:26:49 PM PDT 24
Peak memory 191964 kb
Host smart-ad3978de-a905-4046-aee3-060b566ba279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153721954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3153721954
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2872137261
Short name T180
Test name
Test status
Simulation time 544571175 ps
CPU time 0.79 seconds
Started Aug 10 04:26:48 PM PDT 24
Finished Aug 10 04:26:49 PM PDT 24
Peak memory 196564 kb
Host smart-30b8b797-701c-4369-8048-ae1d0d8f5257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872137261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2872137261
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.429939148
Short name T199
Test name
Test status
Simulation time 59139296587 ps
CPU time 87.8 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:28:25 PM PDT 24
Peak memory 192084 kb
Host smart-dde19cf5-ed30-45c6-94f0-0846fd1a03c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429939148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.429939148
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.593699202
Short name T255
Test name
Test status
Simulation time 454630242 ps
CPU time 1.15 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:27:01 PM PDT 24
Peak memory 191944 kb
Host smart-00738cb9-eee1-47b3-bcc9-4d63d124915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593699202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.593699202
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.102323710
Short name T282
Test name
Test status
Simulation time 19041018250 ps
CPU time 28.04 seconds
Started Aug 10 04:27:02 PM PDT 24
Finished Aug 10 04:27:30 PM PDT 24
Peak memory 196928 kb
Host smart-a170532a-9304-4ac1-a48a-004fff926b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102323710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.102323710
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3274665128
Short name T233
Test name
Test status
Simulation time 419872428 ps
CPU time 1.15 seconds
Started Aug 10 04:26:55 PM PDT 24
Finished Aug 10 04:26:56 PM PDT 24
Peak memory 191924 kb
Host smart-cd2f155e-69a6-4502-b259-f5350de5eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274665128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3274665128
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2320835228
Short name T227
Test name
Test status
Simulation time 12782842533 ps
CPU time 18.42 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:27:19 PM PDT 24
Peak memory 192060 kb
Host smart-f7aa401b-c567-4464-b067-5336743a31d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320835228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2320835228
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4169642328
Short name T272
Test name
Test status
Simulation time 607202914 ps
CPU time 0.71 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 196736 kb
Host smart-a22d073b-68cc-4d60-934b-1d48afac542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169642328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4169642328
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3644590641
Short name T226
Test name
Test status
Simulation time 38720981050 ps
CPU time 30.54 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:30 PM PDT 24
Peak memory 191900 kb
Host smart-7668969c-75f7-4d0a-ad9c-3f3502ea723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644590641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3644590641
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.725594729
Short name T206
Test name
Test status
Simulation time 488413267 ps
CPU time 1.37 seconds
Started Aug 10 04:26:49 PM PDT 24
Finished Aug 10 04:26:50 PM PDT 24
Peak memory 191916 kb
Host smart-e5bdfb4e-d5bd-4232-8f7f-32725f1451e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725594729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.725594729
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2499355213
Short name T3
Test name
Test status
Simulation time 50177337740 ps
CPU time 412.01 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:33:50 PM PDT 24
Peak memory 200112 kb
Host smart-ea4848b5-9081-4700-9fab-634eed7bd9c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499355213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2499355213
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1190106571
Short name T248
Test name
Test status
Simulation time 58187229662 ps
CPU time 39.54 seconds
Started Aug 10 04:27:04 PM PDT 24
Finished Aug 10 04:27:44 PM PDT 24
Peak memory 192024 kb
Host smart-cc775c62-2603-41c2-9417-c0ce3cb57e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190106571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1190106571
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.503426811
Short name T203
Test name
Test status
Simulation time 461855896 ps
CPU time 0.66 seconds
Started Aug 10 04:26:57 PM PDT 24
Finished Aug 10 04:26:58 PM PDT 24
Peak memory 191940 kb
Host smart-0dc75354-5c75-4a00-a4ff-9d335c834f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503426811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.503426811
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2090763010
Short name T261
Test name
Test status
Simulation time 15113729272 ps
CPU time 5.73 seconds
Started Aug 10 04:26:56 PM PDT 24
Finished Aug 10 04:27:02 PM PDT 24
Peak memory 197004 kb
Host smart-6ba49495-1104-4f81-8ea5-e6f4fab95186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090763010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2090763010
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4083221348
Short name T268
Test name
Test status
Simulation time 473476712 ps
CPU time 1.25 seconds
Started Aug 10 04:27:05 PM PDT 24
Finished Aug 10 04:27:07 PM PDT 24
Peak memory 191952 kb
Host smart-4fe0fba8-daf2-46df-aa1a-ceda057247cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083221348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4083221348
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.232290173
Short name T47
Test name
Test status
Simulation time 3883249556 ps
CPU time 6.57 seconds
Started Aug 10 04:27:00 PM PDT 24
Finished Aug 10 04:27:07 PM PDT 24
Peak memory 192120 kb
Host smart-729b287f-73b8-4eee-84b7-735e6ddab7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232290173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.232290173
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1038709503
Short name T281
Test name
Test status
Simulation time 616515970 ps
CPU time 1.42 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 196696 kb
Host smart-6a742c7f-4220-4ecd-83a3-c2e8fb055e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038709503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1038709503
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1223535840
Short name T207
Test name
Test status
Simulation time 1828272009 ps
CPU time 1.21 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:27:00 PM PDT 24
Peak memory 192060 kb
Host smart-e14c0d37-14ae-4456-a3a0-829f1867545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223535840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1223535840
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1024364164
Short name T239
Test name
Test status
Simulation time 641155531 ps
CPU time 0.72 seconds
Started Aug 10 04:26:58 PM PDT 24
Finished Aug 10 04:26:59 PM PDT 24
Peak memory 191920 kb
Host smart-42b60a67-e8aa-48fa-88c3-acd91e99f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024364164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1024364164
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.319736110
Short name T265
Test name
Test status
Simulation time 53356153869 ps
CPU time 74.99 seconds
Started Aug 10 04:26:59 PM PDT 24
Finished Aug 10 04:28:14 PM PDT 24
Peak memory 192004 kb
Host smart-fcea3f4e-122f-40c8-9755-6aa050230755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319736110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.319736110
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1402550831
Short name T263
Test name
Test status
Simulation time 504349662 ps
CPU time 0.89 seconds
Started Aug 10 04:26:51 PM PDT 24
Finished Aug 10 04:26:52 PM PDT 24
Peak memory 191964 kb
Host smart-c0f69867-a2d9-432a-90fc-66d4554ab1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402550831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1402550831
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2305104260
Short name T234
Test name
Test status
Simulation time 11353962673 ps
CPU time 18.86 seconds
Started Aug 10 04:26:08 PM PDT 24
Finished Aug 10 04:26:27 PM PDT 24
Peak memory 196984 kb
Host smart-f02a6f9f-ecf9-43da-bff9-ee623c40b053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305104260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2305104260
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1161100137
Short name T14
Test name
Test status
Simulation time 555323435 ps
CPU time 0.66 seconds
Started Aug 10 04:26:15 PM PDT 24
Finished Aug 10 04:26:16 PM PDT 24
Peak memory 191952 kb
Host smart-de78a496-90b1-4a8c-8d7e-f84f13b79119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161100137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1161100137
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2748944868
Short name T236
Test name
Test status
Simulation time 49956133711 ps
CPU time 61.05 seconds
Started Aug 10 04:26:03 PM PDT 24
Finished Aug 10 04:27:05 PM PDT 24
Peak memory 192016 kb
Host smart-01a21e5a-3d80-4eb2-b0b5-f402880ef0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748944868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2748944868
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.30444268
Short name T219
Test name
Test status
Simulation time 441435025 ps
CPU time 0.7 seconds
Started Aug 10 04:26:25 PM PDT 24
Finished Aug 10 04:26:26 PM PDT 24
Peak memory 196792 kb
Host smart-c442871b-ca99-417e-b621-26271c5617e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30444268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.30444268
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1466057691
Short name T271
Test name
Test status
Simulation time 14141271023 ps
CPU time 4.64 seconds
Started Aug 10 04:26:24 PM PDT 24
Finished Aug 10 04:26:29 PM PDT 24
Peak memory 192032 kb
Host smart-602ad7b0-d9e0-45d4-8bc4-30f45521a725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466057691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1466057691
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2332652871
Short name T202
Test name
Test status
Simulation time 516680048 ps
CPU time 0.72 seconds
Started Aug 10 04:26:10 PM PDT 24
Finished Aug 10 04:26:11 PM PDT 24
Peak memory 191948 kb
Host smart-50153a38-c73a-44cb-a3be-65db61fd0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332652871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2332652871
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2322532137
Short name T221
Test name
Test status
Simulation time 17296212012 ps
CPU time 1.88 seconds
Started Aug 10 04:26:36 PM PDT 24
Finished Aug 10 04:26:38 PM PDT 24
Peak memory 192000 kb
Host smart-178a93ea-3d09-49d5-aac7-ae836b2dd4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322532137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2322532137
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3641534117
Short name T215
Test name
Test status
Simulation time 527531013 ps
CPU time 0.64 seconds
Started Aug 10 04:26:31 PM PDT 24
Finished Aug 10 04:26:32 PM PDT 24
Peak memory 191928 kb
Host smart-5c2deb09-d7f1-4898-b1ea-2a205b607f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641534117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3641534117
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.615326827
Short name T85
Test name
Test status
Simulation time 66133050193 ps
CPU time 420.07 seconds
Started Aug 10 04:26:21 PM PDT 24
Finished Aug 10 04:33:21 PM PDT 24
Peak memory 209776 kb
Host smart-dd561bc1-6912-4393-b9f6-90c9a24a568f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615326827 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.615326827
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2153001678
Short name T262
Test name
Test status
Simulation time 2920063371 ps
CPU time 4.53 seconds
Started Aug 10 04:26:29 PM PDT 24
Finished Aug 10 04:26:33 PM PDT 24
Peak memory 191964 kb
Host smart-667ddadf-8722-48d7-bb26-2c61b76ed468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153001678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2153001678
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3262495172
Short name T277
Test name
Test status
Simulation time 527897232 ps
CPU time 0.71 seconds
Started Aug 10 04:26:34 PM PDT 24
Finished Aug 10 04:26:35 PM PDT 24
Peak memory 196740 kb
Host smart-ab83909b-8703-4242-80bc-3400cdebb6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262495172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3262495172
Directory /workspace/9.aon_timer_smoke/latest
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