Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29687	1		T1	136		T2	73		T3	194
bark[1]	423	1		T1	26		T13	26		T42	21
bark[2]	421	1		T4	45		T13	36		T112	54
bark[3]	551	1		T122	14		T61	30		T49	21
bark[4]	610	1		T1	21		T4	21		T126	14
bark[5]	463	1		T4	21		T42	72		T164	21
bark[6]	1077	1		T12	14		T45	14		T39	205
bark[7]	884	1		T3	64		T138	21		T40	231
bark[8]	565	1		T138	66		T29	94		T105	30
bark[9]	517	1		T135	14		T163	14		T41	93
bark[10]	321	1		T29	21		T105	40		T43	21
bark[11]	516	1		T1	21		T43	171		T21	14
bark[12]	1090	1		T3	68		T38	147		T29	21
bark[13]	591	1		T8	21		T12	26		T13	21
bark[14]	411	1		T3	64		T19	124		T196	14
bark[15]	602	1		T105	31		T188	14		T119	14
bark[16]	355	1		T12	21		T43	21		T94	168
bark[17]	278	1		T3	45		T38	21		T80	107
bark[18]	575	1		T7	21		T103	14		T40	26
bark[19]	731	1		T3	245		T27	39		T184	14
bark[20]	1079	1		T1	47		T11	21		T38	90
bark[21]	404	1		T2	66		T3	235		T27	21
bark[22]	325	1		T2	47		T11	21		T138	21
bark[23]	507	1		T2	78		T186	14		T43	21
bark[24]	391	1		T7	21		T192	14		T41	142
bark[25]	1403	1		T1	14		T28	14		T40	7
bark[26]	440	1		T7	28		T41	30		T24	43
bark[27]	227	1		T4	26		T39	69		T94	43
bark[28]	553	1		T4	128		T13	160		T29	26
bark[29]	505	1		T11	21		T13	143		T170	40
bark[30]	248	1		T27	21		T29	26		T183	14
bark[31]	372	1		T39	253		T163	21		T128	21
bark_0	4804	1		T1	7		T2	7		T3	140

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28478	1		T1	136		T2	72		T3	190
bite[1]	792	1		T39	68		T119	21		T93	21
bite[2]	640	1		T1	47		T38	146		T28	13
bite[3]	478	1		T7	21		T13	159		T27	21
bite[4]	568	1		T138	76		T184	13		T128	13
bite[5]	380	1		T1	26		T4	26		T11	21
bite[6]	340	1		T29	93		T163	30		T43	21
bite[7]	870	1		T3	234		T4	127		T8	21
bite[8]	983	1		T3	98		T11	21		T138	21
bite[9]	564	1		T2	26		T29	21		T105	30
bite[10]	342	1		T38	231		T172	13		T119	13
bite[11]	557	1		T138	21		T135	13		T183	13
bite[12]	898	1		T26	30		T113	26		T161	81
bite[13]	330	1		T2	45		T13	21		T42	30
bite[14]	803	1		T29	195		T40	21		T141	30
bite[15]	430	1		T27	39		T154	13		T97	69
bite[16]	436	1		T2	21		T43	170		T177	13
bite[17]	198	1		T1	13		T12	13		T40	6
bite[18]	594	1		T29	51		T105	40		T113	88
bite[19]	812	1		T3	244		T29	21		T93	21
bite[20]	548	1		T2	21		T4	21		T13	142
bite[21]	565	1		T39	204		T21	13		T93	101
bite[22]	465	1		T7	27		T26	21		T136	21
bite[23]	461	1		T3	63		T12	21		T27	21
bite[24]	332	1		T1	21		T141	38		T128	21
bite[25]	587	1		T4	44		T7	21		T103	13
bite[26]	1009	1		T11	21		T13	26		T39	252
bite[27]	752	1		T3	44		T13	36		T45	13
bite[28]	751	1		T41	92		T42	46		T43	21
bite[29]	691	1		T2	78		T3	67		T112	54
bite[30]	599	1		T1	21		T12	26		T38	89
bite[31]	342	1		T38	21		T174	13		T43	21
bite_0	5331	1		T1	8		T2	8		T3	115

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	44404	1		T1	187		T2	271		T3	787
auto[1]	7522	1		T1	85		T3	268		T4	231

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	674	1		T1	40		T204	9		T19	83
prescale[1]	880	1		T4	37		T7	53		T11	19
prescale[2]	1245	1		T3	126		T40	50		T205	9
prescale[3]	814	1		T2	24		T8	40		T11	9
prescale[4]	563	1		T4	83		T11	19		T27	44
prescale[5]	570	1		T39	41		T40	26		T41	2
prescale[6]	593	1		T2	57		T27	19		T42	49
prescale[7]	702	1		T2	9		T7	28		T13	19
prescale[8]	987	1		T4	95		T7	37		T38	19
prescale[9]	852	1		T8	35		T39	19		T29	19
prescale[10]	921	1		T1	19		T13	2		T27	14
prescale[11]	887	1		T3	36		T4	149		T11	28
prescale[12]	628	1		T2	19		T3	2		T27	19
prescale[13]	895	1		T3	2		T4	40		T12	66
prescale[14]	804	1		T4	110		T38	4		T29	40
prescale[15]	594	1		T1	32		T38	19		T29	38
prescale[16]	385	1		T4	2		T27	19		T38	2
prescale[17]	1340	1		T4	19		T138	9		T39	2
prescale[18]	966	1		T3	59		T29	2		T41	43
prescale[19]	856	1		T3	23		T11	23		T13	63
prescale[20]	718	1		T13	49		T44	9		T29	28
prescale[21]	681	1		T13	9		T38	12		T40	86
prescale[22]	782	1		T138	23		T29	49		T19	92
prescale[23]	417	1		T12	58		T47	9		T39	19
prescale[24]	670	1		T3	2		T10	9		T12	19
prescale[25]	1153	1		T3	40		T138	19		T39	96
prescale[26]	854	1		T3	25		T38	2		T40	33
prescale[27]	619	1		T3	2		T4	19		T6	9
prescale[28]	897	1		T4	40		T7	65		T13	42
prescale[29]	596	1		T3	19		T8	49		T39	57
prescale[30]	444	1		T3	19		T206	9		T29	30
prescale[31]	1285	1		T3	45		T4	129		T38	159
prescale_0	26654	1		T1	181		T2	162		T3	655

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39278	1		T1	163		T2	203		T3	874
auto[1]	12648	1		T1	109		T2	68		T3	181

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51926	1		T1	272		T2	271		T3	1055

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30299	1		T1	184		T2	111		T3	493
wkup[1]	286	1		T1	15		T3	21		T7	21
wkup[2]	192	1		T13	21		T38	21		T19	6
wkup[3]	361	1		T13	30		T112	21		T19	25
wkup[4]	250	1		T2	45		T3	21		T40	21
wkup[5]	165	1		T126	15		T43	36		T26	21
wkup[6]	442	1		T3	42		T4	26		T12	26
wkup[7]	252	1		T112	30		T43	42		T133	15
wkup[8]	270	1		T3	21		T13	36		T105	30
wkup[9]	183	1		T42	8		T128	21		T196	15
wkup[10]	170	1		T138	21		T19	21		T120	26
wkup[11]	293	1		T11	21		T13	44		T38	21
wkup[12]	165	1		T11	21		T39	21		T174	15
wkup[13]	381	1		T27	39		T183	15		T143	42
wkup[14]	348	1		T11	21		T40	21		T43	26
wkup[15]	362	1		T105	21		T43	21		T24	21
wkup[16]	398	1		T4	21		T29	30		T105	40
wkup[17]	233	1		T112	21		T43	21		T119	21
wkup[18]	246	1		T42	30		T43	31		T170	21
wkup[19]	318	1		T1	21		T3	21		T159	21
wkup[20]	354	1		T2	21		T13	26		T39	21
wkup[21]	358	1		T3	42		T4	21		T138	30
wkup[22]	386	1		T7	29		T12	30		T13	21
wkup[23]	206	1		T29	21		T43	8		T128	21
wkup[24]	131	1		T3	21		T130	21		T176	21
wkup[25]	288	1		T38	21		T138	21		T43	21
wkup[26]	246	1		T3	21		T12	15		T39	26
wkup[27]	299	1		T2	21		T3	21		T39	21
wkup[28]	131	1		T93	26		T152	21		T143	21
wkup[29]	286	1		T1	21		T2	21		T141	21
wkup[30]	229	1		T123	33		T96	30		T176	52
wkup[31]	328	1		T8	21		T38	21		T141	30
wkup[32]	122	1		T29	30		T43	21		T123	21
wkup[33]	167	1		T42	21		T43	30		T161	21
wkup[34]	320	1		T4	24		T38	21		T42	21
wkup[35]	324	1		T38	21		T29	21		T186	15
wkup[36]	180	1		T138	21		T40	21		T48	34
wkup[37]	372	1		T2	26		T3	21		T13	26
wkup[38]	240	1		T3	21		T28	15		T113	21
wkup[39]	246	1		T135	15		T29	30		T26	21
wkup[40]	264	1		T45	15		T19	30		T98	21
wkup[41]	282	1		T43	21		T128	21		T93	21
wkup[42]	188	1		T19	21		T175	26		T127	21
wkup[43]	324	1		T8	21		T192	15		T39	21
wkup[44]	411	1		T2	21		T3	21		T4	21
wkup[45]	338	1		T3	8		T27	21		T29	26
wkup[46]	344	1		T40	21		T184	15		T42	21
wkup[47]	291	1		T29	26		T43	21		T94	21
wkup[48]	325	1		T3	21		T93	30		T130	21
wkup[49]	370	1		T3	31		T4	21		T8	21
wkup[50]	201	1		T13	30		T38	42		T163	15
wkup[51]	277	1		T4	26		T13	21		T27	21
wkup[52]	347	1		T3	29		T7	21		T41	21
wkup[53]	365	1		T3	21		T41	21		T43	21
wkup[54]	290	1		T138	21		T43	21		T26	21
wkup[55]	376	1		T40	21		T42	21		T26	15
wkup[56]	251	1		T1	26		T4	21		T103	15
wkup[57]	373	1		T3	26		T105	21		T113	21
wkup[58]	426	1		T4	21		T138	21		T41	30
wkup[59]	242	1		T39	21		T41	30		T128	21
wkup[60]	233	1		T42	21		T43	21		T94	21
wkup[61]	301	1		T3	31		T4	21		T13	21
wkup[62]	298	1		T8	30		T29	21		T19	50
wkup[63]	210	1		T29	21		T132	15		T119	15
wkup_0	3772	1		T1	5		T2	5		T3	101