Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.09 99.33 93.67 100.00 98.40 99.51 49.61


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T285 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1905812196 Aug 11 05:17:41 PM PDT 24 Aug 11 05:17:42 PM PDT 24 478394885 ps
T31 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3557627664 Aug 11 05:17:23 PM PDT 24 Aug 11 05:17:24 PM PDT 24 2211432943 ps
T36 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3085000176 Aug 11 05:16:55 PM PDT 24 Aug 11 05:16:56 PM PDT 24 432879609 ps
T37 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1577358986 Aug 11 05:17:04 PM PDT 24 Aug 11 05:17:06 PM PDT 24 339720373 ps
T32 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3804988088 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:29 PM PDT 24 2741543292 ps
T86 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2424371534 Aug 11 05:16:43 PM PDT 24 Aug 11 05:16:45 PM PDT 24 303797434 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2894045403 Aug 11 05:16:41 PM PDT 24 Aug 11 05:16:51 PM PDT 24 5962140203 ps
T286 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.664010447 Aug 11 05:17:07 PM PDT 24 Aug 11 05:17:08 PM PDT 24 511425096 ps
T287 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3999513329 Aug 11 05:17:52 PM PDT 24 Aug 11 05:17:53 PM PDT 24 503526511 ps
T288 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3273207361 Aug 11 05:17:28 PM PDT 24 Aug 11 05:17:29 PM PDT 24 310049219 ps
T33 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.965756991 Aug 11 05:17:12 PM PDT 24 Aug 11 05:17:20 PM PDT 24 4344860551 ps
T289 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.734110261 Aug 11 05:17:56 PM PDT 24 Aug 11 05:17:57 PM PDT 24 335011338 ps
T290 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.473323655 Aug 11 05:17:22 PM PDT 24 Aug 11 05:17:23 PM PDT 24 474260390 ps
T87 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.895193219 Aug 11 05:16:44 PM PDT 24 Aug 11 05:16:46 PM PDT 24 1490535513 ps
T291 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1300160500 Aug 11 05:17:34 PM PDT 24 Aug 11 05:17:35 PM PDT 24 491114321 ps
T88 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.736297894 Aug 11 05:17:01 PM PDT 24 Aug 11 05:17:04 PM PDT 24 1343005413 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2988478301 Aug 11 05:17:00 PM PDT 24 Aug 11 05:17:04 PM PDT 24 535034393 ps
T207 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.696758593 Aug 11 05:17:12 PM PDT 24 Aug 11 05:17:14 PM PDT 24 383383100 ps
T293 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3328391384 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 528590713 ps
T294 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3233453706 Aug 11 05:17:03 PM PDT 24 Aug 11 05:17:04 PM PDT 24 346956413 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2973740370 Aug 11 05:16:49 PM PDT 24 Aug 11 05:16:52 PM PDT 24 599763276 ps
T296 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.936564554 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:44 PM PDT 24 483792252 ps
T89 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1038619099 Aug 11 05:16:17 PM PDT 24 Aug 11 05:16:18 PM PDT 24 2493159346 ps
T297 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1220065679 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 531193640 ps
T34 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3957117370 Aug 11 05:16:18 PM PDT 24 Aug 11 05:16:24 PM PDT 24 4345697704 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1581347705 Aug 11 05:16:57 PM PDT 24 Aug 11 05:16:58 PM PDT 24 375359003 ps
T55 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.215751257 Aug 11 05:17:35 PM PDT 24 Aug 11 05:17:36 PM PDT 24 378651866 ps
T299 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.237077281 Aug 11 05:17:21 PM PDT 24 Aug 11 05:17:22 PM PDT 24 447702098 ps
T300 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2938585808 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:44 PM PDT 24 317587714 ps
T35 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3241895628 Aug 11 05:17:24 PM PDT 24 Aug 11 05:17:28 PM PDT 24 4401153160 ps
T90 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2548133922 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:28 PM PDT 24 376434072 ps
T200 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1891053633 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:40 PM PDT 24 7817372730 ps
T301 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2980456187 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:10 PM PDT 24 545241500 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2026855377 Aug 11 05:16:42 PM PDT 24 Aug 11 05:16:44 PM PDT 24 381318737 ps
T303 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1328350774 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:45 PM PDT 24 333228204 ps
T304 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1601068514 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:46 PM PDT 24 439696620 ps
T305 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.214260919 Aug 11 05:16:44 PM PDT 24 Aug 11 05:16:45 PM PDT 24 390655596 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3259642967 Aug 11 05:17:15 PM PDT 24 Aug 11 05:17:17 PM PDT 24 4431899108 ps
T307 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.480701012 Aug 11 05:16:52 PM PDT 24 Aug 11 05:16:53 PM PDT 24 361695903 ps
T91 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.188387282 Aug 11 05:16:56 PM PDT 24 Aug 11 05:16:57 PM PDT 24 1517175855 ps
T92 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3947961878 Aug 11 05:17:33 PM PDT 24 Aug 11 05:17:37 PM PDT 24 1459462036 ps
T308 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1456831306 Aug 11 05:17:02 PM PDT 24 Aug 11 05:17:04 PM PDT 24 547285050 ps
T309 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2845425204 Aug 11 05:17:52 PM PDT 24 Aug 11 05:17:53 PM PDT 24 453926485 ps
T310 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.225914629 Aug 11 05:17:15 PM PDT 24 Aug 11 05:17:17 PM PDT 24 698991291 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1127278470 Aug 11 05:16:25 PM PDT 24 Aug 11 05:16:27 PM PDT 24 532745477 ps
T311 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4102663602 Aug 11 05:16:23 PM PDT 24 Aug 11 05:16:25 PM PDT 24 358697240 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2822667559 Aug 11 05:16:42 PM PDT 24 Aug 11 05:16:43 PM PDT 24 367440996 ps
T313 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3776560441 Aug 11 05:17:39 PM PDT 24 Aug 11 05:17:41 PM PDT 24 335411818 ps
T314 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2807143839 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:46 PM PDT 24 442041540 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3776679666 Aug 11 05:16:05 PM PDT 24 Aug 11 05:16:13 PM PDT 24 8515046291 ps
T316 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.642584290 Aug 11 05:17:25 PM PDT 24 Aug 11 05:17:28 PM PDT 24 4468782095 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3777382614 Aug 11 05:16:32 PM PDT 24 Aug 11 05:16:32 PM PDT 24 489102321 ps
T203 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3186480445 Aug 11 05:16:44 PM PDT 24 Aug 11 05:16:46 PM PDT 24 9608481741 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1510840801 Aug 11 05:17:39 PM PDT 24 Aug 11 05:17:40 PM PDT 24 384295556 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1090958746 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:41 PM PDT 24 413869535 ps
T320 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1932384815 Aug 11 05:16:05 PM PDT 24 Aug 11 05:16:08 PM PDT 24 467664435 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3583631724 Aug 11 05:16:30 PM PDT 24 Aug 11 05:16:31 PM PDT 24 504125379 ps
T322 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2974077930 Aug 11 05:17:17 PM PDT 24 Aug 11 05:17:19 PM PDT 24 557903901 ps
T323 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4044020590 Aug 11 05:17:43 PM PDT 24 Aug 11 05:17:44 PM PDT 24 416804854 ps
T324 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1975985374 Aug 11 05:16:24 PM PDT 24 Aug 11 05:16:28 PM PDT 24 7326325619 ps
T71 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.555651102 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:28 PM PDT 24 495229595 ps
T201 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3322365237 Aug 11 05:16:50 PM PDT 24 Aug 11 05:16:54 PM PDT 24 8204976581 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.12865412 Aug 11 05:17:39 PM PDT 24 Aug 11 05:17:40 PM PDT 24 312408781 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2362736104 Aug 11 05:16:32 PM PDT 24 Aug 11 05:16:37 PM PDT 24 7746412281 ps
T327 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3411666788 Aug 11 05:17:41 PM PDT 24 Aug 11 05:17:46 PM PDT 24 2800579169 ps
T72 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2477281547 Aug 11 05:17:00 PM PDT 24 Aug 11 05:17:01 PM PDT 24 340480914 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1948116032 Aug 11 05:16:49 PM PDT 24 Aug 11 05:16:51 PM PDT 24 1333515635 ps
T328 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.323241079 Aug 11 05:17:26 PM PDT 24 Aug 11 05:17:27 PM PDT 24 537878013 ps
T329 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2931457449 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:40 PM PDT 24 544041572 ps
T330 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3181956502 Aug 11 05:17:51 PM PDT 24 Aug 11 05:17:52 PM PDT 24 269615037 ps
T331 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1867283518 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 671657228 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.595250449 Aug 11 05:16:23 PM PDT 24 Aug 11 05:16:24 PM PDT 24 738052300 ps
T333 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2503418481 Aug 11 05:17:54 PM PDT 24 Aug 11 05:17:55 PM PDT 24 269633715 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2804600177 Aug 11 05:17:20 PM PDT 24 Aug 11 05:17:21 PM PDT 24 301963243 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1309299770 Aug 11 05:16:38 PM PDT 24 Aug 11 05:16:39 PM PDT 24 1244337394 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1476625340 Aug 11 05:17:06 PM PDT 24 Aug 11 05:17:09 PM PDT 24 546298202 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3813530951 Aug 11 05:16:03 PM PDT 24 Aug 11 05:16:04 PM PDT 24 486738607 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3068234392 Aug 11 05:17:39 PM PDT 24 Aug 11 05:17:46 PM PDT 24 7523512195 ps
T339 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.479972865 Aug 11 05:17:50 PM PDT 24 Aug 11 05:17:52 PM PDT 24 441011730 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1926724124 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:09 PM PDT 24 327030759 ps
T341 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1715236566 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 378060546 ps
T342 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3753236204 Aug 11 05:17:34 PM PDT 24 Aug 11 05:17:36 PM PDT 24 358023021 ps
T343 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.819235409 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:46 PM PDT 24 516459891 ps
T344 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1633342011 Aug 11 05:16:05 PM PDT 24 Aug 11 05:16:06 PM PDT 24 521613893 ps
T76 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1874868056 Aug 11 05:16:49 PM PDT 24 Aug 11 05:16:49 PM PDT 24 330582837 ps
T345 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2416052284 Aug 11 05:17:42 PM PDT 24 Aug 11 05:17:43 PM PDT 24 437232055 ps
T346 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.17102655 Aug 11 05:17:28 PM PDT 24 Aug 11 05:17:29 PM PDT 24 688429648 ps
T347 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1149611014 Aug 11 05:17:32 PM PDT 24 Aug 11 05:17:34 PM PDT 24 1715788328 ps
T348 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1737763116 Aug 11 05:17:53 PM PDT 24 Aug 11 05:17:53 PM PDT 24 489816619 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3155254571 Aug 11 05:16:08 PM PDT 24 Aug 11 05:16:09 PM PDT 24 506715498 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2296957323 Aug 11 05:16:45 PM PDT 24 Aug 11 05:16:46 PM PDT 24 495625030 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2476258989 Aug 11 05:17:41 PM PDT 24 Aug 11 05:17:43 PM PDT 24 1336591472 ps
T351 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2802893769 Aug 11 05:17:34 PM PDT 24 Aug 11 05:17:35 PM PDT 24 517327771 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3311371935 Aug 11 05:17:26 PM PDT 24 Aug 11 05:17:27 PM PDT 24 560644197 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2097481717 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:10 PM PDT 24 3212788147 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2292569870 Aug 11 05:16:31 PM PDT 24 Aug 11 05:16:32 PM PDT 24 441272910 ps
T355 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3878940750 Aug 11 05:17:34 PM PDT 24 Aug 11 05:17:35 PM PDT 24 327579800 ps
T356 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1141095260 Aug 11 05:17:48 PM PDT 24 Aug 11 05:17:48 PM PDT 24 555156847 ps
T357 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3365902512 Aug 11 05:17:05 PM PDT 24 Aug 11 05:17:06 PM PDT 24 540569051 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3078622573 Aug 11 05:16:30 PM PDT 24 Aug 11 05:16:32 PM PDT 24 434791858 ps
T359 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1392647278 Aug 11 05:16:11 PM PDT 24 Aug 11 05:16:12 PM PDT 24 548990011 ps
T360 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2506227289 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:43 PM PDT 24 1107370538 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3206671901 Aug 11 05:16:17 PM PDT 24 Aug 11 05:16:18 PM PDT 24 296876339 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3522892620 Aug 11 05:16:31 PM PDT 24 Aug 11 05:16:32 PM PDT 24 1162297779 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1785871228 Aug 11 05:17:14 PM PDT 24 Aug 11 05:17:16 PM PDT 24 1321478883 ps
T364 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2430058562 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:41 PM PDT 24 518441627 ps
T365 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3555502775 Aug 11 05:17:41 PM PDT 24 Aug 11 05:17:42 PM PDT 24 620879538 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1646096406 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:28 PM PDT 24 385969925 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3386857273 Aug 11 05:16:10 PM PDT 24 Aug 11 05:16:12 PM PDT 24 870449963 ps
T367 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1692950439 Aug 11 05:17:21 PM PDT 24 Aug 11 05:17:27 PM PDT 24 4405784101 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2291576359 Aug 11 05:17:26 PM PDT 24 Aug 11 05:17:33 PM PDT 24 2849749114 ps
T369 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2977066640 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:45 PM PDT 24 300423852 ps
T370 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.864073358 Aug 11 05:17:44 PM PDT 24 Aug 11 05:17:45 PM PDT 24 289415244 ps
T202 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3446466638 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:53 PM PDT 24 8419444411 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.200238325 Aug 11 05:16:23 PM PDT 24 Aug 11 05:16:24 PM PDT 24 1219779645 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3858298483 Aug 11 05:16:56 PM PDT 24 Aug 11 05:16:57 PM PDT 24 265194011 ps
T373 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3535901062 Aug 11 05:17:21 PM PDT 24 Aug 11 05:17:26 PM PDT 24 2441034383 ps
T374 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1743177685 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 331614504 ps
T375 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3768677477 Aug 11 05:17:02 PM PDT 24 Aug 11 05:17:03 PM PDT 24 378466617 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1531145400 Aug 11 05:16:10 PM PDT 24 Aug 11 05:16:29 PM PDT 24 13683966390 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1461584320 Aug 11 05:17:20 PM PDT 24 Aug 11 05:17:23 PM PDT 24 514891847 ps
T378 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.125108605 Aug 11 05:17:57 PM PDT 24 Aug 11 05:17:58 PM PDT 24 314958434 ps
T379 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.388412334 Aug 11 05:17:27 PM PDT 24 Aug 11 05:17:29 PM PDT 24 385286160 ps
T380 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2123941828 Aug 11 05:17:32 PM PDT 24 Aug 11 05:17:34 PM PDT 24 338992135 ps
T381 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3925441579 Aug 11 05:17:52 PM PDT 24 Aug 11 05:17:53 PM PDT 24 371590487 ps
T382 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.583885259 Aug 11 05:17:33 PM PDT 24 Aug 11 05:17:34 PM PDT 24 459219777 ps
T383 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3242565440 Aug 11 05:17:39 PM PDT 24 Aug 11 05:17:42 PM PDT 24 3918739977 ps
T384 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2551558018 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:46 PM PDT 24 493520081 ps
T385 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3973627672 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:15 PM PDT 24 8444767813 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1654752569 Aug 11 05:17:04 PM PDT 24 Aug 11 05:17:06 PM PDT 24 474629870 ps
T387 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1885830338 Aug 11 05:17:32 PM PDT 24 Aug 11 05:17:36 PM PDT 24 3811975282 ps
T85 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3947789221 Aug 11 05:17:02 PM PDT 24 Aug 11 05:17:03 PM PDT 24 453349411 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2019399748 Aug 11 05:17:01 PM PDT 24 Aug 11 05:17:04 PM PDT 24 1645360518 ps
T389 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2857989350 Aug 11 05:17:54 PM PDT 24 Aug 11 05:17:56 PM PDT 24 516151393 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.96520463 Aug 11 05:16:10 PM PDT 24 Aug 11 05:16:11 PM PDT 24 319064142 ps
T391 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1031132359 Aug 11 05:16:43 PM PDT 24 Aug 11 05:16:46 PM PDT 24 997190759 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2751602043 Aug 11 05:16:16 PM PDT 24 Aug 11 05:16:18 PM PDT 24 360638954 ps
T393 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2025837586 Aug 11 05:16:54 PM PDT 24 Aug 11 05:16:56 PM PDT 24 603151580 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2871772901 Aug 11 05:16:37 PM PDT 24 Aug 11 05:16:39 PM PDT 24 568966655 ps
T394 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1744465184 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:45 PM PDT 24 567489177 ps
T395 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2967983814 Aug 11 05:17:46 PM PDT 24 Aug 11 05:17:47 PM PDT 24 519875407 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3932546276 Aug 11 05:16:31 PM PDT 24 Aug 11 05:16:32 PM PDT 24 422738404 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.694324784 Aug 11 05:16:17 PM PDT 24 Aug 11 05:16:18 PM PDT 24 470729433 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4267809818 Aug 11 05:16:43 PM PDT 24 Aug 11 05:16:44 PM PDT 24 414458971 ps
T399 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.567055028 Aug 11 05:16:41 PM PDT 24 Aug 11 05:16:44 PM PDT 24 1356626260 ps
T400 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1820219370 Aug 11 05:17:02 PM PDT 24 Aug 11 05:17:03 PM PDT 24 4606761665 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3265325499 Aug 11 05:17:03 PM PDT 24 Aug 11 05:17:04 PM PDT 24 440419039 ps
T402 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3809920762 Aug 11 05:17:14 PM PDT 24 Aug 11 05:17:15 PM PDT 24 595894459 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4119744490 Aug 11 05:16:50 PM PDT 24 Aug 11 05:16:50 PM PDT 24 507260502 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.312840499 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:10 PM PDT 24 1505086158 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2053434102 Aug 11 05:16:51 PM PDT 24 Aug 11 05:16:52 PM PDT 24 335866704 ps
T58 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1105862515 Aug 11 05:17:08 PM PDT 24 Aug 11 05:17:09 PM PDT 24 350366790 ps
T406 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1724782318 Aug 11 05:16:30 PM PDT 24 Aug 11 05:16:32 PM PDT 24 684876125 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2213013506 Aug 11 05:17:01 PM PDT 24 Aug 11 05:17:08 PM PDT 24 4608198462 ps
T408 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1317102151 Aug 11 05:17:19 PM PDT 24 Aug 11 05:17:21 PM PDT 24 416661011 ps
T409 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.552617950 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:46 PM PDT 24 481132730 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2017814807 Aug 11 05:16:56 PM PDT 24 Aug 11 05:17:01 PM PDT 24 1425011950 ps
T75 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.65873217 Aug 11 05:16:35 PM PDT 24 Aug 11 05:16:37 PM PDT 24 464076457 ps
T410 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.454280503 Aug 11 05:17:26 PM PDT 24 Aug 11 05:17:27 PM PDT 24 543453735 ps
T411 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.212454124 Aug 11 05:17:20 PM PDT 24 Aug 11 05:17:21 PM PDT 24 463457523 ps
T412 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3558581290 Aug 11 05:17:40 PM PDT 24 Aug 11 05:17:42 PM PDT 24 1527934778 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2701509320 Aug 11 05:17:02 PM PDT 24 Aug 11 05:17:16 PM PDT 24 9390860990 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.340339453 Aug 11 05:16:42 PM PDT 24 Aug 11 05:16:43 PM PDT 24 580767205 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1000132998 Aug 11 05:16:17 PM PDT 24 Aug 11 05:16:18 PM PDT 24 326662565 ps
T416 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1741390277 Aug 11 05:16:55 PM PDT 24 Aug 11 05:17:09 PM PDT 24 8243137108 ps
T417 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1903826754 Aug 11 05:17:14 PM PDT 24 Aug 11 05:17:16 PM PDT 24 928095018 ps
T418 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.585628324 Aug 11 05:16:53 PM PDT 24 Aug 11 05:16:55 PM PDT 24 507670395 ps
T419 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2989386424 Aug 11 05:17:14 PM PDT 24 Aug 11 05:17:15 PM PDT 24 417444830 ps
T420 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.470491130 Aug 11 05:17:21 PM PDT 24 Aug 11 05:17:22 PM PDT 24 367467909 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1089896995 Aug 11 05:16:23 PM PDT 24 Aug 11 05:16:24 PM PDT 24 476666942 ps
T421 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1152245338 Aug 11 05:17:03 PM PDT 24 Aug 11 05:17:03 PM PDT 24 358768720 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1742658708 Aug 11 05:16:55 PM PDT 24 Aug 11 05:16:56 PM PDT 24 1749239396 ps
T423 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2211879394 Aug 11 05:17:45 PM PDT 24 Aug 11 05:17:46 PM PDT 24 345384254 ps

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.242937644
Short name T3
Test name
Test status
Simulation time 463785471029 ps
CPU time 603.89 seconds
Started Aug 11 05:14:36 PM PDT 24
Finished Aug 11 05:24:40 PM PDT 24
Peak memory 213868 kb
Host smart-cb45bf5c-c44f-4a3e-a243-f26f669a8446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242937644 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.242937644
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2350910305
Short name T29
Test name
Test status
Simulation time 34804610373 ps
CPU time 273.88 seconds
Started Aug 11 05:15:17 PM PDT 24
Finished Aug 11 05:19:51 PM PDT 24
Peak memory 214040 kb
Host smart-83eb2246-0d28-455d-833a-bf2b7485453d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350910305 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2350910305
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2780889788
Short name T17
Test name
Test status
Simulation time 8193587686 ps
CPU time 11.98 seconds
Started Aug 11 05:11:19 PM PDT 24
Finished Aug 11 05:11:31 PM PDT 24
Peak memory 215744 kb
Host smart-1c01b1d6-4367-443b-b0b9-d9240e2e1022
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780889788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2780889788
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2678644322
Short name T43
Test name
Test status
Simulation time 812678852338 ps
CPU time 375.86 seconds
Started Aug 11 05:13:21 PM PDT 24
Finished Aug 11 05:19:37 PM PDT 24
Peak memory 202216 kb
Host smart-7c120cb6-a6bc-402b-94a0-d1854c1f819d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678644322 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2678644322
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2894045403
Short name T54
Test name
Test status
Simulation time 5962140203 ps
CPU time 9.23 seconds
Started Aug 11 05:16:41 PM PDT 24
Finished Aug 11 05:16:51 PM PDT 24
Peak memory 183984 kb
Host smart-1e676eef-2752-4943-9601-2be44c3c359f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894045403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2894045403
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1057006170
Short name T1
Test name
Test status
Simulation time 23305745833 ps
CPU time 5.09 seconds
Started Aug 11 05:12:38 PM PDT 24
Finished Aug 11 05:12:43 PM PDT 24
Peak memory 192088 kb
Host smart-b79b65ae-e264-46a6-ae87-cefa84eb7c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057006170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1057006170
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1501403204
Short name T96
Test name
Test status
Simulation time 591571900732 ps
CPU time 1019.4 seconds
Started Aug 11 05:14:43 PM PDT 24
Finished Aug 11 05:31:42 PM PDT 24
Peak memory 209820 kb
Host smart-9823d329-c03b-412a-a9c1-3642ec8b064a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501403204 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1501403204
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3456907959
Short name T143
Test name
Test status
Simulation time 44888146538 ps
CPU time 267.43 seconds
Started Aug 11 05:13:20 PM PDT 24
Finished Aug 11 05:17:47 PM PDT 24
Peak memory 198844 kb
Host smart-0eaf9863-d976-4712-a04d-031f882ce82e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456907959 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3456907959
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3438555262
Short name T128
Test name
Test status
Simulation time 76741334233 ps
CPU time 117.15 seconds
Started Aug 11 05:14:43 PM PDT 24
Finished Aug 11 05:16:40 PM PDT 24
Peak memory 198476 kb
Host smart-145727b9-952a-4131-8aa6-3bcf9953de9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438555262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3438555262
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1057191410
Short name T120
Test name
Test status
Simulation time 113348336846 ps
CPU time 632.08 seconds
Started Aug 11 05:15:22 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 206380 kb
Host smart-484b8827-8d22-4152-af90-7746fff160d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057191410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1057191410
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.623047512
Short name T93
Test name
Test status
Simulation time 230430944166 ps
CPU time 516.37 seconds
Started Aug 11 05:12:06 PM PDT 24
Finished Aug 11 05:20:43 PM PDT 24
Peak memory 204980 kb
Host smart-88c3a1fe-ecda-4320-b498-5bce2fe43ec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623047512 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.623047512
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.615092078
Short name T127
Test name
Test status
Simulation time 40440852241 ps
CPU time 413.47 seconds
Started Aug 11 05:14:18 PM PDT 24
Finished Aug 11 05:21:12 PM PDT 24
Peak memory 208168 kb
Host smart-5bc0fc1c-f43b-4754-92af-dbd7be7d879d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615092078 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.615092078
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2605376478
Short name T48
Test name
Test status
Simulation time 394772864513 ps
CPU time 463.71 seconds
Started Aug 11 05:14:09 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 203436 kb
Host smart-a7d656d9-58d1-456b-9167-e19b5c69d0f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605376478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2605376478
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.930105732
Short name T4
Test name
Test status
Simulation time 325707235408 ps
CPU time 767.98 seconds
Started Aug 11 05:14:54 PM PDT 24
Finished Aug 11 05:27:42 PM PDT 24
Peak memory 215068 kb
Host smart-4425ba1c-0e1a-4582-8384-673e857a60bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930105732 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.930105732
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2773207207
Short name T42
Test name
Test status
Simulation time 260065863019 ps
CPU time 625.54 seconds
Started Aug 11 05:13:51 PM PDT 24
Finished Aug 11 05:24:17 PM PDT 24
Peak memory 206824 kb
Host smart-137362db-f38b-4d47-b10b-a6078a0c6609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773207207 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2773207207
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2557141681
Short name T152
Test name
Test status
Simulation time 217840960541 ps
CPU time 518.21 seconds
Started Aug 11 05:14:30 PM PDT 24
Finished Aug 11 05:23:09 PM PDT 24
Peak memory 206868 kb
Host smart-c68b01e0-c7c3-4574-a1fc-958bffab7ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557141681 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2557141681
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3249620435
Short name T53
Test name
Test status
Simulation time 112729573918 ps
CPU time 1066.69 seconds
Started Aug 11 05:15:03 PM PDT 24
Finished Aug 11 05:32:50 PM PDT 24
Peak memory 215084 kb
Host smart-1e594d8f-c178-42fd-8124-25932776dfc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249620435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3249620435
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1760888993
Short name T123
Test name
Test status
Simulation time 3959225336 ps
CPU time 6.68 seconds
Started Aug 11 05:12:58 PM PDT 24
Finished Aug 11 05:13:04 PM PDT 24
Peak memory 192036 kb
Host smart-68c5daf3-17be-43ea-9763-5af6b0dd3f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760888993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1760888993
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.965756991
Short name T33
Test name
Test status
Simulation time 4344860551 ps
CPU time 7.73 seconds
Started Aug 11 05:17:12 PM PDT 24
Finished Aug 11 05:17:20 PM PDT 24
Peak memory 197728 kb
Host smart-df3d4c8f-6b1d-4393-ad68-5d1d32ad70fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965756991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.965756991
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2105329472
Short name T150
Test name
Test status
Simulation time 58564727070 ps
CPU time 76.39 seconds
Started Aug 11 05:15:11 PM PDT 24
Finished Aug 11 05:16:27 PM PDT 24
Peak memory 193152 kb
Host smart-77b5a465-289e-4bf2-be96-fa648a2d37be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105329472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2105329472
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.244860923
Short name T81
Test name
Test status
Simulation time 217462958022 ps
CPU time 671.97 seconds
Started Aug 11 05:14:02 PM PDT 24
Finished Aug 11 05:25:15 PM PDT 24
Peak memory 214524 kb
Host smart-6e4f5563-396a-4eca-880e-123c3454ed2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244860923 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.244860923
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.4128204038
Short name T40
Test name
Test status
Simulation time 348621399671 ps
CPU time 483.83 seconds
Started Aug 11 05:12:18 PM PDT 24
Finished Aug 11 05:20:22 PM PDT 24
Peak memory 214204 kb
Host smart-6ec17760-76cb-44ea-b691-5020bbb8f106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128204038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.4128204038
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1962403994
Short name T49
Test name
Test status
Simulation time 353194601897 ps
CPU time 725.21 seconds
Started Aug 11 05:12:55 PM PDT 24
Finished Aug 11 05:25:00 PM PDT 24
Peak memory 206524 kb
Host smart-09692500-4e64-4a2f-b09c-2dbd397a6441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962403994 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1962403994
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3769120985
Short name T113
Test name
Test status
Simulation time 17187965252 ps
CPU time 135.2 seconds
Started Aug 11 05:11:46 PM PDT 24
Finished Aug 11 05:14:01 PM PDT 24
Peak memory 198716 kb
Host smart-1d9d8777-0550-472e-918b-31a58e508e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769120985 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3769120985
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2869452810
Short name T144
Test name
Test status
Simulation time 86963285818 ps
CPU time 68.15 seconds
Started Aug 11 05:15:16 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 198412 kb
Host smart-2226aaa4-5a97-4df4-b13d-85efdaaca2b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869452810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2869452810
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3700010602
Short name T26
Test name
Test status
Simulation time 16333863628 ps
CPU time 121.57 seconds
Started Aug 11 05:15:41 PM PDT 24
Finished Aug 11 05:17:43 PM PDT 24
Peak memory 206836 kb
Host smart-69cd8572-a1af-4de4-a64e-e5b6f67fd1ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700010602 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3700010602
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1751649072
Short name T52
Test name
Test status
Simulation time 270500744946 ps
CPU time 642.54 seconds
Started Aug 11 05:11:33 PM PDT 24
Finished Aug 11 05:22:15 PM PDT 24
Peak memory 214332 kb
Host smart-ceed9c1a-f46b-4658-a859-3a4e1c48c170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751649072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1751649072
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1243635712
Short name T151
Test name
Test status
Simulation time 116043214684 ps
CPU time 41.64 seconds
Started Aug 11 05:14:42 PM PDT 24
Finished Aug 11 05:15:24 PM PDT 24
Peak memory 198436 kb
Host smart-a66d94a4-7dc8-4ae1-90e9-40f93162f6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243635712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1243635712
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3260384220
Short name T130
Test name
Test status
Simulation time 68872269866 ps
CPU time 777.35 seconds
Started Aug 11 05:16:08 PM PDT 24
Finished Aug 11 05:29:05 PM PDT 24
Peak memory 214452 kb
Host smart-dba1ad0c-3d05-4efa-8af7-d42417fe4ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260384220 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3260384220
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3412306203
Short name T129
Test name
Test status
Simulation time 122298926168 ps
CPU time 34.75 seconds
Started Aug 11 05:13:10 PM PDT 24
Finished Aug 11 05:13:45 PM PDT 24
Peak memory 193168 kb
Host smart-ccda003f-d2af-4f4a-a6d1-78ca222c6f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412306203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3412306203
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3351914895
Short name T176
Test name
Test status
Simulation time 202213508278 ps
CPU time 455.34 seconds
Started Aug 11 05:14:49 PM PDT 24
Finished Aug 11 05:22:25 PM PDT 24
Peak memory 214104 kb
Host smart-6e0d9383-1a1a-4e89-b510-17bf8a20ac67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351914895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3351914895
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1383694292
Short name T117
Test name
Test status
Simulation time 226584754095 ps
CPU time 319.73 seconds
Started Aug 11 05:15:35 PM PDT 24
Finished Aug 11 05:20:55 PM PDT 24
Peak memory 192756 kb
Host smart-28106f62-a413-4e3b-ae70-7386b0207a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383694292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1383694292
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.408064039
Short name T64
Test name
Test status
Simulation time 107885603253 ps
CPU time 56.21 seconds
Started Aug 11 05:16:07 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 193092 kb
Host smart-1868e3d7-0a0a-4046-abcb-f4161819b151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408064039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.408064039
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2245367192
Short name T80
Test name
Test status
Simulation time 17087334277 ps
CPU time 185.57 seconds
Started Aug 11 05:12:26 PM PDT 24
Finished Aug 11 05:15:31 PM PDT 24
Peak memory 214040 kb
Host smart-1a3c000c-21b6-49d5-aa7b-31ae98bd6d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245367192 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2245367192
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3556840881
Short name T115
Test name
Test status
Simulation time 150165447478 ps
CPU time 101.57 seconds
Started Aug 11 05:12:37 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 192644 kb
Host smart-0fef1b04-b37f-4a5e-8515-d25ac9a72d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556840881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3556840881
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.37277351
Short name T51
Test name
Test status
Simulation time 57475232536 ps
CPU time 612.83 seconds
Started Aug 11 05:12:50 PM PDT 24
Finished Aug 11 05:23:03 PM PDT 24
Peak memory 203924 kb
Host smart-000be081-4f29-4821-aec5-e686bf7ebd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277351 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.37277351
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2833963746
Short name T138
Test name
Test status
Simulation time 138890404799 ps
CPU time 83.75 seconds
Started Aug 11 05:13:32 PM PDT 24
Finished Aug 11 05:14:56 PM PDT 24
Peak memory 193224 kb
Host smart-260c99bc-5675-4a3d-a771-5a539467c2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833963746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2833963746
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1251814423
Short name T159
Test name
Test status
Simulation time 320309276071 ps
CPU time 452.59 seconds
Started Aug 11 05:11:48 PM PDT 24
Finished Aug 11 05:19:20 PM PDT 24
Peak memory 198404 kb
Host smart-3d8be6f7-2026-4f35-a29f-39c5602104aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251814423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1251814423
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.4076476758
Short name T11
Test name
Test status
Simulation time 72355718244 ps
CPU time 108.32 seconds
Started Aug 11 05:14:37 PM PDT 24
Finished Aug 11 05:16:25 PM PDT 24
Peak memory 192060 kb
Host smart-414d2253-790d-45ae-aebd-b2da0d63dbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076476758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.4076476758
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3585393815
Short name T171
Test name
Test status
Simulation time 180363379930 ps
CPU time 354.72 seconds
Started Aug 11 05:15:43 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 214468 kb
Host smart-bc54df2b-8dd4-4ce2-b395-40a9d12f73fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585393815 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3585393815
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2788573513
Short name T125
Test name
Test status
Simulation time 296756885716 ps
CPU time 106.3 seconds
Started Aug 11 05:16:06 PM PDT 24
Finished Aug 11 05:17:52 PM PDT 24
Peak memory 192140 kb
Host smart-872140c7-d667-46f4-8452-0927cf143b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788573513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2788573513
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2984861581
Short name T140
Test name
Test status
Simulation time 312400205674 ps
CPU time 67.5 seconds
Started Aug 11 05:12:20 PM PDT 24
Finished Aug 11 05:13:28 PM PDT 24
Peak memory 193112 kb
Host smart-9445bde3-2c7f-4b5a-a0b8-82d744287fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984861581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2984861581
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2642690454
Short name T24
Test name
Test status
Simulation time 234632910725 ps
CPU time 78.92 seconds
Started Aug 11 05:12:50 PM PDT 24
Finished Aug 11 05:14:09 PM PDT 24
Peak memory 198412 kb
Host smart-77c0a09c-e3b6-4309-843f-776c141db708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642690454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2642690454
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2871145829
Short name T139
Test name
Test status
Simulation time 19176699117 ps
CPU time 146.7 seconds
Started Aug 11 05:13:01 PM PDT 24
Finished Aug 11 05:15:28 PM PDT 24
Peak memory 207004 kb
Host smart-633f0f55-919e-4059-b4c6-5ce12abf30b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871145829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2871145829
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.638623319
Short name T94
Test name
Test status
Simulation time 437524065097 ps
CPU time 889.47 seconds
Started Aug 11 05:15:54 PM PDT 24
Finished Aug 11 05:30:44 PM PDT 24
Peak memory 215040 kb
Host smart-996bbce6-f4f3-43dd-abfc-4f261912c239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638623319 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.638623319
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.142941666
Short name T38
Test name
Test status
Simulation time 71343852650 ps
CPU time 347.25 seconds
Started Aug 11 05:12:36 PM PDT 24
Finished Aug 11 05:18:23 PM PDT 24
Peak memory 209048 kb
Host smart-9201c546-23dd-48f7-8de0-845e0afa9513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142941666 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.142941666
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2548870643
Short name T102
Test name
Test status
Simulation time 77954666768 ps
CPU time 617.04 seconds
Started Aug 11 05:11:43 PM PDT 24
Finished Aug 11 05:22:00 PM PDT 24
Peak memory 206876 kb
Host smart-f9013295-37bd-4e97-aa28-4887378ce74a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548870643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2548870643
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3399896470
Short name T136
Test name
Test status
Simulation time 93781841263 ps
CPU time 129.04 seconds
Started Aug 11 05:12:25 PM PDT 24
Finished Aug 11 05:14:34 PM PDT 24
Peak memory 184312 kb
Host smart-d3e1d684-949b-4561-a0ed-dbaa074a2ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399896470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3399896470
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1852148135
Short name T105
Test name
Test status
Simulation time 5317064907 ps
CPU time 1.89 seconds
Started Aug 11 05:14:48 PM PDT 24
Finished Aug 11 05:14:50 PM PDT 24
Peak memory 193208 kb
Host smart-5b5a19f7-e163-49b2-b001-980f75796c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852148135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1852148135
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1483959923
Short name T7
Test name
Test status
Simulation time 72518842772 ps
CPU time 20.9 seconds
Started Aug 11 05:15:22 PM PDT 24
Finished Aug 11 05:15:43 PM PDT 24
Peak memory 198348 kb
Host smart-3921c595-c7b3-43c6-b9df-11ab4173c0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483959923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1483959923
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3273855433
Short name T119
Test name
Test status
Simulation time 21045435536 ps
CPU time 9.04 seconds
Started Aug 11 05:14:37 PM PDT 24
Finished Aug 11 05:14:46 PM PDT 24
Peak memory 193132 kb
Host smart-5d8e4daa-1564-4814-b56d-77c2af5d35f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273855433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3273855433
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2096197336
Short name T112
Test name
Test status
Simulation time 90954650556 ps
CPU time 120.59 seconds
Started Aug 11 05:14:55 PM PDT 24
Finished Aug 11 05:16:55 PM PDT 24
Peak memory 198324 kb
Host smart-8756c420-07f3-4135-9b6f-d18f3ec2f9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096197336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2096197336
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.531919599
Short name T145
Test name
Test status
Simulation time 190965560612 ps
CPU time 275.82 seconds
Started Aug 11 05:15:10 PM PDT 24
Finished Aug 11 05:19:46 PM PDT 24
Peak memory 198388 kb
Host smart-46cdc89d-3036-41c3-9f9b-a5020cb86f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531919599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.531919599
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.739176600
Short name T97
Test name
Test status
Simulation time 18247988206 ps
CPU time 136.62 seconds
Started Aug 11 05:12:13 PM PDT 24
Finished Aug 11 05:14:30 PM PDT 24
Peak memory 206840 kb
Host smart-5bd46f1d-786c-4176-b5ab-fd0322c69697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739176600 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.739176600
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3880299890
Short name T166
Test name
Test status
Simulation time 33754642129 ps
CPU time 256.67 seconds
Started Aug 11 05:13:08 PM PDT 24
Finished Aug 11 05:17:25 PM PDT 24
Peak memory 206856 kb
Host smart-c8c39fee-cd11-4538-a31d-4faf5b1de40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880299890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3880299890
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4046405392
Short name T27
Test name
Test status
Simulation time 85336316465 ps
CPU time 32.39 seconds
Started Aug 11 05:13:15 PM PDT 24
Finished Aug 11 05:13:47 PM PDT 24
Peak memory 193164 kb
Host smart-0bbf0725-299f-472c-a03a-5da79600418f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046405392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4046405392
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3046093949
Short name T116
Test name
Test status
Simulation time 31788182909 ps
CPU time 255.87 seconds
Started Aug 11 05:13:25 PM PDT 24
Finished Aug 11 05:17:41 PM PDT 24
Peak memory 206864 kb
Host smart-edf71bc0-23e4-488f-b517-32032eb69862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046093949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3046093949
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.949770444
Short name T141
Test name
Test status
Simulation time 335324827868 ps
CPU time 224.54 seconds
Started Aug 11 05:11:41 PM PDT 24
Finished Aug 11 05:15:26 PM PDT 24
Peak memory 198380 kb
Host smart-fd421b9d-9403-4f46-b0c4-00dd9df72d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949770444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.949770444
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3396525785
Short name T167
Test name
Test status
Simulation time 82079047336 ps
CPU time 713.34 seconds
Started Aug 11 05:14:54 PM PDT 24
Finished Aug 11 05:26:47 PM PDT 24
Peak memory 213248 kb
Host smart-362fa533-5748-4abe-babb-b9b0bd93ff56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396525785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3396525785
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1038619099
Short name T89
Test name
Test status
Simulation time 2493159346 ps
CPU time 1.55 seconds
Started Aug 11 05:16:17 PM PDT 24
Finished Aug 11 05:16:18 PM PDT 24
Peak memory 184024 kb
Host smart-2bcf6a51-811e-4028-a630-48fcff57d507
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038619099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1038619099
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2624909587
Short name T50
Test name
Test status
Simulation time 212818263356 ps
CPU time 229.15 seconds
Started Aug 11 05:13:14 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 200560 kb
Host smart-b6432bed-056f-4537-afb9-d63bc6ee456a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624909587 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2624909587
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.120782050
Short name T163
Test name
Test status
Simulation time 166033830937 ps
CPU time 211.54 seconds
Started Aug 11 05:13:20 PM PDT 24
Finished Aug 11 05:16:52 PM PDT 24
Peak memory 193068 kb
Host smart-37b460a3-6c96-4190-adbf-4ccc06cbdd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120782050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.120782050
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2785987030
Short name T114
Test name
Test status
Simulation time 181436648355 ps
CPU time 238.36 seconds
Started Aug 11 05:13:44 PM PDT 24
Finished Aug 11 05:17:42 PM PDT 24
Peak memory 193112 kb
Host smart-132477f3-a248-4d5c-b247-058bacf40b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785987030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2785987030
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3709656563
Short name T142
Test name
Test status
Simulation time 35066473320 ps
CPU time 183.41 seconds
Started Aug 11 05:15:36 PM PDT 24
Finished Aug 11 05:18:39 PM PDT 24
Peak memory 206852 kb
Host smart-248154b1-991c-4509-bacc-a325379fb0b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709656563 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3709656563
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.133302358
Short name T161
Test name
Test status
Simulation time 102668560120 ps
CPU time 38.79 seconds
Started Aug 11 05:11:19 PM PDT 24
Finished Aug 11 05:11:58 PM PDT 24
Peak memory 191980 kb
Host smart-94305b56-553a-4c63-919b-db63f2783951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133302358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.133302358
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2688608359
Short name T2
Test name
Test status
Simulation time 41008995531 ps
CPU time 65.62 seconds
Started Aug 11 05:14:05 PM PDT 24
Finished Aug 11 05:15:11 PM PDT 24
Peak memory 198476 kb
Host smart-bc87e834-26b8-434f-9217-d497d71f0c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688608359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2688608359
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3323927391
Short name T41
Test name
Test status
Simulation time 77557565929 ps
CPU time 339.76 seconds
Started Aug 11 05:15:21 PM PDT 24
Finished Aug 11 05:21:01 PM PDT 24
Peak memory 209556 kb
Host smart-9be66ccd-5707-4780-99b3-07dfc53bb1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323927391 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3323927391
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4077726779
Short name T19
Test name
Test status
Simulation time 209119625005 ps
CPU time 588.75 seconds
Started Aug 11 05:11:18 PM PDT 24
Finished Aug 11 05:21:07 PM PDT 24
Peak memory 213296 kb
Host smart-5f87f683-d8bd-4094-a748-323ea82734fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077726779 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4077726779
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3781268527
Short name T121
Test name
Test status
Simulation time 582036130 ps
CPU time 1.12 seconds
Started Aug 11 05:12:38 PM PDT 24
Finished Aug 11 05:12:39 PM PDT 24
Peak memory 196892 kb
Host smart-0a156652-5802-418c-9021-3b28b3aaee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781268527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3781268527
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3524017112
Short name T132
Test name
Test status
Simulation time 439172550 ps
CPU time 0.75 seconds
Started Aug 11 05:15:11 PM PDT 24
Finished Aug 11 05:15:12 PM PDT 24
Peak memory 196892 kb
Host smart-1d579452-3776-49c5-9dae-fc54ccf678bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524017112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3524017112
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3094222131
Short name T164
Test name
Test status
Simulation time 165207009254 ps
CPU time 215 seconds
Started Aug 11 05:11:53 PM PDT 24
Finished Aug 11 05:15:29 PM PDT 24
Peak memory 192100 kb
Host smart-51b2d889-ad33-4870-b3b0-235b225cf6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094222131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3094222131
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1783781189
Short name T13
Test name
Test status
Simulation time 44679755767 ps
CPU time 181.15 seconds
Started Aug 11 05:16:05 PM PDT 24
Finished Aug 11 05:19:06 PM PDT 24
Peak memory 214908 kb
Host smart-73ed2596-6c36-487c-b02a-2d19603f0009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783781189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1783781189
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3063411522
Short name T61
Test name
Test status
Simulation time 51008638850 ps
CPU time 11.43 seconds
Started Aug 11 05:12:19 PM PDT 24
Finished Aug 11 05:12:31 PM PDT 24
Peak memory 198500 kb
Host smart-ae415a4b-4367-4bd0-81d5-f7172b90f7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063411522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3063411522
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4146530384
Short name T158
Test name
Test status
Simulation time 517511634 ps
CPU time 0.77 seconds
Started Aug 11 05:14:42 PM PDT 24
Finished Aug 11 05:14:43 PM PDT 24
Peak memory 196792 kb
Host smart-bb6c5aa4-c2d7-4b1a-96e4-13f346d2e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146530384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4146530384
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4190972400
Short name T156
Test name
Test status
Simulation time 571561612 ps
CPU time 1.45 seconds
Started Aug 11 05:11:47 PM PDT 24
Finished Aug 11 05:11:48 PM PDT 24
Peak memory 196736 kb
Host smart-0f112165-f8bc-4d78-b237-4876e76297a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190972400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4190972400
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.792411852
Short name T146
Test name
Test status
Simulation time 66402617152 ps
CPU time 48.84 seconds
Started Aug 11 05:15:35 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 198440 kb
Host smart-b987362b-84f9-4004-8d15-c64b90fa9307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792411852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.792411852
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3680163845
Short name T133
Test name
Test status
Simulation time 606815070 ps
CPU time 1.01 seconds
Started Aug 11 05:15:46 PM PDT 24
Finished Aug 11 05:15:47 PM PDT 24
Peak memory 196844 kb
Host smart-41a7d18c-20a9-4c5a-a732-fec24e1e8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680163845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3680163845
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1809876292
Short name T137
Test name
Test status
Simulation time 217471995007 ps
CPU time 127.75 seconds
Started Aug 11 05:16:01 PM PDT 24
Finished Aug 11 05:18:09 PM PDT 24
Peak memory 198376 kb
Host smart-6f29e192-bb47-469d-b053-cc2890bfe754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809876292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1809876292
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.689175897
Short name T8
Test name
Test status
Simulation time 316514936950 ps
CPU time 147 seconds
Started Aug 11 05:12:09 PM PDT 24
Finished Aug 11 05:14:36 PM PDT 24
Peak memory 198524 kb
Host smart-079e53ba-802a-4e33-9ec4-78f65abad3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689175897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.689175897
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3532196173
Short name T154
Test name
Test status
Simulation time 405035291 ps
CPU time 1.29 seconds
Started Aug 11 05:12:12 PM PDT 24
Finished Aug 11 05:12:14 PM PDT 24
Peak memory 196880 kb
Host smart-df5dffce-d488-4344-8cff-24a8ea71f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532196173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3532196173
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.46894228
Short name T162
Test name
Test status
Simulation time 412801657 ps
CPU time 1.15 seconds
Started Aug 11 05:12:26 PM PDT 24
Finished Aug 11 05:12:27 PM PDT 24
Peak memory 196800 kb
Host smart-6295264a-e1c3-4a4e-bcd7-19fc8bb3e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46894228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.46894228
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.932111595
Short name T118
Test name
Test status
Simulation time 586184883 ps
CPU time 0.82 seconds
Started Aug 11 05:12:44 PM PDT 24
Finished Aug 11 05:12:45 PM PDT 24
Peak memory 196780 kb
Host smart-05f85781-d39f-4ee5-98cd-60b74f6e4d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932111595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.932111595
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.188339307
Short name T134
Test name
Test status
Simulation time 355445152 ps
CPU time 0.75 seconds
Started Aug 11 05:11:42 PM PDT 24
Finished Aug 11 05:11:43 PM PDT 24
Peak memory 196872 kb
Host smart-849bb6ec-cecf-470e-bc0d-d1145a121fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188339307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.188339307
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2785584533
Short name T131
Test name
Test status
Simulation time 495843402 ps
CPU time 0.91 seconds
Started Aug 11 05:13:44 PM PDT 24
Finished Aug 11 05:13:45 PM PDT 24
Peak memory 196808 kb
Host smart-d4ef8837-0cf3-49ea-9e25-4d650660a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785584533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2785584533
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2833607222
Short name T169
Test name
Test status
Simulation time 116777816919 ps
CPU time 22.6 seconds
Started Aug 11 05:13:55 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 192012 kb
Host smart-aae8c3bb-4795-4add-ab9a-955719143c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833607222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2833607222
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1699418564
Short name T126
Test name
Test status
Simulation time 377143447 ps
CPU time 0.74 seconds
Started Aug 11 05:15:59 PM PDT 24
Finished Aug 11 05:16:00 PM PDT 24
Peak memory 196884 kb
Host smart-6a1085e7-04e3-451c-a092-c29ebadb3034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699418564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1699418564
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1067779981
Short name T149
Test name
Test status
Simulation time 542243799 ps
CPU time 1.34 seconds
Started Aug 11 05:11:48 PM PDT 24
Finished Aug 11 05:11:49 PM PDT 24
Peak memory 196776 kb
Host smart-a7648381-faa1-42e4-a51c-f7fcc9790645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067779981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1067779981
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.555102777
Short name T21
Test name
Test status
Simulation time 401260807 ps
CPU time 1.18 seconds
Started Aug 11 05:14:37 PM PDT 24
Finished Aug 11 05:14:38 PM PDT 24
Peak memory 196768 kb
Host smart-868b4924-6bd2-4a26-ae9d-c596ab0536fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555102777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.555102777
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3360110681
Short name T124
Test name
Test status
Simulation time 176214890442 ps
CPU time 226.76 seconds
Started Aug 11 05:14:57 PM PDT 24
Finished Aug 11 05:18:43 PM PDT 24
Peak memory 191976 kb
Host smart-4095992c-f85e-4a8a-b3b5-08448c7fb906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360110681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3360110681
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3223617000
Short name T68
Test name
Test status
Simulation time 374262757 ps
CPU time 1.22 seconds
Started Aug 11 05:15:10 PM PDT 24
Finished Aug 11 05:15:12 PM PDT 24
Peak memory 196768 kb
Host smart-6aabeed1-aa50-453a-b048-b30f0602f23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223617000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3223617000
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1842435405
Short name T65
Test name
Test status
Simulation time 521496114 ps
CPU time 0.7 seconds
Started Aug 11 05:15:42 PM PDT 24
Finished Aug 11 05:15:43 PM PDT 24
Peak memory 196808 kb
Host smart-eb12ee6a-938f-4aa6-aebf-9b531680ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842435405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1842435405
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3412737852
Short name T28
Test name
Test status
Simulation time 600892278 ps
CPU time 1.2 seconds
Started Aug 11 05:15:42 PM PDT 24
Finished Aug 11 05:15:43 PM PDT 24
Peak memory 196908 kb
Host smart-e640ae30-0349-49e2-82f4-c74dc6e76b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412737852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3412737852
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2811955110
Short name T168
Test name
Test status
Simulation time 205367123860 ps
CPU time 52.02 seconds
Started Aug 11 05:13:21 PM PDT 24
Finished Aug 11 05:14:14 PM PDT 24
Peak memory 192276 kb
Host smart-5d536f94-5d3c-42fa-aece-51f07366ea39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811955110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2811955110
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4059307225
Short name T100
Test name
Test status
Simulation time 40977568819 ps
CPU time 74.57 seconds
Started Aug 11 05:14:25 PM PDT 24
Finished Aug 11 05:15:39 PM PDT 24
Peak memory 198676 kb
Host smart-21f5e326-9765-4c93-949f-59268f014ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059307225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4059307225
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2176850951
Short name T95
Test name
Test status
Simulation time 106922507590 ps
CPU time 807.42 seconds
Started Aug 11 05:12:36 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 207544 kb
Host smart-84fdc5b5-dbd4-4871-99fd-12c359c58eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176850951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2176850951
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.616948668
Short name T148
Test name
Test status
Simulation time 456952443 ps
CPU time 0.64 seconds
Started Aug 11 05:12:54 PM PDT 24
Finished Aug 11 05:12:55 PM PDT 24
Peak memory 196820 kb
Host smart-06d91ec8-f3c9-49be-b776-b6d92dc5664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616948668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.616948668
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.531703165
Short name T39
Test name
Test status
Simulation time 151612775317 ps
CPU time 327.9 seconds
Started Aug 11 05:13:38 PM PDT 24
Finished Aug 11 05:19:06 PM PDT 24
Peak memory 201892 kb
Host smart-3fe82ae7-1039-40d2-9f39-6461afdb4d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531703165 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.531703165
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.727497423
Short name T103
Test name
Test status
Simulation time 435596373 ps
CPU time 1.29 seconds
Started Aug 11 05:13:57 PM PDT 24
Finished Aug 11 05:13:59 PM PDT 24
Peak memory 196820 kb
Host smart-e3f27c80-1f0f-4e29-bfc0-051634fd1065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727497423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.727497423
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3858834067
Short name T160
Test name
Test status
Simulation time 406546389 ps
CPU time 0.75 seconds
Started Aug 11 05:14:26 PM PDT 24
Finished Aug 11 05:14:27 PM PDT 24
Peak memory 196808 kb
Host smart-2ee54c3f-77df-4511-ba78-f6ccf39b3b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858834067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3858834067
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.188028479
Short name T135
Test name
Test status
Simulation time 442515488 ps
CPU time 0.64 seconds
Started Aug 11 05:14:42 PM PDT 24
Finished Aug 11 05:14:43 PM PDT 24
Peak memory 196972 kb
Host smart-32a73062-3483-4892-965d-6d9c17a32111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188028479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.188028479
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2125553723
Short name T157
Test name
Test status
Simulation time 363070401 ps
CPU time 0.71 seconds
Started Aug 11 05:15:23 PM PDT 24
Finished Aug 11 05:15:23 PM PDT 24
Peak memory 196748 kb
Host smart-873eed02-0f41-40ed-89a8-55e6b34fb038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125553723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2125553723
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2806945536
Short name T147
Test name
Test status
Simulation time 244754593594 ps
CPU time 378.38 seconds
Started Aug 11 05:12:26 PM PDT 24
Finished Aug 11 05:18:45 PM PDT 24
Peak memory 191976 kb
Host smart-be7318cd-04c4-4084-a0cc-035a70bee6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806945536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2806945536
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2656465617
Short name T189
Test name
Test status
Simulation time 242336474682 ps
CPU time 335.67 seconds
Started Aug 11 05:11:32 PM PDT 24
Finished Aug 11 05:17:08 PM PDT 24
Peak memory 192056 kb
Host smart-3e5f5485-6a62-4fb4-88ab-952626e8cd57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656465617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2656465617
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3925599722
Short name T183
Test name
Test status
Simulation time 400987958 ps
CPU time 0.77 seconds
Started Aug 11 05:14:55 PM PDT 24
Finished Aug 11 05:14:56 PM PDT 24
Peak memory 196868 kb
Host smart-adbc83fd-8b83-49d6-8c02-13eb7bf95a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925599722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3925599722
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4194003401
Short name T78
Test name
Test status
Simulation time 161980874735 ps
CPU time 226.82 seconds
Started Aug 11 05:15:34 PM PDT 24
Finished Aug 11 05:19:21 PM PDT 24
Peak memory 192644 kb
Host smart-30adf6f2-733d-449e-b164-e94a99c9b9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194003401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4194003401
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1233156332
Short name T99
Test name
Test status
Simulation time 10850445010 ps
CPU time 38.26 seconds
Started Aug 11 05:15:28 PM PDT 24
Finished Aug 11 05:16:06 PM PDT 24
Peak memory 206884 kb
Host smart-45d240cc-928e-4c66-a84e-e26d77d2d1b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233156332 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1233156332
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3471196058
Short name T62
Test name
Test status
Simulation time 201943186077 ps
CPU time 241.98 seconds
Started Aug 11 05:15:41 PM PDT 24
Finished Aug 11 05:19:43 PM PDT 24
Peak memory 198488 kb
Host smart-60080d66-6626-414b-9105-3da3a99a8d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471196058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3471196058
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1190494604
Short name T12
Test name
Test status
Simulation time 417969021473 ps
CPU time 646.17 seconds
Started Aug 11 05:15:42 PM PDT 24
Finished Aug 11 05:26:28 PM PDT 24
Peak memory 192076 kb
Host smart-ce9929b2-7c80-43a7-891c-aad623e6f27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190494604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1190494604
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3407578510
Short name T174
Test name
Test status
Simulation time 422763137 ps
CPU time 0.9 seconds
Started Aug 11 05:12:18 PM PDT 24
Finished Aug 11 05:12:19 PM PDT 24
Peak memory 196860 kb
Host smart-570d1149-c604-47d8-8536-57511457264e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407578510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3407578510
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3322365237
Short name T201
Test name
Test status
Simulation time 8204976581 ps
CPU time 3.74 seconds
Started Aug 11 05:16:50 PM PDT 24
Finished Aug 11 05:16:54 PM PDT 24
Peak memory 198300 kb
Host smart-1f112768-693e-4d09-974c-6d834af91a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322365237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3322365237
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4135909957
Short name T191
Test name
Test status
Simulation time 622589635 ps
CPU time 1.07 seconds
Started Aug 11 05:12:40 PM PDT 24
Finished Aug 11 05:12:41 PM PDT 24
Peak memory 196792 kb
Host smart-f6e003c1-ad85-4511-b86f-c1ac8d0c6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135909957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4135909957
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2415240810
Short name T195
Test name
Test status
Simulation time 393692899 ps
CPU time 1.18 seconds
Started Aug 11 05:13:09 PM PDT 24
Finished Aug 11 05:13:10 PM PDT 24
Peak memory 196724 kb
Host smart-71757ec7-8aac-465c-8f50-a6cd0cce7da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415240810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2415240810
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2700752112
Short name T153
Test name
Test status
Simulation time 529248434 ps
CPU time 0.73 seconds
Started Aug 11 05:14:10 PM PDT 24
Finished Aug 11 05:14:11 PM PDT 24
Peak memory 196824 kb
Host smart-84d69202-83d1-4a85-89b9-fc7ed3466471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700752112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2700752112
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2228396783
Short name T178
Test name
Test status
Simulation time 546792102 ps
CPU time 1.45 seconds
Started Aug 11 05:14:17 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 196784 kb
Host smart-1ad2c6a4-3647-4c12-aa7a-aba650487d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228396783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2228396783
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.662754285
Short name T188
Test name
Test status
Simulation time 406291561 ps
CPU time 1.23 seconds
Started Aug 11 05:14:27 PM PDT 24
Finished Aug 11 05:14:29 PM PDT 24
Peak memory 196760 kb
Host smart-f006bce7-7d6d-453f-894c-77485cea79a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662754285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.662754285
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3972281007
Short name T165
Test name
Test status
Simulation time 243616943771 ps
CPU time 170.11 seconds
Started Aug 11 05:14:29 PM PDT 24
Finished Aug 11 05:17:19 PM PDT 24
Peak memory 198420 kb
Host smart-bfac836f-0660-4a78-bfaf-e5a6be7bc7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972281007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3972281007
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3826281618
Short name T98
Test name
Test status
Simulation time 57250637410 ps
CPU time 113.47 seconds
Started Aug 11 05:14:43 PM PDT 24
Finished Aug 11 05:16:37 PM PDT 24
Peak memory 198704 kb
Host smart-e1249707-769e-44e4-8857-9c9a62df0175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826281618 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3826281618
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1755917835
Short name T182
Test name
Test status
Simulation time 518561779 ps
CPU time 0.76 seconds
Started Aug 11 05:15:35 PM PDT 24
Finished Aug 11 05:15:36 PM PDT 24
Peak memory 196800 kb
Host smart-40f0f9f7-e8ef-461d-bb5c-c1fd8e2885c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755917835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1755917835
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2066273379
Short name T197
Test name
Test status
Simulation time 107815696949 ps
CPU time 40.89 seconds
Started Aug 11 05:15:53 PM PDT 24
Finished Aug 11 05:16:34 PM PDT 24
Peak memory 198536 kb
Host smart-8cedcba3-c8b7-4a3a-bc68-686126819323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066273379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2066273379
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4062492677
Short name T193
Test name
Test status
Simulation time 29346965235 ps
CPU time 206.15 seconds
Started Aug 11 05:15:47 PM PDT 24
Finished Aug 11 05:19:14 PM PDT 24
Peak memory 206868 kb
Host smart-00b3ac2a-b5c7-4882-b746-43e3d829bd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062492677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4062492677
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3206264385
Short name T190
Test name
Test status
Simulation time 520076567 ps
CPU time 1.35 seconds
Started Aug 11 05:16:04 PM PDT 24
Finished Aug 11 05:16:05 PM PDT 24
Peak memory 196748 kb
Host smart-ddb1e5c9-8097-4f6f-b720-48ca7d3b1a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206264385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3206264385
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2756638512
Short name T187
Test name
Test status
Simulation time 385323059 ps
CPU time 0.71 seconds
Started Aug 11 05:11:17 PM PDT 24
Finished Aug 11 05:11:18 PM PDT 24
Peak memory 196824 kb
Host smart-d64ca72f-7434-40e1-8162-2e638b57f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756638512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2756638512
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1107234717
Short name T45
Test name
Test status
Simulation time 360343066 ps
CPU time 1.06 seconds
Started Aug 11 05:12:50 PM PDT 24
Finished Aug 11 05:12:51 PM PDT 24
Peak memory 196828 kb
Host smart-e64cbdcd-0d4e-4a14-921c-e0dcabba5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107234717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1107234717
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3325324621
Short name T170
Test name
Test status
Simulation time 313986503036 ps
CPU time 123.27 seconds
Started Aug 11 05:12:55 PM PDT 24
Finished Aug 11 05:14:58 PM PDT 24
Peak memory 192084 kb
Host smart-b9cf5fa4-75bd-4dd5-b018-a3261fd44b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325324621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3325324621
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3204078230
Short name T172
Test name
Test status
Simulation time 437374146 ps
CPU time 1.2 seconds
Started Aug 11 05:13:37 PM PDT 24
Finished Aug 11 05:13:38 PM PDT 24
Peak memory 196776 kb
Host smart-206bf980-252a-410d-b56e-ebc3037f10f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204078230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3204078230
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3706293477
Short name T192
Test name
Test status
Simulation time 405111411 ps
CPU time 1.26 seconds
Started Aug 11 05:13:51 PM PDT 24
Finished Aug 11 05:13:52 PM PDT 24
Peak memory 196756 kb
Host smart-23013c7f-91a4-4ce0-9cc8-ad7b7da48ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706293477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3706293477
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3413543180
Short name T77
Test name
Test status
Simulation time 492493354 ps
CPU time 0.81 seconds
Started Aug 11 05:14:04 PM PDT 24
Finished Aug 11 05:14:04 PM PDT 24
Peak memory 196760 kb
Host smart-69adb901-7eba-4fb1-bf7c-49390d3bc847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413543180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3413543180
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2762107989
Short name T175
Test name
Test status
Simulation time 233104526253 ps
CPU time 168.53 seconds
Started Aug 11 05:14:16 PM PDT 24
Finished Aug 11 05:17:05 PM PDT 24
Peak memory 198440 kb
Host smart-71db1c1c-3234-4590-bb0e-2be710aa869d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762107989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2762107989
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.38771152
Short name T185
Test name
Test status
Simulation time 557373745 ps
CPU time 0.81 seconds
Started Aug 11 05:14:29 PM PDT 24
Finished Aug 11 05:14:30 PM PDT 24
Peak memory 196768 kb
Host smart-532933e8-4859-4853-957a-3398508de4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38771152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.38771152
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.882133018
Short name T186
Test name
Test status
Simulation time 536933381 ps
CPU time 0.84 seconds
Started Aug 11 05:14:49 PM PDT 24
Finished Aug 11 05:14:50 PM PDT 24
Peak memory 196704 kb
Host smart-42bbc88d-4a03-4282-b3a8-0606b7b4ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882133018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.882133018
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1683137401
Short name T67
Test name
Test status
Simulation time 590962595 ps
CPU time 1.38 seconds
Started Aug 11 05:14:55 PM PDT 24
Finished Aug 11 05:14:56 PM PDT 24
Peak memory 196768 kb
Host smart-308d0359-c043-4846-ab91-822da8267b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683137401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1683137401
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1077416616
Short name T180
Test name
Test status
Simulation time 472096917 ps
CPU time 1.25 seconds
Started Aug 11 05:15:03 PM PDT 24
Finished Aug 11 05:15:04 PM PDT 24
Peak memory 196732 kb
Host smart-34228af1-77fe-4c60-8944-cf01da9075e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077416616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1077416616
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.868077970
Short name T198
Test name
Test status
Simulation time 123900971203 ps
CPU time 145.52 seconds
Started Aug 11 05:15:52 PM PDT 24
Finished Aug 11 05:18:18 PM PDT 24
Peak memory 192016 kb
Host smart-1fcec16c-771f-4d10-9fa8-5771c8b4eb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868077970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.868077970
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.685110766
Short name T199
Test name
Test status
Simulation time 509033252 ps
CPU time 0.74 seconds
Started Aug 11 05:12:24 PM PDT 24
Finished Aug 11 05:12:25 PM PDT 24
Peak memory 196708 kb
Host smart-73319b3e-10b8-4a0a-8161-8f921819260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685110766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.685110766
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1392647278
Short name T359
Test name
Test status
Simulation time 548990011 ps
CPU time 1.1 seconds
Started Aug 11 05:16:11 PM PDT 24
Finished Aug 11 05:16:12 PM PDT 24
Peak memory 183668 kb
Host smart-9cace8b1-18c2-4e15-b03f-172f5153bc1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392647278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1392647278
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1531145400
Short name T376
Test name
Test status
Simulation time 13683966390 ps
CPU time 18.49 seconds
Started Aug 11 05:16:10 PM PDT 24
Finished Aug 11 05:16:29 PM PDT 24
Peak memory 192132 kb
Host smart-8150a6b0-d508-48c3-aaff-313fa5f28c4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531145400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1531145400
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3386857273
Short name T74
Test name
Test status
Simulation time 870449963 ps
CPU time 0.9 seconds
Started Aug 11 05:16:10 PM PDT 24
Finished Aug 11 05:16:12 PM PDT 24
Peak memory 192888 kb
Host smart-4fad28d0-448c-46ea-bcef-b713750705bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386857273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3386857273
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3206671901
Short name T361
Test name
Test status
Simulation time 296876339 ps
CPU time 1.05 seconds
Started Aug 11 05:16:17 PM PDT 24
Finished Aug 11 05:16:18 PM PDT 24
Peak memory 195668 kb
Host smart-43a8fbf0-c777-472d-8c15-0909a60d004f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206671901 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3206671901
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.96520463
Short name T390
Test name
Test status
Simulation time 319064142 ps
CPU time 0.85 seconds
Started Aug 11 05:16:10 PM PDT 24
Finished Aug 11 05:16:11 PM PDT 24
Peak memory 193000 kb
Host smart-8880b6e1-983c-47c9-8cfa-e7d8100af113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96520463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.96520463
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3155254571
Short name T349
Test name
Test status
Simulation time 506715498 ps
CPU time 0.89 seconds
Started Aug 11 05:16:08 PM PDT 24
Finished Aug 11 05:16:09 PM PDT 24
Peak memory 192920 kb
Host smart-2d931a03-f793-49f3-b9db-45fd41b5e20f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155254571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3155254571
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1633342011
Short name T344
Test name
Test status
Simulation time 521613893 ps
CPU time 0.88 seconds
Started Aug 11 05:16:05 PM PDT 24
Finished Aug 11 05:16:06 PM PDT 24
Peak memory 183592 kb
Host smart-2c032021-6353-4168-8089-dd49c1ea5b46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633342011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1633342011
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3813530951
Short name T337
Test name
Test status
Simulation time 486738607 ps
CPU time 0.68 seconds
Started Aug 11 05:16:03 PM PDT 24
Finished Aug 11 05:16:04 PM PDT 24
Peak memory 183596 kb
Host smart-c83ba33b-150e-49b7-bd1c-ad3e2d38f5a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813530951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3813530951
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1932384815
Short name T320
Test name
Test status
Simulation time 467664435 ps
CPU time 2.88 seconds
Started Aug 11 05:16:05 PM PDT 24
Finished Aug 11 05:16:08 PM PDT 24
Peak memory 198520 kb
Host smart-79e2002e-cf01-458a-912c-1eaf5f99435a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932384815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1932384815
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3776679666
Short name T315
Test name
Test status
Simulation time 8515046291 ps
CPU time 8.16 seconds
Started Aug 11 05:16:05 PM PDT 24
Finished Aug 11 05:16:13 PM PDT 24
Peak memory 198232 kb
Host smart-c7f2fcaf-6db6-44c0-a25b-faba6862ce83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776679666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3776679666
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1089896995
Short name T60
Test name
Test status
Simulation time 476666942 ps
CPU time 1.37 seconds
Started Aug 11 05:16:23 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 183776 kb
Host smart-90ad95a9-1812-4631-a36f-a762fffdf939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089896995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1089896995
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1975985374
Short name T324
Test name
Test status
Simulation time 7326325619 ps
CPU time 3.86 seconds
Started Aug 11 05:16:24 PM PDT 24
Finished Aug 11 05:16:28 PM PDT 24
Peak memory 192208 kb
Host smart-71f68ae5-e6c9-4b21-901e-af9353e651b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975985374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1975985374
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.595250449
Short name T332
Test name
Test status
Simulation time 738052300 ps
CPU time 0.86 seconds
Started Aug 11 05:16:23 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 192140 kb
Host smart-0ae31bae-7eb2-4db2-9872-4afbdc1fa4bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595250449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.595250449
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3932546276
Short name T396
Test name
Test status
Simulation time 422738404 ps
CPU time 1.32 seconds
Started Aug 11 05:16:31 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 196352 kb
Host smart-df2d90d5-9eab-4bb9-aada-0b6c870edbbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932546276 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3932546276
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1127278470
Short name T70
Test name
Test status
Simulation time 532745477 ps
CPU time 1.41 seconds
Started Aug 11 05:16:25 PM PDT 24
Finished Aug 11 05:16:27 PM PDT 24
Peak memory 193940 kb
Host smart-987128fa-7b20-4f84-bb39-08cf4c752172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127278470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1127278470
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.694324784
Short name T397
Test name
Test status
Simulation time 470729433 ps
CPU time 1.22 seconds
Started Aug 11 05:16:17 PM PDT 24
Finished Aug 11 05:16:18 PM PDT 24
Peak memory 183668 kb
Host smart-a74eaf35-a47d-4f3a-af05-c515ce92f707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694324784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.694324784
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4102663602
Short name T311
Test name
Test status
Simulation time 358697240 ps
CPU time 1.09 seconds
Started Aug 11 05:16:23 PM PDT 24
Finished Aug 11 05:16:25 PM PDT 24
Peak memory 183632 kb
Host smart-42bcd4da-eb22-4742-977a-b1c359f842f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102663602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4102663602
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1000132998
Short name T415
Test name
Test status
Simulation time 326662565 ps
CPU time 0.94 seconds
Started Aug 11 05:16:17 PM PDT 24
Finished Aug 11 05:16:18 PM PDT 24
Peak memory 183592 kb
Host smart-7047898b-c352-44a0-aae6-178de0f74ee8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000132998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1000132998
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.200238325
Short name T371
Test name
Test status
Simulation time 1219779645 ps
CPU time 0.99 seconds
Started Aug 11 05:16:23 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 192908 kb
Host smart-be404462-e14c-4774-b3b0-746cd5e0f32a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200238325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.200238325
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2751602043
Short name T392
Test name
Test status
Simulation time 360638954 ps
CPU time 1.17 seconds
Started Aug 11 05:16:16 PM PDT 24
Finished Aug 11 05:16:18 PM PDT 24
Peak memory 198336 kb
Host smart-ac8f1206-655b-4c84-abc2-667517f152b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751602043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2751602043
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3957117370
Short name T34
Test name
Test status
Simulation time 4345697704 ps
CPU time 6.63 seconds
Started Aug 11 05:16:18 PM PDT 24
Finished Aug 11 05:16:24 PM PDT 24
Peak memory 197932 kb
Host smart-790502e3-aaff-4602-86b8-afd8b4194299
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957117370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3957117370
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.696758593
Short name T207
Test name
Test status
Simulation time 383383100 ps
CPU time 1.2 seconds
Started Aug 11 05:17:12 PM PDT 24
Finished Aug 11 05:17:14 PM PDT 24
Peak memory 196188 kb
Host smart-d66ab0fa-b8cf-4995-a48c-8ad4e610fea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696758593 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.696758593
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3809920762
Short name T402
Test name
Test status
Simulation time 595894459 ps
CPU time 0.79 seconds
Started Aug 11 05:17:14 PM PDT 24
Finished Aug 11 05:17:15 PM PDT 24
Peak memory 193092 kb
Host smart-1a9e7f42-e7f4-4d7c-8145-460a36393aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809920762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3809920762
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2989386424
Short name T419
Test name
Test status
Simulation time 417444830 ps
CPU time 1.07 seconds
Started Aug 11 05:17:14 PM PDT 24
Finished Aug 11 05:17:15 PM PDT 24
Peak memory 192896 kb
Host smart-b1397965-9efd-428b-bb62-33598e63aed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989386424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2989386424
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1785871228
Short name T363
Test name
Test status
Simulation time 1321478883 ps
CPU time 2.42 seconds
Started Aug 11 05:17:14 PM PDT 24
Finished Aug 11 05:17:16 PM PDT 24
Peak memory 192964 kb
Host smart-149ee84b-4bda-4d7b-9a20-de15fd5d0641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785871228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1785871228
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.225914629
Short name T310
Test name
Test status
Simulation time 698991291 ps
CPU time 1.54 seconds
Started Aug 11 05:17:15 PM PDT 24
Finished Aug 11 05:17:17 PM PDT 24
Peak memory 198500 kb
Host smart-177f81c6-2421-47e0-a1be-c5f5d77a59d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225914629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.225914629
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2974077930
Short name T322
Test name
Test status
Simulation time 557903901 ps
CPU time 1.55 seconds
Started Aug 11 05:17:17 PM PDT 24
Finished Aug 11 05:17:19 PM PDT 24
Peak memory 196588 kb
Host smart-aae7052e-a23c-4072-a0e1-847fb2d06b91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974077930 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2974077930
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1317102151
Short name T408
Test name
Test status
Simulation time 416661011 ps
CPU time 1.27 seconds
Started Aug 11 05:17:19 PM PDT 24
Finished Aug 11 05:17:21 PM PDT 24
Peak memory 193484 kb
Host smart-627e45bf-011c-4a5d-9b58-ab6e901ec9e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317102151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1317102151
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.470491130
Short name T420
Test name
Test status
Simulation time 367467909 ps
CPU time 1.09 seconds
Started Aug 11 05:17:21 PM PDT 24
Finished Aug 11 05:17:22 PM PDT 24
Peak memory 192924 kb
Host smart-05da51f9-42db-4cc6-b283-b818793c9d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470491130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.470491130
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3557627664
Short name T31
Test name
Test status
Simulation time 2211432943 ps
CPU time 1.47 seconds
Started Aug 11 05:17:23 PM PDT 24
Finished Aug 11 05:17:24 PM PDT 24
Peak memory 192008 kb
Host smart-3911b943-67ba-4046-9642-dae51832144a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557627664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3557627664
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1903826754
Short name T417
Test name
Test status
Simulation time 928095018 ps
CPU time 1.26 seconds
Started Aug 11 05:17:14 PM PDT 24
Finished Aug 11 05:17:16 PM PDT 24
Peak memory 198632 kb
Host smart-8e0cc158-e7c5-42e8-9e45-b34bd7caf47d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903826754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1903826754
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3259642967
Short name T306
Test name
Test status
Simulation time 4431899108 ps
CPU time 2.54 seconds
Started Aug 11 05:17:15 PM PDT 24
Finished Aug 11 05:17:17 PM PDT 24
Peak memory 197944 kb
Host smart-161fb447-cfbe-49c8-97db-d1d6a1989428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259642967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3259642967
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.473323655
Short name T290
Test name
Test status
Simulation time 474260390 ps
CPU time 0.8 seconds
Started Aug 11 05:17:22 PM PDT 24
Finished Aug 11 05:17:23 PM PDT 24
Peak memory 195340 kb
Host smart-6fc7b5c3-d00b-400c-b988-239b2aec4a5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473323655 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.473323655
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.212454124
Short name T411
Test name
Test status
Simulation time 463457523 ps
CPU time 1.2 seconds
Started Aug 11 05:17:20 PM PDT 24
Finished Aug 11 05:17:21 PM PDT 24
Peak memory 193160 kb
Host smart-049490ad-520c-4e4e-a69b-b5437d267780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212454124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.212454124
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2804600177
Short name T334
Test name
Test status
Simulation time 301963243 ps
CPU time 0.64 seconds
Started Aug 11 05:17:20 PM PDT 24
Finished Aug 11 05:17:21 PM PDT 24
Peak memory 183968 kb
Host smart-4ee10df2-104f-4824-a7d3-36ad379e95a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804600177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2804600177
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3535901062
Short name T373
Test name
Test status
Simulation time 2441034383 ps
CPU time 4.24 seconds
Started Aug 11 05:17:21 PM PDT 24
Finished Aug 11 05:17:26 PM PDT 24
Peak memory 193980 kb
Host smart-502b1a83-e254-4424-9770-382207d5a769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535901062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3535901062
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.388412334
Short name T379
Test name
Test status
Simulation time 385286160 ps
CPU time 1.9 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:29 PM PDT 24
Peak memory 198536 kb
Host smart-6a227858-f492-482f-86ee-edf0d5a35bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388412334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.388412334
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3241895628
Short name T35
Test name
Test status
Simulation time 4401153160 ps
CPU time 4.28 seconds
Started Aug 11 05:17:24 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 198028 kb
Host smart-14e0038f-329b-4b46-9ba8-820e9b8e9489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241895628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3241895628
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.17102655
Short name T346
Test name
Test status
Simulation time 688429648 ps
CPU time 1.11 seconds
Started Aug 11 05:17:28 PM PDT 24
Finished Aug 11 05:17:29 PM PDT 24
Peak memory 198316 kb
Host smart-2a6bed17-6f89-45e8-8933-d70082a401a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102655 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.17102655
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.555651102
Short name T71
Test name
Test status
Simulation time 495229595 ps
CPU time 0.92 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 193948 kb
Host smart-6ea0d25c-5cae-4106-8469-90385c6bd98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555651102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.555651102
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.237077281
Short name T299
Test name
Test status
Simulation time 447702098 ps
CPU time 0.59 seconds
Started Aug 11 05:17:21 PM PDT 24
Finished Aug 11 05:17:22 PM PDT 24
Peak memory 183600 kb
Host smart-e7077f69-c531-4e57-b949-4e941db836fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237077281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.237077281
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2291576359
Short name T368
Test name
Test status
Simulation time 2849749114 ps
CPU time 6.28 seconds
Started Aug 11 05:17:26 PM PDT 24
Finished Aug 11 05:17:33 PM PDT 24
Peak memory 195100 kb
Host smart-2cb00e26-7c60-4225-a793-e8322161ff65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291576359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2291576359
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1461584320
Short name T377
Test name
Test status
Simulation time 514891847 ps
CPU time 2.92 seconds
Started Aug 11 05:17:20 PM PDT 24
Finished Aug 11 05:17:23 PM PDT 24
Peak memory 198592 kb
Host smart-aa2e4cec-16cd-480e-8276-13510cfb49a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461584320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1461584320
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1692950439
Short name T367
Test name
Test status
Simulation time 4405784101 ps
CPU time 6.47 seconds
Started Aug 11 05:17:21 PM PDT 24
Finished Aug 11 05:17:27 PM PDT 24
Peak memory 197860 kb
Host smart-bd54e411-1f23-45c5-ac73-780be5b3bb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692950439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1692950439
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3311371935
Short name T352
Test name
Test status
Simulation time 560644197 ps
CPU time 1.11 seconds
Started Aug 11 05:17:26 PM PDT 24
Finished Aug 11 05:17:27 PM PDT 24
Peak memory 196344 kb
Host smart-f8bb3a32-c13a-4b21-89f0-4fe28ff4026b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311371935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3311371935
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2548133922
Short name T90
Test name
Test status
Simulation time 376434072 ps
CPU time 0.73 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 193292 kb
Host smart-74210a31-5e16-4d8e-ba1a-7224e2b71566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548133922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2548133922
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1646096406
Short name T366
Test name
Test status
Simulation time 385969925 ps
CPU time 1.15 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 183736 kb
Host smart-d58e7c4f-8900-4539-840a-0a56e25e58f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646096406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1646096406
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3804988088
Short name T32
Test name
Test status
Simulation time 2741543292 ps
CPU time 1.51 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:29 PM PDT 24
Peak memory 194968 kb
Host smart-2755bd8f-a315-4514-82d9-35144ac7597d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804988088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3804988088
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.454280503
Short name T410
Test name
Test status
Simulation time 543453735 ps
CPU time 1.2 seconds
Started Aug 11 05:17:26 PM PDT 24
Finished Aug 11 05:17:27 PM PDT 24
Peak memory 198184 kb
Host smart-fb255d8b-0eec-479b-9b41-1ca88083d72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454280503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.454280503
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1891053633
Short name T200
Test name
Test status
Simulation time 7817372730 ps
CPU time 12.78 seconds
Started Aug 11 05:17:27 PM PDT 24
Finished Aug 11 05:17:40 PM PDT 24
Peak memory 198168 kb
Host smart-7bfd74eb-e3c3-4b59-82d2-26a41757b579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891053633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1891053633
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3878940750
Short name T355
Test name
Test status
Simulation time 327579800 ps
CPU time 1.17 seconds
Started Aug 11 05:17:34 PM PDT 24
Finished Aug 11 05:17:35 PM PDT 24
Peak memory 196384 kb
Host smart-8b84beeb-fed7-4d3f-a7ae-25648c858955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878940750 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3878940750
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2802893769
Short name T351
Test name
Test status
Simulation time 517327771 ps
CPU time 0.77 seconds
Started Aug 11 05:17:34 PM PDT 24
Finished Aug 11 05:17:35 PM PDT 24
Peak memory 193192 kb
Host smart-e21ff952-3505-43e7-b982-7f7e871133fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802893769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2802893769
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3273207361
Short name T288
Test name
Test status
Simulation time 310049219 ps
CPU time 1.06 seconds
Started Aug 11 05:17:28 PM PDT 24
Finished Aug 11 05:17:29 PM PDT 24
Peak memory 183676 kb
Host smart-cc36a755-4a26-46bf-bedf-fdd71c845a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273207361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3273207361
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1149611014
Short name T347
Test name
Test status
Simulation time 1715788328 ps
CPU time 2.61 seconds
Started Aug 11 05:17:32 PM PDT 24
Finished Aug 11 05:17:34 PM PDT 24
Peak memory 192844 kb
Host smart-ad8267ec-7464-4924-adb8-068d1365d3f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149611014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1149611014
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.323241079
Short name T328
Test name
Test status
Simulation time 537878013 ps
CPU time 1.13 seconds
Started Aug 11 05:17:26 PM PDT 24
Finished Aug 11 05:17:27 PM PDT 24
Peak memory 197264 kb
Host smart-1b0fb5cd-50eb-4a9a-a3b3-1d82164b43c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323241079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.323241079
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.642584290
Short name T316
Test name
Test status
Simulation time 4468782095 ps
CPU time 2.64 seconds
Started Aug 11 05:17:25 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 196704 kb
Host smart-32645a0e-ede3-4660-8da2-8dcd18355d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642584290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.642584290
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.583885259
Short name T382
Test name
Test status
Simulation time 459219777 ps
CPU time 1.22 seconds
Started Aug 11 05:17:33 PM PDT 24
Finished Aug 11 05:17:34 PM PDT 24
Peak memory 195528 kb
Host smart-b7855f83-625e-44ff-b4f4-f57777a3c38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583885259 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.583885259
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.215751257
Short name T55
Test name
Test status
Simulation time 378651866 ps
CPU time 1.15 seconds
Started Aug 11 05:17:35 PM PDT 24
Finished Aug 11 05:17:36 PM PDT 24
Peak memory 192888 kb
Host smart-b0295e8a-3206-4aac-b300-bf2df7f45736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215751257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.215751257
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1300160500
Short name T291
Test name
Test status
Simulation time 491114321 ps
CPU time 0.87 seconds
Started Aug 11 05:17:34 PM PDT 24
Finished Aug 11 05:17:35 PM PDT 24
Peak memory 183984 kb
Host smart-14e8cae2-c1f4-4a58-9a81-8b70932b76bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300160500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1300160500
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3947961878
Short name T92
Test name
Test status
Simulation time 1459462036 ps
CPU time 4.09 seconds
Started Aug 11 05:17:33 PM PDT 24
Finished Aug 11 05:17:37 PM PDT 24
Peak memory 194020 kb
Host smart-8aca197c-b993-4038-9834-b7ee188657c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947961878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3947961878
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3753236204
Short name T342
Test name
Test status
Simulation time 358023021 ps
CPU time 1.71 seconds
Started Aug 11 05:17:34 PM PDT 24
Finished Aug 11 05:17:36 PM PDT 24
Peak memory 198536 kb
Host smart-d36c03d4-bd16-4603-86a0-1ae9cb534e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753236204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3753236204
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1885830338
Short name T387
Test name
Test status
Simulation time 3811975282 ps
CPU time 3.89 seconds
Started Aug 11 05:17:32 PM PDT 24
Finished Aug 11 05:17:36 PM PDT 24
Peak memory 196824 kb
Host smart-74b5a608-dc04-4476-b1db-afc2beee4a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885830338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1885830338
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3555502775
Short name T365
Test name
Test status
Simulation time 620879538 ps
CPU time 0.98 seconds
Started Aug 11 05:17:41 PM PDT 24
Finished Aug 11 05:17:42 PM PDT 24
Peak memory 196800 kb
Host smart-d0db3b01-b2bf-4c12-a1cd-06b84d44f6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555502775 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3555502775
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1510840801
Short name T318
Test name
Test status
Simulation time 384295556 ps
CPU time 1.11 seconds
Started Aug 11 05:17:39 PM PDT 24
Finished Aug 11 05:17:40 PM PDT 24
Peak memory 193936 kb
Host smart-47933ccb-9971-469b-a6e8-69d6e6742c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510840801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1510840801
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2430058562
Short name T364
Test name
Test status
Simulation time 518441627 ps
CPU time 0.71 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:41 PM PDT 24
Peak memory 192916 kb
Host smart-62d12b97-fda5-4062-b1ec-8f0a7daed034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430058562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2430058562
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3411666788
Short name T327
Test name
Test status
Simulation time 2800579169 ps
CPU time 4.94 seconds
Started Aug 11 05:17:41 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 194964 kb
Host smart-ed12b85a-e128-4291-b6ed-65e21d57513e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411666788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3411666788
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2123941828
Short name T380
Test name
Test status
Simulation time 338992135 ps
CPU time 2.3 seconds
Started Aug 11 05:17:32 PM PDT 24
Finished Aug 11 05:17:34 PM PDT 24
Peak memory 198552 kb
Host smart-b7b071ea-ef1b-4ce4-917d-265cc3183bce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123941828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2123941828
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3446466638
Short name T202
Test name
Test status
Simulation time 8419444411 ps
CPU time 12.52 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:53 PM PDT 24
Peak memory 198364 kb
Host smart-a25348de-a67b-45f4-9702-7ffb5d19fce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446466638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3446466638
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3776560441
Short name T313
Test name
Test status
Simulation time 335411818 ps
CPU time 1.06 seconds
Started Aug 11 05:17:39 PM PDT 24
Finished Aug 11 05:17:41 PM PDT 24
Peak memory 196212 kb
Host smart-77b22848-82a1-40a2-b53d-81a760a34e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776560441 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3776560441
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2931457449
Short name T329
Test name
Test status
Simulation time 544041572 ps
CPU time 0.62 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:40 PM PDT 24
Peak memory 192924 kb
Host smart-b0505b8f-0364-464e-a01f-9dfbce20c7f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931457449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2931457449
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2416052284
Short name T345
Test name
Test status
Simulation time 437232055 ps
CPU time 0.61 seconds
Started Aug 11 05:17:42 PM PDT 24
Finished Aug 11 05:17:43 PM PDT 24
Peak memory 183720 kb
Host smart-c5fd7bd3-c2c8-45c0-92dc-a692d0a07af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416052284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2416052284
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2476258989
Short name T350
Test name
Test status
Simulation time 1336591472 ps
CPU time 2.49 seconds
Started Aug 11 05:17:41 PM PDT 24
Finished Aug 11 05:17:43 PM PDT 24
Peak memory 192936 kb
Host smart-c287a9ad-0afa-42f7-86bf-6a0ce631a64a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476258989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2476258989
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3558581290
Short name T412
Test name
Test status
Simulation time 1527934778 ps
CPU time 1.79 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:42 PM PDT 24
Peak memory 198540 kb
Host smart-902b09fb-4293-4a63-949a-427c799e3812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558581290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3558581290
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3242565440
Short name T383
Test name
Test status
Simulation time 3918739977 ps
CPU time 3.84 seconds
Started Aug 11 05:17:39 PM PDT 24
Finished Aug 11 05:17:42 PM PDT 24
Peak memory 197900 kb
Host smart-34a70e72-54e9-417f-b938-b8ffe7cb6142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242565440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3242565440
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4044020590
Short name T323
Test name
Test status
Simulation time 416804854 ps
CPU time 0.9 seconds
Started Aug 11 05:17:43 PM PDT 24
Finished Aug 11 05:17:44 PM PDT 24
Peak memory 198360 kb
Host smart-83c5d9ae-85a7-4c71-bd7f-4030da1ad0a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044020590 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4044020590
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.12865412
Short name T325
Test name
Test status
Simulation time 312408781 ps
CPU time 0.79 seconds
Started Aug 11 05:17:39 PM PDT 24
Finished Aug 11 05:17:40 PM PDT 24
Peak memory 192868 kb
Host smart-12e43d17-4f5b-4b91-9292-b82b8cbfced8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12865412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.12865412
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1905812196
Short name T285
Test name
Test status
Simulation time 478394885 ps
CPU time 1.28 seconds
Started Aug 11 05:17:41 PM PDT 24
Finished Aug 11 05:17:42 PM PDT 24
Peak memory 183600 kb
Host smart-2b3ecc42-628e-4819-ae6a-0fc1d02cae75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905812196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1905812196
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2506227289
Short name T360
Test name
Test status
Simulation time 1107370538 ps
CPU time 2.95 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:43 PM PDT 24
Peak memory 193296 kb
Host smart-28248b9c-6fe0-4df1-9f40-eee0669c0e40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506227289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2506227289
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1090958746
Short name T319
Test name
Test status
Simulation time 413869535 ps
CPU time 1.48 seconds
Started Aug 11 05:17:40 PM PDT 24
Finished Aug 11 05:17:41 PM PDT 24
Peak memory 198532 kb
Host smart-61711410-6ec0-471a-86e5-9de1792ec4b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090958746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1090958746
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3068234392
Short name T338
Test name
Test status
Simulation time 7523512195 ps
CPU time 6.49 seconds
Started Aug 11 05:17:39 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 198352 kb
Host smart-78ea7d90-2637-4207-b7fe-3edfe7338473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068234392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3068234392
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.65873217
Short name T75
Test name
Test status
Simulation time 464076457 ps
CPU time 1.41 seconds
Started Aug 11 05:16:35 PM PDT 24
Finished Aug 11 05:16:37 PM PDT 24
Peak memory 192980 kb
Host smart-60b2411a-a53d-408a-aa18-23042ddfdeba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65873217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_ali
asing.65873217
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2871772901
Short name T57
Test name
Test status
Simulation time 568966655 ps
CPU time 2.3 seconds
Started Aug 11 05:16:37 PM PDT 24
Finished Aug 11 05:16:39 PM PDT 24
Peak memory 195652 kb
Host smart-68162c01-128e-434f-851a-08f92445755d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871772901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2871772901
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3522892620
Short name T362
Test name
Test status
Simulation time 1162297779 ps
CPU time 1.06 seconds
Started Aug 11 05:16:31 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 193840 kb
Host smart-36742173-7314-4b26-bd2a-ff85734da563
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522892620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3522892620
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2026855377
Short name T302
Test name
Test status
Simulation time 381318737 ps
CPU time 1.23 seconds
Started Aug 11 05:16:42 PM PDT 24
Finished Aug 11 05:16:44 PM PDT 24
Peak memory 195948 kb
Host smart-1505b4f2-8ebc-4d46-892e-f673aa1d358e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026855377 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2026855377
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2292569870
Short name T354
Test name
Test status
Simulation time 441272910 ps
CPU time 0.95 seconds
Started Aug 11 05:16:31 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 192884 kb
Host smart-25af6172-4166-4453-a4fe-c28eb919118d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292569870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2292569870
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3583631724
Short name T321
Test name
Test status
Simulation time 504125379 ps
CPU time 1.13 seconds
Started Aug 11 05:16:30 PM PDT 24
Finished Aug 11 05:16:31 PM PDT 24
Peak memory 183688 kb
Host smart-e7575946-76a3-4f96-be51-fd7a2545fea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583631724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3583631724
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3078622573
Short name T358
Test name
Test status
Simulation time 434791858 ps
CPU time 1.14 seconds
Started Aug 11 05:16:30 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 183884 kb
Host smart-0c5f38da-c967-461d-9bd5-fcf287dbca07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078622573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3078622573
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3777382614
Short name T317
Test name
Test status
Simulation time 489102321 ps
CPU time 0.59 seconds
Started Aug 11 05:16:32 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 183592 kb
Host smart-6ef44e65-6ba5-4a0f-bca0-945414a7f229
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777382614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3777382614
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1309299770
Short name T335
Test name
Test status
Simulation time 1244337394 ps
CPU time 1.14 seconds
Started Aug 11 05:16:38 PM PDT 24
Finished Aug 11 05:16:39 PM PDT 24
Peak memory 193516 kb
Host smart-81a617e5-aeae-49e2-925f-eadd4a6e9ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309299770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1309299770
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1724782318
Short name T406
Test name
Test status
Simulation time 684876125 ps
CPU time 2.12 seconds
Started Aug 11 05:16:30 PM PDT 24
Finished Aug 11 05:16:32 PM PDT 24
Peak memory 198536 kb
Host smart-b93138f4-4f8b-4a73-82d6-e1249e8e4639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724782318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1724782318
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2362736104
Short name T326
Test name
Test status
Simulation time 7746412281 ps
CPU time 4.92 seconds
Started Aug 11 05:16:32 PM PDT 24
Finished Aug 11 05:16:37 PM PDT 24
Peak memory 198232 kb
Host smart-b5f7ec1d-4ca7-4857-8c9f-481cbc753398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362736104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2362736104
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2551558018
Short name T384
Test name
Test status
Simulation time 493520081 ps
CPU time 1.3 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 192924 kb
Host smart-a91eb90a-b799-4780-bdfb-ead3239757c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551558018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2551558018
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2977066640
Short name T369
Test name
Test status
Simulation time 300423852 ps
CPU time 0.94 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:45 PM PDT 24
Peak memory 183628 kb
Host smart-f97a703c-fb3d-40f1-860f-54f070abe74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977066640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2977066640
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2938585808
Short name T300
Test name
Test status
Simulation time 317587714 ps
CPU time 0.78 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:44 PM PDT 24
Peak memory 192916 kb
Host smart-0280fae9-00b2-44ee-8cd7-fc72570c6260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938585808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2938585808
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.936564554
Short name T296
Test name
Test status
Simulation time 483792252 ps
CPU time 0.7 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:44 PM PDT 24
Peak memory 183752 kb
Host smart-d5a359f7-9f3a-4c4d-a94e-33fbe3544210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936564554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.936564554
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.704738478
Short name T284
Test name
Test status
Simulation time 470834700 ps
CPU time 0.59 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 193004 kb
Host smart-6725a137-3520-4821-90d4-f59a6322602f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704738478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.704738478
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2967983814
Short name T395
Test name
Test status
Simulation time 519875407 ps
CPU time 0.65 seconds
Started Aug 11 05:17:46 PM PDT 24
Finished Aug 11 05:17:47 PM PDT 24
Peak memory 183696 kb
Host smart-a083b68a-8ffd-457d-8d7c-853c50311be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967983814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2967983814
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1141095260
Short name T356
Test name
Test status
Simulation time 555156847 ps
CPU time 0.63 seconds
Started Aug 11 05:17:48 PM PDT 24
Finished Aug 11 05:17:48 PM PDT 24
Peak memory 183696 kb
Host smart-7e2b6bf8-ad81-441a-aa1b-cb4ed0dc0cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141095260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1141095260
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2211879394
Short name T423
Test name
Test status
Simulation time 345384254 ps
CPU time 1.06 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 183676 kb
Host smart-5b6d1c27-30cd-47f7-b997-8261eb39ccc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211879394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2211879394
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.819235409
Short name T343
Test name
Test status
Simulation time 516459891 ps
CPU time 0.92 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 183684 kb
Host smart-107e9e6b-43eb-4611-9c73-a58af3bd5d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819235409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.819235409
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2807143839
Short name T314
Test name
Test status
Simulation time 442041540 ps
CPU time 0.88 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 183704 kb
Host smart-ca9c0d21-ba3b-4bf3-9eeb-2b04b8395051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807143839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2807143839
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2296957323
Short name T56
Test name
Test status
Simulation time 495625030 ps
CPU time 1.67 seconds
Started Aug 11 05:16:45 PM PDT 24
Finished Aug 11 05:16:46 PM PDT 24
Peak memory 194428 kb
Host smart-3ea47a9a-6729-4a43-88bd-aaa61074fe06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296957323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2296957323
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.567055028
Short name T399
Test name
Test status
Simulation time 1356626260 ps
CPU time 2.59 seconds
Started Aug 11 05:16:41 PM PDT 24
Finished Aug 11 05:16:44 PM PDT 24
Peak memory 193304 kb
Host smart-c3ae6b93-871b-440d-bd13-27e7c1ea483d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567055028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.567055028
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.340339453
Short name T414
Test name
Test status
Simulation time 580767205 ps
CPU time 1.04 seconds
Started Aug 11 05:16:42 PM PDT 24
Finished Aug 11 05:16:43 PM PDT 24
Peak memory 198128 kb
Host smart-c5f9d94a-8dc2-4676-a018-21e1dc25764a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340339453 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.340339453
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2424371534
Short name T86
Test name
Test status
Simulation time 303797434 ps
CPU time 1.09 seconds
Started Aug 11 05:16:43 PM PDT 24
Finished Aug 11 05:16:45 PM PDT 24
Peak memory 193920 kb
Host smart-415701f2-d12d-4081-8ec4-fff92cc6af4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424371534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2424371534
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2822667559
Short name T312
Test name
Test status
Simulation time 367440996 ps
CPU time 1.05 seconds
Started Aug 11 05:16:42 PM PDT 24
Finished Aug 11 05:16:43 PM PDT 24
Peak memory 183652 kb
Host smart-ab729991-c8fa-4439-8332-b3cab3397caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822667559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2822667559
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.214260919
Short name T305
Test name
Test status
Simulation time 390655596 ps
CPU time 0.64 seconds
Started Aug 11 05:16:44 PM PDT 24
Finished Aug 11 05:16:45 PM PDT 24
Peak memory 183508 kb
Host smart-17143e35-0848-4cfb-85ed-a8fd724a9f80
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214260919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.214260919
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4267809818
Short name T398
Test name
Test status
Simulation time 414458971 ps
CPU time 0.65 seconds
Started Aug 11 05:16:43 PM PDT 24
Finished Aug 11 05:16:44 PM PDT 24
Peak memory 183552 kb
Host smart-ec2de080-fc08-414b-9a5e-ac1965c14d2f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267809818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4267809818
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.895193219
Short name T87
Test name
Test status
Simulation time 1490535513 ps
CPU time 2.4 seconds
Started Aug 11 05:16:44 PM PDT 24
Finished Aug 11 05:16:46 PM PDT 24
Peak memory 193856 kb
Host smart-259851a0-8fdf-49b3-bc84-f173b624f7f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895193219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.895193219
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1031132359
Short name T391
Test name
Test status
Simulation time 997190759 ps
CPU time 3.09 seconds
Started Aug 11 05:16:43 PM PDT 24
Finished Aug 11 05:16:46 PM PDT 24
Peak memory 198536 kb
Host smart-ec076d96-932a-4f39-b0f4-3de8bfeb79ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031132359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1031132359
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3186480445
Short name T203
Test name
Test status
Simulation time 9608481741 ps
CPU time 2.53 seconds
Started Aug 11 05:16:44 PM PDT 24
Finished Aug 11 05:16:46 PM PDT 24
Peak memory 198288 kb
Host smart-7260170d-49bd-49b3-87ed-4f258a6f5107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186480445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3186480445
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1744465184
Short name T394
Test name
Test status
Simulation time 567489177 ps
CPU time 0.61 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:45 PM PDT 24
Peak memory 183696 kb
Host smart-2602be6a-3e9d-4e81-adc6-688b7e14f5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744465184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1744465184
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1601068514
Short name T304
Test name
Test status
Simulation time 439696620 ps
CPU time 0.88 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 183676 kb
Host smart-b59e700f-9bce-415e-8771-d1d4d9dfecfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601068514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1601068514
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.864073358
Short name T370
Test name
Test status
Simulation time 289415244 ps
CPU time 0.78 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:45 PM PDT 24
Peak memory 183720 kb
Host smart-ec884aa5-7337-4444-96e1-a18ebefe4710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864073358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.864073358
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.552617950
Short name T409
Test name
Test status
Simulation time 481132730 ps
CPU time 0.83 seconds
Started Aug 11 05:17:45 PM PDT 24
Finished Aug 11 05:17:46 PM PDT 24
Peak memory 183756 kb
Host smart-fc34a169-cb93-4b41-ab83-b93ae7e2b668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552617950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.552617950
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1328350774
Short name T303
Test name
Test status
Simulation time 333228204 ps
CPU time 0.79 seconds
Started Aug 11 05:17:44 PM PDT 24
Finished Aug 11 05:17:45 PM PDT 24
Peak memory 192900 kb
Host smart-5333c025-b91c-45c4-ab38-21143eb0643f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328350774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1328350774
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.125108605
Short name T378
Test name
Test status
Simulation time 314958434 ps
CPU time 1.02 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 183752 kb
Host smart-9a353f57-54c7-4115-a201-b5b7dc2f78be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125108605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.125108605
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.479972865
Short name T339
Test name
Test status
Simulation time 441011730 ps
CPU time 1.2 seconds
Started Aug 11 05:17:50 PM PDT 24
Finished Aug 11 05:17:52 PM PDT 24
Peak memory 192916 kb
Host smart-4514025d-fb3e-4950-acec-ca60e5d3a9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479972865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.479972865
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3328391384
Short name T293
Test name
Test status
Simulation time 528590713 ps
CPU time 0.73 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 183752 kb
Host smart-251327f7-9c60-4cae-a5c8-4f2b61917ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328391384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3328391384
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2503418481
Short name T333
Test name
Test status
Simulation time 269633715 ps
CPU time 0.74 seconds
Started Aug 11 05:17:54 PM PDT 24
Finished Aug 11 05:17:55 PM PDT 24
Peak memory 192940 kb
Host smart-482dea70-499c-44d4-90be-2e1c2d126ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503418481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2503418481
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2857989350
Short name T389
Test name
Test status
Simulation time 516151393 ps
CPU time 1.3 seconds
Started Aug 11 05:17:54 PM PDT 24
Finished Aug 11 05:17:56 PM PDT 24
Peak memory 192940 kb
Host smart-d22f785d-ef24-45b6-82ef-47926362352e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857989350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2857989350
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3085000176
Short name T36
Test name
Test status
Simulation time 432879609 ps
CPU time 0.75 seconds
Started Aug 11 05:16:55 PM PDT 24
Finished Aug 11 05:16:56 PM PDT 24
Peak memory 183656 kb
Host smart-e2c8ee97-c172-40b8-b6ed-e8c01dafd392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085000176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3085000176
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2017814807
Short name T59
Test name
Test status
Simulation time 1425011950 ps
CPU time 5.3 seconds
Started Aug 11 05:16:56 PM PDT 24
Finished Aug 11 05:17:01 PM PDT 24
Peak memory 196192 kb
Host smart-babdea24-f719-4c04-9bb3-0825c129a69e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017814807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2017814807
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1948116032
Short name T73
Test name
Test status
Simulation time 1333515635 ps
CPU time 2.5 seconds
Started Aug 11 05:16:49 PM PDT 24
Finished Aug 11 05:16:51 PM PDT 24
Peak memory 193072 kb
Host smart-95be427f-85ad-4814-81d3-56f4ec2f4ecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948116032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1948116032
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1581347705
Short name T298
Test name
Test status
Simulation time 375359003 ps
CPU time 1.2 seconds
Started Aug 11 05:16:57 PM PDT 24
Finished Aug 11 05:16:58 PM PDT 24
Peak memory 196340 kb
Host smart-c39c0d9c-bee6-4b45-8d4f-bb5440f541b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581347705 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1581347705
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1874868056
Short name T76
Test name
Test status
Simulation time 330582837 ps
CPU time 0.77 seconds
Started Aug 11 05:16:49 PM PDT 24
Finished Aug 11 05:16:49 PM PDT 24
Peak memory 192904 kb
Host smart-38e44ca9-84ee-4e4d-8d31-831664695461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874868056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1874868056
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2053434102
Short name T405
Test name
Test status
Simulation time 335866704 ps
CPU time 0.77 seconds
Started Aug 11 05:16:51 PM PDT 24
Finished Aug 11 05:16:52 PM PDT 24
Peak memory 183756 kb
Host smart-3fda9cd6-542d-4756-a4c0-f6b644174a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053434102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2053434102
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4119744490
Short name T403
Test name
Test status
Simulation time 507260502 ps
CPU time 0.69 seconds
Started Aug 11 05:16:50 PM PDT 24
Finished Aug 11 05:16:50 PM PDT 24
Peak memory 183628 kb
Host smart-57fe825c-6855-45fb-ba92-e4188c081efe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119744490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4119744490
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.480701012
Short name T307
Test name
Test status
Simulation time 361695903 ps
CPU time 0.77 seconds
Started Aug 11 05:16:52 PM PDT 24
Finished Aug 11 05:16:53 PM PDT 24
Peak memory 183660 kb
Host smart-96dbbd43-ff99-4967-ba35-5f5f1224c8e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480701012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.480701012
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1742658708
Short name T422
Test name
Test status
Simulation time 1749239396 ps
CPU time 1.1 seconds
Started Aug 11 05:16:55 PM PDT 24
Finished Aug 11 05:16:56 PM PDT 24
Peak memory 193944 kb
Host smart-5e2b4546-2a37-4db6-a7e6-d94c16821b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742658708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1742658708
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2973740370
Short name T295
Test name
Test status
Simulation time 599763276 ps
CPU time 2.62 seconds
Started Aug 11 05:16:49 PM PDT 24
Finished Aug 11 05:16:52 PM PDT 24
Peak memory 198576 kb
Host smart-33d0dd99-c3f9-471c-bbf6-c2422a7bbc58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973740370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2973740370
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2845425204
Short name T309
Test name
Test status
Simulation time 453926485 ps
CPU time 0.68 seconds
Started Aug 11 05:17:52 PM PDT 24
Finished Aug 11 05:17:53 PM PDT 24
Peak memory 192896 kb
Host smart-5f8d35ed-4d0c-4cda-9536-4d1171584528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845425204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2845425204
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3181956502
Short name T330
Test name
Test status
Simulation time 269615037 ps
CPU time 0.95 seconds
Started Aug 11 05:17:51 PM PDT 24
Finished Aug 11 05:17:52 PM PDT 24
Peak memory 183600 kb
Host smart-2b088dc4-3f56-493d-a585-eb9ca1f59fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181956502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3181956502
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1743177685
Short name T374
Test name
Test status
Simulation time 331614504 ps
CPU time 1.06 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 183752 kb
Host smart-915e89ee-b045-4d60-b9f5-7c8f91bf9d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743177685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1743177685
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3925441579
Short name T381
Test name
Test status
Simulation time 371590487 ps
CPU time 0.61 seconds
Started Aug 11 05:17:52 PM PDT 24
Finished Aug 11 05:17:53 PM PDT 24
Peak memory 192972 kb
Host smart-663474c2-6054-4a83-9cfc-0565724dff24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925441579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3925441579
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1737763116
Short name T348
Test name
Test status
Simulation time 489816619 ps
CPU time 0.73 seconds
Started Aug 11 05:17:53 PM PDT 24
Finished Aug 11 05:17:53 PM PDT 24
Peak memory 183696 kb
Host smart-c8bed56a-cd9b-420d-ba24-b6c84f29a19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737763116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1737763116
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1220065679
Short name T297
Test name
Test status
Simulation time 531193640 ps
CPU time 0.6 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 183724 kb
Host smart-1e7b8dbc-76ce-4e36-ae3f-a3459454aa08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220065679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1220065679
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3999513329
Short name T287
Test name
Test status
Simulation time 503526511 ps
CPU time 0.72 seconds
Started Aug 11 05:17:52 PM PDT 24
Finished Aug 11 05:17:53 PM PDT 24
Peak memory 183672 kb
Host smart-d2dcdd85-633a-4eb1-b6e2-f34039f3938e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999513329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3999513329
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.734110261
Short name T289
Test name
Test status
Simulation time 335011338 ps
CPU time 0.7 seconds
Started Aug 11 05:17:56 PM PDT 24
Finished Aug 11 05:17:57 PM PDT 24
Peak memory 183784 kb
Host smart-fd14995a-d6e9-4b29-b2ef-240ae2f8eeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734110261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.734110261
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1715236566
Short name T341
Test name
Test status
Simulation time 378060546 ps
CPU time 0.87 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 193212 kb
Host smart-df970c88-242c-4a82-bfdd-7c03dc212580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715236566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1715236566
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1867283518
Short name T331
Test name
Test status
Simulation time 671657228 ps
CPU time 0.59 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 183688 kb
Host smart-00ab070a-3198-45b0-8430-7bb1b641d753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867283518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1867283518
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3365902512
Short name T357
Test name
Test status
Simulation time 540569051 ps
CPU time 1.01 seconds
Started Aug 11 05:17:05 PM PDT 24
Finished Aug 11 05:17:06 PM PDT 24
Peak memory 195672 kb
Host smart-474caa3c-37af-482c-9e49-5a7033020ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365902512 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3365902512
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.585628324
Short name T418
Test name
Test status
Simulation time 507670395 ps
CPU time 1.38 seconds
Started Aug 11 05:16:53 PM PDT 24
Finished Aug 11 05:16:55 PM PDT 24
Peak memory 192904 kb
Host smart-d2ea9e85-b622-418a-8690-8656b660c6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585628324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.585628324
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3858298483
Short name T372
Test name
Test status
Simulation time 265194011 ps
CPU time 0.95 seconds
Started Aug 11 05:16:56 PM PDT 24
Finished Aug 11 05:16:57 PM PDT 24
Peak memory 192816 kb
Host smart-87b7b5e6-937e-490b-9e41-fd7290de1a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858298483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3858298483
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.188387282
Short name T91
Test name
Test status
Simulation time 1517175855 ps
CPU time 1.02 seconds
Started Aug 11 05:16:56 PM PDT 24
Finished Aug 11 05:16:57 PM PDT 24
Peak memory 193940 kb
Host smart-7bd61fd8-a2ea-46d0-a960-8de830913d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188387282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.188387282
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2025837586
Short name T393
Test name
Test status
Simulation time 603151580 ps
CPU time 2.06 seconds
Started Aug 11 05:16:54 PM PDT 24
Finished Aug 11 05:16:56 PM PDT 24
Peak memory 198536 kb
Host smart-ecd0f700-669c-499a-a5f8-8541cc93badf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025837586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2025837586
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1741390277
Short name T416
Test name
Test status
Simulation time 8243137108 ps
CPU time 14.23 seconds
Started Aug 11 05:16:55 PM PDT 24
Finished Aug 11 05:17:09 PM PDT 24
Peak memory 198164 kb
Host smart-daab2e71-313d-492a-8305-af8873c7404e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741390277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1741390277
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1577358986
Short name T37
Test name
Test status
Simulation time 339720373 ps
CPU time 1.19 seconds
Started Aug 11 05:17:04 PM PDT 24
Finished Aug 11 05:17:06 PM PDT 24
Peak memory 196828 kb
Host smart-c72d02a3-fc06-4c33-8f27-ac071ca4b6df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577358986 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1577358986
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3947789221
Short name T85
Test name
Test status
Simulation time 453349411 ps
CPU time 0.79 seconds
Started Aug 11 05:17:02 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 193184 kb
Host smart-9111a0b2-817c-4976-a296-2a8bb6afe0f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947789221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3947789221
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3233453706
Short name T294
Test name
Test status
Simulation time 346956413 ps
CPU time 1.02 seconds
Started Aug 11 05:17:03 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 183724 kb
Host smart-9eccbdf1-804a-4ab6-841a-b9174c48705d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233453706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3233453706
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2019399748
Short name T388
Test name
Test status
Simulation time 1645360518 ps
CPU time 2.29 seconds
Started Aug 11 05:17:01 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 192928 kb
Host smart-dc887c05-3e2b-4ed0-960a-144f9b928174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019399748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2019399748
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3768677477
Short name T375
Test name
Test status
Simulation time 378466617 ps
CPU time 1.44 seconds
Started Aug 11 05:17:02 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 198500 kb
Host smart-8528fac5-3aa4-4c3a-bd5d-da744b4d93ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768677477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3768677477
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2701509320
Short name T413
Test name
Test status
Simulation time 9390860990 ps
CPU time 13.5 seconds
Started Aug 11 05:17:02 PM PDT 24
Finished Aug 11 05:17:16 PM PDT 24
Peak memory 198312 kb
Host smart-ee09fa86-0c45-4263-93a9-9f9600d219ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701509320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2701509320
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1456831306
Short name T308
Test name
Test status
Simulation time 547285050 ps
CPU time 1.46 seconds
Started Aug 11 05:17:02 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 197024 kb
Host smart-bb2ee600-8c71-45b6-b10c-4d7afe9ecb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456831306 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1456831306
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2477281547
Short name T72
Test name
Test status
Simulation time 340480914 ps
CPU time 0.83 seconds
Started Aug 11 05:17:00 PM PDT 24
Finished Aug 11 05:17:01 PM PDT 24
Peak memory 193924 kb
Host smart-3658338a-434a-4615-89d5-e95f6f98aa94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477281547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2477281547
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1654752569
Short name T386
Test name
Test status
Simulation time 474629870 ps
CPU time 1.29 seconds
Started Aug 11 05:17:04 PM PDT 24
Finished Aug 11 05:17:06 PM PDT 24
Peak memory 183696 kb
Host smart-9081d3e1-d3bb-4437-b0d9-0e0e58c82340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654752569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1654752569
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.736297894
Short name T88
Test name
Test status
Simulation time 1343005413 ps
CPU time 2.3 seconds
Started Aug 11 05:17:01 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 193456 kb
Host smart-867e95ac-af17-42ed-8b0d-661883ea5d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736297894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.736297894
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3265325499
Short name T401
Test name
Test status
Simulation time 440419039 ps
CPU time 1.13 seconds
Started Aug 11 05:17:03 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 198344 kb
Host smart-9f253a0a-2443-4df9-94aa-0c38a10a9a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265325499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3265325499
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2213013506
Short name T407
Test name
Test status
Simulation time 4608198462 ps
CPU time 6.95 seconds
Started Aug 11 05:17:01 PM PDT 24
Finished Aug 11 05:17:08 PM PDT 24
Peak memory 197980 kb
Host smart-f87b2881-dff6-4c03-ba6c-2af1a8b171d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213013506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2213013506
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2207066202
Short name T30
Test name
Test status
Simulation time 569179210 ps
CPU time 1.04 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:10 PM PDT 24
Peak memory 198160 kb
Host smart-ab7f96c0-b57e-4878-a533-c72867467cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207066202 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2207066202
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1105862515
Short name T58
Test name
Test status
Simulation time 350366790 ps
CPU time 1.02 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:09 PM PDT 24
Peak memory 191952 kb
Host smart-69c518cf-320a-4899-981e-654e9fa71c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105862515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1105862515
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1152245338
Short name T421
Test name
Test status
Simulation time 358768720 ps
CPU time 0.8 seconds
Started Aug 11 05:17:03 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 183716 kb
Host smart-820bf0d4-c64e-483d-b3e1-08c3318a26e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152245338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1152245338
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.312840499
Short name T404
Test name
Test status
Simulation time 1505086158 ps
CPU time 1.27 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:10 PM PDT 24
Peak memory 192940 kb
Host smart-144d50b3-29a9-4037-81c4-f47ca3b23fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312840499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.312840499
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2988478301
Short name T292
Test name
Test status
Simulation time 535034393 ps
CPU time 3.24 seconds
Started Aug 11 05:17:00 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 198560 kb
Host smart-537a4fa3-a3af-4b6d-87b8-0485be5bdb7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988478301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2988478301
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1820219370
Short name T400
Test name
Test status
Simulation time 4606761665 ps
CPU time 1.65 seconds
Started Aug 11 05:17:02 PM PDT 24
Finished Aug 11 05:17:03 PM PDT 24
Peak memory 196776 kb
Host smart-d668ea50-9a9c-488b-9ed6-58b4292c6080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820219370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1820219370
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2980456187
Short name T301
Test name
Test status
Simulation time 545241500 ps
CPU time 0.96 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:10 PM PDT 24
Peak memory 195828 kb
Host smart-9efb3edb-559a-4a70-a022-58743f654c17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980456187 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2980456187
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.664010447
Short name T286
Test name
Test status
Simulation time 511425096 ps
CPU time 0.75 seconds
Started Aug 11 05:17:07 PM PDT 24
Finished Aug 11 05:17:08 PM PDT 24
Peak memory 191892 kb
Host smart-f6216097-80a9-406e-8fd2-7e6815ffddd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664010447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.664010447
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1926724124
Short name T340
Test name
Test status
Simulation time 327030759 ps
CPU time 0.65 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:09 PM PDT 24
Peak memory 183776 kb
Host smart-a2f8f80d-ecf3-4dab-9f5b-cdc7b643050b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926724124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1926724124
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2097481717
Short name T353
Test name
Test status
Simulation time 3212788147 ps
CPU time 1.94 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:10 PM PDT 24
Peak memory 195536 kb
Host smart-d7dd6ae9-189e-41f1-9506-32311c7e4032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097481717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2097481717
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1476625340
Short name T336
Test name
Test status
Simulation time 546298202 ps
CPU time 2.54 seconds
Started Aug 11 05:17:06 PM PDT 24
Finished Aug 11 05:17:09 PM PDT 24
Peak memory 198524 kb
Host smart-bb076c35-4f57-4a80-a1f0-68b60d4517ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476625340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1476625340
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3973627672
Short name T385
Test name
Test status
Simulation time 8444767813 ps
CPU time 7.06 seconds
Started Aug 11 05:17:08 PM PDT 24
Finished Aug 11 05:17:15 PM PDT 24
Peak memory 198176 kb
Host smart-ec57d396-2517-4fdc-8956-acd3ddf34b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973627672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3973627672
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2038422185
Short name T259
Test name
Test status
Simulation time 28661746150 ps
CPU time 43.4 seconds
Started Aug 11 05:11:17 PM PDT 24
Finished Aug 11 05:12:00 PM PDT 24
Peak memory 197068 kb
Host smart-6b5faa8a-c68c-4aff-8d6d-ac403c0b2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038422185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2038422185
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2105527388
Short name T66
Test name
Test status
Simulation time 539511231 ps
CPU time 0.8 seconds
Started Aug 11 05:11:10 PM PDT 24
Finished Aug 11 05:11:11 PM PDT 24
Peak memory 192252 kb
Host smart-105567bb-25e8-4993-b2b3-17b7613bae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105527388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2105527388
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1923759815
Short name T155
Test name
Test status
Simulation time 488547844 ps
CPU time 1.35 seconds
Started Aug 11 05:11:22 PM PDT 24
Finished Aug 11 05:11:23 PM PDT 24
Peak memory 196796 kb
Host smart-d981d649-35ea-4251-8239-1cde918b6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923759815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1923759815
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3863758325
Short name T223
Test name
Test status
Simulation time 25271264562 ps
CPU time 9.74 seconds
Started Aug 11 05:11:21 PM PDT 24
Finished Aug 11 05:11:31 PM PDT 24
Peak memory 192040 kb
Host smart-940df9b9-fa76-4515-b27e-f658b9aa63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863758325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3863758325
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.192111732
Short name T14
Test name
Test status
Simulation time 7822450747 ps
CPU time 4.03 seconds
Started Aug 11 05:11:37 PM PDT 24
Finished Aug 11 05:11:41 PM PDT 24
Peak memory 215752 kb
Host smart-bbebd760-b876-46b7-9524-d8f4b467688b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192111732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.192111732
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3966798901
Short name T213
Test name
Test status
Simulation time 548427117 ps
CPU time 0.76 seconds
Started Aug 11 05:11:20 PM PDT 24
Finished Aug 11 05:11:21 PM PDT 24
Peak memory 196836 kb
Host smart-9c7db345-6fce-46fb-91d4-962446397779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966798901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3966798901
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2253056710
Short name T215
Test name
Test status
Simulation time 11863184695 ps
CPU time 14.1 seconds
Started Aug 11 05:12:30 PM PDT 24
Finished Aug 11 05:12:45 PM PDT 24
Peak memory 197088 kb
Host smart-4f952ed7-495c-44ac-b612-16f43b5a4605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253056710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2253056710
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.666347415
Short name T25
Test name
Test status
Simulation time 609796311 ps
CPU time 0.77 seconds
Started Aug 11 05:12:31 PM PDT 24
Finished Aug 11 05:12:32 PM PDT 24
Peak memory 192088 kb
Host smart-5561322e-a3d0-4f99-bdb9-5a9d3eeaabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666347415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.666347415
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.970922991
Short name T226
Test name
Test status
Simulation time 25633078681 ps
CPU time 2.94 seconds
Started Aug 11 05:12:36 PM PDT 24
Finished Aug 11 05:12:39 PM PDT 24
Peak memory 197144 kb
Host smart-867feff3-0737-42b0-9893-d8ff60c36808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970922991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.970922991
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.298409887
Short name T273
Test name
Test status
Simulation time 519682628 ps
CPU time 0.98 seconds
Started Aug 11 05:12:36 PM PDT 24
Finished Aug 11 05:12:37 PM PDT 24
Peak memory 191996 kb
Host smart-d40d66ba-67f7-412c-9740-c2ca9f8f51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298409887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.298409887
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.360245279
Short name T204
Test name
Test status
Simulation time 1005582283 ps
CPU time 2.09 seconds
Started Aug 11 05:12:43 PM PDT 24
Finished Aug 11 05:12:45 PM PDT 24
Peak memory 192044 kb
Host smart-813bae0f-1f8d-43ff-82dc-db43fc3a1b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360245279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.360245279
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2849230568
Short name T241
Test name
Test status
Simulation time 606589154 ps
CPU time 1.53 seconds
Started Aug 11 05:12:37 PM PDT 24
Finished Aug 11 05:12:39 PM PDT 24
Peak memory 196780 kb
Host smart-082659cf-2565-4fc2-91bf-9eb7bfbcafca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849230568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2849230568
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3214888109
Short name T206
Test name
Test status
Simulation time 38611880479 ps
CPU time 54.9 seconds
Started Aug 11 05:12:48 PM PDT 24
Finished Aug 11 05:13:43 PM PDT 24
Peak memory 192060 kb
Host smart-61340ee5-1dcf-42dd-8f2b-4ded8c89f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214888109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3214888109
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.154236332
Short name T267
Test name
Test status
Simulation time 367042871 ps
CPU time 0.68 seconds
Started Aug 11 05:12:51 PM PDT 24
Finished Aug 11 05:12:52 PM PDT 24
Peak memory 196788 kb
Host smart-a6b7329f-192a-44f6-bd8f-90c9650495dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154236332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.154236332
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2825489603
Short name T220
Test name
Test status
Simulation time 55210940786 ps
CPU time 28.77 seconds
Started Aug 11 05:12:55 PM PDT 24
Finished Aug 11 05:13:24 PM PDT 24
Peak memory 192060 kb
Host smart-1eb60cd3-fb75-477e-aa26-deba50a3d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825489603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2825489603
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3513182071
Short name T283
Test name
Test status
Simulation time 435952801 ps
CPU time 0.68 seconds
Started Aug 11 05:12:54 PM PDT 24
Finished Aug 11 05:12:55 PM PDT 24
Peak memory 191972 kb
Host smart-435b0fe4-fb16-42cc-9f38-fe165cfb63c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513182071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3513182071
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.514467456
Short name T205
Test name
Test status
Simulation time 5157344127 ps
CPU time 4.22 seconds
Started Aug 11 05:13:00 PM PDT 24
Finished Aug 11 05:13:04 PM PDT 24
Peak memory 191984 kb
Host smart-1f77c404-9019-46e9-b3b3-499a7bf3efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514467456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.514467456
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2948986167
Short name T277
Test name
Test status
Simulation time 468628961 ps
CPU time 0.79 seconds
Started Aug 11 05:13:01 PM PDT 24
Finished Aug 11 05:13:02 PM PDT 24
Peak memory 196848 kb
Host smart-28c083ef-1511-458a-838e-0fbcbae00b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948986167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2948986167
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1910171348
Short name T184
Test name
Test status
Simulation time 567054701 ps
CPU time 0.79 seconds
Started Aug 11 05:13:14 PM PDT 24
Finished Aug 11 05:13:15 PM PDT 24
Peak memory 196824 kb
Host smart-e9469501-91b7-4ee5-9998-3efb6d2037fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910171348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1910171348
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.770411732
Short name T230
Test name
Test status
Simulation time 28212796957 ps
CPU time 39.72 seconds
Started Aug 11 05:13:08 PM PDT 24
Finished Aug 11 05:13:48 PM PDT 24
Peak memory 192064 kb
Host smart-6c3adf64-4e62-4739-b42b-628a6f6204fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770411732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.770411732
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.521165265
Short name T227
Test name
Test status
Simulation time 482383835 ps
CPU time 0.77 seconds
Started Aug 11 05:13:08 PM PDT 24
Finished Aug 11 05:13:09 PM PDT 24
Peak memory 196832 kb
Host smart-1dc10244-a01c-4b8d-99ba-6732912dc82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521165265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.521165265
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3127813029
Short name T79
Test name
Test status
Simulation time 452205928 ps
CPU time 0.87 seconds
Started Aug 11 05:13:13 PM PDT 24
Finished Aug 11 05:13:14 PM PDT 24
Peak memory 196856 kb
Host smart-53340bf6-dd51-4575-a9af-9944fe4d8e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127813029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3127813029
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1187210387
Short name T251
Test name
Test status
Simulation time 16370591027 ps
CPU time 13.51 seconds
Started Aug 11 05:13:17 PM PDT 24
Finished Aug 11 05:13:31 PM PDT 24
Peak memory 197112 kb
Host smart-b2c6f586-f86c-4b4b-ad28-abd42485898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187210387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1187210387
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2699342065
Short name T239
Test name
Test status
Simulation time 517038881 ps
CPU time 0.8 seconds
Started Aug 11 05:13:16 PM PDT 24
Finished Aug 11 05:13:17 PM PDT 24
Peak memory 192040 kb
Host smart-290398b6-d7ff-4691-9d24-6543e556970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699342065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2699342065
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1547834875
Short name T122
Test name
Test status
Simulation time 416773692 ps
CPU time 0.75 seconds
Started Aug 11 05:13:21 PM PDT 24
Finished Aug 11 05:13:22 PM PDT 24
Peak memory 196896 kb
Host smart-0ecdfd3b-a6a8-4eca-87db-58f9bad344df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547834875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1547834875
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4232198210
Short name T107
Test name
Test status
Simulation time 9557322069 ps
CPU time 3.57 seconds
Started Aug 11 05:13:20 PM PDT 24
Finished Aug 11 05:13:24 PM PDT 24
Peak memory 191972 kb
Host smart-41aca0b8-3ad7-4460-a108-72eca37e4448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232198210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4232198210
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2532011777
Short name T282
Test name
Test status
Simulation time 556683856 ps
CPU time 0.77 seconds
Started Aug 11 05:13:22 PM PDT 24
Finished Aug 11 05:13:22 PM PDT 24
Peak memory 192036 kb
Host smart-9fd7de7b-b7f4-4778-a88e-a4988bc2cb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532011777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2532011777
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4250123806
Short name T173
Test name
Test status
Simulation time 469986667 ps
CPU time 1.32 seconds
Started Aug 11 05:13:27 PM PDT 24
Finished Aug 11 05:13:28 PM PDT 24
Peak memory 196796 kb
Host smart-25dba290-63ed-4daf-a6a4-c4d604567fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250123806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4250123806
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2442928970
Short name T274
Test name
Test status
Simulation time 1967742908 ps
CPU time 3.55 seconds
Started Aug 11 05:13:26 PM PDT 24
Finished Aug 11 05:13:30 PM PDT 24
Peak memory 191984 kb
Host smart-7670dae0-501a-4872-b16e-6eb23163fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442928970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2442928970
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3991709475
Short name T221
Test name
Test status
Simulation time 580358383 ps
CPU time 0.73 seconds
Started Aug 11 05:13:19 PM PDT 24
Finished Aug 11 05:13:20 PM PDT 24
Peak memory 191940 kb
Host smart-df592332-4734-4306-ba96-e887c4a7a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991709475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3991709475
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2756783899
Short name T235
Test name
Test status
Simulation time 20986044245 ps
CPU time 15.41 seconds
Started Aug 11 05:11:35 PM PDT 24
Finished Aug 11 05:11:50 PM PDT 24
Peak memory 197112 kb
Host smart-3ad2462a-e05e-42d6-ad32-44615bcac095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756783899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2756783899
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3323253694
Short name T18
Test name
Test status
Simulation time 4092832334 ps
CPU time 6.72 seconds
Started Aug 11 05:11:43 PM PDT 24
Finished Aug 11 05:11:50 PM PDT 24
Peak memory 215284 kb
Host smart-812320a1-cfa4-42c0-aee5-98221ec73d15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323253694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3323253694
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3887754798
Short name T271
Test name
Test status
Simulation time 404341062 ps
CPU time 1.13 seconds
Started Aug 11 05:11:36 PM PDT 24
Finished Aug 11 05:11:37 PM PDT 24
Peak memory 191984 kb
Host smart-161babe7-08f4-429c-98b5-b741847af224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887754798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3887754798
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3355656440
Short name T252
Test name
Test status
Simulation time 19859051866 ps
CPU time 18.25 seconds
Started Aug 11 05:13:37 PM PDT 24
Finished Aug 11 05:13:55 PM PDT 24
Peak memory 192072 kb
Host smart-80a39058-696d-4b54-b985-05712c87f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355656440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3355656440
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1749234621
Short name T244
Test name
Test status
Simulation time 423587260 ps
CPU time 1.16 seconds
Started Aug 11 05:13:32 PM PDT 24
Finished Aug 11 05:13:34 PM PDT 24
Peak memory 192088 kb
Host smart-fc2c5d1e-84e7-44ea-8c50-3af8c94a762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749234621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1749234621
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3204696799
Short name T84
Test name
Test status
Simulation time 308668440295 ps
CPU time 211.43 seconds
Started Aug 11 05:13:37 PM PDT 24
Finished Aug 11 05:17:09 PM PDT 24
Peak memory 198392 kb
Host smart-d51e4321-33c4-45c5-88e1-fae509aaaa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204696799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3204696799
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2563819111
Short name T253
Test name
Test status
Simulation time 9578739402 ps
CPU time 3.97 seconds
Started Aug 11 05:13:38 PM PDT 24
Finished Aug 11 05:13:42 PM PDT 24
Peak memory 192060 kb
Host smart-b40b015d-3b3e-4ea4-bb9a-e54559c72468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563819111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2563819111
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.454128134
Short name T211
Test name
Test status
Simulation time 478834638 ps
CPU time 0.74 seconds
Started Aug 11 05:13:36 PM PDT 24
Finished Aug 11 05:13:37 PM PDT 24
Peak memory 192028 kb
Host smart-1e0b6bcb-adc1-4abe-8a42-16c5150ab1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454128134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.454128134
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1103519256
Short name T246
Test name
Test status
Simulation time 60331228517 ps
CPU time 16.35 seconds
Started Aug 11 05:13:48 PM PDT 24
Finished Aug 11 05:14:05 PM PDT 24
Peak memory 197160 kb
Host smart-94387368-d561-49f5-85ff-ef37a8771f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103519256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1103519256
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3141485830
Short name T238
Test name
Test status
Simulation time 387239416 ps
CPU time 0.64 seconds
Started Aug 11 05:13:51 PM PDT 24
Finished Aug 11 05:13:52 PM PDT 24
Peak memory 192004 kb
Host smart-ef10cf19-006e-466a-b2fc-1b3ed5f93685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141485830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3141485830
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2860789356
Short name T245
Test name
Test status
Simulation time 4311617270 ps
CPU time 7.47 seconds
Started Aug 11 05:13:56 PM PDT 24
Finished Aug 11 05:14:04 PM PDT 24
Peak memory 192036 kb
Host smart-3c432f27-c9ba-42ae-aca9-ec845a86642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860789356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2860789356
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1629784691
Short name T224
Test name
Test status
Simulation time 435737533 ps
CPU time 1.17 seconds
Started Aug 11 05:13:56 PM PDT 24
Finished Aug 11 05:13:58 PM PDT 24
Peak memory 191940 kb
Host smart-a8783bd2-51e1-443a-8a34-cf395e5f9420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629784691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1629784691
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3156267355
Short name T264
Test name
Test status
Simulation time 359997446171 ps
CPU time 560.49 seconds
Started Aug 11 05:13:55 PM PDT 24
Finished Aug 11 05:23:16 PM PDT 24
Peak memory 183832 kb
Host smart-5d57414a-57ea-4508-9d1e-8086ef051d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156267355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3156267355
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2071929183
Short name T234
Test name
Test status
Simulation time 49864796649 ps
CPU time 74.08 seconds
Started Aug 11 05:14:02 PM PDT 24
Finished Aug 11 05:15:17 PM PDT 24
Peak memory 192064 kb
Host smart-e53949d4-ad07-40ab-b0e3-dc9fdd3e39a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071929183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2071929183
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1886940186
Short name T240
Test name
Test status
Simulation time 545357399 ps
CPU time 1.29 seconds
Started Aug 11 05:14:03 PM PDT 24
Finished Aug 11 05:14:04 PM PDT 24
Peak memory 196860 kb
Host smart-238ae5ff-ad54-4989-a3e5-95ee7e2308c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886940186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1886940186
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.453399866
Short name T262
Test name
Test status
Simulation time 36737070517 ps
CPU time 52.94 seconds
Started Aug 11 05:14:10 PM PDT 24
Finished Aug 11 05:15:03 PM PDT 24
Peak memory 192152 kb
Host smart-259d2b6d-3564-430d-b5d1-8f328b5bdb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453399866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.453399866
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2977310554
Short name T266
Test name
Test status
Simulation time 631196208 ps
CPU time 0.68 seconds
Started Aug 11 05:14:03 PM PDT 24
Finished Aug 11 05:14:03 PM PDT 24
Peak memory 191936 kb
Host smart-0d2b0192-8482-4032-be79-f9612b31dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977310554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2977310554
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.329474663
Short name T69
Test name
Test status
Simulation time 38237146355 ps
CPU time 36.86 seconds
Started Aug 11 05:14:10 PM PDT 24
Finished Aug 11 05:14:47 PM PDT 24
Peak memory 192060 kb
Host smart-792baa2c-52b6-47fe-a2e0-45e9b1d7c56c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329474663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.329474663
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2296148467
Short name T249
Test name
Test status
Simulation time 46080523078 ps
CPU time 69.01 seconds
Started Aug 11 05:14:16 PM PDT 24
Finished Aug 11 05:15:25 PM PDT 24
Peak memory 192044 kb
Host smart-0dbc42e2-55bb-4aa1-81d6-256fb6b13e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296148467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2296148467
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2141059448
Short name T219
Test name
Test status
Simulation time 422038817 ps
CPU time 0.75 seconds
Started Aug 11 05:14:17 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 191976 kb
Host smart-8b3f92a8-91c2-4146-bbd1-b8b1db8aa36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141059448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2141059448
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2941341253
Short name T242
Test name
Test status
Simulation time 14603306569 ps
CPU time 7.4 seconds
Started Aug 11 05:14:18 PM PDT 24
Finished Aug 11 05:14:25 PM PDT 24
Peak memory 192072 kb
Host smart-27a3e48a-f652-4f64-91d4-16f7d8c0a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941341253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2941341253
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1832649147
Short name T208
Test name
Test status
Simulation time 427554218 ps
CPU time 1.14 seconds
Started Aug 11 05:14:17 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 192036 kb
Host smart-34b9219a-aa1e-40ce-864b-1de15c344789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832649147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1832649147
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1081590953
Short name T63
Test name
Test status
Simulation time 42459879472 ps
CPU time 34.17 seconds
Started Aug 11 05:14:24 PM PDT 24
Finished Aug 11 05:14:59 PM PDT 24
Peak memory 192048 kb
Host smart-6f58bebc-ff39-48a5-8388-01d35786822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081590953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1081590953
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2057932620
Short name T22
Test name
Test status
Simulation time 584616282 ps
CPU time 1.47 seconds
Started Aug 11 05:14:25 PM PDT 24
Finished Aug 11 05:14:27 PM PDT 24
Peak memory 192064 kb
Host smart-3d62081d-79a8-48e3-9c48-d5c573b45218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057932620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2057932620
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.434352648
Short name T228
Test name
Test status
Simulation time 6491574706 ps
CPU time 5.55 seconds
Started Aug 11 05:14:32 PM PDT 24
Finished Aug 11 05:14:37 PM PDT 24
Peak memory 192068 kb
Host smart-3a22eb31-9695-4d14-a358-e236eca2767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434352648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.434352648
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3408464730
Short name T237
Test name
Test status
Simulation time 397620398 ps
CPU time 1.23 seconds
Started Aug 11 05:14:30 PM PDT 24
Finished Aug 11 05:14:32 PM PDT 24
Peak memory 192000 kb
Host smart-d779a8a2-8c35-4759-ac96-59b5433b7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408464730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3408464730
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2311943265
Short name T279
Test name
Test status
Simulation time 26157416635 ps
CPU time 38.87 seconds
Started Aug 11 05:11:42 PM PDT 24
Finished Aug 11 05:12:21 PM PDT 24
Peak memory 192012 kb
Host smart-dad39ff6-a6b2-48c6-8b60-9059744f0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311943265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2311943265
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3854833652
Short name T16
Test name
Test status
Simulation time 8032318699 ps
CPU time 3.41 seconds
Started Aug 11 05:11:46 PM PDT 24
Finished Aug 11 05:11:50 PM PDT 24
Peak memory 215788 kb
Host smart-becbc705-47ce-411c-9fae-09d5183689c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854833652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3854833652
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.103363224
Short name T261
Test name
Test status
Simulation time 612342908 ps
CPU time 0.81 seconds
Started Aug 11 05:11:42 PM PDT 24
Finished Aug 11 05:11:43 PM PDT 24
Peak memory 191960 kb
Host smart-3718a751-02ce-44af-960f-79774a85c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103363224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.103363224
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.844293059
Short name T6
Test name
Test status
Simulation time 53121893728 ps
CPU time 75.5 seconds
Started Aug 11 05:14:38 PM PDT 24
Finished Aug 11 05:15:54 PM PDT 24
Peak memory 192064 kb
Host smart-76bfc802-cfcc-41e0-9e3f-ad835ae3de80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844293059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.844293059
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1202751370
Short name T278
Test name
Test status
Simulation time 614601593 ps
CPU time 0.63 seconds
Started Aug 11 05:14:38 PM PDT 24
Finished Aug 11 05:14:39 PM PDT 24
Peak memory 196816 kb
Host smart-e9859803-916b-4bdd-8ffd-f7212fc92100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202751370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1202751370
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3658262100
Short name T218
Test name
Test status
Simulation time 22951733778 ps
CPU time 8.44 seconds
Started Aug 11 05:14:36 PM PDT 24
Finished Aug 11 05:14:45 PM PDT 24
Peak memory 192068 kb
Host smart-ae5734c5-71c6-4347-ae7a-659fa6d4af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658262100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3658262100
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4177459974
Short name T214
Test name
Test status
Simulation time 363329120 ps
CPU time 1.12 seconds
Started Aug 11 05:14:39 PM PDT 24
Finished Aug 11 05:14:40 PM PDT 24
Peak memory 196844 kb
Host smart-4edb0c1b-b8d8-4d28-af30-923e638ebe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177459974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4177459974
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.172881480
Short name T258
Test name
Test status
Simulation time 52560465679 ps
CPU time 67.41 seconds
Started Aug 11 05:14:42 PM PDT 24
Finished Aug 11 05:15:49 PM PDT 24
Peak memory 192036 kb
Host smart-8cb51d08-8edd-4fdf-8693-e79e887c8c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172881480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.172881480
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3390743826
Short name T280
Test name
Test status
Simulation time 466092040 ps
CPU time 0.76 seconds
Started Aug 11 05:14:41 PM PDT 24
Finished Aug 11 05:14:42 PM PDT 24
Peak memory 191940 kb
Host smart-49c34841-d2c7-4779-a802-88d78490a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390743826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3390743826
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1115805882
Short name T260
Test name
Test status
Simulation time 9075398408 ps
CPU time 12.88 seconds
Started Aug 11 05:14:50 PM PDT 24
Finished Aug 11 05:15:03 PM PDT 24
Peak memory 197116 kb
Host smart-9e30aa9e-4623-44ca-9307-56bc2d6ee658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115805882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1115805882
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2093504972
Short name T20
Test name
Test status
Simulation time 535305076 ps
CPU time 0.68 seconds
Started Aug 11 05:14:48 PM PDT 24
Finished Aug 11 05:14:49 PM PDT 24
Peak memory 192020 kb
Host smart-0f7504fb-d359-44c0-abbb-ebf97fc2e4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093504972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2093504972
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3970375020
Short name T210
Test name
Test status
Simulation time 9570294839 ps
CPU time 12.93 seconds
Started Aug 11 05:14:50 PM PDT 24
Finished Aug 11 05:15:03 PM PDT 24
Peak memory 192012 kb
Host smart-a43d18db-5af7-4320-9c85-bcc0b9713bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970375020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3970375020
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.765050291
Short name T243
Test name
Test status
Simulation time 511358531 ps
CPU time 0.73 seconds
Started Aug 11 05:14:50 PM PDT 24
Finished Aug 11 05:14:51 PM PDT 24
Peak memory 196836 kb
Host smart-b0aee14a-1e9b-46a3-b5e6-588715adc8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765050291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.765050291
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3998137884
Short name T212
Test name
Test status
Simulation time 35782504362 ps
CPU time 8.08 seconds
Started Aug 11 05:14:56 PM PDT 24
Finished Aug 11 05:15:04 PM PDT 24
Peak memory 192104 kb
Host smart-3fb7ff0f-c1e6-459e-b97e-fd4e0e37f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998137884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3998137884
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2571064988
Short name T236
Test name
Test status
Simulation time 425966733 ps
CPU time 0.87 seconds
Started Aug 11 05:14:55 PM PDT 24
Finished Aug 11 05:14:56 PM PDT 24
Peak memory 191976 kb
Host smart-622d1af9-02af-4b15-aeda-0e26afb607dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571064988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2571064988
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2130886662
Short name T255
Test name
Test status
Simulation time 12814235020 ps
CPU time 16.16 seconds
Started Aug 11 05:15:03 PM PDT 24
Finished Aug 11 05:15:19 PM PDT 24
Peak memory 192072 kb
Host smart-73d2c2a2-e94c-49ce-a8c4-d5392887ce9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130886662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2130886662
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.325814524
Short name T104
Test name
Test status
Simulation time 474676703 ps
CPU time 0.75 seconds
Started Aug 11 05:15:04 PM PDT 24
Finished Aug 11 05:15:05 PM PDT 24
Peak memory 196856 kb
Host smart-2763fdf3-9dd1-4f07-b707-be1972644392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325814524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.325814524
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3518669538
Short name T47
Test name
Test status
Simulation time 29996865343 ps
CPU time 11.38 seconds
Started Aug 11 05:15:11 PM PDT 24
Finished Aug 11 05:15:22 PM PDT 24
Peak memory 192060 kb
Host smart-f883e7d0-f9b5-4f41-a32b-bb2ef92320b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518669538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3518669538
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3997197189
Short name T247
Test name
Test status
Simulation time 376155606 ps
CPU time 0.97 seconds
Started Aug 11 05:15:10 PM PDT 24
Finished Aug 11 05:15:11 PM PDT 24
Peak memory 192012 kb
Host smart-2dc20b70-e5b3-4d64-aace-6eefc721ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997197189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3997197189
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1699156673
Short name T101
Test name
Test status
Simulation time 69692320351 ps
CPU time 44.66 seconds
Started Aug 11 05:15:11 PM PDT 24
Finished Aug 11 05:15:55 PM PDT 24
Peak memory 206748 kb
Host smart-9e4dbee6-847c-4cc6-9746-2c2c5470c577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699156673 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1699156673
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.462924432
Short name T44
Test name
Test status
Simulation time 39888870807 ps
CPU time 12.82 seconds
Started Aug 11 05:15:12 PM PDT 24
Finished Aug 11 05:15:25 PM PDT 24
Peak memory 192048 kb
Host smart-4489f55f-fd54-433c-bcbc-c31a4b551e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462924432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.462924432
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.935526935
Short name T5
Test name
Test status
Simulation time 348192044 ps
CPU time 1.04 seconds
Started Aug 11 05:15:10 PM PDT 24
Finished Aug 11 05:15:12 PM PDT 24
Peak memory 191948 kb
Host smart-5da15229-5e4a-47ca-9f6b-512984e1184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935526935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.935526935
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2497960501
Short name T181
Test name
Test status
Simulation time 587674311 ps
CPU time 1.04 seconds
Started Aug 11 05:15:17 PM PDT 24
Finished Aug 11 05:15:18 PM PDT 24
Peak memory 196796 kb
Host smart-fb0409a1-2202-4e3e-a827-670cd560700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497960501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2497960501
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3236962680
Short name T231
Test name
Test status
Simulation time 1122516304 ps
CPU time 1.96 seconds
Started Aug 11 05:15:15 PM PDT 24
Finished Aug 11 05:15:17 PM PDT 24
Peak memory 196816 kb
Host smart-a9aa471b-40e5-4a08-8855-b724b8e5590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236962680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3236962680
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4269239263
Short name T263
Test name
Test status
Simulation time 534401768 ps
CPU time 1.33 seconds
Started Aug 11 05:15:15 PM PDT 24
Finished Aug 11 05:15:17 PM PDT 24
Peak memory 196928 kb
Host smart-62132192-26fc-44d4-a5ce-d9bade82b54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269239263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4269239263
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3891305092
Short name T46
Test name
Test status
Simulation time 13925412211 ps
CPU time 4.58 seconds
Started Aug 11 05:11:47 PM PDT 24
Finished Aug 11 05:11:52 PM PDT 24
Peak memory 197076 kb
Host smart-ab8868eb-837b-4f80-a72e-07936ba48b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891305092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3891305092
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3467547847
Short name T15
Test name
Test status
Simulation time 4147612405 ps
CPU time 6.63 seconds
Started Aug 11 05:11:52 PM PDT 24
Finished Aug 11 05:11:59 PM PDT 24
Peak memory 215440 kb
Host smart-996e7a21-d80f-485a-8b15-ffe70da69226
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467547847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3467547847
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2354494011
Short name T233
Test name
Test status
Simulation time 551083953 ps
CPU time 1.36 seconds
Started Aug 11 05:11:47 PM PDT 24
Finished Aug 11 05:11:48 PM PDT 24
Peak memory 196756 kb
Host smart-bdc15da8-ffbb-4aa0-802c-65a8e7a4032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354494011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2354494011
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2899829315
Short name T108
Test name
Test status
Simulation time 17592715101 ps
CPU time 7.25 seconds
Started Aug 11 05:15:24 PM PDT 24
Finished Aug 11 05:15:32 PM PDT 24
Peak memory 197024 kb
Host smart-0032b166-cdf4-4cef-90da-fd0cdb8f9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899829315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2899829315
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3653616511
Short name T106
Test name
Test status
Simulation time 589794688 ps
CPU time 1.43 seconds
Started Aug 11 05:15:23 PM PDT 24
Finished Aug 11 05:15:25 PM PDT 24
Peak memory 196780 kb
Host smart-d108565c-9234-4b22-80c4-8fa3f6c44f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653616511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3653616511
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1310996015
Short name T194
Test name
Test status
Simulation time 590462492 ps
CPU time 0.78 seconds
Started Aug 11 05:15:28 PM PDT 24
Finished Aug 11 05:15:29 PM PDT 24
Peak memory 196800 kb
Host smart-becad43a-88a5-4ae6-89ed-97130b2f5a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310996015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1310996015
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1576127211
Short name T216
Test name
Test status
Simulation time 3220180065 ps
CPU time 1.36 seconds
Started Aug 11 05:15:30 PM PDT 24
Finished Aug 11 05:15:31 PM PDT 24
Peak memory 192044 kb
Host smart-12b9ceae-6d7a-4f50-b580-16274bc0f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576127211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1576127211
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.129204940
Short name T275
Test name
Test status
Simulation time 593786536 ps
CPU time 1.46 seconds
Started Aug 11 05:15:30 PM PDT 24
Finished Aug 11 05:15:32 PM PDT 24
Peak memory 196792 kb
Host smart-d4c44502-d8b8-441e-8d9d-e232d5ffc0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129204940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.129204940
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2190406551
Short name T110
Test name
Test status
Simulation time 26328857682 ps
CPU time 42.23 seconds
Started Aug 11 05:15:34 PM PDT 24
Finished Aug 11 05:16:17 PM PDT 24
Peak memory 196988 kb
Host smart-2b6caf41-5528-422d-a45f-5aa12a537e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190406551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2190406551
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2214885384
Short name T268
Test name
Test status
Simulation time 454498590 ps
CPU time 1.19 seconds
Started Aug 11 05:15:42 PM PDT 24
Finished Aug 11 05:15:44 PM PDT 24
Peak memory 192012 kb
Host smart-bfcc19eb-5ef1-4049-834a-e2f98408310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214885384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2214885384
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3004252381
Short name T10
Test name
Test status
Simulation time 31215043175 ps
CPU time 12.56 seconds
Started Aug 11 05:15:34 PM PDT 24
Finished Aug 11 05:15:46 PM PDT 24
Peak memory 192148 kb
Host smart-76a82a7f-dabd-41bf-919c-b78b9e6e8d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004252381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3004252381
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2879873152
Short name T209
Test name
Test status
Simulation time 530082279 ps
CPU time 0.78 seconds
Started Aug 11 05:15:34 PM PDT 24
Finished Aug 11 05:15:35 PM PDT 24
Peak memory 191980 kb
Host smart-6db7efc5-b94f-4afb-9d3f-c50eb27e7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879873152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2879873152
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1883634614
Short name T248
Test name
Test status
Simulation time 19625718350 ps
CPU time 7.08 seconds
Started Aug 11 05:15:42 PM PDT 24
Finished Aug 11 05:15:50 PM PDT 24
Peak memory 192056 kb
Host smart-4a988fb1-3201-4801-a1d3-28f3432f2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883634614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1883634614
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.630355806
Short name T222
Test name
Test status
Simulation time 527115970 ps
CPU time 0.82 seconds
Started Aug 11 05:15:43 PM PDT 24
Finished Aug 11 05:15:44 PM PDT 24
Peak memory 192008 kb
Host smart-9571d141-f5bf-4c78-bb82-00750b13265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630355806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.630355806
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1588200307
Short name T229
Test name
Test status
Simulation time 45673318979 ps
CPU time 15.9 seconds
Started Aug 11 05:15:47 PM PDT 24
Finished Aug 11 05:16:03 PM PDT 24
Peak memory 192156 kb
Host smart-0535fa02-a260-4f27-9750-6333bcb475da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588200307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1588200307
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3675820040
Short name T217
Test name
Test status
Simulation time 417722615 ps
CPU time 0.71 seconds
Started Aug 11 05:15:47 PM PDT 24
Finished Aug 11 05:15:47 PM PDT 24
Peak memory 192012 kb
Host smart-f193f152-4a01-4210-aa30-1f089eb73b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675820040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3675820040
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2862619519
Short name T196
Test name
Test status
Simulation time 356715253 ps
CPU time 0.7 seconds
Started Aug 11 05:15:53 PM PDT 24
Finished Aug 11 05:15:54 PM PDT 24
Peak memory 196788 kb
Host smart-01ff1ad6-8732-4278-8511-4561a954558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862619519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2862619519
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2812902619
Short name T82
Test name
Test status
Simulation time 56076952513 ps
CPU time 18.89 seconds
Started Aug 11 05:15:53 PM PDT 24
Finished Aug 11 05:16:12 PM PDT 24
Peak memory 192100 kb
Host smart-dbd3401a-b88e-4908-8a7a-daacb4f7aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812902619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2812902619
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1054098696
Short name T269
Test name
Test status
Simulation time 395367231 ps
CPU time 1.17 seconds
Started Aug 11 05:15:53 PM PDT 24
Finished Aug 11 05:15:55 PM PDT 24
Peak memory 196856 kb
Host smart-f524bd99-c5ec-407c-b3dc-7033c121e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054098696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1054098696
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3884562556
Short name T83
Test name
Test status
Simulation time 37646097007 ps
CPU time 4.85 seconds
Started Aug 11 05:16:00 PM PDT 24
Finished Aug 11 05:16:05 PM PDT 24
Peak memory 192072 kb
Host smart-40e21df9-803f-4ff9-8eec-84b7296491cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884562556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3884562556
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3523631422
Short name T9
Test name
Test status
Simulation time 616263310 ps
CPU time 0.83 seconds
Started Aug 11 05:15:54 PM PDT 24
Finished Aug 11 05:15:55 PM PDT 24
Peak memory 191996 kb
Host smart-7fa7ce15-c200-4d4f-99f4-e516086e06f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523631422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3523631422
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3456377283
Short name T179
Test name
Test status
Simulation time 372325033 ps
CPU time 1.12 seconds
Started Aug 11 05:15:58 PM PDT 24
Finished Aug 11 05:16:00 PM PDT 24
Peak memory 196824 kb
Host smart-6825df62-4751-482a-8ebb-20d69361fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456377283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3456377283
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1734743657
Short name T256
Test name
Test status
Simulation time 23788756730 ps
CPU time 22.94 seconds
Started Aug 11 05:16:00 PM PDT 24
Finished Aug 11 05:16:23 PM PDT 24
Peak memory 197016 kb
Host smart-6abfa4a5-6d44-4cb2-b1a5-3b37c9cd1d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734743657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1734743657
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1000334467
Short name T276
Test name
Test status
Simulation time 384731114 ps
CPU time 0.71 seconds
Started Aug 11 05:16:00 PM PDT 24
Finished Aug 11 05:16:01 PM PDT 24
Peak memory 191984 kb
Host smart-1f5e6fab-20fb-4f78-add1-8af0b78d67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000334467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1000334467
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3144585715
Short name T225
Test name
Test status
Simulation time 49685856442 ps
CPU time 10.33 seconds
Started Aug 11 05:16:03 PM PDT 24
Finished Aug 11 05:16:13 PM PDT 24
Peak memory 192112 kb
Host smart-7b54cbc8-beb5-49f2-bc2f-20d0b7a1a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144585715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3144585715
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2852044148
Short name T23
Test name
Test status
Simulation time 406146560 ps
CPU time 1.12 seconds
Started Aug 11 05:16:07 PM PDT 24
Finished Aug 11 05:16:09 PM PDT 24
Peak memory 191996 kb
Host smart-0d2bab93-5eec-41b6-b3b9-f470eef08f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852044148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2852044148
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2003967691
Short name T177
Test name
Test status
Simulation time 545995463 ps
CPU time 1.06 seconds
Started Aug 11 05:12:02 PM PDT 24
Finished Aug 11 05:12:03 PM PDT 24
Peak memory 196872 kb
Host smart-5f753693-40d3-458c-bae1-13f5d8265fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003967691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2003967691
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2084712518
Short name T265
Test name
Test status
Simulation time 20387158615 ps
CPU time 15.24 seconds
Started Aug 11 05:12:04 PM PDT 24
Finished Aug 11 05:12:19 PM PDT 24
Peak memory 192056 kb
Host smart-3494a2fd-f142-43e3-8fa6-154708dce3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084712518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2084712518
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.4155570172
Short name T270
Test name
Test status
Simulation time 506883902 ps
CPU time 0.68 seconds
Started Aug 11 05:11:53 PM PDT 24
Finished Aug 11 05:11:54 PM PDT 24
Peak memory 196792 kb
Host smart-5dc0f764-50b2-445f-9eb1-629462bde375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155570172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4155570172
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1375494586
Short name T111
Test name
Test status
Simulation time 36917993781 ps
CPU time 29.14 seconds
Started Aug 11 05:12:12 PM PDT 24
Finished Aug 11 05:12:41 PM PDT 24
Peak memory 197364 kb
Host smart-10e70972-1a5e-4d6e-82a0-41adeeb14a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375494586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1375494586
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.807779028
Short name T109
Test name
Test status
Simulation time 416321455 ps
CPU time 1.18 seconds
Started Aug 11 05:12:12 PM PDT 24
Finished Aug 11 05:12:13 PM PDT 24
Peak memory 191932 kb
Host smart-5dbfb04c-310a-49bd-9ae6-02e90a90e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807779028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.807779028
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2276312347
Short name T250
Test name
Test status
Simulation time 16413484562 ps
CPU time 14.96 seconds
Started Aug 11 05:12:18 PM PDT 24
Finished Aug 11 05:12:33 PM PDT 24
Peak memory 192036 kb
Host smart-321091bb-dd84-45b9-882b-72fbced61ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276312347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2276312347
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3247854367
Short name T281
Test name
Test status
Simulation time 563698002 ps
CPU time 1.39 seconds
Started Aug 11 05:12:23 PM PDT 24
Finished Aug 11 05:12:25 PM PDT 24
Peak memory 196856 kb
Host smart-b270ae6d-825e-4594-b103-15641c94b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247854367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3247854367
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.292607992
Short name T254
Test name
Test status
Simulation time 34362361749 ps
CPU time 50.13 seconds
Started Aug 11 05:12:25 PM PDT 24
Finished Aug 11 05:13:15 PM PDT 24
Peak memory 197016 kb
Host smart-1d6c6d6e-5f38-4ea2-afd6-c1e64c0cab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292607992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.292607992
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1962031253
Short name T272
Test name
Test status
Simulation time 473310687 ps
CPU time 0.71 seconds
Started Aug 11 05:12:20 PM PDT 24
Finished Aug 11 05:12:21 PM PDT 24
Peak memory 192008 kb
Host smart-8eb33943-00b0-4d0b-8eaf-87bee5cb3aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962031253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1962031253
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3903817008
Short name T257
Test name
Test status
Simulation time 12452425233 ps
CPU time 4.91 seconds
Started Aug 11 05:12:27 PM PDT 24
Finished Aug 11 05:12:32 PM PDT 24
Peak memory 192104 kb
Host smart-86856435-ba08-4cd4-8c87-cb5ef9fc5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903817008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3903817008
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.4141668480
Short name T232
Test name
Test status
Simulation time 435900555 ps
CPU time 1.29 seconds
Started Aug 11 05:12:27 PM PDT 24
Finished Aug 11 05:12:28 PM PDT 24
Peak memory 192040 kb
Host smart-e42442dd-eef2-43fc-8d50-78164c1c7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141668480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.4141668480
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%