Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18412	1		T1	186		T2	11		T3	11
bark[1]	287	1		T1	57		T45	21		T19	5
bark[2]	294	1		T8	21		T40	7		T42	5
bark[3]	267	1		T11	7		T39	24		T178	14
bark[4]	928	1		T21	208		T125	291		T106	56
bark[5]	192	1		T12	42		T41	26		T65	14
bark[6]	580	1		T12	31		T39	47		T34	14
bark[7]	386	1		T7	7		T27	14		T151	146
bark[8]	431	1		T13	14		T31	44		T103	21
bark[9]	511	1		T12	21		T41	21		T117	66
bark[10]	312	1		T10	56		T31	52		T20	14
bark[11]	433	1		T10	26		T30	21		T39	64
bark[12]	442	1		T7	268		T87	21		T120	21
bark[13]	385	1		T31	14		T45	39		T19	5
bark[14]	221	1		T10	21		T138	58		T87	21
bark[15]	413	1		T29	14		T25	21		T42	21
bark[16]	631	1		T30	90		T103	21		T117	7
bark[17]	238	1		T30	30		T39	26		T26	14
bark[18]	194	1		T22	14		T125	30		T87	35
bark[19]	464	1		T117	93		T85	21		T94	21
bark[20]	286	1		T10	14		T172	21		T80	64
bark[21]	448	1		T32	14		T24	197		T97	21
bark[22]	823	1		T41	21		T125	103		T138	26
bark[23]	103	1		T12	54		T80	14		T176	14
bark[24]	493	1		T31	21		T105	14		T125	21
bark[25]	593	1		T41	204		T92	14		T106	143
bark[26]	168	1		T4	14		T12	21		T151	21
bark[27]	549	1		T8	31		T172	21		T151	21
bark[28]	676	1		T45	21		T186	30		T187	14
bark[29]	623	1		T30	21		T103	21		T25	21
bark[30]	110	1		T41	7		T152	14		T82	21
bark[31]	390	1		T8	21		T11	98		T45	21
bark_0	4634	1		T1	35		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	18512	1		T1	182		T2	10		T3	10
bite[1]	257	1		T8	21		T12	31		T107	4
bite[2]	237	1		T10	21		T92	13		T96	26
bite[3]	256	1		T39	26		T96	21		T100	61
bite[4]	454	1		T30	51		T80	63		T178	13
bite[5]	217	1		T7	6		T10	26		T34	13
bite[6]	541	1		T12	54		T103	21		T151	40
bite[7]	265	1		T30	38		T172	21		T105	13
bite[8]	465	1		T172	21		T24	6		T80	13
bite[9]	357	1		T12	21		T13	13		T82	34
bite[10]	293	1		T12	21		T117	21		T124	21
bite[11]	899	1		T24	196		T125	290		T173	13
bite[12]	396	1		T10	35		T161	72		T94	26
bite[13]	368	1		T10	21		T138	26		T106	142
bite[14]	337	1		T29	13		T41	21		T125	102
bite[15]	514	1		T11	97		T151	21		T41	27
bite[16]	462	1		T1	64		T7	260		T31	13
bite[17]	656	1		T41	42		T125	250		T97	21
bite[18]	226	1		T31	21		T25	21		T27	13
bite[19]	600	1		T4	13		T103	21		T41	211
bite[20]	346	1		T39	23		T151	146		T41	21
bite[21]	358	1		T31	44		T39	71		T26	13
bite[22]	229	1		T12	21		T85	21		T97	21
bite[23]	268	1		T31	52		T30	42		T42	42
bite[24]	180	1		T42	21		T117	21		T168	78
bite[25]	174	1		T8	52		T96	53		T68	4
bite[26]	737	1		T21	21		T25	21		T106	21
bite[27]	309	1		T12	21		T30	30		T45	60
bite[28]	327	1		T10	13		T32	13		T40	6
bite[29]	710	1		T11	6		T45	21		T19	4
bite[30]	415	1		T39	46		T151	21		T150	13
bite[31]	465	1		T45	21		T21	186		T106	4
bite_0	5087	1		T1	32		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32358	1		T1	233		T2	11		T3	18
auto[1]	3559	1		T1	45		T2	7		T5	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	789	1		T8	9		T40	23		T21	19
prescale[1]	462	1		T31	23		T42	2		T80	19
prescale[2]	565	1		T8	78		T31	19		T45	19
prescale[3]	400	1		T8	23		T103	42		T41	9
prescale[4]	345	1		T7	2		T172	19		T25	19
prescale[5]	322	1		T103	24		T24	2		T196	9
prescale[6]	284	1		T7	2		T10	19		T39	9
prescale[7]	315	1		T151	24		T80	2		T197	9
prescale[8]	429	1		T30	60		T19	2		T21	125
prescale[9]	607	1		T40	2		T41	2		T125	2
prescale[10]	631	1		T1	19		T172	51		T39	2
prescale[11]	585	1		T1	33		T151	40		T161	2
prescale[12]	270	1		T1	2		T8	19		T147	2
prescale[13]	219	1		T1	2		T7	2		T44	9
prescale[14]	245	1		T8	19		T198	2		T118	23
prescale[15]	552	1		T11	2		T39	2		T24	45
prescale[16]	595	1		T8	19		T40	2		T199	9
prescale[17]	431	1		T10	23		T172	28		T103	40
prescale[18]	279	1		T30	19		T106	76		T82	2
prescale[19]	284	1		T147	9		T107	19		T198	2
prescale[20]	473	1		T103	19		T41	24		T125	63
prescale[21]	818	1		T21	90		T41	226		T81	2
prescale[22]	236	1		T45	23		T103	23		T21	82
prescale[23]	264	1		T1	2		T10	19		T21	26
prescale[24]	357	1		T8	23		T45	19		T25	9
prescale[25]	364	1		T1	2		T125	2		T138	72
prescale[26]	222	1		T11	2		T125	21		T186	46
prescale[27]	455	1		T12	30		T39	2		T19	2
prescale[28]	401	1		T11	2		T31	37		T21	2
prescale[29]	392	1		T9	9		T12	37		T19	2
prescale[30]	462	1		T10	19		T41	230		T80	2
prescale[31]	471	1		T172	23		T21	53		T25	19
prescale_0	22393	1		T1	218		T2	18		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24224	1		T1	202		T2	9		T3	9
auto[1]	11693	1		T1	76		T2	9		T3	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	35917	1		T1	278		T2	18		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19914	1		T1	176		T2	13		T3	13
wkup[1]	147	1		T106	6		T118	21		T168	8
wkup[2]	289	1		T7	21		T11	21		T39	21
wkup[3]	161	1		T32	15		T21	21		T96	47
wkup[4]	120	1		T31	44		T125	31		T72	15
wkup[5]	234	1		T12	31		T30	21		T118	21
wkup[6]	221	1		T10	26		T40	30		T161	6
wkup[7]	244	1		T21	21		T107	26		T85	21
wkup[8]	202	1		T40	21		T125	42		T68	21
wkup[9]	217	1		T12	15		T22	15		T151	21
wkup[10]	178	1		T103	21		T21	21		T41	8
wkup[11]	192	1		T7	21		T41	8		T87	21
wkup[12]	57	1		T172	21		T153	21		T159	15
wkup[13]	120	1		T41	21		T104	21		T167	21
wkup[14]	223	1		T7	56		T117	42		T87	35
wkup[15]	161	1		T19	6		T161	21		T168	21
wkup[16]	174	1		T45	21		T125	21		T106	21
wkup[17]	289	1		T31	15		T103	21		T21	21
wkup[18]	213	1		T82	15		T64	21		T68	21
wkup[19]	361	1		T40	21		T26	15		T138	40
wkup[20]	258	1		T151	21		T80	21		T125	21
wkup[21]	250	1		T7	21		T20	15		T92	15
wkup[22]	156	1		T10	21		T27	15		T41	30
wkup[23]	210	1		T7	21		T21	21		T25	40
wkup[24]	157	1		T30	21		T41	26		T117	21
wkup[25]	254	1		T161	21		T107	21		T85	21
wkup[26]	190	1		T8	26		T30	21		T41	21
wkup[27]	361	1		T10	65		T31	21		T39	21
wkup[28]	162	1		T13	15		T147	21		T159	21
wkup[29]	247	1		T41	21		T125	26		T138	26
wkup[30]	159	1		T40	21		T107	21		T106	30
wkup[31]	98	1		T29	15		T84	26		T73	15
wkup[32]	176	1		T39	26		T40	8		T161	21
wkup[33]	63	1		T81	6		T153	21		T131	21
wkup[34]	287	1		T1	30		T30	30		T172	21
wkup[35]	202	1		T45	39		T40	8		T125	21
wkup[36]	167	1		T151	21		T41	21		T118	21
wkup[37]	178	1		T11	8		T45	21		T24	8
wkup[38]	209	1		T31	21		T107	24		T97	21
wkup[39]	182	1		T42	6		T178	15		T81	68
wkup[40]	138	1		T12	21		T138	21		T81	30
wkup[41]	219	1		T1	26		T21	21		T161	21
wkup[42]	153	1		T151	21		T107	21		T82	6
wkup[43]	195	1		T1	21		T4	15		T186	30
wkup[44]	288	1		T12	21		T45	21		T41	21
wkup[45]	188	1		T31	21		T24	21		T188	15
wkup[46]	320	1		T8	31		T12	21		T24	26
wkup[47]	251	1		T12	21		T147	21		T107	21
wkup[48]	114	1		T39	21		T103	21		T82	21
wkup[49]	307	1		T7	47		T103	21		T80	36
wkup[50]	182	1		T30	21		T41	26		T125	21
wkup[51]	141	1		T8	21		T106	21		T83	21
wkup[52]	200	1		T41	21		T125	15		T106	21
wkup[53]	146	1		T125	21		T81	21		T117	21
wkup[54]	239	1		T11	21		T21	15		T150	15
wkup[55]	86	1		T125	21		T97	21		T108	44
wkup[56]	236	1		T39	21		T81	21		T107	21
wkup[57]	131	1		T12	21		T30	15		T34	15
wkup[58]	197	1		T8	21		T10	15		T151	35
wkup[59]	166	1		T7	21		T125	21		T81	21
wkup[60]	177	1		T125	21		T161	21		T117	21
wkup[61]	130	1		T7	8		T39	21		T161	21
wkup[62]	213	1		T107	27		T96	21		T104	26
wkup[63]	245	1		T25	21		T125	21		T106	21
wkup_0	3572	1		T1	25		T2	5		T3	5