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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.69 99.33 93.67 100.00 98.40 99.51 47.25


Total test records in report: 426
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T115 /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1655893822 Aug 12 05:25:28 PM PDT 24 Aug 12 05:25:41 PM PDT 24 2636078845 ps
T285 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.479577990 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:31 PM PDT 24 334862748 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3761650280 Aug 12 04:25:44 PM PDT 24 Aug 12 04:25:46 PM PDT 24 351627372 ps
T35 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1360708283 Aug 12 04:26:03 PM PDT 24 Aug 12 04:26:10 PM PDT 24 8578563884 ps
T36 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.378236363 Aug 12 04:25:40 PM PDT 24 Aug 12 04:25:42 PM PDT 24 402424815 ps
T287 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1772011747 Aug 12 04:26:03 PM PDT 24 Aug 12 04:26:04 PM PDT 24 508539975 ps
T288 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1536352671 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:26 PM PDT 24 317300189 ps
T37 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2958416131 Aug 12 04:25:56 PM PDT 24 Aug 12 04:26:00 PM PDT 24 4235471955 ps
T74 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.790258490 Aug 12 04:26:12 PM PDT 24 Aug 12 04:26:13 PM PDT 24 442995432 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4091241121 Aug 12 04:23:14 PM PDT 24 Aug 12 04:23:15 PM PDT 24 328059904 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2476979789 Aug 12 04:22:31 PM PDT 24 Aug 12 04:22:32 PM PDT 24 478131285 ps
T290 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.455707678 Aug 12 04:26:48 PM PDT 24 Aug 12 04:26:49 PM PDT 24 375695795 ps
T291 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2995548613 Aug 12 04:26:10 PM PDT 24 Aug 12 04:26:11 PM PDT 24 427056616 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.688532751 Aug 12 04:23:39 PM PDT 24 Aug 12 04:23:39 PM PDT 24 551064563 ps
T38 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.401679463 Aug 12 04:21:57 PM PDT 24 Aug 12 04:22:04 PM PDT 24 8319182686 ps
T293 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2238330906 Aug 12 04:26:06 PM PDT 24 Aug 12 04:26:07 PM PDT 24 442359495 ps
T294 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2006120570 Aug 12 04:27:26 PM PDT 24 Aug 12 04:27:27 PM PDT 24 382414115 ps
T295 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4162170623 Aug 12 04:27:13 PM PDT 24 Aug 12 04:27:15 PM PDT 24 413103975 ps
T194 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2537837512 Aug 12 04:27:09 PM PDT 24 Aug 12 04:27:11 PM PDT 24 4377964470 ps
T296 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2840660958 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:34 PM PDT 24 502304194 ps
T191 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2563552430 Aug 12 04:21:48 PM PDT 24 Aug 12 04:21:56 PM PDT 24 7713338259 ps
T192 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.762415561 Aug 12 04:27:11 PM PDT 24 Aug 12 04:27:26 PM PDT 24 8295199043 ps
T297 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2862053818 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:30 PM PDT 24 505992918 ps
T298 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3315983405 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:34 PM PDT 24 4753845888 ps
T299 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.511973492 Aug 12 04:22:15 PM PDT 24 Aug 12 04:22:17 PM PDT 24 335855080 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1612229222 Aug 12 04:21:07 PM PDT 24 Aug 12 04:21:09 PM PDT 24 508484837 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1317250604 Aug 12 04:22:47 PM PDT 24 Aug 12 04:22:48 PM PDT 24 418860836 ps
T302 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.666781946 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:35 PM PDT 24 452105935 ps
T76 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1015665149 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:00 PM PDT 24 434242892 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3634583286 Aug 12 04:24:25 PM PDT 24 Aug 12 04:24:41 PM PDT 24 7333320516 ps
T304 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1071738726 Aug 12 04:25:47 PM PDT 24 Aug 12 04:25:48 PM PDT 24 392786356 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4193806293 Aug 12 04:26:17 PM PDT 24 Aug 12 04:26:20 PM PDT 24 414940648 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3011481864 Aug 12 04:26:19 PM PDT 24 Aug 12 04:26:20 PM PDT 24 552956690 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3402066543 Aug 12 04:22:25 PM PDT 24 Aug 12 04:22:26 PM PDT 24 375878879 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.611937639 Aug 12 04:21:52 PM PDT 24 Aug 12 04:21:54 PM PDT 24 1005925654 ps
T78 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4071813330 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:47 PM PDT 24 433859651 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3595417518 Aug 12 04:27:50 PM PDT 24 Aug 12 04:27:54 PM PDT 24 1126346703 ps
T308 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4253513182 Aug 12 04:26:56 PM PDT 24 Aug 12 04:26:59 PM PDT 24 482509532 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2296564163 Aug 12 04:26:08 PM PDT 24 Aug 12 04:26:11 PM PDT 24 782191471 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3435491745 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:15 PM PDT 24 486671917 ps
T58 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3078921477 Aug 12 04:26:10 PM PDT 24 Aug 12 04:26:14 PM PDT 24 1874982592 ps
T59 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2862694160 Aug 12 04:25:41 PM PDT 24 Aug 12 04:25:42 PM PDT 24 1514485999 ps
T46 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1556007923 Aug 12 04:26:03 PM PDT 24 Aug 12 04:26:03 PM PDT 24 532426970 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3800898012 Aug 12 04:24:40 PM PDT 24 Aug 12 04:24:41 PM PDT 24 291040960 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3027641698 Aug 12 04:25:36 PM PDT 24 Aug 12 04:25:37 PM PDT 24 323417741 ps
T312 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3989413618 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:26 PM PDT 24 350234472 ps
T313 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1200204195 Aug 12 04:22:08 PM PDT 24 Aug 12 04:22:09 PM PDT 24 404088613 ps
T314 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2763969558 Aug 12 04:25:44 PM PDT 24 Aug 12 04:25:46 PM PDT 24 388488901 ps
T315 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2842929361 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:47 PM PDT 24 464623825 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3692969985 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:15 PM PDT 24 525148841 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.608321109 Aug 12 04:21:05 PM PDT 24 Aug 12 04:21:12 PM PDT 24 4042638757 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2805634059 Aug 12 04:27:34 PM PDT 24 Aug 12 04:27:36 PM PDT 24 496925066 ps
T195 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.818071165 Aug 12 04:26:19 PM PDT 24 Aug 12 04:26:22 PM PDT 24 8280687736 ps
T319 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3690819473 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:30 PM PDT 24 513384170 ps
T320 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.48873149 Aug 12 04:26:24 PM PDT 24 Aug 12 04:26:26 PM PDT 24 596954242 ps
T321 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1224869839 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:05 PM PDT 24 4553030661 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3335362613 Aug 12 04:21:04 PM PDT 24 Aug 12 04:21:06 PM PDT 24 538964751 ps
T323 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1215466000 Aug 12 04:25:36 PM PDT 24 Aug 12 04:25:38 PM PDT 24 511698242 ps
T324 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2827765613 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:19 PM PDT 24 388479421 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1037156716 Aug 12 04:27:13 PM PDT 24 Aug 12 04:27:15 PM PDT 24 490563973 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3710405188 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:29 PM PDT 24 707819800 ps
T327 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3181618055 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:31 PM PDT 24 405120174 ps
T328 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1543983372 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:31 PM PDT 24 495762859 ps
T329 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.469825593 Aug 12 04:23:27 PM PDT 24 Aug 12 04:23:29 PM PDT 24 1768018359 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1866227249 Aug 12 04:23:46 PM PDT 24 Aug 12 04:23:58 PM PDT 24 7878219145 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.915837666 Aug 12 04:25:37 PM PDT 24 Aug 12 04:25:39 PM PDT 24 422348879 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1850178919 Aug 12 04:24:35 PM PDT 24 Aug 12 04:24:37 PM PDT 24 604251422 ps
T333 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4176074465 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:26 PM PDT 24 499213823 ps
T334 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.670624545 Aug 12 04:26:17 PM PDT 24 Aug 12 04:26:18 PM PDT 24 459627672 ps
T47 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2557028237 Aug 12 04:23:03 PM PDT 24 Aug 12 04:23:04 PM PDT 24 729985311 ps
T335 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.245725857 Aug 12 04:26:34 PM PDT 24 Aug 12 04:26:35 PM PDT 24 419859481 ps
T336 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.618903312 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:20 PM PDT 24 520262319 ps
T337 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2390098935 Aug 12 04:25:04 PM PDT 24 Aug 12 04:25:05 PM PDT 24 533652129 ps
T60 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1143870910 Aug 12 04:27:11 PM PDT 24 Aug 12 04:27:14 PM PDT 24 1815708203 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.242789732 Aug 12 04:26:11 PM PDT 24 Aug 12 04:26:13 PM PDT 24 425492846 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1874316805 Aug 12 04:21:05 PM PDT 24 Aug 12 04:21:07 PM PDT 24 2219387609 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1963999955 Aug 12 04:25:45 PM PDT 24 Aug 12 04:25:46 PM PDT 24 610768055 ps
T340 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.848050815 Aug 12 04:25:59 PM PDT 24 Aug 12 04:26:00 PM PDT 24 529116058 ps
T48 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3190554369 Aug 12 04:23:15 PM PDT 24 Aug 12 04:23:26 PM PDT 24 3739051073 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2423914436 Aug 12 04:24:16 PM PDT 24 Aug 12 04:24:17 PM PDT 24 663236900 ps
T342 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.41801506 Aug 12 04:23:41 PM PDT 24 Aug 12 04:23:42 PM PDT 24 493426332 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1889523028 Aug 12 04:21:05 PM PDT 24 Aug 12 04:21:08 PM PDT 24 1227865827 ps
T49 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2868720957 Aug 12 04:23:37 PM PDT 24 Aug 12 04:23:39 PM PDT 24 483436547 ps
T344 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2103941925 Aug 12 04:27:10 PM PDT 24 Aug 12 04:27:12 PM PDT 24 491708544 ps
T345 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2347213176 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:02 PM PDT 24 761004578 ps
T50 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.39990852 Aug 12 04:21:04 PM PDT 24 Aug 12 04:21:16 PM PDT 24 6716312157 ps
T193 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.174336190 Aug 12 04:26:30 PM PDT 24 Aug 12 04:26:38 PM PDT 24 4358295156 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3106891012 Aug 12 04:24:52 PM PDT 24 Aug 12 04:24:53 PM PDT 24 367969647 ps
T347 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2350383422 Aug 12 04:27:28 PM PDT 24 Aug 12 04:27:30 PM PDT 24 660895660 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3314621495 Aug 12 04:25:54 PM PDT 24 Aug 12 04:25:55 PM PDT 24 459032115 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2735910283 Aug 12 04:22:17 PM PDT 24 Aug 12 04:22:18 PM PDT 24 583310494 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3627946088 Aug 12 04:26:17 PM PDT 24 Aug 12 04:26:18 PM PDT 24 1114236106 ps
T62 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1881024253 Aug 12 04:26:23 PM PDT 24 Aug 12 04:26:29 PM PDT 24 2144421840 ps
T63 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2713146293 Aug 12 04:25:33 PM PDT 24 Aug 12 04:25:35 PM PDT 24 2173762253 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2373026131 Aug 12 04:26:09 PM PDT 24 Aug 12 04:26:11 PM PDT 24 468503470 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2032918578 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:07 PM PDT 24 4094668767 ps
T352 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1365179888 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:29 PM PDT 24 360827980 ps
T353 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2780736234 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:30 PM PDT 24 332038214 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1328457226 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:20 PM PDT 24 907237825 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3401831902 Aug 12 04:22:25 PM PDT 24 Aug 12 04:22:26 PM PDT 24 296589516 ps
T356 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2030390744 Aug 12 04:26:51 PM PDT 24 Aug 12 04:26:53 PM PDT 24 4008777328 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1420980425 Aug 12 04:21:48 PM PDT 24 Aug 12 04:21:49 PM PDT 24 2287209718 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3722407200 Aug 12 04:25:44 PM PDT 24 Aug 12 04:25:46 PM PDT 24 530946940 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1234500697 Aug 12 04:26:32 PM PDT 24 Aug 12 04:26:33 PM PDT 24 409128269 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2404938375 Aug 12 04:26:00 PM PDT 24 Aug 12 04:26:10 PM PDT 24 12387710087 ps
T360 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2031244754 Aug 12 04:23:01 PM PDT 24 Aug 12 04:23:02 PM PDT 24 1590676126 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1938847894 Aug 12 04:27:26 PM PDT 24 Aug 12 04:27:27 PM PDT 24 640050151 ps
T362 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3302815175 Aug 12 04:26:42 PM PDT 24 Aug 12 04:26:44 PM PDT 24 443378334 ps
T363 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.514468297 Aug 12 04:26:52 PM PDT 24 Aug 12 04:26:53 PM PDT 24 364094397 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1578641497 Aug 12 04:25:02 PM PDT 24 Aug 12 04:25:27 PM PDT 24 10115140425 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4050244082 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:29 PM PDT 24 1262352461 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3717347805 Aug 12 04:27:43 PM PDT 24 Aug 12 04:27:44 PM PDT 24 365613931 ps
T366 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4211023278 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:31 PM PDT 24 505158622 ps
T367 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2311551686 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:29 PM PDT 24 473917085 ps
T368 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.308376320 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:30 PM PDT 24 398547909 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.561130350 Aug 12 04:21:07 PM PDT 24 Aug 12 04:21:09 PM PDT 24 441471040 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1111741582 Aug 12 04:22:17 PM PDT 24 Aug 12 04:22:19 PM PDT 24 436994279 ps
T371 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4136906927 Aug 12 04:26:18 PM PDT 24 Aug 12 04:26:19 PM PDT 24 434765226 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3126801302 Aug 12 04:26:55 PM PDT 24 Aug 12 04:26:56 PM PDT 24 589600968 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3773148947 Aug 12 04:21:10 PM PDT 24 Aug 12 04:21:12 PM PDT 24 504579006 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.399758638 Aug 12 04:26:57 PM PDT 24 Aug 12 04:27:01 PM PDT 24 4346504861 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1599141050 Aug 12 04:26:12 PM PDT 24 Aug 12 04:26:13 PM PDT 24 2619392181 ps
T376 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1107500307 Aug 12 04:26:35 PM PDT 24 Aug 12 04:26:36 PM PDT 24 389855345 ps
T377 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.34206295 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:30 PM PDT 24 332060837 ps
T378 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2347614821 Aug 12 04:22:47 PM PDT 24 Aug 12 04:22:48 PM PDT 24 495561670 ps
T379 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.551195820 Aug 12 04:25:45 PM PDT 24 Aug 12 04:25:47 PM PDT 24 366783918 ps
T380 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3648894873 Aug 12 04:26:19 PM PDT 24 Aug 12 04:26:21 PM PDT 24 1557275747 ps
T381 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4263541169 Aug 12 04:26:37 PM PDT 24 Aug 12 04:26:38 PM PDT 24 329430278 ps
T382 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.592406595 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:31 PM PDT 24 2055922927 ps
T383 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3648761403 Aug 12 04:22:29 PM PDT 24 Aug 12 04:22:36 PM PDT 24 8649708692 ps
T384 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4114849684 Aug 12 04:26:11 PM PDT 24 Aug 12 04:26:12 PM PDT 24 536309231 ps
T385 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4108577679 Aug 12 04:26:28 PM PDT 24 Aug 12 04:26:29 PM PDT 24 303766758 ps
T54 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1710643921 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:34 PM PDT 24 430189568 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2684804056 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:47 PM PDT 24 291456797 ps
T387 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1434644012 Aug 12 04:26:45 PM PDT 24 Aug 12 04:26:46 PM PDT 24 498395019 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2314226725 Aug 12 04:24:25 PM PDT 24 Aug 12 04:24:26 PM PDT 24 368495530 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1881103619 Aug 12 04:25:57 PM PDT 24 Aug 12 04:25:58 PM PDT 24 484119640 ps
T390 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3547483312 Aug 12 04:25:59 PM PDT 24 Aug 12 04:26:02 PM PDT 24 2548516071 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1511725717 Aug 12 04:25:48 PM PDT 24 Aug 12 04:25:49 PM PDT 24 1048915925 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1442429457 Aug 12 04:21:00 PM PDT 24 Aug 12 04:21:02 PM PDT 24 491909554 ps
T393 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1444113549 Aug 12 04:26:09 PM PDT 24 Aug 12 04:26:12 PM PDT 24 463609258 ps
T394 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.481925800 Aug 12 04:27:15 PM PDT 24 Aug 12 04:27:16 PM PDT 24 398437728 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.112132132 Aug 12 04:24:21 PM PDT 24 Aug 12 04:24:22 PM PDT 24 838869730 ps
T396 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3190015702 Aug 12 04:26:29 PM PDT 24 Aug 12 04:26:31 PM PDT 24 369464947 ps
T397 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.710408356 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:48 PM PDT 24 8745102487 ps
T398 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1358923246 Aug 12 04:26:12 PM PDT 24 Aug 12 04:26:14 PM PDT 24 512957613 ps
T55 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3995237308 Aug 12 04:26:08 PM PDT 24 Aug 12 04:26:09 PM PDT 24 324349130 ps
T399 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1006282094 Aug 12 04:23:04 PM PDT 24 Aug 12 04:23:05 PM PDT 24 461618349 ps
T400 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1326848890 Aug 12 04:21:49 PM PDT 24 Aug 12 04:21:56 PM PDT 24 4367476845 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3004483890 Aug 12 04:27:19 PM PDT 24 Aug 12 04:27:21 PM PDT 24 411119399 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1613124678 Aug 12 04:21:05 PM PDT 24 Aug 12 04:21:06 PM PDT 24 480615530 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1821100891 Aug 12 04:25:47 PM PDT 24 Aug 12 04:25:48 PM PDT 24 648043437 ps
T404 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.79620063 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:29 PM PDT 24 497147371 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2372859444 Aug 12 04:21:16 PM PDT 24 Aug 12 04:21:17 PM PDT 24 468702627 ps
T405 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.732680564 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:49 PM PDT 24 1078892852 ps
T406 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1599745484 Aug 12 04:26:12 PM PDT 24 Aug 12 04:26:14 PM PDT 24 1238989368 ps
T407 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3982126840 Aug 12 04:27:18 PM PDT 24 Aug 12 04:27:19 PM PDT 24 380134850 ps
T408 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.917057483 Aug 12 04:26:33 PM PDT 24 Aug 12 04:26:34 PM PDT 24 495763906 ps
T409 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.670741878 Aug 12 04:27:14 PM PDT 24 Aug 12 04:27:17 PM PDT 24 491076727 ps
T410 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2709540715 Aug 12 04:27:26 PM PDT 24 Aug 12 04:27:27 PM PDT 24 452385265 ps
T411 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2981718919 Aug 12 04:25:46 PM PDT 24 Aug 12 04:25:49 PM PDT 24 1408105063 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.286528123 Aug 12 04:26:04 PM PDT 24 Aug 12 04:26:05 PM PDT 24 530392310 ps
T413 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.303237048 Aug 12 04:25:40 PM PDT 24 Aug 12 04:25:43 PM PDT 24 4384742968 ps
T414 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3747532617 Aug 12 04:26:57 PM PDT 24 Aug 12 04:27:00 PM PDT 24 4642836696 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.375341887 Aug 12 04:26:14 PM PDT 24 Aug 12 04:26:16 PM PDT 24 303027604 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2753933930 Aug 12 04:25:45 PM PDT 24 Aug 12 04:25:46 PM PDT 24 344684038 ps
T417 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2488805292 Aug 12 04:26:05 PM PDT 24 Aug 12 04:26:06 PM PDT 24 539970752 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3438238354 Aug 12 04:21:05 PM PDT 24 Aug 12 04:21:06 PM PDT 24 314376197 ps
T419 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1651000275 Aug 12 04:25:42 PM PDT 24 Aug 12 04:25:43 PM PDT 24 445897879 ps
T420 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3403160988 Aug 12 04:26:27 PM PDT 24 Aug 12 04:26:28 PM PDT 24 339633898 ps
T421 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1393451786 Aug 12 04:26:26 PM PDT 24 Aug 12 04:26:27 PM PDT 24 508987569 ps
T422 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.936372081 Aug 12 04:25:40 PM PDT 24 Aug 12 04:25:41 PM PDT 24 404998580 ps
T423 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2054100001 Aug 12 04:26:10 PM PDT 24 Aug 12 04:26:11 PM PDT 24 1412666387 ps
T424 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.859021228 Aug 12 04:23:54 PM PDT 24 Aug 12 04:23:55 PM PDT 24 464572290 ps
T425 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.536429885 Aug 12 04:22:18 PM PDT 24 Aug 12 04:22:19 PM PDT 24 324421089 ps
T426 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.218239472 Aug 12 04:26:25 PM PDT 24 Aug 12 04:26:26 PM PDT 24 552309647 ps

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3617392641
Short name T1
Test name
Test status
Simulation time 38487609445 ps
CPU time 16.37 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 199012 kb
Host smart-d2e6bd70-fad9-43b3-a811-16207c579057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617392641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3617392641
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1658347825
Short name T10
Test name
Test status
Simulation time 102640841756 ps
CPU time 39.56 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:55 PM PDT 24
Peak memory 193228 kb
Host smart-7f5afa70-7459-46c7-8e69-7fe947fa05a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658347825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1658347825
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2958416131
Short name T37
Test name
Test status
Simulation time 4235471955 ps
CPU time 4.36 seconds
Started Aug 12 04:25:56 PM PDT 24
Finished Aug 12 04:26:00 PM PDT 24
Peak memory 198140 kb
Host smart-668109fb-47f0-4125-af1b-9e7c338d9eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958416131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2958416131
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1036217483
Short name T30
Test name
Test status
Simulation time 50588398274 ps
CPU time 65.55 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:26:24 PM PDT 24
Peak memory 192720 kb
Host smart-de3bfa47-3a59-421c-b187-6faf3255d72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036217483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1036217483
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.790029475
Short name T125
Test name
Test status
Simulation time 33149824922 ps
CPU time 63.72 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 207008 kb
Host smart-3e0d80e6-ab58-4714-b52f-998adf52d822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790029475 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.790029475
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.378236363
Short name T36
Test name
Test status
Simulation time 402424815 ps
CPU time 1.12 seconds
Started Aug 12 04:25:40 PM PDT 24
Finished Aug 12 04:25:42 PM PDT 24
Peak memory 193296 kb
Host smart-5b634f95-ac5b-4eb9-af9d-eb02cc25b422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378236363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.378236363
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.102245523
Short name T117
Test name
Test status
Simulation time 5630330901 ps
CPU time 41.49 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 215192 kb
Host smart-2fdcc783-11be-4647-8d9d-cb029f312a4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102245523 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.102245523
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1564772607
Short name T97
Test name
Test status
Simulation time 80152878612 ps
CPU time 65.9 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:26:35 PM PDT 24
Peak memory 193184 kb
Host smart-127d7cb1-e07e-426d-8566-c684d98c18b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564772607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1564772607
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.741109947
Short name T94
Test name
Test status
Simulation time 22592989532 ps
CPU time 15.17 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 192152 kb
Host smart-07df40d1-6f20-4818-afff-15577d626ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741109947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.741109947
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2703418041
Short name T119
Test name
Test status
Simulation time 98762775411 ps
CPU time 71.29 seconds
Started Aug 12 05:25:12 PM PDT 24
Finished Aug 12 05:26:23 PM PDT 24
Peak memory 193432 kb
Host smart-e6c3998a-8d8a-4758-807f-99dadbc28a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703418041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2703418041
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.28749113
Short name T14
Test name
Test status
Simulation time 7801152474 ps
CPU time 13.1 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:24 PM PDT 24
Peak memory 216188 kb
Host smart-f5b663fd-d7d3-4e25-aab0-7881d9f072e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28749113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.28749113
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3174140203
Short name T93
Test name
Test status
Simulation time 109455614747 ps
CPU time 21.37 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 193240 kb
Host smart-b8fc18a8-0201-4c73-8e8e-f84c39803e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174140203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3174140203
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1966040319
Short name T113
Test name
Test status
Simulation time 19094208299 ps
CPU time 49.02 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:26:18 PM PDT 24
Peak memory 198752 kb
Host smart-c4e180bc-dbc4-43be-b993-7ef1529b612b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966040319 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1966040319
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4057253433
Short name T106
Test name
Test status
Simulation time 5501656362 ps
CPU time 35.8 seconds
Started Aug 12 05:25:46 PM PDT 24
Finished Aug 12 05:26:21 PM PDT 24
Peak memory 206996 kb
Host smart-b88d3eea-2b3a-4128-90da-a42160835707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057253433 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4057253433
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.548330842
Short name T87
Test name
Test status
Simulation time 343165475835 ps
CPU time 129.12 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:27:18 PM PDT 24
Peak memory 193108 kb
Host smart-009ce551-81ab-4f85-aa4e-f74147180957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548330842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.548330842
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.503387459
Short name T83
Test name
Test status
Simulation time 4350665829 ps
CPU time 16.1 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:24 PM PDT 24
Peak memory 215100 kb
Host smart-955c2966-2baf-4e42-a923-c1a79b94d3a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503387459 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.503387459
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1299514769
Short name T45
Test name
Test status
Simulation time 101147686401 ps
CPU time 126.8 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:27:37 PM PDT 24
Peak memory 198496 kb
Host smart-289f2bbe-d873-400e-b5ff-f3b91aa8b8f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299514769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1299514769
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.936230223
Short name T103
Test name
Test status
Simulation time 168347135303 ps
CPU time 38.57 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:26:15 PM PDT 24
Peak memory 192200 kb
Host smart-64a87335-d90b-4db2-9cee-ebce8cb0b2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936230223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.936230223
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1655893822
Short name T115
Test name
Test status
Simulation time 2636078845 ps
CPU time 12.81 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:41 PM PDT 24
Peak memory 206936 kb
Host smart-0c10fdba-cc0f-4c9b-95d9-7dc397ee8958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655893822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1655893822
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2081394565
Short name T153
Test name
Test status
Simulation time 91796848298 ps
CPU time 119.28 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:27:08 PM PDT 24
Peak memory 198504 kb
Host smart-dd2033e4-eb27-4fef-a29f-070e392c5c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081394565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2081394565
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3005777699
Short name T89
Test name
Test status
Simulation time 196422513073 ps
CPU time 66.41 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 193304 kb
Host smart-28cfb258-89ea-44c5-ab26-2699bf8e2a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005777699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3005777699
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2376340962
Short name T132
Test name
Test status
Simulation time 101473132298 ps
CPU time 30.96 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:26:07 PM PDT 24
Peak memory 198556 kb
Host smart-83a2fb26-0e0a-4f9f-8c07-e3a8caf44498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376340962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2376340962
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3659475737
Short name T133
Test name
Test status
Simulation time 388535086461 ps
CPU time 537.77 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:34:13 PM PDT 24
Peak memory 193220 kb
Host smart-77e97e65-4716-4c09-9477-38f50e2b227d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659475737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3659475737
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2061175563
Short name T112
Test name
Test status
Simulation time 159544236250 ps
CPU time 104.57 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:27:12 PM PDT 24
Peak memory 193224 kb
Host smart-d032b82f-bba9-4050-99e6-c8f1ca290bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061175563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2061175563
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2450448227
Short name T136
Test name
Test status
Simulation time 3309889165 ps
CPU time 18.07 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:34 PM PDT 24
Peak memory 198764 kb
Host smart-5be19f5e-6eac-4d5d-8b38-41275d9fda3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450448227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2450448227
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2897146421
Short name T102
Test name
Test status
Simulation time 260370530132 ps
CPU time 59.49 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:26:16 PM PDT 24
Peak memory 192156 kb
Host smart-8b99a988-0edc-4e8f-b555-778c7977207b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897146421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2897146421
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1571100919
Short name T8
Test name
Test status
Simulation time 143368105271 ps
CPU time 52.52 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:26:20 PM PDT 24
Peak memory 193276 kb
Host smart-63083633-c34c-47b0-b44f-5a1f0e381f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571100919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1571100919
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.689391423
Short name T12
Test name
Test status
Simulation time 3094162459 ps
CPU time 5.47 seconds
Started Aug 12 05:25:52 PM PDT 24
Finished Aug 12 05:25:58 PM PDT 24
Peak memory 198480 kb
Host smart-46e21426-aadd-4ae3-98f3-e37793d40636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689391423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.689391423
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2443816456
Short name T31
Test name
Test status
Simulation time 47140846368 ps
CPU time 18.7 seconds
Started Aug 12 05:25:45 PM PDT 24
Finished Aug 12 05:26:04 PM PDT 24
Peak memory 198428 kb
Host smart-333dc469-2fbc-4161-a2ab-a23c74b8052c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443816456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2443816456
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2283974161
Short name T82
Test name
Test status
Simulation time 5032162968 ps
CPU time 32.59 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 206996 kb
Host smart-50d4991f-eb3c-4a64-ae31-c60e708911d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283974161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2283974161
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3571855061
Short name T68
Test name
Test status
Simulation time 5260236729 ps
CPU time 16.14 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:25:44 PM PDT 24
Peak memory 214260 kb
Host smart-4e1619de-27dc-4d18-8151-7eaa101d61f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571855061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3571855061
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.939906010
Short name T116
Test name
Test status
Simulation time 18897452274 ps
CPU time 55.38 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:26:27 PM PDT 24
Peak memory 207032 kb
Host smart-eb7a6c26-3e0e-4814-8d1d-80bc32e03120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939906010 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.939906010
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3717728134
Short name T100
Test name
Test status
Simulation time 248498441270 ps
CPU time 89.61 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:26:40 PM PDT 24
Peak memory 193172 kb
Host smart-517f70a1-d7a1-418e-b671-b627268201a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717728134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3717728134
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1997959761
Short name T7
Test name
Test status
Simulation time 8833338813 ps
CPU time 16.43 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 198816 kb
Host smart-5d2c7057-b805-4e73-b5bc-d75238c577d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997959761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1997959761
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3579088830
Short name T159
Test name
Test status
Simulation time 8185731629 ps
CPU time 24.75 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:41 PM PDT 24
Peak memory 198780 kb
Host smart-46bede64-8d16-4667-b3f0-3372ac710cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579088830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3579088830
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2046405409
Short name T114
Test name
Test status
Simulation time 3304338737 ps
CPU time 23.94 seconds
Started Aug 12 05:25:25 PM PDT 24
Finished Aug 12 05:25:49 PM PDT 24
Peak memory 207016 kb
Host smart-10715d4d-1afd-4020-b690-f748820f5115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046405409 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2046405409
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1211830984
Short name T161
Test name
Test status
Simulation time 5668693806 ps
CPU time 48.12 seconds
Started Aug 12 05:25:11 PM PDT 24
Finished Aug 12 05:25:59 PM PDT 24
Peak memory 198760 kb
Host smart-6599bbb3-e886-4f72-b3b5-f0a2efbc9e2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211830984 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1211830984
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3551475058
Short name T91
Test name
Test status
Simulation time 3729900967 ps
CPU time 28.73 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 206712 kb
Host smart-bf1f0b82-9a32-482a-b9a7-de11b44341ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551475058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3551475058
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.200047681
Short name T141
Test name
Test status
Simulation time 68459731146 ps
CPU time 21.9 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 192132 kb
Host smart-9b57160d-1c5f-4123-9a20-57579d6a8c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200047681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.200047681
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.530586728
Short name T144
Test name
Test status
Simulation time 262491114601 ps
CPU time 151.69 seconds
Started Aug 12 05:25:33 PM PDT 24
Finished Aug 12 05:28:05 PM PDT 24
Peak memory 192668 kb
Host smart-f7d43aed-3ffa-47f8-8c7e-04246a51a1da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530586728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.530586728
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1885396294
Short name T118
Test name
Test status
Simulation time 482714939555 ps
CPU time 361.98 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:31:17 PM PDT 24
Peak memory 184928 kb
Host smart-80ce2658-f5b3-4937-ad0d-f5d7793a3d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885396294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1885396294
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.736031075
Short name T104
Test name
Test status
Simulation time 114152551647 ps
CPU time 18 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 192160 kb
Host smart-a8b5ce0b-dd7b-4f9d-82d0-0b48dd7cdb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736031075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.736031075
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1657632568
Short name T85
Test name
Test status
Simulation time 113910084606 ps
CPU time 142.61 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:27:39 PM PDT 24
Peak memory 192288 kb
Host smart-ce3cca99-c6f3-4b50-af21-96029cb78dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657632568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1657632568
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2273828745
Short name T164
Test name
Test status
Simulation time 13451202869 ps
CPU time 40.41 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:10 PM PDT 24
Peak memory 198684 kb
Host smart-df548540-9e8c-4449-ad16-94b0d8ad790b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273828745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2273828745
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.429149409
Short name T131
Test name
Test status
Simulation time 182685782810 ps
CPU time 75.53 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:26:52 PM PDT 24
Peak memory 193284 kb
Host smart-2b9d9986-adb4-4720-acfe-a82d0f06ae84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429149409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.429149409
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3450305258
Short name T130
Test name
Test status
Simulation time 99931734628 ps
CPU time 39.04 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:09 PM PDT 24
Peak memory 192144 kb
Host smart-0e37a7f3-9c26-40b6-97f6-4dd04adeaf40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450305258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3450305258
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4201297626
Short name T121
Test name
Test status
Simulation time 4991017603 ps
CPU time 44.72 seconds
Started Aug 12 05:25:39 PM PDT 24
Finished Aug 12 05:26:23 PM PDT 24
Peak memory 207040 kb
Host smart-d8cd448a-1b52-4228-b573-fa6b618831b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201297626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4201297626
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1113826635
Short name T146
Test name
Test status
Simulation time 34793677114 ps
CPU time 52.55 seconds
Started Aug 12 05:25:38 PM PDT 24
Finished Aug 12 05:26:31 PM PDT 24
Peak memory 192128 kb
Host smart-af8a9ded-a2f8-405b-a4b5-a64549894089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113826635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1113826635
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3646062743
Short name T99
Test name
Test status
Simulation time 274976197756 ps
CPU time 200.81 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:28:39 PM PDT 24
Peak memory 192780 kb
Host smart-5575d31d-c7bd-41a8-ae5e-11b262d45d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646062743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3646062743
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4126206171
Short name T72
Test name
Test status
Simulation time 320893447848 ps
CPU time 35.96 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:52 PM PDT 24
Peak memory 193300 kb
Host smart-c1a5e42d-2b81-4565-90dc-6edcceabd73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126206171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4126206171
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1758070010
Short name T81
Test name
Test status
Simulation time 5502441786 ps
CPU time 35.23 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:26:03 PM PDT 24
Peak memory 207052 kb
Host smart-82a30249-303b-4e5f-bf9d-f925d6777537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758070010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1758070010
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2631749349
Short name T134
Test name
Test status
Simulation time 250629684750 ps
CPU time 91.9 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:26:40 PM PDT 24
Peak memory 198488 kb
Host smart-af0826ba-558d-44b1-b2b1-ea352776dc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631749349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2631749349
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3740025493
Short name T108
Test name
Test status
Simulation time 78260233219 ps
CPU time 55.31 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:26:30 PM PDT 24
Peak memory 198520 kb
Host smart-dbc276d3-6eef-4058-9ef2-7bf3fd62a03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740025493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3740025493
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.165934328
Short name T145
Test name
Test status
Simulation time 3538669088 ps
CPU time 5.98 seconds
Started Aug 12 05:25:39 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 198464 kb
Host smart-12bdc80c-a165-4e22-ba62-8178cf9e0443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165934328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.165934328
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3526215684
Short name T39
Test name
Test status
Simulation time 2927258363 ps
CPU time 15.51 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:25:48 PM PDT 24
Peak memory 199024 kb
Host smart-335a1334-ad0a-410b-94b3-a62a71fbe7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526215684 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3526215684
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1692495057
Short name T109
Test name
Test status
Simulation time 200781527005 ps
CPU time 315.29 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:30:32 PM PDT 24
Peak memory 198604 kb
Host smart-f493b1b6-06c4-43c3-90fa-ecac8a95d2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692495057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1692495057
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2374897457
Short name T80
Test name
Test status
Simulation time 20324685471 ps
CPU time 27.49 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 207016 kb
Host smart-574f7d9c-fb88-4a51-a538-7a2fcb674f37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374897457 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2374897457
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.363377714
Short name T96
Test name
Test status
Simulation time 130868832905 ps
CPU time 201.13 seconds
Started Aug 12 05:25:34 PM PDT 24
Finished Aug 12 05:28:56 PM PDT 24
Peak memory 198496 kb
Host smart-478cfeca-944a-448b-b833-ab7eaec4adc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363377714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.363377714
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3122306954
Short name T98
Test name
Test status
Simulation time 81011029539 ps
CPU time 31.69 seconds
Started Aug 12 05:25:40 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 198592 kb
Host smart-2655d488-32e1-40a6-a3e0-5c327d31919a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122306954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3122306954
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3993220369
Short name T148
Test name
Test status
Simulation time 7096193934 ps
CPU time 14.11 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 214428 kb
Host smart-6114798b-4735-4bdd-9aaa-53b848948755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993220369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3993220369
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.39990852
Short name T50
Test name
Test status
Simulation time 6716312157 ps
CPU time 12.32 seconds
Started Aug 12 04:21:04 PM PDT 24
Finished Aug 12 04:21:16 PM PDT 24
Peak memory 195092 kb
Host smart-d2a93151-d16d-4899-a7bc-a6303f900ffa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39990852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit
_bash.39990852
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3379565810
Short name T151
Test name
Test status
Simulation time 145304357090 ps
CPU time 57.94 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:26:16 PM PDT 24
Peak memory 193192 kb
Host smart-d55b3c00-3ec2-452b-ad0b-3e35c0afb87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379565810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3379565810
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2223249783
Short name T123
Test name
Test status
Simulation time 14310552906 ps
CPU time 24.85 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:55 PM PDT 24
Peak memory 198712 kb
Host smart-3df0f4f2-e352-4f44-a4b9-aa1535b0a9e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223249783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2223249783
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.989192020
Short name T138
Test name
Test status
Simulation time 285680707001 ps
CPU time 348.66 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:31:17 PM PDT 24
Peak memory 198380 kb
Host smart-77b121b0-2746-4197-86fe-07c5c929bcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989192020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.989192020
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1029095692
Short name T124
Test name
Test status
Simulation time 10457542958 ps
CPU time 24.71 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:55 PM PDT 24
Peak memory 198780 kb
Host smart-26eb3474-b42b-4e99-94c9-dbb32c03330a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029095692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1029095692
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.32805721
Short name T41
Test name
Test status
Simulation time 17992657238 ps
CPU time 34.77 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:05 PM PDT 24
Peak memory 198796 kb
Host smart-bd2dcec4-19f9-4e84-919b-f6e54dabf9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32805721 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.32805721
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3203951838
Short name T135
Test name
Test status
Simulation time 646802768005 ps
CPU time 435.97 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:32:52 PM PDT 24
Peak memory 193252 kb
Host smart-529e111d-a2e2-42e0-89b1-d1537fb39b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203951838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3203951838
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3471065016
Short name T163
Test name
Test status
Simulation time 687417663212 ps
CPU time 480.17 seconds
Started Aug 12 05:25:48 PM PDT 24
Finished Aug 12 05:33:49 PM PDT 24
Peak memory 193128 kb
Host smart-16b2cb7f-554c-40eb-9b3f-d215d805fd75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471065016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3471065016
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.561144430
Short name T170
Test name
Test status
Simulation time 5997018333 ps
CPU time 40.23 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:59 PM PDT 24
Peak memory 214768 kb
Host smart-02e5b066-8737-49bf-b626-f11d142ccc2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561144430 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.561144430
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.467558032
Short name T42
Test name
Test status
Simulation time 1379921888 ps
CPU time 5.03 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:15 PM PDT 24
Peak memory 198928 kb
Host smart-e481dbd7-dedd-4bc6-a522-004690f2fa2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467558032 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.467558032
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.840733530
Short name T21
Test name
Test status
Simulation time 5574662801 ps
CPU time 18.76 seconds
Started Aug 12 05:25:50 PM PDT 24
Finished Aug 12 05:26:09 PM PDT 24
Peak memory 207000 kb
Host smart-e4cacbe7-dd86-4542-9233-2d35a6b366ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840733530 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.840733530
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4156170939
Short name T154
Test name
Test status
Simulation time 547459769 ps
CPU time 1.06 seconds
Started Aug 12 05:25:20 PM PDT 24
Finished Aug 12 05:25:21 PM PDT 24
Peak memory 196940 kb
Host smart-f3d2e0b8-bc7e-4d95-a214-376711ef3088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156170939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4156170939
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.397457902
Short name T168
Test name
Test status
Simulation time 3650485812 ps
CPU time 33.19 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:49 PM PDT 24
Peak memory 206900 kb
Host smart-821ac389-2832-4dbb-8641-c9954cbb5dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397457902 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.397457902
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.381242548
Short name T167
Test name
Test status
Simulation time 4789854463 ps
CPU time 22.87 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:54 PM PDT 24
Peak memory 198820 kb
Host smart-9386dca4-6138-414c-a26d-148b62de30c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381242548 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.381242548
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1848291392
Short name T122
Test name
Test status
Simulation time 401038721 ps
CPU time 1.22 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:27 PM PDT 24
Peak memory 196976 kb
Host smart-c8262929-97e9-49d1-b3aa-847ec79b5425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848291392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1848291392
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2250354548
Short name T143
Test name
Test status
Simulation time 404249481 ps
CPU time 0.75 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 197008 kb
Host smart-143f8d10-1b22-4ec8-931f-639dee49f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250354548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2250354548
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.107459598
Short name T120
Test name
Test status
Simulation time 205410253954 ps
CPU time 17.67 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 193248 kb
Host smart-f57b5a4c-7317-4dd5-bb1b-b269782ef469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107459598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.107459598
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1361941113
Short name T34
Test name
Test status
Simulation time 514834701 ps
CPU time 1 seconds
Started Aug 12 05:25:49 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 197012 kb
Host smart-8b9b41a2-6c35-43be-9b4d-091cbee0f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361941113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1361941113
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.544507054
Short name T140
Test name
Test status
Simulation time 451291352 ps
CPU time 0.77 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 197000 kb
Host smart-6ece3ad8-d855-4e35-8050-7c4f012fa75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544507054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.544507054
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.212350837
Short name T111
Test name
Test status
Simulation time 90261451383 ps
CPU time 32.35 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 192156 kb
Host smart-e22668ad-20c8-4ef3-b0e4-8e7b9556be0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212350837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.212350837
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2993233940
Short name T152
Test name
Test status
Simulation time 546223945 ps
CPU time 0.86 seconds
Started Aug 12 05:25:07 PM PDT 24
Finished Aug 12 05:25:08 PM PDT 24
Peak memory 196960 kb
Host smart-0d84c0db-d836-437f-b013-5665df930a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993233940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2993233940
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4128531568
Short name T92
Test name
Test status
Simulation time 393552200 ps
CPU time 1.2 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 196952 kb
Host smart-d3806866-9d64-479a-831f-730fedb35f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128531568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4128531568
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3943459668
Short name T156
Test name
Test status
Simulation time 460097923113 ps
CPU time 298.48 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:30:27 PM PDT 24
Peak memory 193144 kb
Host smart-a2a2cd7d-a7c0-4a31-afbe-0fa83d217714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943459668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3943459668
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2880929234
Short name T166
Test name
Test status
Simulation time 6246665623 ps
CPU time 11.87 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 206980 kb
Host smart-1cf77b2f-94f4-4939-a6ed-f483be1714a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880929234 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2880929234
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2502348745
Short name T129
Test name
Test status
Simulation time 550769035 ps
CPU time 0.82 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 196944 kb
Host smart-40a7553b-850d-496d-a1da-50e35e8fdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502348745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2502348745
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2939483129
Short name T169
Test name
Test status
Simulation time 10209027100 ps
CPU time 20.17 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:25:53 PM PDT 24
Peak memory 198852 kb
Host smart-4ee30831-bd58-4b79-9100-525d690a42ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939483129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2939483129
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2513375806
Short name T32
Test name
Test status
Simulation time 501112623 ps
CPU time 1.3 seconds
Started Aug 12 05:25:34 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 196988 kb
Host smart-8641947e-0d0a-4568-917a-df779d7ad946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513375806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2513375806
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.444138467
Short name T84
Test name
Test status
Simulation time 2439444889 ps
CPU time 7.93 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:26 PM PDT 24
Peak memory 214140 kb
Host smart-3fee9c4d-0f03-4c2e-a42b-ccba144f7a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444138467 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.444138467
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2407159911
Short name T88
Test name
Test status
Simulation time 26578789788 ps
CPU time 28.49 seconds
Started Aug 12 05:25:52 PM PDT 24
Finished Aug 12 05:26:20 PM PDT 24
Peak memory 198788 kb
Host smart-9e7dca31-9e0c-46c4-a686-ee3e84591fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407159911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2407159911
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.259838216
Short name T107
Test name
Test status
Simulation time 5077749494 ps
CPU time 16.41 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:35 PM PDT 24
Peak memory 198812 kb
Host smart-8230a19a-fceb-48f3-a663-b0378db4211d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259838216 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.259838216
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.913938070
Short name T40
Test name
Test status
Simulation time 5687820430 ps
CPU time 12.63 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 214204 kb
Host smart-f6e2448b-6b96-4df4-b8d3-416b5490adea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913938070 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.913938070
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.388147061
Short name T29
Test name
Test status
Simulation time 562597234 ps
CPU time 0.7 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 197008 kb
Host smart-eb31787f-c816-484e-81d4-2431d3c04af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388147061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.388147061
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3834225851
Short name T147
Test name
Test status
Simulation time 5270497957 ps
CPU time 13.91 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 207036 kb
Host smart-a4ca2662-ba27-4a1d-b0a0-ae99564ef8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834225851 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3834225851
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2873622562
Short name T86
Test name
Test status
Simulation time 540519563 ps
CPU time 0.78 seconds
Started Aug 12 05:25:45 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 196956 kb
Host smart-e3f064e0-087d-477f-afaa-0fab72f79f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873622562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2873622562
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1242978210
Short name T65
Test name
Test status
Simulation time 472832271 ps
CPU time 0.64 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 196984 kb
Host smart-1d278271-1039-4ebe-a378-5e8abb073078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242978210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1242978210
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2395095084
Short name T26
Test name
Test status
Simulation time 406410029 ps
CPU time 1 seconds
Started Aug 12 05:25:03 PM PDT 24
Finished Aug 12 05:25:04 PM PDT 24
Peak memory 196828 kb
Host smart-1a84d1e0-fd64-46e6-bd1e-d93743b9b224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395095084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2395095084
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4242434474
Short name T137
Test name
Test status
Simulation time 2481164156 ps
CPU time 13.53 seconds
Started Aug 12 05:25:02 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 214748 kb
Host smart-d6b989f2-d96d-4a52-a96e-110fb4c8efe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242434474 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4242434474
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2553286419
Short name T4
Test name
Test status
Simulation time 609690886 ps
CPU time 0.67 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 196824 kb
Host smart-cbd1606d-aa3b-4849-a503-c8cd8739df30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553286419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2553286419
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2248689019
Short name T27
Test name
Test status
Simulation time 581920848 ps
CPU time 0.72 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 197012 kb
Host smart-8d5f42bb-3200-4218-b2f9-c4d23a125b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248689019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2248689019
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2598206604
Short name T25
Test name
Test status
Simulation time 268986344075 ps
CPU time 100.44 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:26:59 PM PDT 24
Peak memory 193220 kb
Host smart-063c69ad-f861-4967-97bc-65c808a0351d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598206604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2598206604
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3423301878
Short name T64
Test name
Test status
Simulation time 3399275351 ps
CPU time 28.13 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:47 PM PDT 24
Peak memory 198960 kb
Host smart-13df166f-66ef-4151-825a-9c8ff8edb50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423301878 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3423301878
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1889752269
Short name T95
Test name
Test status
Simulation time 423640855 ps
CPU time 0.88 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 197064 kb
Host smart-b237e79f-d4ef-4eb9-b976-bfd3d991723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889752269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1889752269
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4155534540
Short name T172
Test name
Test status
Simulation time 122572388628 ps
CPU time 63.21 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 192180 kb
Host smart-ea0db34a-b5ba-43da-a093-30bc5551d054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155534540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4155534540
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1436060951
Short name T127
Test name
Test status
Simulation time 461026038 ps
CPU time 1.21 seconds
Started Aug 12 05:25:51 PM PDT 24
Finished Aug 12 05:25:52 PM PDT 24
Peak memory 196900 kb
Host smart-a962b8d6-6a47-4cce-a2fe-0ce1ed097744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436060951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1436060951
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3112108191
Short name T150
Test name
Test status
Simulation time 513097323 ps
CPU time 0.75 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 196932 kb
Host smart-7564bd0c-090e-44d6-a766-50473699030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112108191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3112108191
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3879986784
Short name T165
Test name
Test status
Simulation time 251451408156 ps
CPU time 88.2 seconds
Started Aug 12 05:25:02 PM PDT 24
Finished Aug 12 05:26:31 PM PDT 24
Peak memory 193168 kb
Host smart-38adb851-c7d3-4883-93e9-10bf8c412a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879986784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3879986784
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2683501413
Short name T90
Test name
Test status
Simulation time 457729192 ps
CPU time 0.74 seconds
Started Aug 12 05:25:20 PM PDT 24
Finished Aug 12 05:25:21 PM PDT 24
Peak memory 196924 kb
Host smart-96229a9d-c06b-4e21-acda-d9b487b14d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683501413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2683501413
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2625249276
Short name T155
Test name
Test status
Simulation time 585087635 ps
CPU time 1 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 196912 kb
Host smart-f46db94c-4e4c-4d62-8287-3602d4a6affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625249276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2625249276
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.526775540
Short name T139
Test name
Test status
Simulation time 89776183558 ps
CPU time 27.09 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:53 PM PDT 24
Peak memory 198476 kb
Host smart-f9f04b07-1856-454d-abda-b5dbb8c34b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526775540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.526775540
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3131224594
Short name T142
Test name
Test status
Simulation time 413684352 ps
CPU time 0.87 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 196936 kb
Host smart-3e4a2b15-42d3-4a64-a977-5b2f1183a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131224594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3131224594
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1535336395
Short name T149
Test name
Test status
Simulation time 455671187 ps
CPU time 0.81 seconds
Started Aug 12 05:25:50 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 196992 kb
Host smart-e244ef94-129c-424b-afb6-44cb2cae7087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535336395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1535336395
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.887440323
Short name T177
Test name
Test status
Simulation time 617808389 ps
CPU time 1.04 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 196880 kb
Host smart-7414c778-bd73-48d8-b37e-d7e3f72aec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887440323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.887440323
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.4154074288
Short name T188
Test name
Test status
Simulation time 376567974 ps
CPU time 0.76 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 197012 kb
Host smart-209bbfc7-d2fc-44cc-a195-3985add45d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154074288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4154074288
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.498538556
Short name T181
Test name
Test status
Simulation time 490729493 ps
CPU time 0.74 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 196888 kb
Host smart-092e0db7-357e-48e9-b49e-7e94df4bc245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498538556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.498538556
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2171210087
Short name T171
Test name
Test status
Simulation time 594617588 ps
CPU time 1.48 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 196788 kb
Host smart-a33b2e7b-6dee-4f25-b0c1-d4762c4e283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171210087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2171210087
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3078675880
Short name T126
Test name
Test status
Simulation time 473918992 ps
CPU time 1.43 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 197008 kb
Host smart-7839d8b0-43f7-4e87-9439-97de22f5bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078675880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3078675880
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2545430863
Short name T128
Test name
Test status
Simulation time 549603063 ps
CPU time 0.86 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 197020 kb
Host smart-420f1e40-c299-4dc3-a65f-cec757daa32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545430863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2545430863
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4188850270
Short name T105
Test name
Test status
Simulation time 424727775 ps
CPU time 0.85 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 197008 kb
Host smart-21431ad3-3314-40a4-87d4-b5d53f680d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188850270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4188850270
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1383749395
Short name T179
Test name
Test status
Simulation time 533905377 ps
CPU time 1.32 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 196932 kb
Host smart-9d1ea30f-f92d-4866-a342-8bb4cb5c5a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383749395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1383749395
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1853265682
Short name T20
Test name
Test status
Simulation time 475643644 ps
CPU time 0.78 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 196996 kb
Host smart-9f6f3e43-4584-43c5-a9c4-2f7e74e022cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853265682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1853265682
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3231249341
Short name T11
Test name
Test status
Simulation time 10570322047 ps
CPU time 17.47 seconds
Started Aug 12 05:25:43 PM PDT 24
Finished Aug 12 05:26:01 PM PDT 24
Peak memory 206992 kb
Host smart-3f8925c0-9080-4d03-8740-0a92c36a3f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231249341 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3231249341
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.540872087
Short name T180
Test name
Test status
Simulation time 165962813149 ps
CPU time 48.01 seconds
Started Aug 12 05:25:40 PM PDT 24
Finished Aug 12 05:26:28 PM PDT 24
Peak memory 193232 kb
Host smart-c80e76b2-6657-4aaa-9065-962e251354d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540872087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.540872087
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.701644344
Short name T185
Test name
Test status
Simulation time 425648661 ps
CPU time 1.29 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 196992 kb
Host smart-da48ea69-66f6-42c8-ad52-816e29d5a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701644344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.701644344
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.762415561
Short name T192
Test name
Test status
Simulation time 8295199043 ps
CPU time 14.61 seconds
Started Aug 12 04:27:11 PM PDT 24
Finished Aug 12 04:27:26 PM PDT 24
Peak memory 198204 kb
Host smart-7ece379c-46d8-4b9b-9946-2c500dc8834c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762415561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.762415561
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1435270943
Short name T110
Test name
Test status
Simulation time 576796726 ps
CPU time 0.99 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 196932 kb
Host smart-1b479b2c-6aeb-4645-861e-9c25255a6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435270943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1435270943
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1719828710
Short name T160
Test name
Test status
Simulation time 9155587088 ps
CPU time 23.59 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 198896 kb
Host smart-1d94fe27-f2b6-494a-afbc-5ab98c813859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719828710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1719828710
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.391891212
Short name T162
Test name
Test status
Simulation time 421032215 ps
CPU time 1.23 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 196896 kb
Host smart-9c14384e-c596-463d-9bfd-95ec010a8378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391891212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.391891212
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3331863536
Short name T13
Test name
Test status
Simulation time 442680034 ps
CPU time 0.79 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 196880 kb
Host smart-32afcbc3-8998-4106-a69b-d59058782901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331863536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3331863536
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2718911500
Short name T186
Test name
Test status
Simulation time 61743207241 ps
CPU time 25.67 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:54 PM PDT 24
Peak memory 198484 kb
Host smart-7e61392f-b25e-4f8e-8089-1920a03e1272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718911500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2718911500
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1808972702
Short name T173
Test name
Test status
Simulation time 538397118 ps
CPU time 0.78 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:25:37 PM PDT 24
Peak memory 196892 kb
Host smart-19d67862-6994-4216-a90c-6a3d5cb2d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808972702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1808972702
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2439334161
Short name T189
Test name
Test status
Simulation time 7473897035 ps
CPU time 17.15 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:47 PM PDT 24
Peak memory 206884 kb
Host smart-ac134894-55c4-4842-8d02-0dd476b45404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439334161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2439334161
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3563539344
Short name T182
Test name
Test status
Simulation time 639387038 ps
CPU time 0.76 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:25:37 PM PDT 24
Peak memory 196980 kb
Host smart-356b62d6-3f86-4b33-b126-a2970558e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563539344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3563539344
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3928257627
Short name T190
Test name
Test status
Simulation time 558402182 ps
CPU time 0.82 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 196880 kb
Host smart-48531f6e-b80f-483f-aa27-6c7f961532f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928257627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3928257627
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1823174950
Short name T22
Test name
Test status
Simulation time 513179397 ps
CPU time 1.34 seconds
Started Aug 12 05:25:40 PM PDT 24
Finished Aug 12 05:25:41 PM PDT 24
Peak memory 196936 kb
Host smart-bdd2472f-c995-4144-9021-973d129d09c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823174950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1823174950
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1208749615
Short name T175
Test name
Test status
Simulation time 390994467 ps
CPU time 0.77 seconds
Started Aug 12 05:25:42 PM PDT 24
Finished Aug 12 05:25:43 PM PDT 24
Peak memory 196908 kb
Host smart-419ba364-3db8-455b-8705-504b68af3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208749615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1208749615
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.904488468
Short name T184
Test name
Test status
Simulation time 535822031 ps
CPU time 1 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 197012 kb
Host smart-bd6fef1f-a28a-48ad-b745-f42f4209becb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904488468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.904488468
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.818071165
Short name T195
Test name
Test status
Simulation time 8280687736 ps
CPU time 3.01 seconds
Started Aug 12 04:26:19 PM PDT 24
Finished Aug 12 04:26:22 PM PDT 24
Peak memory 198556 kb
Host smart-68284cf8-9158-4f7c-aa14-1503779e9108
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818071165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.818071165
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1543159864
Short name T157
Test name
Test status
Simulation time 480037197 ps
CPU time 1.32 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:21 PM PDT 24
Peak memory 196796 kb
Host smart-b506af8d-29fe-477e-bb70-6d000a0e62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543159864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1543159864
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.557559910
Short name T174
Test name
Test status
Simulation time 544459748 ps
CPU time 0.98 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 197048 kb
Host smart-dfb578c3-adb4-436d-9239-fbdb63626d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557559910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.557559910
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.940984682
Short name T183
Test name
Test status
Simulation time 480747975 ps
CPU time 0.75 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 196968 kb
Host smart-10a39f43-ca16-405d-9954-630a64fbb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940984682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.940984682
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3741727581
Short name T24
Test name
Test status
Simulation time 6189047639 ps
CPU time 12.01 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 199140 kb
Host smart-b2032b7c-3ba3-4f7f-b297-7a3768f7ddb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741727581 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3741727581
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.936053830
Short name T73
Test name
Test status
Simulation time 521665381 ps
CPU time 0.75 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 196900 kb
Host smart-bd625b71-e817-4681-9757-e118f4471f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936053830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.936053830
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3597800069
Short name T178
Test name
Test status
Simulation time 585937191 ps
CPU time 1.04 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 196860 kb
Host smart-f068d0f7-934a-424b-a84c-745a34c8150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597800069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3597800069
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2689463721
Short name T101
Test name
Test status
Simulation time 355089071 ps
CPU time 0.94 seconds
Started Aug 12 05:25:37 PM PDT 24
Finished Aug 12 05:25:38 PM PDT 24
Peak memory 196704 kb
Host smart-68b371d9-a429-4e07-9e3f-e00ebe76afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689463721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2689463721
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3773148947
Short name T373
Test name
Test status
Simulation time 504579006 ps
CPU time 1.42 seconds
Started Aug 12 04:21:10 PM PDT 24
Finished Aug 12 04:21:12 PM PDT 24
Peak memory 182644 kb
Host smart-99c62ce4-87d7-4966-8cbd-56f38d9f1c71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773148947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3773148947
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1889523028
Short name T343
Test name
Test status
Simulation time 1227865827 ps
CPU time 2.37 seconds
Started Aug 12 04:21:05 PM PDT 24
Finished Aug 12 04:21:08 PM PDT 24
Peak memory 183436 kb
Host smart-ed6c8b8f-fcdc-490d-a4b9-7d967f14b97c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889523028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1889523028
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2735910283
Short name T349
Test name
Test status
Simulation time 583310494 ps
CPU time 1.29 seconds
Started Aug 12 04:22:17 PM PDT 24
Finished Aug 12 04:22:18 PM PDT 24
Peak memory 198608 kb
Host smart-b1d61f54-9cc9-4e2b-a63c-bf529c3f82bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735910283 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2735910283
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.561130350
Short name T369
Test name
Test status
Simulation time 441471040 ps
CPU time 1.19 seconds
Started Aug 12 04:21:07 PM PDT 24
Finished Aug 12 04:21:09 PM PDT 24
Peak memory 192648 kb
Host smart-598f3db5-8c02-49fe-897b-b37b92950487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561130350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.561130350
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1613124678
Short name T402
Test name
Test status
Simulation time 480615530 ps
CPU time 1.2 seconds
Started Aug 12 04:21:05 PM PDT 24
Finished Aug 12 04:21:06 PM PDT 24
Peak memory 183344 kb
Host smart-a5839eea-7280-4e6c-9c2d-378afa8bbdb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613124678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1613124678
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3438238354
Short name T418
Test name
Test status
Simulation time 314376197 ps
CPU time 0.97 seconds
Started Aug 12 04:21:05 PM PDT 24
Finished Aug 12 04:21:06 PM PDT 24
Peak memory 183980 kb
Host smart-93e6034b-61b7-4fb2-a1df-635747c97d5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438238354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3438238354
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1612229222
Short name T300
Test name
Test status
Simulation time 508484837 ps
CPU time 1.25 seconds
Started Aug 12 04:21:07 PM PDT 24
Finished Aug 12 04:21:09 PM PDT 24
Peak memory 183408 kb
Host smart-5832f14e-fd22-4022-be19-82532a8fabb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612229222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1612229222
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1874316805
Short name T61
Test name
Test status
Simulation time 2219387609 ps
CPU time 1.43 seconds
Started Aug 12 04:21:05 PM PDT 24
Finished Aug 12 04:21:07 PM PDT 24
Peak memory 192312 kb
Host smart-0913973f-3487-41f6-b2ff-2759e008fafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874316805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1874316805
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3335362613
Short name T322
Test name
Test status
Simulation time 538964751 ps
CPU time 2.45 seconds
Started Aug 12 04:21:04 PM PDT 24
Finished Aug 12 04:21:06 PM PDT 24
Peak memory 197648 kb
Host smart-0504f980-c6d3-46af-81ad-83551bc64912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335362613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3335362613
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.608321109
Short name T317
Test name
Test status
Simulation time 4042638757 ps
CPU time 6.9 seconds
Started Aug 12 04:21:05 PM PDT 24
Finished Aug 12 04:21:12 PM PDT 24
Peak memory 197532 kb
Host smart-6ddedfd6-9662-4e1f-b1f6-d416172e8131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608321109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.608321109
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2372859444
Short name T56
Test name
Test status
Simulation time 468702627 ps
CPU time 1.51 seconds
Started Aug 12 04:21:16 PM PDT 24
Finished Aug 12 04:21:17 PM PDT 24
Peak memory 183420 kb
Host smart-921e7bb2-d179-43de-8712-a76432342b5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372859444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2372859444
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3634583286
Short name T303
Test name
Test status
Simulation time 7333320516 ps
CPU time 16.01 seconds
Started Aug 12 04:24:25 PM PDT 24
Finished Aug 12 04:24:41 PM PDT 24
Peak memory 192244 kb
Host smart-9ad6292a-cee4-4930-a6d4-26cc8df1d945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634583286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3634583286
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.112132132
Short name T395
Test name
Test status
Simulation time 838869730 ps
CPU time 1.7 seconds
Started Aug 12 04:24:21 PM PDT 24
Finished Aug 12 04:24:22 PM PDT 24
Peak memory 183760 kb
Host smart-947d178f-b8ab-4bde-9b0d-a2e07f367de2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112132132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.112132132
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2476979789
Short name T289
Test name
Test status
Simulation time 478131285 ps
CPU time 1.41 seconds
Started Aug 12 04:22:31 PM PDT 24
Finished Aug 12 04:22:32 PM PDT 24
Peak memory 195752 kb
Host smart-b553348f-3ad8-4a7b-ab70-d21d6b6f4886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476979789 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2476979789
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3435491745
Short name T79
Test name
Test status
Simulation time 486671917 ps
CPU time 0.92 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:15 PM PDT 24
Peak memory 191812 kb
Host smart-cfa518b3-dc40-4c6e-a1d9-4b46c564910b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435491745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3435491745
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3692969985
Short name T316
Test name
Test status
Simulation time 525148841 ps
CPU time 0.74 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:15 PM PDT 24
Peak memory 182508 kb
Host smart-d38ac272-09d9-469b-b8b3-14fa8a977659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692969985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3692969985
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1317250604
Short name T301
Test name
Test status
Simulation time 418860836 ps
CPU time 0.67 seconds
Started Aug 12 04:22:47 PM PDT 24
Finished Aug 12 04:22:48 PM PDT 24
Peak memory 183640 kb
Host smart-58862417-2817-45e0-be81-8685ad0051c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317250604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1317250604
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.375341887
Short name T415
Test name
Test status
Simulation time 303027604 ps
CPU time 0.97 seconds
Started Aug 12 04:26:14 PM PDT 24
Finished Aug 12 04:26:16 PM PDT 24
Peak memory 183200 kb
Host smart-a6192e09-2c04-49a8-b5b4-13e0e67b828f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375341887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.375341887
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2031244754
Short name T360
Test name
Test status
Simulation time 1590676126 ps
CPU time 1.68 seconds
Started Aug 12 04:23:01 PM PDT 24
Finished Aug 12 04:23:02 PM PDT 24
Peak memory 193272 kb
Host smart-ac6fb4f8-3651-42b9-bb15-def4bd921568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031244754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2031244754
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1442429457
Short name T392
Test name
Test status
Simulation time 491909554 ps
CPU time 2.33 seconds
Started Aug 12 04:21:00 PM PDT 24
Finished Aug 12 04:21:02 PM PDT 24
Peak memory 197712 kb
Host smart-ea9293fe-5b3a-4773-b50b-ebe3c2f3ed5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442429457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1442429457
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2032918578
Short name T351
Test name
Test status
Simulation time 4094668767 ps
CPU time 6.55 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:07 PM PDT 24
Peak memory 197640 kb
Host smart-bc0dc69f-03e1-4cbb-819f-ae53e38cef01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032918578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2032918578
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.936372081
Short name T422
Test name
Test status
Simulation time 404998580 ps
CPU time 1.35 seconds
Started Aug 12 04:25:40 PM PDT 24
Finished Aug 12 04:25:41 PM PDT 24
Peak memory 196712 kb
Host smart-d0fbe7b0-7680-40b4-8e5c-99903c98c229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936372081 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.936372081
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1434644012
Short name T387
Test name
Test status
Simulation time 498395019 ps
CPU time 0.82 seconds
Started Aug 12 04:26:45 PM PDT 24
Finished Aug 12 04:26:46 PM PDT 24
Peak memory 194008 kb
Host smart-573c868b-d534-459f-9f99-d51177160c3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434644012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1434644012
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.915837666
Short name T331
Test name
Test status
Simulation time 422348879 ps
CPU time 1.22 seconds
Started Aug 12 04:25:37 PM PDT 24
Finished Aug 12 04:25:39 PM PDT 24
Peak memory 183620 kb
Host smart-4762433d-1f96-4090-8fd0-df0ebc5edb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915837666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.915837666
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1511725717
Short name T391
Test name
Test status
Simulation time 1048915925 ps
CPU time 1.15 seconds
Started Aug 12 04:25:48 PM PDT 24
Finished Aug 12 04:25:49 PM PDT 24
Peak memory 194008 kb
Host smart-fc94d973-f77a-458b-9601-8dda3189f714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511725717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1511725717
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.670741878
Short name T409
Test name
Test status
Simulation time 491076727 ps
CPU time 2.07 seconds
Started Aug 12 04:27:14 PM PDT 24
Finished Aug 12 04:27:17 PM PDT 24
Peak memory 198560 kb
Host smart-ccdf072a-f82f-42db-8807-2019804cc9ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670741878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.670741878
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.399758638
Short name T374
Test name
Test status
Simulation time 4346504861 ps
CPU time 3.84 seconds
Started Aug 12 04:26:57 PM PDT 24
Finished Aug 12 04:27:01 PM PDT 24
Peak memory 197648 kb
Host smart-0a965bfc-926d-401c-84eb-7069a08e8445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399758638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.399758638
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1821100891
Short name T403
Test name
Test status
Simulation time 648043437 ps
CPU time 1.14 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:25:48 PM PDT 24
Peak memory 198328 kb
Host smart-66ad3040-1f15-4039-be2b-596e0a135d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821100891 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1821100891
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3027641698
Short name T311
Test name
Test status
Simulation time 323417741 ps
CPU time 0.6 seconds
Started Aug 12 04:25:36 PM PDT 24
Finished Aug 12 04:25:37 PM PDT 24
Peak memory 183660 kb
Host smart-44636fa9-b473-4786-94a8-a3a491fb14ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027641698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3027641698
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2862694160
Short name T59
Test name
Test status
Simulation time 1514485999 ps
CPU time 1.06 seconds
Started Aug 12 04:25:41 PM PDT 24
Finished Aug 12 04:25:42 PM PDT 24
Peak memory 192252 kb
Host smart-ff5cfe89-9958-44d2-87fd-4cb2f7550910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862694160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2862694160
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1215466000
Short name T323
Test name
Test status
Simulation time 511698242 ps
CPU time 1.8 seconds
Started Aug 12 04:25:36 PM PDT 24
Finished Aug 12 04:25:38 PM PDT 24
Peak memory 198680 kb
Host smart-0d9c6ec8-6f19-4969-b918-bd87f0422b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215466000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1215466000
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.303237048
Short name T413
Test name
Test status
Simulation time 4384742968 ps
CPU time 2.72 seconds
Started Aug 12 04:25:40 PM PDT 24
Finished Aug 12 04:25:43 PM PDT 24
Peak memory 197848 kb
Host smart-eb6c0c54-bf1c-466f-bf3f-bd87ea7d235a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303237048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.303237048
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1071738726
Short name T304
Test name
Test status
Simulation time 392786356 ps
CPU time 0.95 seconds
Started Aug 12 04:25:47 PM PDT 24
Finished Aug 12 04:25:48 PM PDT 24
Peak memory 196868 kb
Host smart-f0c62931-83fe-40b4-b276-53b5ae63a19e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071738726 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1071738726
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2753933930
Short name T416
Test name
Test status
Simulation time 344684038 ps
CPU time 1.04 seconds
Started Aug 12 04:25:45 PM PDT 24
Finished Aug 12 04:25:46 PM PDT 24
Peak memory 192996 kb
Host smart-d27748a3-9a84-43d8-bfbc-82d89c3b2f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753933930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2753933930
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1651000275
Short name T419
Test name
Test status
Simulation time 445897879 ps
CPU time 1.17 seconds
Started Aug 12 04:25:42 PM PDT 24
Finished Aug 12 04:25:43 PM PDT 24
Peak memory 192960 kb
Host smart-619f6fee-e6dd-4470-82ad-1f1f88a86d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651000275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1651000275
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2981718919
Short name T411
Test name
Test status
Simulation time 1408105063 ps
CPU time 2.9 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:49 PM PDT 24
Peak memory 193988 kb
Host smart-90b33da9-23f0-4811-a502-e094ca6baec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981718919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2981718919
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2763969558
Short name T314
Test name
Test status
Simulation time 388488901 ps
CPU time 1.82 seconds
Started Aug 12 04:25:44 PM PDT 24
Finished Aug 12 04:25:46 PM PDT 24
Peak memory 198568 kb
Host smart-afa32b0d-24da-48ca-9de5-553405be8885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763969558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2763969558
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.710408356
Short name T397
Test name
Test status
Simulation time 8745102487 ps
CPU time 2.34 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:48 PM PDT 24
Peak memory 198216 kb
Host smart-f8000c1d-4401-467b-9688-f1c6c6b6b37a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710408356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.710408356
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1963999955
Short name T339
Test name
Test status
Simulation time 610768055 ps
CPU time 1.1 seconds
Started Aug 12 04:25:45 PM PDT 24
Finished Aug 12 04:25:46 PM PDT 24
Peak memory 198416 kb
Host smart-8521cf75-3c49-40f9-843e-2c88b289c638
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963999955 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1963999955
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3004483890
Short name T401
Test name
Test status
Simulation time 411119399 ps
CPU time 1.17 seconds
Started Aug 12 04:27:19 PM PDT 24
Finished Aug 12 04:27:21 PM PDT 24
Peak memory 191148 kb
Host smart-07d74724-45df-43b3-97c9-c3dcda899871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004483890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3004483890
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2684804056
Short name T386
Test name
Test status
Simulation time 291456797 ps
CPU time 0.76 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:47 PM PDT 24
Peak memory 183652 kb
Host smart-63f74cf5-ffb6-4867-9845-099ee6335d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684804056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2684804056
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.732680564
Short name T405
Test name
Test status
Simulation time 1078892852 ps
CPU time 2.78 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:49 PM PDT 24
Peak memory 193452 kb
Host smart-9d3dcb06-9b90-451d-824b-5b8eaa8bb813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732680564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.732680564
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.551195820
Short name T379
Test name
Test status
Simulation time 366783918 ps
CPU time 1.34 seconds
Started Aug 12 04:25:45 PM PDT 24
Finished Aug 12 04:25:47 PM PDT 24
Peak memory 198644 kb
Host smart-f802437a-e7a4-41ae-a3f9-b57937bc7e11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551195820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.551195820
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3747532617
Short name T414
Test name
Test status
Simulation time 4642836696 ps
CPU time 2.79 seconds
Started Aug 12 04:26:57 PM PDT 24
Finished Aug 12 04:27:00 PM PDT 24
Peak memory 197592 kb
Host smart-74a58aca-a80f-4fc4-b90a-d0178523f8dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747532617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3747532617
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.848050815
Short name T340
Test name
Test status
Simulation time 529116058 ps
CPU time 1.56 seconds
Started Aug 12 04:25:59 PM PDT 24
Finished Aug 12 04:26:00 PM PDT 24
Peak memory 196824 kb
Host smart-b8c3e1ce-e87d-4d44-9250-f71bf8ce2215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848050815 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.848050815
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1881103619
Short name T389
Test name
Test status
Simulation time 484119640 ps
CPU time 0.86 seconds
Started Aug 12 04:25:57 PM PDT 24
Finished Aug 12 04:25:58 PM PDT 24
Peak memory 193924 kb
Host smart-0de37913-c91b-4877-93e5-bb2d8f7b8f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881103619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1881103619
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3314621495
Short name T348
Test name
Test status
Simulation time 459032115 ps
CPU time 0.96 seconds
Started Aug 12 04:25:54 PM PDT 24
Finished Aug 12 04:25:55 PM PDT 24
Peak memory 192916 kb
Host smart-e0bfc2e0-e80e-4fb3-895a-987658edec73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314621495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3314621495
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1143870910
Short name T60
Test name
Test status
Simulation time 1815708203 ps
CPU time 2.71 seconds
Started Aug 12 04:27:11 PM PDT 24
Finished Aug 12 04:27:14 PM PDT 24
Peak memory 193628 kb
Host smart-1ac36808-ecb0-43d3-8771-600e24034381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143870910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1143870910
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4253513182
Short name T308
Test name
Test status
Simulation time 482509532 ps
CPU time 2.06 seconds
Started Aug 12 04:26:56 PM PDT 24
Finished Aug 12 04:26:59 PM PDT 24
Peak memory 198584 kb
Host smart-5cdf7303-1e95-4e7d-b3b3-432cd5c54720
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253513182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4253513182
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2488805292
Short name T417
Test name
Test status
Simulation time 539970752 ps
CPU time 1.52 seconds
Started Aug 12 04:26:05 PM PDT 24
Finished Aug 12 04:26:06 PM PDT 24
Peak memory 195844 kb
Host smart-c5e72fdd-b3b3-48b9-bc7c-c66da15efeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488805292 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2488805292
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1556007923
Short name T46
Test name
Test status
Simulation time 532426970 ps
CPU time 0.81 seconds
Started Aug 12 04:26:03 PM PDT 24
Finished Aug 12 04:26:03 PM PDT 24
Peak memory 192312 kb
Host smart-20d0a4c0-6878-4a1e-b750-d95a3d409b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556007923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1556007923
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2238330906
Short name T293
Test name
Test status
Simulation time 442359495 ps
CPU time 1.23 seconds
Started Aug 12 04:26:06 PM PDT 24
Finished Aug 12 04:26:07 PM PDT 24
Peak memory 183716 kb
Host smart-a975413f-946e-4373-95a6-6803646ab980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238330906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2238330906
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3547483312
Short name T390
Test name
Test status
Simulation time 2548516071 ps
CPU time 2.22 seconds
Started Aug 12 04:25:59 PM PDT 24
Finished Aug 12 04:26:02 PM PDT 24
Peak memory 195160 kb
Host smart-fb58ba08-e538-445a-bb3b-cfebcf3d3a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547483312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3547483312
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1444113549
Short name T393
Test name
Test status
Simulation time 463609258 ps
CPU time 2.07 seconds
Started Aug 12 04:26:09 PM PDT 24
Finished Aug 12 04:26:12 PM PDT 24
Peak memory 198576 kb
Host smart-82b72ca5-611b-46a5-b2f7-8185a010613e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444113549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1444113549
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1224869839
Short name T321
Test name
Test status
Simulation time 4553030661 ps
CPU time 4.3 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:05 PM PDT 24
Peak memory 197576 kb
Host smart-0b359345-b680-4b54-aa73-99f9c5c1f7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224869839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1224869839
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4114849684
Short name T384
Test name
Test status
Simulation time 536309231 ps
CPU time 0.89 seconds
Started Aug 12 04:26:11 PM PDT 24
Finished Aug 12 04:26:12 PM PDT 24
Peak memory 196780 kb
Host smart-336e77ff-a20f-4a6b-afdf-9812ab459b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114849684 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4114849684
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1015665149
Short name T76
Test name
Test status
Simulation time 434242892 ps
CPU time 0.71 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:00 PM PDT 24
Peak memory 192932 kb
Host smart-98669e33-8530-49de-9038-053ae1884f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015665149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1015665149
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.286528123
Short name T412
Test name
Test status
Simulation time 530392310 ps
CPU time 0.73 seconds
Started Aug 12 04:26:04 PM PDT 24
Finished Aug 12 04:26:05 PM PDT 24
Peak memory 183620 kb
Host smart-b39d16fe-9577-4e13-ab1a-bed6e8f197d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286528123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.286528123
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1599141050
Short name T375
Test name
Test status
Simulation time 2619392181 ps
CPU time 1.31 seconds
Started Aug 12 04:26:12 PM PDT 24
Finished Aug 12 04:26:13 PM PDT 24
Peak memory 193804 kb
Host smart-c30c8c9a-cf86-4135-96de-e91bbdef07b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599141050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1599141050
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1772011747
Short name T287
Test name
Test status
Simulation time 508539975 ps
CPU time 1.58 seconds
Started Aug 12 04:26:03 PM PDT 24
Finished Aug 12 04:26:04 PM PDT 24
Peak memory 197688 kb
Host smart-f1ab59b2-96a2-4bd0-89f8-448330cd7d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772011747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1772011747
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1360708283
Short name T35
Test name
Test status
Simulation time 8578563884 ps
CPU time 7.14 seconds
Started Aug 12 04:26:03 PM PDT 24
Finished Aug 12 04:26:10 PM PDT 24
Peak memory 197392 kb
Host smart-89602d3b-7b8f-4774-a528-dbeee3d7d503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360708283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1360708283
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1358923246
Short name T398
Test name
Test status
Simulation time 512957613 ps
CPU time 1.13 seconds
Started Aug 12 04:26:12 PM PDT 24
Finished Aug 12 04:26:14 PM PDT 24
Peak memory 198320 kb
Host smart-3714bbae-e36d-4287-b441-2608eb7af2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358923246 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1358923246
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.790258490
Short name T74
Test name
Test status
Simulation time 442995432 ps
CPU time 0.96 seconds
Started Aug 12 04:26:12 PM PDT 24
Finished Aug 12 04:26:13 PM PDT 24
Peak memory 192916 kb
Host smart-84cfe285-a7c7-48e1-932a-f351e7f94848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790258490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.790258490
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2995548613
Short name T291
Test name
Test status
Simulation time 427056616 ps
CPU time 0.72 seconds
Started Aug 12 04:26:10 PM PDT 24
Finished Aug 12 04:26:11 PM PDT 24
Peak memory 183660 kb
Host smart-a44bc94f-f894-479c-9184-57f1b60be1ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995548613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2995548613
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2054100001
Short name T423
Test name
Test status
Simulation time 1412666387 ps
CPU time 1.22 seconds
Started Aug 12 04:26:10 PM PDT 24
Finished Aug 12 04:26:11 PM PDT 24
Peak memory 192236 kb
Host smart-79cc2c9b-b6ce-4b17-8a2d-eb959011f96d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054100001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2054100001
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2296564163
Short name T309
Test name
Test status
Simulation time 782191471 ps
CPU time 2.44 seconds
Started Aug 12 04:26:08 PM PDT 24
Finished Aug 12 04:26:11 PM PDT 24
Peak memory 198696 kb
Host smart-a3dcd73e-86e5-487e-8741-f6cf95e09cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296564163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2296564163
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1938847894
Short name T361
Test name
Test status
Simulation time 640050151 ps
CPU time 0.78 seconds
Started Aug 12 04:27:26 PM PDT 24
Finished Aug 12 04:27:27 PM PDT 24
Peak memory 196692 kb
Host smart-eddd06ed-bca6-418a-9626-24273e60ed27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938847894 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1938847894
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3995237308
Short name T55
Test name
Test status
Simulation time 324349130 ps
CPU time 1.11 seconds
Started Aug 12 04:26:08 PM PDT 24
Finished Aug 12 04:26:09 PM PDT 24
Peak memory 193268 kb
Host smart-04fcdfb7-6f6b-48d4-a078-5b758400c63b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995237308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3995237308
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2373026131
Short name T350
Test name
Test status
Simulation time 468503470 ps
CPU time 1.22 seconds
Started Aug 12 04:26:09 PM PDT 24
Finished Aug 12 04:26:11 PM PDT 24
Peak memory 192880 kb
Host smart-f5ee037a-ad60-4b1e-a943-841f992eed85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373026131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2373026131
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3078921477
Short name T58
Test name
Test status
Simulation time 1874982592 ps
CPU time 3.25 seconds
Started Aug 12 04:26:10 PM PDT 24
Finished Aug 12 04:26:14 PM PDT 24
Peak memory 193900 kb
Host smart-14a32b4f-664a-49b7-a4e1-7e93131bee67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078921477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3078921477
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2350383422
Short name T347
Test name
Test status
Simulation time 660895660 ps
CPU time 2.12 seconds
Started Aug 12 04:27:28 PM PDT 24
Finished Aug 12 04:27:30 PM PDT 24
Peak memory 198528 kb
Host smart-69dbe30f-2032-4bba-9576-7dd6aaa53377
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350383422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2350383422
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2537837512
Short name T194
Test name
Test status
Simulation time 4377964470 ps
CPU time 2.1 seconds
Started Aug 12 04:27:09 PM PDT 24
Finished Aug 12 04:27:11 PM PDT 24
Peak memory 196492 kb
Host smart-e6564c73-eb62-4853-8122-141f08972c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537837512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2537837512
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.618903312
Short name T336
Test name
Test status
Simulation time 520262319 ps
CPU time 1.43 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:20 PM PDT 24
Peak memory 196788 kb
Host smart-42f2f4bc-3e3b-48f1-b34f-913c9c872c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618903312 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.618903312
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3011481864
Short name T77
Test name
Test status
Simulation time 552956690 ps
CPU time 0.8 seconds
Started Aug 12 04:26:19 PM PDT 24
Finished Aug 12 04:26:20 PM PDT 24
Peak memory 191960 kb
Host smart-7fa513e0-2df0-40ab-9032-3589526f204a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011481864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3011481864
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4136906927
Short name T371
Test name
Test status
Simulation time 434765226 ps
CPU time 0.88 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:19 PM PDT 24
Peak memory 183416 kb
Host smart-8e7e4da0-7527-40ec-8ab6-ba86506206af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136906927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4136906927
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1881024253
Short name T62
Test name
Test status
Simulation time 2144421840 ps
CPU time 5.98 seconds
Started Aug 12 04:26:23 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 195012 kb
Host smart-63b97d0c-ea5d-4e7a-93de-629df7b0aa76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881024253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1881024253
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4193806293
Short name T305
Test name
Test status
Simulation time 414940648 ps
CPU time 2.2 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:26:20 PM PDT 24
Peak memory 198628 kb
Host smart-d3bb103c-4def-4334-9f65-4a139f8f46f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193806293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4193806293
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3710405188
Short name T326
Test name
Test status
Simulation time 707819800 ps
CPU time 1.14 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 194336 kb
Host smart-15c0eb90-c546-440a-af94-2bf5d6a5eb01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710405188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3710405188
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2404938375
Short name T52
Test name
Test status
Simulation time 12387710087 ps
CPU time 9.72 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:10 PM PDT 24
Peak memory 192080 kb
Host smart-7ced6136-f4e0-4768-9144-9a4358b12540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404938375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2404938375
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2557028237
Short name T47
Test name
Test status
Simulation time 729985311 ps
CPU time 1.07 seconds
Started Aug 12 04:23:03 PM PDT 24
Finished Aug 12 04:23:04 PM PDT 24
Peak memory 192100 kb
Host smart-bd7c1de6-493c-4377-b7e7-ddce68d321d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557028237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2557028237
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3126801302
Short name T372
Test name
Test status
Simulation time 589600968 ps
CPU time 0.92 seconds
Started Aug 12 04:26:55 PM PDT 24
Finished Aug 12 04:26:56 PM PDT 24
Peak memory 197112 kb
Host smart-ef3d0269-c9cf-400d-a542-45d6e81925b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126801302 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3126801302
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.536429885
Short name T425
Test name
Test status
Simulation time 324421089 ps
CPU time 0.8 seconds
Started Aug 12 04:22:18 PM PDT 24
Finished Aug 12 04:22:19 PM PDT 24
Peak memory 192596 kb
Host smart-41bbf3a6-2187-46f7-a705-67f121187983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536429885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.536429885
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3402066543
Short name T306
Test name
Test status
Simulation time 375878879 ps
CPU time 0.69 seconds
Started Aug 12 04:22:25 PM PDT 24
Finished Aug 12 04:22:26 PM PDT 24
Peak memory 192536 kb
Host smart-f9c751f2-acfa-441b-8588-607b4deefae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402066543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3402066543
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3401831902
Short name T355
Test name
Test status
Simulation time 296589516 ps
CPU time 0.92 seconds
Started Aug 12 04:22:25 PM PDT 24
Finished Aug 12 04:22:26 PM PDT 24
Peak memory 183292 kb
Host smart-096475b7-49b4-449d-b725-9398cf316c13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401831902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3401831902
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1111741582
Short name T370
Test name
Test status
Simulation time 436994279 ps
CPU time 0.74 seconds
Started Aug 12 04:22:17 PM PDT 24
Finished Aug 12 04:22:19 PM PDT 24
Peak memory 182660 kb
Host smart-1b8dfd73-61b4-451d-8d58-e0b2ab80bb95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111741582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1111741582
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3595417518
Short name T57
Test name
Test status
Simulation time 1126346703 ps
CPU time 3.7 seconds
Started Aug 12 04:27:50 PM PDT 24
Finished Aug 12 04:27:54 PM PDT 24
Peak memory 193344 kb
Host smart-b2fd23de-6e34-4ecf-a28e-679d9164b2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595417518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3595417518
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.611937639
Short name T307
Test name
Test status
Simulation time 1005925654 ps
CPU time 1.75 seconds
Started Aug 12 04:21:52 PM PDT 24
Finished Aug 12 04:21:54 PM PDT 24
Peak memory 198644 kb
Host smart-6ca73b75-8a8a-4924-aa52-8dc5817675db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611937639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.611937639
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3648761403
Short name T383
Test name
Test status
Simulation time 8649708692 ps
CPU time 7.01 seconds
Started Aug 12 04:22:29 PM PDT 24
Finished Aug 12 04:22:36 PM PDT 24
Peak memory 198288 kb
Host smart-2f189ac8-3f29-4fc4-af14-4c257b979bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648761403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3648761403
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2709540715
Short name T410
Test name
Test status
Simulation time 452385265 ps
CPU time 1.25 seconds
Started Aug 12 04:27:26 PM PDT 24
Finished Aug 12 04:27:27 PM PDT 24
Peak memory 183612 kb
Host smart-fbd1e0ed-859a-4950-af6f-863bc548d6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709540715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2709540715
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.670624545
Short name T334
Test name
Test status
Simulation time 459627672 ps
CPU time 0.73 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:26:18 PM PDT 24
Peak memory 183740 kb
Host smart-0b440df9-70e0-43ec-a087-7ef117c13c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670624545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.670624545
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2006120570
Short name T294
Test name
Test status
Simulation time 382414115 ps
CPU time 1.12 seconds
Started Aug 12 04:27:26 PM PDT 24
Finished Aug 12 04:27:27 PM PDT 24
Peak memory 183612 kb
Host smart-17585e00-d2d5-41c6-9946-d782573b2d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006120570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2006120570
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2827765613
Short name T324
Test name
Test status
Simulation time 388479421 ps
CPU time 0.78 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:19 PM PDT 24
Peak memory 183392 kb
Host smart-93ae2d67-0de8-44ec-984d-b5eccad8fa94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827765613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2827765613
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1543983372
Short name T328
Test name
Test status
Simulation time 495762859 ps
CPU time 0.92 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 192852 kb
Host smart-d6f86ee0-7733-41eb-be90-560049a81257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543983372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1543983372
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3190015702
Short name T396
Test name
Test status
Simulation time 369464947 ps
CPU time 1.17 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 183696 kb
Host smart-6bffc0d5-d8b9-4fe4-aa7a-d7a4f59fba67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190015702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3190015702
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.34206295
Short name T377
Test name
Test status
Simulation time 332060837 ps
CPU time 0.67 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 183664 kb
Host smart-97a48423-00e4-44c6-867a-9b4911672b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.34206295
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.308376320
Short name T368
Test name
Test status
Simulation time 398547909 ps
CPU time 0.71 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 192916 kb
Host smart-7e875d35-22d1-4958-9a47-11fe39aa8543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308376320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.308376320
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4176074465
Short name T333
Test name
Test status
Simulation time 499213823 ps
CPU time 0.9 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 192876 kb
Host smart-85733b78-83b5-4fe0-a002-4f391e8a3dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176074465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4176074465
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2311551686
Short name T367
Test name
Test status
Simulation time 473917085 ps
CPU time 0.74 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 192936 kb
Host smart-a6a6432c-de6b-48e3-a2e7-a8c5d88663c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311551686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2311551686
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2347213176
Short name T345
Test name
Test status
Simulation time 761004578 ps
CPU time 1.02 seconds
Started Aug 12 04:26:00 PM PDT 24
Finished Aug 12 04:26:02 PM PDT 24
Peak memory 193708 kb
Host smart-b4f757a3-0ff0-4382-86d0-4edcaab495b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347213176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2347213176
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3190554369
Short name T48
Test name
Test status
Simulation time 3739051073 ps
CPU time 10.77 seconds
Started Aug 12 04:23:15 PM PDT 24
Finished Aug 12 04:23:26 PM PDT 24
Peak memory 192208 kb
Host smart-a723c212-25c4-423b-b930-b687b319ba04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190554369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3190554369
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2423914436
Short name T341
Test name
Test status
Simulation time 663236900 ps
CPU time 0.82 seconds
Started Aug 12 04:24:16 PM PDT 24
Finished Aug 12 04:24:17 PM PDT 24
Peak memory 183716 kb
Host smart-a8a2bfff-7664-4d2a-adcf-ecbb248c7b07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423914436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2423914436
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1234500697
Short name T359
Test name
Test status
Simulation time 409128269 ps
CPU time 0.95 seconds
Started Aug 12 04:26:32 PM PDT 24
Finished Aug 12 04:26:33 PM PDT 24
Peak memory 196244 kb
Host smart-9e726858-87f2-42e9-8ee4-6f1f6e2592fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234500697 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1234500697
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4091241121
Short name T75
Test name
Test status
Simulation time 328059904 ps
CPU time 0.83 seconds
Started Aug 12 04:23:14 PM PDT 24
Finished Aug 12 04:23:15 PM PDT 24
Peak memory 192072 kb
Host smart-2612c3d8-b4b8-4186-a115-78ab1f5901a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091241121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4091241121
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2805634059
Short name T318
Test name
Test status
Simulation time 496925066 ps
CPU time 1.35 seconds
Started Aug 12 04:27:34 PM PDT 24
Finished Aug 12 04:27:36 PM PDT 24
Peak memory 182656 kb
Host smart-8a475ca4-0b13-4820-a660-78a9e3be23ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805634059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2805634059
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1006282094
Short name T399
Test name
Test status
Simulation time 461618349 ps
CPU time 1.26 seconds
Started Aug 12 04:23:04 PM PDT 24
Finished Aug 12 04:23:05 PM PDT 24
Peak memory 183688 kb
Host smart-6df566fa-1bcd-436f-9f2c-ed3541450b49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006282094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1006282094
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1200204195
Short name T313
Test name
Test status
Simulation time 404088613 ps
CPU time 0.66 seconds
Started Aug 12 04:22:08 PM PDT 24
Finished Aug 12 04:22:09 PM PDT 24
Peak memory 183660 kb
Host smart-e41bf6b2-1495-4b43-b39f-248adb0694f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200204195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1200204195
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1420980425
Short name T357
Test name
Test status
Simulation time 2287209718 ps
CPU time 1.38 seconds
Started Aug 12 04:21:48 PM PDT 24
Finished Aug 12 04:21:49 PM PDT 24
Peak memory 194856 kb
Host smart-35092243-fadc-4b6b-85bf-8f10d7fc6f8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420980425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1420980425
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.469825593
Short name T329
Test name
Test status
Simulation time 1768018359 ps
CPU time 1.74 seconds
Started Aug 12 04:23:27 PM PDT 24
Finished Aug 12 04:23:29 PM PDT 24
Peak memory 198576 kb
Host smart-106dd7ab-ec09-4a2d-b365-c778de5bb19f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469825593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.469825593
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1866227249
Short name T330
Test name
Test status
Simulation time 7878219145 ps
CPU time 11.89 seconds
Started Aug 12 04:23:46 PM PDT 24
Finished Aug 12 04:23:58 PM PDT 24
Peak memory 198256 kb
Host smart-c4263bd5-18cf-4568-b690-1a189b0cb07f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866227249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1866227249
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2780736234
Short name T353
Test name
Test status
Simulation time 332038214 ps
CPU time 1.03 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 183716 kb
Host smart-9a66e99a-d7b3-426b-8a50-37393fc5473b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780736234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2780736234
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.79620063
Short name T404
Test name
Test status
Simulation time 497147371 ps
CPU time 0.93 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 183656 kb
Host smart-6b90bdbe-ba63-49d6-af90-cb064f188828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79620063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.79620063
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3989413618
Short name T312
Test name
Test status
Simulation time 350234472 ps
CPU time 0.87 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 183740 kb
Host smart-1ef67781-13f5-4c69-b8a2-53604595c09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989413618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3989413618
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.479577990
Short name T285
Test name
Test status
Simulation time 334862748 ps
CPU time 1.13 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 183716 kb
Host smart-aefeb493-5881-434f-a39b-30b2f4312ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479577990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.479577990
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.514468297
Short name T363
Test name
Test status
Simulation time 364094397 ps
CPU time 0.6 seconds
Started Aug 12 04:26:52 PM PDT 24
Finished Aug 12 04:26:53 PM PDT 24
Peak memory 192848 kb
Host smart-1c5e4784-9937-4bf9-86f9-c8442304c4da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514468297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.514468297
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.481925800
Short name T394
Test name
Test status
Simulation time 398437728 ps
CPU time 1.13 seconds
Started Aug 12 04:27:15 PM PDT 24
Finished Aug 12 04:27:16 PM PDT 24
Peak memory 183712 kb
Host smart-a509ba12-8459-44de-b0d6-a2abc0070c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481925800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.481925800
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1536352671
Short name T288
Test name
Test status
Simulation time 317300189 ps
CPU time 0.68 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 183652 kb
Host smart-692ff7ce-7fe6-4625-8e8c-0a260014288e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536352671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1536352671
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3181618055
Short name T327
Test name
Test status
Simulation time 405120174 ps
CPU time 1.17 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 192784 kb
Host smart-4a9eb866-b713-49cf-880a-1b58d1a584a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181618055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3181618055
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1365179888
Short name T352
Test name
Test status
Simulation time 360827980 ps
CPU time 0.86 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 183716 kb
Host smart-23de9e11-b2dc-4f38-8e41-d6f269bb89a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365179888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1365179888
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1393451786
Short name T421
Test name
Test status
Simulation time 508987569 ps
CPU time 0.69 seconds
Started Aug 12 04:26:26 PM PDT 24
Finished Aug 12 04:26:27 PM PDT 24
Peak memory 192884 kb
Host smart-0dad1160-0af6-4551-b28f-7eb4cf078683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393451786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1393451786
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1710643921
Short name T54
Test name
Test status
Simulation time 430189568 ps
CPU time 0.78 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:34 PM PDT 24
Peak memory 193020 kb
Host smart-20fd155e-6912-4237-bbcc-a6cc95726b81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710643921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1710643921
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1578641497
Short name T53
Test name
Test status
Simulation time 10115140425 ps
CPU time 24.36 seconds
Started Aug 12 04:25:02 PM PDT 24
Finished Aug 12 04:25:27 PM PDT 24
Peak memory 184044 kb
Host smart-8e2d0caa-46f5-4053-a935-03f2bc84ebcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578641497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1578641497
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3627946088
Short name T51
Test name
Test status
Simulation time 1114236106 ps
CPU time 0.7 seconds
Started Aug 12 04:26:17 PM PDT 24
Finished Aug 12 04:26:18 PM PDT 24
Peak memory 183244 kb
Host smart-db809a4e-cc58-4d50-9c27-ec766ad85186
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627946088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3627946088
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2390098935
Short name T337
Test name
Test status
Simulation time 533652129 ps
CPU time 0.81 seconds
Started Aug 12 04:25:04 PM PDT 24
Finished Aug 12 04:25:05 PM PDT 24
Peak memory 196580 kb
Host smart-8b55f16a-875a-4e00-aeb9-271c1b1d8b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390098935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2390098935
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4071813330
Short name T78
Test name
Test status
Simulation time 433859651 ps
CPU time 0.76 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:47 PM PDT 24
Peak memory 193444 kb
Host smart-78940dea-b887-4978-b83c-8894f1cfe695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071813330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4071813330
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3800898012
Short name T310
Test name
Test status
Simulation time 291040960 ps
CPU time 0.69 seconds
Started Aug 12 04:24:40 PM PDT 24
Finished Aug 12 04:24:41 PM PDT 24
Peak memory 192852 kb
Host smart-01c5ac71-431a-4896-adab-329fa70cabf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800898012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3800898012
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3761650280
Short name T286
Test name
Test status
Simulation time 351627372 ps
CPU time 0.66 seconds
Started Aug 12 04:25:44 PM PDT 24
Finished Aug 12 04:25:46 PM PDT 24
Peak memory 182332 kb
Host smart-18241a4f-b9aa-4cd0-801b-c94c81166888
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761650280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3761650280
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3106891012
Short name T346
Test name
Test status
Simulation time 367969647 ps
CPU time 1.03 seconds
Started Aug 12 04:24:52 PM PDT 24
Finished Aug 12 04:24:53 PM PDT 24
Peak memory 183644 kb
Host smart-b8156c70-26eb-4257-be22-9de0c2d79a35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106891012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3106891012
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4050244082
Short name T364
Test name
Test status
Simulation time 1262352461 ps
CPU time 2.05 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 182964 kb
Host smart-20ccf415-3665-4e74-b924-20b54cd25bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050244082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4050244082
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3722407200
Short name T358
Test name
Test status
Simulation time 530946940 ps
CPU time 1.52 seconds
Started Aug 12 04:25:44 PM PDT 24
Finished Aug 12 04:25:46 PM PDT 24
Peak memory 197336 kb
Host smart-f2b15ef2-1675-458c-aa6b-ecab31622877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722407200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3722407200
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.401679463
Short name T38
Test name
Test status
Simulation time 8319182686 ps
CPU time 7.6 seconds
Started Aug 12 04:21:57 PM PDT 24
Finished Aug 12 04:22:04 PM PDT 24
Peak memory 197936 kb
Host smart-b710957d-9f8a-4b02-b239-68ad307c64a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401679463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.401679463
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4108577679
Short name T385
Test name
Test status
Simulation time 303766758 ps
CPU time 0.77 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:29 PM PDT 24
Peak memory 192936 kb
Host smart-6fd5859c-2110-4067-b92b-b95817de7746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108577679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4108577679
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3302815175
Short name T362
Test name
Test status
Simulation time 443378334 ps
CPU time 1.21 seconds
Started Aug 12 04:26:42 PM PDT 24
Finished Aug 12 04:26:44 PM PDT 24
Peak memory 183716 kb
Host smart-d5a2f713-3a29-48c2-9b1c-e93a5aa8aad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302815175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3302815175
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.218239472
Short name T426
Test name
Test status
Simulation time 552309647 ps
CPU time 0.71 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 183660 kb
Host smart-960823d7-af0d-4789-ab6a-94e45fe30bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218239472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.218239472
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1107500307
Short name T376
Test name
Test status
Simulation time 389855345 ps
CPU time 0.71 seconds
Started Aug 12 04:26:35 PM PDT 24
Finished Aug 12 04:26:36 PM PDT 24
Peak memory 183664 kb
Host smart-abee93fb-48ca-481e-83f8-aee6e09f95da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107500307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1107500307
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3690819473
Short name T319
Test name
Test status
Simulation time 513384170 ps
CPU time 1.2 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 192912 kb
Host smart-9a23c32d-c4fe-4304-93e2-4c6e0a023409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690819473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3690819473
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3403160988
Short name T420
Test name
Test status
Simulation time 339633898 ps
CPU time 1.01 seconds
Started Aug 12 04:26:27 PM PDT 24
Finished Aug 12 04:26:28 PM PDT 24
Peak memory 183668 kb
Host smart-a3bcf47f-2d10-4d7e-936a-2417a1316559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403160988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3403160988
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2862053818
Short name T297
Test name
Test status
Simulation time 505992918 ps
CPU time 1.34 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:30 PM PDT 24
Peak memory 192884 kb
Host smart-30657603-05a4-4ffc-97fd-191051dda1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862053818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2862053818
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4263541169
Short name T381
Test name
Test status
Simulation time 329430278 ps
CPU time 0.63 seconds
Started Aug 12 04:26:37 PM PDT 24
Finished Aug 12 04:26:38 PM PDT 24
Peak memory 183592 kb
Host smart-a5920fe4-0337-4b90-8fc4-eb7a68e6d12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263541169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4263541169
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3982126840
Short name T407
Test name
Test status
Simulation time 380134850 ps
CPU time 1.1 seconds
Started Aug 12 04:27:18 PM PDT 24
Finished Aug 12 04:27:19 PM PDT 24
Peak memory 183664 kb
Host smart-e4da088d-0ba3-4fb5-be1c-cb2ab19c2405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982126840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3982126840
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4211023278
Short name T366
Test name
Test status
Simulation time 505158622 ps
CPU time 0.95 seconds
Started Aug 12 04:26:29 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 183696 kb
Host smart-c06232cf-16ac-4542-85dd-63013c3e570c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211023278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4211023278
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.666781946
Short name T302
Test name
Test status
Simulation time 452105935 ps
CPU time 0.99 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:35 PM PDT 24
Peak memory 195872 kb
Host smart-6c7baff3-e8ea-45b5-9762-89a5a897b8dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666781946 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.666781946
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2347614821
Short name T378
Test name
Test status
Simulation time 495561670 ps
CPU time 0.97 seconds
Started Aug 12 04:22:47 PM PDT 24
Finished Aug 12 04:22:48 PM PDT 24
Peak memory 192048 kb
Host smart-05342096-87f8-438b-b035-324eafaf832a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347614821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2347614821
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2840660958
Short name T296
Test name
Test status
Simulation time 502304194 ps
CPU time 0.6 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:34 PM PDT 24
Peak memory 183584 kb
Host smart-d5739c41-ca06-4032-8e31-6c90567584ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840660958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2840660958
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3648894873
Short name T380
Test name
Test status
Simulation time 1557275747 ps
CPU time 1.72 seconds
Started Aug 12 04:26:19 PM PDT 24
Finished Aug 12 04:26:21 PM PDT 24
Peak memory 192756 kb
Host smart-d0e16dc3-e386-47e5-87a6-5394fdd9c49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648894873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3648894873
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1850178919
Short name T332
Test name
Test status
Simulation time 604251422 ps
CPU time 1.79 seconds
Started Aug 12 04:24:35 PM PDT 24
Finished Aug 12 04:24:37 PM PDT 24
Peak memory 198584 kb
Host smart-f8607463-4d92-45d2-a50d-97a642fdd2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850178919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1850178919
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3315983405
Short name T298
Test name
Test status
Simulation time 4753845888 ps
CPU time 4.95 seconds
Started Aug 12 04:26:28 PM PDT 24
Finished Aug 12 04:26:34 PM PDT 24
Peak memory 197552 kb
Host smart-b17a665e-50a9-46a5-acc3-8d3b23d2862f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315983405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3315983405
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1037156716
Short name T325
Test name
Test status
Simulation time 490563973 ps
CPU time 1.49 seconds
Started Aug 12 04:27:13 PM PDT 24
Finished Aug 12 04:27:15 PM PDT 24
Peak memory 195384 kb
Host smart-c630366d-c857-49b5-bf58-e46fc3c58d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037156716 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1037156716
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.917057483
Short name T408
Test name
Test status
Simulation time 495763906 ps
CPU time 0.75 seconds
Started Aug 12 04:26:33 PM PDT 24
Finished Aug 12 04:26:34 PM PDT 24
Peak memory 191628 kb
Host smart-52e52405-f2de-459d-8d61-ada77ee004b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917057483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.917057483
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2314226725
Short name T388
Test name
Test status
Simulation time 368495530 ps
CPU time 0.85 seconds
Started Aug 12 04:24:25 PM PDT 24
Finished Aug 12 04:24:26 PM PDT 24
Peak memory 183660 kb
Host smart-e2a418cb-78d7-4107-b96a-a3b176c95dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314226725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2314226725
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.592406595
Short name T382
Test name
Test status
Simulation time 2055922927 ps
CPU time 4.75 seconds
Started Aug 12 04:26:25 PM PDT 24
Finished Aug 12 04:26:31 PM PDT 24
Peak memory 191660 kb
Host smart-7f63b484-3e61-4356-b9c1-ed827bb25104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592406595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.592406595
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.48873149
Short name T320
Test name
Test status
Simulation time 596954242 ps
CPU time 1.73 seconds
Started Aug 12 04:26:24 PM PDT 24
Finished Aug 12 04:26:26 PM PDT 24
Peak memory 198232 kb
Host smart-9f1781ce-e4ab-4b86-954f-936de4eba099
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48873149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.48873149
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2563552430
Short name T191
Test name
Test status
Simulation time 7713338259 ps
CPU time 8.05 seconds
Started Aug 12 04:21:48 PM PDT 24
Finished Aug 12 04:21:56 PM PDT 24
Peak memory 198168 kb
Host smart-edce24a6-5329-4727-952f-f56460e58e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563552430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2563552430
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.859021228
Short name T424
Test name
Test status
Simulation time 464572290 ps
CPU time 0.93 seconds
Started Aug 12 04:23:54 PM PDT 24
Finished Aug 12 04:23:55 PM PDT 24
Peak memory 197340 kb
Host smart-e4064728-4d52-4dd9-9ff2-3006d0b48f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859021228 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.859021228
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.245725857
Short name T335
Test name
Test status
Simulation time 419859481 ps
CPU time 1.11 seconds
Started Aug 12 04:26:34 PM PDT 24
Finished Aug 12 04:26:35 PM PDT 24
Peak memory 192428 kb
Host smart-1d39a82d-74ac-49ad-866d-3be5696078a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245725857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.245725857
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.41801506
Short name T342
Test name
Test status
Simulation time 493426332 ps
CPU time 0.93 seconds
Started Aug 12 04:23:41 PM PDT 24
Finished Aug 12 04:23:42 PM PDT 24
Peak memory 192916 kb
Host smart-a280720d-e863-41a9-a8b5-94e30e8412b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.41801506
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1328457226
Short name T354
Test name
Test status
Simulation time 907237825 ps
CPU time 1.82 seconds
Started Aug 12 04:26:18 PM PDT 24
Finished Aug 12 04:26:20 PM PDT 24
Peak memory 193132 kb
Host smart-ab731965-feb5-42a0-9a44-f40fd8ea2548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328457226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1328457226
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4162170623
Short name T295
Test name
Test status
Simulation time 413103975 ps
CPU time 1.91 seconds
Started Aug 12 04:27:13 PM PDT 24
Finished Aug 12 04:27:15 PM PDT 24
Peak memory 198216 kb
Host smart-5c5c875a-b5c3-4414-9f86-08224599a5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162170623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4162170623
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1326848890
Short name T400
Test name
Test status
Simulation time 4367476845 ps
CPU time 7.42 seconds
Started Aug 12 04:21:49 PM PDT 24
Finished Aug 12 04:21:56 PM PDT 24
Peak memory 198072 kb
Host smart-5b65c978-69b1-40b8-9a61-63a6cc35cae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326848890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1326848890
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.688532751
Short name T292
Test name
Test status
Simulation time 551064563 ps
CPU time 0.87 seconds
Started Aug 12 04:23:39 PM PDT 24
Finished Aug 12 04:23:39 PM PDT 24
Peak memory 196424 kb
Host smart-a50f4774-a5a6-4cc6-b3d2-4ad3b82cfe03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688532751 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.688532751
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.242789732
Short name T338
Test name
Test status
Simulation time 425492846 ps
CPU time 1.16 seconds
Started Aug 12 04:26:11 PM PDT 24
Finished Aug 12 04:26:13 PM PDT 24
Peak memory 192000 kb
Host smart-6c1f3502-7e47-43fd-aa6a-e08c27bf8277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242789732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.242789732
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.455707678
Short name T290
Test name
Test status
Simulation time 375695795 ps
CPU time 0.67 seconds
Started Aug 12 04:26:48 PM PDT 24
Finished Aug 12 04:26:49 PM PDT 24
Peak memory 183572 kb
Host smart-15253e35-ad71-4a44-b7e7-df00c8a50c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455707678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.455707678
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1599745484
Short name T406
Test name
Test status
Simulation time 1238989368 ps
CPU time 1.62 seconds
Started Aug 12 04:26:12 PM PDT 24
Finished Aug 12 04:26:14 PM PDT 24
Peak memory 183528 kb
Host smart-2ed99c65-7f33-49bd-8e00-7c8983448ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599745484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1599745484
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.511973492
Short name T299
Test name
Test status
Simulation time 335855080 ps
CPU time 1.86 seconds
Started Aug 12 04:22:15 PM PDT 24
Finished Aug 12 04:22:17 PM PDT 24
Peak memory 198564 kb
Host smart-4b601a87-e6ca-4349-87b4-a9bc05881d25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511973492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.511973492
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2030390744
Short name T356
Test name
Test status
Simulation time 4008777328 ps
CPU time 2.37 seconds
Started Aug 12 04:26:51 PM PDT 24
Finished Aug 12 04:26:53 PM PDT 24
Peak memory 197216 kb
Host smart-2c56d7f3-a7aa-4c49-bc9f-2965e65ba4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030390744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2030390744
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2842929361
Short name T315
Test name
Test status
Simulation time 464623825 ps
CPU time 0.8 seconds
Started Aug 12 04:25:46 PM PDT 24
Finished Aug 12 04:25:47 PM PDT 24
Peak memory 195456 kb
Host smart-949a1ff7-a9f3-49c9-a094-123c5c8d4cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842929361 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2842929361
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2868720957
Short name T49
Test name
Test status
Simulation time 483436547 ps
CPU time 1.35 seconds
Started Aug 12 04:23:37 PM PDT 24
Finished Aug 12 04:23:39 PM PDT 24
Peak memory 193436 kb
Host smart-138d0768-6705-42e4-8edd-46132e4a7f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868720957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2868720957
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3717347805
Short name T365
Test name
Test status
Simulation time 365613931 ps
CPU time 0.6 seconds
Started Aug 12 04:27:43 PM PDT 24
Finished Aug 12 04:27:44 PM PDT 24
Peak memory 192528 kb
Host smart-0684b30f-49df-42ac-8476-650373144cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717347805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3717347805
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2713146293
Short name T63
Test name
Test status
Simulation time 2173762253 ps
CPU time 2.59 seconds
Started Aug 12 04:25:33 PM PDT 24
Finished Aug 12 04:25:35 PM PDT 24
Peak memory 194996 kb
Host smart-f2e8686c-d901-4495-b5d8-19a13ae5d822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713146293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2713146293
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2103941925
Short name T344
Test name
Test status
Simulation time 491708544 ps
CPU time 1.34 seconds
Started Aug 12 04:27:10 PM PDT 24
Finished Aug 12 04:27:12 PM PDT 24
Peak memory 198172 kb
Host smart-352c6852-665c-49b2-b542-fdea75fff5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103941925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2103941925
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.174336190
Short name T193
Test name
Test status
Simulation time 4358295156 ps
CPU time 7.3 seconds
Started Aug 12 04:26:30 PM PDT 24
Finished Aug 12 04:26:38 PM PDT 24
Peak memory 197532 kb
Host smart-124748f6-d6e9-4a3a-8a65-b6acbbd62959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174336190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.174336190
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2455521179
Short name T9
Test name
Test status
Simulation time 37797823839 ps
CPU time 15.39 seconds
Started Aug 12 05:25:01 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 192136 kb
Host smart-a8faf733-e534-464d-9dd7-1e074c29e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455521179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2455521179
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2274747294
Short name T235
Test name
Test status
Simulation time 480405301 ps
CPU time 1.27 seconds
Started Aug 12 05:25:01 PM PDT 24
Finished Aug 12 05:25:03 PM PDT 24
Peak memory 192060 kb
Host smart-fab4f0ca-0267-4873-a21c-cf75eab61cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274747294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2274747294
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1035214524
Short name T210
Test name
Test status
Simulation time 15528507475 ps
CPU time 19.9 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 197200 kb
Host smart-c8b21095-8273-4d55-889c-5b9c9051b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035214524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1035214524
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.4100129449
Short name T17
Test name
Test status
Simulation time 8361714891 ps
CPU time 6.85 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 216092 kb
Host smart-7b838289-9b95-4f69-a9ab-4c4937c66df2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100129449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4100129449
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3880633978
Short name T262
Test name
Test status
Simulation time 390657801 ps
CPU time 1.15 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 192156 kb
Host smart-0d755126-e8d8-4fd3-b343-70a9aba4c1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880633978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3880633978
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4141054966
Short name T232
Test name
Test status
Simulation time 14291053447 ps
CPU time 19.5 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:38 PM PDT 24
Peak memory 192192 kb
Host smart-acb5bb45-96f1-4edd-9a5c-3196fcb746c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141054966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4141054966
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2316784923
Short name T251
Test name
Test status
Simulation time 509717836 ps
CPU time 0.97 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 192068 kb
Host smart-7e5835dd-7774-4409-afb5-bbb6f75eb24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316784923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2316784923
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1228101107
Short name T234
Test name
Test status
Simulation time 6800170408 ps
CPU time 5.66 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:21 PM PDT 24
Peak memory 192084 kb
Host smart-087a1a15-f41e-4440-ad71-d6f3c71a395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228101107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1228101107
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2462922304
Short name T242
Test name
Test status
Simulation time 473975171 ps
CPU time 0.73 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 192128 kb
Host smart-7cd449cd-360c-4952-9adf-8d31f805d70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462922304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2462922304
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1196615949
Short name T265
Test name
Test status
Simulation time 739005579 ps
CPU time 1.71 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 192072 kb
Host smart-38f95514-22d1-4fdb-b211-ccf80d3e62eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196615949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1196615949
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.199604966
Short name T43
Test name
Test status
Simulation time 473868040 ps
CPU time 1.3 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 192152 kb
Host smart-fbd90341-0d09-4881-8287-bd33adddba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199604966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.199604966
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2445126350
Short name T243
Test name
Test status
Simulation time 14568910059 ps
CPU time 19.09 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 197180 kb
Host smart-64c72d21-a1f7-4bc2-b34c-0f339807ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445126350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2445126350
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1653505386
Short name T248
Test name
Test status
Simulation time 427727458 ps
CPU time 1.14 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 192056 kb
Host smart-6f5d0c92-aa94-49ac-bb52-b11bb5e77537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653505386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1653505386
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.386360568
Short name T219
Test name
Test status
Simulation time 37187928354 ps
CPU time 53.56 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:26:09 PM PDT 24
Peak memory 192204 kb
Host smart-e94e8302-f30d-4fcc-b658-4468d8ae9d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386360568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.386360568
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1690686598
Short name T271
Test name
Test status
Simulation time 566393212 ps
CPU time 1 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 192108 kb
Host smart-60c6c416-15da-44ce-9adb-81419d2e6a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690686598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1690686598
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4138209504
Short name T246
Test name
Test status
Simulation time 12239678842 ps
CPU time 13.88 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 197144 kb
Host smart-49838827-7de8-437c-8652-28fe30c5319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138209504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4138209504
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3598499528
Short name T261
Test name
Test status
Simulation time 438377460 ps
CPU time 1.24 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 192100 kb
Host smart-ed610d77-b065-455b-90aa-866493effc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598499528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3598499528
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.283246365
Short name T187
Test name
Test status
Simulation time 395956448 ps
CPU time 1.16 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 196916 kb
Host smart-47651d7b-fc31-4db0-877f-2dad3b592bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283246365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.283246365
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3876362262
Short name T249
Test name
Test status
Simulation time 18003262158 ps
CPU time 3.32 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 197132 kb
Host smart-78976a5a-0de6-494e-a166-f8ba4b99e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876362262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3876362262
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4065935017
Short name T230
Test name
Test status
Simulation time 422990174 ps
CPU time 1.18 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 192068 kb
Host smart-948287f5-70c2-4cdc-b750-8d70d3236a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065935017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4065935017
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2943664670
Short name T216
Test name
Test status
Simulation time 4617337719 ps
CPU time 20.06 seconds
Started Aug 12 05:25:14 PM PDT 24
Finished Aug 12 05:25:34 PM PDT 24
Peak memory 206996 kb
Host smart-644d7aa6-b98a-43d4-9206-62cc157db96c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943664670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2943664670
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2900718745
Short name T211
Test name
Test status
Simulation time 21993823660 ps
CPU time 4.7 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 192192 kb
Host smart-a760db74-cce7-4053-bea7-5a679446b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900718745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2900718745
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2634865376
Short name T241
Test name
Test status
Simulation time 514449022 ps
CPU time 1.39 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 196884 kb
Host smart-261091c1-b6a5-43e1-9eca-f8a58214b034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634865376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2634865376
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.464122375
Short name T69
Test name
Test status
Simulation time 23190998137 ps
CPU time 3.56 seconds
Started Aug 12 05:25:19 PM PDT 24
Finished Aug 12 05:25:22 PM PDT 24
Peak memory 192168 kb
Host smart-9096f97a-a008-45dd-b6a0-7e14cd4c9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464122375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.464122375
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.458912920
Short name T264
Test name
Test status
Simulation time 600278379 ps
CPU time 0.82 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 197016 kb
Host smart-399df0d8-8123-420e-9d87-7e0e5fc79c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458912920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.458912920
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1874626365
Short name T245
Test name
Test status
Simulation time 13339989410 ps
CPU time 11.3 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 192160 kb
Host smart-c4813547-5b36-4c9a-9ddb-3345b81a0f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874626365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1874626365
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3270390465
Short name T204
Test name
Test status
Simulation time 390067713 ps
CPU time 0.76 seconds
Started Aug 12 05:25:18 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 192120 kb
Host smart-33baa3ab-fc35-4bf0-9e4f-a60f1c060673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270390465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3270390465
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1659216456
Short name T229
Test name
Test status
Simulation time 22907163452 ps
CPU time 2.99 seconds
Started Aug 12 05:25:07 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 192188 kb
Host smart-1bf00a51-19ea-4869-8416-5b823c98a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659216456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1659216456
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1135914836
Short name T15
Test name
Test status
Simulation time 4184031788 ps
CPU time 6.69 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:14 PM PDT 24
Peak memory 215816 kb
Host smart-57613ad8-e3c3-4822-aa4d-895e814fe29f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135914836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1135914836
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.545424090
Short name T214
Test name
Test status
Simulation time 517074780 ps
CPU time 1.35 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 196980 kb
Host smart-b7a4438b-3545-4e76-8988-0e1a5c725b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545424090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.545424090
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.676894134
Short name T223
Test name
Test status
Simulation time 55916625398 ps
CPU time 87.14 seconds
Started Aug 12 05:25:17 PM PDT 24
Finished Aug 12 05:26:44 PM PDT 24
Peak memory 192184 kb
Host smart-2e727e33-6f5e-4461-a8c0-219a7bac40f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676894134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.676894134
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2368146479
Short name T3
Test name
Test status
Simulation time 600025072 ps
CPU time 0.82 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 197124 kb
Host smart-20332b70-a229-49ce-b76b-e940f7c91756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368146479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2368146479
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1451539787
Short name T44
Test name
Test status
Simulation time 17518959938 ps
CPU time 6.77 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 192168 kb
Host smart-ceac892c-4ce8-4167-a387-9b0fc459b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451539787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1451539787
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3689586107
Short name T70
Test name
Test status
Simulation time 562846871 ps
CPU time 1.42 seconds
Started Aug 12 05:25:16 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 196700 kb
Host smart-1b2491d6-6918-4bc9-b325-aff4fc19e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689586107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3689586107
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3846132934
Short name T281
Test name
Test status
Simulation time 8261653769 ps
CPU time 6.07 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:34 PM PDT 24
Peak memory 192136 kb
Host smart-f8cab2e8-629c-4d83-8557-815c04f5b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846132934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3846132934
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2405733077
Short name T201
Test name
Test status
Simulation time 522018878 ps
CPU time 0.64 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 192056 kb
Host smart-3c8b1dff-af7f-4e8d-bd30-90160d738adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405733077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2405733077
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4222133916
Short name T209
Test name
Test status
Simulation time 20190378311 ps
CPU time 31.36 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:57 PM PDT 24
Peak memory 192180 kb
Host smart-1bba1abf-0a43-4ca5-9a14-0910856b715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222133916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4222133916
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2731203069
Short name T218
Test name
Test status
Simulation time 533093965 ps
CPU time 0.64 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:27 PM PDT 24
Peak memory 192128 kb
Host smart-9725d421-861f-4276-a463-14ca124498d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731203069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2731203069
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1156571310
Short name T231
Test name
Test status
Simulation time 3725230695 ps
CPU time 2.03 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 192164 kb
Host smart-30e21401-2dd1-4aca-957e-a3c6fcd41f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156571310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1156571310
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1070910908
Short name T33
Test name
Test status
Simulation time 482368567 ps
CPU time 0.74 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 192128 kb
Host smart-ef4281b8-14a0-4513-abfc-e75ffd870f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070910908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1070910908
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3208089086
Short name T227
Test name
Test status
Simulation time 9781757761 ps
CPU time 7.04 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:35 PM PDT 24
Peak memory 192084 kb
Host smart-e6f98d6c-0bf9-4c9b-b8a4-593aa4dac212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208089086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3208089086
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1030959163
Short name T66
Test name
Test status
Simulation time 469763293 ps
CPU time 0.89 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:27 PM PDT 24
Peak memory 192124 kb
Host smart-8fc47c5c-4947-48e2-add6-e8fe2694f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030959163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1030959163
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3195270355
Short name T263
Test name
Test status
Simulation time 34297420602 ps
CPU time 23.37 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 192128 kb
Host smart-c95451e8-7fa0-4fed-88ef-1879664c44c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195270355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3195270355
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4234047821
Short name T240
Test name
Test status
Simulation time 391609067 ps
CPU time 0.7 seconds
Started Aug 12 05:25:28 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 192068 kb
Host smart-f40f5813-1672-4d03-b763-de7aa7b1769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234047821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4234047821
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1848991024
Short name T276
Test name
Test status
Simulation time 11173895987 ps
CPU time 15.71 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 197248 kb
Host smart-be40004c-ce72-4d03-ba9d-a0ec6bf861db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848991024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1848991024
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3928150386
Short name T215
Test name
Test status
Simulation time 340156480 ps
CPU time 1.16 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:25:34 PM PDT 24
Peak memory 192060 kb
Host smart-ae041fdd-9518-4cdb-8d3b-486f0b4692b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928150386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3928150386
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1114164802
Short name T258
Test name
Test status
Simulation time 19054997017 ps
CPU time 29.83 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:00 PM PDT 24
Peak memory 192168 kb
Host smart-d3774de2-0d60-4faf-b40d-ca80fe7cec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114164802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1114164802
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2119767755
Short name T266
Test name
Test status
Simulation time 556358125 ps
CPU time 0.96 seconds
Started Aug 12 05:25:25 PM PDT 24
Finished Aug 12 05:25:26 PM PDT 24
Peak memory 191892 kb
Host smart-b89fb795-42d7-497c-989a-a1f9e56ee87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119767755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2119767755
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.376116823
Short name T198
Test name
Test status
Simulation time 6103352526 ps
CPU time 15.49 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 207052 kb
Host smart-21445824-ddd1-4fd5-9467-27a538dadec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376116823 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.376116823
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3841951713
Short name T176
Test name
Test status
Simulation time 456651558 ps
CPU time 0.87 seconds
Started Aug 12 05:25:26 PM PDT 24
Finished Aug 12 05:25:27 PM PDT 24
Peak memory 196892 kb
Host smart-ad3a5487-747f-4e4b-8355-0be8be5c887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841951713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3841951713
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3913019876
Short name T196
Test name
Test status
Simulation time 6987989007 ps
CPU time 9.38 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 192196 kb
Host smart-8e3c468f-1b03-4e17-af2e-86bcb49e30ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913019876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3913019876
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.28799028
Short name T253
Test name
Test status
Simulation time 439224069 ps
CPU time 0.73 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 192008 kb
Host smart-5702e148-a0de-4396-97f9-842eb573bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28799028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.28799028
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1571549970
Short name T250
Test name
Test status
Simulation time 405794105664 ps
CPU time 614.29 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:35:45 PM PDT 24
Peak memory 192096 kb
Host smart-68f5382e-644d-4c0b-a39a-df78ddc0f124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571549970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1571549970
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1704987141
Short name T228
Test name
Test status
Simulation time 24784972391 ps
CPU time 9.15 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 192168 kb
Host smart-946d332d-04e0-47cf-9b20-0d635c5807c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704987141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1704987141
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3895379970
Short name T18
Test name
Test status
Simulation time 8297041921 ps
CPU time 3.26 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:13 PM PDT 24
Peak memory 216264 kb
Host smart-2248fac0-79f9-4193-9af7-47c3a4d175b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895379970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3895379970
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1712156203
Short name T212
Test name
Test status
Simulation time 423146478 ps
CPU time 0.92 seconds
Started Aug 12 05:25:07 PM PDT 24
Finished Aug 12 05:25:08 PM PDT 24
Peak memory 192116 kb
Host smart-9e3340ea-f61f-4480-ac20-9a83d02f2b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712156203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1712156203
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.451165411
Short name T274
Test name
Test status
Simulation time 30550502723 ps
CPU time 42.72 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:26:13 PM PDT 24
Peak memory 192176 kb
Host smart-39637889-b118-4014-b2d1-2987af584abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451165411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.451165411
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.289073266
Short name T272
Test name
Test status
Simulation time 421282958 ps
CPU time 1.2 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 196832 kb
Host smart-d6b23845-2e85-43e6-9018-54924a64c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289073266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.289073266
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3215112264
Short name T277
Test name
Test status
Simulation time 35964934779 ps
CPU time 53.6 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:26:26 PM PDT 24
Peak memory 192176 kb
Host smart-064c8d76-dc10-407e-bb90-4da09ae3639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215112264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3215112264
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2314518504
Short name T259
Test name
Test status
Simulation time 499082810 ps
CPU time 1.36 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 192140 kb
Host smart-8288c758-9987-4be7-9780-c0f0344a4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314518504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2314518504
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1191417796
Short name T67
Test name
Test status
Simulation time 29705133374 ps
CPU time 40.4 seconds
Started Aug 12 05:25:27 PM PDT 24
Finished Aug 12 05:26:08 PM PDT 24
Peak memory 197144 kb
Host smart-8dc7189a-f5d1-41c5-a48c-c39108a185fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191417796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1191417796
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1456049459
Short name T6
Test name
Test status
Simulation time 490595930 ps
CPU time 0.95 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 192132 kb
Host smart-c58cb187-db55-48d6-bb7a-95a4c2e46147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456049459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1456049459
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1276881144
Short name T221
Test name
Test status
Simulation time 20388305604 ps
CPU time 31.53 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:26:01 PM PDT 24
Peak memory 191948 kb
Host smart-851df69a-2a05-4dc6-b0c6-e2fe1c4261cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276881144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1276881144
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2717007466
Short name T269
Test name
Test status
Simulation time 620248348 ps
CPU time 0.65 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 192108 kb
Host smart-a0bcbc1a-7461-4e2e-99c6-2ab968438ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717007466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2717007466
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1335323129
Short name T158
Test name
Test status
Simulation time 380176823 ps
CPU time 0.69 seconds
Started Aug 12 05:25:34 PM PDT 24
Finished Aug 12 05:25:35 PM PDT 24
Peak memory 196984 kb
Host smart-19de1940-8cfb-49a8-8fbe-bfbca3f74eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335323129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1335323129
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2271428989
Short name T213
Test name
Test status
Simulation time 6637777322 ps
CPU time 10.3 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 197176 kb
Host smart-fbcc0d22-74b0-441b-9e74-e6ef36517079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271428989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2271428989
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.140888278
Short name T268
Test name
Test status
Simulation time 601723536 ps
CPU time 1.44 seconds
Started Aug 12 05:25:34 PM PDT 24
Finished Aug 12 05:25:35 PM PDT 24
Peak memory 192100 kb
Host smart-3b32b307-0747-4707-8a76-00776e8c750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140888278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.140888278
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1866374534
Short name T282
Test name
Test status
Simulation time 20548742112 ps
CPU time 8.29 seconds
Started Aug 12 05:25:30 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 192208 kb
Host smart-ed2403a5-591b-47c3-afa0-7a98c0719192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866374534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1866374534
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2777689847
Short name T267
Test name
Test status
Simulation time 598553195 ps
CPU time 0.95 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 192112 kb
Host smart-05c87436-8c4c-41e4-9fa3-6cc1916ab9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777689847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2777689847
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4198287825
Short name T279
Test name
Test status
Simulation time 41168630440 ps
CPU time 64.88 seconds
Started Aug 12 05:25:29 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 192180 kb
Host smart-39edfe67-9c1b-452e-96ff-2ae6d4ae1762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198287825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4198287825
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.353028946
Short name T273
Test name
Test status
Simulation time 341924159 ps
CPU time 0.75 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 192096 kb
Host smart-be07e04e-5dd1-454a-9ae8-73c2cf2a03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353028946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.353028946
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.694193757
Short name T233
Test name
Test status
Simulation time 46943091929 ps
CPU time 18.55 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:54 PM PDT 24
Peak memory 197188 kb
Host smart-8b8bc9c7-f46e-4a33-b251-45d1cde86494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694193757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.694193757
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.901165081
Short name T239
Test name
Test status
Simulation time 366520603 ps
CPU time 0.86 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:25:32 PM PDT 24
Peak memory 192140 kb
Host smart-5cdfc27b-73cc-41d2-aee5-e5bd1d407fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901165081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.901165081
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3821341575
Short name T197
Test name
Test status
Simulation time 13955601831 ps
CPU time 5.64 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:25:37 PM PDT 24
Peak memory 197200 kb
Host smart-47ebc40c-3232-44b0-b240-8f7724b15926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821341575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3821341575
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.908323126
Short name T2
Test name
Test status
Simulation time 500566028 ps
CPU time 1.33 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 192124 kb
Host smart-af3581fe-4849-449a-be4d-15efbe4f41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908323126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.908323126
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2407354267
Short name T217
Test name
Test status
Simulation time 39680546753 ps
CPU time 58.08 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:26:33 PM PDT 24
Peak memory 192168 kb
Host smart-e4edb68f-9f4c-4155-9100-26225a7452b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407354267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2407354267
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.998672816
Short name T222
Test name
Test status
Simulation time 624521752 ps
CPU time 0.73 seconds
Started Aug 12 05:25:33 PM PDT 24
Finished Aug 12 05:25:34 PM PDT 24
Peak memory 192188 kb
Host smart-28a8bbc2-120a-41af-aa5c-21241bf1f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998672816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.998672816
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1194067989
Short name T238
Test name
Test status
Simulation time 38348623725 ps
CPU time 5.58 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 197184 kb
Host smart-29e76658-c267-4fc8-bf24-9b72718f7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194067989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1194067989
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2749136214
Short name T16
Test name
Test status
Simulation time 8444476220 ps
CPU time 3.94 seconds
Started Aug 12 05:25:11 PM PDT 24
Finished Aug 12 05:25:15 PM PDT 24
Peak memory 216184 kb
Host smart-70ef9ee6-942b-4cbb-b81e-2f824dfcf2b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749136214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2749136214
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3315180748
Short name T23
Test name
Test status
Simulation time 520369670 ps
CPU time 0.76 seconds
Started Aug 12 05:25:08 PM PDT 24
Finished Aug 12 05:25:09 PM PDT 24
Peak memory 192112 kb
Host smart-25dfe940-5e7d-4066-a50b-97b14f4b3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315180748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3315180748
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1632562932
Short name T236
Test name
Test status
Simulation time 28677082381 ps
CPU time 9.58 seconds
Started Aug 12 05:25:33 PM PDT 24
Finished Aug 12 05:25:43 PM PDT 24
Peak memory 197264 kb
Host smart-e14a4f46-16c0-4af2-a224-a702487b7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632562932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1632562932
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3633676649
Short name T237
Test name
Test status
Simulation time 371384261 ps
CPU time 1.17 seconds
Started Aug 12 05:25:34 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 192100 kb
Host smart-fe2cdd39-6b3f-4864-8d6f-fb67a5340520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633676649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3633676649
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4053849521
Short name T275
Test name
Test status
Simulation time 26897857509 ps
CPU time 39.13 seconds
Started Aug 12 05:25:32 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 197188 kb
Host smart-1aa53561-57c2-415f-8401-5b59bb41b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053849521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4053849521
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3476952497
Short name T244
Test name
Test status
Simulation time 575296703 ps
CPU time 1.44 seconds
Started Aug 12 05:25:36 PM PDT 24
Finished Aug 12 05:25:38 PM PDT 24
Peak memory 196932 kb
Host smart-c5c4ce66-e0e9-4b7d-bd0c-4bf8fb15d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476952497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3476952497
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2335162687
Short name T199
Test name
Test status
Simulation time 31720278089 ps
CPU time 44.41 seconds
Started Aug 12 05:25:31 PM PDT 24
Finished Aug 12 05:26:16 PM PDT 24
Peak memory 192224 kb
Host smart-234ce928-8c61-4c88-a02f-e83661190ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335162687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2335162687
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3235512043
Short name T256
Test name
Test status
Simulation time 475294415 ps
CPU time 0.98 seconds
Started Aug 12 05:25:35 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 196912 kb
Host smart-d2368a5d-e573-4008-887a-9926e496ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235512043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3235512043
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1263615770
Short name T208
Test name
Test status
Simulation time 35519863960 ps
CPU time 25.1 seconds
Started Aug 12 05:25:47 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 192168 kb
Host smart-01a8e804-a6e0-4cec-9412-8f359ed1740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263615770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1263615770
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1602949939
Short name T202
Test name
Test status
Simulation time 572248807 ps
CPU time 1.45 seconds
Started Aug 12 05:25:48 PM PDT 24
Finished Aug 12 05:25:49 PM PDT 24
Peak memory 196936 kb
Host smart-a55d08a9-52be-44b5-9b89-d300d854d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602949939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1602949939
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3931160549
Short name T19
Test name
Test status
Simulation time 3013905217 ps
CPU time 19.35 seconds
Started Aug 12 05:25:45 PM PDT 24
Finished Aug 12 05:26:05 PM PDT 24
Peak memory 198796 kb
Host smart-9cc49150-a468-42ca-9bb7-88fc713f3d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931160549 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3931160549
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4084289753
Short name T220
Test name
Test status
Simulation time 33774996857 ps
CPU time 53.66 seconds
Started Aug 12 05:25:40 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 197188 kb
Host smart-77a7f4e8-3d13-449f-a3f6-5bb2bea1aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084289753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4084289753
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2966136824
Short name T200
Test name
Test status
Simulation time 444350187 ps
CPU time 1.14 seconds
Started Aug 12 05:25:49 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 192100 kb
Host smart-c1883df2-78df-406a-aa95-c72770c40717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966136824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2966136824
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2296459265
Short name T71
Test name
Test status
Simulation time 38214271448 ps
CPU time 30.67 seconds
Started Aug 12 05:25:48 PM PDT 24
Finished Aug 12 05:26:19 PM PDT 24
Peak memory 197128 kb
Host smart-07b4d31a-8202-499c-a97f-b45c939244dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296459265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2296459265
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1431932063
Short name T226
Test name
Test status
Simulation time 403056384 ps
CPU time 0.74 seconds
Started Aug 12 05:25:38 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 192152 kb
Host smart-2a0cc168-76d9-4639-a615-5829acb4a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431932063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1431932063
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2585239234
Short name T252
Test name
Test status
Simulation time 18444907691 ps
CPU time 7.36 seconds
Started Aug 12 05:25:38 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 197092 kb
Host smart-3cf4cb26-a85c-4d69-8fa9-f520af77a71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585239234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2585239234
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.328403158
Short name T207
Test name
Test status
Simulation time 542035977 ps
CPU time 0.96 seconds
Started Aug 12 05:25:54 PM PDT 24
Finished Aug 12 05:25:55 PM PDT 24
Peak memory 192012 kb
Host smart-c9fff7af-1a42-4a17-8224-87917c85dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328403158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.328403158
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3226315071
Short name T283
Test name
Test status
Simulation time 725603371 ps
CPU time 2 seconds
Started Aug 12 05:25:40 PM PDT 24
Finished Aug 12 05:25:42 PM PDT 24
Peak memory 198612 kb
Host smart-e2b4663f-7796-4cca-9997-64e65e2e73f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226315071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3226315071
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3566233033
Short name T284
Test name
Test status
Simulation time 9318267928 ps
CPU time 12.55 seconds
Started Aug 12 05:25:38 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 192172 kb
Host smart-3dee1b30-a44f-489d-bd38-2ef5715e5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566233033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3566233033
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2947911756
Short name T278
Test name
Test status
Simulation time 525649986 ps
CPU time 1.36 seconds
Started Aug 12 05:25:49 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 192064 kb
Host smart-240de753-1f61-4518-822e-6ba788c29f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947911756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2947911756
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2715162050
Short name T257
Test name
Test status
Simulation time 52732782025 ps
CPU time 36.94 seconds
Started Aug 12 05:25:50 PM PDT 24
Finished Aug 12 05:26:27 PM PDT 24
Peak memory 192244 kb
Host smart-1d5494ef-a4ae-4df5-b793-b7444c3701d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715162050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2715162050
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3520021496
Short name T5
Test name
Test status
Simulation time 458497287 ps
CPU time 0.93 seconds
Started Aug 12 05:25:39 PM PDT 24
Finished Aug 12 05:25:40 PM PDT 24
Peak memory 192032 kb
Host smart-f3e5ff23-f2c3-47eb-985a-fb8f51b44a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520021496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3520021496
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.29673563
Short name T225
Test name
Test status
Simulation time 30879748406 ps
CPU time 43.13 seconds
Started Aug 12 05:25:38 PM PDT 24
Finished Aug 12 05:26:21 PM PDT 24
Peak memory 192140 kb
Host smart-023f66ae-c3a2-49f5-b246-5daa50ab3c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29673563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.29673563
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3278429642
Short name T280
Test name
Test status
Simulation time 354595695 ps
CPU time 0.7 seconds
Started Aug 12 05:25:52 PM PDT 24
Finished Aug 12 05:25:52 PM PDT 24
Peak memory 192084 kb
Host smart-63f4874b-fa2b-4df6-9fae-5e3a173a6ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278429642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3278429642
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1789237704
Short name T205
Test name
Test status
Simulation time 12606179351 ps
CPU time 2.91 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:13 PM PDT 24
Peak memory 192176 kb
Host smart-80f7aa1a-016c-464a-bff8-fe841f6243da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789237704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1789237704
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.282990380
Short name T224
Test name
Test status
Simulation time 421692554 ps
CPU time 0.74 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 192064 kb
Host smart-02b51d21-be5b-413a-8f47-ecab6171c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282990380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.282990380
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1663794054
Short name T203
Test name
Test status
Simulation time 44829805361 ps
CPU time 29.9 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 192208 kb
Host smart-80ddf873-722a-43f4-832f-125f8cef2591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663794054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1663794054
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.979643832
Short name T28
Test name
Test status
Simulation time 551022339 ps
CPU time 1.33 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 192108 kb
Host smart-8f1c7013-26bc-4abe-aa35-8afd051d0713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979643832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.979643832
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3542764166
Short name T247
Test name
Test status
Simulation time 38937648737 ps
CPU time 3.84 seconds
Started Aug 12 05:25:15 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 192136 kb
Host smart-946f5d3f-7329-4213-ab6e-315d52a105c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542764166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3542764166
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1998548036
Short name T260
Test name
Test status
Simulation time 413272909 ps
CPU time 0.75 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:10 PM PDT 24
Peak memory 192100 kb
Host smart-c74c4215-ac28-42a4-baa6-8baf199c3531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998548036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1998548036
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4032477681
Short name T255
Test name
Test status
Simulation time 46977149051 ps
CPU time 16.7 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:26 PM PDT 24
Peak memory 192196 kb
Host smart-a9658573-33f1-49ef-a5db-d8f25e61654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032477681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4032477681
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3333411179
Short name T254
Test name
Test status
Simulation time 363401577 ps
CPU time 1.14 seconds
Started Aug 12 05:25:11 PM PDT 24
Finished Aug 12 05:25:12 PM PDT 24
Peak memory 192076 kb
Host smart-f060fbee-bdc2-47b5-a8fc-8808c9aac725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333411179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3333411179
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.936831870
Short name T206
Test name
Test status
Simulation time 39830601992 ps
CPU time 14.56 seconds
Started Aug 12 05:25:09 PM PDT 24
Finished Aug 12 05:25:24 PM PDT 24
Peak memory 192188 kb
Host smart-06932dc7-37b2-4f38-a1f8-6b4a3b5cf1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936831870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.936831870
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.4243538873
Short name T270
Test name
Test status
Simulation time 604868502 ps
CPU time 0.79 seconds
Started Aug 12 05:25:10 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 192096 kb
Host smart-03395272-c7f2-4062-822f-25a3be4a4759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243538873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.4243538873
Directory /workspace/9.aon_timer_smoke/latest
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