Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18125	1		T1	474		T5	112		T6	166
bark[1]	258	1		T8	77		T93	21		T24	14
bark[2]	252	1		T40	23		T42	7		T88	21
bark[3]	189	1		T10	35		T27	63		T174	14
bark[4]	258	1		T2	14		T6	104		T11	21
bark[5]	276	1		T46	14		T97	50		T19	66
bark[6]	279	1		T11	26		T33	26		T97	21
bark[7]	77	1		T1	26		T20	30		T95	21
bark[8]	397	1		T11	33		T42	131		T81	21
bark[9]	264	1		T8	47		T108	26		T100	21
bark[10]	271	1		T5	21		T89	42		T104	30
bark[11]	374	1		T1	21		T41	7		T158	26
bark[12]	870	1		T70	7		T93	44		T176	21
bark[13]	168	1		T81	21		T102	14		T175	56
bark[14]	553	1		T5	21		T33	21		T41	21
bark[15]	126	1		T5	21		T89	21		T110	21
bark[16]	388	1		T4	14		T29	60		T82	14
bark[17]	457	1		T33	21		T42	26		T81	35
bark[18]	690	1		T3	14		T5	56		T113	14
bark[19]	502	1		T42	48		T19	49		T104	35
bark[20]	544	1		T33	99		T97	21		T93	68
bark[21]	239	1		T18	45		T20	21		T127	30
bark[22]	322	1		T5	21		T11	21		T27	21
bark[23]	329	1		T8	14		T19	30		T136	229
bark[24]	262	1		T131	21		T77	21		T192	21
bark[25]	323	1		T31	14		T27	30		T81	21
bark[26]	388	1		T29	21		T42	7		T44	19
bark[27]	423	1		T8	38		T29	49		T166	14
bark[28]	210	1		T28	14		T83	21		T71	45
bark[29]	178	1		T91	21		T120	40		T154	21
bark[30]	528	1		T5	21		T83	30		T97	82
bark[31]	498	1		T32	7		T158	43		T20	21
bark_0	4575	1		T1	74		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17959	1		T1	466		T5	132		T6	163
bite[1]	197	1		T1	21		T10	34		T27	30
bite[2]	268	1		T97	21		T89	21		T20	21
bite[3]	222	1		T42	47		T97	21		T71	46
bite[4]	463	1		T5	21		T81	21		T146	75
bite[5]	239	1		T4	13		T29	49		T70	6
bite[6]	34	1		T114	21		T167	13		-	-
bite[7]	394	1		T40	22		T166	13		T184	25
bite[8]	190	1		T30	13		T42	6		T97	21
bite[9]	586	1		T5	42		T8	77		T42	130
bite[10]	187	1		T3	13		T19	40		T120	40
bite[11]	212	1		T6	46		T100	26		T110	21
bite[12]	333	1		T8	38		T33	119		T83	30
bite[13]	378	1		T8	21		T31	13		T28	13
bite[14]	522	1		T8	26		T42	26		T89	21
bite[15]	272	1		T33	46		T113	13		T81	21
bite[16]	232	1		T46	13		T120	21		T138	39
bite[17]	409	1		T1	26		T32	6		T91	21
bite[18]	339	1		T8	13		T82	13		T83	21
bite[19]	559	1		T11	21		T20	21		T120	21
bite[20]	542	1		T2	13		T32	35		T19	21
bite[21]	180	1		T174	13		T105	21		T122	21
bite[22]	254	1		T93	44		T139	57		T91	21
bite[23]	327	1		T41	21		T44	13		T18	21
bite[24]	419	1		T5	56		T27	63		T81	35
bite[25]	168	1		T5	21		T169	13		T41	6
bite[26]	387	1		T6	56		T11	26		T26	13
bite[27]	250	1		T83	21		T19	30		T20	13
bite[28]	690	1		T33	21		T136	238		T75	224
bite[29]	255	1		T27	21		T115	21		T71	6
bite[30]	480	1		T29	60		T43	42		T44	25
bite[31]	580	1		T42	6		T158	38		T70	44
bite_0	5066	1		T1	82		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30087	1		T1	595		T2	21		T3	21
auto[1]	3506	1		T6	80		T8	20		T11	38

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	464	1		T1	24		T27	24		T41	53
prescale[1]	411	1		T10	2		T11	82		T193	9
prescale[2]	372	1		T1	23		T11	28		T40	2
prescale[3]	324	1		T93	23		T89	28		T146	36
prescale[4]	281	1		T5	9		T27	49		T194	9
prescale[5]	520	1		T195	9		T33	168		T83	23
prescale[6]	631	1		T7	9		T29	40		T44	9
prescale[7]	581	1		T8	23		T33	180		T41	2
prescale[8]	432	1		T27	31		T41	55		T184	2
prescale[9]	419	1		T43	2		T89	28		T196	9
prescale[10]	510	1		T1	2		T32	2		T33	9
prescale[11]	361	1		T33	19		T158	2		T115	2
prescale[12]	471	1		T18	24		T136	63		T120	19
prescale[13]	385	1		T5	44		T6	2		T10	2
prescale[14]	460	1		T6	2		T42	92		T23	19
prescale[15]	365	1		T11	42		T33	19		T158	14
prescale[16]	190	1		T45	9		T33	9		T42	2
prescale[17]	444	1		T41	21		T81	40		T158	2
prescale[18]	278	1		T1	18		T9	9		T43	2
prescale[19]	335	1		T5	64		T11	9		T79	9
prescale[20]	353	1		T29	28		T41	19		T88	53
prescale[21]	283	1		T8	19		T33	68		T139	9
prescale[22]	340	1		T40	2		T42	42		T115	2
prescale[23]	260	1		T8	23		T42	26		T197	9
prescale[24]	402	1		T6	2		T32	2		T41	92
prescale[25]	315	1		T5	23		T139	19		T176	43
prescale[26]	351	1		T40	2		T93	45		T88	40
prescale[27]	470	1		T33	61		T43	2		T18	19
prescale[28]	281	1		T1	2		T11	23		T41	36
prescale[29]	423	1		T1	12		T5	19		T44	48
prescale[30]	160	1		T10	2		T41	40		T44	2
prescale[31]	212	1		T6	2		T29	46		T115	2
prescale_0	21509	1		T1	514		T2	21		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	22919	1		T1	464		T2	21		T3	9
auto[1]	10674	1		T1	131		T3	12		T5	120

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	33593	1		T1	595		T2	21		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	18711	1		T1	345		T2	1		T3	1
wkup[1]	144	1		T176	30		T127	30		T154	21
wkup[2]	122	1		T20	15		T124	26		T149	21
wkup[3]	322	1		T11	21		T27	21		T89	21
wkup[4]	185	1		T33	21		T20	21		T159	15
wkup[5]	125	1		T20	21		T120	20		T150	6
wkup[6]	198	1		T28	15		T93	21		T136	21
wkup[7]	263	1		T6	21		T33	36		T24	15
wkup[8]	194	1		T1	21		T5	56		T33	21
wkup[9]	134	1		T71	21		T104	35		T91	30
wkup[10]	214	1		T4	15		T136	31		T104	21
wkup[11]	139	1		T8	26		T44	21		T158	21
wkup[12]	122	1		T93	44		T72	21		T137	15
wkup[13]	66	1		T112	15		T172	15		T90	21
wkup[14]	208	1		T11	35		T27	21		T40	26
wkup[15]	236	1		T29	21		T44	26		T97	21
wkup[16]	274	1		T11	21		T32	21		T33	21
wkup[17]	193	1		T32	15		T93	15		T120	21
wkup[18]	169	1		T1	21		T33	8		T184	21
wkup[19]	187	1		T33	21		T44	21		T97	30
wkup[20]	251	1		T8	15		T81	21		T158	21
wkup[21]	143	1		T1	39		T41	21		T127	26
wkup[22]	105	1		T5	21		T124	21		T75	21
wkup[23]	253	1		T1	21		T41	8		T42	57
wkup[24]	275	1		T81	21		T93	21		T145	15
wkup[25]	223	1		T32	8		T33	21		T43	21
wkup[26]	99	1		T8	21		T42	21		T136	15
wkup[27]	170	1		T3	15		T32	35		T33	21
wkup[28]	181	1		T5	21		T46	15		T72	21
wkup[29]	265	1		T27	30		T81	35		T19	26
wkup[30]	210	1		T83	30		T97	21		T131	34
wkup[31]	184	1		T27	21		T91	21		T124	8
wkup[32]	99	1		T113	15		T97	21		T139	21
wkup[33]	126	1		T5	21		T42	12		T138	30
wkup[34]	330	1		T29	39		T33	21		T146	21
wkup[35]	143	1		T11	26		T19	30		T23	21
wkup[36]	224	1		T11	21		T40	24		T115	21
wkup[37]	204	1		T115	42		T19	21		T161	21
wkup[38]	47	1		T146	26		T78	21		-	-
wkup[39]	267	1		T70	39		T71	14		T100	21
wkup[40]	78	1		T6	21		T131	36		T162	21
wkup[41]	203	1		T1	26		T5	21		T10	15
wkup[42]	158	1		T42	39		T20	30		T140	26
wkup[43]	179	1		T1	26		T83	21		T18	21
wkup[44]	182	1		T81	21		T174	15		T70	8
wkup[45]	92	1		T149	8		T94	21		T111	21
wkup[46]	174	1		T27	21		T44	15		T120	21
wkup[47]	308	1		T1	8		T6	21		T8	39
wkup[48]	254	1		T2	15		T31	15		T166	15
wkup[49]	156	1		T89	21		T72	21		T91	21
wkup[50]	84	1		T5	21		T124	21		T172	21
wkup[51]	165	1		T8	21		T158	21		T136	30
wkup[52]	204	1		T10	21		T169	15		T81	21
wkup[53]	103	1		T184	8		T18	21		T100	26
wkup[54]	176	1		T42	8		T88	21		T131	30
wkup[55]	163	1		T44	26		T88	21		T106	15
wkup[56]	249	1		T8	21		T30	15		T33	21
wkup[57]	249	1		T6	26		T42	26		T44	21
wkup[58]	48	1		T89	21		T75	6		T78	21
wkup[59]	130	1		T32	21		T82	15		T91	31
wkup[60]	123	1		T1	30		T97	21		T120	21
wkup[61]	250	1		T29	21		T40	35		T33	21
wkup[62]	164	1		T42	21		T70	44		T154	21
wkup[63]	138	1		T33	30		T19	21		T171	15
wkup_0	3558	1		T1	58		T2	5		T3	5