Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.04 99.33 93.67 100.00 98.40 99.51 43.34


Total test records in report: 426
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T153 /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2771737521 Aug 13 05:01:32 PM PDT 24 Aug 13 05:02:08 PM PDT 24 7653868682 ps
T34 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1244103008 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:20 PM PDT 24 1533047486 ps
T285 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4032517168 Aug 13 04:30:04 PM PDT 24 Aug 13 04:30:05 PM PDT 24 348722957 ps
T286 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.884144619 Aug 13 04:30:34 PM PDT 24 Aug 13 04:30:35 PM PDT 24 309064295 ps
T35 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2468571854 Aug 13 04:30:17 PM PDT 24 Aug 13 04:30:18 PM PDT 24 366409837 ps
T287 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3355008658 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:16 PM PDT 24 466852097 ps
T288 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.545574020 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:26 PM PDT 24 453573553 ps
T39 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2567116213 Aug 13 04:30:43 PM PDT 24 Aug 13 04:30:44 PM PDT 24 430086605 ps
T289 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.859376686 Aug 13 04:30:40 PM PDT 24 Aug 13 04:30:40 PM PDT 24 457296797 ps
T290 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1287512943 Aug 13 04:31:14 PM PDT 24 Aug 13 04:31:16 PM PDT 24 476220171 ps
T36 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.564278084 Aug 13 04:30:24 PM PDT 24 Aug 13 04:30:31 PM PDT 24 4494127714 ps
T291 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.655186094 Aug 13 04:30:07 PM PDT 24 Aug 13 04:30:15 PM PDT 24 454633419 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3619700845 Aug 13 04:30:35 PM PDT 24 Aug 13 04:30:36 PM PDT 24 354589576 ps
T47 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1386492447 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:15 PM PDT 24 482046802 ps
T67 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4104186153 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:25 PM PDT 24 490426014 ps
T62 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2257381248 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:26 PM PDT 24 1297091080 ps
T293 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3735496827 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:28 PM PDT 24 481765848 ps
T37 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3424185824 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:29 PM PDT 24 4430374375 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2204916798 Aug 13 04:30:13 PM PDT 24 Aug 13 04:30:20 PM PDT 24 431210498 ps
T295 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1186967769 Aug 13 04:30:24 PM PDT 24 Aug 13 04:30:25 PM PDT 24 324478302 ps
T68 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.842747148 Aug 13 04:30:16 PM PDT 24 Aug 13 04:30:17 PM PDT 24 428530207 ps
T296 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3539180790 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:25 PM PDT 24 613918566 ps
T48 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2515044536 Aug 13 04:30:13 PM PDT 24 Aug 13 04:30:14 PM PDT 24 531962241 ps
T297 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1117729928 Aug 13 04:30:41 PM PDT 24 Aug 13 04:30:42 PM PDT 24 359395252 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1403961911 Aug 13 04:30:15 PM PDT 24 Aug 13 04:30:17 PM PDT 24 1100347567 ps
T298 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.68243522 Aug 13 04:30:50 PM PDT 24 Aug 13 04:30:51 PM PDT 24 417861719 ps
T299 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.780524950 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:26 PM PDT 24 368873811 ps
T38 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3890421521 Aug 13 04:29:59 PM PDT 24 Aug 13 04:30:06 PM PDT 24 8364504699 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.411556951 Aug 13 04:30:17 PM PDT 24 Aug 13 04:30:21 PM PDT 24 2203470447 ps
T300 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.448815550 Aug 13 04:30:15 PM PDT 24 Aug 13 04:30:16 PM PDT 24 301057117 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1721821438 Aug 13 04:30:08 PM PDT 24 Aug 13 04:30:11 PM PDT 24 401656998 ps
T188 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2748774079 Aug 13 04:31:41 PM PDT 24 Aug 13 04:31:47 PM PDT 24 8031887675 ps
T69 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3876299101 Aug 13 04:29:58 PM PDT 24 Aug 13 04:29:58 PM PDT 24 405978900 ps
T302 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4254477697 Aug 13 04:30:20 PM PDT 24 Aug 13 04:30:22 PM PDT 24 412961530 ps
T49 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2207847166 Aug 13 04:30:15 PM PDT 24 Aug 13 04:30:16 PM PDT 24 507246240 ps
T303 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.393143466 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 281293869 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4137346668 Aug 13 04:30:07 PM PDT 24 Aug 13 04:30:08 PM PDT 24 318805391 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1099510743 Aug 13 04:30:10 PM PDT 24 Aug 13 04:30:11 PM PDT 24 1196771335 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2424528639 Aug 13 04:30:13 PM PDT 24 Aug 13 04:30:14 PM PDT 24 459854732 ps
T306 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1661432644 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 401063885 ps
T307 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1091730620 Aug 13 04:30:39 PM PDT 24 Aug 13 04:30:40 PM PDT 24 340514280 ps
T308 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3635559317 Aug 13 04:30:30 PM PDT 24 Aug 13 04:30:31 PM PDT 24 344978251 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4065097761 Aug 13 04:30:29 PM PDT 24 Aug 13 04:30:30 PM PDT 24 470803412 ps
T310 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1481842533 Aug 13 04:30:28 PM PDT 24 Aug 13 04:30:29 PM PDT 24 484664298 ps
T311 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2250474111 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 454497413 ps
T50 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2471205796 Aug 13 04:30:15 PM PDT 24 Aug 13 04:30:16 PM PDT 24 406530607 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2168811150 Aug 13 04:30:16 PM PDT 24 Aug 13 04:30:18 PM PDT 24 500800986 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3991719429 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:20 PM PDT 24 560050861 ps
T314 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.223063881 Aug 13 04:30:31 PM PDT 24 Aug 13 04:30:32 PM PDT 24 514604246 ps
T315 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2520099031 Aug 13 04:30:53 PM PDT 24 Aug 13 04:30:54 PM PDT 24 311705111 ps
T316 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2564769959 Aug 13 04:30:29 PM PDT 24 Aug 13 04:30:31 PM PDT 24 446394099 ps
T317 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2086830856 Aug 13 04:30:42 PM PDT 24 Aug 13 04:30:43 PM PDT 24 399416458 ps
T318 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1807136327 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:23 PM PDT 24 323070966 ps
T319 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1926545030 Aug 13 04:30:37 PM PDT 24 Aug 13 04:30:38 PM PDT 24 371909614 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2339167182 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:24 PM PDT 24 785935585 ps
T321 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1111828197 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:25 PM PDT 24 374742013 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3706952248 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 303177423 ps
T322 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3136800762 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 432830146 ps
T191 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3557176134 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:32 PM PDT 24 4692741677 ps
T52 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4223142428 Aug 13 04:31:35 PM PDT 24 Aug 13 04:31:37 PM PDT 24 395849670 ps
T323 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2258705002 Aug 13 04:30:38 PM PDT 24 Aug 13 04:30:39 PM PDT 24 494226908 ps
T66 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2258612294 Aug 13 04:30:13 PM PDT 24 Aug 13 04:30:19 PM PDT 24 2558143262 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3659381425 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:25 PM PDT 24 433710394 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3907664487 Aug 13 04:30:17 PM PDT 24 Aug 13 04:30:19 PM PDT 24 595330826 ps
T189 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1730322284 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:30 PM PDT 24 8501189413 ps
T325 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3823863465 Aug 13 04:30:24 PM PDT 24 Aug 13 04:30:26 PM PDT 24 449661897 ps
T326 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.390413288 Aug 13 04:30:12 PM PDT 24 Aug 13 04:30:14 PM PDT 24 2579808222 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2897718475 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:28 PM PDT 24 356337289 ps
T328 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2510416752 Aug 13 04:30:43 PM PDT 24 Aug 13 04:30:44 PM PDT 24 466916281 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2846100432 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:23 PM PDT 24 1386291612 ps
T330 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1181790695 Aug 13 04:30:39 PM PDT 24 Aug 13 04:30:40 PM PDT 24 510151643 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1798639570 Aug 13 04:31:30 PM PDT 24 Aug 13 04:31:36 PM PDT 24 1281987047 ps
T332 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.423844865 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:26 PM PDT 24 404320391 ps
T333 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.922434281 Aug 13 04:31:41 PM PDT 24 Aug 13 04:31:43 PM PDT 24 437202363 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2331391367 Aug 13 04:30:09 PM PDT 24 Aug 13 04:30:36 PM PDT 24 13899105749 ps
T335 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.307591081 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:24 PM PDT 24 401268982 ps
T336 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.47324128 Aug 13 04:30:39 PM PDT 24 Aug 13 04:30:40 PM PDT 24 420829868 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1142816291 Aug 13 04:30:28 PM PDT 24 Aug 13 04:30:33 PM PDT 24 2470408975 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.27388180 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:28 PM PDT 24 279967508 ps
T339 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2902114579 Aug 13 04:30:38 PM PDT 24 Aug 13 04:30:38 PM PDT 24 336012712 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2106601681 Aug 13 04:31:17 PM PDT 24 Aug 13 04:31:19 PM PDT 24 514011752 ps
T190 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3381052992 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:26 PM PDT 24 8241305685 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1765933996 Aug 13 04:30:32 PM PDT 24 Aug 13 04:30:34 PM PDT 24 423139790 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3334534716 Aug 13 04:31:36 PM PDT 24 Aug 13 04:31:43 PM PDT 24 2630128555 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3946216841 Aug 13 04:30:25 PM PDT 24 Aug 13 04:30:26 PM PDT 24 378999308 ps
T343 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1222540041 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:20 PM PDT 24 433078128 ps
T344 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3166864271 Aug 13 04:30:38 PM PDT 24 Aug 13 04:30:39 PM PDT 24 482677127 ps
T345 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3882670127 Aug 13 04:30:47 PM PDT 24 Aug 13 04:30:48 PM PDT 24 301087744 ps
T346 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3867959996 Aug 13 04:30:39 PM PDT 24 Aug 13 04:30:40 PM PDT 24 444416933 ps
T347 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1103770655 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:20 PM PDT 24 442902338 ps
T348 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.551132601 Aug 13 04:30:16 PM PDT 24 Aug 13 04:30:19 PM PDT 24 2597360347 ps
T349 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1135927152 Aug 13 04:30:21 PM PDT 24 Aug 13 04:30:22 PM PDT 24 481484691 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4272177949 Aug 13 04:30:24 PM PDT 24 Aug 13 04:30:25 PM PDT 24 463922097 ps
T351 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.111071313 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:19 PM PDT 24 424767635 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2384804725 Aug 13 04:30:10 PM PDT 24 Aug 13 04:30:12 PM PDT 24 403447244 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1090834553 Aug 13 04:30:12 PM PDT 24 Aug 13 04:30:21 PM PDT 24 7991955669 ps
T354 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.482693206 Aug 13 04:30:40 PM PDT 24 Aug 13 04:30:41 PM PDT 24 339946098 ps
T355 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3116827803 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:20 PM PDT 24 433581782 ps
T356 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1957419100 Aug 13 04:30:26 PM PDT 24 Aug 13 04:30:27 PM PDT 24 491662947 ps
T357 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4030798814 Aug 13 04:30:29 PM PDT 24 Aug 13 04:30:30 PM PDT 24 372087302 ps
T358 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1607832449 Aug 13 04:30:39 PM PDT 24 Aug 13 04:30:40 PM PDT 24 609252659 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1065517902 Aug 13 04:31:44 PM PDT 24 Aug 13 04:31:45 PM PDT 24 1332604329 ps
T360 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.108533598 Aug 13 04:31:32 PM PDT 24 Aug 13 04:31:33 PM PDT 24 555275835 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.762317945 Aug 13 04:30:03 PM PDT 24 Aug 13 04:30:05 PM PDT 24 808689643 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1752253505 Aug 13 04:30:04 PM PDT 24 Aug 13 04:30:06 PM PDT 24 890699951 ps
T363 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1291580369 Aug 13 04:30:37 PM PDT 24 Aug 13 04:30:39 PM PDT 24 432465682 ps
T364 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4335173 Aug 13 04:31:35 PM PDT 24 Aug 13 04:31:36 PM PDT 24 369976526 ps
T365 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2658498952 Aug 13 04:30:31 PM PDT 24 Aug 13 04:30:31 PM PDT 24 307002149 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1783346256 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:22 PM PDT 24 4387653167 ps
T367 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3171234566 Aug 13 04:30:36 PM PDT 24 Aug 13 04:30:38 PM PDT 24 1602262176 ps
T368 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3285790610 Aug 13 04:30:08 PM PDT 24 Aug 13 04:30:09 PM PDT 24 479620137 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1031915173 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:20 PM PDT 24 398057602 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1579296499 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:29 PM PDT 24 1099373959 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3674898721 Aug 13 04:30:11 PM PDT 24 Aug 13 04:30:12 PM PDT 24 370931404 ps
T372 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.837194175 Aug 13 04:31:40 PM PDT 24 Aug 13 04:31:42 PM PDT 24 832274544 ps
T373 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.282148564 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:29 PM PDT 24 547064422 ps
T374 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.643708414 Aug 13 04:30:29 PM PDT 24 Aug 13 04:30:43 PM PDT 24 8129901990 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4026210523 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:23 PM PDT 24 476298749 ps
T376 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4001754069 Aug 13 04:30:34 PM PDT 24 Aug 13 04:30:35 PM PDT 24 483681547 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4248600194 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:24 PM PDT 24 14151447045 ps
T378 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2016377687 Aug 13 04:30:16 PM PDT 24 Aug 13 04:30:18 PM PDT 24 444868261 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3179069614 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:40 PM PDT 24 9862212502 ps
T379 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4242755667 Aug 13 04:30:34 PM PDT 24 Aug 13 04:30:35 PM PDT 24 401522069 ps
T380 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2379812757 Aug 13 04:30:17 PM PDT 24 Aug 13 04:30:24 PM PDT 24 2327066293 ps
T381 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.421881292 Aug 13 04:30:45 PM PDT 24 Aug 13 04:30:46 PM PDT 24 427548013 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3566816765 Aug 13 04:30:36 PM PDT 24 Aug 13 04:30:40 PM PDT 24 1254215602 ps
T383 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1399509897 Aug 13 04:30:41 PM PDT 24 Aug 13 04:30:43 PM PDT 24 516183942 ps
T384 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2344094651 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:24 PM PDT 24 4741041490 ps
T385 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2473053038 Aug 13 04:30:31 PM PDT 24 Aug 13 04:30:32 PM PDT 24 388316337 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1734225755 Aug 13 04:31:39 PM PDT 24 Aug 13 04:32:04 PM PDT 24 12905845894 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2837630963 Aug 13 04:31:14 PM PDT 24 Aug 13 04:31:15 PM PDT 24 355907106 ps
T387 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4036635926 Aug 13 04:30:09 PM PDT 24 Aug 13 04:30:11 PM PDT 24 534857890 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1129662101 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:24 PM PDT 24 580553633 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3258127538 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:28 PM PDT 24 457192420 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1067574195 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:21 PM PDT 24 1588208497 ps
T391 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.770351573 Aug 13 04:30:35 PM PDT 24 Aug 13 04:30:50 PM PDT 24 8481640186 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3295432522 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:20 PM PDT 24 626267624 ps
T393 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2246158993 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:24 PM PDT 24 504561898 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.149788265 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:16 PM PDT 24 648353343 ps
T394 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2928184035 Aug 13 04:30:29 PM PDT 24 Aug 13 04:30:30 PM PDT 24 323814008 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2211020408 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:27 PM PDT 24 4440982731 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3567441711 Aug 13 04:31:30 PM PDT 24 Aug 13 04:31:31 PM PDT 24 345940428 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.713435741 Aug 13 04:30:07 PM PDT 24 Aug 13 04:30:09 PM PDT 24 1319925522 ps
T397 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3239575098 Aug 13 04:30:09 PM PDT 24 Aug 13 04:30:10 PM PDT 24 530480073 ps
T398 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1840503230 Aug 13 04:30:38 PM PDT 24 Aug 13 04:30:40 PM PDT 24 598375524 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3159408128 Aug 13 04:30:08 PM PDT 24 Aug 13 04:30:10 PM PDT 24 1218857018 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2932624776 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:24 PM PDT 24 491288356 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2111003559 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:25 PM PDT 24 4592375749 ps
T400 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4068677090 Aug 13 04:30:48 PM PDT 24 Aug 13 04:30:49 PM PDT 24 377396936 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4293088676 Aug 13 04:30:18 PM PDT 24 Aug 13 04:30:22 PM PDT 24 8592510973 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3335113865 Aug 13 04:30:14 PM PDT 24 Aug 13 04:30:24 PM PDT 24 7058044209 ps
T403 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.571734848 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:19 PM PDT 24 448573359 ps
T404 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.62713157 Aug 13 04:30:45 PM PDT 24 Aug 13 04:30:46 PM PDT 24 452317313 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3631248882 Aug 13 04:29:59 PM PDT 24 Aug 13 04:30:00 PM PDT 24 890009405 ps
T406 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2547159751 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:24 PM PDT 24 4378690047 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2829646403 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:24 PM PDT 24 448492139 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1278736876 Aug 13 04:30:02 PM PDT 24 Aug 13 04:30:04 PM PDT 24 443284885 ps
T409 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2447935094 Aug 13 04:30:13 PM PDT 24 Aug 13 04:30:14 PM PDT 24 342502034 ps
T410 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.788686209 Aug 13 04:30:23 PM PDT 24 Aug 13 04:30:24 PM PDT 24 511185808 ps
T411 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1730576026 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:23 PM PDT 24 421779692 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4097671188 Aug 13 04:30:30 PM PDT 24 Aug 13 04:30:37 PM PDT 24 399676930 ps
T413 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3661333376 Aug 13 04:30:15 PM PDT 24 Aug 13 04:30:18 PM PDT 24 4704666737 ps
T414 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3450957854 Aug 13 04:30:40 PM PDT 24 Aug 13 04:30:41 PM PDT 24 2577744029 ps
T415 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4148236194 Aug 13 04:30:28 PM PDT 24 Aug 13 04:30:29 PM PDT 24 2302783637 ps
T416 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2413738285 Aug 13 04:30:22 PM PDT 24 Aug 13 04:30:23 PM PDT 24 442469455 ps
T417 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3531726087 Aug 13 04:30:19 PM PDT 24 Aug 13 04:30:22 PM PDT 24 8870293847 ps
T418 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4240799022 Aug 13 04:30:38 PM PDT 24 Aug 13 04:30:39 PM PDT 24 518452308 ps
T419 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1302280877 Aug 13 04:30:21 PM PDT 24 Aug 13 04:30:24 PM PDT 24 8616432137 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1552439683 Aug 13 04:30:34 PM PDT 24 Aug 13 04:30:35 PM PDT 24 373423706 ps
T421 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3561779728 Aug 13 04:30:43 PM PDT 24 Aug 13 04:30:44 PM PDT 24 501755039 ps
T422 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2801224695 Aug 13 04:31:14 PM PDT 24 Aug 13 04:31:17 PM PDT 24 4375056489 ps
T423 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3282338473 Aug 13 04:30:27 PM PDT 24 Aug 13 04:30:28 PM PDT 24 407986074 ps
T424 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3479274808 Aug 13 04:30:17 PM PDT 24 Aug 13 04:30:19 PM PDT 24 437422193 ps
T425 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.586436383 Aug 13 04:30:35 PM PDT 24 Aug 13 04:30:37 PM PDT 24 410563240 ps
T426 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2454524487 Aug 13 04:30:40 PM PDT 24 Aug 13 04:30:43 PM PDT 24 676618642 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2047573069 Aug 13 04:31:34 PM PDT 24 Aug 13 04:31:35 PM PDT 24 632775464 ps

Test location /workspace/coverage/default/25.aon_timer_stress_all.1152726960
Short name T8
Test name
Test status
Simulation time 100400092897 ps
CPU time 39.59 seconds
Started Aug 13 05:01:48 PM PDT 24
Finished Aug 13 05:02:28 PM PDT 24
Peak memory 198488 kb
Host smart-180bac03-3ecf-4807-be81-26789fe1489d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152726960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1152726960
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3263878817
Short name T41
Test name
Test status
Simulation time 6005219828 ps
CPU time 11.31 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:10 PM PDT 24
Peak memory 214260 kb
Host smart-84798fc3-c883-44b5-892e-82576e29539d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263878817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3263878817
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2515044536
Short name T48
Test name
Test status
Simulation time 531962241 ps
CPU time 0.93 seconds
Started Aug 13 04:30:13 PM PDT 24
Finished Aug 13 04:30:14 PM PDT 24
Peak memory 194644 kb
Host smart-d284cd5d-cff4-4210-b298-d9643c7db176
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515044536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2515044536
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2034431515
Short name T5
Test name
Test status
Simulation time 240864398076 ps
CPU time 34.94 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 198416 kb
Host smart-348486dc-4259-4059-80a6-d66720eb0f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034431515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2034431515
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3979075664
Short name T13
Test name
Test status
Simulation time 7981166849 ps
CPU time 11.25 seconds
Started Aug 13 05:01:27 PM PDT 24
Finished Aug 13 05:01:38 PM PDT 24
Peak memory 216188 kb
Host smart-e01d6f52-fd2c-410f-9458-72408b9560b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979075664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3979075664
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2357842645
Short name T20
Test name
Test status
Simulation time 106088004420 ps
CPU time 137.74 seconds
Started Aug 13 05:02:07 PM PDT 24
Finished Aug 13 05:04:25 PM PDT 24
Peak memory 198524 kb
Host smart-5d82ea89-f8b0-4e96-b9a9-028fe45d0f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357842645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2357842645
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3630197243
Short name T91
Test name
Test status
Simulation time 165109721211 ps
CPU time 252.12 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:05:55 PM PDT 24
Peak memory 193196 kb
Host smart-b94812be-f6fa-4e32-899a-9318acd39808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630197243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3630197243
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.986317072
Short name T111
Test name
Test status
Simulation time 97932079151 ps
CPU time 70.3 seconds
Started Aug 13 05:02:04 PM PDT 24
Finished Aug 13 05:03:14 PM PDT 24
Peak memory 198712 kb
Host smart-dc5fcd4d-e797-4e22-8488-402cc1c31d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986317072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.986317072
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3341904933
Short name T78
Test name
Test status
Simulation time 38264769149 ps
CPU time 18.89 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 198668 kb
Host smart-fd07adad-6e31-4609-98b4-60b4e01b75df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341904933 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3341904933
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1642138776
Short name T97
Test name
Test status
Simulation time 28752044134 ps
CPU time 17.14 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:55 PM PDT 24
Peak memory 198448 kb
Host smart-60283867-1941-49e0-9950-ff6d41a39c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642138776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1642138776
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2086824213
Short name T75
Test name
Test status
Simulation time 10871277537 ps
CPU time 38.08 seconds
Started Aug 13 05:01:51 PM PDT 24
Finished Aug 13 05:02:29 PM PDT 24
Peak memory 206928 kb
Host smart-925ee502-ff97-4a9c-aa28-f0ab107bb9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086824213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2086824213
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1265158962
Short name T110
Test name
Test status
Simulation time 62399661330 ps
CPU time 46.64 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:02:11 PM PDT 24
Peak memory 198428 kb
Host smart-a16f74e6-71fd-4a68-bfad-558aadad92b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265158962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1265158962
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4193730620
Short name T104
Test name
Test status
Simulation time 95008628911 ps
CPU time 32.31 seconds
Started Aug 13 05:02:04 PM PDT 24
Finished Aug 13 05:02:36 PM PDT 24
Peak memory 193260 kb
Host smart-3c7387d3-2f28-4ba6-9f49-b9ca6afc82bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193730620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4193730620
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1049337705
Short name T99
Test name
Test status
Simulation time 5942726738 ps
CPU time 40.61 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:02:13 PM PDT 24
Peak memory 214188 kb
Host smart-f4515a01-5b75-4782-9893-0464232e573a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049337705 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1049337705
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1383795324
Short name T90
Test name
Test status
Simulation time 102582941129 ps
CPU time 66.5 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:02:50 PM PDT 24
Peak memory 192880 kb
Host smart-38669f22-47be-480b-ba78-46a825eccae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383795324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1383795324
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3488660939
Short name T94
Test name
Test status
Simulation time 7635157564 ps
CPU time 30.43 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:02:13 PM PDT 24
Peak memory 198804 kb
Host smart-fa4a4767-1acf-4954-9efa-8e4e951928a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488660939 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3488660939
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3190682730
Short name T93
Test name
Test status
Simulation time 71765430910 ps
CPU time 78.79 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:03:18 PM PDT 24
Peak memory 191960 kb
Host smart-4509c245-caa7-4d05-a187-62afe6d42080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190682730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3190682730
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2748774079
Short name T188
Test name
Test status
Simulation time 8031887675 ps
CPU time 6 seconds
Started Aug 13 04:31:41 PM PDT 24
Finished Aug 13 04:31:47 PM PDT 24
Peak memory 198068 kb
Host smart-2e0a3e1d-e3e7-4f2f-bf61-8ee38f4ff04d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748774079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2748774079
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2716254613
Short name T121
Test name
Test status
Simulation time 37115020675 ps
CPU time 14.66 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 193140 kb
Host smart-06684b11-6297-4b5e-b5ee-a7a9d3566af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716254613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2716254613
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2103006935
Short name T86
Test name
Test status
Simulation time 179218762523 ps
CPU time 63.28 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:02:45 PM PDT 24
Peak memory 192692 kb
Host smart-c64e436e-7f15-4a00-8463-a8b5d8b9afef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103006935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2103006935
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3215998731
Short name T103
Test name
Test status
Simulation time 129967716966 ps
CPU time 50.17 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:02:33 PM PDT 24
Peak memory 192152 kb
Host smart-b4db14dd-bf45-4f2c-aded-0148ab6b5daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215998731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3215998731
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1753051806
Short name T1
Test name
Test status
Simulation time 14889997030 ps
CPU time 33.03 seconds
Started Aug 13 05:01:57 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 214280 kb
Host smart-840ddcce-d794-4ed0-ba92-cea1687af919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753051806 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1753051806
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1155641996
Short name T89
Test name
Test status
Simulation time 86833394870 ps
CPU time 63.78 seconds
Started Aug 13 05:01:35 PM PDT 24
Finished Aug 13 05:02:39 PM PDT 24
Peak memory 198432 kb
Host smart-7e1b38a4-965a-4299-b4f4-de4eac0d742e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155641996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1155641996
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4100020934
Short name T95
Test name
Test status
Simulation time 3250910172 ps
CPU time 22.51 seconds
Started Aug 13 05:01:47 PM PDT 24
Finished Aug 13 05:02:10 PM PDT 24
Peak memory 198792 kb
Host smart-75c7a26e-b7d3-432e-977c-bbe4bb28568d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100020934 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4100020934
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2579397896
Short name T108
Test name
Test status
Simulation time 214024505778 ps
CPU time 81.75 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:03:06 PM PDT 24
Peak memory 192092 kb
Host smart-aa4d757d-089a-4a76-ab3d-c40c5aa6b58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579397896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2579397896
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.80114146
Short name T122
Test name
Test status
Simulation time 149856986655 ps
CPU time 44.3 seconds
Started Aug 13 05:02:06 PM PDT 24
Finished Aug 13 05:02:51 PM PDT 24
Peak memory 198528 kb
Host smart-eed84610-8d97-4c0d-9d00-c6a601ef1140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80114146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_al
l.80114146
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2048514906
Short name T81
Test name
Test status
Simulation time 31803088468 ps
CPU time 10.99 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:01:54 PM PDT 24
Peak memory 198376 kb
Host smart-f9cbb10d-b88b-4b43-a5a9-251b75161118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048514906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2048514906
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4179669321
Short name T19
Test name
Test status
Simulation time 38374344320 ps
CPU time 15.02 seconds
Started Aug 13 05:01:57 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 193480 kb
Host smart-632bcbc7-a124-48b9-bb81-57db7a61e379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179669321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4179669321
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2149504918
Short name T33
Test name
Test status
Simulation time 6218976963 ps
CPU time 38.95 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:40 PM PDT 24
Peak memory 215160 kb
Host smart-4e6d0033-acaf-4125-8b12-814083afe14b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149504918 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2149504918
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.111235972
Short name T130
Test name
Test status
Simulation time 220203391533 ps
CPU time 94.2 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:03:13 PM PDT 24
Peak memory 198428 kb
Host smart-4a153623-cb63-4e91-8dc3-5fdfc6320159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111235972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.111235972
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.4175342684
Short name T140
Test name
Test status
Simulation time 16501536667 ps
CPU time 6.92 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 193104 kb
Host smart-0ac3aa66-dae3-432b-809f-262670b746dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175342684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.4175342684
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3360438350
Short name T117
Test name
Test status
Simulation time 353939092598 ps
CPU time 470.75 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:09:24 PM PDT 24
Peak memory 193260 kb
Host smart-9fd83932-489c-4a30-b638-1a02c79701db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360438350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3360438350
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3096152780
Short name T11
Test name
Test status
Simulation time 113244167406 ps
CPU time 148.23 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:04:05 PM PDT 24
Peak memory 193208 kb
Host smart-a7697f10-dba3-4cfb-8de9-09b4e9ba3fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096152780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3096152780
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2980399400
Short name T77
Test name
Test status
Simulation time 5460110987 ps
CPU time 10.7 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:45 PM PDT 24
Peak memory 214696 kb
Host smart-5637e003-6342-49fd-b17d-0d930b6ead23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980399400 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2980399400
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.252846062
Short name T101
Test name
Test status
Simulation time 241055071301 ps
CPU time 193.63 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:04:52 PM PDT 24
Peak memory 193172 kb
Host smart-2d92c435-f084-4599-9b3b-8a07717c633f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252846062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.252846062
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.87135446
Short name T83
Test name
Test status
Simulation time 69347489133 ps
CPU time 97.41 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:03:32 PM PDT 24
Peak memory 192140 kb
Host smart-1f9289a8-d498-487b-aac8-18b431061c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87135446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_al
l.87135446
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3628090100
Short name T116
Test name
Test status
Simulation time 6612540676 ps
CPU time 31.15 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:31 PM PDT 24
Peak memory 198716 kb
Host smart-6bb249af-4c38-4539-a62e-8dc34580a498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628090100 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3628090100
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2822316003
Short name T120
Test name
Test status
Simulation time 129374661177 ps
CPU time 168.06 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:04:26 PM PDT 24
Peak memory 198516 kb
Host smart-94ee3ac9-90ef-4f7d-8f23-2e90efd04490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822316003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2822316003
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1018439646
Short name T112
Test name
Test status
Simulation time 17543180314 ps
CPU time 4.74 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 198520 kb
Host smart-ffb07dac-9b73-42ae-9fa6-9a9cca98d1c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018439646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1018439646
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.440978767
Short name T131
Test name
Test status
Simulation time 25805068425 ps
CPU time 52.04 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:02:48 PM PDT 24
Peak memory 206912 kb
Host smart-17f92cea-77bd-4b68-bb79-f978758065ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440978767 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.440978767
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3275745647
Short name T44
Test name
Test status
Simulation time 5738821685 ps
CPU time 39.27 seconds
Started Aug 13 05:02:05 PM PDT 24
Finished Aug 13 05:02:45 PM PDT 24
Peak memory 206872 kb
Host smart-d8da684c-9694-410f-ae6e-dcc8611644e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275745647 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3275745647
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2894950909
Short name T23
Test name
Test status
Simulation time 166865374076 ps
CPU time 67.23 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:02:40 PM PDT 24
Peak memory 192064 kb
Host smart-c72ec0b0-3734-40ef-8669-f72b1d9f8ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894950909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2894950909
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2882536191
Short name T88
Test name
Test status
Simulation time 389482640316 ps
CPU time 480.87 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:10:00 PM PDT 24
Peak memory 198432 kb
Host smart-c8b1f237-77a4-4492-ab5d-24ca9b941ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882536191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2882536191
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1078570971
Short name T92
Test name
Test status
Simulation time 228922838534 ps
CPU time 163.94 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:04:45 PM PDT 24
Peak memory 198452 kb
Host smart-be6ae8a8-cb41-4ade-a8fd-7405997a73e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078570971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1078570971
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3398103674
Short name T27
Test name
Test status
Simulation time 70104408341 ps
CPU time 91.87 seconds
Started Aug 13 05:01:35 PM PDT 24
Finished Aug 13 05:03:07 PM PDT 24
Peak memory 192168 kb
Host smart-af432821-8c9f-42de-ba38-3d746ec94150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398103674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3398103674
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1109564017
Short name T105
Test name
Test status
Simulation time 27107004946 ps
CPU time 40.47 seconds
Started Aug 13 05:01:49 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 193248 kb
Host smart-b6c96ac6-d530-4a74-ad36-a9e0444e95fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109564017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1109564017
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3786028439
Short name T154
Test name
Test status
Simulation time 189302173276 ps
CPU time 120.14 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:03:42 PM PDT 24
Peak memory 193204 kb
Host smart-78df6915-18a1-455d-b2eb-74ba70b4303e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786028439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3786028439
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2780273342
Short name T164
Test name
Test status
Simulation time 220499008293 ps
CPU time 306.01 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:07:08 PM PDT 24
Peak memory 193276 kb
Host smart-36bf28b1-ce4f-46c6-82ae-584ed6177236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780273342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2780273342
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3874360283
Short name T114
Test name
Test status
Simulation time 196675397918 ps
CPU time 273.85 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:06:11 PM PDT 24
Peak memory 198468 kb
Host smart-a317a3a7-13c2-40d4-8563-ad3dabfb8cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874360283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3874360283
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2309975832
Short name T124
Test name
Test status
Simulation time 5894889458 ps
CPU time 22.63 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:24 PM PDT 24
Peak memory 198752 kb
Host smart-d5f84b80-3bef-46c5-a1a7-670a4f2690e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309975832 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2309975832
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1545591203
Short name T96
Test name
Test status
Simulation time 1612921515 ps
CPU time 9.73 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:11 PM PDT 24
Peak memory 206872 kb
Host smart-2273998c-1947-4110-8a87-5cfc3eaa60b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545591203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1545591203
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.411556951
Short name T64
Test name
Test status
Simulation time 2203470447 ps
CPU time 4.58 seconds
Started Aug 13 04:30:17 PM PDT 24
Finished Aug 13 04:30:21 PM PDT 24
Peak memory 194012 kb
Host smart-0e71c9f3-cb61-4c05-873d-b8a1c85aaaf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411556951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.411556951
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3455591450
Short name T149
Test name
Test status
Simulation time 8611385855 ps
CPU time 38.91 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:02:07 PM PDT 24
Peak memory 198744 kb
Host smart-ce9eefe5-fa11-4c72-b1b5-e54e4102b28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455591450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3455591450
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1921439590
Short name T71
Test name
Test status
Simulation time 2330233828 ps
CPU time 11.94 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:01:58 PM PDT 24
Peak memory 198760 kb
Host smart-a56595ac-270e-481f-a220-3165a2aac269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921439590 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1921439590
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3699195615
Short name T76
Test name
Test status
Simulation time 2998032961 ps
CPU time 18.1 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 198708 kb
Host smart-8205617a-f4ac-47a3-8588-e0aa725d87be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699195615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3699195615
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1147671335
Short name T100
Test name
Test status
Simulation time 294294748247 ps
CPU time 227.73 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:05:48 PM PDT 24
Peak memory 192140 kb
Host smart-0b8b0f59-f40d-4f20-a074-92a9b07707f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147671335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1147671335
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2984443107
Short name T162
Test name
Test status
Simulation time 4485183693 ps
CPU time 12.08 seconds
Started Aug 13 05:01:36 PM PDT 24
Finished Aug 13 05:01:48 PM PDT 24
Peak memory 215092 kb
Host smart-6fe1ad46-7c7b-40a1-8e01-8a2928e3c5eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984443107 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2984443107
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2003879622
Short name T135
Test name
Test status
Simulation time 112863016397 ps
CPU time 9.14 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 192528 kb
Host smart-d139f95c-e57b-4ab7-a212-ca78a4263c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003879622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2003879622
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.401560918
Short name T42
Test name
Test status
Simulation time 4282786136 ps
CPU time 22.43 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:02:07 PM PDT 24
Peak memory 198808 kb
Host smart-85bda469-6556-4434-8ba0-4eeaa4a68966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401560918 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.401560918
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4095356406
Short name T70
Test name
Test status
Simulation time 18312959075 ps
CPU time 23.89 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:27 PM PDT 24
Peak memory 214424 kb
Host smart-c8dee5ea-39c8-408b-bee5-c9c8b81a3fd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095356406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4095356406
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2335570659
Short name T98
Test name
Test status
Simulation time 1767442490 ps
CPU time 11.22 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:49 PM PDT 24
Peak memory 206908 kb
Host smart-3b798f12-498f-4a45-ad0c-3c0757c50d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335570659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2335570659
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2663593282
Short name T157
Test name
Test status
Simulation time 2366049245 ps
CPU time 13.14 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:01:56 PM PDT 24
Peak memory 198736 kb
Host smart-03071266-b611-42a7-9454-a9907ae18b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663593282 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2663593282
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.213161172
Short name T18
Test name
Test status
Simulation time 208628899857 ps
CPU time 86.71 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:03:12 PM PDT 24
Peak memory 193160 kb
Host smart-fd315c40-4c36-4ea7-b195-a7101f064e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213161172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.213161172
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1886764077
Short name T109
Test name
Test status
Simulation time 409563596 ps
CPU time 0.73 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:01:40 PM PDT 24
Peak memory 196832 kb
Host smart-d014bcc0-c079-46ee-b2f0-121fd14b2615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886764077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1886764077
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3817756429
Short name T138
Test name
Test status
Simulation time 206091493825 ps
CPU time 145.35 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:04:08 PM PDT 24
Peak memory 192640 kb
Host smart-f6f52e22-035e-489a-aae7-07f10a3858ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817756429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3817756429
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1605439680
Short name T139
Test name
Test status
Simulation time 204738027930 ps
CPU time 268.92 seconds
Started Aug 13 05:02:07 PM PDT 24
Finished Aug 13 05:06:36 PM PDT 24
Peak memory 184760 kb
Host smart-13bdc154-7241-45c0-a7f9-23cd403a856d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605439680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1605439680
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.638460237
Short name T119
Test name
Test status
Simulation time 379225911 ps
CPU time 0.71 seconds
Started Aug 13 05:02:07 PM PDT 24
Finished Aug 13 05:02:07 PM PDT 24
Peak memory 196900 kb
Host smart-1db4c1c8-d162-4712-8fa3-6ba7decc383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638460237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.638460237
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2461246354
Short name T40
Test name
Test status
Simulation time 8491137777 ps
CPU time 21.53 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 206924 kb
Host smart-baa1ec0c-88c5-41ba-a807-d1f33e6fb987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461246354 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2461246354
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1027630515
Short name T113
Test name
Test status
Simulation time 470053301 ps
CPU time 1.26 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196816 kb
Host smart-bd0c9fed-f97e-46d4-9352-64d4eeb84009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027630515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1027630515
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.711642336
Short name T72
Test name
Test status
Simulation time 3783083591 ps
CPU time 12.7 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 214464 kb
Host smart-6c4a9cce-a887-40ee-9841-25d4ddce8b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711642336 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.711642336
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.889334842
Short name T168
Test name
Test status
Simulation time 4711601522 ps
CPU time 31.68 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 198756 kb
Host smart-419a921d-ad29-4f92-8756-ce20b6472cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889334842 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.889334842
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2334212519
Short name T115
Test name
Test status
Simulation time 6294289080 ps
CPU time 23.71 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 206964 kb
Host smart-35724db8-9cfb-4ff6-87bf-adbccdd405d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334212519 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2334212519
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2092038854
Short name T137
Test name
Test status
Simulation time 420018171 ps
CPU time 1.25 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 196828 kb
Host smart-ef61242a-9a85-437a-b4d3-2de9095a822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092038854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2092038854
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.108540387
Short name T107
Test name
Test status
Simulation time 497268576 ps
CPU time 1 seconds
Started Aug 13 05:01:52 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 196920 kb
Host smart-3cf6c29d-759a-4a9f-9a27-f96a7ca19480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108540387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.108540387
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2560607128
Short name T128
Test name
Test status
Simulation time 592988263 ps
CPU time 1 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 196916 kb
Host smart-7b7661cf-3e83-4d58-8483-bdf5eb9e6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560607128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2560607128
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1091107369
Short name T129
Test name
Test status
Simulation time 579630767 ps
CPU time 0.64 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:01 PM PDT 24
Peak memory 196820 kb
Host smart-72fb3506-4e9d-415f-8345-b2681e3fcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091107369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1091107369
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3818870827
Short name T106
Test name
Test status
Simulation time 438070779 ps
CPU time 0.77 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:01:33 PM PDT 24
Peak memory 196836 kb
Host smart-1b2cef83-cd6a-4b57-bbeb-dbb6bd19f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818870827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3818870827
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.229940482
Short name T28
Test name
Test status
Simulation time 512036860 ps
CPU time 1 seconds
Started Aug 13 05:01:50 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 196804 kb
Host smart-d55c0565-c2c5-4d0f-a9a1-c1f132f7f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229940482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.229940482
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2198653631
Short name T132
Test name
Test status
Simulation time 605775336 ps
CPU time 0.82 seconds
Started Aug 13 05:01:51 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 196900 kb
Host smart-4c712edc-89ef-4059-ad32-625129de10df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198653631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2198653631
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2771737521
Short name T153
Test name
Test status
Simulation time 7653868682 ps
CPU time 35.73 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 207008 kb
Host smart-2b7c1c09-ae70-4410-86f2-1a02776b48aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771737521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2771737521
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.158327170
Short name T125
Test name
Test status
Simulation time 562199560 ps
CPU time 0.68 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 196860 kb
Host smart-65a34f6c-0ddb-45e7-a3be-567c05aca5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158327170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.158327170
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.992494373
Short name T31
Test name
Test status
Simulation time 585444963 ps
CPU time 1.05 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 196852 kb
Host smart-0a586e52-f714-4ad9-b0b8-ca80f73f2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992494373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.992494373
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4251101772
Short name T102
Test name
Test status
Simulation time 466458434 ps
CPU time 1.25 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196932 kb
Host smart-e78496ee-e010-4b4f-b3a1-59334228fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251101772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4251101772
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.952301982
Short name T146
Test name
Test status
Simulation time 100132909701 ps
CPU time 36.95 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:36 PM PDT 24
Peak memory 192100 kb
Host smart-7dc385e5-6f0b-4916-981d-dd8f6b7ed7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952301982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.952301982
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.794058002
Short name T133
Test name
Test status
Simulation time 379372642 ps
CPU time 0.71 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 196908 kb
Host smart-25f0b223-1fee-49b0-b037-b28d24273390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794058002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.794058002
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3941403314
Short name T6
Test name
Test status
Simulation time 36328060986 ps
CPU time 16.5 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:16 PM PDT 24
Peak memory 198696 kb
Host smart-e9413a11-2421-462c-a382-25786d204eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941403314 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3941403314
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3098796361
Short name T87
Test name
Test status
Simulation time 1859882683 ps
CPU time 10.53 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:45 PM PDT 24
Peak memory 206884 kb
Host smart-ba7cdcec-60c6-48f5-b109-0baa69afd611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098796361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3098796361
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4258613170
Short name T143
Test name
Test status
Simulation time 227718179280 ps
CPU time 148.22 seconds
Started Aug 13 05:01:48 PM PDT 24
Finished Aug 13 05:04:17 PM PDT 24
Peak memory 193248 kb
Host smart-4c1555d6-8cbf-420b-a104-1cd8bfb689b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258613170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4258613170
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3142714967
Short name T183
Test name
Test status
Simulation time 4456789258 ps
CPU time 15.6 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 214164 kb
Host smart-d232846a-1209-472a-9725-43be21e3f3ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142714967 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3142714967
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3953460077
Short name T123
Test name
Test status
Simulation time 570499199 ps
CPU time 1.48 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 196908 kb
Host smart-2fd71797-7723-482a-830c-c24ce3dbf525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953460077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3953460077
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1345479687
Short name T141
Test name
Test status
Simulation time 387109316 ps
CPU time 0.8 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:01:46 PM PDT 24
Peak memory 196920 kb
Host smart-6d31204b-bac5-47e4-93f8-a914193f969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345479687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1345479687
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2916833792
Short name T3
Test name
Test status
Simulation time 534806370 ps
CPU time 0.64 seconds
Started Aug 13 05:01:57 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 196908 kb
Host smart-0b055b4a-a50b-48cd-a6ec-7ac6f148da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916833792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2916833792
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3457824953
Short name T158
Test name
Test status
Simulation time 3900370732 ps
CPU time 38.85 seconds
Started Aug 13 05:01:51 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 206980 kb
Host smart-11afa8d3-1670-4296-ae19-4e000304b48e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457824953 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3457824953
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.387270726
Short name T30
Test name
Test status
Simulation time 397514333 ps
CPU time 1.24 seconds
Started Aug 13 05:01:51 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 196832 kb
Host smart-249e7b4c-f6f0-45e8-a678-eb012da48240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387270726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.387270726
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2915716696
Short name T43
Test name
Test status
Simulation time 4278293785 ps
CPU time 19.64 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:01:59 PM PDT 24
Peak memory 215108 kb
Host smart-01cfbdd2-3cbe-4ecc-a753-991dee97b775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915716696 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2915716696
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3885746270
Short name T32
Test name
Test status
Simulation time 1871439785 ps
CPU time 12.03 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:13 PM PDT 24
Peak memory 214568 kb
Host smart-e78290a5-d551-45dc-bf6e-999aaa27e955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885746270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3885746270
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.239046189
Short name T156
Test name
Test status
Simulation time 175695713663 ps
CPU time 109.18 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:03:26 PM PDT 24
Peak memory 192092 kb
Host smart-3557175e-c3e8-4a5d-985a-61b400bfcbb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239046189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.239046189
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1792369459
Short name T144
Test name
Test status
Simulation time 114183555679 ps
CPU time 38.91 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:02:17 PM PDT 24
Peak memory 192104 kb
Host smart-21730667-2d59-4761-85b8-f68631841e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792369459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1792369459
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.992527491
Short name T134
Test name
Test status
Simulation time 456499797 ps
CPU time 1.01 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:01:40 PM PDT 24
Peak memory 196832 kb
Host smart-c8846613-ccdb-428f-858d-40bcfdff9a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992527491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.992527491
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2780920543
Short name T82
Test name
Test status
Simulation time 425085678 ps
CPU time 1.24 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 196888 kb
Host smart-d375e918-0d15-480c-9358-f93bf0718a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780920543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2780920543
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2541874692
Short name T10
Test name
Test status
Simulation time 5230646959 ps
CPU time 10.33 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:02:06 PM PDT 24
Peak memory 207008 kb
Host smart-659a58dc-b0f7-4ac2-8fdf-daeb15b70897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541874692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2541874692
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1807198134
Short name T175
Test name
Test status
Simulation time 134399920934 ps
CPU time 102.26 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:03:25 PM PDT 24
Peak memory 198460 kb
Host smart-2de3977b-9cab-4f5d-bfd0-aa34510a36b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807198134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1807198134
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2759953249
Short name T29
Test name
Test status
Simulation time 156711239350 ps
CPU time 122 seconds
Started Aug 13 05:01:53 PM PDT 24
Finished Aug 13 05:03:56 PM PDT 24
Peak memory 193232 kb
Host smart-165a20fc-480a-417b-93bb-439e54cb97f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759953249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2759953249
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3759795214
Short name T127
Test name
Test status
Simulation time 2606162066 ps
CPU time 19.45 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 206988 kb
Host smart-044614b8-b49a-44ea-b7a5-da5ed5f571ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759795214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3759795214
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2114096001
Short name T185
Test name
Test status
Simulation time 517601408 ps
CPU time 1 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 196908 kb
Host smart-7efc2ddf-9083-4cc2-83dc-9368aa234684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114096001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2114096001
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1385985888
Short name T178
Test name
Test status
Simulation time 473666728 ps
CPU time 0.95 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 196868 kb
Host smart-c853320c-7c7a-44ac-a36c-c01698d2f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385985888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1385985888
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1905067559
Short name T151
Test name
Test status
Simulation time 145297896783 ps
CPU time 195.69 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:04:58 PM PDT 24
Peak memory 198452 kb
Host smart-4180747b-fef7-41d9-84d0-ddbab5ae1e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905067559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1905067559
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1278803570
Short name T21
Test name
Test status
Simulation time 478692043 ps
CPU time 1.32 seconds
Started Aug 13 05:01:44 PM PDT 24
Finished Aug 13 05:01:46 PM PDT 24
Peak memory 196952 kb
Host smart-77dfabdb-e287-4814-a7dd-60e682298a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278803570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1278803570
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3064065565
Short name T118
Test name
Test status
Simulation time 475494516 ps
CPU time 1.37 seconds
Started Aug 13 05:01:44 PM PDT 24
Finished Aug 13 05:01:46 PM PDT 24
Peak memory 196908 kb
Host smart-ce80c8af-79db-4264-9446-489dc6e0c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064065565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3064065565
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.243096373
Short name T184
Test name
Test status
Simulation time 8907778375 ps
CPU time 16.38 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:01:59 PM PDT 24
Peak memory 214380 kb
Host smart-e6f05002-6872-432f-8969-e1feb3c33732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243096373 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.243096373
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3346217213
Short name T165
Test name
Test status
Simulation time 4494895192 ps
CPU time 23.21 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 207016 kb
Host smart-ee944ac5-c316-4e92-b33f-80912e64adbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346217213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3346217213
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.322531787
Short name T145
Test name
Test status
Simulation time 410833663 ps
CPU time 0.89 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 196800 kb
Host smart-de83bf22-2be0-417e-9ee7-9f7712c6ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322531787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.322531787
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2497245386
Short name T187
Test name
Test status
Simulation time 577234188 ps
CPU time 1.03 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:01 PM PDT 24
Peak memory 196812 kb
Host smart-fbe98fc3-8d1d-4548-a61a-5d295d3dbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497245386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2497245386
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3803968122
Short name T176
Test name
Test status
Simulation time 167182318397 ps
CPU time 233.22 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:05:28 PM PDT 24
Peak memory 198448 kb
Host smart-3dc035ad-ccf3-4b3f-a9c9-4a8e89656e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803968122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3803968122
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3364666631
Short name T169
Test name
Test status
Simulation time 410628279 ps
CPU time 0.76 seconds
Started Aug 13 05:01:23 PM PDT 24
Finished Aug 13 05:01:24 PM PDT 24
Peak memory 196976 kb
Host smart-5b647606-5e66-4659-893a-36482c8c133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364666631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3364666631
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4055886604
Short name T163
Test name
Test status
Simulation time 2186831937 ps
CPU time 13.16 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 199276 kb
Host smart-9ee534bd-5e61-4cd7-87a6-f48253e61df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055886604 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4055886604
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1931848566
Short name T24
Test name
Test status
Simulation time 479000505 ps
CPU time 1.33 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196916 kb
Host smart-1ab466e3-70d7-48e1-8289-dbef32bb6a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931848566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1931848566
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2179485847
Short name T152
Test name
Test status
Simulation time 537584566 ps
CPU time 0.69 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:01:40 PM PDT 24
Peak memory 196896 kb
Host smart-9327c795-e7b9-43f2-92a7-8eddec1db237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179485847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2179485847
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4248370144
Short name T126
Test name
Test status
Simulation time 427869486 ps
CPU time 0.8 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 196892 kb
Host smart-f2dcdd9b-625e-4858-afe7-064e66659376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248370144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4248370144
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3974718306
Short name T171
Test name
Test status
Simulation time 488027997 ps
CPU time 0.77 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:01:43 PM PDT 24
Peak memory 196812 kb
Host smart-c19327d1-eb33-4a04-bcfb-0eee5386dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974718306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3974718306
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1060474846
Short name T136
Test name
Test status
Simulation time 15962347952 ps
CPU time 40.78 seconds
Started Aug 13 05:01:49 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 214668 kb
Host smart-15ba2527-dfbd-4b26-af0f-27708ca6e646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060474846 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1060474846
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.158090333
Short name T148
Test name
Test status
Simulation time 599255094 ps
CPU time 0.79 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 196796 kb
Host smart-8677469d-4bc6-46f0-9034-0be58ca888a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158090333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.158090333
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2077806986
Short name T4
Test name
Test status
Simulation time 616775766 ps
CPU time 1.5 seconds
Started Aug 13 05:01:58 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 196880 kb
Host smart-76381ce6-241f-4da7-a5ae-2103cbc1b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077806986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2077806986
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1286879755
Short name T180
Test name
Test status
Simulation time 530725090118 ps
CPU time 177.5 seconds
Started Aug 13 05:02:07 PM PDT 24
Finished Aug 13 05:05:05 PM PDT 24
Peak memory 192980 kb
Host smart-85c0b777-cff2-4692-a2d0-5eb4a1759e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286879755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1286879755
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3675418776
Short name T46
Test name
Test status
Simulation time 559302961 ps
CPU time 1.4 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 196852 kb
Host smart-efefd451-e7e6-473f-be2c-8f9e27b45eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675418776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3675418776
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3156867020
Short name T177
Test name
Test status
Simulation time 3809710381 ps
CPU time 23.48 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:23 PM PDT 24
Peak memory 198744 kb
Host smart-6882e167-514c-42fd-83c6-59d83787ee3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156867020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3156867020
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2903562350
Short name T160
Test name
Test status
Simulation time 416158266 ps
CPU time 0.84 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 196800 kb
Host smart-257d9268-9137-496b-9038-8a910e385fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903562350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2903562350
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2111003559
Short name T399
Test name
Test status
Simulation time 4592375749 ps
CPU time 1.84 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 197808 kb
Host smart-3c501348-1192-440d-91e4-35e8aae36d02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111003559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2111003559
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1186228588
Short name T174
Test name
Test status
Simulation time 568636636 ps
CPU time 0.99 seconds
Started Aug 13 05:01:36 PM PDT 24
Finished Aug 13 05:01:37 PM PDT 24
Peak memory 196932 kb
Host smart-bf384527-eeb0-49b8-b38d-ab2d813dca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186228588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1186228588
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3105355035
Short name T173
Test name
Test status
Simulation time 436345081 ps
CPU time 0.72 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 196800 kb
Host smart-4420c48a-086f-426f-9df5-eb93b8d6e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105355035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3105355035
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.358853748
Short name T2
Test name
Test status
Simulation time 540246220 ps
CPU time 0.77 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:01:55 PM PDT 24
Peak memory 196896 kb
Host smart-dba5e6c8-9625-4fcc-a22a-0692f961a314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358853748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.358853748
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2753664227
Short name T172
Test name
Test status
Simulation time 2729574810 ps
CPU time 8.91 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 206932 kb
Host smart-233cd696-5ec6-41a2-935c-00bebd5ca0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753664227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2753664227
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.354706205
Short name T167
Test name
Test status
Simulation time 592733293 ps
CPU time 1.42 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:01:56 PM PDT 24
Peak memory 196836 kb
Host smart-4b1b1a1f-f4a9-40ac-b449-a89c4e1298db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354706205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.354706205
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4113450772
Short name T74
Test name
Test status
Simulation time 4616734339 ps
CPU time 29.47 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:02:24 PM PDT 24
Peak memory 214680 kb
Host smart-1c543f18-2ca9-455a-94a6-5226c1e0ca90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113450772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4113450772
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3727493138
Short name T155
Test name
Test status
Simulation time 428192919 ps
CPU time 0.77 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 196836 kb
Host smart-4c7789ae-1548-4d76-8466-f581dec96d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727493138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3727493138
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3949727379
Short name T26
Test name
Test status
Simulation time 503094314 ps
CPU time 0.97 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 196920 kb
Host smart-74165aee-3f97-4729-9cf8-73c4b2662390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949727379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3949727379
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.392605013
Short name T142
Test name
Test status
Simulation time 363646679 ps
CPU time 0.88 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 196800 kb
Host smart-9427a1f5-51a0-49fd-be7c-e46545b38d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392605013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.392605013
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1643273348
Short name T182
Test name
Test status
Simulation time 585649214 ps
CPU time 0.75 seconds
Started Aug 13 05:01:36 PM PDT 24
Finished Aug 13 05:01:37 PM PDT 24
Peak memory 196912 kb
Host smart-1cf3a115-3a3b-4573-a7f5-53d20e094078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643273348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1643273348
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2032738069
Short name T186
Test name
Test status
Simulation time 381854344 ps
CPU time 0.75 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196820 kb
Host smart-7d362bc3-c966-403f-aa12-71dc433f5c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032738069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2032738069
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1149972932
Short name T150
Test name
Test status
Simulation time 2985118980 ps
CPU time 14.86 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 198868 kb
Host smart-7aa91e4f-b646-4bb3-8504-c4923709edfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149972932 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1149972932
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.831277744
Short name T170
Test name
Test status
Simulation time 445314634 ps
CPU time 0.63 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196876 kb
Host smart-ff64cabd-4461-4540-a20e-29cd3cca852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831277744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.831277744
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3907664487
Short name T53
Test name
Test status
Simulation time 595330826 ps
CPU time 1.79 seconds
Started Aug 13 04:30:17 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 183732 kb
Host smart-8c6108c0-6c04-45bb-9e93-801bbe6f8165
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907664487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3907664487
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3179069614
Short name T55
Test name
Test status
Simulation time 9862212502 ps
CPU time 25.05 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 195364 kb
Host smart-5e894d06-2522-4ad0-adf9-fd0f61c09e6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179069614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3179069614
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1798639570
Short name T331
Test name
Test status
Simulation time 1281987047 ps
CPU time 1.02 seconds
Started Aug 13 04:31:30 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 183644 kb
Host smart-da09b4a5-3535-4fcd-bff9-b6878fe5cdbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798639570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1798639570
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2424528639
Short name T305
Test name
Test status
Simulation time 459854732 ps
CPU time 1.31 seconds
Started Aug 13 04:30:13 PM PDT 24
Finished Aug 13 04:30:14 PM PDT 24
Peak memory 195948 kb
Host smart-48079649-4e70-45d7-97b5-cc3710113a3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424528639 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2424528639
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3567441711
Short name T60
Test name
Test status
Simulation time 345940428 ps
CPU time 0.68 seconds
Started Aug 13 04:31:30 PM PDT 24
Finished Aug 13 04:31:31 PM PDT 24
Peak memory 193252 kb
Host smart-d17bbdd7-e55a-49d8-b9b2-4e9e46c71f61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567441711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3567441711
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3355008658
Short name T287
Test name
Test status
Simulation time 466852097 ps
CPU time 1.24 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:16 PM PDT 24
Peak memory 183656 kb
Host smart-7cda6d66-fe50-4940-9b7f-8134a871c886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355008658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3355008658
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.108533598
Short name T360
Test name
Test status
Simulation time 555275835 ps
CPU time 0.57 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 183496 kb
Host smart-145c66de-9f0d-4e64-aeac-8fc6b8331508
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108533598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.108533598
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1031915173
Short name T369
Test name
Test status
Simulation time 398057602 ps
CPU time 0.91 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 183560 kb
Host smart-3bdb0e58-947c-4c59-a2ef-b3c5089cd06e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031915173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1031915173
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4026210523
Short name T375
Test name
Test status
Simulation time 476298749 ps
CPU time 1.5 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:23 PM PDT 24
Peak memory 198540 kb
Host smart-e7306db8-ddf1-45e1-8936-98a3ba8cd706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026210523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4026210523
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4248600194
Short name T377
Test name
Test status
Simulation time 14151447045 ps
CPU time 9.82 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 183956 kb
Host smart-cd71f223-3f76-4647-862c-36561956c351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248600194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4248600194
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3159408128
Short name T61
Test name
Test status
Simulation time 1218857018 ps
CPU time 2.42 seconds
Started Aug 13 04:30:08 PM PDT 24
Finished Aug 13 04:30:10 PM PDT 24
Peak memory 193132 kb
Host smart-15b84e95-bd92-4833-9dc9-bee7bf5dcd79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159408128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3159408128
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2384804725
Short name T352
Test name
Test status
Simulation time 403447244 ps
CPU time 1.16 seconds
Started Aug 13 04:30:10 PM PDT 24
Finished Aug 13 04:30:12 PM PDT 24
Peak memory 197464 kb
Host smart-a84961f6-af63-42dc-998f-bfb5b78aad6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384804725 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2384804725
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2471205796
Short name T50
Test name
Test status
Simulation time 406530607 ps
CPU time 1.21 seconds
Started Aug 13 04:30:15 PM PDT 24
Finished Aug 13 04:30:16 PM PDT 24
Peak memory 193948 kb
Host smart-2b4b2841-a444-46db-bd38-4c5751ed5bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471205796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2471205796
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1278736876
Short name T408
Test name
Test status
Simulation time 443284885 ps
CPU time 1.15 seconds
Started Aug 13 04:30:02 PM PDT 24
Finished Aug 13 04:30:04 PM PDT 24
Peak memory 183660 kb
Host smart-ad3db834-829d-4312-8753-12d4c67f0d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278736876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1278736876
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1135927152
Short name T349
Test name
Test status
Simulation time 481484691 ps
CPU time 0.93 seconds
Started Aug 13 04:30:21 PM PDT 24
Finished Aug 13 04:30:22 PM PDT 24
Peak memory 183568 kb
Host smart-391c7e21-d6d3-400d-8547-869a37bca5bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135927152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1135927152
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4137346668
Short name T304
Test name
Test status
Simulation time 318805391 ps
CPU time 0.76 seconds
Started Aug 13 04:30:07 PM PDT 24
Finished Aug 13 04:30:08 PM PDT 24
Peak memory 183556 kb
Host smart-69a27d0c-84c5-4028-8681-68d52b34e73d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137346668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4137346668
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1099510743
Short name T65
Test name
Test status
Simulation time 1196771335 ps
CPU time 1.05 seconds
Started Aug 13 04:30:10 PM PDT 24
Finished Aug 13 04:30:11 PM PDT 24
Peak memory 192880 kb
Host smart-3fd33d26-01b8-4efd-812c-bc6d556fa679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099510743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1099510743
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.655186094
Short name T291
Test name
Test status
Simulation time 454633419 ps
CPU time 2.31 seconds
Started Aug 13 04:30:07 PM PDT 24
Finished Aug 13 04:30:15 PM PDT 24
Peak memory 198476 kb
Host smart-ef61e52c-e952-40f9-b759-ce77985897f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655186094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.655186094
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1090834553
Short name T353
Test name
Test status
Simulation time 7991955669 ps
CPU time 9.03 seconds
Started Aug 13 04:30:12 PM PDT 24
Finished Aug 13 04:30:21 PM PDT 24
Peak memory 198296 kb
Host smart-18ea1ed5-107f-4c6c-ae24-a7ac38ca9320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090834553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1090834553
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4030798814
Short name T357
Test name
Test status
Simulation time 372087302 ps
CPU time 0.83 seconds
Started Aug 13 04:30:29 PM PDT 24
Finished Aug 13 04:30:30 PM PDT 24
Peak memory 197204 kb
Host smart-08c446be-1fd2-4b72-8db4-6f8e4c3e21ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030798814 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4030798814
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4223142428
Short name T52
Test name
Test status
Simulation time 395849670 ps
CPU time 1.14 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:37 PM PDT 24
Peak memory 193148 kb
Host smart-6ad214e1-aba2-4e31-bf35-625bd65ec2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223142428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4223142428
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.571734848
Short name T403
Test name
Test status
Simulation time 448573359 ps
CPU time 0.75 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 192848 kb
Host smart-8d71e9b5-777c-4935-aea6-8c2587426fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571734848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.571734848
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2258612294
Short name T66
Test name
Test status
Simulation time 2558143262 ps
CPU time 6.04 seconds
Started Aug 13 04:30:13 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 193908 kb
Host smart-2f8616d0-d528-40f0-bd30-4d3d7f49e286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258612294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2258612294
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1399509897
Short name T383
Test name
Test status
Simulation time 516183942 ps
CPU time 1.64 seconds
Started Aug 13 04:30:41 PM PDT 24
Finished Aug 13 04:30:43 PM PDT 24
Peak memory 197524 kb
Host smart-d8f8fff5-281f-4191-a12d-e07197449545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399509897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1399509897
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2829646403
Short name T407
Test name
Test status
Simulation time 448492139 ps
CPU time 0.76 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 195040 kb
Host smart-74e6a9db-5896-4bbc-993a-4deb87a465c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829646403 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2829646403
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3282338473
Short name T423
Test name
Test status
Simulation time 407986074 ps
CPU time 0.95 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:28 PM PDT 24
Peak memory 193176 kb
Host smart-fa95fdb1-6beb-4fb2-a941-f59825bf7071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282338473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3282338473
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3136800762
Short name T322
Test name
Test status
Simulation time 432830146 ps
CPU time 0.91 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 183652 kb
Host smart-f79d70b4-4fb7-4907-82c5-d569690d4bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136800762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3136800762
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2846100432
Short name T329
Test name
Test status
Simulation time 1386291612 ps
CPU time 1.29 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:23 PM PDT 24
Peak memory 193960 kb
Host smart-b6caefaf-8cad-4b6d-9089-dd0937ec205a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846100432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2846100432
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1765933996
Short name T340
Test name
Test status
Simulation time 423139790 ps
CPU time 1.61 seconds
Started Aug 13 04:30:32 PM PDT 24
Finished Aug 13 04:30:34 PM PDT 24
Peak memory 198480 kb
Host smart-e01920d0-835e-4b03-b660-550d0e86ee74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765933996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1765933996
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3531726087
Short name T417
Test name
Test status
Simulation time 8870293847 ps
CPU time 2.99 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:22 PM PDT 24
Peak memory 198264 kb
Host smart-11d4ee5a-bb50-40c0-93ad-1ddb2d42b505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531726087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3531726087
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1552439683
Short name T420
Test name
Test status
Simulation time 373423706 ps
CPU time 0.8 seconds
Started Aug 13 04:30:34 PM PDT 24
Finished Aug 13 04:30:35 PM PDT 24
Peak memory 196080 kb
Host smart-7fdbfa78-b284-4fd2-b212-e74bdda14347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552439683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1552439683
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.307591081
Short name T335
Test name
Test status
Simulation time 401268982 ps
CPU time 0.78 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 192872 kb
Host smart-5a082ae8-a7bb-42fb-b673-e467950fdebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307591081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.307591081
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3619700845
Short name T292
Test name
Test status
Simulation time 354589576 ps
CPU time 0.79 seconds
Started Aug 13 04:30:35 PM PDT 24
Finished Aug 13 04:30:36 PM PDT 24
Peak memory 183696 kb
Host smart-1ecb3da7-9ed9-4880-9447-7cfe4202a879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619700845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3619700845
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2379812757
Short name T380
Test name
Test status
Simulation time 2327066293 ps
CPU time 6.23 seconds
Started Aug 13 04:30:17 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 194852 kb
Host smart-e2bf9453-977b-4987-b31b-31cc32b0c2fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379812757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2379812757
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.837194175
Short name T372
Test name
Test status
Simulation time 832274544 ps
CPU time 1.43 seconds
Started Aug 13 04:31:40 PM PDT 24
Finished Aug 13 04:31:42 PM PDT 24
Peak memory 198412 kb
Host smart-717aa16c-28fc-4b48-aeeb-cd9bff254f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837194175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.837194175
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1730322284
Short name T189
Test name
Test status
Simulation time 8501189413 ps
CPU time 7.08 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:30 PM PDT 24
Peak memory 198212 kb
Host smart-85c0e2c4-c0f3-4d52-a628-4c0d91072d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730322284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1730322284
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4097671188
Short name T412
Test name
Test status
Simulation time 399676930 ps
CPU time 1.34 seconds
Started Aug 13 04:30:30 PM PDT 24
Finished Aug 13 04:30:37 PM PDT 24
Peak memory 196244 kb
Host smart-1b8c95d4-33f2-479d-8220-d5367159b404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097671188 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.4097671188
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2837630963
Short name T386
Test name
Test status
Simulation time 355907106 ps
CPU time 0.75 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 191680 kb
Host smart-0972f88f-8b27-4266-a4e8-09689d70501a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837630963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2837630963
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.780524950
Short name T299
Test name
Test status
Simulation time 368873811 ps
CPU time 0.63 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 183608 kb
Host smart-29cc69a5-cc8a-4a66-b4a7-4281affcaa8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780524950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.780524950
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1065517902
Short name T359
Test name
Test status
Simulation time 1332604329 ps
CPU time 0.99 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:31:45 PM PDT 24
Peak memory 193264 kb
Host smart-9d04df46-f2aa-46f5-9773-cbbb81acf1db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065517902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1065517902
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1111828197
Short name T321
Test name
Test status
Simulation time 374742013 ps
CPU time 1.54 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 198548 kb
Host smart-636ca186-6624-41eb-9234-f11677553903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111828197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1111828197
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4293088676
Short name T401
Test name
Test status
Simulation time 8592510973 ps
CPU time 4.39 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:22 PM PDT 24
Peak memory 198296 kb
Host smart-7536a11b-7197-44db-9cfe-899ce8d39d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293088676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4293088676
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3258127538
Short name T389
Test name
Test status
Simulation time 457192420 ps
CPU time 1.37 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:28 PM PDT 24
Peak memory 195240 kb
Host smart-b7efe0bb-8c76-4902-9698-83e5865c2e1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258127538 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3258127538
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3659381425
Short name T324
Test name
Test status
Simulation time 433710394 ps
CPU time 1.24 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 193392 kb
Host smart-d47fed02-6f00-4b61-aea2-32a8e3e42c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659381425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3659381425
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4272177949
Short name T350
Test name
Test status
Simulation time 463922097 ps
CPU time 1.11 seconds
Started Aug 13 04:30:24 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 192872 kb
Host smart-1d1856a0-e324-41e4-a426-cc870c155e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272177949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4272177949
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3450957854
Short name T414
Test name
Test status
Simulation time 2577744029 ps
CPU time 1.37 seconds
Started Aug 13 04:30:40 PM PDT 24
Finished Aug 13 04:30:41 PM PDT 24
Peak memory 194660 kb
Host smart-7a5076a5-bf9f-4e06-9e36-a7ae96a53652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450957854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3450957854
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1287512943
Short name T290
Test name
Test status
Simulation time 476220171 ps
CPU time 1.77 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:16 PM PDT 24
Peak memory 195980 kb
Host smart-885b5308-b999-4e0b-ac4f-9c0d545dd900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287512943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1287512943
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2801224695
Short name T422
Test name
Test status
Simulation time 4375056489 ps
CPU time 2.38 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:17 PM PDT 24
Peak memory 196260 kb
Host smart-bdefaf23-767e-4d0d-9b65-f8f5eb7b7d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801224695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2801224695
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1957419100
Short name T356
Test name
Test status
Simulation time 491662947 ps
CPU time 1.29 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 196116 kb
Host smart-5456eb30-6fa7-49f0-83c0-b3502930f50e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957419100 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1957419100
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2250474111
Short name T311
Test name
Test status
Simulation time 454497413 ps
CPU time 0.85 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 192876 kb
Host smart-0fda85b4-7fa1-4e5f-9558-d0754691eac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250474111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2250474111
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3674898721
Short name T371
Test name
Test status
Simulation time 370931404 ps
CPU time 1.06 seconds
Started Aug 13 04:30:11 PM PDT 24
Finished Aug 13 04:30:12 PM PDT 24
Peak memory 192872 kb
Host smart-6e66f9cb-c5ef-4792-b9b8-99a0cbf135e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674898721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3674898721
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4148236194
Short name T415
Test name
Test status
Simulation time 2302783637 ps
CPU time 1.05 seconds
Started Aug 13 04:30:28 PM PDT 24
Finished Aug 13 04:30:29 PM PDT 24
Peak memory 193880 kb
Host smart-24e4d30b-4e1e-495e-b03b-3f9a65034d7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148236194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4148236194
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.282148564
Short name T373
Test name
Test status
Simulation time 547064422 ps
CPU time 2.29 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:29 PM PDT 24
Peak memory 198448 kb
Host smart-1f725bdb-7d90-4e5d-b51a-1997ef26ee49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282148564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.282148564
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.770351573
Short name T391
Test name
Test status
Simulation time 8481640186 ps
CPU time 15.06 seconds
Started Aug 13 04:30:35 PM PDT 24
Finished Aug 13 04:30:50 PM PDT 24
Peak memory 198052 kb
Host smart-5b47833b-e135-4a96-8698-7bef118ffce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770351573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.770351573
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2447935094
Short name T409
Test name
Test status
Simulation time 342502034 ps
CPU time 0.86 seconds
Started Aug 13 04:30:13 PM PDT 24
Finished Aug 13 04:30:14 PM PDT 24
Peak memory 196096 kb
Host smart-55d895eb-028c-4d4d-a776-8cb8d5faf179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447935094 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2447935094
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4104186153
Short name T67
Test name
Test status
Simulation time 490426014 ps
CPU time 0.74 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 191972 kb
Host smart-a2373d92-b660-4710-ac8d-3d2c2a7e8a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104186153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4104186153
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1807136327
Short name T318
Test name
Test status
Simulation time 323070966 ps
CPU time 1.02 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:23 PM PDT 24
Peak memory 192880 kb
Host smart-2e261e99-9957-48b2-87bf-a2fd3af89701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807136327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1807136327
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.551132601
Short name T348
Test name
Test status
Simulation time 2597360347 ps
CPU time 2.19 seconds
Started Aug 13 04:30:16 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 195324 kb
Host smart-537875a3-554b-4e90-8152-32eedfd79679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551132601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.551132601
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2339167182
Short name T320
Test name
Test status
Simulation time 785935585 ps
CPU time 1.62 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 198544 kb
Host smart-54ef1ffc-a4b2-4f4c-9ec3-004afc7fa589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339167182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2339167182
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2344094651
Short name T384
Test name
Test status
Simulation time 4741041490 ps
CPU time 4.49 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 197564 kb
Host smart-63d63e62-53f1-41f9-8c27-fa68ac26f6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344094651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2344094651
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1840503230
Short name T398
Test name
Test status
Simulation time 598375524 ps
CPU time 1.07 seconds
Started Aug 13 04:30:38 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 198364 kb
Host smart-05a3d70f-0cda-40e5-8dbf-f9e61c66ad1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840503230 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1840503230
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2246158993
Short name T393
Test name
Test status
Simulation time 504561898 ps
CPU time 1.25 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 193268 kb
Host smart-5ecef8ea-9d34-4518-9b76-b2737aba9c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246158993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2246158993
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4242755667
Short name T379
Test name
Test status
Simulation time 401522069 ps
CPU time 0.68 seconds
Started Aug 13 04:30:34 PM PDT 24
Finished Aug 13 04:30:35 PM PDT 24
Peak memory 183736 kb
Host smart-0a6b5eaa-8f01-4067-a983-b6136dd7dfdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242755667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4242755667
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3566816765
Short name T382
Test name
Test status
Simulation time 1254215602 ps
CPU time 3.65 seconds
Started Aug 13 04:30:36 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 183912 kb
Host smart-c58bc337-1284-4bf0-a7b6-199a7b4d2391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566816765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3566816765
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4036635926
Short name T387
Test name
Test status
Simulation time 534857890 ps
CPU time 1.74 seconds
Started Aug 13 04:30:09 PM PDT 24
Finished Aug 13 04:30:11 PM PDT 24
Peak memory 198312 kb
Host smart-f9453e06-3fe1-41d7-bef3-ae43b4ad3b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036635926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4036635926
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3424185824
Short name T37
Test name
Test status
Simulation time 4430374375 ps
CPU time 2.3 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:29 PM PDT 24
Peak memory 196768 kb
Host smart-cbb922a4-39a1-44dd-aad2-bc78ed0c1f28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424185824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3424185824
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4065097761
Short name T309
Test name
Test status
Simulation time 470803412 ps
CPU time 1.32 seconds
Started Aug 13 04:30:29 PM PDT 24
Finished Aug 13 04:30:30 PM PDT 24
Peak memory 196296 kb
Host smart-a9d6376d-3fe7-461f-8ab2-836a7aba59dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065097761 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4065097761
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2928184035
Short name T394
Test name
Test status
Simulation time 323814008 ps
CPU time 0.67 seconds
Started Aug 13 04:30:29 PM PDT 24
Finished Aug 13 04:30:30 PM PDT 24
Peak memory 193108 kb
Host smart-830f1ac7-e37a-4641-ac91-dceff8c7274c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928184035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2928184035
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2564769959
Short name T316
Test name
Test status
Simulation time 446394099 ps
CPU time 1.14 seconds
Started Aug 13 04:30:29 PM PDT 24
Finished Aug 13 04:30:31 PM PDT 24
Peak memory 183600 kb
Host smart-2c3ff98e-742a-4e38-b1bc-a33374e972de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564769959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2564769959
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1142816291
Short name T337
Test name
Test status
Simulation time 2470408975 ps
CPU time 4.7 seconds
Started Aug 13 04:30:28 PM PDT 24
Finished Aug 13 04:30:33 PM PDT 24
Peak memory 195016 kb
Host smart-426c808f-2027-48dc-91b2-c4fa213a17ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142816291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1142816291
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3823863465
Short name T325
Test name
Test status
Simulation time 449661897 ps
CPU time 1.91 seconds
Started Aug 13 04:30:24 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 198452 kb
Host smart-2d018535-d3c6-47e8-8c83-8f23a3a8ade2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823863465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3823863465
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2211020408
Short name T395
Test name
Test status
Simulation time 4440982731 ps
CPU time 3.65 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 197880 kb
Host smart-74bc9570-4121-4526-b50e-56a20a945aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211020408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2211020408
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3635559317
Short name T308
Test name
Test status
Simulation time 344978251 ps
CPU time 0.93 seconds
Started Aug 13 04:30:30 PM PDT 24
Finished Aug 13 04:30:31 PM PDT 24
Peak memory 196504 kb
Host smart-200233c2-9100-413b-9c32-cc6e546db06b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635559317 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3635559317
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2567116213
Short name T39
Test name
Test status
Simulation time 430086605 ps
CPU time 0.91 seconds
Started Aug 13 04:30:43 PM PDT 24
Finished Aug 13 04:30:44 PM PDT 24
Peak memory 192876 kb
Host smart-1686126c-2b69-4b64-bc2e-d339cf7daa42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567116213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2567116213
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2473053038
Short name T385
Test name
Test status
Simulation time 388316337 ps
CPU time 0.81 seconds
Started Aug 13 04:30:31 PM PDT 24
Finished Aug 13 04:30:32 PM PDT 24
Peak memory 192896 kb
Host smart-a28a5dcd-37c8-4bc8-80d7-e8cfaa3cc4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473053038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2473053038
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1244103008
Short name T34
Test name
Test status
Simulation time 1533047486 ps
CPU time 1.56 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 193960 kb
Host smart-2cc3d8bc-6e95-4fe5-83f3-1241b49b5ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244103008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1244103008
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3735496827
Short name T293
Test name
Test status
Simulation time 481765848 ps
CPU time 1.67 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:28 PM PDT 24
Peak memory 198464 kb
Host smart-83709648-00f5-44f7-aec3-c71bf788cc02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735496827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3735496827
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3557176134
Short name T191
Test name
Test status
Simulation time 4692741677 ps
CPU time 8.35 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:32 PM PDT 24
Peak memory 197812 kb
Host smart-68f1918a-20da-4012-bd37-c7a5f207dd0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557176134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3557176134
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2932624776
Short name T59
Test name
Test status
Simulation time 491288356 ps
CPU time 1.48 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 194344 kb
Host smart-0cf2203b-d4c6-4d48-b642-064d2b179fe9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932624776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2932624776
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2331391367
Short name T334
Test name
Test status
Simulation time 13899105749 ps
CPU time 27.73 seconds
Started Aug 13 04:30:09 PM PDT 24
Finished Aug 13 04:30:36 PM PDT 24
Peak memory 192200 kb
Host smart-b1bcfc3b-afae-4001-9bc0-2880e3f19908
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331391367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2331391367
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1752253505
Short name T362
Test name
Test status
Simulation time 890699951 ps
CPU time 1.93 seconds
Started Aug 13 04:30:04 PM PDT 24
Finished Aug 13 04:30:06 PM PDT 24
Peak memory 192084 kb
Host smart-ecb0c879-2008-4b32-ba5c-133a0c16f4e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752253505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1752253505
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3295432522
Short name T392
Test name
Test status
Simulation time 626267624 ps
CPU time 0.85 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 196428 kb
Host smart-2c98197d-a72f-46be-9cb3-17a315f29c79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295432522 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3295432522
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3876299101
Short name T69
Test name
Test status
Simulation time 405978900 ps
CPU time 0.86 seconds
Started Aug 13 04:29:58 PM PDT 24
Finished Aug 13 04:29:58 PM PDT 24
Peak memory 193956 kb
Host smart-bedac16a-8436-4ed2-8ad8-1d2c3605c01f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876299101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3876299101
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.448815550
Short name T300
Test name
Test status
Simulation time 301057117 ps
CPU time 0.93 seconds
Started Aug 13 04:30:15 PM PDT 24
Finished Aug 13 04:30:16 PM PDT 24
Peak memory 183776 kb
Host smart-3ca6e710-fb83-4b1a-b2ba-66916a52e172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448815550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.448815550
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3285790610
Short name T368
Test name
Test status
Simulation time 479620137 ps
CPU time 0.87 seconds
Started Aug 13 04:30:08 PM PDT 24
Finished Aug 13 04:30:09 PM PDT 24
Peak memory 183544 kb
Host smart-15502a1e-e862-43ed-992a-1ecc9ce49152
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285790610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3285790610
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3946216841
Short name T342
Test name
Test status
Simulation time 378999308 ps
CPU time 0.69 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 183592 kb
Host smart-d087c329-3663-4ebd-a180-2be9e7c1a0ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946216841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3946216841
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.713435741
Short name T396
Test name
Test status
Simulation time 1319925522 ps
CPU time 1.83 seconds
Started Aug 13 04:30:07 PM PDT 24
Finished Aug 13 04:30:09 PM PDT 24
Peak memory 193304 kb
Host smart-2b5e22b3-5973-4bd4-90d0-fb34c0b33677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713435741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.713435741
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1721821438
Short name T301
Test name
Test status
Simulation time 401656998 ps
CPU time 2.47 seconds
Started Aug 13 04:30:08 PM PDT 24
Finished Aug 13 04:30:11 PM PDT 24
Peak memory 198552 kb
Host smart-54fb98fd-c0f6-4037-b2b7-28c36b346abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721821438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1721821438
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3890421521
Short name T38
Test name
Test status
Simulation time 8364504699 ps
CPU time 6.97 seconds
Started Aug 13 04:29:59 PM PDT 24
Finished Aug 13 04:30:06 PM PDT 24
Peak memory 198208 kb
Host smart-01faaf65-a82b-491f-a26a-c586d88662e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890421521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3890421521
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.545574020
Short name T288
Test name
Test status
Simulation time 453573553 ps
CPU time 0.67 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 183628 kb
Host smart-fe6ebaee-e3bc-47a6-b75e-674097860b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545574020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.545574020
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1926545030
Short name T319
Test name
Test status
Simulation time 371909614 ps
CPU time 1.03 seconds
Started Aug 13 04:30:37 PM PDT 24
Finished Aug 13 04:30:38 PM PDT 24
Peak memory 183648 kb
Host smart-117e142d-9018-42d4-a44c-5cb8c4ff73b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926545030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1926545030
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4001754069
Short name T376
Test name
Test status
Simulation time 483681547 ps
CPU time 0.93 seconds
Started Aug 13 04:30:34 PM PDT 24
Finished Aug 13 04:30:35 PM PDT 24
Peak memory 183648 kb
Host smart-c6a7b861-71b3-4a43-84a0-574e81d91058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001754069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4001754069
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4240799022
Short name T418
Test name
Test status
Simulation time 518452308 ps
CPU time 0.75 seconds
Started Aug 13 04:30:38 PM PDT 24
Finished Aug 13 04:30:39 PM PDT 24
Peak memory 192868 kb
Host smart-dca2a689-63cf-4b82-8564-bf8e04dfde84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240799022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4240799022
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1661432644
Short name T306
Test name
Test status
Simulation time 401063885 ps
CPU time 0.69 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 183968 kb
Host smart-db1684d5-2291-4bf9-ba11-fbaff85c95fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661432644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1661432644
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.586436383
Short name T425
Test name
Test status
Simulation time 410563240 ps
CPU time 1.24 seconds
Started Aug 13 04:30:35 PM PDT 24
Finished Aug 13 04:30:37 PM PDT 24
Peak memory 192856 kb
Host smart-eccb770c-e430-482e-aa52-6efa168d77ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586436383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.586436383
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1481842533
Short name T310
Test name
Test status
Simulation time 484664298 ps
CPU time 0.78 seconds
Started Aug 13 04:30:28 PM PDT 24
Finished Aug 13 04:30:29 PM PDT 24
Peak memory 183572 kb
Host smart-b231bbcd-c9fe-468c-9b71-fb1caf107182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481842533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1481842533
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.859376686
Short name T289
Test name
Test status
Simulation time 457296797 ps
CPU time 0.69 seconds
Started Aug 13 04:30:40 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 183628 kb
Host smart-040e38ed-efeb-4498-8594-56df7d79b002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859376686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.859376686
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1291580369
Short name T363
Test name
Test status
Simulation time 432465682 ps
CPU time 1.21 seconds
Started Aug 13 04:30:37 PM PDT 24
Finished Aug 13 04:30:39 PM PDT 24
Peak memory 183648 kb
Host smart-4850c354-8576-408f-b6d3-e2d119e46bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291580369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1291580369
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3166864271
Short name T344
Test name
Test status
Simulation time 482677127 ps
CPU time 1.22 seconds
Started Aug 13 04:30:38 PM PDT 24
Finished Aug 13 04:30:39 PM PDT 24
Peak memory 192872 kb
Host smart-fe6539d0-1943-4f36-b29d-ab977da253f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166864271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3166864271
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2047573069
Short name T56
Test name
Test status
Simulation time 632775464 ps
CPU time 1.33 seconds
Started Aug 13 04:31:34 PM PDT 24
Finished Aug 13 04:31:35 PM PDT 24
Peak memory 183644 kb
Host smart-72ee978b-2588-43bf-9791-5708e98f5ed4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047573069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2047573069
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3335113865
Short name T402
Test name
Test status
Simulation time 7058044209 ps
CPU time 9.46 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 183960 kb
Host smart-e5a8fc43-865b-46c5-8516-3e709c030222
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335113865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3335113865
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3631248882
Short name T405
Test name
Test status
Simulation time 890009405 ps
CPU time 0.94 seconds
Started Aug 13 04:29:59 PM PDT 24
Finished Aug 13 04:30:00 PM PDT 24
Peak memory 193112 kb
Host smart-5390046d-ec80-4ea3-bc79-a4a0cd960daa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631248882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3631248882
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3867959996
Short name T346
Test name
Test status
Simulation time 444416933 ps
CPU time 0.83 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 196040 kb
Host smart-fee8c375-3593-42c6-8e4a-bd6708887a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867959996 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3867959996
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2106601681
Short name T54
Test name
Test status
Simulation time 514011752 ps
CPU time 1.24 seconds
Started Aug 13 04:31:17 PM PDT 24
Finished Aug 13 04:31:19 PM PDT 24
Peak memory 192500 kb
Host smart-decc639a-df1c-445c-929d-5dbd700bafce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106601681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2106601681
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2902114579
Short name T339
Test name
Test status
Simulation time 336012712 ps
CPU time 0.69 seconds
Started Aug 13 04:30:38 PM PDT 24
Finished Aug 13 04:30:38 PM PDT 24
Peak memory 183648 kb
Host smart-3ca640ed-0c1d-4d60-b11b-f3a4b942ad09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902114579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2902114579
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.111071313
Short name T351
Test name
Test status
Simulation time 424767635 ps
CPU time 0.82 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 183584 kb
Host smart-3aa9b060-e68e-4e5e-9e2f-c944bd505155
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111071313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.111071313
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2897718475
Short name T327
Test name
Test status
Simulation time 356337289 ps
CPU time 0.93 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:28 PM PDT 24
Peak memory 183604 kb
Host smart-efe26507-ad22-4fe4-9b2c-fa4c2a7894a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897718475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2897718475
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1067574195
Short name T390
Test name
Test status
Simulation time 1588208497 ps
CPU time 2.33 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:21 PM PDT 24
Peak memory 193232 kb
Host smart-31e4da39-2c6e-4f0a-9128-2bf47b766304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067574195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1067574195
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2454524487
Short name T426
Test name
Test status
Simulation time 676618642 ps
CPU time 2.51 seconds
Started Aug 13 04:30:40 PM PDT 24
Finished Aug 13 04:30:43 PM PDT 24
Peak memory 198488 kb
Host smart-8dd52bd4-5e34-4f0e-854b-6a13c786a1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454524487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2454524487
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3381052992
Short name T190
Test name
Test status
Simulation time 8241305685 ps
CPU time 7.36 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 198136 kb
Host smart-1c27503e-4776-45b6-ac57-5f5ad651ff12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381052992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3381052992
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2086830856
Short name T317
Test name
Test status
Simulation time 399416458 ps
CPU time 0.67 seconds
Started Aug 13 04:30:42 PM PDT 24
Finished Aug 13 04:30:43 PM PDT 24
Peak memory 192820 kb
Host smart-7971d829-84d5-4e84-9238-58231f9a27b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086830856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2086830856
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1186967769
Short name T295
Test name
Test status
Simulation time 324478302 ps
CPU time 0.62 seconds
Started Aug 13 04:30:24 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 183736 kb
Host smart-71f15170-7cdd-4481-93a8-7c2069e11842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186967769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1186967769
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.421881292
Short name T381
Test name
Test status
Simulation time 427548013 ps
CPU time 0.89 seconds
Started Aug 13 04:30:45 PM PDT 24
Finished Aug 13 04:30:46 PM PDT 24
Peak memory 183644 kb
Host smart-d06c7717-473e-42bb-9e82-6391c39cd504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421881292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.421881292
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2258705002
Short name T323
Test name
Test status
Simulation time 494226908 ps
CPU time 1.23 seconds
Started Aug 13 04:30:38 PM PDT 24
Finished Aug 13 04:30:39 PM PDT 24
Peak memory 192880 kb
Host smart-6787bdac-cee7-490b-8cc3-7984eb759881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258705002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2258705002
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1607832449
Short name T358
Test name
Test status
Simulation time 609252659 ps
CPU time 0.58 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 183628 kb
Host smart-eda5435d-7ee5-4742-af31-c796b18e453f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607832449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1607832449
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4068677090
Short name T400
Test name
Test status
Simulation time 377396936 ps
CPU time 0.81 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:30:49 PM PDT 24
Peak memory 192860 kb
Host smart-8b86ab43-3fd0-4c88-9466-16964aa25fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068677090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4068677090
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.223063881
Short name T314
Test name
Test status
Simulation time 514604246 ps
CPU time 0.7 seconds
Started Aug 13 04:30:31 PM PDT 24
Finished Aug 13 04:30:32 PM PDT 24
Peak memory 183620 kb
Host smart-e80711d1-46ab-4714-89e8-eb759e5539b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223063881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.223063881
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.884144619
Short name T286
Test name
Test status
Simulation time 309064295 ps
CPU time 0.63 seconds
Started Aug 13 04:30:34 PM PDT 24
Finished Aug 13 04:30:35 PM PDT 24
Peak memory 183616 kb
Host smart-5bd0e07b-0189-49e2-a8c8-625bd35cf95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884144619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.884144619
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2658498952
Short name T365
Test name
Test status
Simulation time 307002149 ps
CPU time 0.62 seconds
Started Aug 13 04:30:31 PM PDT 24
Finished Aug 13 04:30:31 PM PDT 24
Peak memory 192880 kb
Host smart-434798bc-c272-4610-99ea-a3d7fda96df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658498952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2658498952
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2510416752
Short name T328
Test name
Test status
Simulation time 466916281 ps
CPU time 1.32 seconds
Started Aug 13 04:30:43 PM PDT 24
Finished Aug 13 04:30:44 PM PDT 24
Peak memory 183660 kb
Host smart-303a6475-8d00-42fb-97c2-5d2ade49c218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510416752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2510416752
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.149788265
Short name T58
Test name
Test status
Simulation time 648353343 ps
CPU time 1.47 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:16 PM PDT 24
Peak memory 194920 kb
Host smart-566291b5-e13e-46bc-8654-0bbddd89e628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149788265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.149788265
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1734225755
Short name T57
Test name
Test status
Simulation time 12905845894 ps
CPU time 24.59 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 192124 kb
Host smart-a225b04e-a61f-479c-96f0-d3172536688a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734225755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1734225755
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.762317945
Short name T361
Test name
Test status
Simulation time 808689643 ps
CPU time 1.66 seconds
Started Aug 13 04:30:03 PM PDT 24
Finished Aug 13 04:30:05 PM PDT 24
Peak memory 183708 kb
Host smart-fdd2199c-6cf7-45d7-9b3a-58390634346e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762317945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.762317945
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3116827803
Short name T355
Test name
Test status
Simulation time 433581782 ps
CPU time 1.03 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 196324 kb
Host smart-60be7dd1-3336-4efc-9add-c75469344368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116827803 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3116827803
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3706952248
Short name T51
Test name
Test status
Simulation time 303177423 ps
CPU time 0.97 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 193020 kb
Host smart-61074acd-a5fa-44d9-acf5-6e764b55eda7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706952248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3706952248
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.393143466
Short name T303
Test name
Test status
Simulation time 281293869 ps
CPU time 0.95 seconds
Started Aug 13 04:30:26 PM PDT 24
Finished Aug 13 04:30:27 PM PDT 24
Peak memory 192828 kb
Host smart-ec623cea-5db6-4ddc-b036-b7762f0077e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393143466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.393143466
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4032517168
Short name T285
Test name
Test status
Simulation time 348722957 ps
CPU time 0.97 seconds
Started Aug 13 04:30:04 PM PDT 24
Finished Aug 13 04:30:05 PM PDT 24
Peak memory 183568 kb
Host smart-a72908b0-e473-49ba-8de1-0c09dce94c4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032517168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4032517168
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2204916798
Short name T294
Test name
Test status
Simulation time 431210498 ps
CPU time 1.12 seconds
Started Aug 13 04:30:13 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 183580 kb
Host smart-87435795-2840-4073-91f2-0b6eebaf15d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204916798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2204916798
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1403961911
Short name T63
Test name
Test status
Simulation time 1100347567 ps
CPU time 1.39 seconds
Started Aug 13 04:30:15 PM PDT 24
Finished Aug 13 04:30:17 PM PDT 24
Peak memory 193472 kb
Host smart-90da153e-7e78-4a6d-9970-cb893e1d539e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403961911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1403961911
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2168811150
Short name T312
Test name
Test status
Simulation time 500800986 ps
CPU time 1.71 seconds
Started Aug 13 04:30:16 PM PDT 24
Finished Aug 13 04:30:18 PM PDT 24
Peak memory 198492 kb
Host smart-16f936ec-098b-4b11-8c0e-4d066cd702df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168811150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2168811150
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3661333376
Short name T413
Test name
Test status
Simulation time 4704666737 ps
CPU time 2.35 seconds
Started Aug 13 04:30:15 PM PDT 24
Finished Aug 13 04:30:18 PM PDT 24
Peak memory 197440 kb
Host smart-9923ebd8-8f5d-47e8-9438-45c701937b83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661333376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3661333376
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3561779728
Short name T421
Test name
Test status
Simulation time 501755039 ps
CPU time 0.92 seconds
Started Aug 13 04:30:43 PM PDT 24
Finished Aug 13 04:30:44 PM PDT 24
Peak memory 183604 kb
Host smart-2d0f785d-6626-4b5e-a3ea-38865f9be752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561779728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3561779728
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.47324128
Short name T336
Test name
Test status
Simulation time 420829868 ps
CPU time 1.14 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 192808 kb
Host smart-d38d0cc8-48b3-41f1-92bb-a0512efb5d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47324128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.47324128
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1117729928
Short name T297
Test name
Test status
Simulation time 359395252 ps
CPU time 0.68 seconds
Started Aug 13 04:30:41 PM PDT 24
Finished Aug 13 04:30:42 PM PDT 24
Peak memory 183644 kb
Host smart-1c2a076d-7211-47e1-98f4-cb4c3662d824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117729928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1117729928
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.482693206
Short name T354
Test name
Test status
Simulation time 339946098 ps
CPU time 1.01 seconds
Started Aug 13 04:30:40 PM PDT 24
Finished Aug 13 04:30:41 PM PDT 24
Peak memory 183584 kb
Host smart-d47368eb-619b-40ef-8168-d1553531a510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482693206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.482693206
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.62713157
Short name T404
Test name
Test status
Simulation time 452317313 ps
CPU time 0.72 seconds
Started Aug 13 04:30:45 PM PDT 24
Finished Aug 13 04:30:46 PM PDT 24
Peak memory 192876 kb
Host smart-cac5e40d-6e09-4553-8cfb-b216d2973d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62713157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.62713157
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3882670127
Short name T345
Test name
Test status
Simulation time 301087744 ps
CPU time 0.67 seconds
Started Aug 13 04:30:47 PM PDT 24
Finished Aug 13 04:30:48 PM PDT 24
Peak memory 183656 kb
Host smart-85aa68b4-351f-4f9b-9383-f3a27681b385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882670127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3882670127
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2520099031
Short name T315
Test name
Test status
Simulation time 311705111 ps
CPU time 0.64 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:30:54 PM PDT 24
Peak memory 192896 kb
Host smart-6eb4103f-43bc-49e2-8a4b-ae25dbff3a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520099031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2520099031
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1091730620
Short name T307
Test name
Test status
Simulation time 340514280 ps
CPU time 0.64 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 183648 kb
Host smart-f74dd06a-828e-469f-827c-e5e1c7ea455a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091730620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1091730620
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1181790695
Short name T330
Test name
Test status
Simulation time 510151643 ps
CPU time 1.26 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:40 PM PDT 24
Peak memory 183628 kb
Host smart-2ff4a73f-fe21-43bc-91f0-66b1459367c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181790695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1181790695
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.68243522
Short name T298
Test name
Test status
Simulation time 417861719 ps
CPU time 0.85 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:30:51 PM PDT 24
Peak memory 192844 kb
Host smart-7fee281a-c9bf-4760-990c-af826554550a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68243522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.68243522
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4254477697
Short name T302
Test name
Test status
Simulation time 412961530 ps
CPU time 1.21 seconds
Started Aug 13 04:30:20 PM PDT 24
Finished Aug 13 04:30:22 PM PDT 24
Peak memory 195680 kb
Host smart-c0252a70-1bdf-4e02-bedc-0cf13531ccbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254477697 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4254477697
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4335173
Short name T364
Test name
Test status
Simulation time 369976526 ps
CPU time 0.71 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 193172 kb
Host smart-d75b981c-ada8-4cd9-ad9b-652f879c541e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4335173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4335173
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2413738285
Short name T416
Test name
Test status
Simulation time 442469455 ps
CPU time 1.25 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:23 PM PDT 24
Peak memory 183588 kb
Host smart-de96a27e-b8d9-471f-bd38-554b92220f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413738285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2413738285
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2257381248
Short name T62
Test name
Test status
Simulation time 1297091080 ps
CPU time 1.3 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 183640 kb
Host smart-bda97028-35df-43c1-9f81-b04dc3a72e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257381248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2257381248
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.922434281
Short name T333
Test name
Test status
Simulation time 437202363 ps
CPU time 2.3 seconds
Started Aug 13 04:31:41 PM PDT 24
Finished Aug 13 04:31:43 PM PDT 24
Peak memory 198444 kb
Host smart-fb939a76-5b5e-4515-8d14-98757e5be943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922434281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.922434281
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.643708414
Short name T374
Test name
Test status
Simulation time 8129901990 ps
CPU time 14.03 seconds
Started Aug 13 04:30:29 PM PDT 24
Finished Aug 13 04:30:43 PM PDT 24
Peak memory 198144 kb
Host smart-56a32c01-4390-4037-b468-b325beaf63a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643708414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.643708414
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1222540041
Short name T343
Test name
Test status
Simulation time 433078128 ps
CPU time 0.87 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 195952 kb
Host smart-9aa911d6-980a-4371-a33e-315ccfaf0afd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222540041 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1222540041
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2207847166
Short name T49
Test name
Test status
Simulation time 507246240 ps
CPU time 1.26 seconds
Started Aug 13 04:30:15 PM PDT 24
Finished Aug 13 04:30:16 PM PDT 24
Peak memory 193036 kb
Host smart-b3db6fd5-8184-4601-8192-28275ab1700c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207847166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2207847166
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.423844865
Short name T332
Test name
Test status
Simulation time 404320391 ps
CPU time 0.77 seconds
Started Aug 13 04:30:25 PM PDT 24
Finished Aug 13 04:30:26 PM PDT 24
Peak memory 192808 kb
Host smart-c358ea3f-0d46-4a0e-bf0f-ef04bc11af65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423844865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.423844865
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3334534716
Short name T341
Test name
Test status
Simulation time 2630128555 ps
CPU time 6.69 seconds
Started Aug 13 04:31:36 PM PDT 24
Finished Aug 13 04:31:43 PM PDT 24
Peak memory 193980 kb
Host smart-4db179d5-d284-4bea-b898-55b8f6cb585a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334534716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3334534716
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1129662101
Short name T388
Test name
Test status
Simulation time 580553633 ps
CPU time 1.54 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 198444 kb
Host smart-1969483e-c524-45e6-ac64-6a2ad11d25ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129662101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1129662101
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1783346256
Short name T366
Test name
Test status
Simulation time 4387653167 ps
CPU time 2.52 seconds
Started Aug 13 04:30:19 PM PDT 24
Finished Aug 13 04:30:22 PM PDT 24
Peak memory 197832 kb
Host smart-2a6688c8-77e8-4109-81e8-461b2c4cd0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783346256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1783346256
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3991719429
Short name T313
Test name
Test status
Simulation time 560050861 ps
CPU time 0.93 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 197704 kb
Host smart-75150622-0b08-4657-b09a-0409dae698d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991719429 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3991719429
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.788686209
Short name T410
Test name
Test status
Simulation time 511185808 ps
CPU time 0.73 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 193096 kb
Host smart-f758dfc6-0e9d-49f1-93f0-efa149bc7c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788686209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.788686209
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3239575098
Short name T397
Test name
Test status
Simulation time 530480073 ps
CPU time 0.7 seconds
Started Aug 13 04:30:09 PM PDT 24
Finished Aug 13 04:30:10 PM PDT 24
Peak memory 192856 kb
Host smart-291bf03a-1e6d-42ff-9498-35bd24377cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239575098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3239575098
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.390413288
Short name T326
Test name
Test status
Simulation time 2579808222 ps
CPU time 1.38 seconds
Started Aug 13 04:30:12 PM PDT 24
Finished Aug 13 04:30:14 PM PDT 24
Peak memory 195056 kb
Host smart-ad95bac1-fc9b-4291-9eaf-e561d3155c9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390413288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.390413288
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3479274808
Short name T424
Test name
Test status
Simulation time 437422193 ps
CPU time 1.5 seconds
Started Aug 13 04:30:17 PM PDT 24
Finished Aug 13 04:30:19 PM PDT 24
Peak memory 198472 kb
Host smart-8403c71d-7cbb-4f38-a874-e2f176b04333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479274808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3479274808
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1302280877
Short name T419
Test name
Test status
Simulation time 8616432137 ps
CPU time 3.27 seconds
Started Aug 13 04:30:21 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 198168 kb
Host smart-4bb7f04a-c1f5-455c-a7b6-a3b74b90dab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302280877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1302280877
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2468571854
Short name T35
Test name
Test status
Simulation time 366409837 ps
CPU time 0.82 seconds
Started Aug 13 04:30:17 PM PDT 24
Finished Aug 13 04:30:18 PM PDT 24
Peak memory 196576 kb
Host smart-ffe805a4-4de2-40b5-b660-b2d1bbc61f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468571854 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2468571854
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.842747148
Short name T68
Test name
Test status
Simulation time 428530207 ps
CPU time 1.2 seconds
Started Aug 13 04:30:16 PM PDT 24
Finished Aug 13 04:30:17 PM PDT 24
Peak memory 192000 kb
Host smart-7348ad32-5f86-47ae-96d4-4b8f3de123a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842747148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.842747148
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.27388180
Short name T338
Test name
Test status
Simulation time 279967508 ps
CPU time 0.74 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:28 PM PDT 24
Peak memory 183684 kb
Host smart-ad2e93c2-1e7d-46e7-b704-0318ac3e346b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.27388180
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3171234566
Short name T367
Test name
Test status
Simulation time 1602262176 ps
CPU time 1.16 seconds
Started Aug 13 04:30:36 PM PDT 24
Finished Aug 13 04:30:38 PM PDT 24
Peak memory 193708 kb
Host smart-73712049-108e-4f04-b694-90d8c43b10ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171234566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3171234566
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3539180790
Short name T296
Test name
Test status
Simulation time 613918566 ps
CPU time 1.85 seconds
Started Aug 13 04:30:23 PM PDT 24
Finished Aug 13 04:30:25 PM PDT 24
Peak memory 198572 kb
Host smart-191f124a-3808-4ff2-bb24-09e6829f7e45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539180790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3539180790
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2547159751
Short name T406
Test name
Test status
Simulation time 4378690047 ps
CPU time 2.21 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:24 PM PDT 24
Peak memory 197740 kb
Host smart-f3da2842-fd5a-48a8-a886-87e85ee91be3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547159751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2547159751
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1730576026
Short name T411
Test name
Test status
Simulation time 421779692 ps
CPU time 0.88 seconds
Started Aug 13 04:30:22 PM PDT 24
Finished Aug 13 04:30:23 PM PDT 24
Peak memory 198204 kb
Host smart-dc012d86-0dcb-467a-9def-d345dcf01c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730576026 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1730576026
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1386492447
Short name T47
Test name
Test status
Simulation time 482046802 ps
CPU time 1.22 seconds
Started Aug 13 04:30:14 PM PDT 24
Finished Aug 13 04:30:15 PM PDT 24
Peak memory 191988 kb
Host smart-3130bbf1-675f-4a27-8161-815000f51e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386492447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1386492447
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2016377687
Short name T378
Test name
Test status
Simulation time 444868261 ps
CPU time 1.15 seconds
Started Aug 13 04:30:16 PM PDT 24
Finished Aug 13 04:30:18 PM PDT 24
Peak memory 183636 kb
Host smart-61e9bd73-e07a-4fa2-905c-bd0ed4b40303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016377687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2016377687
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1579296499
Short name T370
Test name
Test status
Simulation time 1099373959 ps
CPU time 1.25 seconds
Started Aug 13 04:30:27 PM PDT 24
Finished Aug 13 04:30:29 PM PDT 24
Peak memory 193356 kb
Host smart-a3acb563-4e88-455c-9917-fc319cea39a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579296499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1579296499
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1103770655
Short name T347
Test name
Test status
Simulation time 442902338 ps
CPU time 1.36 seconds
Started Aug 13 04:30:18 PM PDT 24
Finished Aug 13 04:30:20 PM PDT 24
Peak memory 198528 kb
Host smart-c33e579c-07c3-4774-9c4b-02e947612f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103770655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1103770655
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.564278084
Short name T36
Test name
Test status
Simulation time 4494127714 ps
CPU time 7.08 seconds
Started Aug 13 04:30:24 PM PDT 24
Finished Aug 13 04:30:31 PM PDT 24
Peak memory 197972 kb
Host smart-1b13dfa7-f599-4da1-89f1-cb6fdc91eeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564278084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.564278084
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4053665819
Short name T247
Test name
Test status
Simulation time 9777347669 ps
CPU time 6.94 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 192104 kb
Host smart-46024517-b05d-4b80-be59-60ad1a5d81b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053665819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4053665819
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3022998214
Short name T265
Test name
Test status
Simulation time 547712463 ps
CPU time 0.99 seconds
Started Aug 13 05:01:23 PM PDT 24
Finished Aug 13 05:01:25 PM PDT 24
Peak memory 192024 kb
Host smart-b463dd4f-e7cd-4334-90f8-1a9e4ea434b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022998214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3022998214
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.252628752
Short name T284
Test name
Test status
Simulation time 5713118228 ps
CPU time 12.47 seconds
Started Aug 13 05:01:22 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 214876 kb
Host smart-f5d4286c-197b-4905-bbfa-f30f1a6d1866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252628752 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.252628752
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1433339265
Short name T159
Test name
Test status
Simulation time 566178288 ps
CPU time 0.82 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:30 PM PDT 24
Peak memory 196820 kb
Host smart-5e23a456-e8ea-483c-b71d-a7c896b660be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433339265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1433339265
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.910681281
Short name T255
Test name
Test status
Simulation time 31509380671 ps
CPU time 38.57 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 197104 kb
Host smart-d7deba83-f173-4f51-878d-77730b48eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910681281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.910681281
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1109754897
Short name T17
Test name
Test status
Simulation time 3885832752 ps
CPU time 2.56 seconds
Started Aug 13 05:01:27 PM PDT 24
Finished Aug 13 05:01:30 PM PDT 24
Peak memory 215704 kb
Host smart-f467c6c6-f347-4475-931f-45b5c7f10a0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109754897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1109754897
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2178459311
Short name T223
Test name
Test status
Simulation time 476970469 ps
CPU time 0.72 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:25 PM PDT 24
Peak memory 192036 kb
Host smart-f4670a26-5889-45a5-ae24-cc0c26f61720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178459311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2178459311
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1501114049
Short name T277
Test name
Test status
Simulation time 1577262128 ps
CPU time 2.71 seconds
Started Aug 13 05:01:36 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196840 kb
Host smart-c8743acb-17b0-4d03-b46a-e3498c994e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501114049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1501114049
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2259490202
Short name T254
Test name
Test status
Simulation time 479733618 ps
CPU time 0.67 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:38 PM PDT 24
Peak memory 192036 kb
Host smart-733b4917-6574-423c-9e0d-b40fb9edae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259490202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2259490202
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.123734207
Short name T272
Test name
Test status
Simulation time 39753023368 ps
CPU time 24.22 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:58 PM PDT 24
Peak memory 192172 kb
Host smart-735947ae-98a2-40fe-bb82-62d2a928df5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123734207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.123734207
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1008814354
Short name T214
Test name
Test status
Simulation time 452205412 ps
CPU time 1.18 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 196808 kb
Host smart-2297443a-2e58-4012-8946-dde63172f691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008814354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1008814354
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3837943915
Short name T236
Test name
Test status
Simulation time 17443283126 ps
CPU time 26.8 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 192084 kb
Host smart-675c6ef5-d8a4-4eb1-8875-bf1780124ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837943915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3837943915
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2197488826
Short name T238
Test name
Test status
Simulation time 362038786 ps
CPU time 0.7 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 196860 kb
Host smart-a0d2a823-4fed-4114-ac90-dbeb64b68cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197488826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2197488826
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1449157986
Short name T194
Test name
Test status
Simulation time 6631847930 ps
CPU time 3.44 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:01:36 PM PDT 24
Peak memory 192156 kb
Host smart-0592c304-db01-4654-950d-8f87b3b98cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449157986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1449157986
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3058918226
Short name T250
Test name
Test status
Simulation time 475987436 ps
CPU time 1.3 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 192100 kb
Host smart-802fefc5-a52a-46e4-b753-78068be94ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058918226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3058918226
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3073892166
Short name T196
Test name
Test status
Simulation time 12744571250 ps
CPU time 3.74 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 197120 kb
Host smart-fbedbd01-f58b-42b6-b5d1-a7d4782512ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073892166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3073892166
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1003152104
Short name T235
Test name
Test status
Simulation time 512627196 ps
CPU time 0.64 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196832 kb
Host smart-5c65d007-7514-41d8-b738-d052ad850857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003152104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1003152104
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2552386517
Short name T166
Test name
Test status
Simulation time 402586827 ps
CPU time 0.75 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196796 kb
Host smart-55c4115a-185b-49ff-8e7e-110bd6119307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552386517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2552386517
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2112821475
Short name T230
Test name
Test status
Simulation time 2468008965 ps
CPU time 3.59 seconds
Started Aug 13 05:01:40 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 196904 kb
Host smart-6528fbc1-a255-486a-94c0-4cf1f51dde9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112821475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2112821475
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3025918042
Short name T233
Test name
Test status
Simulation time 425023722 ps
CPU time 0.73 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 196880 kb
Host smart-eed5b3a7-f786-44e8-827f-a7b8e7323113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025918042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3025918042
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1819716555
Short name T147
Test name
Test status
Simulation time 430120007 ps
CPU time 0.65 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:32 PM PDT 24
Peak memory 196856 kb
Host smart-736fb28f-3500-47e0-9bb6-90cb37b62738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819716555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1819716555
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2982798155
Short name T224
Test name
Test status
Simulation time 2764907030 ps
CPU time 4.71 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:01:37 PM PDT 24
Peak memory 192092 kb
Host smart-25bb46da-18fa-4632-b198-2ad532553065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982798155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2982798155
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1807071105
Short name T264
Test name
Test status
Simulation time 447660252 ps
CPU time 0.73 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 196848 kb
Host smart-f0f37078-eef8-4b67-88a9-3c4fb907dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807071105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1807071105
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.925794236
Short name T211
Test name
Test status
Simulation time 55288606062 ps
CPU time 77.11 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:02:49 PM PDT 24
Peak memory 197092 kb
Host smart-732d5705-372b-4284-a8c6-4ecdcdfcd69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925794236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.925794236
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2789168259
Short name T199
Test name
Test status
Simulation time 557935452 ps
CPU time 0.76 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 192100 kb
Host smart-d6f4be30-ae60-4c62-90be-9f6cce01d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789168259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2789168259
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3461625237
Short name T22
Test name
Test status
Simulation time 14504012123 ps
CPU time 1.6 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 192080 kb
Host smart-3b371ee5-60e3-4f18-9379-e76d169e58f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461625237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3461625237
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2357959775
Short name T240
Test name
Test status
Simulation time 440326848 ps
CPU time 0.67 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 192104 kb
Host smart-c285905b-be78-433c-be46-7adfb3800756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357959775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2357959775
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2402319661
Short name T218
Test name
Test status
Simulation time 34450535707 ps
CPU time 14.46 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 197104 kb
Host smart-7989a9ed-9d44-42bb-9426-657c04c4a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402319661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2402319661
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1295137456
Short name T207
Test name
Test status
Simulation time 406933531 ps
CPU time 0.99 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 196944 kb
Host smart-0cbc549e-bbaf-46ae-88d3-921bbbfa3575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295137456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1295137456
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1876978712
Short name T215
Test name
Test status
Simulation time 10707352921 ps
CPU time 16.06 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 192168 kb
Host smart-57a8d834-95f8-44ab-9d57-5bbbbe772b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876978712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1876978712
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.827729224
Short name T16
Test name
Test status
Simulation time 8292107205 ps
CPU time 3.81 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 216188 kb
Host smart-11e3fb16-c0cb-493e-9437-424523613a9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827729224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.827729224
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2239751078
Short name T200
Test name
Test status
Simulation time 528723951 ps
CPU time 0.77 seconds
Started Aug 13 05:01:23 PM PDT 24
Finished Aug 13 05:01:24 PM PDT 24
Peak memory 192032 kb
Host smart-c3a4edcb-9df6-43c2-a212-5bbabcf8729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239751078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2239751078
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1795404989
Short name T242
Test name
Test status
Simulation time 58452519745 ps
CPU time 20.7 seconds
Started Aug 13 05:01:55 PM PDT 24
Finished Aug 13 05:02:16 PM PDT 24
Peak memory 197164 kb
Host smart-fb8b79fb-005f-4440-8017-4d5c47b2c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795404989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1795404989
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2360735469
Short name T266
Test name
Test status
Simulation time 578576053 ps
CPU time 0.8 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 192000 kb
Host smart-8b285f97-eda1-48ff-90f0-24d854d7b301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360735469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2360735469
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.969561276
Short name T197
Test name
Test status
Simulation time 30599242747 ps
CPU time 45 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:02:32 PM PDT 24
Peak memory 192168 kb
Host smart-07ea4407-21aa-4784-8429-7bd7110e2bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969561276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.969561276
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3535173862
Short name T201
Test name
Test status
Simulation time 425464071 ps
CPU time 0.71 seconds
Started Aug 13 05:01:39 PM PDT 24
Finished Aug 13 05:01:40 PM PDT 24
Peak memory 192112 kb
Host smart-f66447aa-f056-46ad-a1b4-512b4ac0bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535173862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3535173862
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2989884618
Short name T195
Test name
Test status
Simulation time 7204230820 ps
CPU time 3.37 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:01:45 PM PDT 24
Peak memory 192168 kb
Host smart-d1ac525e-b45c-429e-92df-722d4e398296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989884618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2989884618
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.635147163
Short name T231
Test name
Test status
Simulation time 618201984 ps
CPU time 0.98 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 196876 kb
Host smart-a54e46a5-64c3-4ddb-a943-b193e18add63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635147163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.635147163
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1229780554
Short name T7
Test name
Test status
Simulation time 8778992586 ps
CPU time 7.08 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:01:50 PM PDT 24
Peak memory 197092 kb
Host smart-7bc58b33-cdda-41de-9a1e-3a6676196b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229780554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1229780554
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1973162001
Short name T281
Test name
Test status
Simulation time 554850057 ps
CPU time 0.66 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 192104 kb
Host smart-02ae0a61-442e-4d50-ad08-0adc090fde68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973162001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1973162001
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1803188584
Short name T181
Test name
Test status
Simulation time 422405472 ps
CPU time 1.26 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:48 PM PDT 24
Peak memory 196828 kb
Host smart-c9669273-ba24-4592-80ee-3c9ffcc3bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803188584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1803188584
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.468053704
Short name T9
Test name
Test status
Simulation time 35675772405 ps
CPU time 49.58 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:02:32 PM PDT 24
Peak memory 197168 kb
Host smart-3d7d0a0c-24e2-486b-8879-5d5f003f2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468053704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.468053704
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2531863417
Short name T249
Test name
Test status
Simulation time 577920824 ps
CPU time 1 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 192016 kb
Host smart-80674e4c-b19f-41f4-b022-2e8cc70c262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531863417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2531863417
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2855851283
Short name T217
Test name
Test status
Simulation time 37844724603 ps
CPU time 53.73 seconds
Started Aug 13 05:01:42 PM PDT 24
Finished Aug 13 05:02:36 PM PDT 24
Peak memory 192112 kb
Host smart-0f26a5c0-1b3b-4c0e-946a-59645db8011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855851283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2855851283
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2679078656
Short name T274
Test name
Test status
Simulation time 599763589 ps
CPU time 0.78 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:01:46 PM PDT 24
Peak memory 192036 kb
Host smart-57ef650f-bd31-4021-85ca-706841303aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679078656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2679078656
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3901003719
Short name T258
Test name
Test status
Simulation time 13833326907 ps
CPU time 18.08 seconds
Started Aug 13 05:01:48 PM PDT 24
Finished Aug 13 05:02:06 PM PDT 24
Peak memory 192140 kb
Host smart-5cb82983-a5c6-465e-9a28-0a1c97381988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901003719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3901003719
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2606195077
Short name T226
Test name
Test status
Simulation time 500199157 ps
CPU time 0.98 seconds
Started Aug 13 05:01:40 PM PDT 24
Finished Aug 13 05:01:41 PM PDT 24
Peak memory 196924 kb
Host smart-77b45b4c-42c0-4b59-9c88-6b3f499b932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606195077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2606195077
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2999846777
Short name T269
Test name
Test status
Simulation time 1665857167 ps
CPU time 15.55 seconds
Started Aug 13 05:01:43 PM PDT 24
Finished Aug 13 05:01:59 PM PDT 24
Peak memory 198700 kb
Host smart-13b9def1-2277-4a9e-9928-0c5c8340f5f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999846777 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2999846777
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2989456865
Short name T244
Test name
Test status
Simulation time 4639143817 ps
CPU time 6.36 seconds
Started Aug 13 05:01:48 PM PDT 24
Finished Aug 13 05:01:55 PM PDT 24
Peak memory 192144 kb
Host smart-5b8eeb9e-efdb-4480-9975-b373c4efcef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989456865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2989456865
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.388642303
Short name T276
Test name
Test status
Simulation time 476040499 ps
CPU time 1.33 seconds
Started Aug 13 05:01:45 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 192096 kb
Host smart-48d7a284-b765-40be-b706-97b57f060845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388642303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.388642303
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2483021576
Short name T259
Test name
Test status
Simulation time 43719113813 ps
CPU time 16.05 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 192168 kb
Host smart-76b4424e-e8a5-4012-bd45-c7c7c93ad3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483021576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2483021576
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2957332694
Short name T202
Test name
Test status
Simulation time 471731206 ps
CPU time 0.77 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 192088 kb
Host smart-b083c130-73bf-465e-b620-a063042a4452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957332694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2957332694
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3113612727
Short name T210
Test name
Test status
Simulation time 22109672560 ps
CPU time 30.41 seconds
Started Aug 13 05:01:55 PM PDT 24
Finished Aug 13 05:02:25 PM PDT 24
Peak memory 192168 kb
Host smart-1b000842-177e-4f6c-a1cc-6d2ef373c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113612727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3113612727
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.249727242
Short name T12
Test name
Test status
Simulation time 369746498 ps
CPU time 0.83 seconds
Started Aug 13 05:01:49 PM PDT 24
Finished Aug 13 05:01:49 PM PDT 24
Peak memory 196876 kb
Host smart-747e004e-cd93-478c-b7e9-b0b55ad3455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249727242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.249727242
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1781710579
Short name T241
Test name
Test status
Simulation time 23756160231 ps
CPU time 9.32 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 192084 kb
Host smart-7b314c97-26a4-4f4e-a8a1-007e69966878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781710579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1781710579
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4075796581
Short name T15
Test name
Test status
Simulation time 7957618972 ps
CPU time 3.3 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:36 PM PDT 24
Peak memory 216244 kb
Host smart-33bf0d11-8d35-4df8-acee-ef3272d04be9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075796581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4075796581
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2905843778
Short name T246
Test name
Test status
Simulation time 373093432 ps
CPU time 1.13 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 192012 kb
Host smart-867c063c-7b2a-4dc8-a37c-82e1c8630feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905843778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2905843778
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2862333942
Short name T268
Test name
Test status
Simulation time 22080064130 ps
CPU time 8.44 seconds
Started Aug 13 05:01:46 PM PDT 24
Finished Aug 13 05:01:54 PM PDT 24
Peak memory 192156 kb
Host smart-4d7d6f7a-2a16-435b-aa37-6df91836ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862333942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2862333942
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3189805981
Short name T262
Test name
Test status
Simulation time 518284552 ps
CPU time 1.13 seconds
Started Aug 13 05:01:49 PM PDT 24
Finished Aug 13 05:01:50 PM PDT 24
Peak memory 196900 kb
Host smart-e25ae145-8bd9-4c96-b4ac-d81aad89c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189805981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3189805981
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1740931323
Short name T252
Test name
Test status
Simulation time 22882090813 ps
CPU time 34.23 seconds
Started Aug 13 05:01:55 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 192080 kb
Host smart-5668d077-3084-4ab1-bd16-05b310fbe0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740931323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1740931323
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2499386647
Short name T213
Test name
Test status
Simulation time 373246542 ps
CPU time 1.07 seconds
Started Aug 13 05:01:50 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 192004 kb
Host smart-680b3a0d-4888-44c1-b90a-2b0144388beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499386647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2499386647
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1888588321
Short name T203
Test name
Test status
Simulation time 2671107339 ps
CPU time 1.21 seconds
Started Aug 13 05:01:51 PM PDT 24
Finished Aug 13 05:01:52 PM PDT 24
Peak memory 192168 kb
Host smart-1529e4d9-0102-4d6e-9603-440cb33db241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888588321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1888588321
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2004168948
Short name T212
Test name
Test status
Simulation time 560809398 ps
CPU time 0.82 seconds
Started Aug 13 05:01:49 PM PDT 24
Finished Aug 13 05:01:50 PM PDT 24
Peak memory 192028 kb
Host smart-70c1842c-26c8-4fb6-8230-bf491be32a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004168948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2004168948
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.793832032
Short name T279
Test name
Test status
Simulation time 45893121092 ps
CPU time 59.67 seconds
Started Aug 13 05:01:55 PM PDT 24
Finished Aug 13 05:02:55 PM PDT 24
Peak memory 192104 kb
Host smart-77c9e9cc-7919-4fdd-a59d-d5c24807a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793832032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.793832032
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1473237127
Short name T228
Test name
Test status
Simulation time 402527392 ps
CPU time 0.75 seconds
Started Aug 13 05:01:52 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 192088 kb
Host smart-8c978e47-7ab2-4895-96de-a343cf10204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473237127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1473237127
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1308049522
Short name T227
Test name
Test status
Simulation time 8687315841 ps
CPU time 1.7 seconds
Started Aug 13 05:01:53 PM PDT 24
Finished Aug 13 05:01:55 PM PDT 24
Peak memory 197148 kb
Host smart-2e7f0adb-d49c-44e9-bc33-5ffd35d2c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308049522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1308049522
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.10279553
Short name T245
Test name
Test status
Simulation time 423428023 ps
CPU time 0.72 seconds
Started Aug 13 05:01:50 PM PDT 24
Finished Aug 13 05:01:51 PM PDT 24
Peak memory 192096 kb
Host smart-02844217-af97-4824-9f1f-37126d1bb145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10279553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.10279553
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.682402240
Short name T161
Test name
Test status
Simulation time 417889949826 ps
CPU time 408.23 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:08:44 PM PDT 24
Peak memory 192092 kb
Host smart-6693886f-d24c-4bc7-bb9a-2a56ce53560e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682402240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.682402240
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1233790332
Short name T209
Test name
Test status
Simulation time 54547120745 ps
CPU time 80.7 seconds
Started Aug 13 05:01:56 PM PDT 24
Finished Aug 13 05:03:17 PM PDT 24
Peak memory 192184 kb
Host smart-593e08c0-cadb-4e33-ba37-8f04c3307ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233790332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1233790332
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3210546963
Short name T283
Test name
Test status
Simulation time 461573584 ps
CPU time 0.71 seconds
Started Aug 13 05:01:50 PM PDT 24
Finished Aug 13 05:01:51 PM PDT 24
Peak memory 192032 kb
Host smart-a5b3d27a-a6a5-4bcd-be9a-b305d2aff7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210546963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3210546963
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1717703839
Short name T237
Test name
Test status
Simulation time 48370403242 ps
CPU time 9.21 seconds
Started Aug 13 05:01:53 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 192080 kb
Host smart-2c2c53cf-7a98-4432-af61-b452d740077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717703839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1717703839
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.629234799
Short name T282
Test name
Test status
Simulation time 554129353 ps
CPU time 1.36 seconds
Started Aug 13 05:01:54 PM PDT 24
Finished Aug 13 05:01:56 PM PDT 24
Peak memory 192008 kb
Host smart-1504f612-81dd-4ce5-a528-3b715a1fa034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629234799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.629234799
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2111674997
Short name T45
Test name
Test status
Simulation time 21323296210 ps
CPU time 31.69 seconds
Started Aug 13 05:01:52 PM PDT 24
Finished Aug 13 05:02:24 PM PDT 24
Peak memory 192104 kb
Host smart-2f5610c3-87ed-4fde-8057-283ee5036977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111674997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2111674997
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2581198507
Short name T234
Test name
Test status
Simulation time 583300146 ps
CPU time 0.8 seconds
Started Aug 13 05:01:53 PM PDT 24
Finished Aug 13 05:01:55 PM PDT 24
Peak memory 192048 kb
Host smart-c6da4da9-a419-4b51-b0a0-705c5b7f7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581198507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2581198507
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.510018782
Short name T179
Test name
Test status
Simulation time 525645861 ps
CPU time 0.77 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 196788 kb
Host smart-829806fa-c952-42f5-8c37-fa86b750abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510018782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.510018782
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1904398013
Short name T267
Test name
Test status
Simulation time 18445290552 ps
CPU time 8.47 seconds
Started Aug 13 05:01:57 PM PDT 24
Finished Aug 13 05:02:05 PM PDT 24
Peak memory 192176 kb
Host smart-d1e70e2e-10a8-4bb4-92fc-fd358c62bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904398013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1904398013
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2178570203
Short name T208
Test name
Test status
Simulation time 560036251 ps
CPU time 0.63 seconds
Started Aug 13 05:01:52 PM PDT 24
Finished Aug 13 05:01:53 PM PDT 24
Peak memory 196876 kb
Host smart-a7228cf6-f7b2-4a1f-b92b-edfaccacb31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178570203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2178570203
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2423982066
Short name T248
Test name
Test status
Simulation time 33670213430 ps
CPU time 5.77 seconds
Started Aug 13 05:01:58 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 192152 kb
Host smart-444f1e8a-8b7f-4598-b1af-e4ac42618643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423982066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2423982066
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2669006887
Short name T229
Test name
Test status
Simulation time 583137308 ps
CPU time 0.84 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 192056 kb
Host smart-46a285ce-cb36-4a7c-89d4-dca9e4c805e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669006887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2669006887
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1354446305
Short name T193
Test name
Test status
Simulation time 3436307979 ps
CPU time 3.12 seconds
Started Aug 13 05:01:41 PM PDT 24
Finished Aug 13 05:01:44 PM PDT 24
Peak memory 192096 kb
Host smart-b3bf6d8e-9dbe-40cf-beb6-2d02cc49f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354446305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1354446305
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1725407532
Short name T14
Test name
Test status
Simulation time 4202377008 ps
CPU time 2.15 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 215948 kb
Host smart-7b2ddf2a-d3a7-4948-bd5b-f5ec2b537f16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725407532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1725407532
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.506672753
Short name T80
Test name
Test status
Simulation time 428801386 ps
CPU time 0.92 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196872 kb
Host smart-9767d194-14cb-45fb-bfa2-2de8aa81283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506672753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.506672753
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.246905114
Short name T206
Test name
Test status
Simulation time 1192574617 ps
CPU time 1.02 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:01 PM PDT 24
Peak memory 192072 kb
Host smart-86a88d81-bbd5-4301-81c7-05b4dbfc125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246905114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.246905114
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.341897008
Short name T257
Test name
Test status
Simulation time 443601547 ps
CPU time 0.71 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 192012 kb
Host smart-23ae276f-1a2d-446d-bba8-9841c5059e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341897008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.341897008
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.368639134
Short name T261
Test name
Test status
Simulation time 16315698577 ps
CPU time 6.65 seconds
Started Aug 13 05:02:05 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 192052 kb
Host smart-8a93fceb-3e9f-426d-89d5-fac4838d0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368639134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.368639134
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2216271756
Short name T216
Test name
Test status
Simulation time 538480394 ps
CPU time 0.79 seconds
Started Aug 13 05:01:59 PM PDT 24
Finished Aug 13 05:02:00 PM PDT 24
Peak memory 192024 kb
Host smart-12766422-03f5-4977-bc66-663dc3d90d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216271756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2216271756
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2113469246
Short name T271
Test name
Test status
Simulation time 8595951808 ps
CPU time 6.82 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:07 PM PDT 24
Peak memory 197152 kb
Host smart-fbeb292d-cac9-4d1b-a247-3f17ea673338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113469246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2113469246
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2258271002
Short name T84
Test name
Test status
Simulation time 579031180 ps
CPU time 0.92 seconds
Started Aug 13 05:01:58 PM PDT 24
Finished Aug 13 05:01:59 PM PDT 24
Peak memory 192076 kb
Host smart-54ac3b0a-1bed-4be3-808b-a4980df027ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258271002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2258271002
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1554589331
Short name T192
Test name
Test status
Simulation time 181875820930 ps
CPU time 233.86 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:05:54 PM PDT 24
Peak memory 198412 kb
Host smart-7b3a1b4d-4423-48b2-8501-4dae27bd05ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554589331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1554589331
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.412931713
Short name T225
Test name
Test status
Simulation time 31650976165 ps
CPU time 7.61 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:10 PM PDT 24
Peak memory 192136 kb
Host smart-edd602aa-cc66-472b-82f6-0c804186e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412931713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.412931713
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1004373788
Short name T243
Test name
Test status
Simulation time 430771638 ps
CPU time 0.88 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:01 PM PDT 24
Peak memory 196868 kb
Host smart-909243d4-5cd8-490c-980e-049714061ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004373788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1004373788
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2272392399
Short name T275
Test name
Test status
Simulation time 45382610889 ps
CPU time 17.35 seconds
Started Aug 13 05:02:04 PM PDT 24
Finished Aug 13 05:02:22 PM PDT 24
Peak memory 197100 kb
Host smart-e3d82a8c-b73a-4061-b724-ce832ac83c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272392399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2272392399
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2846080351
Short name T232
Test name
Test status
Simulation time 561307648 ps
CPU time 1.36 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 192112 kb
Host smart-62dbc682-09e5-413e-a3d9-8c72acfa12b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846080351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2846080351
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4098363230
Short name T256
Test name
Test status
Simulation time 3070701662 ps
CPU time 2.63 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 192168 kb
Host smart-43cf6785-75a3-4a25-b3e9-b752b10cc69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098363230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4098363230
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3853762146
Short name T278
Test name
Test status
Simulation time 491973609 ps
CPU time 0.76 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 192076 kb
Host smart-3f766619-d629-4c88-be67-232eb54f4bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853762146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3853762146
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3354922461
Short name T79
Test name
Test status
Simulation time 25622937102 ps
CPU time 8.74 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 192088 kb
Host smart-438dbfcd-4219-4475-9e74-556dc616a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354922461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3354922461
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1974824034
Short name T219
Test name
Test status
Simulation time 483392807 ps
CPU time 1.1 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 192032 kb
Host smart-45ea9d80-6e7f-4589-b1a3-0c42ca33a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974824034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1974824034
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3319831026
Short name T205
Test name
Test status
Simulation time 17187503852 ps
CPU time 26.39 seconds
Started Aug 13 05:02:09 PM PDT 24
Finished Aug 13 05:02:35 PM PDT 24
Peak memory 192164 kb
Host smart-5406ff73-4953-48fc-8aa6-d3e41073d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319831026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3319831026
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.982620591
Short name T221
Test name
Test status
Simulation time 464887013 ps
CPU time 0.74 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 196820 kb
Host smart-cb87251b-ba5f-49f4-abc7-8221613013a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982620591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.982620591
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2986042920
Short name T204
Test name
Test status
Simulation time 1951893281 ps
CPU time 1.7 seconds
Started Aug 13 05:02:00 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 192108 kb
Host smart-02721cd9-a2dc-4548-abd6-73963aa29b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986042920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2986042920
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.135833941
Short name T198
Test name
Test status
Simulation time 484131858 ps
CPU time 1.09 seconds
Started Aug 13 05:02:03 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 192032 kb
Host smart-4ee99f1f-aa5b-41a3-97b3-763c7d00d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135833941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.135833941
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2375268820
Short name T263
Test name
Test status
Simulation time 11302854894 ps
CPU time 16.74 seconds
Started Aug 13 05:02:02 PM PDT 24
Finished Aug 13 05:02:19 PM PDT 24
Peak memory 192168 kb
Host smart-d8a5d4f1-484f-48c2-b3bf-1ec8b68d701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375268820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2375268820
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1441093858
Short name T25
Test name
Test status
Simulation time 495288743 ps
CPU time 1.23 seconds
Started Aug 13 05:02:01 PM PDT 24
Finished Aug 13 05:02:02 PM PDT 24
Peak memory 192024 kb
Host smart-0eededdb-c71d-4e8f-80f2-6ab02a801178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441093858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1441093858
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2682002337
Short name T273
Test name
Test status
Simulation time 40893153915 ps
CPU time 47.71 seconds
Started Aug 13 05:01:35 PM PDT 24
Finished Aug 13 05:02:23 PM PDT 24
Peak memory 197136 kb
Host smart-4bee07bf-dbd3-4ba1-9a7e-95aff897ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682002337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2682002337
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3768469683
Short name T270
Test name
Test status
Simulation time 540314713 ps
CPU time 0.74 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 192012 kb
Host smart-93e2c71a-afad-4cab-8dbf-b4b064fd9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768469683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3768469683
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2947822165
Short name T85
Test name
Test status
Simulation time 20900437635 ps
CPU time 16.44 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:47 PM PDT 24
Peak memory 192080 kb
Host smart-10713d3f-cf25-4cd9-a4a3-000e9a2b6a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947822165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2947822165
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4133533421
Short name T280
Test name
Test status
Simulation time 472895684 ps
CPU time 0.73 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 192008 kb
Host smart-531b1b41-b600-4f49-b155-bf691013f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133533421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4133533421
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1193386133
Short name T73
Test name
Test status
Simulation time 1637392883 ps
CPU time 9.51 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:43 PM PDT 24
Peak memory 206880 kb
Host smart-3fba7e5e-fb62-427e-bfa5-af1981661a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193386133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1193386133
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4177096044
Short name T253
Test name
Test status
Simulation time 26891684121 ps
CPU time 7.79 seconds
Started Aug 13 05:01:34 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 192128 kb
Host smart-74183cbd-df57-47cc-baa1-7da54ff724eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177096044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4177096044
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3862118762
Short name T222
Test name
Test status
Simulation time 565058118 ps
CPU time 1.43 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 196872 kb
Host smart-82796239-6696-408d-953c-84276f616090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862118762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3862118762
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.117749689
Short name T239
Test name
Test status
Simulation time 1733444415 ps
CPU time 3.12 seconds
Started Aug 13 05:01:32 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 196736 kb
Host smart-dd277451-07e9-4e51-a83e-13d5ea704c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117749689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.117749689
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2621233775
Short name T220
Test name
Test status
Simulation time 477748301 ps
CPU time 0.73 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:01:38 PM PDT 24
Peak memory 192096 kb
Host smart-af33b225-8b2a-4acb-a027-a94147405f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621233775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2621233775
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4077840045
Short name T251
Test name
Test status
Simulation time 34970187323 ps
CPU time 26.24 seconds
Started Aug 13 05:01:37 PM PDT 24
Finished Aug 13 05:02:04 PM PDT 24
Peak memory 192176 kb
Host smart-2d2d4def-f0d1-448f-a2dd-0c0a22b224ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077840045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4077840045
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1437937785
Short name T260
Test name
Test status
Simulation time 394163419 ps
CPU time 0.83 seconds
Started Aug 13 05:01:38 PM PDT 24
Finished Aug 13 05:01:39 PM PDT 24
Peak memory 192116 kb
Host smart-99c47f92-fc8e-4dac-ab80-373eb2d231c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437937785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1437937785
Directory /workspace/9.aon_timer_smoke/latest
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