Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	16803	1		T1	12		T2	17		T3	172
bark[1]	335	1		T8	26		T106	21		T75	21
bark[2]	541	1		T91	14		T106	130		T90	14
bark[3]	375	1		T106	26		T23	14		T122	65
bark[4]	438	1		T4	51		T9	43		T33	21
bark[5]	510	1		T8	21		T33	21		T98	21
bark[6]	552	1		T33	47		T129	26		T146	5
bark[7]	415	1		T14	14		T43	96		T178	14
bark[8]	113	1		T45	14		T165	5		T103	21
bark[9]	486	1		T3	61		T45	209		T106	21
bark[10]	420	1		T8	21		T50	42		T109	26
bark[11]	302	1		T27	26		T92	21		T113	163
bark[12]	184	1		T24	14		T170	5		T78	7
bark[13]	245	1		T28	21		T103	21		T114	64
bark[14]	496	1		T169	14		T76	21		T92	21
bark[15]	206	1		T50	21		T132	21		T107	40
bark[16]	364	1		T4	21		T44	7		T47	182
bark[17]	519	1		T44	30		T137	14		T48	47
bark[18]	258	1		T5	14		T45	43		T165	26
bark[19]	108	1		T52	14		T183	14		T103	80
bark[20]	302	1		T9	5		T15	68		T75	21
bark[21]	444	1		T144	26		T118	14		T27	21
bark[22]	484	1		T36	241		T43	7		T45	26
bark[23]	221	1		T50	21		T27	14		T78	21
bark[24]	310	1		T50	35		T36	21		T129	21
bark[25]	202	1		T32	14		T43	26		T48	5
bark[26]	377	1		T50	21		T100	35		T138	7
bark[27]	324	1		T98	65		T128	128		T122	59
bark[28]	238	1		T9	19		T15	7		T33	21
bark[29]	472	1		T165	82		T109	21		T143	30
bark[30]	508	1		T50	42		T44	133		T45	125
bark[31]	140	1		T15	7		T46	21		T146	21
bark_0	4413	1		T1	7		T2	33		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	16359	1		T1	11		T2	21		T3	172
bite[1]	186	1		T35	13		T46	21		T165	25
bite[2]	508	1		T3	60		T9	42		T51	61
bite[3]	562	1		T46	21		T183	13		T109	39
bite[4]	418	1		T32	13		T27	21		T92	21
bite[5]	145	1		T45	26		T88	21		T186	13
bite[6]	513	1		T50	21		T45	208		T165	4
bite[7]	641	1		T50	35		T43	95		T44	30
bite[8]	403	1		T33	42		T143	30		T122	59
bite[9]	167	1		T50	21		T91	13		T48	4
bite[10]	814	1		T36	240		T106	21		T52	13
bite[11]	282	1		T9	13		T75	21		T146	4
bite[12]	186	1		T36	21		T43	25		T113	21
bite[13]	196	1		T14	13		T36	21		T98	21
bite[14]	168	1		T129	26		T27	13		T84	13
bite[15]	297	1		T5	13		T78	6		T104	60
bite[16]	259	1		T15	67		T33	21		T50	42
bite[17]	95	1		T104	21		T83	21		T151	21
bite[18]	135	1		T140	13		T185	13		T100	21
bite[19]	293	1		T15	6		T98	21		T25	13
bite[20]	295	1		T165	25		T129	85		T77	6
bite[21]	539	1		T4	51		T165	81		T29	13
bite[22]	614	1		T50	21		T76	21		T129	21
bite[23]	238	1		T90	13		T27	30		T92	42
bite[24]	308	1		T137	13		T75	64		T159	26
bite[25]	631	1		T50	21		T45	42		T47	181
bite[26]	93	1		T8	47		T98	21		T77	21
bite[27]	253	1		T50	21		T23	13		T109	92
bite[28]	622	1		T8	21		T44	132		T45	13
bite[29]	230	1		T15	6		T33	68		T178	13
bite[30]	247	1		T144	26		T51	21		T27	21
bite[31]	531	1		T4	21		T50	42		T43	6
bite_0	4877	1		T1	8		T2	29		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27957	1		T1	19		T2	50		T3	202
auto[1]	4148	1		T3	38		T33	19		T36	348

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	355	1		T3	38		T8	45		T9	2
prescale[1]	290	1		T2	2		T9	12		T144	31
prescale[2]	389	1		T45	58		T51	23		T106	63
prescale[3]	498	1		T1	9		T2	2		T8	40
prescale[4]	328	1		T3	28		T195	9		T45	83
prescale[5]	270	1		T15	2		T46	2		T75	9
prescale[6]	527	1		T10	9		T15	4		T36	251
prescale[7]	529	1		T44	9		T196	9		T103	19
prescale[8]	434	1		T43	2		T48	2		T75	57
prescale[9]	339	1		T44	40		T35	19		T75	19
prescale[10]	328	1		T4	36		T9	2		T13	9
prescale[11]	416	1		T8	36		T15	2		T35	19
prescale[12]	298	1		T15	2		T50	23		T144	56
prescale[13]	345	1		T44	19		T35	19		T51	40
prescale[14]	368	1		T44	2		T45	2		T47	2
prescale[15]	483	1		T44	2		T47	68		T48	2
prescale[16]	408	1		T144	23		T45	9		T48	2
prescale[17]	263	1		T49	9		T47	36		T143	23
prescale[18]	374	1		T33	37		T197	9		T47	2
prescale[19]	393	1		T4	19		T36	2		T44	2
prescale[20]	326	1		T4	19		T35	36		T76	46
prescale[21]	323	1		T36	19		T76	2		T129	44
prescale[22]	326	1		T44	23		T48	2		T198	9
prescale[23]	388	1		T12	9		T98	23		T199	9
prescale[24]	565	1		T3	73		T35	28		T51	57
prescale[25]	362	1		T3	19		T4	23		T36	9
prescale[26]	462	1		T50	19		T36	180		T44	2
prescale[27]	319	1		T36	32		T35	63		T47	9
prescale[28]	393	1		T4	38		T47	71		T98	19
prescale[29]	533	1		T33	32		T44	21		T45	19
prescale[30]	145	1		T8	23		T50	18		T76	19
prescale[31]	714	1		T8	14		T15	2		T45	57
prescale_0	19614	1		T1	10		T2	46		T3	82

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	21624	1		T1	9		T2	13		T3	175
auto[1]	10481	1		T1	10		T2	37		T3	65

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	32105	1		T1	19		T2	50		T3	240

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	17791	1		T1	14		T2	25		T3	164
wkup[1]	217	1		T144	21		T47	42		T103	30
wkup[2]	224	1		T45	21		T83	21		T113	21
wkup[3]	200	1		T4	30		T35	30		T107	21
wkup[4]	160	1		T36	52		T109	60		T131	6
wkup[5]	121	1		T44	8		T27	21		T109	30
wkup[6]	162	1		T45	26		T47	21		T109	26
wkup[7]	164	1		T27	21		T92	21		T77	21
wkup[8]	176	1		T36	21		T45	8		T51	21
wkup[9]	84	1		T27	21		T103	21		T122	21
wkup[10]	135	1		T3	15		T129	21		T84	15
wkup[11]	133	1		T91	15		T34	15		T75	31
wkup[12]	149	1		T3	30		T43	21		T104	21
wkup[13]	203	1		T9	6		T36	42		T45	26
wkup[14]	293	1		T36	21		T43	36		T98	21
wkup[15]	414	1		T15	21		T44	21		T46	21
wkup[16]	161	1		T9	6		T44	8		T45	30
wkup[17]	143	1		T36	15		T27	30		T78	21
wkup[18]	189	1		T33	21		T50	21		T169	15
wkup[19]	290	1		T44	30		T75	21		T159	26
wkup[20]	161	1		T143	26		T104	21		T113	21
wkup[21]	138	1		T50	21		T35	15		T139	15
wkup[22]	146	1		T8	26		T51	21		T106	21
wkup[23]	176	1		T32	15		T106	26		T29	15
wkup[24]	107	1		T44	21		T90	15		T103	42
wkup[25]	341	1		T45	41		T75	21		T76	21
wkup[26]	179	1		T4	21		T51	21		T27	15
wkup[27]	164	1		T45	26		T145	30		T96	30
wkup[28]	176	1		T8	21		T9	15		T50	21
wkup[29]	208	1		T43	8		T132	21		T138	8
wkup[30]	99	1		T36	21		T83	21		T133	21
wkup[31]	113	1		T14	15		T144	26		T79	30
wkup[32]	161	1		T47	21		T77	21		T133	21
wkup[33]	269	1		T8	21		T9	21		T47	21
wkup[34]	84	1		T106	21		T76	21		T155	21
wkup[35]	224	1		T8	21		T15	21		T36	21
wkup[36]	184	1		T98	21		T146	6		T27	21
wkup[37]	104	1		T106	21		T98	21		T157	15
wkup[38]	171	1		T165	21		T140	15		T28	21
wkup[39]	101	1		T78	21		T132	21		T87	30
wkup[40]	143	1		T36	21		T75	21		T113	30
wkup[41]	206	1		T50	21		T36	21		T159	21
wkup[42]	92	1		T50	56		T52	15		T27	21
wkup[43]	74	1		T137	15		T143	15		T113	21
wkup[44]	208	1		T33	21		T47	21		T25	15
wkup[45]	206	1		T50	21		T98	44		T159	21
wkup[46]	128	1		T50	21		T107	26		T95	15
wkup[47]	245	1		T33	21		T98	21		T48	21
wkup[48]	182	1		T44	21		T144	21		T46	21
wkup[49]	146	1		T15	21		T36	21		T92	21
wkup[50]	189	1		T33	21		T178	15		T128	30
wkup[51]	98	1		T5	15		T77	21		T151	26
wkup[52]	149	1		T165	21		T28	21		T77	8
wkup[53]	195	1		T144	26		T47	21		T122	44
wkup[54]	181	1		T50	21		T132	21		T100	35
wkup[55]	145	1		T94	30		T89	21		T79	21
wkup[56]	179	1		T15	8		T50	21		T36	21
wkup[57]	252	1		T3	26		T33	30		T47	15
wkup[58]	175	1		T51	21		T75	30		T129	26
wkup[59]	50	1		T15	8		T45	21		T115	21
wkup[60]	120	1		T48	21		T146	21		T23	15
wkup[61]	195	1		T77	42		T83	30		T79	15
wkup[62]	162	1		T4	21		T36	21		T78	8
wkup[63]	246	1		T45	21		T48	6		T75	6
wkup_0	3424	1		T1	5		T2	25		T3	5