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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.78 99.33 93.67 100.00 98.40 99.51 41.79


Total test records in report: 425
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T37 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3902840530 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:33 PM PDT 24 414217454 ps
T286 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1657938992 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 270986689 ps
T38 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2781198020 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:26 PM PDT 24 561350315 ps
T287 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2738212466 Aug 15 04:31:40 PM PDT 24 Aug 15 04:31:41 PM PDT 24 527029107 ps
T39 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3317882036 Aug 15 04:31:12 PM PDT 24 Aug 15 04:31:13 PM PDT 24 1190502836 ps
T53 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3529894391 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:23 PM PDT 24 388311593 ps
T40 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.149021421 Aug 15 04:31:42 PM PDT 24 Aug 15 04:31:43 PM PDT 24 4912151749 ps
T288 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1739027988 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:34 PM PDT 24 436697447 ps
T289 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.58579628 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:23 PM PDT 24 443109941 ps
T200 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.431455764 Aug 15 04:31:17 PM PDT 24 Aug 15 04:31:18 PM PDT 24 389120576 ps
T290 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2789725626 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:32 PM PDT 24 587411538 ps
T54 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2491832300 Aug 15 04:31:07 PM PDT 24 Aug 15 04:31:27 PM PDT 24 13703147064 ps
T201 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1267559530 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:31 PM PDT 24 544822006 ps
T41 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3975771078 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:27 PM PDT 24 8038846766 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3952716508 Aug 15 04:30:56 PM PDT 24 Aug 15 04:30:57 PM PDT 24 474929628 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3543400627 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:33 PM PDT 24 381224896 ps
T293 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.840393823 Aug 15 04:31:39 PM PDT 24 Aug 15 04:31:40 PM PDT 24 341067523 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1072823163 Aug 15 04:31:10 PM PDT 24 Aug 15 04:31:12 PM PDT 24 1597193045 ps
T294 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2810114327 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:23 PM PDT 24 450153926 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3719050362 Aug 15 04:31:02 PM PDT 24 Aug 15 04:31:03 PM PDT 24 582613475 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1120639110 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:18 PM PDT 24 1103895985 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3093154915 Aug 15 04:31:11 PM PDT 24 Aug 15 04:31:14 PM PDT 24 10071807470 ps
T296 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2773760064 Aug 15 04:31:29 PM PDT 24 Aug 15 04:31:30 PM PDT 24 366738299 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3591705081 Aug 15 04:31:13 PM PDT 24 Aug 15 04:31:14 PM PDT 24 500776392 ps
T297 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3846091488 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 460403949 ps
T298 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1337707128 Aug 15 04:31:33 PM PDT 24 Aug 15 04:31:34 PM PDT 24 301530008 ps
T42 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2860880782 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:36 PM PDT 24 7663768010 ps
T299 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3296533336 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:28 PM PDT 24 369804153 ps
T300 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3910076579 Aug 15 04:31:41 PM PDT 24 Aug 15 04:31:43 PM PDT 24 601386691 ps
T301 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2567642734 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:24 PM PDT 24 470301183 ps
T302 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3415845650 Aug 15 04:31:25 PM PDT 24 Aug 15 04:31:26 PM PDT 24 333038943 ps
T303 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4097327582 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:16 PM PDT 24 993466839 ps
T304 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1409001882 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:23 PM PDT 24 525151757 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1446884551 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:34 PM PDT 24 1005331782 ps
T70 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3470777208 Aug 15 04:31:29 PM PDT 24 Aug 15 04:31:31 PM PDT 24 1095831028 ps
T71 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1663710318 Aug 15 04:31:23 PM PDT 24 Aug 15 04:31:24 PM PDT 24 1277693342 ps
T305 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3010385705 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:29 PM PDT 24 362547899 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2833323534 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:29 PM PDT 24 516751590 ps
T307 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3855623880 Aug 15 04:31:28 PM PDT 24 Aug 15 04:31:30 PM PDT 24 392924836 ps
T308 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4116343861 Aug 15 04:31:39 PM PDT 24 Aug 15 04:31:40 PM PDT 24 280122638 ps
T72 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2204656444 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:33 PM PDT 24 1335854072 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3442149891 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:05 PM PDT 24 486274182 ps
T309 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1518900402 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:23 PM PDT 24 437205802 ps
T190 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2223992858 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:23 PM PDT 24 8156117372 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2478599497 Aug 15 04:31:03 PM PDT 24 Aug 15 04:31:04 PM PDT 24 335903944 ps
T193 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.432658858 Aug 15 04:31:05 PM PDT 24 Aug 15 04:31:13 PM PDT 24 8955583757 ps
T311 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.657365504 Aug 15 04:31:36 PM PDT 24 Aug 15 04:31:37 PM PDT 24 387507957 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1623811223 Aug 15 04:31:07 PM PDT 24 Aug 15 04:31:10 PM PDT 24 2399849181 ps
T312 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1280827615 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:28 PM PDT 24 521040311 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.650934114 Aug 15 04:31:15 PM PDT 24 Aug 15 04:31:33 PM PDT 24 6190037312 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2921165756 Aug 15 04:31:10 PM PDT 24 Aug 15 04:31:11 PM PDT 24 817265037 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3334968827 Aug 15 04:31:00 PM PDT 24 Aug 15 04:31:01 PM PDT 24 460814073 ps
T315 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.553235404 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 427809860 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1975770341 Aug 15 04:31:26 PM PDT 24 Aug 15 04:31:30 PM PDT 24 1671254415 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1846442645 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:15 PM PDT 24 396412054 ps
T317 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.71388706 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:31 PM PDT 24 387603273 ps
T318 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3873517735 Aug 15 04:31:45 PM PDT 24 Aug 15 04:31:46 PM PDT 24 379015739 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1765935397 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:37 PM PDT 24 2863697858 ps
T320 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2731279234 Aug 15 04:31:26 PM PDT 24 Aug 15 04:31:27 PM PDT 24 467446575 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2752568694 Aug 15 04:31:12 PM PDT 24 Aug 15 04:31:13 PM PDT 24 903705036 ps
T321 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3254271308 Aug 15 04:31:01 PM PDT 24 Aug 15 04:31:02 PM PDT 24 489198122 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.629816986 Aug 15 04:31:11 PM PDT 24 Aug 15 04:31:12 PM PDT 24 681986574 ps
T323 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1154073674 Aug 15 04:31:06 PM PDT 24 Aug 15 04:31:07 PM PDT 24 312165210 ps
T324 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2262342358 Aug 15 04:31:44 PM PDT 24 Aug 15 04:31:46 PM PDT 24 503290395 ps
T194 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4089381857 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:37 PM PDT 24 8565017062 ps
T325 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2616690993 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:23 PM PDT 24 2701237312 ps
T191 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.641863283 Aug 15 04:31:26 PM PDT 24 Aug 15 04:31:35 PM PDT 24 8131564532 ps
T192 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4080633525 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:35 PM PDT 24 8406864965 ps
T326 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.66093487 Aug 15 04:31:42 PM PDT 24 Aug 15 04:31:42 PM PDT 24 295780109 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1235322231 Aug 15 04:31:12 PM PDT 24 Aug 15 04:31:13 PM PDT 24 540020814 ps
T327 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2469560015 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 423728653 ps
T328 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.157465071 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:34 PM PDT 24 379704282 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1955292563 Aug 15 04:31:17 PM PDT 24 Aug 15 04:31:18 PM PDT 24 465686259 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2849484903 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:25 PM PDT 24 595497999 ps
T330 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3141035844 Aug 15 04:31:36 PM PDT 24 Aug 15 04:31:37 PM PDT 24 372050264 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2460947943 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:33 PM PDT 24 515697955 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1536051063 Aug 15 04:30:56 PM PDT 24 Aug 15 04:30:57 PM PDT 24 309412151 ps
T333 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3658501049 Aug 15 04:31:47 PM PDT 24 Aug 15 04:31:48 PM PDT 24 527671565 ps
T334 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1754695377 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:36 PM PDT 24 4418219098 ps
T335 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4049261131 Aug 15 04:31:41 PM PDT 24 Aug 15 04:31:42 PM PDT 24 325824912 ps
T336 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1386101664 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:31 PM PDT 24 2085234041 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1077863213 Aug 15 04:31:29 PM PDT 24 Aug 15 04:31:31 PM PDT 24 1158638504 ps
T338 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.986967828 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:40 PM PDT 24 437781661 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3012203630 Aug 15 04:31:42 PM PDT 24 Aug 15 04:31:44 PM PDT 24 425221476 ps
T61 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3899365255 Aug 15 04:31:23 PM PDT 24 Aug 15 04:31:24 PM PDT 24 368735154 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2158065721 Aug 15 04:31:26 PM PDT 24 Aug 15 04:31:26 PM PDT 24 633646970 ps
T341 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4009940854 Aug 15 04:31:11 PM PDT 24 Aug 15 04:31:12 PM PDT 24 554872923 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2257940116 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:31 PM PDT 24 529442926 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2978965759 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:32 PM PDT 24 12045260812 ps
T343 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3152551876 Aug 15 04:31:25 PM PDT 24 Aug 15 04:31:27 PM PDT 24 500709336 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3878496409 Aug 15 04:31:09 PM PDT 24 Aug 15 04:31:10 PM PDT 24 434278693 ps
T345 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.172162444 Aug 15 04:31:23 PM PDT 24 Aug 15 04:31:25 PM PDT 24 380598409 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3016477023 Aug 15 04:31:42 PM PDT 24 Aug 15 04:31:43 PM PDT 24 307676359 ps
T347 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.263141305 Aug 15 04:31:09 PM PDT 24 Aug 15 04:31:22 PM PDT 24 8184175059 ps
T348 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2320560196 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 453435049 ps
T349 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1228650339 Aug 15 04:31:06 PM PDT 24 Aug 15 04:31:08 PM PDT 24 4610448405 ps
T350 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2336578738 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:29 PM PDT 24 2679897320 ps
T351 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4142896030 Aug 15 04:31:19 PM PDT 24 Aug 15 04:31:20 PM PDT 24 419109896 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2113294419 Aug 15 04:31:33 PM PDT 24 Aug 15 04:31:36 PM PDT 24 2443377340 ps
T353 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3589665893 Aug 15 04:31:33 PM PDT 24 Aug 15 04:31:34 PM PDT 24 454281047 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4145477694 Aug 15 04:31:11 PM PDT 24 Aug 15 04:31:12 PM PDT 24 437069586 ps
T355 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3507688497 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:32 PM PDT 24 663954168 ps
T65 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3838656109 Aug 15 04:31:16 PM PDT 24 Aug 15 04:31:17 PM PDT 24 551426258 ps
T356 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1338960168 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:22 PM PDT 24 1143044567 ps
T357 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.85081029 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:34 PM PDT 24 2409681773 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1124576071 Aug 15 04:31:08 PM PDT 24 Aug 15 04:31:09 PM PDT 24 388639090 ps
T359 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1216573170 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 339848167 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1944385240 Aug 15 04:31:17 PM PDT 24 Aug 15 04:31:18 PM PDT 24 547982825 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.459109155 Aug 15 04:31:06 PM PDT 24 Aug 15 04:31:07 PM PDT 24 510449322 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2374952267 Aug 15 04:31:15 PM PDT 24 Aug 15 04:31:16 PM PDT 24 283834471 ps
T363 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.418718 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:39 PM PDT 24 1010813752 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2878636211 Aug 15 04:31:17 PM PDT 24 Aug 15 04:31:17 PM PDT 24 508983678 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2281264420 Aug 15 04:31:12 PM PDT 24 Aug 15 04:31:13 PM PDT 24 422379331 ps
T366 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.929060315 Aug 15 04:31:15 PM PDT 24 Aug 15 04:31:16 PM PDT 24 504882680 ps
T367 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3413162099 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:31 PM PDT 24 522616279 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3406466115 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:05 PM PDT 24 553289468 ps
T368 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1890152594 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:24 PM PDT 24 4920663027 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.559468673 Aug 15 04:31:12 PM PDT 24 Aug 15 04:31:13 PM PDT 24 511608663 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.973047159 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:24 PM PDT 24 420908107 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1092904618 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:31 PM PDT 24 8441816082 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3648598066 Aug 15 04:31:28 PM PDT 24 Aug 15 04:31:29 PM PDT 24 517851222 ps
T373 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3200505232 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:32 PM PDT 24 446821825 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1844560938 Aug 15 04:31:20 PM PDT 24 Aug 15 04:31:22 PM PDT 24 996564070 ps
T375 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1520238284 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 496499671 ps
T376 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4224684037 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 347487091 ps
T377 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2234084474 Aug 15 04:31:39 PM PDT 24 Aug 15 04:31:40 PM PDT 24 263385376 ps
T378 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.12528319 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:29 PM PDT 24 365372915 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1787436258 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:16 PM PDT 24 438450986 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2398803265 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:24 PM PDT 24 1612278662 ps
T381 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.967266316 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:35 PM PDT 24 1012854374 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1602203648 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:33 PM PDT 24 497410080 ps
T383 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3365558257 Aug 15 04:31:32 PM PDT 24 Aug 15 04:31:33 PM PDT 24 401072892 ps
T384 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2477261451 Aug 15 04:31:39 PM PDT 24 Aug 15 04:31:40 PM PDT 24 388582562 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3686422022 Aug 15 04:31:03 PM PDT 24 Aug 15 04:31:05 PM PDT 24 1203445046 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1077535352 Aug 15 04:31:05 PM PDT 24 Aug 15 04:31:13 PM PDT 24 8448685214 ps
T387 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.837754523 Aug 15 04:31:43 PM PDT 24 Aug 15 04:31:44 PM PDT 24 500420326 ps
T388 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2109609296 Aug 15 04:31:03 PM PDT 24 Aug 15 04:31:04 PM PDT 24 627449175 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3983699911 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:05 PM PDT 24 503860432 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2901802216 Aug 15 04:31:28 PM PDT 24 Aug 15 04:31:30 PM PDT 24 403149487 ps
T62 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4158222501 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:33 PM PDT 24 469725611 ps
T391 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3130803224 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:21 PM PDT 24 431184378 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1344084720 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:37 PM PDT 24 4304372137 ps
T393 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4093344136 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:05 PM PDT 24 579892855 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3804648881 Aug 15 04:31:20 PM PDT 24 Aug 15 04:31:22 PM PDT 24 314656817 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1779730189 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:04 PM PDT 24 374253875 ps
T396 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.534183610 Aug 15 04:31:21 PM PDT 24 Aug 15 04:31:22 PM PDT 24 1299203866 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2318259217 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:32 PM PDT 24 523683481 ps
T398 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2351530301 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 318462741 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2273918918 Aug 15 04:31:09 PM PDT 24 Aug 15 04:31:10 PM PDT 24 573427113 ps
T400 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.860448535 Aug 15 04:31:29 PM PDT 24 Aug 15 04:31:30 PM PDT 24 560013099 ps
T401 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2143758299 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 427234390 ps
T402 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.795493981 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 338381917 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3098364197 Aug 15 04:31:15 PM PDT 24 Aug 15 04:31:17 PM PDT 24 1635522031 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2175798768 Aug 15 04:31:11 PM PDT 24 Aug 15 04:31:12 PM PDT 24 343710271 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.176645907 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:26 PM PDT 24 431887067 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3612090101 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:32 PM PDT 24 476764390 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3924266247 Aug 15 04:31:24 PM PDT 24 Aug 15 04:31:26 PM PDT 24 4259352305 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3811113008 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:20 PM PDT 24 4323096780 ps
T409 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1366750143 Aug 15 04:31:41 PM PDT 24 Aug 15 04:31:42 PM PDT 24 300078108 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2418529962 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:38 PM PDT 24 4291683308 ps
T411 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.953079833 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 483869265 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1354140950 Aug 15 04:31:04 PM PDT 24 Aug 15 04:31:06 PM PDT 24 390385556 ps
T413 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2001132719 Aug 15 04:31:41 PM PDT 24 Aug 15 04:31:42 PM PDT 24 302321854 ps
T414 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3291031858 Aug 15 04:31:27 PM PDT 24 Aug 15 04:31:30 PM PDT 24 4235467879 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1071800856 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:23 PM PDT 24 504174135 ps
T416 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3580566585 Aug 15 04:31:02 PM PDT 24 Aug 15 04:31:08 PM PDT 24 7323580942 ps
T417 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3860611857 Aug 15 04:31:22 PM PDT 24 Aug 15 04:31:24 PM PDT 24 2352196395 ps
T418 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4188752858 Aug 15 04:31:38 PM PDT 24 Aug 15 04:31:39 PM PDT 24 500799163 ps
T419 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.366243013 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:34 PM PDT 24 4248527594 ps
T420 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2120890159 Aug 15 04:31:37 PM PDT 24 Aug 15 04:31:38 PM PDT 24 334458029 ps
T421 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1219799104 Aug 15 04:31:09 PM PDT 24 Aug 15 04:31:11 PM PDT 24 566125353 ps
T422 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2846158591 Aug 15 04:31:30 PM PDT 24 Aug 15 04:31:32 PM PDT 24 463028481 ps
T423 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1840052509 Aug 15 04:31:44 PM PDT 24 Aug 15 04:31:45 PM PDT 24 295137259 ps
T424 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1278892018 Aug 15 04:31:14 PM PDT 24 Aug 15 04:31:14 PM PDT 24 355813437 ps
T425 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2315710787 Aug 15 04:31:31 PM PDT 24 Aug 15 04:31:33 PM PDT 24 452592509 ps

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4169157564
Short name T9
Test name
Test status
Simulation time 2692409382 ps
CPU time 15.76 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:24:32 PM PDT 24
Peak memory 206600 kb
Host smart-98465d30-8be3-4d57-9da8-5444915bf6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169157564 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4169157564
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3948885413
Short name T4
Test name
Test status
Simulation time 195637730727 ps
CPU time 295.96 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:25:51 PM PDT 24
Peak memory 198272 kb
Host smart-b7e944ba-f349-48d5-94b2-380b0626a13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948885413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3948885413
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3529894391
Short name T53
Test name
Test status
Simulation time 388311593 ps
CPU time 0.82 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 193176 kb
Host smart-f2806edf-56f3-4112-a5b2-0eaba1a63b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529894391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3529894391
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1484379784
Short name T98
Test name
Test status
Simulation time 32640578691 ps
CPU time 36.54 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:23:56 PM PDT 24
Peak memory 198304 kb
Host smart-c073afab-8916-4ff1-8709-6f09011d47d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484379784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1484379784
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3308270223
Short name T17
Test name
Test status
Simulation time 4504375482 ps
CPU time 1.69 seconds
Started Aug 15 04:20:16 PM PDT 24
Finished Aug 15 04:20:17 PM PDT 24
Peak memory 215932 kb
Host smart-0e53b7cc-bb5d-4ddd-85ae-720c5d7b0f36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308270223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3308270223
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2315600257
Short name T50
Test name
Test status
Simulation time 145258476542 ps
CPU time 92.82 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:25:02 PM PDT 24
Peak memory 192716 kb
Host smart-bb8eca95-fcff-422f-bc9f-9b02ef9dedfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315600257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2315600257
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.368365857
Short name T27
Test name
Test status
Simulation time 44285083773 ps
CPU time 36.47 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:43 PM PDT 24
Peak memory 191808 kb
Host smart-87d197e9-c79e-4f69-b229-e62578d647bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368365857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.368365857
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.760023407
Short name T45
Test name
Test status
Simulation time 28485414322 ps
CPU time 20.01 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:37 PM PDT 24
Peak memory 205868 kb
Host smart-25aace14-7b80-4a0d-9c40-64ce34b1f203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760023407 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.760023407
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2834561291
Short name T133
Test name
Test status
Simulation time 204081553016 ps
CPU time 294.63 seconds
Started Aug 15 04:23:27 PM PDT 24
Finished Aug 15 04:28:22 PM PDT 24
Peak memory 191508 kb
Host smart-c84fa822-6366-4651-9149-69ff2ae686af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834561291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2834561291
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2525941670
Short name T109
Test name
Test status
Simulation time 6550276992 ps
CPU time 5.08 seconds
Started Aug 15 04:23:55 PM PDT 24
Finished Aug 15 04:24:00 PM PDT 24
Peak memory 191936 kb
Host smart-dea0266e-9ce3-4e18-a78a-6e9abab966c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525941670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2525941670
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3257307496
Short name T88
Test name
Test status
Simulation time 230564413716 ps
CPU time 68.52 seconds
Started Aug 15 04:19:25 PM PDT 24
Finished Aug 15 04:20:33 PM PDT 24
Peak memory 193096 kb
Host smart-f132c8e7-7ef9-4b14-85e1-92bff9f3b559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257307496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3257307496
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3894664730
Short name T104
Test name
Test status
Simulation time 153639838110 ps
CPU time 13.56 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:31 PM PDT 24
Peak memory 196696 kb
Host smart-d80552ae-55e5-407c-86a1-44939adc0793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894664730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3894664730
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.80331254
Short name T103
Test name
Test status
Simulation time 200216830073 ps
CPU time 33.34 seconds
Started Aug 15 04:24:59 PM PDT 24
Finished Aug 15 04:25:33 PM PDT 24
Peak memory 191744 kb
Host smart-07ec41b6-2ee7-4e3f-9310-64bd6a31bef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80331254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_al
l.80331254
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3670957601
Short name T75
Test name
Test status
Simulation time 2928940187 ps
CPU time 13.28 seconds
Started Aug 15 04:23:50 PM PDT 24
Finished Aug 15 04:24:03 PM PDT 24
Peak memory 206756 kb
Host smart-eb456ece-9251-4e16-85b9-7085fafca0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670957601 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3670957601
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.428030750
Short name T108
Test name
Test status
Simulation time 117791798584 ps
CPU time 175.77 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:25:51 PM PDT 24
Peak memory 192640 kb
Host smart-e6766bff-119a-4f19-a34d-f82d97a93f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428030750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.428030750
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2555365939
Short name T93
Test name
Test status
Simulation time 6871949146 ps
CPU time 14.57 seconds
Started Aug 15 04:23:35 PM PDT 24
Finished Aug 15 04:23:50 PM PDT 24
Peak memory 197200 kb
Host smart-0d587324-1c34-4392-9e87-84f633255a9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555365939 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2555365939
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4257045450
Short name T110
Test name
Test status
Simulation time 245574011678 ps
CPU time 173.98 seconds
Started Aug 15 04:23:30 PM PDT 24
Finished Aug 15 04:26:24 PM PDT 24
Peak memory 198244 kb
Host smart-c797e3c0-76c0-4f36-a08d-9cf7407c0ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257045450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4257045450
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2144171260
Short name T106
Test name
Test status
Simulation time 706814895473 ps
CPU time 131.09 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:25:31 PM PDT 24
Peak memory 193080 kb
Host smart-a984623f-09fc-49e8-89f8-329332ef4353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144171260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2144171260
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2223992858
Short name T190
Test name
Test status
Simulation time 8156117372 ps
CPU time 8.27 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 198268 kb
Host smart-7f881f43-60c2-446d-8a66-3378f93a401a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223992858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2223992858
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3113368710
Short name T81
Test name
Test status
Simulation time 6240193799 ps
CPU time 20.69 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:23:38 PM PDT 24
Peak memory 206852 kb
Host smart-e16efce2-f79f-4aa1-8a86-d802a2237113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113368710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3113368710
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3560969385
Short name T107
Test name
Test status
Simulation time 27687065641 ps
CPU time 10.58 seconds
Started Aug 15 04:23:35 PM PDT 24
Finished Aug 15 04:23:46 PM PDT 24
Peak memory 196912 kb
Host smart-e52ef139-a03b-49ae-b704-5bed704415e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560969385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3560969385
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1881984774
Short name T83
Test name
Test status
Simulation time 242391570456 ps
CPU time 166.97 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:27:04 PM PDT 24
Peak memory 192360 kb
Host smart-3085fa69-85fb-457c-8700-0cc6709169be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881984774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1881984774
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4061920485
Short name T8
Test name
Test status
Simulation time 212707462940 ps
CPU time 301.58 seconds
Started Aug 15 04:20:50 PM PDT 24
Finished Aug 15 04:25:52 PM PDT 24
Peak memory 192456 kb
Host smart-396687a0-0613-4a8a-aa3b-643f88c7d15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061920485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4061920485
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2613079388
Short name T33
Test name
Test status
Simulation time 137580879186 ps
CPU time 185.89 seconds
Started Aug 15 04:23:47 PM PDT 24
Finished Aug 15 04:26:53 PM PDT 24
Peak memory 192624 kb
Host smart-8ec22018-f689-4d8d-9354-0b352fb931c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613079388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2613079388
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2965987041
Short name T101
Test name
Test status
Simulation time 122328859727 ps
CPU time 137.94 seconds
Started Aug 15 04:21:09 PM PDT 24
Finished Aug 15 04:23:27 PM PDT 24
Peak memory 198328 kb
Host smart-10ca3128-accc-480e-9d7a-4dd2217b0cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965987041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2965987041
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2188561457
Short name T89
Test name
Test status
Simulation time 80077873536 ps
CPU time 23.55 seconds
Started Aug 15 04:23:06 PM PDT 24
Finished Aug 15 04:23:29 PM PDT 24
Peak memory 196948 kb
Host smart-bc8f10ec-eff2-4ecf-a5f6-1a07a20c2aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188561457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2188561457
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1317578275
Short name T113
Test name
Test status
Simulation time 7151409260 ps
CPU time 37.08 seconds
Started Aug 15 04:20:55 PM PDT 24
Finished Aug 15 04:21:32 PM PDT 24
Peak memory 198552 kb
Host smart-a8f063e3-15f4-4799-ac0c-44c0f85f8196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317578275 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1317578275
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2927068591
Short name T112
Test name
Test status
Simulation time 198371992293 ps
CPU time 251.61 seconds
Started Aug 15 04:19:27 PM PDT 24
Finished Aug 15 04:23:39 PM PDT 24
Peak memory 193008 kb
Host smart-85137b22-2e86-46a9-95f8-b4fca11b772e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927068591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2927068591
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1077486984
Short name T156
Test name
Test status
Simulation time 36690431720 ps
CPU time 29.09 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:24:03 PM PDT 24
Peak memory 213172 kb
Host smart-46cafb9a-f618-492c-9d0f-6b70763feee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077486984 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1077486984
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2690060655
Short name T97
Test name
Test status
Simulation time 2190560262 ps
CPU time 10.76 seconds
Started Aug 15 04:23:05 PM PDT 24
Finished Aug 15 04:23:16 PM PDT 24
Peak memory 213996 kb
Host smart-a4b322aa-8113-44b7-92e7-e7f42de186ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690060655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2690060655
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.659927449
Short name T124
Test name
Test status
Simulation time 65963125450 ps
CPU time 103.96 seconds
Started Aug 15 04:18:26 PM PDT 24
Finished Aug 15 04:20:10 PM PDT 24
Peak memory 198684 kb
Host smart-371fb440-2c14-44b2-bb65-420f88a52efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659927449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.659927449
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.674278395
Short name T122
Test name
Test status
Simulation time 211299563140 ps
CPU time 307.76 seconds
Started Aug 15 04:20:00 PM PDT 24
Finished Aug 15 04:25:08 PM PDT 24
Peak memory 193076 kb
Host smart-c5ef09c6-a6ae-4949-9647-fe58fad5e9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674278395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.674278395
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3317436423
Short name T132
Test name
Test status
Simulation time 357407594223 ps
CPU time 538.68 seconds
Started Aug 15 04:20:49 PM PDT 24
Finished Aug 15 04:29:48 PM PDT 24
Peak memory 192680 kb
Host smart-3aa88495-72d5-4cee-925a-c8229023db8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317436423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3317436423
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3061956052
Short name T102
Test name
Test status
Simulation time 1169474335 ps
CPU time 6.48 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:23:02 PM PDT 24
Peak memory 206460 kb
Host smart-a8f80f54-7560-499f-a2b5-14a44402d6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061956052 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3061956052
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3097028795
Short name T28
Test name
Test status
Simulation time 70423005596 ps
CPU time 96.16 seconds
Started Aug 15 04:24:07 PM PDT 24
Finished Aug 15 04:25:43 PM PDT 24
Peak memory 193048 kb
Host smart-eea02742-2795-4552-85de-bb64e555c000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097028795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3097028795
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2574926967
Short name T95
Test name
Test status
Simulation time 814082385952 ps
CPU time 638.48 seconds
Started Aug 15 04:20:17 PM PDT 24
Finished Aug 15 04:30:56 PM PDT 24
Peak memory 198368 kb
Host smart-35298c2f-6d52-4c16-9ad1-e10bed01fa9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574926967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2574926967
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3710796467
Short name T131
Test name
Test status
Simulation time 4779804545 ps
CPU time 22.79 seconds
Started Aug 15 04:24:07 PM PDT 24
Finished Aug 15 04:24:30 PM PDT 24
Peak memory 206780 kb
Host smart-d7749b5b-eb82-4f7d-8377-b8773e21d8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710796467 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3710796467
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1785540261
Short name T87
Test name
Test status
Simulation time 5198440769 ps
CPU time 32.97 seconds
Started Aug 15 04:23:23 PM PDT 24
Finished Aug 15 04:23:57 PM PDT 24
Peak memory 206828 kb
Host smart-dd8815c5-c544-4667-b430-37eabe5fa6f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785540261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1785540261
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3898794141
Short name T168
Test name
Test status
Simulation time 28995098671 ps
CPU time 22.97 seconds
Started Aug 15 04:22:58 PM PDT 24
Finished Aug 15 04:23:21 PM PDT 24
Peak memory 213288 kb
Host smart-b9a5c968-ef90-4e14-9d22-0b25f18738dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898794141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3898794141
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3013384504
Short name T92
Test name
Test status
Simulation time 68287006682 ps
CPU time 47.64 seconds
Started Aug 15 04:23:23 PM PDT 24
Finished Aug 15 04:24:11 PM PDT 24
Peak memory 198340 kb
Host smart-cbbe70ac-2f7b-406f-a4ab-33b16b946688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013384504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3013384504
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.920656307
Short name T115
Test name
Test status
Simulation time 9771550065 ps
CPU time 40.01 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:23:35 PM PDT 24
Peak memory 198180 kb
Host smart-89039720-d603-46ce-a3b5-f883691f1ed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920656307 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.920656307
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2159891643
Short name T36
Test name
Test status
Simulation time 39905603793 ps
CPU time 36.01 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:23:53 PM PDT 24
Peak memory 197772 kb
Host smart-6184769a-5853-48c1-83e6-17924652804e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159891643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2159891643
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1118169494
Short name T51
Test name
Test status
Simulation time 299053685835 ps
CPU time 413.3 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:30:58 PM PDT 24
Peak memory 192996 kb
Host smart-e4c1b544-e312-4514-9097-e7045040f38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118169494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1118169494
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1754396633
Short name T143
Test name
Test status
Simulation time 126099659072 ps
CPU time 40.58 seconds
Started Aug 15 04:23:05 PM PDT 24
Finished Aug 15 04:23:46 PM PDT 24
Peak memory 191364 kb
Host smart-41f1ac4c-aed8-4d2d-9309-2c11e427bb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754396633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1754396633
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.834964162
Short name T148
Test name
Test status
Simulation time 226642840972 ps
CPU time 74.16 seconds
Started Aug 15 04:20:24 PM PDT 24
Finished Aug 15 04:21:38 PM PDT 24
Peak memory 192636 kb
Host smart-9fabeee3-b241-4966-84e2-9c75d347ead2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834964162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.834964162
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.974939614
Short name T129
Test name
Test status
Simulation time 166761983412 ps
CPU time 119.38 seconds
Started Aug 15 04:22:58 PM PDT 24
Finished Aug 15 04:24:58 PM PDT 24
Peak memory 191300 kb
Host smart-746180bc-f2f7-4c69-b470-4e076090d02e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974939614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.974939614
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1833919704
Short name T128
Test name
Test status
Simulation time 161970765264 ps
CPU time 118.37 seconds
Started Aug 15 04:22:46 PM PDT 24
Finished Aug 15 04:24:44 PM PDT 24
Peak memory 190884 kb
Host smart-04d17cc3-ec93-4732-855f-6eced6709ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833919704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1833919704
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2737405871
Short name T78
Test name
Test status
Simulation time 2115516473 ps
CPU time 12.35 seconds
Started Aug 15 04:18:54 PM PDT 24
Finished Aug 15 04:19:06 PM PDT 24
Peak memory 213952 kb
Host smart-99bacc74-f5ec-4f13-a50c-013c0cd8f743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737405871 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2737405871
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3257721219
Short name T119
Test name
Test status
Simulation time 256757974300 ps
CPU time 330.38 seconds
Started Aug 15 04:22:59 PM PDT 24
Finished Aug 15 04:28:29 PM PDT 24
Peak memory 192336 kb
Host smart-6445f21f-b613-478c-8dff-d2e970baaa7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257721219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3257721219
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4022625887
Short name T100
Test name
Test status
Simulation time 171904557635 ps
CPU time 135.01 seconds
Started Aug 15 04:21:46 PM PDT 24
Finished Aug 15 04:24:02 PM PDT 24
Peak memory 198388 kb
Host smart-6dce48c8-b533-451b-9d9b-cb29b5bf8ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022625887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4022625887
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1487911347
Short name T117
Test name
Test status
Simulation time 7280522583 ps
CPU time 23.16 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:46 PM PDT 24
Peak memory 214044 kb
Host smart-318a64af-c776-4647-9182-fa280cfe0546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487911347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1487911347
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.828883001
Short name T144
Test name
Test status
Simulation time 108423970911 ps
CPU time 105.77 seconds
Started Aug 15 04:24:45 PM PDT 24
Finished Aug 15 04:26:32 PM PDT 24
Peak memory 191876 kb
Host smart-4f211f93-9357-4b13-91d4-333365468dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828883001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.828883001
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3151144392
Short name T77
Test name
Test status
Simulation time 38004983647 ps
CPU time 23.42 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:23:58 PM PDT 24
Peak memory 206820 kb
Host smart-3951db54-4693-477d-af3a-9fe7d0242021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151144392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3151144392
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2095711178
Short name T114
Test name
Test status
Simulation time 164551633508 ps
CPU time 61.1 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:24:23 PM PDT 24
Peak memory 192136 kb
Host smart-53f59954-589b-4711-a620-45ab532dad7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095711178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2095711178
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.83346428
Short name T154
Test name
Test status
Simulation time 2865037429 ps
CPU time 17.6 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:23:50 PM PDT 24
Peak memory 198700 kb
Host smart-66e6284b-a9e5-4f73-be91-ddc2820380b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83346428 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.83346428
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.529844533
Short name T145
Test name
Test status
Simulation time 184427729423 ps
CPU time 127.27 seconds
Started Aug 15 04:24:20 PM PDT 24
Finished Aug 15 04:26:27 PM PDT 24
Peak memory 191964 kb
Host smart-2ac8ef93-99a4-485f-beff-85c13affa8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529844533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.529844533
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.562488783
Short name T44
Test name
Test status
Simulation time 21316240930 ps
CPU time 47.17 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:49 PM PDT 24
Peak memory 205592 kb
Host smart-76ff2b2b-5fd5-4009-8985-4c3eb5191f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562488783 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.562488783
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1635909477
Short name T123
Test name
Test status
Simulation time 590460878 ps
CPU time 1.56 seconds
Started Aug 15 04:23:17 PM PDT 24
Finished Aug 15 04:23:19 PM PDT 24
Peak memory 196832 kb
Host smart-b74e1428-197e-4292-96af-3e05a1ff6281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635909477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1635909477
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2217741167
Short name T158
Test name
Test status
Simulation time 2929211047 ps
CPU time 17.76 seconds
Started Aug 15 04:21:10 PM PDT 24
Finished Aug 15 04:21:28 PM PDT 24
Peak memory 214168 kb
Host smart-4012c04d-80e4-47a0-8cee-f0cd35db5baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217741167 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2217741167
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1819019792
Short name T34
Test name
Test status
Simulation time 435004390 ps
CPU time 0.94 seconds
Started Aug 15 04:24:01 PM PDT 24
Finished Aug 15 04:24:02 PM PDT 24
Peak memory 196824 kb
Host smart-3896dc4c-43b7-4ed3-898a-642bf74f0de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819019792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1819019792
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.729133093
Short name T111
Test name
Test status
Simulation time 1702678928 ps
CPU time 11.17 seconds
Started Aug 15 04:23:12 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 206564 kb
Host smart-73820238-f7ca-4633-aee1-50aa96f9468b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729133093 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.729133093
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1340577107
Short name T116
Test name
Test status
Simulation time 572323144 ps
CPU time 0.99 seconds
Started Aug 15 04:24:20 PM PDT 24
Finished Aug 15 04:24:21 PM PDT 24
Peak memory 196588 kb
Host smart-b09f747e-c0b8-4990-bbe8-8dd47a67cae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340577107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1340577107
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1041381722
Short name T94
Test name
Test status
Simulation time 246438909878 ps
CPU time 94.46 seconds
Started Aug 15 04:23:51 PM PDT 24
Finished Aug 15 04:25:25 PM PDT 24
Peak memory 198164 kb
Host smart-5bda647a-aa24-4e91-99e0-0bf9a291efd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041381722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1041381722
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3143131589
Short name T137
Test name
Test status
Simulation time 412372879 ps
CPU time 0.76 seconds
Started Aug 15 04:19:29 PM PDT 24
Finished Aug 15 04:19:30 PM PDT 24
Peak memory 196456 kb
Host smart-6bd23957-6f1f-423b-8c0e-69750608c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143131589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3143131589
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3753171464
Short name T76
Test name
Test status
Simulation time 5734785051 ps
CPU time 32.86 seconds
Started Aug 15 04:24:20 PM PDT 24
Finished Aug 15 04:24:53 PM PDT 24
Peak memory 214304 kb
Host smart-97abae4f-1363-4719-91a2-a247527ef334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753171464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3753171464
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2271617241
Short name T134
Test name
Test status
Simulation time 278607137706 ps
CPU time 166.64 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:25:56 PM PDT 24
Peak memory 198148 kb
Host smart-5626de31-4b7e-439e-ac9d-735210077a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271617241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2271617241
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1885365290
Short name T46
Test name
Test status
Simulation time 1704060271 ps
CPU time 12.33 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:28 PM PDT 24
Peak memory 199176 kb
Host smart-615950ff-7713-421a-8737-e66bfb20ac31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885365290 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1885365290
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.113309102
Short name T84
Test name
Test status
Simulation time 376179218 ps
CPU time 0.76 seconds
Started Aug 15 04:23:27 PM PDT 24
Finished Aug 15 04:23:28 PM PDT 24
Peak memory 195792 kb
Host smart-4079a71a-47c8-46ef-aa3b-3aab9225ac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113309102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.113309102
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1815970567
Short name T127
Test name
Test status
Simulation time 3781033939 ps
CPU time 16.11 seconds
Started Aug 15 04:23:51 PM PDT 24
Finished Aug 15 04:24:07 PM PDT 24
Peak memory 206792 kb
Host smart-174787fa-3e9d-4a0d-9e88-7a95d427014a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815970567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1815970567
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2465539292
Short name T85
Test name
Test status
Simulation time 488725645 ps
CPU time 1.22 seconds
Started Aug 15 04:19:34 PM PDT 24
Finished Aug 15 04:19:35 PM PDT 24
Peak memory 196792 kb
Host smart-dc690e29-15cc-4b19-90ff-4495ccc8f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465539292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2465539292
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.760854980
Short name T3
Test name
Test status
Simulation time 197510844955 ps
CPU time 257.51 seconds
Started Aug 15 04:20:11 PM PDT 24
Finished Aug 15 04:24:29 PM PDT 24
Peak memory 191976 kb
Host smart-c98c4dd9-c6ee-4556-a5c1-e97aa6cdd019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760854980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.760854980
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1003562787
Short name T52
Test name
Test status
Simulation time 398331693 ps
CPU time 0.96 seconds
Started Aug 15 04:18:30 PM PDT 24
Finished Aug 15 04:18:31 PM PDT 24
Peak memory 195996 kb
Host smart-21c03eb8-e4bf-413a-878d-06281d541158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003562787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1003562787
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4215559734
Short name T32
Test name
Test status
Simulation time 379539429 ps
CPU time 0.91 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:04 PM PDT 24
Peak memory 195620 kb
Host smart-9e2b9661-14c8-4d43-a161-539b4a6519ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215559734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4215559734
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1288745235
Short name T96
Test name
Test status
Simulation time 113279982327 ps
CPU time 161.39 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:23:36 PM PDT 24
Peak memory 198372 kb
Host smart-21c10edc-46c2-4645-917f-85c9f87b7aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288745235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1288745235
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.385444938
Short name T135
Test name
Test status
Simulation time 352510309 ps
CPU time 0.75 seconds
Started Aug 15 04:21:09 PM PDT 24
Finished Aug 15 04:21:10 PM PDT 24
Peak memory 196716 kb
Host smart-12840d7a-373d-479c-b980-c9f00289e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385444938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.385444938
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3029324434
Short name T86
Test name
Test status
Simulation time 545625547 ps
CPU time 0.65 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 196308 kb
Host smart-744e81e5-4c98-400d-bfd4-484249a2411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029324434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3029324434
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2425844005
Short name T146
Test name
Test status
Simulation time 1664809425 ps
CPU time 9.83 seconds
Started Aug 15 04:23:18 PM PDT 24
Finished Aug 15 04:23:29 PM PDT 24
Peak memory 213236 kb
Host smart-91bc6f5b-986c-4ae0-95b2-164fbf725c28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425844005 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2425844005
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1499024701
Short name T153
Test name
Test status
Simulation time 130551633093 ps
CPU time 94.49 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:24:30 PM PDT 24
Peak memory 192868 kb
Host smart-e7a32a2e-c7f6-4a1d-9152-607ea2d065b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499024701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1499024701
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.316510437
Short name T142
Test name
Test status
Simulation time 431824138 ps
CPU time 1.18 seconds
Started Aug 15 04:20:16 PM PDT 24
Finished Aug 15 04:20:17 PM PDT 24
Peak memory 196720 kb
Host smart-1b6b7b2c-0e2f-456b-980c-2ba3a36e39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316510437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.316510437
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.975823056
Short name T91
Test name
Test status
Simulation time 595727413 ps
CPU time 0.8 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:20 PM PDT 24
Peak memory 196800 kb
Host smart-e7af1cbf-00fe-4a46-b6d6-77bd25ed6114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975823056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.975823056
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3833074320
Short name T15
Test name
Test status
Simulation time 5836848340 ps
CPU time 28.21 seconds
Started Aug 15 04:19:30 PM PDT 24
Finished Aug 15 04:19:58 PM PDT 24
Peak memory 214300 kb
Host smart-211915bf-de7a-4df8-973b-33f1a3d2bd00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833074320 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3833074320
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4143411966
Short name T140
Test name
Test status
Simulation time 450543290 ps
CPU time 0.75 seconds
Started Aug 15 04:20:53 PM PDT 24
Finished Aug 15 04:20:54 PM PDT 24
Peak memory 197180 kb
Host smart-7eec0781-c785-4af2-aa5d-23844d5a478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143411966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4143411966
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2129223097
Short name T90
Test name
Test status
Simulation time 334023683 ps
CPU time 1.19 seconds
Started Aug 15 04:19:31 PM PDT 24
Finished Aug 15 04:19:32 PM PDT 24
Peak memory 197172 kb
Host smart-0055b85c-edb0-4f65-83c2-0222580c1e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129223097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2129223097
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4117129466
Short name T120
Test name
Test status
Simulation time 488010564 ps
CPU time 0.76 seconds
Started Aug 15 04:24:13 PM PDT 24
Finished Aug 15 04:24:14 PM PDT 24
Peak memory 196492 kb
Host smart-25b2e26e-a765-4c50-ad59-3e3563c149db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117129466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4117129466
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1346943570
Short name T125
Test name
Test status
Simulation time 456846486 ps
CPU time 0.89 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:06 PM PDT 24
Peak memory 196088 kb
Host smart-60368d1b-0e1a-40ef-b028-5e3377f05141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346943570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1346943570
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.324658674
Short name T105
Test name
Test status
Simulation time 238657719030 ps
CPU time 148.49 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:26:46 PM PDT 24
Peak memory 182984 kb
Host smart-c53b8109-a7de-4650-92ff-2020bed709be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324658674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.324658674
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1595787168
Short name T159
Test name
Test status
Simulation time 60006380719 ps
CPU time 87.22 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:24:49 PM PDT 24
Peak memory 191652 kb
Host smart-21439824-bff4-4730-8abd-e8d541ee8b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595787168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1595787168
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2259107532
Short name T14
Test name
Test status
Simulation time 526700632 ps
CPU time 0.78 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:04 PM PDT 24
Peak memory 195716 kb
Host smart-251b9249-2683-4cff-9f5e-62c3319fd0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259107532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2259107532
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.193856259
Short name T121
Test name
Test status
Simulation time 393317506 ps
CPU time 0.8 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:17 PM PDT 24
Peak memory 195412 kb
Host smart-7efa1ed4-0c46-4c8c-9ec5-d71e2e7ee1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193856259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.193856259
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2742973387
Short name T138
Test name
Test status
Simulation time 18745672993 ps
CPU time 19.89 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 04:24:41 PM PDT 24
Peak memory 213856 kb
Host smart-fb05ead6-4f6f-43a1-bab4-5b4c3fa2739b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742973387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2742973387
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.367935780
Short name T163
Test name
Test status
Simulation time 261269556083 ps
CPU time 55.4 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 04:25:16 PM PDT 24
Peak memory 191940 kb
Host smart-22e95c03-e51b-47d2-b771-e0ffa1ad6020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367935780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.367935780
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2127805598
Short name T151
Test name
Test status
Simulation time 154957884240 ps
CPU time 220.16 seconds
Started Aug 15 04:20:59 PM PDT 24
Finished Aug 15 04:24:39 PM PDT 24
Peak memory 191992 kb
Host smart-f4f41761-f807-4578-ac70-e7284368db85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127805598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2127805598
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3890381196
Short name T118
Test name
Test status
Simulation time 478625073 ps
CPU time 0.96 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:03 PM PDT 24
Peak memory 196236 kb
Host smart-4138bc5e-86a4-4133-9f5c-7903c0ab143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890381196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3890381196
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.497670222
Short name T141
Test name
Test status
Simulation time 468092224 ps
CPU time 0.92 seconds
Started Aug 15 04:18:44 PM PDT 24
Finished Aug 15 04:18:45 PM PDT 24
Peak memory 196708 kb
Host smart-6ece6474-8395-4508-93d4-00da2146c2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497670222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.497670222
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3255497578
Short name T35
Test name
Test status
Simulation time 436958065307 ps
CPU time 337.54 seconds
Started Aug 15 04:23:24 PM PDT 24
Finished Aug 15 04:29:02 PM PDT 24
Peak memory 198104 kb
Host smart-6c1ab7d8-0c8f-4423-824e-919280b88241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255497578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3255497578
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4145752414
Short name T29
Test name
Test status
Simulation time 415152462 ps
CPU time 1.19 seconds
Started Aug 15 04:20:06 PM PDT 24
Finished Aug 15 04:20:07 PM PDT 24
Peak memory 197100 kb
Host smart-f1dbf5a4-854a-43f9-9359-06c8db793420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145752414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4145752414
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2707875953
Short name T79
Test name
Test status
Simulation time 7959351597 ps
CPU time 11.27 seconds
Started Aug 15 04:19:28 PM PDT 24
Finished Aug 15 04:19:40 PM PDT 24
Peak memory 197384 kb
Host smart-82fe7a83-1786-4d46-a418-745b1d3ae80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707875953 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2707875953
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2295087778
Short name T43
Test name
Test status
Simulation time 8760399046 ps
CPU time 13.64 seconds
Started Aug 15 04:19:33 PM PDT 24
Finished Aug 15 04:19:47 PM PDT 24
Peak memory 198616 kb
Host smart-316b3565-9ac4-421f-a9ed-463d1c6bd54f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295087778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2295087778
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.805393507
Short name T155
Test name
Test status
Simulation time 12758416523 ps
CPU time 20.14 seconds
Started Aug 15 04:24:26 PM PDT 24
Finished Aug 15 04:24:46 PM PDT 24
Peak memory 213728 kb
Host smart-6c524cc2-4f7a-4d2f-91de-4046c34a3225
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805393507 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.805393507
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1233666617
Short name T167
Test name
Test status
Simulation time 8917214554 ps
CPU time 33.87 seconds
Started Aug 15 04:23:02 PM PDT 24
Finished Aug 15 04:23:36 PM PDT 24
Peak memory 205672 kb
Host smart-7dc3de6d-c1a4-4f1c-834d-3c94d81d7b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233666617 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1233666617
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.569492269
Short name T139
Test name
Test status
Simulation time 528673237 ps
CPU time 0.95 seconds
Started Aug 15 04:21:55 PM PDT 24
Finished Aug 15 04:21:56 PM PDT 24
Peak memory 196744 kb
Host smart-ac83a90e-d560-44ab-9c8a-6fd45f331140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569492269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.569492269
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.350021475
Short name T80
Test name
Test status
Simulation time 34239649606 ps
CPU time 17.74 seconds
Started Aug 15 04:24:02 PM PDT 24
Finished Aug 15 04:24:20 PM PDT 24
Peak memory 213328 kb
Host smart-d1ccb8c5-f2d1-45f8-8083-743d40ac61fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350021475 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.350021475
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.274439650
Short name T165
Test name
Test status
Simulation time 4146139301 ps
CPU time 26.56 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:44 PM PDT 24
Peak memory 198704 kb
Host smart-5335ca41-f913-448a-a994-36eae9d99a0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274439650 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.274439650
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2235604588
Short name T160
Test name
Test status
Simulation time 28249832207 ps
CPU time 35.33 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 04:24:56 PM PDT 24
Peak memory 206600 kb
Host smart-1b9ec7f0-7520-4447-a841-0286989fb64b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235604588 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2235604588
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2136277549
Short name T147
Test name
Test status
Simulation time 4677860055 ps
CPU time 17.87 seconds
Started Aug 15 04:19:28 PM PDT 24
Finished Aug 15 04:19:46 PM PDT 24
Peak memory 214116 kb
Host smart-7b63acd8-a8d6-442d-a9bf-5a907c549717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136277549 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2136277549
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.290322997
Short name T157
Test name
Test status
Simulation time 401128676 ps
CPU time 0.89 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 196748 kb
Host smart-44c65808-ef83-4bab-8941-41c7b96ee032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290322997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.290322997
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3120400856
Short name T184
Test name
Test status
Simulation time 1972100091 ps
CPU time 15.14 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:21:10 PM PDT 24
Peak memory 198604 kb
Host smart-29e2a572-26c3-41ed-a2bd-2e255845b52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120400856 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3120400856
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1234574280
Short name T82
Test name
Test status
Simulation time 3152045144 ps
CPU time 12.6 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:29 PM PDT 24
Peak memory 205720 kb
Host smart-900b5d9a-cd82-407c-aaf4-8de1b599dda5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234574280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1234574280
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2947060820
Short name T186
Test name
Test status
Simulation time 522434238 ps
CPU time 0.7 seconds
Started Aug 15 04:21:09 PM PDT 24
Finished Aug 15 04:21:10 PM PDT 24
Peak memory 196780 kb
Host smart-06e65a6c-4770-48fa-9677-114e3034f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947060820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2947060820
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3158307401
Short name T5
Test name
Test status
Simulation time 524931157 ps
CPU time 1.33 seconds
Started Aug 15 04:20:52 PM PDT 24
Finished Aug 15 04:20:54 PM PDT 24
Peak memory 196068 kb
Host smart-1427a316-6737-4a72-9876-a0bdc26480a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158307401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3158307401
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4171015639
Short name T130
Test name
Test status
Simulation time 514237087 ps
CPU time 0.7 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:20:55 PM PDT 24
Peak memory 196752 kb
Host smart-264ea27b-be50-40db-90b2-dbc4ecd99ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171015639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4171015639
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3140682092
Short name T174
Test name
Test status
Simulation time 385487521 ps
CPU time 0.71 seconds
Started Aug 15 04:24:26 PM PDT 24
Finished Aug 15 04:24:27 PM PDT 24
Peak memory 195736 kb
Host smart-38c104a8-e7df-43b1-9d1c-39a3222d86c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140682092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3140682092
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.615466755
Short name T164
Test name
Test status
Simulation time 489202149 ps
CPU time 0.93 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:24:17 PM PDT 24
Peak memory 195472 kb
Host smart-6287b6b0-9a44-403f-bb55-3266f50bcca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615466755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.615466755
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2069782868
Short name T25
Test name
Test status
Simulation time 545095244 ps
CPU time 1.3 seconds
Started Aug 15 04:23:00 PM PDT 24
Finished Aug 15 04:23:02 PM PDT 24
Peak memory 195988 kb
Host smart-9c8ec59b-6740-45a7-a853-052581d013c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069782868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2069782868
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.431455764
Short name T200
Test name
Test status
Simulation time 389120576 ps
CPU time 1.35 seconds
Started Aug 15 04:31:17 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 196508 kb
Host smart-b63d59e9-518c-4c27-b604-43b32720400f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431455764 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.431455764
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2040272574
Short name T172
Test name
Test status
Simulation time 435603545 ps
CPU time 1.18 seconds
Started Aug 15 04:23:18 PM PDT 24
Finished Aug 15 04:23:19 PM PDT 24
Peak memory 196692 kb
Host smart-9637fc19-5fe8-43f2-8a49-60e5454465b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040272574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2040272574
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1869180117
Short name T178
Test name
Test status
Simulation time 541560411 ps
CPU time 0.63 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:24:17 PM PDT 24
Peak memory 196440 kb
Host smart-f9790260-d512-4218-97f0-267ac3ca0993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869180117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1869180117
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1095462782
Short name T187
Test name
Test status
Simulation time 418189106 ps
CPU time 1.13 seconds
Started Aug 15 04:23:08 PM PDT 24
Finished Aug 15 04:23:10 PM PDT 24
Peak memory 195844 kb
Host smart-85e6d8b8-f7ec-43ef-ad0b-c0a450ba96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095462782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1095462782
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.96441700
Short name T176
Test name
Test status
Simulation time 352431137 ps
CPU time 0.85 seconds
Started Aug 15 04:21:39 PM PDT 24
Finished Aug 15 04:21:40 PM PDT 24
Peak memory 196688 kb
Host smart-edf7c2d9-45a1-40e6-bf20-5e4d865701e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96441700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.96441700
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3727163898
Short name T23
Test name
Test status
Simulation time 380387594 ps
CPU time 0.74 seconds
Started Aug 15 04:21:56 PM PDT 24
Finished Aug 15 04:21:56 PM PDT 24
Peak memory 196700 kb
Host smart-ccbd15f7-f901-4bee-90f0-f58d89d28dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727163898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3727163898
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4005057167
Short name T48
Test name
Test status
Simulation time 2211615834 ps
CPU time 17.36 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:23:13 PM PDT 24
Peak memory 196820 kb
Host smart-6266c722-2a82-45da-88cc-cb89cb533149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005057167 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4005057167
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.647052909
Short name T177
Test name
Test status
Simulation time 452195406 ps
CPU time 0.73 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:22:55 PM PDT 24
Peak memory 196724 kb
Host smart-4c7a32dd-110c-403f-b7a8-80cece736345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647052909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.647052909
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3471931171
Short name T47
Test name
Test status
Simulation time 10351842612 ps
CPU time 20.67 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:49 PM PDT 24
Peak memory 198596 kb
Host smart-a332dbb6-d727-43f8-aef4-5f2d57e5851e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471931171 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3471931171
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1679966548
Short name T179
Test name
Test status
Simulation time 255457100994 ps
CPU time 99.54 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:25:56 PM PDT 24
Peak memory 191016 kb
Host smart-8b314504-3600-438c-a697-00edd996b66c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679966548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1679966548
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1668805944
Short name T169
Test name
Test status
Simulation time 515641795 ps
CPU time 0.98 seconds
Started Aug 15 04:24:02 PM PDT 24
Finished Aug 15 04:24:03 PM PDT 24
Peak memory 196656 kb
Host smart-82bf2ba3-43b6-4434-b05a-9f4c63bfcad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668805944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1668805944
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2808922756
Short name T150
Test name
Test status
Simulation time 45283805336 ps
CPU time 19.82 seconds
Started Aug 15 04:24:15 PM PDT 24
Finished Aug 15 04:24:35 PM PDT 24
Peak memory 198116 kb
Host smart-c570525c-f07a-4ce7-b670-f051177071f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808922756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2808922756
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3743551146
Short name T188
Test name
Test status
Simulation time 926764502 ps
CPU time 7.82 seconds
Started Aug 15 04:20:38 PM PDT 24
Finished Aug 15 04:20:46 PM PDT 24
Peak memory 198536 kb
Host smart-1ba81781-4a97-4435-ae91-600c008857d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743551146 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3743551146
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1197984276
Short name T175
Test name
Test status
Simulation time 483197853 ps
CPU time 1 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:16 PM PDT 24
Peak memory 195956 kb
Host smart-81feb6c2-59fe-4c59-a53f-f11f8d2dec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197984276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1197984276
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.561059881
Short name T136
Test name
Test status
Simulation time 241042849042 ps
CPU time 81.24 seconds
Started Aug 15 04:19:47 PM PDT 24
Finished Aug 15 04:21:08 PM PDT 24
Peak memory 191984 kb
Host smart-77694a11-5531-439b-a4c3-240155d68f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561059881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.561059881
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2636690183
Short name T99
Test name
Test status
Simulation time 367522663 ps
CPU time 0.99 seconds
Started Aug 15 04:19:45 PM PDT 24
Finished Aug 15 04:19:46 PM PDT 24
Peak memory 196836 kb
Host smart-a69b399e-d84d-4fa8-bfd3-96fc7ad29ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636690183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2636690183
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1918582790
Short name T24
Test name
Test status
Simulation time 587147042 ps
CPU time 1.38 seconds
Started Aug 15 04:20:24 PM PDT 24
Finished Aug 15 04:20:25 PM PDT 24
Peak memory 196684 kb
Host smart-df745f87-63b7-42a5-894c-7ed9ed5cf399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918582790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1918582790
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3775968162
Short name T170
Test name
Test status
Simulation time 2316800888 ps
CPU time 15.48 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:44 PM PDT 24
Peak memory 206684 kb
Host smart-5bb21c1d-b285-4c50-94ed-ecf445be08ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775968162 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3775968162
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.888877418
Short name T182
Test name
Test status
Simulation time 45098320123 ps
CPU time 24.4 seconds
Started Aug 15 04:19:28 PM PDT 24
Finished Aug 15 04:19:53 PM PDT 24
Peak memory 205656 kb
Host smart-1c7dd37b-7ba8-4aa2-8b91-eaef4c293cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888877418 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.888877418
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2789422304
Short name T185
Test name
Test status
Simulation time 464143844 ps
CPU time 1.24 seconds
Started Aug 15 04:23:51 PM PDT 24
Finished Aug 15 04:23:52 PM PDT 24
Peak memory 196740 kb
Host smart-6ab20c93-51ba-49f4-a565-a51440291e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789422304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2789422304
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3658686643
Short name T161
Test name
Test status
Simulation time 468627263 ps
CPU time 0.83 seconds
Started Aug 15 04:19:56 PM PDT 24
Finished Aug 15 04:19:57 PM PDT 24
Peak memory 196788 kb
Host smart-f298c311-fba8-467a-bd7f-1ce530ba27eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658686643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3658686643
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2616985450
Short name T171
Test name
Test status
Simulation time 2298661407 ps
CPU time 21.62 seconds
Started Aug 15 04:24:02 PM PDT 24
Finished Aug 15 04:24:24 PM PDT 24
Peak memory 214528 kb
Host smart-14e70b69-2c1b-46ed-9f8b-8828ded17f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616985450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2616985450
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1097846686
Short name T173
Test name
Test status
Simulation time 506117153 ps
CPU time 0.75 seconds
Started Aug 15 04:23:57 PM PDT 24
Finished Aug 15 04:23:58 PM PDT 24
Peak memory 196620 kb
Host smart-7ee8c367-302a-4ac9-9fdf-3104aba105d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097846686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1097846686
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3051721003
Short name T162
Test name
Test status
Simulation time 131620984928 ps
CPU time 103.84 seconds
Started Aug 15 04:23:33 PM PDT 24
Finished Aug 15 04:25:17 PM PDT 24
Peak memory 191960 kb
Host smart-dbd3b7d9-84f9-4676-920c-bd7e46b8ff7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051721003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3051721003
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4009940854
Short name T341
Test name
Test status
Simulation time 554872923 ps
CPU time 0.83 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 193220 kb
Host smart-94af10c9-1ec2-4eca-8347-c64dbaf3b982
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009940854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4009940854
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3580566585
Short name T416
Test name
Test status
Simulation time 7323580942 ps
CPU time 5.94 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 195628 kb
Host smart-2a2cb29a-bc5b-41ab-934d-c7eab2ecb0e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580566585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3580566585
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2109609296
Short name T388
Test name
Test status
Simulation time 627449175 ps
CPU time 1.46 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 183692 kb
Host smart-eb84e4d2-8926-4358-b007-732366036bd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109609296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2109609296
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3334968827
Short name T314
Test name
Test status
Simulation time 460814073 ps
CPU time 0.97 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 198092 kb
Host smart-c0f7c548-ee0d-493e-83b4-63994400f95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334968827 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3334968827
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3591705081
Short name T68
Test name
Test status
Simulation time 500776392 ps
CPU time 0.91 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 192880 kb
Host smart-eaa100cd-0ca8-47d0-a263-2dc4b4be3c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591705081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3591705081
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3952716508
Short name T291
Test name
Test status
Simulation time 474929628 ps
CPU time 0.72 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 183548 kb
Host smart-41a87a67-9eee-4db6-9237-3a3d2e8dd547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952716508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3952716508
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2478599497
Short name T310
Test name
Test status
Simulation time 335903944 ps
CPU time 1.12 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 183504 kb
Host smart-1ece5349-3ad6-4cae-801d-78aa3a58a218
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478599497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2478599497
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3254271308
Short name T321
Test name
Test status
Simulation time 489198122 ps
CPU time 0.72 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:02 PM PDT 24
Peak memory 183492 kb
Host smart-bfd1c55e-7880-4688-970a-2c0592987c0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254271308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3254271308
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3686422022
Short name T385
Test name
Test status
Simulation time 1203445046 ps
CPU time 2.35 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 192920 kb
Host smart-8b3ca90c-97b0-4ede-967e-539eefc6ac76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686422022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3686422022
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3719050362
Short name T295
Test name
Test status
Simulation time 582613475 ps
CPU time 0.87 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:31:03 PM PDT 24
Peak memory 196904 kb
Host smart-52517fc9-1ce1-4398-817f-d93db9c747fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719050362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3719050362
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.263141305
Short name T347
Test name
Test status
Simulation time 8184175059 ps
CPU time 12.84 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 198080 kb
Host smart-c3660116-abb4-4e1b-afc5-221cb07d9b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263141305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.263141305
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.629816986
Short name T322
Test name
Test status
Simulation time 681986574 ps
CPU time 0.78 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 193300 kb
Host smart-c06f2774-3c9e-47f9-a21e-0220d2344e5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629816986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.629816986
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2978965759
Short name T63
Test name
Test status
Simulation time 12045260812 ps
CPU time 17.52 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 192168 kb
Host smart-aa2e6869-f39b-4d6e-9076-b1a7d3d9773d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978965759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2978965759
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2921165756
Short name T313
Test name
Test status
Simulation time 817265037 ps
CPU time 1.02 seconds
Started Aug 15 04:31:10 PM PDT 24
Finished Aug 15 04:31:11 PM PDT 24
Peak memory 183664 kb
Host smart-dda68f8b-3f76-462b-9b0c-e9f25e333799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921165756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2921165756
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1124576071
Short name T358
Test name
Test status
Simulation time 388639090 ps
CPU time 0.89 seconds
Started Aug 15 04:31:08 PM PDT 24
Finished Aug 15 04:31:09 PM PDT 24
Peak memory 193216 kb
Host smart-419037b6-4b4e-425b-8886-d5616a861717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124576071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1124576071
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1779730189
Short name T395
Test name
Test status
Simulation time 374253875 ps
CPU time 0.7 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 183660 kb
Host smart-42d728c9-8ae2-454c-950d-8629a17c5fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779730189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1779730189
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.559468673
Short name T369
Test name
Test status
Simulation time 511608663 ps
CPU time 0.69 seconds
Started Aug 15 04:31:12 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 183544 kb
Host smart-3b8e105b-fd2a-411a-b7f6-3f1a27847c18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559468673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.559468673
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1536051063
Short name T332
Test name
Test status
Simulation time 309412151 ps
CPU time 0.64 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 183536 kb
Host smart-137335a0-9ee3-4aba-af7a-928e5edfe166
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536051063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1536051063
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1623811223
Short name T73
Test name
Test status
Simulation time 2399849181 ps
CPU time 2.81 seconds
Started Aug 15 04:31:07 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 194956 kb
Host smart-cd28c128-568c-46ab-b404-a920968f435f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623811223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1623811223
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2273918918
Short name T399
Test name
Test status
Simulation time 573427113 ps
CPU time 1.23 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 198268 kb
Host smart-756df3ba-79ad-411b-a226-63e811794a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273918918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2273918918
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.432658858
Short name T193
Test name
Test status
Simulation time 8955583757 ps
CPU time 7.71 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 198200 kb
Host smart-94f4783d-19e9-4704-931e-acdaf35e2dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432658858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.432658858
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3855623880
Short name T307
Test name
Test status
Simulation time 392924836 ps
CPU time 1.32 seconds
Started Aug 15 04:31:28 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 196028 kb
Host smart-de89456e-1f91-462b-b8ea-4c4b135fdb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855623880 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3855623880
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3648598066
Short name T372
Test name
Test status
Simulation time 517851222 ps
CPU time 1.3 seconds
Started Aug 15 04:31:28 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 183604 kb
Host smart-12498c7f-a3fc-4fcd-b0fd-cf65b3cce1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648598066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3648598066
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1386101664
Short name T336
Test name
Test status
Simulation time 2085234041 ps
CPU time 3.42 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 191848 kb
Host smart-7a73c3f5-95e1-4e7c-86f8-33a4b3b3e623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386101664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1386101664
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2398803265
Short name T380
Test name
Test status
Simulation time 1612278662 ps
CPU time 1.6 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 198460 kb
Host smart-d7b481b9-f389-4582-aa97-2ebc302cd423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398803265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2398803265
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1890152594
Short name T368
Test name
Test status
Simulation time 4920663027 ps
CPU time 2.67 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 197844 kb
Host smart-9499e4ff-c09b-4266-9249-44abe42d8871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890152594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1890152594
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2849484903
Short name T329
Test name
Test status
Simulation time 595497999 ps
CPU time 0.92 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:25 PM PDT 24
Peak memory 195976 kb
Host smart-46d332df-44ec-4e41-baad-23ff875460c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849484903 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2849484903
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.176645907
Short name T405
Test name
Test status
Simulation time 431887067 ps
CPU time 1.27 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 193192 kb
Host smart-f2af66c9-9848-458e-8695-61cb2b99dc44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176645907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.176645907
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2833323534
Short name T306
Test name
Test status
Simulation time 516751590 ps
CPU time 1.34 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 192816 kb
Host smart-4fa59f82-3157-4a2f-b5fe-7ac0e5b76774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833323534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2833323534
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.534183610
Short name T396
Test name
Test status
Simulation time 1299203866 ps
CPU time 1.01 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 193688 kb
Host smart-43d7dcb4-6ba2-4849-9511-068c98241bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534183610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.534183610
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.58579628
Short name T289
Test name
Test status
Simulation time 443109941 ps
CPU time 2.19 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 198440 kb
Host smart-7ab901f5-06a2-4335-b3f2-7266be1ceb90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58579628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.58579628
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1092904618
Short name T371
Test name
Test status
Simulation time 8441816082 ps
CPU time 6.63 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 198156 kb
Host smart-98b0e3c3-b683-4343-a6af-21812ee273ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092904618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1092904618
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2781198020
Short name T38
Test name
Test status
Simulation time 561350315 ps
CPU time 1.45 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 196848 kb
Host smart-870a4309-1790-455e-8384-b04a2a65d35f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781198020 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2781198020
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3130803224
Short name T391
Test name
Test status
Simulation time 431184378 ps
CPU time 0.8 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:21 PM PDT 24
Peak memory 192944 kb
Host smart-388c2d81-ac6c-4028-80bb-805a1ef6679e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130803224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3130803224
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1071800856
Short name T415
Test name
Test status
Simulation time 504174135 ps
CPU time 0.91 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 183592 kb
Host smart-6934f708-1bab-410c-ac5a-103e8148c4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071800856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1071800856
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2616690993
Short name T325
Test name
Test status
Simulation time 2701237312 ps
CPU time 1.2 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 194904 kb
Host smart-b66fedd4-2313-4d5d-94d6-90c5232abfcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616690993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2616690993
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1409001882
Short name T304
Test name
Test status
Simulation time 525151757 ps
CPU time 1.81 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 198480 kb
Host smart-483b785c-aff7-4568-b63e-43a989713cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409001882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1409001882
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3975771078
Short name T41
Test name
Test status
Simulation time 8038846766 ps
CPU time 2.94 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:27 PM PDT 24
Peak memory 198172 kb
Host smart-c2cd076b-125f-4cab-a6cc-3fd70351c8f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975771078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3975771078
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2315710787
Short name T425
Test name
Test status
Simulation time 452592509 ps
CPU time 1.02 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 196188 kb
Host smart-bf9d4f1b-07be-467b-9ef8-aea1ff8056fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315710787 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2315710787
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4158222501
Short name T62
Test name
Test status
Simulation time 469725611 ps
CPU time 1.39 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 191944 kb
Host smart-e8afd4b6-4864-44cc-9e9e-3746197fd8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158222501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4158222501
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1337707128
Short name T298
Test name
Test status
Simulation time 301530008 ps
CPU time 1.02 seconds
Started Aug 15 04:31:33 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 192828 kb
Host smart-2b620664-9228-4939-80a7-156fb743e0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337707128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1337707128
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2113294419
Short name T352
Test name
Test status
Simulation time 2443377340 ps
CPU time 2.72 seconds
Started Aug 15 04:31:33 PM PDT 24
Finished Aug 15 04:31:36 PM PDT 24
Peak memory 194828 kb
Host smart-fc4a4347-7805-494d-af3c-d05b379a59b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113294419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2113294419
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3507688497
Short name T355
Test name
Test status
Simulation time 663954168 ps
CPU time 1.07 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 198056 kb
Host smart-de639b0f-1452-41d8-93b9-83b7422b30db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507688497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3507688497
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1344084720
Short name T392
Test name
Test status
Simulation time 4304372137 ps
CPU time 6.44 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 197716 kb
Host smart-d6355a5d-9855-434e-9869-7837865586e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344084720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1344084720
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1602203648
Short name T382
Test name
Test status
Simulation time 497410080 ps
CPU time 1.07 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 196676 kb
Host smart-82ae0328-92eb-4c84-af96-373a053a9802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602203648 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1602203648
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.860448535
Short name T400
Test name
Test status
Simulation time 560013099 ps
CPU time 0.86 seconds
Started Aug 15 04:31:29 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 193904 kb
Host smart-f6d9f0ed-0933-44e4-8da9-849af04b5641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860448535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.860448535
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.71388706
Short name T317
Test name
Test status
Simulation time 387603273 ps
CPU time 0.7 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 183724 kb
Host smart-04686bbb-df9c-4b6e-868e-f5da35aad6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71388706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.71388706
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1765935397
Short name T319
Test name
Test status
Simulation time 2863697858 ps
CPU time 4.7 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 193888 kb
Host smart-02fd4847-abb5-42c8-9921-3b2975de212a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765935397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1765935397
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1739027988
Short name T288
Test name
Test status
Simulation time 436697447 ps
CPU time 2.06 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 198456 kb
Host smart-50995d08-277d-4d4d-bdb7-3fd0ec18e23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739027988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1739027988
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4080633525
Short name T192
Test name
Test status
Simulation time 8406864965 ps
CPU time 4.3 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:35 PM PDT 24
Peak memory 197968 kb
Host smart-b4c5ff60-1ab8-4bf8-9b5a-d8be08b99095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080633525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4080633525
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3365558257
Short name T383
Test name
Test status
Simulation time 401072892 ps
CPU time 0.84 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 196160 kb
Host smart-f5259ead-7927-40a5-abc0-ec6db1889b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365558257 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3365558257
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3413162099
Short name T367
Test name
Test status
Simulation time 522616279 ps
CPU time 0.99 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 193268 kb
Host smart-635b22fd-c0a7-43ca-baed-e65eae4ce418
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413162099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3413162099
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3589665893
Short name T353
Test name
Test status
Simulation time 454281047 ps
CPU time 0.89 seconds
Started Aug 15 04:31:33 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 183608 kb
Host smart-f29813b8-0486-4d1b-a7d1-c7a58c02efe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589665893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3589665893
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1446884551
Short name T69
Test name
Test status
Simulation time 1005331782 ps
CPU time 2.14 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 193192 kb
Host smart-f118fe1c-9092-4f4f-8074-1b657fe0d13f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446884551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1446884551
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2789725626
Short name T290
Test name
Test status
Simulation time 587411538 ps
CPU time 2.34 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 198520 kb
Host smart-bf2ae8ac-24a7-4b50-882d-eb3adcd61130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789725626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2789725626
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2418529962
Short name T410
Test name
Test status
Simulation time 4291683308 ps
CPU time 7.26 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 198040 kb
Host smart-40eb8097-0564-473f-9e95-be9e89a51e22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418529962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2418529962
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3141035844
Short name T330
Test name
Test status
Simulation time 372050264 ps
CPU time 0.92 seconds
Started Aug 15 04:31:36 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 198308 kb
Host smart-40768c56-8084-4385-8467-7e6c01f3ae70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141035844 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3141035844
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3200505232
Short name T373
Test name
Test status
Simulation time 446821825 ps
CPU time 0.89 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 192872 kb
Host smart-eee2712d-5542-4878-809d-69f2bbaa9d97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200505232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3200505232
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2846158591
Short name T422
Test name
Test status
Simulation time 463028481 ps
CPU time 1.29 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 183604 kb
Host smart-50fac513-9251-46c9-b6b4-3d4417dff3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846158591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2846158591
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.85081029
Short name T357
Test name
Test status
Simulation time 2409681773 ps
CPU time 2.97 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 195000 kb
Host smart-e6d2f204-ddb7-486f-8965-232c7c9f5e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85081029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_
timer_same_csr_outstanding.85081029
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.967266316
Short name T381
Test name
Test status
Simulation time 1012854374 ps
CPU time 2.71 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:35 PM PDT 24
Peak memory 198556 kb
Host smart-a360d525-6a93-4e1e-83dd-3d4105f4fdc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967266316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.967266316
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4089381857
Short name T194
Test name
Test status
Simulation time 8565017062 ps
CPU time 6.43 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 198188 kb
Host smart-6aaf50ee-c8ae-43df-a597-66711c1daf09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089381857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4089381857
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3902840530
Short name T37
Test name
Test status
Simulation time 414217454 ps
CPU time 0.95 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 197512 kb
Host smart-ba87b370-e4d1-4029-aff8-6c02915e3adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902840530 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3902840530
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2257940116
Short name T342
Test name
Test status
Simulation time 529442926 ps
CPU time 0.71 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 193004 kb
Host smart-da660e41-3f12-4c0c-b4bc-18689f76c0e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257940116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2257940116
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2773760064
Short name T296
Test name
Test status
Simulation time 366738299 ps
CPU time 1.13 seconds
Started Aug 15 04:31:29 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 192816 kb
Host smart-88969cdb-4d1b-4693-ac77-5ec2320e6d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773760064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2773760064
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3470777208
Short name T70
Test name
Test status
Simulation time 1095831028 ps
CPU time 1.45 seconds
Started Aug 15 04:31:29 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 193440 kb
Host smart-a97be5c6-3e3c-4670-a01a-0b2839dfd533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470777208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3470777208
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.157465071
Short name T328
Test name
Test status
Simulation time 379704282 ps
CPU time 2.47 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 198460 kb
Host smart-1049262d-b785-486f-940d-cbd70b6dc605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157465071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.157465071
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1754695377
Short name T334
Test name
Test status
Simulation time 4418219098 ps
CPU time 3.98 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:36 PM PDT 24
Peak memory 197860 kb
Host smart-63622ff9-dd54-4443-b91d-e32417a52c97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754695377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1754695377
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1267559530
Short name T201
Test name
Test status
Simulation time 544822006 ps
CPU time 1.33 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 195596 kb
Host smart-96854021-7e9c-4fe5-859a-03a67bffe6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267559530 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1267559530
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3612090101
Short name T406
Test name
Test status
Simulation time 476764390 ps
CPU time 1.35 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 192816 kb
Host smart-ef9a6c24-2d8d-4366-ba48-01ac6df13fe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612090101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3612090101
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2318259217
Short name T397
Test name
Test status
Simulation time 523683481 ps
CPU time 0.75 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:32 PM PDT 24
Peak memory 183596 kb
Host smart-7b7494a9-7372-4146-bfb7-54bda7dc6f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318259217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2318259217
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2204656444
Short name T72
Test name
Test status
Simulation time 1335854072 ps
CPU time 1.3 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 193572 kb
Host smart-5a169677-c0ff-4fdc-8ff0-a310546eee1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204656444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2204656444
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1077863213
Short name T337
Test name
Test status
Simulation time 1158638504 ps
CPU time 1.46 seconds
Started Aug 15 04:31:29 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 198484 kb
Host smart-73822511-2b60-4826-988a-84c802a882c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077863213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1077863213
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.366243013
Short name T419
Test name
Test status
Simulation time 4248527594 ps
CPU time 2.94 seconds
Started Aug 15 04:31:31 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 197416 kb
Host smart-306069f7-ca24-4db6-8446-3e13583d9fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366243013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.366243013
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3910076579
Short name T300
Test name
Test status
Simulation time 601386691 ps
CPU time 0.95 seconds
Started Aug 15 04:31:41 PM PDT 24
Finished Aug 15 04:31:43 PM PDT 24
Peak memory 197444 kb
Host smart-b2d1963c-6278-43af-8b2b-cc7f49799518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910076579 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3910076579
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3016477023
Short name T346
Test name
Test status
Simulation time 307676359 ps
CPU time 1.05 seconds
Started Aug 15 04:31:42 PM PDT 24
Finished Aug 15 04:31:43 PM PDT 24
Peak memory 193284 kb
Host smart-2a561c6d-4cbe-4247-8942-b9a99cedca6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016477023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3016477023
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3012203630
Short name T339
Test name
Test status
Simulation time 425221476 ps
CPU time 1.08 seconds
Started Aug 15 04:31:42 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 183592 kb
Host smart-f1df5946-891c-48ec-9da1-9b85cddea26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012203630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3012203630
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.418718
Short name T363
Test name
Test status
Simulation time 1010813752 ps
CPU time 1.29 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 193452 kb
Host smart-2651c038-4441-48e6-8b41-9c6060177af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_same_csr_outstanding.418718
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2460947943
Short name T331
Test name
Test status
Simulation time 515697955 ps
CPU time 2.29 seconds
Started Aug 15 04:31:30 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 198460 kb
Host smart-e9b33acf-35e0-48cd-8aac-8ec9c1902cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460947943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2460947943
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.149021421
Short name T40
Test name
Test status
Simulation time 4912151749 ps
CPU time 1.17 seconds
Started Aug 15 04:31:42 PM PDT 24
Finished Aug 15 04:31:43 PM PDT 24
Peak memory 196632 kb
Host smart-ba1a7dd6-76e0-4d91-a181-1bf80330f8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149021421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.149021421
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3406466115
Short name T64
Test name
Test status
Simulation time 553289468 ps
CPU time 1.16 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 193896 kb
Host smart-f6397595-1551-4d56-8939-f1ba28ebdc6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406466115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3406466115
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2491832300
Short name T54
Test name
Test status
Simulation time 13703147064 ps
CPU time 19.86 seconds
Started Aug 15 04:31:07 PM PDT 24
Finished Aug 15 04:31:27 PM PDT 24
Peak memory 196272 kb
Host smart-131739d5-1c7f-433e-ba6c-62c79bae06e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491832300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2491832300
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2752568694
Short name T58
Test name
Test status
Simulation time 903705036 ps
CPU time 0.86 seconds
Started Aug 15 04:31:12 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 192048 kb
Host smart-ad360c0e-a08f-4e75-9150-9be00ef838d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752568694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2752568694
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.459109155
Short name T361
Test name
Test status
Simulation time 510449322 ps
CPU time 1.02 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 195328 kb
Host smart-f1542a84-cc69-4cb8-ba56-0da32efa05c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459109155 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.459109155
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1235322231
Short name T59
Test name
Test status
Simulation time 540020814 ps
CPU time 1.46 seconds
Started Aug 15 04:31:12 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 193452 kb
Host smart-6c7eb33e-a252-428c-9284-99d59a3cac64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235322231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1235322231
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1154073674
Short name T323
Test name
Test status
Simulation time 312165210 ps
CPU time 1 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 183624 kb
Host smart-bbea2a1c-28a6-4476-b163-00249fc75633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154073674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1154073674
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1354140950
Short name T412
Test name
Test status
Simulation time 390385556 ps
CPU time 1.1 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:06 PM PDT 24
Peak memory 183452 kb
Host smart-27fbe03e-7d0e-4aae-9fdc-5afacee12369
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354140950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1354140950
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1278892018
Short name T424
Test name
Test status
Simulation time 355813437 ps
CPU time 0.72 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 183512 kb
Host smart-1c4dfbcc-2f8f-47a9-99e8-4a13aa0b5e80
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278892018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1278892018
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3098364197
Short name T403
Test name
Test status
Simulation time 1635522031 ps
CPU time 2.27 seconds
Started Aug 15 04:31:15 PM PDT 24
Finished Aug 15 04:31:17 PM PDT 24
Peak memory 192940 kb
Host smart-9e21b1f8-9248-489a-861c-0309e0a13521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098364197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3098364197
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4093344136
Short name T393
Test name
Test status
Simulation time 579892855 ps
CPU time 1.33 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 198572 kb
Host smart-1ba1d034-6250-4c81-9271-0899324a89d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093344136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4093344136
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1077535352
Short name T386
Test name
Test status
Simulation time 8448685214 ps
CPU time 6.97 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 198136 kb
Host smart-a8a36b8e-309c-4cf2-919f-495ec2f3a987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077535352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1077535352
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1657938992
Short name T286
Test name
Test status
Simulation time 270986689 ps
CPU time 0.98 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 183720 kb
Host smart-d65a3a5c-9de0-4bac-ab51-cbbecd136ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657938992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1657938992
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.66093487
Short name T326
Test name
Test status
Simulation time 295780109 ps
CPU time 0.64 seconds
Started Aug 15 04:31:42 PM PDT 24
Finished Aug 15 04:31:42 PM PDT 24
Peak memory 192796 kb
Host smart-f1d69427-22eb-4b7c-b214-b265664c8891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66093487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.66093487
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4188752858
Short name T418
Test name
Test status
Simulation time 500799163 ps
CPU time 0.78 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 192812 kb
Host smart-1849d7f1-5f7d-4c7d-a395-482fac4096e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188752858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4188752858
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1520238284
Short name T375
Test name
Test status
Simulation time 496499671 ps
CPU time 0.98 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183636 kb
Host smart-5827028e-f944-4a57-8969-3ea13e664ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520238284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1520238284
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4224684037
Short name T376
Test name
Test status
Simulation time 347487091 ps
CPU time 1.01 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183624 kb
Host smart-bd16c011-fd0d-4456-bf6a-58e6bcce41c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224684037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4224684037
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.553235404
Short name T315
Test name
Test status
Simulation time 427809860 ps
CPU time 1.2 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 192824 kb
Host smart-439e9bba-4b50-4b7c-93e5-631938f4e6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553235404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.553235404
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2143758299
Short name T401
Test name
Test status
Simulation time 427234390 ps
CPU time 0.65 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 192828 kb
Host smart-2a1001b0-eade-45c2-8713-91bc55cd7a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143758299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2143758299
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.840393823
Short name T293
Test name
Test status
Simulation time 341067523 ps
CPU time 0.69 seconds
Started Aug 15 04:31:39 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 192832 kb
Host smart-cd7b7104-a795-444c-8f53-4b1f3e5a1994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840393823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.840393823
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2477261451
Short name T384
Test name
Test status
Simulation time 388582562 ps
CPU time 0.66 seconds
Started Aug 15 04:31:39 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 183584 kb
Host smart-024683d9-f4aa-4959-8131-facc1e194beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477261451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2477261451
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.837754523
Short name T387
Test name
Test status
Simulation time 500420326 ps
CPU time 0.74 seconds
Started Aug 15 04:31:43 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 183596 kb
Host smart-5a119026-acfd-4c5c-9069-2854dd9997b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837754523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.837754523
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3442149891
Short name T56
Test name
Test status
Simulation time 486274182 ps
CPU time 0.86 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 193904 kb
Host smart-2918e3c7-74bd-4eb8-b5e1-b358c0b0cf07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442149891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3442149891
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3093154915
Short name T55
Test name
Test status
Simulation time 10071807470 ps
CPU time 2.93 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 183988 kb
Host smart-3682b766-770c-4d9a-bb04-ebdf3f615d10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093154915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3093154915
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3317882036
Short name T39
Test name
Test status
Simulation time 1190502836 ps
CPU time 0.8 seconds
Started Aug 15 04:31:12 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 193220 kb
Host smart-c8364be9-803a-4dfa-9380-57a6c5eb60e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317882036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3317882036
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3983699911
Short name T389
Test name
Test status
Simulation time 503860432 ps
CPU time 0.76 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 195528 kb
Host smart-d671fa7a-cbad-448c-b17c-aae988d9943a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983699911 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3983699911
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4145477694
Short name T354
Test name
Test status
Simulation time 437069586 ps
CPU time 0.76 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 192864 kb
Host smart-0c5e3212-6115-4d4c-8ecd-947af82774f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145477694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4145477694
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2374952267
Short name T362
Test name
Test status
Simulation time 283834471 ps
CPU time 0.84 seconds
Started Aug 15 04:31:15 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 183572 kb
Host smart-45737a70-577d-4a9d-bb61-bfbe8790f1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374952267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2374952267
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2175798768
Short name T404
Test name
Test status
Simulation time 343710271 ps
CPU time 1.02 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 183536 kb
Host smart-ef7aec05-bcc2-4fef-81ca-3819c6922bc3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175798768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2175798768
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3878496409
Short name T344
Test name
Test status
Simulation time 434278693 ps
CPU time 0.84 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 183632 kb
Host smart-690ded2e-334c-485f-aabc-64fad8f7501a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878496409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3878496409
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1072823163
Short name T66
Test name
Test status
Simulation time 1597193045 ps
CPU time 2.24 seconds
Started Aug 15 04:31:10 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 193488 kb
Host smart-abc59466-041a-41d1-b928-8adf9ebf725c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072823163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1072823163
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1787436258
Short name T379
Test name
Test status
Simulation time 438450986 ps
CPU time 1.96 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 198456 kb
Host smart-96dfc105-3e77-4514-a2eb-553fef0dcf8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787436258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1787436258
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3811113008
Short name T408
Test name
Test status
Simulation time 4323096780 ps
CPU time 6.37 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:20 PM PDT 24
Peak memory 196448 kb
Host smart-49084d86-28c4-44b8-9d74-cc0f8cd95b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811113008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3811113008
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2001132719
Short name T413
Test name
Test status
Simulation time 302321854 ps
CPU time 1.02 seconds
Started Aug 15 04:31:41 PM PDT 24
Finished Aug 15 04:31:42 PM PDT 24
Peak memory 183680 kb
Host smart-1a84e972-7d21-4f82-92a0-68e495e3e3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001132719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2001132719
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4116343861
Short name T308
Test name
Test status
Simulation time 280122638 ps
CPU time 0.94 seconds
Started Aug 15 04:31:39 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 183536 kb
Host smart-34234091-608f-4d40-8e10-4eef7a2cb7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116343861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4116343861
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4049261131
Short name T335
Test name
Test status
Simulation time 325824912 ps
CPU time 0.71 seconds
Started Aug 15 04:31:41 PM PDT 24
Finished Aug 15 04:31:42 PM PDT 24
Peak memory 183680 kb
Host smart-861eec78-4321-4f77-827b-8cfd6d5f2a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049261131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4049261131
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2469560015
Short name T327
Test name
Test status
Simulation time 423728653 ps
CPU time 0.68 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183592 kb
Host smart-80c3f742-b6da-4794-8cc7-c8c33598ceae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469560015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2469560015
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.657365504
Short name T311
Test name
Test status
Simulation time 387507957 ps
CPU time 0.67 seconds
Started Aug 15 04:31:36 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 183660 kb
Host smart-fb2c9a49-b665-4faa-97d8-b3edd38cbfec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657365504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.657365504
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2738212466
Short name T287
Test name
Test status
Simulation time 527029107 ps
CPU time 0.75 seconds
Started Aug 15 04:31:40 PM PDT 24
Finished Aug 15 04:31:41 PM PDT 24
Peak memory 192800 kb
Host smart-7777c8f0-b623-4def-8cfb-1fbf0817bcb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738212466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2738212466
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2234084474
Short name T377
Test name
Test status
Simulation time 263385376 ps
CPU time 0.89 seconds
Started Aug 15 04:31:39 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 183616 kb
Host smart-c648d44c-584b-4fbf-a2da-d2518d67f617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234084474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2234084474
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2351530301
Short name T398
Test name
Test status
Simulation time 318462741 ps
CPU time 0.62 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183664 kb
Host smart-605fbcc6-3989-4b6f-95e1-df9b4f8a5043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351530301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2351530301
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1216573170
Short name T359
Test name
Test status
Simulation time 339848167 ps
CPU time 0.9 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183700 kb
Host smart-dd954a54-5fe4-49d2-832d-c10db548b94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216573170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1216573170
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.986967828
Short name T338
Test name
Test status
Simulation time 437781661 ps
CPU time 0.89 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 183668 kb
Host smart-a44e7aad-3c88-440c-a996-1930b9747db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986967828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.986967828
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2158065721
Short name T340
Test name
Test status
Simulation time 633646970 ps
CPU time 0.76 seconds
Started Aug 15 04:31:26 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 183652 kb
Host smart-66aedd7a-2dbf-4686-a1bb-7c3c1b3a513e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158065721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2158065721
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.650934114
Short name T57
Test name
Test status
Simulation time 6190037312 ps
CPU time 17.71 seconds
Started Aug 15 04:31:15 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 196008 kb
Host smart-6d672173-dae0-4971-b51d-0588359136ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650934114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.650934114
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1844560938
Short name T374
Test name
Test status
Simulation time 996564070 ps
CPU time 1.4 seconds
Started Aug 15 04:31:20 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 193224 kb
Host smart-4858edac-c39f-4132-9e57-81e476350003
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844560938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1844560938
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1846442645
Short name T316
Test name
Test status
Simulation time 396412054 ps
CPU time 1.15 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:15 PM PDT 24
Peak memory 196044 kb
Host smart-4b80ecd4-a8ef-41ee-a926-730d9e85d988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846442645 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1846442645
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1955292563
Short name T60
Test name
Test status
Simulation time 465686259 ps
CPU time 0.72 seconds
Started Aug 15 04:31:17 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 193236 kb
Host smart-ee911e51-7cf2-4cdb-98ba-6d15c32f61f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955292563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1955292563
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2281264420
Short name T365
Test name
Test status
Simulation time 422379331 ps
CPU time 1.11 seconds
Started Aug 15 04:31:12 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 183608 kb
Host smart-869f47aa-7dba-40bd-8993-efcc60e80190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281264420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2281264420
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1944385240
Short name T360
Test name
Test status
Simulation time 547982825 ps
CPU time 0.57 seconds
Started Aug 15 04:31:17 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 183612 kb
Host smart-82245a58-3572-47e5-9526-d9b6b6a3916e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944385240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1944385240
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2878636211
Short name T364
Test name
Test status
Simulation time 508983678 ps
CPU time 0.61 seconds
Started Aug 15 04:31:17 PM PDT 24
Finished Aug 15 04:31:17 PM PDT 24
Peak memory 183456 kb
Host smart-6170257e-09ef-4e84-802d-8284edc39e92
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878636211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2878636211
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1120639110
Short name T67
Test name
Test status
Simulation time 1103895985 ps
CPU time 3.63 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 193540 kb
Host smart-6014085b-fdbc-4521-8524-cdbff469e35d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120639110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1120639110
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1219799104
Short name T421
Test name
Test status
Simulation time 566125353 ps
CPU time 2.2 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:11 PM PDT 24
Peak memory 198432 kb
Host smart-da15b928-26e0-4deb-9352-252e01905269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219799104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1219799104
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1228650339
Short name T349
Test name
Test status
Simulation time 4610448405 ps
CPU time 1.99 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 197468 kb
Host smart-662b53d1-f19d-4e50-9026-a1d9990b8812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228650339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1228650339
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3846091488
Short name T297
Test name
Test status
Simulation time 460403949 ps
CPU time 0.74 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183604 kb
Host smart-fdb25c29-b80b-43ad-a9b2-895b866daace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846091488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3846091488
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2320560196
Short name T348
Test name
Test status
Simulation time 453435049 ps
CPU time 1.28 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 183620 kb
Host smart-35dd1b98-ab12-499c-ba16-09357db86f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320560196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2320560196
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.953079833
Short name T411
Test name
Test status
Simulation time 483869265 ps
CPU time 1.19 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 183612 kb
Host smart-24a57d15-278d-4911-9780-d4c707833631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953079833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.953079833
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.795493981
Short name T402
Test name
Test status
Simulation time 338381917 ps
CPU time 0.82 seconds
Started Aug 15 04:31:38 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 183600 kb
Host smart-93276189-866f-46ef-b007-bd93133c7eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795493981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.795493981
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1366750143
Short name T409
Test name
Test status
Simulation time 300078108 ps
CPU time 0.74 seconds
Started Aug 15 04:31:41 PM PDT 24
Finished Aug 15 04:31:42 PM PDT 24
Peak memory 183680 kb
Host smart-139af639-2eae-4705-85a6-e3723defbdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366750143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1366750143
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2120890159
Short name T420
Test name
Test status
Simulation time 334458029 ps
CPU time 0.66 seconds
Started Aug 15 04:31:37 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 183608 kb
Host smart-7d03db4e-3999-46be-b782-d4b171d6f8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120890159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2120890159
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1840052509
Short name T423
Test name
Test status
Simulation time 295137259 ps
CPU time 0.67 seconds
Started Aug 15 04:31:44 PM PDT 24
Finished Aug 15 04:31:45 PM PDT 24
Peak memory 183580 kb
Host smart-ec9570a5-2e3c-4cbb-b250-a729a8900140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840052509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1840052509
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2262342358
Short name T324
Test name
Test status
Simulation time 503290395 ps
CPU time 1.23 seconds
Started Aug 15 04:31:44 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 183572 kb
Host smart-2fca5fe8-4cd6-4516-9ba2-2f3438170f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262342358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2262342358
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3658501049
Short name T333
Test name
Test status
Simulation time 527671565 ps
CPU time 0.76 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 183636 kb
Host smart-010b17ba-2d83-4980-913a-eb08c93713d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658501049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3658501049
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3873517735
Short name T318
Test name
Test status
Simulation time 379015739 ps
CPU time 0.76 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 183600 kb
Host smart-c0f1b484-0e77-40d4-912c-dbe12b6eaf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873517735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3873517735
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.929060315
Short name T366
Test name
Test status
Simulation time 504882680 ps
CPU time 0.84 seconds
Started Aug 15 04:31:15 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 197608 kb
Host smart-c72bc7e3-93dc-473a-8c21-6f256f5f7720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929060315 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.929060315
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3838656109
Short name T65
Test name
Test status
Simulation time 551426258 ps
CPU time 0.83 seconds
Started Aug 15 04:31:16 PM PDT 24
Finished Aug 15 04:31:17 PM PDT 24
Peak memory 193264 kb
Host smart-5bde1120-6382-4c95-8bca-0e3e36300b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838656109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3838656109
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4142896030
Short name T351
Test name
Test status
Simulation time 419109896 ps
CPU time 0.86 seconds
Started Aug 15 04:31:19 PM PDT 24
Finished Aug 15 04:31:20 PM PDT 24
Peak memory 183608 kb
Host smart-3b9804ab-d770-4c02-b728-20d9146fca16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142896030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4142896030
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2336578738
Short name T350
Test name
Test status
Simulation time 2679897320 ps
CPU time 8.62 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 195112 kb
Host smart-21dff6c5-f3cc-498e-a975-bbb76fec6d27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336578738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2336578738
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3804648881
Short name T394
Test name
Test status
Simulation time 314656817 ps
CPU time 1.88 seconds
Started Aug 15 04:31:20 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 198504 kb
Host smart-d57ad45a-a6fa-4914-a513-7374a1102080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804648881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3804648881
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.12528319
Short name T378
Test name
Test status
Simulation time 365372915 ps
CPU time 1.04 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 196324 kb
Host smart-e5b176f2-7949-4343-93a3-1ef673b63d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528319 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.12528319
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3899365255
Short name T61
Test name
Test status
Simulation time 368735154 ps
CPU time 0.7 seconds
Started Aug 15 04:31:23 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 193168 kb
Host smart-fef029cd-2946-4cf4-be2b-87b3eb8d43da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899365255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3899365255
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2567642734
Short name T301
Test name
Test status
Simulation time 470301183 ps
CPU time 0.64 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 183616 kb
Host smart-311daf96-2899-4f12-a462-31e9010a20e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567642734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2567642734
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1338960168
Short name T356
Test name
Test status
Simulation time 1143044567 ps
CPU time 0.91 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 193908 kb
Host smart-7ee8c624-fe06-4408-8eb4-c167e9edadd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338960168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1338960168
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4097327582
Short name T303
Test name
Test status
Simulation time 993466839 ps
CPU time 2.06 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 198468 kb
Host smart-319faa29-7ded-41e2-acb7-07cdc9d90cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097327582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4097327582
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2860880782
Short name T42
Test name
Test status
Simulation time 7663768010 ps
CPU time 13.36 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:36 PM PDT 24
Peak memory 198164 kb
Host smart-5c77f000-1092-46a6-8e6e-48c333ad63ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860880782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2860880782
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3010385705
Short name T305
Test name
Test status
Simulation time 362547899 ps
CPU time 1.07 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 195328 kb
Host smart-5abc8e0f-38f6-41ae-9829-67dd5e754248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010385705 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3010385705
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1280827615
Short name T312
Test name
Test status
Simulation time 521040311 ps
CPU time 0.79 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:28 PM PDT 24
Peak memory 193244 kb
Host smart-3b7dca8a-3da1-4ab5-aa02-d3c004399264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280827615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1280827615
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3296533336
Short name T299
Test name
Test status
Simulation time 369804153 ps
CPU time 0.7 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:28 PM PDT 24
Peak memory 183580 kb
Host smart-acc94080-fa77-4d5b-aa9e-fe895716a5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296533336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3296533336
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1975770341
Short name T74
Test name
Test status
Simulation time 1671254415 ps
CPU time 4.7 seconds
Started Aug 15 04:31:26 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 194012 kb
Host smart-ac379a71-a7fd-443f-943c-f45bd1b86be5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975770341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1975770341
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1518900402
Short name T309
Test name
Test status
Simulation time 437205802 ps
CPU time 2 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 198516 kb
Host smart-1e07204e-a9df-4361-bf94-159ba174570a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518900402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1518900402
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.641863283
Short name T191
Test name
Test status
Simulation time 8131564532 ps
CPU time 8.98 seconds
Started Aug 15 04:31:26 PM PDT 24
Finished Aug 15 04:31:35 PM PDT 24
Peak memory 198052 kb
Host smart-5c3b17de-f82c-4fb7-8698-d35e6e13567e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641863283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.641863283
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2901802216
Short name T390
Test name
Test status
Simulation time 403149487 ps
CPU time 0.97 seconds
Started Aug 15 04:31:28 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 196344 kb
Host smart-ef8fe2ad-cd90-4f93-8462-6b76fac7613d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901802216 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2901802216
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2731279234
Short name T320
Test name
Test status
Simulation time 467446575 ps
CPU time 0.7 seconds
Started Aug 15 04:31:26 PM PDT 24
Finished Aug 15 04:31:27 PM PDT 24
Peak memory 192896 kb
Host smart-a62e805e-cf1d-4894-b0f7-81b093fcb20b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731279234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2731279234
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3543400627
Short name T292
Test name
Test status
Simulation time 381224896 ps
CPU time 0.75 seconds
Started Aug 15 04:31:32 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 183608 kb
Host smart-b896f5ca-a087-484e-b362-35ca0eb72f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543400627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3543400627
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1663710318
Short name T71
Test name
Test status
Simulation time 1277693342 ps
CPU time 0.94 seconds
Started Aug 15 04:31:23 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 193332 kb
Host smart-986303d7-d186-452c-bdbb-3105d070d00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663710318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1663710318
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2810114327
Short name T294
Test name
Test status
Simulation time 450153926 ps
CPU time 2.26 seconds
Started Aug 15 04:31:21 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 198388 kb
Host smart-ba257da1-0cdb-4938-94fb-81a33a663c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810114327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2810114327
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3924266247
Short name T407
Test name
Test status
Simulation time 4259352305 ps
CPU time 2.03 seconds
Started Aug 15 04:31:24 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 196444 kb
Host smart-ee02dc68-e9a0-4690-91c4-20b0454a2531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924266247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3924266247
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3415845650
Short name T302
Test name
Test status
Simulation time 333038943 ps
CPU time 1.16 seconds
Started Aug 15 04:31:25 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 197496 kb
Host smart-7c7049e7-164c-4e72-97f1-e3c54c352c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415845650 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3415845650
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3152551876
Short name T343
Test name
Test status
Simulation time 500709336 ps
CPU time 1.43 seconds
Started Aug 15 04:31:25 PM PDT 24
Finished Aug 15 04:31:27 PM PDT 24
Peak memory 191932 kb
Host smart-3e57477c-2ebc-4522-b657-67f231ae7e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152551876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3152551876
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.973047159
Short name T370
Test name
Test status
Simulation time 420908107 ps
CPU time 1.18 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 192816 kb
Host smart-f9076856-1602-4dc1-ad3c-e6387dd37670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973047159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.973047159
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3860611857
Short name T417
Test name
Test status
Simulation time 2352196395 ps
CPU time 1.33 seconds
Started Aug 15 04:31:22 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 191928 kb
Host smart-b24be7f7-80a0-4bd7-9512-4d5b9239d597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860611857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3860611857
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.172162444
Short name T345
Test name
Test status
Simulation time 380598409 ps
CPU time 2.06 seconds
Started Aug 15 04:31:23 PM PDT 24
Finished Aug 15 04:31:25 PM PDT 24
Peak memory 198496 kb
Host smart-4348032b-a106-4316-9b97-5a0df520b061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172162444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.172162444
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3291031858
Short name T414
Test name
Test status
Simulation time 4235467879 ps
CPU time 2.26 seconds
Started Aug 15 04:31:27 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 197600 kb
Host smart-aab4b7b8-0059-4d31-9d25-8f621c247820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291031858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3291031858
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2356964527
Short name T13
Test name
Test status
Simulation time 14370518878 ps
CPU time 5.35 seconds
Started Aug 15 04:23:03 PM PDT 24
Finished Aug 15 04:23:08 PM PDT 24
Peak memory 196692 kb
Host smart-f24dbbfd-52b0-4654-b939-aba86443904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356964527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2356964527
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4115602670
Short name T239
Test name
Test status
Simulation time 504356223 ps
CPU time 0.77 seconds
Started Aug 15 04:21:35 PM PDT 24
Finished Aug 15 04:21:36 PM PDT 24
Peak memory 195612 kb
Host smart-17022041-d102-4e0f-a0e0-5b01bf9bcdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115602670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4115602670
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2661160627
Short name T272
Test name
Test status
Simulation time 38866377250 ps
CPU time 31.19 seconds
Started Aug 15 04:19:05 PM PDT 24
Finished Aug 15 04:19:36 PM PDT 24
Peak memory 192340 kb
Host smart-b63d24f7-48c4-4df7-8e11-93618f72891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661160627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2661160627
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.892272196
Short name T18
Test name
Test status
Simulation time 8127117890 ps
CPU time 10.77 seconds
Started Aug 15 04:23:20 PM PDT 24
Finished Aug 15 04:23:31 PM PDT 24
Peak memory 215664 kb
Host smart-a7259ce0-e353-4d49-9a6d-5ec2d4d2af37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892272196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.892272196
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.726304297
Short name T202
Test name
Test status
Simulation time 491269532 ps
CPU time 0.73 seconds
Started Aug 15 04:23:12 PM PDT 24
Finished Aug 15 04:23:13 PM PDT 24
Peak memory 191896 kb
Host smart-8d695d3f-cbf6-439e-9738-38f539fb1d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726304297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.726304297
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2837670856
Short name T237
Test name
Test status
Simulation time 25118084176 ps
CPU time 9.18 seconds
Started Aug 15 04:22:28 PM PDT 24
Finished Aug 15 04:22:37 PM PDT 24
Peak memory 196964 kb
Host smart-29d632e3-61e8-4da2-bb69-3b183bf5efd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837670856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2837670856
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.191453687
Short name T241
Test name
Test status
Simulation time 566362254 ps
CPU time 1.39 seconds
Started Aug 15 04:22:26 PM PDT 24
Finished Aug 15 04:22:28 PM PDT 24
Peak memory 191992 kb
Host smart-34d58331-4426-437c-8685-ba5205528cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191453687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.191453687
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2692500979
Short name T219
Test name
Test status
Simulation time 40823578762 ps
CPU time 50.71 seconds
Started Aug 15 04:23:06 PM PDT 24
Finished Aug 15 04:23:57 PM PDT 24
Peak memory 190568 kb
Host smart-809d953f-3409-41b8-94b8-b1610d4a8ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692500979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2692500979
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2023288455
Short name T266
Test name
Test status
Simulation time 536400493 ps
CPU time 1.01 seconds
Started Aug 15 04:24:20 PM PDT 24
Finished Aug 15 04:24:22 PM PDT 24
Peak memory 191696 kb
Host smart-fe3e851e-7433-40c0-9e1f-a5d3f7da4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023288455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2023288455
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3545919098
Short name T213
Test name
Test status
Simulation time 10941828969 ps
CPU time 8.06 seconds
Started Aug 15 04:19:16 PM PDT 24
Finished Aug 15 04:19:25 PM PDT 24
Peak memory 197340 kb
Host smart-c183c02e-9c31-4d6e-a065-8e1c6a65feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545919098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3545919098
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1422144524
Short name T221
Test name
Test status
Simulation time 439081203 ps
CPU time 1.2 seconds
Started Aug 15 04:21:44 PM PDT 24
Finished Aug 15 04:21:45 PM PDT 24
Peak memory 191928 kb
Host smart-1061d428-4c61-4190-a632-4e92d31f81aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422144524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1422144524
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3554226739
Short name T226
Test name
Test status
Simulation time 25117653303 ps
CPU time 16.25 seconds
Started Aug 15 04:22:09 PM PDT 24
Finished Aug 15 04:22:26 PM PDT 24
Peak memory 191964 kb
Host smart-abe14411-6f5a-4197-9321-f0d7497ac345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554226739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3554226739
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2472595222
Short name T258
Test name
Test status
Simulation time 347159350 ps
CPU time 1.06 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:06 PM PDT 24
Peak memory 190824 kb
Host smart-ddf5636c-14a1-4a18-92ef-9b7c55546656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472595222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2472595222
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3880237287
Short name T1
Test name
Test status
Simulation time 6348789439 ps
CPU time 10.66 seconds
Started Aug 15 04:20:21 PM PDT 24
Finished Aug 15 04:20:32 PM PDT 24
Peak memory 192340 kb
Host smart-e4c53f9f-c690-442b-a465-5c576b833a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880237287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3880237287
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.356743145
Short name T248
Test name
Test status
Simulation time 480392177 ps
CPU time 0.87 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 196704 kb
Host smart-ba914c8b-7d1e-41ea-995a-5d8146e4253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356743145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.356743145
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2990549665
Short name T197
Test name
Test status
Simulation time 24564587330 ps
CPU time 10.66 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:23:06 PM PDT 24
Peak memory 190756 kb
Host smart-79c99d4a-2ff9-4668-a081-4462ffde1c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990549665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2990549665
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.869763054
Short name T203
Test name
Test status
Simulation time 417655152 ps
CPU time 1.14 seconds
Started Aug 15 04:22:56 PM PDT 24
Finished Aug 15 04:22:57 PM PDT 24
Peak memory 191588 kb
Host smart-33f866b3-9ec4-4c48-b1d6-e2eae6b2f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869763054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.869763054
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1213871644
Short name T282
Test name
Test status
Simulation time 20030270950 ps
CPU time 14.24 seconds
Started Aug 15 04:20:14 PM PDT 24
Finished Aug 15 04:20:28 PM PDT 24
Peak memory 191968 kb
Host smart-7a5672f8-4f56-474e-8791-c6b66751b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213871644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1213871644
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1953346415
Short name T246
Test name
Test status
Simulation time 576598161 ps
CPU time 0.72 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:20 PM PDT 24
Peak memory 191940 kb
Host smart-bc7b09fc-16f4-4ec7-a6a2-2b4b7369ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953346415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1953346415
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4131898373
Short name T275
Test name
Test status
Simulation time 32562920788 ps
CPU time 45.25 seconds
Started Aug 15 04:23:13 PM PDT 24
Finished Aug 15 04:23:58 PM PDT 24
Peak memory 192016 kb
Host smart-8c8c3752-f3ff-42b7-9cea-73133ce5c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131898373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4131898373
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1087004532
Short name T209
Test name
Test status
Simulation time 588010055 ps
CPU time 1.32 seconds
Started Aug 15 04:22:59 PM PDT 24
Finished Aug 15 04:23:00 PM PDT 24
Peak memory 191560 kb
Host smart-e8bda422-a75f-4b69-82a1-356940d11d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087004532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1087004532
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1873028657
Short name T183
Test name
Test status
Simulation time 392169584 ps
CPU time 1.17 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:32 PM PDT 24
Peak memory 196564 kb
Host smart-9b689012-dac3-4b88-b10b-87450da292bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873028657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1873028657
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3880164789
Short name T259
Test name
Test status
Simulation time 31312202226 ps
CPU time 48.1 seconds
Started Aug 15 04:24:12 PM PDT 24
Finished Aug 15 04:25:01 PM PDT 24
Peak memory 191764 kb
Host smart-4423f513-fe47-4f52-9c3c-271982c557e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880164789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3880164789
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2488904068
Short name T277
Test name
Test status
Simulation time 495167784 ps
CPU time 0.71 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:32 PM PDT 24
Peak memory 191908 kb
Host smart-9faee4b1-6366-4c19-89d7-c7d7fe4ffeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488904068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2488904068
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1953140189
Short name T212
Test name
Test status
Simulation time 3943377321 ps
CPU time 2.07 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:25 PM PDT 24
Peak memory 191668 kb
Host smart-2babdf96-647c-411f-a84a-c11dd69b8be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953140189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1953140189
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3605376532
Short name T217
Test name
Test status
Simulation time 433759015 ps
CPU time 1.2 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:33 PM PDT 24
Peak memory 196740 kb
Host smart-92b96f50-7991-40a1-8b81-f36d9fb8e2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605376532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3605376532
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3379549207
Short name T208
Test name
Test status
Simulation time 2909859160 ps
CPU time 4.39 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:23:00 PM PDT 24
Peak memory 196472 kb
Host smart-34955a75-cec4-46d2-aa38-c7d7f06bdc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379549207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3379549207
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4026083649
Short name T16
Test name
Test status
Simulation time 3962714506 ps
CPU time 1.66 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:23:23 PM PDT 24
Peak memory 215548 kb
Host smart-608254c4-bbb6-4501-bdcf-377a5f2a7fef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026083649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4026083649
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.539823236
Short name T6
Test name
Test status
Simulation time 494917760 ps
CPU time 1.24 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 196364 kb
Host smart-c9a1acca-a4b1-4c80-bc36-cede8233ea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539823236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.539823236
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1547255132
Short name T265
Test name
Test status
Simulation time 14862476706 ps
CPU time 6.04 seconds
Started Aug 15 04:24:21 PM PDT 24
Finished Aug 15 04:24:27 PM PDT 24
Peak memory 191776 kb
Host smart-70adac3d-446a-4f38-be26-8b543f990f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547255132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1547255132
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2914026391
Short name T31
Test name
Test status
Simulation time 372154149 ps
CPU time 1.12 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:23:35 PM PDT 24
Peak memory 191904 kb
Host smart-53dfb6bb-f9ed-44ae-ab65-14482e792ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914026391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2914026391
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1523903924
Short name T224
Test name
Test status
Simulation time 56830729277 ps
CPU time 84.39 seconds
Started Aug 15 04:20:52 PM PDT 24
Finished Aug 15 04:22:16 PM PDT 24
Peak memory 192340 kb
Host smart-9e2e9f83-9194-4aed-b62a-3b86aa05ecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523903924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1523903924
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1397011669
Short name T216
Test name
Test status
Simulation time 383487734 ps
CPU time 1.05 seconds
Started Aug 15 04:23:50 PM PDT 24
Finished Aug 15 04:23:51 PM PDT 24
Peak memory 191996 kb
Host smart-0a9bf18a-f210-4b7a-9e68-fcd45b240cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397011669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1397011669
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3321920775
Short name T2
Test name
Test status
Simulation time 1313962253 ps
CPU time 10.86 seconds
Started Aug 15 04:24:08 PM PDT 24
Finished Aug 15 04:24:19 PM PDT 24
Peak memory 206780 kb
Host smart-c8d5f21b-01e6-498a-9f23-f136983a82df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321920775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3321920775
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.4137783145
Short name T195
Test name
Test status
Simulation time 5917394175 ps
CPU time 4.43 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:21 PM PDT 24
Peak memory 191980 kb
Host smart-2e342478-5f87-4380-a92a-6c9ecb7fa170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137783145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4137783145
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3151798079
Short name T215
Test name
Test status
Simulation time 532626163 ps
CPU time 1.2 seconds
Started Aug 15 04:19:35 PM PDT 24
Finished Aug 15 04:19:36 PM PDT 24
Peak memory 191920 kb
Host smart-0a2c2efc-af13-4dfb-a712-ee74a9b480b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151798079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3151798079
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.85071
Short name T261
Test name
Test status
Simulation time 32951562555 ps
CPU time 48.78 seconds
Started Aug 15 04:23:12 PM PDT 24
Finished Aug 15 04:24:01 PM PDT 24
Peak memory 196792 kb
Host smart-1984d6aa-e8ba-40ca-8b67-e766a2b280a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.85071
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.763422729
Short name T269
Test name
Test status
Simulation time 564479384 ps
CPU time 0.77 seconds
Started Aug 15 04:24:22 PM PDT 24
Finished Aug 15 04:24:23 PM PDT 24
Peak memory 196752 kb
Host smart-f19bad8b-1e88-4eac-a8fa-c7d018bca3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763422729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.763422729
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2446933103
Short name T238
Test name
Test status
Simulation time 44918231868 ps
CPU time 65.48 seconds
Started Aug 15 04:18:38 PM PDT 24
Finished Aug 15 04:19:44 PM PDT 24
Peak memory 196260 kb
Host smart-ab7d8308-8e2a-4252-bd18-217f75e369ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446933103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2446933103
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1770088992
Short name T231
Test name
Test status
Simulation time 427026126 ps
CPU time 0.76 seconds
Started Aug 15 04:23:07 PM PDT 24
Finished Aug 15 04:23:09 PM PDT 24
Peak memory 195248 kb
Host smart-530311cd-311c-47eb-a960-67ffa686e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770088992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1770088992
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3921705401
Short name T285
Test name
Test status
Simulation time 12684066935 ps
CPU time 4.05 seconds
Started Aug 15 04:18:47 PM PDT 24
Finished Aug 15 04:18:51 PM PDT 24
Peak memory 191760 kb
Host smart-6ac28d99-e434-4988-b3b2-b362b9b9dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921705401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3921705401
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.770471504
Short name T236
Test name
Test status
Simulation time 526152120 ps
CPU time 0.96 seconds
Started Aug 15 04:25:00 PM PDT 24
Finished Aug 15 04:25:01 PM PDT 24
Peak memory 196464 kb
Host smart-a1a19e34-2dae-4f08-9ade-c052f78f8c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770471504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.770471504
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.60497028
Short name T256
Test name
Test status
Simulation time 19099043049 ps
CPU time 13.99 seconds
Started Aug 15 04:24:19 PM PDT 24
Finished Aug 15 04:24:33 PM PDT 24
Peak memory 196776 kb
Host smart-43ff03fd-a5cc-40d4-9658-64116a2d4cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60497028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.60497028
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1683200409
Short name T220
Test name
Test status
Simulation time 481400252 ps
CPU time 0.96 seconds
Started Aug 15 04:23:48 PM PDT 24
Finished Aug 15 04:23:49 PM PDT 24
Peak memory 196548 kb
Host smart-cae9876a-12b3-4231-b40a-ac6a1493d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683200409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1683200409
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3848406740
Short name T245
Test name
Test status
Simulation time 22795186766 ps
CPU time 33.91 seconds
Started Aug 15 04:21:18 PM PDT 24
Finished Aug 15 04:21:52 PM PDT 24
Peak memory 192020 kb
Host smart-66566b8c-7d6f-4c7d-8af0-55d681e0a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848406740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3848406740
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3389736141
Short name T7
Test name
Test status
Simulation time 585882453 ps
CPU time 0.97 seconds
Started Aug 15 04:18:44 PM PDT 24
Finished Aug 15 04:18:45 PM PDT 24
Peak memory 191920 kb
Host smart-43fdc237-e321-44a5-83f4-55ebd53f6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389736141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3389736141
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.4178805660
Short name T283
Test name
Test status
Simulation time 22490126020 ps
CPU time 6.91 seconds
Started Aug 15 04:18:44 PM PDT 24
Finished Aug 15 04:18:51 PM PDT 24
Peak memory 191976 kb
Host smart-fb8218d0-1ee6-4d3b-a36d-0927a0cf0895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178805660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4178805660
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1891943707
Short name T244
Test name
Test status
Simulation time 533412744 ps
CPU time 1.3 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:33 PM PDT 24
Peak memory 196752 kb
Host smart-c3e62a42-c48d-4d2e-826a-50a50fb47c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891943707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1891943707
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3114888553
Short name T273
Test name
Test status
Simulation time 21642988886 ps
CPU time 15.65 seconds
Started Aug 15 04:23:24 PM PDT 24
Finished Aug 15 04:23:40 PM PDT 24
Peak memory 191736 kb
Host smart-fb4fbe7d-2276-4687-9272-706d66f1a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114888553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3114888553
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1052349554
Short name T284
Test name
Test status
Simulation time 545789097 ps
CPU time 0.72 seconds
Started Aug 15 04:18:49 PM PDT 24
Finished Aug 15 04:18:50 PM PDT 24
Peak memory 191600 kb
Host smart-33575283-06bd-4783-b0f8-e10681b90fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052349554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1052349554
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1100630355
Short name T152
Test name
Test status
Simulation time 566984817 ps
CPU time 1.52 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:30 PM PDT 24
Peak memory 196760 kb
Host smart-ab08b1dd-b39c-44d3-aa65-219869aa7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100630355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1100630355
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1219147275
Short name T257
Test name
Test status
Simulation time 24509665520 ps
CPU time 29.25 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:23:51 PM PDT 24
Peak memory 191800 kb
Host smart-213316a8-d91d-434a-9297-5981e171788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219147275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1219147275
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4165611869
Short name T19
Test name
Test status
Simulation time 4446405936 ps
CPU time 6.46 seconds
Started Aug 15 04:23:28 PM PDT 24
Finished Aug 15 04:23:35 PM PDT 24
Peak memory 215888 kb
Host smart-f7f651e3-5b05-4ea7-a8ee-67776a14ab70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165611869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4165611869
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3361407877
Short name T205
Test name
Test status
Simulation time 385597969 ps
CPU time 1.07 seconds
Started Aug 15 04:23:21 PM PDT 24
Finished Aug 15 04:23:22 PM PDT 24
Peak memory 191896 kb
Host smart-6c5ac1e6-bd93-452f-89aa-a0f623fdcd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361407877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3361407877
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1332768928
Short name T267
Test name
Test status
Simulation time 23182585647 ps
CPU time 14.71 seconds
Started Aug 15 04:20:54 PM PDT 24
Finished Aug 15 04:21:09 PM PDT 24
Peak memory 206804 kb
Host smart-55cc46c2-e4b2-45d8-91b2-df7ab8eaac20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332768928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1332768928
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1055216923
Short name T204
Test name
Test status
Simulation time 49544142418 ps
CPU time 63.85 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:24:19 PM PDT 24
Peak memory 191256 kb
Host smart-79cff781-a2d9-4615-b3fe-9f48c057e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055216923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1055216923
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3486174445
Short name T264
Test name
Test status
Simulation time 530826745 ps
CPU time 1.55 seconds
Started Aug 15 04:18:51 PM PDT 24
Finished Aug 15 04:18:52 PM PDT 24
Peak memory 192280 kb
Host smart-c0874180-e257-4b29-afec-2647bbd9e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486174445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3486174445
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.325204895
Short name T126
Test name
Test status
Simulation time 449974343 ps
CPU time 1.15 seconds
Started Aug 15 04:23:13 PM PDT 24
Finished Aug 15 04:23:15 PM PDT 24
Peak memory 196780 kb
Host smart-61053626-c508-491e-9e8d-bfca08ff5d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325204895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.325204895
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1744820034
Short name T228
Test name
Test status
Simulation time 38014721940 ps
CPU time 60.82 seconds
Started Aug 15 04:23:13 PM PDT 24
Finished Aug 15 04:24:14 PM PDT 24
Peak memory 192016 kb
Host smart-8156e6dc-fe09-4326-bd04-b67e1193acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744820034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1744820034
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1240797532
Short name T254
Test name
Test status
Simulation time 609141412 ps
CPU time 0.8 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:24:18 PM PDT 24
Peak memory 196556 kb
Host smart-3db8cf0a-0fc5-4fe0-9c9a-b484039dbeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240797532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1240797532
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2678916007
Short name T12
Test name
Test status
Simulation time 45390233575 ps
CPU time 69.91 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:25:34 PM PDT 24
Peak memory 196968 kb
Host smart-a78ef2c5-5d72-49fc-a9fc-06e239831e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678916007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2678916007
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1553746725
Short name T218
Test name
Test status
Simulation time 446406933 ps
CPU time 0.95 seconds
Started Aug 15 04:20:19 PM PDT 24
Finished Aug 15 04:20:20 PM PDT 24
Peak memory 192280 kb
Host smart-fe9a79a9-6a22-4243-b826-b64cc388d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553746725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1553746725
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.362475088
Short name T149
Test name
Test status
Simulation time 618700106 ps
CPU time 1.08 seconds
Started Aug 15 04:20:22 PM PDT 24
Finished Aug 15 04:20:23 PM PDT 24
Peak memory 196776 kb
Host smart-c71d8a60-dbf1-4db5-ad5f-60b4bed6ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362475088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.362475088
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4187550803
Short name T249
Test name
Test status
Simulation time 14294961015 ps
CPU time 5.5 seconds
Started Aug 15 04:24:20 PM PDT 24
Finished Aug 15 04:24:26 PM PDT 24
Peak memory 196916 kb
Host smart-d3e99b44-d0b5-45f6-bf59-21b7ff408236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187550803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4187550803
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1349047581
Short name T225
Test name
Test status
Simulation time 531611094 ps
CPU time 1.33 seconds
Started Aug 15 04:23:50 PM PDT 24
Finished Aug 15 04:23:52 PM PDT 24
Peak memory 191868 kb
Host smart-d007e9fb-527f-456d-b5d8-c4c66053e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349047581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1349047581
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.182201734
Short name T242
Test name
Test status
Simulation time 39702365559 ps
CPU time 52.32 seconds
Started Aug 15 04:20:55 PM PDT 24
Finished Aug 15 04:21:47 PM PDT 24
Peak memory 191908 kb
Host smart-2f962e2e-f4c2-402b-a377-ac4ff67e7c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182201734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.182201734
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.229747635
Short name T223
Test name
Test status
Simulation time 570887459 ps
CPU time 0.7 seconds
Started Aug 15 04:20:48 PM PDT 24
Finished Aug 15 04:20:49 PM PDT 24
Peak memory 191096 kb
Host smart-86eecfdf-de0f-4806-986e-30ee0539e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229747635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.229747635
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2193768366
Short name T222
Test name
Test status
Simulation time 32704466993 ps
CPU time 42.5 seconds
Started Aug 15 04:21:10 PM PDT 24
Finished Aug 15 04:21:52 PM PDT 24
Peak memory 191968 kb
Host smart-326434f7-b18f-42f6-871c-e0ba5868324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193768366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2193768366
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.139728995
Short name T251
Test name
Test status
Simulation time 380337085 ps
CPU time 0.8 seconds
Started Aug 15 04:24:16 PM PDT 24
Finished Aug 15 04:24:17 PM PDT 24
Peak memory 196768 kb
Host smart-556b4f5a-a37c-410e-aa4b-c35a526855ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139728995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.139728995
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2547317863
Short name T189
Test name
Test status
Simulation time 478199587 ps
CPU time 0.91 seconds
Started Aug 15 04:23:11 PM PDT 24
Finished Aug 15 04:23:13 PM PDT 24
Peak memory 195964 kb
Host smart-ae8ef7d8-61a2-4033-bd50-e6eafe840ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547317863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2547317863
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2733124603
Short name T21
Test name
Test status
Simulation time 11119281342 ps
CPU time 14.88 seconds
Started Aug 15 04:20:49 PM PDT 24
Finished Aug 15 04:21:04 PM PDT 24
Peak memory 191752 kb
Host smart-00fcc99c-7b9d-4d5c-af42-3a7daaac4ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733124603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2733124603
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3236798669
Short name T243
Test name
Test status
Simulation time 504707203 ps
CPU time 1.3 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:19 PM PDT 24
Peak memory 191156 kb
Host smart-9cbdd949-cc96-4ffe-8811-217742030f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236798669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3236798669
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4152806784
Short name T166
Test name
Test status
Simulation time 584002311 ps
CPU time 1.39 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:23:36 PM PDT 24
Peak memory 196336 kb
Host smart-1b30de24-c8e4-45b9-9950-7f6f53116042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152806784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4152806784
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.626144032
Short name T281
Test name
Test status
Simulation time 1166332394 ps
CPU time 2.13 seconds
Started Aug 15 04:23:34 PM PDT 24
Finished Aug 15 04:23:36 PM PDT 24
Peak memory 195440 kb
Host smart-747debfa-4b40-437d-bd26-545f66c35f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626144032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.626144032
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.412987398
Short name T11
Test name
Test status
Simulation time 592242651 ps
CPU time 0.74 seconds
Started Aug 15 04:24:13 PM PDT 24
Finished Aug 15 04:24:14 PM PDT 24
Peak memory 191692 kb
Host smart-c08eda51-5174-41d5-96aa-66f8ce8c42fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412987398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.412987398
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2555842567
Short name T199
Test name
Test status
Simulation time 31028516850 ps
CPU time 7.31 seconds
Started Aug 15 04:23:55 PM PDT 24
Finished Aug 15 04:24:02 PM PDT 24
Peak memory 190916 kb
Host smart-a167d54c-a099-473e-9230-c2eae401328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555842567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2555842567
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2668057738
Short name T234
Test name
Test status
Simulation time 524071909 ps
CPU time 0.9 seconds
Started Aug 15 04:23:51 PM PDT 24
Finished Aug 15 04:23:52 PM PDT 24
Peak memory 196520 kb
Host smart-6fd77bc1-2818-42b3-aa4a-360034693a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668057738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2668057738
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.503519625
Short name T235
Test name
Test status
Simulation time 34885288454 ps
CPU time 12.61 seconds
Started Aug 15 04:21:18 PM PDT 24
Finished Aug 15 04:21:31 PM PDT 24
Peak memory 192064 kb
Host smart-385e0480-04d7-4ca8-acce-c7637cf789c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503519625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.503519625
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.140391472
Short name T250
Test name
Test status
Simulation time 349476018 ps
CPU time 0.82 seconds
Started Aug 15 04:23:56 PM PDT 24
Finished Aug 15 04:23:57 PM PDT 24
Peak memory 191736 kb
Host smart-68bdacb7-1fa1-47e9-a398-2b8e56d1d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140391472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.140391472
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2669035008
Short name T255
Test name
Test status
Simulation time 19131799649 ps
CPU time 3.8 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:28 PM PDT 24
Peak memory 196984 kb
Host smart-b26b3172-658e-4333-a3f1-04cc52d35e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669035008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2669035008
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.733199844
Short name T20
Test name
Test status
Simulation time 4095243344 ps
CPU time 7.31 seconds
Started Aug 15 04:22:01 PM PDT 24
Finished Aug 15 04:22:09 PM PDT 24
Peak memory 215672 kb
Host smart-4aeb617d-4e4d-4a93-8321-3ebdc073baf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733199844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.733199844
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2526500888
Short name T214
Test name
Test status
Simulation time 486535062 ps
CPU time 1.2 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:18 PM PDT 24
Peak memory 190664 kb
Host smart-afc738be-f1cc-4657-b963-d33a0e5fe35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526500888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2526500888
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2890944376
Short name T10
Test name
Test status
Simulation time 8295005601 ps
CPU time 3.65 seconds
Started Aug 15 04:24:17 PM PDT 24
Finished Aug 15 04:24:21 PM PDT 24
Peak memory 191300 kb
Host smart-d59ac4d5-2aa0-43fc-a0b9-9cd5fd51a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890944376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2890944376
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.261221685
Short name T247
Test name
Test status
Simulation time 418621168 ps
CPU time 1.17 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:08 PM PDT 24
Peak memory 191868 kb
Host smart-607f199b-42aa-40f4-9cd4-aeca2c60c725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261221685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.261221685
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1075074830
Short name T196
Test name
Test status
Simulation time 15046073168 ps
CPU time 6.7 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:13 PM PDT 24
Peak memory 191944 kb
Host smart-f29ed3a8-fd23-4cfc-831f-ddeebd4d688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075074830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1075074830
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2567953213
Short name T278
Test name
Test status
Simulation time 529624065 ps
CPU time 1.42 seconds
Started Aug 15 04:23:22 PM PDT 24
Finished Aug 15 04:23:24 PM PDT 24
Peak memory 192000 kb
Host smart-5f9a1e8b-82ab-4314-967e-8dee263021d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567953213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2567953213
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.17325114
Short name T22
Test name
Test status
Simulation time 12107287178 ps
CPU time 17.04 seconds
Started Aug 15 04:23:55 PM PDT 24
Finished Aug 15 04:24:12 PM PDT 24
Peak memory 191992 kb
Host smart-a3dfff99-ff33-4b50-bd45-b145588613b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17325114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.17325114
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2386073
Short name T233
Test name
Test status
Simulation time 532146983 ps
CPU time 0.84 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:07 PM PDT 24
Peak memory 191872 kb
Host smart-7190e7dd-62a5-4ad4-831b-7750a6a3185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2386073
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3632292653
Short name T227
Test name
Test status
Simulation time 20117096905 ps
CPU time 5.19 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:25 PM PDT 24
Peak memory 196992 kb
Host smart-efe61a49-6a59-410f-b405-0810b12355e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632292653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3632292653
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.719118691
Short name T30
Test name
Test status
Simulation time 348130786 ps
CPU time 1.02 seconds
Started Aug 15 04:19:54 PM PDT 24
Finished Aug 15 04:19:55 PM PDT 24
Peak memory 191920 kb
Host smart-a5a3dbe1-d4ea-4292-8b17-9e31bd702878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719118691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.719118691
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.533845620
Short name T180
Test name
Test status
Simulation time 520597796 ps
CPU time 0.92 seconds
Started Aug 15 04:23:05 PM PDT 24
Finished Aug 15 04:23:06 PM PDT 24
Peak memory 196400 kb
Host smart-a6171d35-3aae-4f1d-8414-6cb068c0c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533845620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.533845620
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.644486691
Short name T263
Test name
Test status
Simulation time 7719444586 ps
CPU time 12.74 seconds
Started Aug 15 04:20:38 PM PDT 24
Finished Aug 15 04:20:51 PM PDT 24
Peak memory 191964 kb
Host smart-cc1769be-216e-40ec-8616-1a9bfba6e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644486691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.644486691
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.514213593
Short name T271
Test name
Test status
Simulation time 501041227 ps
CPU time 0.77 seconds
Started Aug 15 04:22:54 PM PDT 24
Finished Aug 15 04:22:55 PM PDT 24
Peak memory 196716 kb
Host smart-3c27e44c-42e7-4272-93e1-6a3654835850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514213593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.514213593
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3742706344
Short name T181
Test name
Test status
Simulation time 411373540 ps
CPU time 1.15 seconds
Started Aug 15 04:23:09 PM PDT 24
Finished Aug 15 04:23:10 PM PDT 24
Peak memory 196752 kb
Host smart-61996d5d-1ee2-421d-875f-eb7db337c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742706344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3742706344
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3676944691
Short name T270
Test name
Test status
Simulation time 15442091281 ps
CPU time 23.05 seconds
Started Aug 15 04:23:31 PM PDT 24
Finished Aug 15 04:23:54 PM PDT 24
Peak memory 196976 kb
Host smart-747743d7-5a7f-41a8-971f-2020305a1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676944691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3676944691
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3372560436
Short name T268
Test name
Test status
Simulation time 408137509 ps
CPU time 1.2 seconds
Started Aug 15 04:22:55 PM PDT 24
Finished Aug 15 04:22:56 PM PDT 24
Peak memory 196168 kb
Host smart-d36fab68-6e6c-4e9c-8f29-5a7d7c48ee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372560436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3372560436
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3919293389
Short name T252
Test name
Test status
Simulation time 61369569778 ps
CPU time 89.4 seconds
Started Aug 15 04:20:23 PM PDT 24
Finished Aug 15 04:21:53 PM PDT 24
Peak memory 191964 kb
Host smart-d9fd34b3-551b-447b-a17b-3ac11835f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919293389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3919293389
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1643194279
Short name T240
Test name
Test status
Simulation time 606778970 ps
CPU time 0.66 seconds
Started Aug 15 04:20:36 PM PDT 24
Finished Aug 15 04:20:37 PM PDT 24
Peak memory 195632 kb
Host smart-0f1d37c1-6af8-47e1-a624-a41a6937ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643194279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1643194279
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.454083050
Short name T229
Test name
Test status
Simulation time 12599596292 ps
CPU time 2.89 seconds
Started Aug 15 04:20:25 PM PDT 24
Finished Aug 15 04:20:29 PM PDT 24
Peak memory 192020 kb
Host smart-e6a2ea57-8e83-4cd2-bad7-e5b11da59ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454083050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.454083050
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.685040965
Short name T232
Test name
Test status
Simulation time 393517401 ps
CPU time 0.67 seconds
Started Aug 15 04:23:46 PM PDT 24
Finished Aug 15 04:23:47 PM PDT 24
Peak memory 195640 kb
Host smart-d23c39f5-c7cc-49fa-b82c-a24afd82c0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685040965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.685040965
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1284488137
Short name T276
Test name
Test status
Simulation time 18514975056 ps
CPU time 14.91 seconds
Started Aug 15 04:24:26 PM PDT 24
Finished Aug 15 04:24:41 PM PDT 24
Peak memory 190360 kb
Host smart-81809f4c-c773-4ac6-bb83-af8f09f5d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284488137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1284488137
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3153787074
Short name T260
Test name
Test status
Simulation time 530101264 ps
CPU time 0.72 seconds
Started Aug 15 04:20:27 PM PDT 24
Finished Aug 15 04:20:28 PM PDT 24
Peak memory 191912 kb
Host smart-0995ac7e-7532-45b7-8cee-8550519dd027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153787074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3153787074
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1091339126
Short name T210
Test name
Test status
Simulation time 20534605345 ps
CPU time 8.67 seconds
Started Aug 15 04:23:00 PM PDT 24
Finished Aug 15 04:23:08 PM PDT 24
Peak memory 196920 kb
Host smart-81b9614b-e0bc-43fd-89e1-ed82e675e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091339126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1091339126
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.836917546
Short name T26
Test name
Test status
Simulation time 569750249 ps
CPU time 0.73 seconds
Started Aug 15 04:23:19 PM PDT 24
Finished Aug 15 04:23:20 PM PDT 24
Peak memory 190856 kb
Host smart-929365ba-93e4-4f66-8e1f-9bf6f0682bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836917546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.836917546
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1747522559
Short name T262
Test name
Test status
Simulation time 3312425074 ps
CPU time 2.67 seconds
Started Aug 15 04:24:24 PM PDT 24
Finished Aug 15 04:24:27 PM PDT 24
Peak memory 191676 kb
Host smart-d7353a34-4c32-4cb9-847c-9d043910fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747522559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1747522559
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1108965692
Short name T274
Test name
Test status
Simulation time 370388266 ps
CPU time 0.72 seconds
Started Aug 15 04:24:06 PM PDT 24
Finished Aug 15 04:24:07 PM PDT 24
Peak memory 191192 kb
Host smart-388024a4-8733-4493-9002-e1c0bd745210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108965692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1108965692
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1427629071
Short name T198
Test name
Test status
Simulation time 42785449630 ps
CPU time 59.21 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:24:32 PM PDT 24
Peak memory 191976 kb
Host smart-7c48bbe3-2f57-4273-9b7a-2c49d739abaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427629071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1427629071
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.540162012
Short name T206
Test name
Test status
Simulation time 457911886 ps
CPU time 0.63 seconds
Started Aug 15 04:24:04 PM PDT 24
Finished Aug 15 04:24:05 PM PDT 24
Peak memory 191884 kb
Host smart-22ae0a53-63cd-4b9b-a302-17e9670e8f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540162012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.540162012
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4022797808
Short name T253
Test name
Test status
Simulation time 8758035182 ps
CPU time 7.15 seconds
Started Aug 15 04:23:14 PM PDT 24
Finished Aug 15 04:23:22 PM PDT 24
Peak memory 196212 kb
Host smart-76295f91-a339-4cfe-9cc1-dab59991c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022797808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4022797808
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3771014387
Short name T211
Test name
Test status
Simulation time 420866446 ps
CPU time 1.21 seconds
Started Aug 15 04:23:32 PM PDT 24
Finished Aug 15 04:23:34 PM PDT 24
Peak memory 196464 kb
Host smart-85f36d97-6ca9-4860-86e4-6af62a55dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771014387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3771014387
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.916611642
Short name T49
Test name
Test status
Simulation time 33818492087 ps
CPU time 10.79 seconds
Started Aug 15 04:18:40 PM PDT 24
Finished Aug 15 04:18:51 PM PDT 24
Peak memory 192340 kb
Host smart-7fc21dc7-ca17-4ae2-8f86-62810268ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916611642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.916611642
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.420541379
Short name T279
Test name
Test status
Simulation time 460953927 ps
CPU time 1.21 seconds
Started Aug 15 04:23:15 PM PDT 24
Finished Aug 15 04:23:16 PM PDT 24
Peak memory 191524 kb
Host smart-4bc92bd5-715f-45e0-819b-9a3bac3b2767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420541379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.420541379
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1545568628
Short name T230
Test name
Test status
Simulation time 32085511490 ps
CPU time 10.31 seconds
Started Aug 15 04:19:37 PM PDT 24
Finished Aug 15 04:19:47 PM PDT 24
Peak memory 191992 kb
Host smart-c4a2f056-2700-4cd3-827e-463d1bca5501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545568628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1545568628
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2722742703
Short name T207
Test name
Test status
Simulation time 421310705 ps
CPU time 0.72 seconds
Started Aug 15 04:23:16 PM PDT 24
Finished Aug 15 04:23:17 PM PDT 24
Peak memory 191880 kb
Host smart-2bc28556-d7f7-49a6-b34f-a6ffd4db430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722742703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2722742703
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3464282121
Short name T280
Test name
Test status
Simulation time 3640663438 ps
CPU time 8.96 seconds
Started Aug 15 04:24:22 PM PDT 24
Finished Aug 15 04:24:31 PM PDT 24
Peak memory 206828 kb
Host smart-d5747db2-d540-4022-a395-7681f3807448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464282121 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3464282121
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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