Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	19981	1			T1	12		T2	247		T3	12
bark[1]	232	1			T30	30		T109	73		T88	14
bark[2]	539	1			T163	85		T151	45		T154	216
bark[3]	633	1			T4	35		T5	63		T10	182
bark[4]	266	1			T45	31		T109	91		T112	7
bark[5]	240	1			T2	35		T42	74		T86	14
bark[6]	618	1			T32	21		T89	21		T115	21
bark[7]	237	1			T126	5		T170	21		T78	44
bark[8]	314	1			T171	47		T93	21		T102	21
bark[9]	200	1			T31	55		T98	61		T112	14
bark[10]	416	1			T45	87		T109	21		T113	21
bark[11]	449	1			T121	5		T123	21		T126	43
bark[12]	260	1			T2	21		T29	21		T31	14
bark[13]	451	1			T121	52		T126	21		T156	127
bark[14]	358	1			T42	21		T44	7		T121	26
bark[15]	379	1			T5	30		T120	21		T123	21
bark[16]	136	1			T109	7		T102	31		T75	21
bark[17]	256	1			T33	14		T42	21		T43	21
bark[18]	371	1			T4	14		T12	7		T43	61
bark[19]	483	1			T4	21		T9	64		T187	14
bark[20]	173	1			T45	36		T82	21		T135	21
bark[21]	327	1			T27	14		T137	14		T190	14
bark[22]	154	1			T123	30		T82	21		T75	24
bark[23]	412	1			T28	14		T12	5		T31	47
bark[24]	222	1			T4	14		T47	14		T31	21
bark[25]	762	1			T11	14		T44	21		T121	31
bark[26]	293	1			T31	61		T75	21		T79	64
bark[27]	332	1			T29	5		T32	7		T42	21
bark[28]	355	1			T42	21		T120	21		T44	134
bark[29]	174	1			T10	5		T164	14		T32	26
bark[30]	368	1			T4	47		T30	21		T32	21
bark[31]	728	1			T2	21		T4	82		T5	21
bark_0	5104	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	19884	1			T1	11		T2	225		T3	11
bite[1]	416	1			T42	73		T86	13		T87	13
bite[2]	369	1			T29	21		T43	60		T89	21
bite[3]	253	1			T32	69		T45	35		T91	13
bite[4]	109	1			T82	21		T151	42		T99	6
bite[5]	348	1			T4	34		T187	13		T30	21
bite[6]	455	1			T2	21		T115	21		T194	13
bite[7]	549	1			T4	13		T5	63		T29	4
bite[8]	172	1			T33	13		T109	21		T138	30
bite[9]	339	1			T11	13		T30	30		T32	52
bite[10]	233	1			T2	21		T47	13		T42	21
bite[11]	495	1			T32	21		T42	6		T120	21
bite[12]	131	1			T43	4		T115	21		T130	34
bite[13]	539	1			T4	67		T31	13		T121	51
bite[14]	174	1			T10	4		T12	4		T182	13
bite[15]	460	1			T4	21		T32	21		T120	21
bite[16]	230	1			T4	54		T5	30		T31	47
bite[17]	392	1			T4	13		T12	6		T31	21
bite[18]	256	1			T2	35		T31	55		T75	23
bite[19]	627	1			T164	13		T44	139		T93	21
bite[20]	161	1			T126	21		T147	13		T82	21
bite[21]	289	1			T2	21		T190	13		T132	34
bite[22]	519	1			T126	4		T75	78		T77	193
bite[23]	167	1			T5	21		T42	21		T121	4
bite[24]	364	1			T31	40		T46	25		T89	21
bite[25]	660	1			T27	13		T32	27		T109	115
bite[26]	204	1			T120	21		T137	13		T125	13
bite[27]	390	1			T89	21		T115	42		T109	95
bite[28]	308	1			T31	21		T43	21		T123	30
bite[29]	217	1			T42	21		T121	21		T109	72
bite[30]	225	1			T177	13		T93	21		T117	21
bite[31]	606	1			T9	64		T42	21		T82	21
bite_0	5682	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31125

1

T1

19

T2

292

T3

19

auto[1]

5098

1

T2

39

T10

117

T200

7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	643	1			T2	9		T44	100		T45	2
prescale[1]	500	1			T4	33		T5	40		T173	41
prescale[2]	229	1			T201	9		T109	2		T202	2
prescale[3]	431	1			T10	2		T32	40		T120	36
prescale[4]	538	1			T30	19		T44	108		T89	19
prescale[5]	486	1			T2	85		T46	36		T89	42
prescale[6]	162	1			T4	2		T203	9		T30	30
prescale[7]	435	1			T3	9		T42	53		T204	9
prescale[8]	696	1			T4	2		T5	41		T8	9
prescale[9]	400	1			T5	28		T30	19		T42	119
prescale[10]	547	1			T50	9		T31	32		T32	9
prescale[11]	234	1			T93	2		T156	19		T110	57
prescale[12]	311	1			T4	82		T9	37		T32	27
prescale[13]	290	1			T12	2		T123	55		T102	64
prescale[14]	569	1			T2	19		T44	9		T89	93
prescale[15]	295	1			T2	28		T42	2		T120	19
prescale[16]	541	1			T29	19		T31	23		T43	134
prescale[17]	522	1			T4	2		T9	36		T29	57
prescale[18]	204	1			T32	2		T44	2		T45	4
prescale[19]	604	1			T4	2		T42	94		T120	94
prescale[20]	280	1			T10	2		T173	99		T46	9
prescale[21]	218	1			T12	2		T42	2		T205	9
prescale[22]	222	1			T206	9		T207	9		T89	2
prescale[23]	153	1			T31	29		T93	16		T113	23
prescale[24]	310	1			T49	9		T29	4		T42	21
prescale[25]	309	1			T5	19		T32	45		T202	2
prescale[26]	267	1			T44	60		T45	2		T121	2
prescale[27]	231	1			T12	2		T29	19		T31	19
prescale[28]	351	1			T4	2		T208	9		T32	2
prescale[29]	457	1			T2	19		T32	52		T43	9
prescale[30]	232	1			T1	9		T4	19		T42	19
prescale[31]	595	1			T41	9		T173	57		T43	23
prescale_0	23961	1			T1	10		T2	171		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23829

1

T1

9

T2

145

T3

9

auto[1]

12394

1

T1

10

T2

186

T3

10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

36223

1

T1

19

T2

331

T3

19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19959	1			T1	14		T2	228		T3	14
wkup[1]	280	1			T4	21		T11	15		T30	21
wkup[2]	136	1			T123	21		T161	21		T156	31
wkup[3]	142	1			T32	30		T89	21		T109	8
wkup[4]	130	1			T120	21		T126	21		T102	31
wkup[5]	116	1			T12	8		T91	15		T110	21
wkup[6]	221	1			T46	21		T121	21		T93	21
wkup[7]	150	1			T4	21		T42	21		T86	15
wkup[8]	179	1			T9	21		T30	26		T113	21
wkup[9]	186	1			T4	21		T30	30		T115	21
wkup[10]	215	1			T5	21		T10	21		T93	21
wkup[11]	144	1			T187	15		T42	21		T113	21
wkup[12]	243	1			T31	21		T43	21		T192	15
wkup[13]	167	1			T5	21		T9	26		T31	21
wkup[14]	241	1			T4	26		T173	21		T120	21
wkup[15]	227	1			T4	15		T42	21		T115	21
wkup[16]	197	1			T10	15		T32	26		T169	6
wkup[17]	250	1			T5	21		T29	27		T32	21
wkup[18]	197	1			T12	21		T30	21		T194	15
wkup[19]	207	1			T4	21		T27	15		T30	21
wkup[20]	128	1			T43	30		T45	26		T170	21
wkup[21]	165	1			T4	30		T89	21		T93	42
wkup[22]	277	1			T42	8		T123	26		T115	42
wkup[23]	163	1			T44	30		T89	21		T132	15
wkup[24]	150	1			T10	21		T31	21		T151	15
wkup[25]	194	1			T47	15		T44	42		T109	39
wkup[26]	108	1			T4	15		T43	21		T76	21
wkup[27]	168	1			T33	15		T30	48		T42	21
wkup[28]	246	1			T9	21		T10	21		T173	21
wkup[29]	106	1			T4	21		T32	8		T98	21
wkup[30]	123	1			T43	30		T169	21		T99	51
wkup[31]	245	1			T42	21		T163	21		T156	21
wkup[32]	113	1			T174	35		T158	15		T84	21
wkup[33]	342	1			T29	15		T43	21		T89	21
wkup[34]	203	1			T173	21		T89	21		T107	26
wkup[35]	131	1			T10	27		T42	21		T93	21
wkup[36]	207	1			T32	21		T44	30		T109	21
wkup[37]	205	1			T2	21		T89	21		T182	15
wkup[38]	180	1			T169	21		T102	15		T74	21
wkup[39]	232	1			T5	21		T9	21		T32	15
wkup[40]	156	1			T12	6		T43	26		T115	21
wkup[41]	134	1			T32	21		T121	21		T126	21
wkup[42]	187	1			T30	21		T32	21		T121	26
wkup[43]	130	1			T43	21		T170	21		T156	21
wkup[44]	237	1			T32	26		T42	21		T190	15
wkup[45]	194	1			T44	26		T184	15		T161	30
wkup[46]	137	1			T109	8		T171	21		T139	15
wkup[47]	129	1			T4	30		T28	15		T171	21
wkup[48]	150	1			T93	21		T132	21		T142	21
wkup[49]	194	1			T10	21		T43	15		T44	21
wkup[50]	270	1			T2	35		T89	42		T126	31
wkup[51]	191	1			T4	15		T123	21		T171	8
wkup[52]	242	1			T10	21		T43	21		T126	6
wkup[53]	167	1			T164	15		T109	26		T156	21
wkup[54]	209	1			T2	21		T5	30		T31	15
wkup[55]	203	1			T43	26		T45	15		T126	21
wkup[56]	276	1			T10	15		T29	21		T44	21
wkup[57]	294	1			T2	21		T30	15		T32	26
wkup[58]	236	1			T42	42		T44	21		T156	21
wkup[59]	281	1			T5	21		T31	21		T42	15
wkup[60]	177	1			T43	21		T123	21		T109	21
wkup[61]	278	1			T31	21		T42	21		T44	21
wkup[62]	360	1			T4	15		T10	21		T120	21
wkup[63]	124	1			T43	26		T44	21		T112	21
wkup_0	3994	1			T1	5		T2	5		T3	5