Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.96 99.33 95.61 100.00 98.40 99.51 46.94


Total test records in report: 426
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T159 /workspace/coverage/default/16.aon_timer_stress_all.517392835 Aug 16 04:34:57 PM PDT 24 Aug 16 04:36:16 PM PDT 24 295675925802 ps
T290 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.951257935 Aug 16 04:35:55 PM PDT 24 Aug 16 04:35:57 PM PDT 24 397360732 ps
T34 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2308794193 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:22 PM PDT 24 451630878 ps
T35 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4140243346 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:46 PM PDT 24 1653680420 ps
T291 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4040290570 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:40 PM PDT 24 504326132 ps
T36 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2892421836 Aug 16 04:35:42 PM PDT 24 Aug 16 04:35:44 PM PDT 24 1159720110 ps
T292 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.669152138 Aug 16 04:35:50 PM PDT 24 Aug 16 04:35:52 PM PDT 24 479890596 ps
T293 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2195289768 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:33 PM PDT 24 454410099 ps
T294 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3099392436 Aug 16 04:35:31 PM PDT 24 Aug 16 04:35:32 PM PDT 24 285494915 ps
T295 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.103520868 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:45 PM PDT 24 415111310 ps
T40 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4188770175 Aug 16 04:35:11 PM PDT 24 Aug 16 04:35:13 PM PDT 24 483984625 ps
T210 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2771322304 Aug 16 04:35:53 PM PDT 24 Aug 16 04:35:54 PM PDT 24 734416116 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.353058250 Aug 16 04:35:07 PM PDT 24 Aug 16 04:35:08 PM PDT 24 493481564 ps
T297 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2115683068 Aug 16 04:35:28 PM PDT 24 Aug 16 04:35:29 PM PDT 24 291619647 ps
T298 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2771045543 Aug 16 04:35:49 PM PDT 24 Aug 16 04:35:50 PM PDT 24 374258764 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3595552164 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:26 PM PDT 24 747452553 ps
T211 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.379471956 Aug 16 04:35:29 PM PDT 24 Aug 16 04:35:30 PM PDT 24 581710140 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1438225748 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:16 PM PDT 24 464232368 ps
T67 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3681759941 Aug 16 04:35:40 PM PDT 24 Aug 16 04:35:40 PM PDT 24 332853155 ps
T300 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2537381924 Aug 16 04:35:09 PM PDT 24 Aug 16 04:35:09 PM PDT 24 283102966 ps
T51 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3659949287 Aug 16 04:35:31 PM PDT 24 Aug 16 04:35:32 PM PDT 24 343472640 ps
T301 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.86330063 Aug 16 04:35:36 PM PDT 24 Aug 16 04:35:37 PM PDT 24 322701464 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2395262005 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:22 PM PDT 24 357877211 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.404835891 Aug 16 04:35:30 PM PDT 24 Aug 16 04:35:32 PM PDT 24 514581331 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4269061586 Aug 16 04:35:17 PM PDT 24 Aug 16 04:35:18 PM PDT 24 1033378634 ps
T209 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.582946919 Aug 16 04:35:20 PM PDT 24 Aug 16 04:35:21 PM PDT 24 371941841 ps
T37 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2205119080 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:48 PM PDT 24 8162797433 ps
T52 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1695751787 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:28 PM PDT 24 382385072 ps
T304 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1007124092 Aug 16 04:35:20 PM PDT 24 Aug 16 04:35:22 PM PDT 24 394974137 ps
T305 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.314083808 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 374787195 ps
T306 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2886020309 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:23 PM PDT 24 354301374 ps
T307 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3857244788 Aug 16 04:35:17 PM PDT 24 Aug 16 04:35:18 PM PDT 24 480278700 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.865321517 Aug 16 04:35:27 PM PDT 24 Aug 16 04:35:28 PM PDT 24 579649776 ps
T38 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.52692246 Aug 16 04:35:47 PM PDT 24 Aug 16 04:35:52 PM PDT 24 8666040159 ps
T54 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2007883919 Aug 16 04:35:31 PM PDT 24 Aug 16 04:35:32 PM PDT 24 512264344 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.385323876 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 368207544 ps
T308 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3288387154 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:47 PM PDT 24 598211241 ps
T309 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2656947021 Aug 16 04:35:11 PM PDT 24 Aug 16 04:35:13 PM PDT 24 769802650 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2558594528 Aug 16 04:35:48 PM PDT 24 Aug 16 04:35:49 PM PDT 24 314089394 ps
T311 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2916491606 Aug 16 04:35:14 PM PDT 24 Aug 16 04:35:15 PM PDT 24 545124627 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.177383293 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:23 PM PDT 24 493877740 ps
T39 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.366250482 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:23 PM PDT 24 4527904438 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1706846120 Aug 16 04:35:48 PM PDT 24 Aug 16 04:35:49 PM PDT 24 911281513 ps
T195 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1531688334 Aug 16 04:35:28 PM PDT 24 Aug 16 04:35:32 PM PDT 24 8109538322 ps
T313 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3907047586 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:28 PM PDT 24 4980420352 ps
T314 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2087906061 Aug 16 04:35:28 PM PDT 24 Aug 16 04:35:29 PM PDT 24 283634607 ps
T315 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.126790248 Aug 16 04:35:09 PM PDT 24 Aug 16 04:35:11 PM PDT 24 4544148234 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3755591190 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:24 PM PDT 24 361228322 ps
T56 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1607084861 Aug 16 04:35:14 PM PDT 24 Aug 16 04:35:15 PM PDT 24 514674103 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1926594035 Aug 16 04:35:08 PM PDT 24 Aug 16 04:35:09 PM PDT 24 349128299 ps
T318 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4169449652 Aug 16 04:35:34 PM PDT 24 Aug 16 04:35:35 PM PDT 24 580657632 ps
T196 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3440710737 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:40 PM PDT 24 4320069627 ps
T199 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2202316634 Aug 16 04:35:13 PM PDT 24 Aug 16 04:35:17 PM PDT 24 8758770131 ps
T319 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3238859554 Aug 16 04:35:18 PM PDT 24 Aug 16 04:35:19 PM PDT 24 490778996 ps
T197 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.814324925 Aug 16 04:35:05 PM PDT 24 Aug 16 04:35:08 PM PDT 24 9241762306 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.56807825 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:13 PM PDT 24 419235486 ps
T321 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.49769967 Aug 16 04:35:14 PM PDT 24 Aug 16 04:35:28 PM PDT 24 8412244419 ps
T70 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1387950039 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:25 PM PDT 24 1594897569 ps
T322 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2809842634 Aug 16 04:35:29 PM PDT 24 Aug 16 04:35:31 PM PDT 24 496090702 ps
T323 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2607885856 Aug 16 04:35:31 PM PDT 24 Aug 16 04:35:32 PM PDT 24 412172878 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.338824564 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:47 PM PDT 24 4768427827 ps
T325 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.721736597 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:14 PM PDT 24 550472318 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.652492112 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:25 PM PDT 24 485655929 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.280790534 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 446325821 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3362798203 Aug 16 04:35:11 PM PDT 24 Aug 16 04:35:13 PM PDT 24 3168223924 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1829918620 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:40 PM PDT 24 286927225 ps
T198 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3200626904 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:33 PM PDT 24 7954824182 ps
T329 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1072442785 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:23 PM PDT 24 360207200 ps
T57 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.64764640 Aug 16 04:35:57 PM PDT 24 Aug 16 04:35:57 PM PDT 24 397200469 ps
T330 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2923060427 Aug 16 04:35:37 PM PDT 24 Aug 16 04:35:38 PM PDT 24 312677743 ps
T72 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1115890808 Aug 16 04:35:33 PM PDT 24 Aug 16 04:35:34 PM PDT 24 2505347635 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.940240266 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:23 PM PDT 24 385571919 ps
T331 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4229634420 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:23 PM PDT 24 477094242 ps
T332 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1734509019 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:15 PM PDT 24 2408517497 ps
T333 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4166185987 Aug 16 04:35:43 PM PDT 24 Aug 16 04:35:45 PM PDT 24 404843114 ps
T334 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2056200630 Aug 16 04:35:45 PM PDT 24 Aug 16 04:35:46 PM PDT 24 379698381 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2020467314 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:39 PM PDT 24 431038923 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3188519507 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:22 PM PDT 24 605731087 ps
T337 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3540314426 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:18 PM PDT 24 1134095978 ps
T338 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1437805293 Aug 16 04:35:34 PM PDT 24 Aug 16 04:35:36 PM PDT 24 511413811 ps
T339 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3566133823 Aug 16 04:35:27 PM PDT 24 Aug 16 04:35:29 PM PDT 24 563162976 ps
T340 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3170639834 Aug 16 04:35:47 PM PDT 24 Aug 16 04:35:48 PM PDT 24 437853625 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.511092757 Aug 16 04:35:35 PM PDT 24 Aug 16 04:35:40 PM PDT 24 2621786072 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.959167892 Aug 16 04:35:35 PM PDT 24 Aug 16 04:35:39 PM PDT 24 2031395165 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2033255490 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 273723243 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1597810892 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:27 PM PDT 24 363420655 ps
T345 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.939933349 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 572580193 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3101446789 Aug 16 04:35:56 PM PDT 24 Aug 16 04:35:57 PM PDT 24 372277534 ps
T347 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3352505685 Aug 16 04:35:19 PM PDT 24 Aug 16 04:35:20 PM PDT 24 403178995 ps
T348 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4113866083 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:24 PM PDT 24 1256498120 ps
T349 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4018572878 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:41 PM PDT 24 8080475005 ps
T350 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1782798599 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:16 PM PDT 24 514039829 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3074200317 Aug 16 04:35:08 PM PDT 24 Aug 16 04:35:12 PM PDT 24 8121455494 ps
T352 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4292732996 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:40 PM PDT 24 528706008 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1118933096 Aug 16 04:35:31 PM PDT 24 Aug 16 04:35:33 PM PDT 24 428209011 ps
T354 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2015733321 Aug 16 04:35:41 PM PDT 24 Aug 16 04:35:42 PM PDT 24 420448325 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.808330031 Aug 16 04:35:50 PM PDT 24 Aug 16 04:35:52 PM PDT 24 2172837638 ps
T356 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1613346595 Aug 16 04:35:30 PM PDT 24 Aug 16 04:35:38 PM PDT 24 2974218899 ps
T357 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2618961032 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:38 PM PDT 24 435865616 ps
T358 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1748063143 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:39 PM PDT 24 503392373 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1210052850 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:24 PM PDT 24 638098870 ps
T360 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2578463189 Aug 16 04:35:18 PM PDT 24 Aug 16 04:35:32 PM PDT 24 8122910557 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4269989810 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:45 PM PDT 24 744574892 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3631701600 Aug 16 04:35:25 PM PDT 24 Aug 16 04:35:28 PM PDT 24 454352698 ps
T363 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1357162499 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:40 PM PDT 24 412923349 ps
T364 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2803139805 Aug 16 04:35:34 PM PDT 24 Aug 16 04:35:35 PM PDT 24 609014473 ps
T365 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.174985928 Aug 16 04:35:53 PM PDT 24 Aug 16 04:35:55 PM PDT 24 2814485088 ps
T366 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.752981773 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:39 PM PDT 24 290270400 ps
T367 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2346119804 Aug 16 04:35:40 PM PDT 24 Aug 16 04:35:42 PM PDT 24 498439871 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1557467669 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:13 PM PDT 24 807533220 ps
T368 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1936688623 Aug 16 04:35:34 PM PDT 24 Aug 16 04:35:35 PM PDT 24 514168312 ps
T369 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.280119080 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:24 PM PDT 24 2068613316 ps
T370 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3920883613 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:40 PM PDT 24 448232586 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1380040909 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:40 PM PDT 24 299630674 ps
T372 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.511479616 Aug 16 04:35:42 PM PDT 24 Aug 16 04:35:43 PM PDT 24 401922934 ps
T373 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2437585230 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:24 PM PDT 24 435989853 ps
T374 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3409539306 Aug 16 04:35:42 PM PDT 24 Aug 16 04:35:50 PM PDT 24 4141317877 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1699495510 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:17 PM PDT 24 432365606 ps
T375 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.608862971 Aug 16 04:35:56 PM PDT 24 Aug 16 04:35:58 PM PDT 24 456355737 ps
T376 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1205071377 Aug 16 04:35:43 PM PDT 24 Aug 16 04:35:44 PM PDT 24 429605533 ps
T377 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1951351779 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:23 PM PDT 24 481296476 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2197143766 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:36 PM PDT 24 7164584103 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4261806769 Aug 16 04:35:39 PM PDT 24 Aug 16 04:35:41 PM PDT 24 419902982 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.950503316 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:16 PM PDT 24 465343680 ps
T381 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3482022569 Aug 16 04:35:48 PM PDT 24 Aug 16 04:35:50 PM PDT 24 433718208 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2917082778 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:15 PM PDT 24 3824739635 ps
T383 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.801935975 Aug 16 04:35:27 PM PDT 24 Aug 16 04:35:28 PM PDT 24 494914347 ps
T384 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3593583799 Aug 16 04:35:44 PM PDT 24 Aug 16 04:35:45 PM PDT 24 502650238 ps
T385 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.531654849 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:25 PM PDT 24 544146810 ps
T386 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4046409481 Aug 16 04:35:12 PM PDT 24 Aug 16 04:35:13 PM PDT 24 493258085 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3273823587 Aug 16 04:35:32 PM PDT 24 Aug 16 04:35:33 PM PDT 24 348266454 ps
T388 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2082089254 Aug 16 04:35:40 PM PDT 24 Aug 16 04:35:41 PM PDT 24 492402689 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.935269694 Aug 16 04:35:35 PM PDT 24 Aug 16 04:35:43 PM PDT 24 2236042130 ps
T390 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2476548121 Aug 16 04:35:46 PM PDT 24 Aug 16 04:35:47 PM PDT 24 287956903 ps
T66 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3818967834 Aug 16 04:35:37 PM PDT 24 Aug 16 04:35:38 PM PDT 24 473565179 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3399057282 Aug 16 04:35:56 PM PDT 24 Aug 16 04:35:58 PM PDT 24 617908062 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.40024965 Aug 16 04:35:14 PM PDT 24 Aug 16 04:35:18 PM PDT 24 4386781172 ps
T393 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2338482061 Aug 16 04:35:30 PM PDT 24 Aug 16 04:35:31 PM PDT 24 500883688 ps
T394 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2460727532 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:23 PM PDT 24 506096577 ps
T395 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.254700438 Aug 16 04:35:36 PM PDT 24 Aug 16 04:35:37 PM PDT 24 482487706 ps
T396 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.494034215 Aug 16 04:35:47 PM PDT 24 Aug 16 04:35:48 PM PDT 24 355087751 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3314843743 Aug 16 04:35:34 PM PDT 24 Aug 16 04:35:37 PM PDT 24 7689198650 ps
T398 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1414276071 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:20 PM PDT 24 2097252124 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1524083510 Aug 16 04:35:08 PM PDT 24 Aug 16 04:35:09 PM PDT 24 401501192 ps
T400 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1365721057 Aug 16 04:35:46 PM PDT 24 Aug 16 04:35:47 PM PDT 24 520848346 ps
T401 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1741239936 Aug 16 04:35:21 PM PDT 24 Aug 16 04:35:24 PM PDT 24 2231288733 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2134528671 Aug 16 04:35:43 PM PDT 24 Aug 16 04:35:45 PM PDT 24 493294045 ps
T402 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.912981147 Aug 16 04:35:38 PM PDT 24 Aug 16 04:35:41 PM PDT 24 845767524 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1772686730 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:26 PM PDT 24 1245549159 ps
T404 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2308752396 Aug 16 04:35:46 PM PDT 24 Aug 16 04:35:47 PM PDT 24 323302401 ps
T405 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.365510127 Aug 16 04:35:42 PM PDT 24 Aug 16 04:35:43 PM PDT 24 387521725 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2279445908 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:31 PM PDT 24 3652396377 ps
T406 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1391335830 Aug 16 04:35:29 PM PDT 24 Aug 16 04:35:30 PM PDT 24 457805499 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.918879073 Aug 16 04:35:29 PM PDT 24 Aug 16 04:35:30 PM PDT 24 314489028 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3502092381 Aug 16 04:35:20 PM PDT 24 Aug 16 04:35:21 PM PDT 24 322258348 ps
T409 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.712843060 Aug 16 04:35:20 PM PDT 24 Aug 16 04:35:21 PM PDT 24 431031210 ps
T62 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2773952849 Aug 16 04:35:35 PM PDT 24 Aug 16 04:35:36 PM PDT 24 436295498 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2875497713 Aug 16 04:35:22 PM PDT 24 Aug 16 04:35:23 PM PDT 24 461564205 ps
T411 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.232782449 Aug 16 04:35:35 PM PDT 24 Aug 16 04:35:37 PM PDT 24 286319393 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1358533927 Aug 16 04:35:46 PM PDT 24 Aug 16 04:35:47 PM PDT 24 350947765 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3266720724 Aug 16 04:35:48 PM PDT 24 Aug 16 04:35:53 PM PDT 24 7513667605 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2323439123 Aug 16 04:35:33 PM PDT 24 Aug 16 04:35:53 PM PDT 24 7080021652 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3007381832 Aug 16 04:35:17 PM PDT 24 Aug 16 04:35:18 PM PDT 24 1075467472 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1549639300 Aug 16 04:35:13 PM PDT 24 Aug 16 04:35:14 PM PDT 24 400534615 ps
T416 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3637687624 Aug 16 04:35:10 PM PDT 24 Aug 16 04:35:12 PM PDT 24 1246867932 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1781304757 Aug 16 04:35:10 PM PDT 24 Aug 16 04:35:11 PM PDT 24 478133884 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.819300797 Aug 16 04:35:13 PM PDT 24 Aug 16 04:35:14 PM PDT 24 458895566 ps
T419 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3303869402 Aug 16 04:35:32 PM PDT 24 Aug 16 04:35:33 PM PDT 24 397087821 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2243723533 Aug 16 04:35:17 PM PDT 24 Aug 16 04:35:18 PM PDT 24 335076280 ps
T420 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.57055038 Aug 16 04:35:24 PM PDT 24 Aug 16 04:35:28 PM PDT 24 8361790312 ps
T421 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2564274505 Aug 16 04:35:15 PM PDT 24 Aug 16 04:35:17 PM PDT 24 310412881 ps
T422 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1672529104 Aug 16 04:35:33 PM PDT 24 Aug 16 04:35:38 PM PDT 24 8581760868 ps
T423 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2810248702 Aug 16 04:35:16 PM PDT 24 Aug 16 04:35:17 PM PDT 24 496851819 ps
T424 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4045344375 Aug 16 04:35:26 PM PDT 24 Aug 16 04:35:27 PM PDT 24 388891617 ps
T425 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.789296757 Aug 16 04:35:40 PM PDT 24 Aug 16 04:35:42 PM PDT 24 2343460755 ps
T426 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4066717233 Aug 16 04:35:43 PM PDT 24 Aug 16 04:35:44 PM PDT 24 339439334 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2747242740
Short name T10
Test name
Test status
Simulation time 6524930560 ps
CPU time 16.65 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 198696 kb
Host smart-098c0f12-8c68-41ec-afbd-be8f6b7310ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747242740 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2747242740
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.568702640
Short name T2
Test name
Test status
Simulation time 61946599094 ps
CPU time 27.65 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:34 PM PDT 24
Peak memory 197348 kb
Host smart-f061701e-ce89-4084-a476-87c408c87576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568702640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.568702640
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1819463627
Short name T4
Test name
Test status
Simulation time 54958523370 ps
CPU time 26.53 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 206824 kb
Host smart-32b07523-1599-465e-8c61-40b7bfdc2b4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819463627 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1819463627
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.759564350
Short name T13
Test name
Test status
Simulation time 4161732645 ps
CPU time 7.29 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 216012 kb
Host smart-39676238-eba0-4a4f-ac7b-d9a715b90051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759564350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.759564350
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3659949287
Short name T51
Test name
Test status
Simulation time 343472640 ps
CPU time 1.13 seconds
Started Aug 16 04:35:31 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 193112 kb
Host smart-05f5e437-edf4-4237-86c9-16a5174b6195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659949287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3659949287
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.4104189073
Short name T107
Test name
Test status
Simulation time 5037516344 ps
CPU time 31.63 seconds
Started Aug 16 04:34:47 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 214116 kb
Host smart-61018fb0-0fb7-44f9-b8c0-92f0a0df9b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104189073 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.4104189073
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2623893882
Short name T32
Test name
Test status
Simulation time 4775475055 ps
CPU time 23.52 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 206940 kb
Host smart-6cd2de87-e848-4857-84e4-1c684f9f37e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623893882 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2623893882
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3023641784
Short name T92
Test name
Test status
Simulation time 5702104330 ps
CPU time 43.72 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:54 PM PDT 24
Peak memory 214192 kb
Host smart-784077b3-3497-49e3-98b2-7a849bf080fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023641784 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3023641784
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3583750374
Short name T42
Test name
Test status
Simulation time 11392193479 ps
CPU time 51.84 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:36:05 PM PDT 24
Peak memory 214464 kb
Host smart-fe83b298-6efc-4340-b2d3-24e6d7f19111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583750374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3583750374
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1344619306
Short name T43
Test name
Test status
Simulation time 5689103657 ps
CPU time 21.3 seconds
Started Aug 16 04:34:43 PM PDT 24
Finished Aug 16 04:35:05 PM PDT 24
Peak memory 198720 kb
Host smart-0fa94d60-d1ce-406d-9b67-c9d79183691c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344619306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1344619306
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1392627350
Short name T100
Test name
Test status
Simulation time 63439828141 ps
CPU time 21.36 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 198368 kb
Host smart-9687104c-6a94-4b37-8f99-4dd8cb3cf925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392627350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1392627350
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3703720945
Short name T109
Test name
Test status
Simulation time 15517958934 ps
CPU time 31.57 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 214972 kb
Host smart-1707a4dd-59ed-400e-bd5d-4c9ca9512ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703720945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3703720945
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3362842497
Short name T93
Test name
Test status
Simulation time 7726184089 ps
CPU time 15.07 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 206896 kb
Host smart-3c8bd834-0880-46ec-890d-0fe8f9e2fd72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362842497 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3362842497
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3127877484
Short name T96
Test name
Test status
Simulation time 442291424739 ps
CPU time 679.01 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:46:27 PM PDT 24
Peak memory 192688 kb
Host smart-eb92fc4f-a9d2-4223-8e23-7ce9beffd3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127877484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3127877484
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.39430648
Short name T84
Test name
Test status
Simulation time 37841494928 ps
CPU time 41.89 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:48 PM PDT 24
Peak memory 214140 kb
Host smart-f7c38a26-083d-4ff8-b812-77c5b38f2813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39430648 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.39430648
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2205119080
Short name T37
Test name
Test status
Simulation time 8162797433 ps
CPU time 4.38 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:48 PM PDT 24
Peak memory 198248 kb
Host smart-955ce500-85bf-4562-9c2f-670ac959ac93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205119080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2205119080
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2243723533
Short name T63
Test name
Test status
Simulation time 335076280 ps
CPU time 0.79 seconds
Started Aug 16 04:35:17 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 183736 kb
Host smart-d8353124-d8a6-4083-b0a4-e5219e4c3d0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243723533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2243723533
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1025696435
Short name T156
Test name
Test status
Simulation time 25550847202 ps
CPU time 66.07 seconds
Started Aug 16 04:34:58 PM PDT 24
Finished Aug 16 04:36:04 PM PDT 24
Peak memory 206992 kb
Host smart-bab0d728-ae4b-40be-9131-02556ab648dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025696435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1025696435
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2250635696
Short name T80
Test name
Test status
Simulation time 79170405394 ps
CPU time 14.75 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 198404 kb
Host smart-a106b383-0414-42eb-9aa4-a70cf1b83920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250635696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2250635696
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1524178579
Short name T89
Test name
Test status
Simulation time 16037811319 ps
CPU time 34.3 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 199080 kb
Host smart-bdbf3665-2ef6-459c-9b75-b0c5fd115af7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524178579 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1524178579
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3644642495
Short name T79
Test name
Test status
Simulation time 8344373002 ps
CPU time 32.91 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:42 PM PDT 24
Peak memory 206896 kb
Host smart-8dedc005-8d9a-4919-be3a-aa3fc43135e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644642495 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3644642495
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.207080742
Short name T110
Test name
Test status
Simulation time 242838333755 ps
CPU time 124.29 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:37:07 PM PDT 24
Peak memory 198444 kb
Host smart-2b316750-465c-464f-82f8-f12d0e1a16e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207080742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.207080742
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4176466829
Short name T31
Test name
Test status
Simulation time 84957470254 ps
CPU time 60.04 seconds
Started Aug 16 04:34:55 PM PDT 24
Finished Aug 16 04:35:55 PM PDT 24
Peak memory 198380 kb
Host smart-24723a4a-aedc-40d7-91fc-f01061ca6241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176466829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4176466829
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2313824751
Short name T30
Test name
Test status
Simulation time 37738187659 ps
CPU time 61.78 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:36:13 PM PDT 24
Peak memory 184816 kb
Host smart-786c3075-70cc-407c-85ae-38817867e8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313824751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2313824751
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2743910180
Short name T102
Test name
Test status
Simulation time 222080082355 ps
CPU time 67.93 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:36:19 PM PDT 24
Peak memory 193176 kb
Host smart-0297c4d7-ec2d-4f88-8b30-58c40b393d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743910180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2743910180
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.322293226
Short name T134
Test name
Test status
Simulation time 3674145725 ps
CPU time 30.73 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 214700 kb
Host smart-b6081433-2068-49cb-9182-ef1c94fa37ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322293226 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.322293226
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2910958046
Short name T75
Test name
Test status
Simulation time 4047835284 ps
CPU time 23.5 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:34 PM PDT 24
Peak memory 214588 kb
Host smart-b4a25c3f-f043-475b-aa29-effb0f1e73dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910958046 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2910958046
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.910234026
Short name T121
Test name
Test status
Simulation time 3260485118 ps
CPU time 29.87 seconds
Started Aug 16 04:34:58 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 198612 kb
Host smart-5b13bd5d-6316-498f-ad97-adf527e400da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910234026 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.910234026
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4004199398
Short name T82
Test name
Test status
Simulation time 93077699039 ps
CPU time 13.64 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 198508 kb
Host smart-25377b25-ff71-4145-8aa9-97d1dc2bb519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004199398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4004199398
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3797939455
Short name T104
Test name
Test status
Simulation time 94977264399 ps
CPU time 142.69 seconds
Started Aug 16 04:34:49 PM PDT 24
Finished Aug 16 04:37:12 PM PDT 24
Peak memory 192652 kb
Host smart-3c1908f4-986e-454a-9237-4df011d4ea5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797939455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3797939455
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.609939664
Short name T123
Test name
Test status
Simulation time 171655517551 ps
CPU time 183.22 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:38:10 PM PDT 24
Peak memory 193164 kb
Host smart-8ba715cd-5a24-495d-8fc4-6b72d2423d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609939664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.609939664
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2025393176
Short name T127
Test name
Test status
Simulation time 2737881880 ps
CPU time 16.67 seconds
Started Aug 16 04:34:35 PM PDT 24
Finished Aug 16 04:34:52 PM PDT 24
Peak memory 198740 kb
Host smart-17c72147-4a72-476a-8405-aa47966c2930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025393176 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2025393176
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2907438166
Short name T115
Test name
Test status
Simulation time 76324186294 ps
CPU time 68.27 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:36:01 PM PDT 24
Peak memory 198520 kb
Host smart-c4712746-29de-4116-981a-08feac38a025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907438166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2907438166
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.372060334
Short name T128
Test name
Test status
Simulation time 6473327178 ps
CPU time 37.54 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:43 PM PDT 24
Peak memory 198704 kb
Host smart-5f2d1742-0f55-4c39-9900-3b091f91e350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372060334 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.372060334
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1422658241
Short name T135
Test name
Test status
Simulation time 49303907356 ps
CPU time 20.58 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 193168 kb
Host smart-6561268c-91cd-42dd-a647-2e25259bb6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422658241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1422658241
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1138385366
Short name T5
Test name
Test status
Simulation time 41408626424 ps
CPU time 51.36 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:59 PM PDT 24
Peak memory 193156 kb
Host smart-b29fbd79-e4e4-4e27-8fe2-963ae3d3bbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138385366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1138385366
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3731455706
Short name T174
Test name
Test status
Simulation time 29508562233 ps
CPU time 36.69 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:50 PM PDT 24
Peak memory 198408 kb
Host smart-3c670347-7f90-40d3-96cc-86019cfe0cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731455706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3731455706
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.588979567
Short name T85
Test name
Test status
Simulation time 79111571165 ps
CPU time 31.03 seconds
Started Aug 16 04:34:44 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 198392 kb
Host smart-3db7ed30-6a4f-4be9-bdb9-f4b0732e74e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588979567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.588979567
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3155718630
Short name T77
Test name
Test status
Simulation time 14094288462 ps
CPU time 16.72 seconds
Started Aug 16 04:34:47 PM PDT 24
Finished Aug 16 04:35:04 PM PDT 24
Peak memory 198740 kb
Host smart-cca169a6-62e0-4d92-85c0-348a0751e6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155718630 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3155718630
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1457148678
Short name T171
Test name
Test status
Simulation time 2887434160 ps
CPU time 24.98 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:34 PM PDT 24
Peak memory 198764 kb
Host smart-6805c026-9d88-4afc-a661-853e6aecfdec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457148678 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1457148678
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.290132792
Short name T130
Test name
Test status
Simulation time 171551745606 ps
CPU time 33.94 seconds
Started Aug 16 04:35:19 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 198412 kb
Host smart-75447dd9-0f6e-43be-9e73-e15546529029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290132792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.290132792
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2854686420
Short name T142
Test name
Test status
Simulation time 206988438518 ps
CPU time 70.39 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:36:11 PM PDT 24
Peak memory 193148 kb
Host smart-fd9632c3-c52c-4b31-bedd-6440537c70bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854686420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2854686420
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3431555770
Short name T119
Test name
Test status
Simulation time 130737549983 ps
CPU time 56.41 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:35:50 PM PDT 24
Peak memory 192060 kb
Host smart-1571dbea-dec4-4e4b-8670-16057ea72e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431555770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3431555770
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.627518914
Short name T138
Test name
Test status
Simulation time 336880430599 ps
CPU time 198.41 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:38:26 PM PDT 24
Peak memory 198380 kb
Host smart-f95d7561-a397-4892-98a4-800086ea849b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627518914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.627518914
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1425520770
Short name T99
Test name
Test status
Simulation time 8242982272 ps
CPU time 15.07 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 198668 kb
Host smart-c30a17c6-3d76-484d-81b7-e6322dabcf4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425520770 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1425520770
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1722853460
Short name T98
Test name
Test status
Simulation time 39727166552 ps
CPU time 19.78 seconds
Started Aug 16 04:35:03 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 198368 kb
Host smart-97032ef6-3f9c-46ec-bfd1-f36f71b1302e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722853460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1722853460
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2877680603
Short name T151
Test name
Test status
Simulation time 68433583105 ps
CPU time 41.39 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 214200 kb
Host smart-d7251f75-0cf0-46a3-9ab8-f91ae3cc617b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877680603 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2877680603
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3337067276
Short name T141
Test name
Test status
Simulation time 4723080811 ps
CPU time 2.46 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 184332 kb
Host smart-597def73-ffb8-4439-beb3-2ca35d6de2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337067276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3337067276
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1486878544
Short name T131
Test name
Test status
Simulation time 32401525491 ps
CPU time 45.33 seconds
Started Aug 16 04:34:50 PM PDT 24
Finished Aug 16 04:35:36 PM PDT 24
Peak memory 198472 kb
Host smart-ca8ed23c-be75-43f6-8a4b-20698e771d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486878544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1486878544
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1898490410
Short name T153
Test name
Test status
Simulation time 4874920340 ps
CPU time 11.4 seconds
Started Aug 16 04:35:00 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 214440 kb
Host smart-ee9af12f-8168-4fcc-bc2f-8fdbf0bea3b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898490410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1898490410
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2494072893
Short name T113
Test name
Test status
Simulation time 80830452321 ps
CPU time 101 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:36:47 PM PDT 24
Peak memory 190744 kb
Host smart-a0bc1631-7de9-45d0-8294-bc56f9508e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494072893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2494072893
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.16162692
Short name T112
Test name
Test status
Simulation time 2409466087 ps
CPU time 12.22 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 215048 kb
Host smart-76970fbe-a79d-4681-9595-22b522b46af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16162692 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.16162692
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.330545152
Short name T145
Test name
Test status
Simulation time 115031241884 ps
CPU time 64.21 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:36:12 PM PDT 24
Peak memory 192824 kb
Host smart-b254a875-1391-41b3-b66d-a8894cc59085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330545152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.330545152
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2851387498
Short name T78
Test name
Test status
Simulation time 3738791239 ps
CPU time 23.33 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:44 PM PDT 24
Peak memory 206844 kb
Host smart-3031619f-727d-46e5-a06f-66d389fdd151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851387498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2851387498
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2626812593
Short name T132
Test name
Test status
Simulation time 45784080918 ps
CPU time 21.08 seconds
Started Aug 16 04:35:19 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 192532 kb
Host smart-970f52f0-8e97-47e8-973f-d9c1100f19ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626812593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2626812593
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3705332936
Short name T120
Test name
Test status
Simulation time 426455618488 ps
CPU time 159.93 seconds
Started Aug 16 04:34:37 PM PDT 24
Finished Aug 16 04:37:17 PM PDT 24
Peak memory 198348 kb
Host smart-374400b1-4921-4468-9292-4db877637d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705332936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3705332936
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3106857415
Short name T154
Test name
Test status
Simulation time 4175712710 ps
CPU time 13.63 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 214020 kb
Host smart-9cfc0cc3-9420-4fc7-972e-87662f268f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106857415 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3106857415
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3080725674
Short name T146
Test name
Test status
Simulation time 140389304039 ps
CPU time 18.71 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 191996 kb
Host smart-eb4cef37-c878-4cd6-b437-6f3be259545d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080725674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3080725674
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2217320550
Short name T126
Test name
Test status
Simulation time 3825990070 ps
CPU time 27.77 seconds
Started Aug 16 04:34:43 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 206892 kb
Host smart-c31c0ec6-2849-4da8-a61e-bd4cb7c28a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217320550 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2217320550
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2962651703
Short name T101
Test name
Test status
Simulation time 5430592901 ps
CPU time 33.42 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 206908 kb
Host smart-5faf2c27-79e0-4c13-92f9-6b156513f9f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962651703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2962651703
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3690894656
Short name T152
Test name
Test status
Simulation time 101716450541 ps
CPU time 11.7 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 198436 kb
Host smart-00f5b504-7423-4265-8b7f-d30fedf792b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690894656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3690894656
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1916585702
Short name T45
Test name
Test status
Simulation time 5358838471 ps
CPU time 35.45 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:46 PM PDT 24
Peak memory 206852 kb
Host smart-6aaed34a-9db6-4c47-93c4-4145422becfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916585702 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1916585702
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2811641056
Short name T44
Test name
Test status
Simulation time 13529672605 ps
CPU time 33.98 seconds
Started Aug 16 04:35:03 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 214420 kb
Host smart-43015976-b3ee-48c8-80b6-0c35565ac054
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811641056 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2811641056
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2416043459
Short name T149
Test name
Test status
Simulation time 206657774229 ps
CPU time 279.57 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:39:22 PM PDT 24
Peak memory 198340 kb
Host smart-fa25e6a1-7b3f-4f56-85f8-da9be2461f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416043459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2416043459
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1047835437
Short name T91
Test name
Test status
Simulation time 456163565 ps
CPU time 1.22 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 196900 kb
Host smart-19c9a45f-ccf6-48b9-ba1f-f7542464bb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047835437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1047835437
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2637654562
Short name T166
Test name
Test status
Simulation time 3567619068 ps
CPU time 16.69 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 215140 kb
Host smart-fe36ff8a-22b9-466a-950c-282c0d8c7331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637654562 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2637654562
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.324680610
Short name T97
Test name
Test status
Simulation time 463956964 ps
CPU time 0.8 seconds
Started Aug 16 04:35:04 PM PDT 24
Finished Aug 16 04:35:05 PM PDT 24
Peak memory 196864 kb
Host smart-fae8547a-f2b7-48fc-b678-fb2538ee0f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324680610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.324680610
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3886634871
Short name T95
Test name
Test status
Simulation time 79119772456 ps
CPU time 113.12 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:37:09 PM PDT 24
Peak memory 198392 kb
Host smart-2871861f-7943-4f53-bd00-5b57e1e2aab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886634871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3886634871
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4149368032
Short name T90
Test name
Test status
Simulation time 431282180 ps
CPU time 1.28 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 196856 kb
Host smart-4fe85a2a-faea-415a-ae4a-1618524413d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149368032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4149368032
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.512290472
Short name T9
Test name
Test status
Simulation time 159954908435 ps
CPU time 42.67 seconds
Started Aug 16 04:34:40 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 184316 kb
Host smart-cf6dd419-3506-454b-8f45-2b544ab0a373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512290472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.512290472
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4181088485
Short name T161
Test name
Test status
Simulation time 154204809735 ps
CPU time 38.97 seconds
Started Aug 16 04:34:41 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 192660 kb
Host smart-8b01be5d-bc0d-4b3f-8c63-4ec290f43066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181088485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4181088485
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3670764330
Short name T103
Test name
Test status
Simulation time 536978709 ps
CPU time 0.76 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 196768 kb
Host smart-b9637241-6e69-4034-a9e4-dd1e497adb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670764330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3670764330
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2405173379
Short name T108
Test name
Test status
Simulation time 551944947 ps
CPU time 1.39 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 196888 kb
Host smart-7b98a5c3-3556-4740-a428-d042e199949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405173379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2405173379
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1061585147
Short name T170
Test name
Test status
Simulation time 93850006007 ps
CPU time 128.64 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:37:19 PM PDT 24
Peak memory 193092 kb
Host smart-0f5f950b-819a-4781-9151-2adfc5636245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061585147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1061585147
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1547989208
Short name T173
Test name
Test status
Simulation time 472361988568 ps
CPU time 46.47 seconds
Started Aug 16 04:35:04 PM PDT 24
Finished Aug 16 04:35:55 PM PDT 24
Peak memory 198428 kb
Host smart-5c3de03e-9176-4fa6-9a13-b627f9717e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547989208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1547989208
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1455282871
Short name T125
Test name
Test status
Simulation time 574707733 ps
CPU time 1.45 seconds
Started Aug 16 04:34:32 PM PDT 24
Finished Aug 16 04:34:34 PM PDT 24
Peak memory 196784 kb
Host smart-77f62d99-0775-4e01-a4d1-9e1db00f5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455282871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1455282871
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3879204236
Short name T88
Test name
Test status
Simulation time 524213465 ps
CPU time 1.29 seconds
Started Aug 16 04:34:37 PM PDT 24
Finished Aug 16 04:34:39 PM PDT 24
Peak memory 196808 kb
Host smart-fcef3c29-69d4-4de5-98fb-4f27eb8b3b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879204236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3879204236
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.945504296
Short name T129
Test name
Test status
Simulation time 179089596586 ps
CPU time 58.66 seconds
Started Aug 16 04:34:49 PM PDT 24
Finished Aug 16 04:35:48 PM PDT 24
Peak memory 192548 kb
Host smart-91399d4b-bd02-41bb-9b4e-421c74de9536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945504296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.945504296
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.228237294
Short name T139
Test name
Test status
Simulation time 578304237 ps
CPU time 0.91 seconds
Started Aug 16 04:34:48 PM PDT 24
Finished Aug 16 04:34:49 PM PDT 24
Peak memory 196752 kb
Host smart-82d8d410-3153-4a89-9e02-e5f1859c99b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228237294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.228237294
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2692152710
Short name T147
Test name
Test status
Simulation time 555352151 ps
CPU time 1.46 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:34:53 PM PDT 24
Peak memory 196780 kb
Host smart-d18d4176-e473-4778-b26d-af43354f002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692152710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2692152710
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1437369568
Short name T124
Test name
Test status
Simulation time 136025247243 ps
CPU time 95.56 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:36:37 PM PDT 24
Peak memory 192056 kb
Host smart-fb519e17-f34c-49dc-bf4b-2204dcc127f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437369568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1437369568
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2808066276
Short name T33
Test name
Test status
Simulation time 474477498 ps
CPU time 0.9 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 196768 kb
Host smart-ac06633b-c354-4493-8def-065bc8ad891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808066276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2808066276
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3712240723
Short name T143
Test name
Test status
Simulation time 66599607633 ps
CPU time 28.15 seconds
Started Aug 16 04:34:46 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 193096 kb
Host smart-5507a038-8302-4db9-b5c1-e0a421c8cbcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712240723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3712240723
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2222100542
Short name T133
Test name
Test status
Simulation time 237863089901 ps
CPU time 309.85 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:39:52 PM PDT 24
Peak memory 198336 kb
Host smart-0e2a21f4-c11a-4f4f-83ca-759ce4790b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222100542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2222100542
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.593494898
Short name T137
Test name
Test status
Simulation time 500725069 ps
CPU time 0.63 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 196860 kb
Host smart-8b229158-6a2e-487c-807a-b0cc08f0f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593494898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.593494898
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3266277004
Short name T105
Test name
Test status
Simulation time 412106397 ps
CPU time 0.73 seconds
Started Aug 16 04:34:58 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 196780 kb
Host smart-a6c2eb43-6028-409e-bfd8-b2243a365df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266277004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3266277004
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.780199231
Short name T122
Test name
Test status
Simulation time 529453132 ps
CPU time 0.75 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 196840 kb
Host smart-5a8d8829-b006-40cb-8706-902ab7453e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780199231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.780199231
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2662166919
Short name T169
Test name
Test status
Simulation time 4293310573 ps
CPU time 29.34 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 198712 kb
Host smart-cf01f1cd-9af8-4b94-8dc5-d2a4007bf165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662166919 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2662166919
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.211620208
Short name T117
Test name
Test status
Simulation time 103017747135 ps
CPU time 33.42 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 192084 kb
Host smart-4009a7fa-3db3-4b77-b1fc-b8ecb2a00078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211620208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.211620208
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.782599538
Short name T94
Test name
Test status
Simulation time 437547828 ps
CPU time 0.71 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:35:03 PM PDT 24
Peak memory 196828 kb
Host smart-81ebe19e-7ece-46dc-96dc-8fc0b649877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782599538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.782599538
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1821391754
Short name T18
Test name
Test status
Simulation time 1413046311 ps
CPU time 7.69 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 206888 kb
Host smart-70c58bb0-22d2-4191-80a3-140d4e5668f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821391754 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1821391754
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.434948863
Short name T136
Test name
Test status
Simulation time 476167607 ps
CPU time 1.21 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 196840 kb
Host smart-09dcceca-b0b1-4370-bb11-769c4001cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434948863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.434948863
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3363930413
Short name T167
Test name
Test status
Simulation time 103125419708 ps
CPU time 150.23 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:37:15 PM PDT 24
Peak memory 193224 kb
Host smart-02b40b24-46fb-4e66-b6dc-2aa00b76ed39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363930413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3363930413
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3004093075
Short name T144
Test name
Test status
Simulation time 544939001 ps
CPU time 0.79 seconds
Started Aug 16 04:34:41 PM PDT 24
Finished Aug 16 04:34:42 PM PDT 24
Peak memory 196952 kb
Host smart-1eec4a1d-8b88-4515-8757-c9a8a25441f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004093075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3004093075
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2606929904
Short name T163
Test name
Test status
Simulation time 2465320434 ps
CPU time 18.5 seconds
Started Aug 16 04:34:50 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 214532 kb
Host smart-fd93beac-e7ef-4738-944c-bf80a5d52015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606929904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2606929904
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1361207354
Short name T83
Test name
Test status
Simulation time 57591445799 ps
CPU time 88.11 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:36:30 PM PDT 24
Peak memory 198404 kb
Host smart-ecf722ff-b6a4-459b-830d-0e9fdc79d85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361207354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1361207354
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2242308404
Short name T165
Test name
Test status
Simulation time 8279920128 ps
CPU time 29.93 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 215032 kb
Host smart-7076b81c-6588-4517-a3ec-2ae33595917b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242308404 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2242308404
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2237291131
Short name T140
Test name
Test status
Simulation time 562529174 ps
CPU time 0.78 seconds
Started Aug 16 04:35:03 PM PDT 24
Finished Aug 16 04:35:04 PM PDT 24
Peak memory 196872 kb
Host smart-336c73ed-bb46-40dc-ba4c-197b015c0138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237291131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2237291131
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3567615693
Short name T162
Test name
Test status
Simulation time 134626011960 ps
CPU time 213.35 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:38:40 PM PDT 24
Peak memory 192060 kb
Host smart-d45bb97d-8fa5-46cb-b974-6dc12552b33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567615693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3567615693
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2985872861
Short name T111
Test name
Test status
Simulation time 566423231 ps
CPU time 1.32 seconds
Started Aug 16 04:35:23 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 196828 kb
Host smart-35c57033-8d21-45af-a57a-d143d215f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985872861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2985872861
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2668489420
Short name T27
Test name
Test status
Simulation time 604848101 ps
CPU time 0.84 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 196828 kb
Host smart-d4f89835-1ebf-4597-9811-27f311404576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668489420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2668489420
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.734791777
Short name T148
Test name
Test status
Simulation time 660615461 ps
CPU time 0.65 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:34:43 PM PDT 24
Peak memory 196796 kb
Host smart-31487a6f-f577-40bd-98cd-d68932076a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734791777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.734791777
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3130433091
Short name T114
Test name
Test status
Simulation time 438779655 ps
CPU time 0.73 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 196872 kb
Host smart-a45f4086-2894-4f48-85cd-9cb66771004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130433091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3130433091
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.23468252
Short name T168
Test name
Test status
Simulation time 9897843288 ps
CPU time 24.58 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 206836 kb
Host smart-20a8b675-09e8-4970-9c6b-093756e8a367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23468252 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.23468252
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2178812752
Short name T106
Test name
Test status
Simulation time 399582318 ps
CPU time 0.96 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 196800 kb
Host smart-4fa57c60-c15f-47dc-8f50-f1c521525f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178812752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2178812752
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.718685221
Short name T116
Test name
Test status
Simulation time 77990783506 ps
CPU time 28.09 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 192164 kb
Host smart-e45ff57a-253a-40fa-ae3d-43c7dc940bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718685221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.718685221
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1238173115
Short name T87
Test name
Test status
Simulation time 573835628 ps
CPU time 0.73 seconds
Started Aug 16 04:35:17 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 196752 kb
Host smart-9791be58-ee1c-401a-b08f-003d7d30d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238173115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1238173115
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2921063647
Short name T86
Test name
Test status
Simulation time 556258340 ps
CPU time 1.36 seconds
Started Aug 16 04:34:37 PM PDT 24
Finished Aug 16 04:34:39 PM PDT 24
Peak memory 196868 kb
Host smart-758878ea-0dc2-452b-a20e-d4e0b4d31d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921063647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2921063647
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2807293858
Short name T46
Test name
Test status
Simulation time 2349335351 ps
CPU time 12.01 seconds
Started Aug 16 04:34:49 PM PDT 24
Finished Aug 16 04:35:01 PM PDT 24
Peak memory 206864 kb
Host smart-bcbf79f2-256c-445b-9937-746735b212b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807293858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2807293858
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.187689160
Short name T176
Test name
Test status
Simulation time 473444538 ps
CPU time 0.78 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:34:51 PM PDT 24
Peak memory 196888 kb
Host smart-8c5944ae-e41c-42de-b925-27a231e1b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187689160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.187689160
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.54165951
Short name T187
Test name
Test status
Simulation time 392701410 ps
CPU time 1.05 seconds
Started Aug 16 04:34:58 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 196940 kb
Host smart-38d1e3bf-53ac-4be9-9acc-b1853a0f09aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54165951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.54165951
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.511031973
Short name T158
Test name
Test status
Simulation time 522916458 ps
CPU time 0.81 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:34:54 PM PDT 24
Peak memory 196704 kb
Host smart-66906d16-8ef8-4c17-b5bf-51c093dd525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511031973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.511031973
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2181581689
Short name T25
Test name
Test status
Simulation time 603929982 ps
CPU time 0.83 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 196764 kb
Host smart-b2d482c4-f7e9-4448-9e4f-aa0a993050e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181581689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2181581689
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1576783368
Short name T160
Test name
Test status
Simulation time 512435184 ps
CPU time 1.35 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 196844 kb
Host smart-b1c038fb-dc83-4372-b3ab-9dc253ecd16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576783368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1576783368
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.139149405
Short name T175
Test name
Test status
Simulation time 501682605 ps
CPU time 0.78 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 196772 kb
Host smart-2171b582-fe29-48f5-92d4-c8e066b7e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139149405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.139149405
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.915377688
Short name T20
Test name
Test status
Simulation time 82551759134 ps
CPU time 28.02 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:39 PM PDT 24
Peak memory 198424 kb
Host smart-84419889-1a62-47a3-ac85-f07b8d922404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915377688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.915377688
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.443720662
Short name T47
Test name
Test status
Simulation time 579510859 ps
CPU time 0.78 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 196880 kb
Host smart-073d42b2-f551-48a6-9d42-c77dcedf29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443720662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.443720662
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2283669266
Short name T157
Test name
Test status
Simulation time 97950673467 ps
CPU time 30.09 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 192076 kb
Host smart-eb5086c5-f7bd-4121-986d-39dcccc3f501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283669266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2283669266
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.407693068
Short name T12
Test name
Test status
Simulation time 6410238804 ps
CPU time 22.31 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 214096 kb
Host smart-a92bed76-5460-4fdf-a3f2-12a5db545567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407693068 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.407693068
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1501284119
Short name T76
Test name
Test status
Simulation time 3098407175 ps
CPU time 20.59 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 206892 kb
Host smart-4a994821-b8ef-4423-9216-ddffdb6cf567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501284119 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1501284119
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.814324925
Short name T197
Test name
Test status
Simulation time 9241762306 ps
CPU time 2.2 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 198196 kb
Host smart-c3bcb73d-33bd-492b-a760-698d7d515783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814324925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.814324925
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1123000263
Short name T118
Test name
Test status
Simulation time 446275884 ps
CPU time 0.76 seconds
Started Aug 16 04:34:54 PM PDT 24
Finished Aug 16 04:34:55 PM PDT 24
Peak memory 196900 kb
Host smart-7196f2bc-bfda-4dfd-b857-44168ed32a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123000263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1123000263
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.69117897
Short name T188
Test name
Test status
Simulation time 487917937 ps
CPU time 0.77 seconds
Started Aug 16 04:35:03 PM PDT 24
Finished Aug 16 04:35:04 PM PDT 24
Peak memory 196752 kb
Host smart-5be28b0d-c664-4145-a99b-46290cbfec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69117897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.69117897
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1604153392
Short name T183
Test name
Test status
Simulation time 2132728453 ps
CPU time 17.58 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 206808 kb
Host smart-c7685971-cae5-42fc-a850-d8ad6d0ecadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604153392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1604153392
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.438218725
Short name T11
Test name
Test status
Simulation time 407833016 ps
CPU time 0.75 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:07 PM PDT 24
Peak memory 196968 kb
Host smart-258def2e-7f09-4793-bb2b-54f294d7b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438218725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.438218725
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2153655163
Short name T164
Test name
Test status
Simulation time 463765945 ps
CPU time 0.63 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 196772 kb
Host smart-52965c99-86f5-43cd-bbc9-0d3bd9a93f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153655163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2153655163
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1581459279
Short name T178
Test name
Test status
Simulation time 430231901 ps
CPU time 0.93 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 196820 kb
Host smart-76bd8dcf-f5ed-4595-9b07-e8da40cac46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581459279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1581459279
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.314269133
Short name T192
Test name
Test status
Simulation time 566801660 ps
CPU time 0.8 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 196780 kb
Host smart-a951966d-0490-4a20-bd78-cab82aced323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314269133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.314269133
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1258131578
Short name T81
Test name
Test status
Simulation time 386894201 ps
CPU time 0.73 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:05 PM PDT 24
Peak memory 196816 kb
Host smart-c6807c1a-7a0b-464d-afcd-2c454c5fac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258131578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1258131578
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2815419119
Short name T184
Test name
Test status
Simulation time 409747915 ps
CPU time 0.78 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 196772 kb
Host smart-48e87a0d-da22-4c66-8165-7cf38a1a2250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815419119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2815419119
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3957539761
Short name T150
Test name
Test status
Simulation time 392864554 ps
CPU time 0.64 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 196844 kb
Host smart-c7e7ec43-03e5-4bd5-8527-0dcb486258e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957539761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3957539761
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2087554480
Short name T28
Test name
Test status
Simulation time 523728164 ps
CPU time 0.76 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:34:46 PM PDT 24
Peak memory 196848 kb
Host smart-339567d0-99da-4614-a109-018a1f9dd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087554480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2087554480
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1329127261
Short name T186
Test name
Test status
Simulation time 373785063 ps
CPU time 0.87 seconds
Started Aug 16 04:34:48 PM PDT 24
Finished Aug 16 04:34:48 PM PDT 24
Peak memory 196784 kb
Host smart-d7714f83-fa99-4f29-8d2a-55eede9ce4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329127261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1329127261
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.517392835
Short name T159
Test name
Test status
Simulation time 295675925802 ps
CPU time 78.63 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:36:16 PM PDT 24
Peak memory 184344 kb
Host smart-3be89094-6e9b-490a-9de1-410e04d3d05e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517392835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.517392835
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1641715431
Short name T179
Test name
Test status
Simulation time 541670644 ps
CPU time 0.66 seconds
Started Aug 16 04:34:54 PM PDT 24
Finished Aug 16 04:34:55 PM PDT 24
Peak memory 196872 kb
Host smart-35eb6c53-2a4b-4598-90e9-3f5f0904eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641715431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1641715431
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3346419863
Short name T194
Test name
Test status
Simulation time 425391541 ps
CPU time 0.74 seconds
Started Aug 16 04:35:00 PM PDT 24
Finished Aug 16 04:35:01 PM PDT 24
Peak memory 196876 kb
Host smart-0e913bc3-2edf-4a10-afc2-c0901de9ead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346419863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3346419863
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.636220512
Short name T189
Test name
Test status
Simulation time 535834585 ps
CPU time 0.86 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 196816 kb
Host smart-fd6ef367-849c-4c4b-940b-306a96e2e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636220512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.636220512
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3572463311
Short name T185
Test name
Test status
Simulation time 452768693 ps
CPU time 0.71 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 196796 kb
Host smart-74f3964d-8c37-4250-8ce7-dd9fb07de7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572463311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3572463311
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.87757840
Short name T29
Test name
Test status
Simulation time 5051498288 ps
CPU time 10.29 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 198696 kb
Host smart-0385dcd7-b625-4cca-8f3f-5dd1511822cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87757840 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.87757840
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3475581595
Short name T172
Test name
Test status
Simulation time 1025432908 ps
CPU time 5.47 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 206848 kb
Host smart-4dddc6ee-0270-4b17-b644-cb720307f28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475581595 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3475581595
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2568199516
Short name T180
Test name
Test status
Simulation time 8541991024 ps
CPU time 16.49 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 206900 kb
Host smart-e9f30a0a-86d5-4067-8e57-1cb901afd6c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568199516 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2568199516
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3188519507
Short name T336
Test name
Test status
Simulation time 605731087 ps
CPU time 1.09 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 193144 kb
Host smart-aed8a4e1-5410-4352-b119-f4e5d44d8af9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188519507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3188519507
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2197143766
Short name T378
Test name
Test status
Simulation time 7164584103 ps
CPU time 9.25 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:36 PM PDT 24
Peak memory 192188 kb
Host smart-d18771ab-6fb6-444d-88f2-0f978a896075
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197143766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2197143766
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2892421836
Short name T36
Test name
Test status
Simulation time 1159720110 ps
CPU time 2.41 seconds
Started Aug 16 04:35:42 PM PDT 24
Finished Aug 16 04:35:44 PM PDT 24
Peak memory 193340 kb
Host smart-f1da9430-d485-4f86-bf69-98b489cef4d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892421836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2892421836
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.582946919
Short name T209
Test name
Test status
Simulation time 371941841 ps
CPU time 0.88 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 198012 kb
Host smart-5270f764-1997-4ec3-9176-d22caec9057a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582946919 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.582946919
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2308794193
Short name T34
Test name
Test status
Simulation time 451630878 ps
CPU time 1.17 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 192936 kb
Host smart-f250d576-4b5f-4bcf-b5b1-b24292d3c02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308794193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2308794193
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1524083510
Short name T399
Test name
Test status
Simulation time 401501192 ps
CPU time 0.72 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 192852 kb
Host smart-65b52f8e-a1aa-4433-97dc-b4847c034b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524083510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1524083510
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1926594035
Short name T317
Test name
Test status
Simulation time 349128299 ps
CPU time 0.59 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 183568 kb
Host smart-e8231d58-3ba4-4ce6-a82d-ff35dd3a6eb5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926594035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1926594035
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4046409481
Short name T386
Test name
Test status
Simulation time 493258085 ps
CPU time 1.3 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 183596 kb
Host smart-aec26ee9-9c63-4315-99ce-e7ba778adb17
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046409481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4046409481
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3637687624
Short name T416
Test name
Test status
Simulation time 1246867932 ps
CPU time 2.33 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 193496 kb
Host smart-b738fc99-388a-40dd-ab18-50692a90a76c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637687624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3637687624
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.721736597
Short name T325
Test name
Test status
Simulation time 550472318 ps
CPU time 1.31 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 198564 kb
Host smart-9cc39daf-da85-4ad2-9743-fd7a3951a53c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721736597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.721736597
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3266720724
Short name T413
Test name
Test status
Simulation time 7513667605 ps
CPU time 4.71 seconds
Started Aug 16 04:35:48 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 192164 kb
Host smart-943ef76f-3dec-48f2-8f7f-8579974bb9b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266720724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3266720724
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3595552164
Short name T73
Test name
Test status
Simulation time 747452553 ps
CPU time 1.55 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:26 PM PDT 24
Peak memory 183648 kb
Host smart-6de528d2-7e72-4bcc-b9d4-bff2b959e8a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595552164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3595552164
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.353058250
Short name T296
Test name
Test status
Simulation time 493481564 ps
CPU time 0.77 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 195564 kb
Host smart-4a4a375f-7531-49a2-ae3b-73114deb99e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353058250 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.353058250
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1699495510
Short name T60
Test name
Test status
Simulation time 432365606 ps
CPU time 0.79 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 193304 kb
Host smart-45b34bb0-039a-4a5a-b2d7-8bf8b176e014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699495510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1699495510
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2916491606
Short name T311
Test name
Test status
Simulation time 545124627 ps
CPU time 0.58 seconds
Started Aug 16 04:35:14 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 192980 kb
Host smart-61d107ad-a7a9-42bc-883a-0f3c599151e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916491606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2916491606
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1549639300
Short name T415
Test name
Test status
Simulation time 400534615 ps
CPU time 1 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 183608 kb
Host smart-6d2c7946-6088-4de1-b37a-a65bf0c49532
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549639300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1549639300
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1597810892
Short name T344
Test name
Test status
Simulation time 363420655 ps
CPU time 0.77 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 183592 kb
Host smart-778b3851-91dc-4953-b76e-1256fdc10a7e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597810892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1597810892
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.959167892
Short name T342
Test name
Test status
Simulation time 2031395165 ps
CPU time 3.37 seconds
Started Aug 16 04:35:35 PM PDT 24
Finished Aug 16 04:35:39 PM PDT 24
Peak memory 183936 kb
Host smart-02c0413b-7c7c-42bb-89f3-f10b733fa0ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959167892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.959167892
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3631701600
Short name T362
Test name
Test status
Simulation time 454352698 ps
CPU time 2.39 seconds
Started Aug 16 04:35:25 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 198472 kb
Host smart-9363194e-bc50-4666-82c9-766cb8247f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631701600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3631701600
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3074200317
Short name T351
Test name
Test status
Simulation time 8121455494 ps
CPU time 3.26 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 198004 kb
Host smart-e4113352-3c5a-43c0-8498-72aa929bd79d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074200317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3074200317
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4169449652
Short name T318
Test name
Test status
Simulation time 580657632 ps
CPU time 1.02 seconds
Started Aug 16 04:35:34 PM PDT 24
Finished Aug 16 04:35:35 PM PDT 24
Peak memory 198368 kb
Host smart-0133581b-3b64-4255-b7d6-997e239324fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169449652 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4169449652
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1607084861
Short name T56
Test name
Test status
Simulation time 514674103 ps
CPU time 1 seconds
Started Aug 16 04:35:14 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 193276 kb
Host smart-18492987-fcb8-40b8-8847-38f91a4ab873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607084861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1607084861
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.314083808
Short name T305
Test name
Test status
Simulation time 374787195 ps
CPU time 1.13 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183756 kb
Host smart-68b82c0e-9e4e-4ac8-a980-c9d942881483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314083808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.314083808
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1414276071
Short name T398
Test name
Test status
Simulation time 2097252124 ps
CPU time 3.62 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 193788 kb
Host smart-6e86925f-d508-451e-a098-e98aae3de9c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414276071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1414276071
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3566133823
Short name T339
Test name
Test status
Simulation time 563162976 ps
CPU time 1.63 seconds
Started Aug 16 04:35:27 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 198560 kb
Host smart-dfdcc8fd-0426-4755-b5ba-d1397c8e898d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566133823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3566133823
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1531688334
Short name T195
Test name
Test status
Simulation time 8109538322 ps
CPU time 4.17 seconds
Started Aug 16 04:35:28 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 198428 kb
Host smart-3217904e-03f8-4b55-86d7-ade572c9f2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531688334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1531688334
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2460727532
Short name T394
Test name
Test status
Simulation time 506096577 ps
CPU time 1.3 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 195496 kb
Host smart-4341729d-3ba8-46e7-bcbb-44799d0122b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460727532 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2460727532
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3818967834
Short name T66
Test name
Test status
Simulation time 473565179 ps
CPU time 0.62 seconds
Started Aug 16 04:35:37 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 193268 kb
Host smart-3562fc68-ae55-4ca2-904a-933712fa9aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818967834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3818967834
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1782798599
Short name T350
Test name
Test status
Simulation time 514039829 ps
CPU time 0.72 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183656 kb
Host smart-996de8b8-d48b-45c1-976e-05aa1cf34159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782798599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1782798599
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1734509019
Short name T332
Test name
Test status
Simulation time 2408517497 ps
CPU time 2.14 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 194852 kb
Host smart-ceb46257-2e9b-44f5-b0ae-406b53f15f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734509019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1734509019
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1380040909
Short name T371
Test name
Test status
Simulation time 299630674 ps
CPU time 1.31 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 198496 kb
Host smart-2c015f3f-8bfd-4ab1-aff3-9c8e70f87009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380040909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1380040909
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.126790248
Short name T315
Test name
Test status
Simulation time 4544148234 ps
CPU time 2.39 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 197984 kb
Host smart-69182c0e-cf30-4ce4-9721-e3784d686741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126790248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.126790248
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3273823587
Short name T387
Test name
Test status
Simulation time 348266454 ps
CPU time 0.85 seconds
Started Aug 16 04:35:32 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 196324 kb
Host smart-40d2385a-5b12-4d36-ad35-45422312d367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273823587 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3273823587
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2007883919
Short name T54
Test name
Test status
Simulation time 512264344 ps
CPU time 1.42 seconds
Started Aug 16 04:35:31 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 193932 kb
Host smart-d81eda3f-8e6e-47fa-926e-3c18c0ee3601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007883919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2007883919
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2195289768
Short name T293
Test name
Test status
Simulation time 454410099 ps
CPU time 1.15 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 192892 kb
Host smart-7232a682-a5c7-42d5-a4e0-6222f1eedeee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195289768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2195289768
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.935269694
Short name T389
Test name
Test status
Simulation time 2236042130 ps
CPU time 1.99 seconds
Started Aug 16 04:35:35 PM PDT 24
Finished Aug 16 04:35:43 PM PDT 24
Peak memory 193956 kb
Host smart-3087003e-283c-4eed-a643-0881ff384ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935269694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.935269694
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3288387154
Short name T308
Test name
Test status
Simulation time 598211241 ps
CPU time 2.82 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 198480 kb
Host smart-d6e78504-60e6-41e7-a7a5-e7ce0245770c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288387154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3288387154
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1672529104
Short name T422
Test name
Test status
Simulation time 8581760868 ps
CPU time 4.59 seconds
Started Aug 16 04:35:33 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 198136 kb
Host smart-e4f75281-0f35-41ec-beab-4b66ca22c7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672529104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1672529104
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2020467314
Short name T335
Test name
Test status
Simulation time 431038923 ps
CPU time 1.13 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:39 PM PDT 24
Peak memory 198368 kb
Host smart-5059d991-14ae-46c6-ac97-5884c4db293b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020467314 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2020467314
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4166185987
Short name T333
Test name
Test status
Simulation time 404843114 ps
CPU time 1.12 seconds
Started Aug 16 04:35:43 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 192936 kb
Host smart-1cb64bb9-d5e6-40e2-8725-557e52dc3821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166185987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4166185987
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1829918620
Short name T328
Test name
Test status
Simulation time 286927225 ps
CPU time 0.69 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 192908 kb
Host smart-75d5b91b-bbdd-4840-a71f-19538d4a013c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829918620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1829918620
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1387950039
Short name T70
Test name
Test status
Simulation time 1594897569 ps
CPU time 1.15 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 193832 kb
Host smart-efb3d32d-2703-4fff-9c05-eab67c6f61ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387950039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1387950039
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.511479616
Short name T372
Test name
Test status
Simulation time 401922934 ps
CPU time 1.22 seconds
Started Aug 16 04:35:42 PM PDT 24
Finished Aug 16 04:35:43 PM PDT 24
Peak memory 198300 kb
Host smart-f5b317f4-6938-42bd-af3f-210abda7b409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511479616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.511479616
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.52692246
Short name T38
Test name
Test status
Simulation time 8666040159 ps
CPU time 4.28 seconds
Started Aug 16 04:35:47 PM PDT 24
Finished Aug 16 04:35:52 PM PDT 24
Peak memory 198104 kb
Host smart-54e4aebe-f15c-4243-b370-3e9cb0da4390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52692246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_
intg_err.52692246
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1936688623
Short name T368
Test name
Test status
Simulation time 514168312 ps
CPU time 0.78 seconds
Started Aug 16 04:35:34 PM PDT 24
Finished Aug 16 04:35:35 PM PDT 24
Peak memory 195652 kb
Host smart-98448a3c-f3f9-4937-af98-32a44f9801c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936688623 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1936688623
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2134528671
Short name T64
Test name
Test status
Simulation time 493294045 ps
CPU time 1.41 seconds
Started Aug 16 04:35:43 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 194040 kb
Host smart-5e98ba06-d9e7-436b-b245-e091430f8d28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134528671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2134528671
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1748063143
Short name T358
Test name
Test status
Simulation time 503392373 ps
CPU time 0.62 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:39 PM PDT 24
Peak memory 183660 kb
Host smart-90a37bef-15fa-4726-99c1-8872aa48d64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748063143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1748063143
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.808330031
Short name T355
Test name
Test status
Simulation time 2172837638 ps
CPU time 2.08 seconds
Started Aug 16 04:35:50 PM PDT 24
Finished Aug 16 04:35:52 PM PDT 24
Peak memory 193788 kb
Host smart-80a279c0-521c-4542-8419-09a96fa5ea9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808330031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.808330031
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.912981147
Short name T402
Test name
Test status
Simulation time 845767524 ps
CPU time 2.44 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 198524 kb
Host smart-03415fbb-aea9-4478-88c7-ef2ee28eb084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912981147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.912981147
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.338824564
Short name T324
Test name
Test status
Simulation time 4768427827 ps
CPU time 7.87 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 197900 kb
Host smart-b6caf530-321b-4623-a1c4-40642064eb79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338824564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.338824564
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1391335830
Short name T406
Test name
Test status
Simulation time 457805499 ps
CPU time 0.98 seconds
Started Aug 16 04:35:29 PM PDT 24
Finished Aug 16 04:35:30 PM PDT 24
Peak memory 196320 kb
Host smart-b2a4f2fb-eb51-4701-9f59-fd6b45eeaa4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391335830 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1391335830
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.64764640
Short name T57
Test name
Test status
Simulation time 397200469 ps
CPU time 0.82 seconds
Started Aug 16 04:35:57 PM PDT 24
Finished Aug 16 04:35:57 PM PDT 24
Peak memory 193228 kb
Host smart-c7a5d6af-1311-4211-9e1c-080666ca036e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64764640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.64764640
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1007124092
Short name T304
Test name
Test status
Simulation time 394974137 ps
CPU time 1.03 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 183640 kb
Host smart-1364c143-7774-4f47-8c31-41a8ec8fce00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007124092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1007124092
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1706846120
Short name T69
Test name
Test status
Simulation time 911281513 ps
CPU time 1.41 seconds
Started Aug 16 04:35:48 PM PDT 24
Finished Aug 16 04:35:49 PM PDT 24
Peak memory 192904 kb
Host smart-5e166204-8b19-4a0c-b759-ae7dcc274842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706846120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1706846120
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.177383293
Short name T312
Test name
Test status
Simulation time 493877740 ps
CPU time 1.57 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 198552 kb
Host smart-d325f091-1db9-4612-9f3c-806c2aa545a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177383293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.177383293
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3200626904
Short name T198
Test name
Test status
Simulation time 7954824182 ps
CPU time 11.29 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 198448 kb
Host smart-bcee3508-f6b1-4e87-803a-c1975964653f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200626904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3200626904
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.801935975
Short name T383
Test name
Test status
Simulation time 494914347 ps
CPU time 0.79 seconds
Started Aug 16 04:35:27 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 196816 kb
Host smart-99d5e2ea-9461-4738-8fab-4039b95426f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801935975 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.801935975
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1358533927
Short name T412
Test name
Test status
Simulation time 350947765 ps
CPU time 0.87 seconds
Started Aug 16 04:35:46 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 193084 kb
Host smart-a1037733-fb5b-44ba-8a05-8dc7437396e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358533927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1358533927
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2923060427
Short name T330
Test name
Test status
Simulation time 312677743 ps
CPU time 0.65 seconds
Started Aug 16 04:35:37 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 192828 kb
Host smart-54859427-af7a-42f0-b33a-4e06dd607f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923060427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2923060427
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3540314426
Short name T337
Test name
Test status
Simulation time 1134095978 ps
CPU time 1.32 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 193192 kb
Host smart-e3f118cd-530d-4de6-b5d8-8c0caaf6b540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540314426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3540314426
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2437585230
Short name T373
Test name
Test status
Simulation time 435989853 ps
CPU time 2.72 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 198552 kb
Host smart-acb2a205-861f-4bca-a7f9-834494bdc4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437585230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2437585230
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3440710737
Short name T196
Test name
Test status
Simulation time 4320069627 ps
CPU time 1.49 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 196804 kb
Host smart-38b8f84d-72f8-4ff0-9697-0710f5c247a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440710737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3440710737
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2771322304
Short name T210
Test name
Test status
Simulation time 734416116 ps
CPU time 0.8 seconds
Started Aug 16 04:35:53 PM PDT 24
Finished Aug 16 04:35:54 PM PDT 24
Peak memory 197068 kb
Host smart-c2f650a9-e398-42a0-a436-15341fa12eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771322304 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2771322304
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4045344375
Short name T424
Test name
Test status
Simulation time 388891617 ps
CPU time 0.69 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 192872 kb
Host smart-15d62187-4ed5-43db-80c3-7780fad37089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045344375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4045344375
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2015733321
Short name T354
Test name
Test status
Simulation time 420448325 ps
CPU time 0.81 seconds
Started Aug 16 04:35:41 PM PDT 24
Finished Aug 16 04:35:42 PM PDT 24
Peak memory 192868 kb
Host smart-9b7966f3-36ea-4ac4-96f8-da559a87f3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015733321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2015733321
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.174985928
Short name T365
Test name
Test status
Simulation time 2814485088 ps
CPU time 1.6 seconds
Started Aug 16 04:35:53 PM PDT 24
Finished Aug 16 04:35:55 PM PDT 24
Peak memory 195048 kb
Host smart-769433d9-6748-40b0-ada2-74cf2bac9cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174985928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.174985928
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2346119804
Short name T367
Test name
Test status
Simulation time 498439871 ps
CPU time 1.34 seconds
Started Aug 16 04:35:40 PM PDT 24
Finished Aug 16 04:35:42 PM PDT 24
Peak memory 198508 kb
Host smart-fe5e3436-cae2-46d1-aaaa-ee0890d8c74f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346119804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2346119804
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.366250482
Short name T39
Test name
Test status
Simulation time 4527904438 ps
CPU time 7.33 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 197804 kb
Host smart-a2f7c292-f636-4b75-a3a5-9da94e12e10c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366250482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.366250482
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3101446789
Short name T346
Test name
Test status
Simulation time 372277534 ps
CPU time 0.85 seconds
Started Aug 16 04:35:56 PM PDT 24
Finished Aug 16 04:35:57 PM PDT 24
Peak memory 196028 kb
Host smart-9791a27a-2142-4077-99ad-dd77e50bdde1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101446789 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3101446789
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2809842634
Short name T322
Test name
Test status
Simulation time 496090702 ps
CPU time 1.22 seconds
Started Aug 16 04:35:29 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 183608 kb
Host smart-77e04a87-9a47-40da-b9cf-764b2cc21e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809842634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2809842634
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4140243346
Short name T35
Test name
Test status
Simulation time 1653680420 ps
CPU time 1.22 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:46 PM PDT 24
Peak memory 183748 kb
Host smart-5e51dfc0-3fd5-4f48-8d24-702e1c410b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140243346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.4140243346
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2803139805
Short name T364
Test name
Test status
Simulation time 609014473 ps
CPU time 1.18 seconds
Started Aug 16 04:35:34 PM PDT 24
Finished Aug 16 04:35:35 PM PDT 24
Peak memory 197332 kb
Host smart-fd1aab69-2af4-40e0-a58f-3a5975b0b665
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803139805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2803139805
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3409539306
Short name T374
Test name
Test status
Simulation time 4141317877 ps
CPU time 7.42 seconds
Started Aug 16 04:35:42 PM PDT 24
Finished Aug 16 04:35:50 PM PDT 24
Peak memory 197916 kb
Host smart-be7feda1-d578-415a-9c8f-198d5372ecde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409539306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3409539306
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4269989810
Short name T361
Test name
Test status
Simulation time 744574892 ps
CPU time 0.8 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 196164 kb
Host smart-7211fd67-b316-44d2-b408-2bff0d3317b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269989810 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4269989810
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2773952849
Short name T62
Test name
Test status
Simulation time 436295498 ps
CPU time 0.87 seconds
Started Aug 16 04:35:35 PM PDT 24
Finished Aug 16 04:35:36 PM PDT 24
Peak memory 192972 kb
Host smart-a4ec03b3-7565-41b5-af4f-43c08449d0fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773952849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2773952849
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2115683068
Short name T297
Test name
Test status
Simulation time 291619647 ps
CPU time 0.96 seconds
Started Aug 16 04:35:28 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 183652 kb
Host smart-944459b1-ebc0-4cd0-ad89-26b649ca6696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115683068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2115683068
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.511092757
Short name T341
Test name
Test status
Simulation time 2621786072 ps
CPU time 5.23 seconds
Started Aug 16 04:35:35 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 194028 kb
Host smart-0b7e7b0f-ea42-44fc-815d-ad6c4c695e06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511092757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.511092757
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.404835891
Short name T303
Test name
Test status
Simulation time 514581331 ps
CPU time 1.77 seconds
Started Aug 16 04:35:30 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 198504 kb
Host smart-019503b3-8337-45ce-a042-400c34ba6219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404835891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.404835891
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3907047586
Short name T313
Test name
Test status
Simulation time 4980420352 ps
CPU time 1.3 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 196848 kb
Host smart-46fdcdd0-6073-4ce0-a84e-64fe9228f01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907047586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3907047586
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3399057282
Short name T391
Test name
Test status
Simulation time 617908062 ps
CPU time 1.58 seconds
Started Aug 16 04:35:56 PM PDT 24
Finished Aug 16 04:35:58 PM PDT 24
Peak memory 193244 kb
Host smart-aa731f4c-b4ea-4b07-9131-88e67e76b973
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399057282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3399057282
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2279445908
Short name T61
Test name
Test status
Simulation time 3652396377 ps
CPU time 4.3 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 192160 kb
Host smart-b18ba76a-d8ba-4810-8cc8-4b8b7869a4e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279445908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2279445908
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1772686730
Short name T403
Test name
Test status
Simulation time 1245549159 ps
CPU time 2.06 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:26 PM PDT 24
Peak memory 193224 kb
Host smart-d6834573-4175-4050-a01e-c1fb9c1aaf11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772686730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1772686730
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4261806769
Short name T379
Test name
Test status
Simulation time 419902982 ps
CPU time 1.2 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 195900 kb
Host smart-15b75cb5-9f49-4f0c-bbf8-25ebc80fdd4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261806769 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4261806769
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.940240266
Short name T58
Test name
Test status
Simulation time 385571919 ps
CPU time 0.67 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 191616 kb
Host smart-cfb11263-1ed4-4f81-87c1-158810746e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940240266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.940240266
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1438225748
Short name T299
Test name
Test status
Simulation time 464232368 ps
CPU time 0.72 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183680 kb
Host smart-ac5d09a2-a742-41c9-bd21-017370f0cf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438225748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1438225748
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2558594528
Short name T310
Test name
Test status
Simulation time 314089394 ps
CPU time 0.6 seconds
Started Aug 16 04:35:48 PM PDT 24
Finished Aug 16 04:35:49 PM PDT 24
Peak memory 183572 kb
Host smart-39e35dca-87f7-45de-a421-81eae0858aa2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558594528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2558594528
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2033255490
Short name T343
Test name
Test status
Simulation time 273723243 ps
CPU time 0.94 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183604 kb
Host smart-41c0cbfa-d38f-4476-bda9-4922fe40ce49
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033255490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2033255490
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3362798203
Short name T71
Test name
Test status
Simulation time 3168223924 ps
CPU time 2.36 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 192228 kb
Host smart-615e8086-7be5-4688-9e7a-f911b99621d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362798203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3362798203
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3755591190
Short name T316
Test name
Test status
Simulation time 361228322 ps
CPU time 1.62 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 198052 kb
Host smart-0ec9ceb2-85fb-489f-9c17-18e7086419bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755591190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3755591190
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.40024965
Short name T392
Test name
Test status
Simulation time 4386781172 ps
CPU time 4.06 seconds
Started Aug 16 04:35:14 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 197484 kb
Host smart-3da3c84b-7498-4060-94e4-7549bff63313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_i
ntg_err.40024965
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.365510127
Short name T405
Test name
Test status
Simulation time 387521725 ps
CPU time 0.7 seconds
Started Aug 16 04:35:42 PM PDT 24
Finished Aug 16 04:35:43 PM PDT 24
Peak memory 192836 kb
Host smart-07f1ed37-64a8-471c-8a92-18556097cb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365510127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.365510127
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2476548121
Short name T390
Test name
Test status
Simulation time 287956903 ps
CPU time 0.76 seconds
Started Aug 16 04:35:46 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 183500 kb
Host smart-74a8a5f1-2be9-4791-aa79-a9c5f4348679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476548121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2476548121
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1072442785
Short name T329
Test name
Test status
Simulation time 360207200 ps
CPU time 1 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 183632 kb
Host smart-4f4f9807-c50e-403e-8caa-be3bff59c40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072442785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1072442785
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.103520868
Short name T295
Test name
Test status
Simulation time 415111310 ps
CPU time 0.86 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 192892 kb
Host smart-ea6af47f-4337-4f0a-9512-2a84cd632fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103520868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.103520868
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.86330063
Short name T301
Test name
Test status
Simulation time 322701464 ps
CPU time 0.98 seconds
Started Aug 16 04:35:36 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 183756 kb
Host smart-53877da5-9d12-4c07-8966-827efa2c802e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86330063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.86330063
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.951257935
Short name T290
Test name
Test status
Simulation time 397360732 ps
CPU time 1.11 seconds
Started Aug 16 04:35:55 PM PDT 24
Finished Aug 16 04:35:57 PM PDT 24
Peak memory 183648 kb
Host smart-b3df07c6-1256-4447-b7d2-6bcd5202bacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951257935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.951257935
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3303869402
Short name T419
Test name
Test status
Simulation time 397087821 ps
CPU time 0.69 seconds
Started Aug 16 04:35:32 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 183704 kb
Host smart-bef511d0-0a5a-4964-b1a7-d023f1c58877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303869402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3303869402
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2618961032
Short name T357
Test name
Test status
Simulation time 435865616 ps
CPU time 0.67 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 183624 kb
Host smart-ca7af5a3-9a10-4b37-a44e-d9b11b0eb596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618961032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2618961032
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2607885856
Short name T323
Test name
Test status
Simulation time 412172878 ps
CPU time 0.78 seconds
Started Aug 16 04:35:31 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 183612 kb
Host smart-eb68e28c-1a36-4abe-83d6-f61121faf107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607885856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2607885856
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3593583799
Short name T384
Test name
Test status
Simulation time 502650238 ps
CPU time 1.28 seconds
Started Aug 16 04:35:44 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 183660 kb
Host smart-dd0f81ab-c578-444e-b616-c99f2b74b849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593583799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3593583799
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1951351779
Short name T377
Test name
Test status
Simulation time 481296476 ps
CPU time 0.97 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 193296 kb
Host smart-0374f56e-6fe8-42ca-b225-220aeed585d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951351779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1951351779
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3314843743
Short name T397
Test name
Test status
Simulation time 7689198650 ps
CPU time 2.09 seconds
Started Aug 16 04:35:34 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 195756 kb
Host smart-85fda4ab-321d-40b4-b595-eaeea3ff4819
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314843743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3314843743
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1557467669
Short name T59
Test name
Test status
Simulation time 807533220 ps
CPU time 1.4 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 183740 kb
Host smart-247210bf-c1c8-4867-bf96-63184f2f7908
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557467669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1557467669
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1118933096
Short name T353
Test name
Test status
Simulation time 428209011 ps
CPU time 0.93 seconds
Started Aug 16 04:35:31 PM PDT 24
Finished Aug 16 04:35:33 PM PDT 24
Peak memory 195940 kb
Host smart-8321fe86-ac21-40b1-9ab7-d6e530ef400d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118933096 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1118933096
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.385323876
Short name T55
Test name
Test status
Simulation time 368207544 ps
CPU time 1.13 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 193968 kb
Host smart-158c4e9e-5528-4bbf-b413-d19dad9d5fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385323876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.385323876
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2395262005
Short name T302
Test name
Test status
Simulation time 357877211 ps
CPU time 0.64 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 183620 kb
Host smart-bc9859fe-3a64-405e-9ca0-2de0d180dd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395262005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2395262005
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.819300797
Short name T418
Test name
Test status
Simulation time 458895566 ps
CPU time 0.64 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 183604 kb
Host smart-4b79f5f8-8f09-4b66-8a34-e1a6e69e9124
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819300797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.819300797
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2537381924
Short name T300
Test name
Test status
Simulation time 283102966 ps
CPU time 0.75 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 183576 kb
Host smart-c20ef1d5-ee16-4b7b-a564-406c248d0b9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537381924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2537381924
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.789296757
Short name T425
Test name
Test status
Simulation time 2343460755 ps
CPU time 1.37 seconds
Started Aug 16 04:35:40 PM PDT 24
Finished Aug 16 04:35:42 PM PDT 24
Peak memory 183876 kb
Host smart-a0deb97e-54be-4e08-9fb8-7e037ead1e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789296757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.789296757
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2564274505
Short name T421
Test name
Test status
Simulation time 310412881 ps
CPU time 2.59 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 198496 kb
Host smart-70981089-2314-4d63-8897-14f56be6c5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564274505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2564274505
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2917082778
Short name T382
Test name
Test status
Simulation time 3824739635 ps
CPU time 2.35 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:15 PM PDT 24
Peak memory 197872 kb
Host smart-32fbe714-aa95-4681-8365-ce7b590a2f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917082778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2917082778
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.232782449
Short name T411
Test name
Test status
Simulation time 286319393 ps
CPU time 0.94 seconds
Started Aug 16 04:35:35 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 183628 kb
Host smart-e8465e3c-a34a-4fb2-9c54-14443bfbfcc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232782449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.232782449
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2771045543
Short name T298
Test name
Test status
Simulation time 374258764 ps
CPU time 1.19 seconds
Started Aug 16 04:35:49 PM PDT 24
Finished Aug 16 04:35:50 PM PDT 24
Peak memory 183652 kb
Host smart-2fb65a21-c210-4487-b66a-e54a62353ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771045543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2771045543
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3857244788
Short name T307
Test name
Test status
Simulation time 480278700 ps
CPU time 0.7 seconds
Started Aug 16 04:35:17 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 192908 kb
Host smart-9532cf7a-3ae1-448e-8b69-0e9382f8e832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857244788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3857244788
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1205071377
Short name T376
Test name
Test status
Simulation time 429605533 ps
CPU time 0.8 seconds
Started Aug 16 04:35:43 PM PDT 24
Finished Aug 16 04:35:44 PM PDT 24
Peak memory 183704 kb
Host smart-6394f070-0bdb-4738-a091-292468c5f8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205071377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1205071377
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4066717233
Short name T426
Test name
Test status
Simulation time 339439334 ps
CPU time 0.72 seconds
Started Aug 16 04:35:43 PM PDT 24
Finished Aug 16 04:35:44 PM PDT 24
Peak memory 183660 kb
Host smart-7880e8a8-32d0-4f9f-9f79-898e9cb93baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066717233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4066717233
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.494034215
Short name T396
Test name
Test status
Simulation time 355087751 ps
CPU time 0.65 seconds
Started Aug 16 04:35:47 PM PDT 24
Finished Aug 16 04:35:48 PM PDT 24
Peak memory 192896 kb
Host smart-7396ed89-54e3-4d10-9069-1f02921af333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494034215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.494034215
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2056200630
Short name T334
Test name
Test status
Simulation time 379698381 ps
CPU time 0.69 seconds
Started Aug 16 04:35:45 PM PDT 24
Finished Aug 16 04:35:46 PM PDT 24
Peak memory 183936 kb
Host smart-33c4442c-0d86-4b08-8a3e-8082cd9c42fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056200630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2056200630
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.254700438
Short name T395
Test name
Test status
Simulation time 482487706 ps
CPU time 0.68 seconds
Started Aug 16 04:35:36 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 183672 kb
Host smart-25d003b8-462e-4110-b537-9069f2cb623b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254700438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.254700438
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.939933349
Short name T345
Test name
Test status
Simulation time 572580193 ps
CPU time 0.61 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183756 kb
Host smart-0f393ff3-0f37-4b1b-9da1-c182ba88b13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939933349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.939933349
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1357162499
Short name T363
Test name
Test status
Simulation time 412923349 ps
CPU time 1.18 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 183668 kb
Host smart-f0b8b704-9918-4d32-958c-b15ca341e08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357162499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1357162499
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.865321517
Short name T53
Test name
Test status
Simulation time 579649776 ps
CPU time 1.14 seconds
Started Aug 16 04:35:27 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 183660 kb
Host smart-28ed207f-0ba7-4977-8217-0749cefcf5af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865321517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.865321517
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2323439123
Short name T65
Test name
Test status
Simulation time 7080021652 ps
CPU time 20.2 seconds
Started Aug 16 04:35:33 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 192128 kb
Host smart-12f2fd49-8b18-42f6-8521-915a4fcfdf47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323439123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2323439123
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3007381832
Short name T414
Test name
Test status
Simulation time 1075467472 ps
CPU time 1.3 seconds
Started Aug 16 04:35:17 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 193260 kb
Host smart-753d6855-64dd-4c7e-8482-536865f1ee74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007381832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3007381832
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.531654849
Short name T385
Test name
Test status
Simulation time 544146810 ps
CPU time 0.89 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 198096 kb
Host smart-b2169d78-4357-468f-a80e-9842e430f563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531654849 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.531654849
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2875497713
Short name T410
Test name
Test status
Simulation time 461564205 ps
CPU time 1.24 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 191940 kb
Host smart-8ca0f062-3606-4e8d-9f04-62d4b5ac4a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875497713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2875497713
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1781304757
Short name T417
Test name
Test status
Simulation time 478133884 ps
CPU time 0.68 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 183740 kb
Host smart-2a5c0652-a03b-473a-b802-886ebf3c35d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781304757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1781304757
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.652492112
Short name T326
Test name
Test status
Simulation time 485655929 ps
CPU time 0.71 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:25 PM PDT 24
Peak memory 183612 kb
Host smart-5ba5a705-1bd0-45eb-86f2-421bf1b6105d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652492112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.652492112
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.918879073
Short name T407
Test name
Test status
Simulation time 314489028 ps
CPU time 0.97 seconds
Started Aug 16 04:35:29 PM PDT 24
Finished Aug 16 04:35:30 PM PDT 24
Peak memory 183592 kb
Host smart-7cf2952f-6a04-4c6d-ab3b-5805926505f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918879073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.918879073
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4269061586
Short name T68
Test name
Test status
Simulation time 1033378634 ps
CPU time 0.91 seconds
Started Aug 16 04:35:17 PM PDT 24
Finished Aug 16 04:35:18 PM PDT 24
Peak memory 183752 kb
Host smart-05707cb5-92e7-4600-acba-379edb284f69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269061586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4269061586
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1210052850
Short name T359
Test name
Test status
Simulation time 638098870 ps
CPU time 3.12 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 198480 kb
Host smart-a2f03769-7e71-41ae-97dd-8097edc1e201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210052850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1210052850
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.49769967
Short name T321
Test name
Test status
Simulation time 8412244419 ps
CPU time 13.61 seconds
Started Aug 16 04:35:14 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 198188 kb
Host smart-2e61f2e9-c4e6-417a-a02c-065ea00beff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49769967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_i
ntg_err.49769967
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4040290570
Short name T291
Test name
Test status
Simulation time 504326132 ps
CPU time 1.2 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 183664 kb
Host smart-730ee70a-2565-4b57-98be-01587559baa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040290570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4040290570
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.669152138
Short name T292
Test name
Test status
Simulation time 479890596 ps
CPU time 1.19 seconds
Started Aug 16 04:35:50 PM PDT 24
Finished Aug 16 04:35:52 PM PDT 24
Peak memory 192800 kb
Host smart-cc6f7269-bf48-49f2-9a66-accef1d993fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669152138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.669152138
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.608862971
Short name T375
Test name
Test status
Simulation time 456355737 ps
CPU time 1.23 seconds
Started Aug 16 04:35:56 PM PDT 24
Finished Aug 16 04:35:58 PM PDT 24
Peak memory 192896 kb
Host smart-178a3159-05ce-4429-89fa-2912245f44ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608862971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.608862971
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2338482061
Short name T393
Test name
Test status
Simulation time 500883688 ps
CPU time 0.71 seconds
Started Aug 16 04:35:30 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 192884 kb
Host smart-121c789e-4570-416e-990f-76834ec599a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338482061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2338482061
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.752981773
Short name T366
Test name
Test status
Simulation time 290270400 ps
CPU time 0.7 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:39 PM PDT 24
Peak memory 183768 kb
Host smart-9cb35c48-0167-4ba6-9e01-8e2f9bfb8076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752981773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.752981773
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2082089254
Short name T388
Test name
Test status
Simulation time 492402689 ps
CPU time 0.94 seconds
Started Aug 16 04:35:40 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 183660 kb
Host smart-35e396e7-6e15-4372-90f3-11fac181ad8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082089254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2082089254
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3920883613
Short name T370
Test name
Test status
Simulation time 448232586 ps
CPU time 0.7 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 183580 kb
Host smart-12fb944a-5516-444b-b724-209213f5b14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920883613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3920883613
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2308752396
Short name T404
Test name
Test status
Simulation time 323302401 ps
CPU time 1.03 seconds
Started Aug 16 04:35:46 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 192860 kb
Host smart-5e81fad9-611a-4c39-868d-ac0444bd4a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308752396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2308752396
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3170639834
Short name T340
Test name
Test status
Simulation time 437853625 ps
CPU time 0.74 seconds
Started Aug 16 04:35:47 PM PDT 24
Finished Aug 16 04:35:48 PM PDT 24
Peak memory 192828 kb
Host smart-4347d361-eebc-4c9a-b2f1-8b80f8ba6813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170639834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3170639834
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1365721057
Short name T400
Test name
Test status
Simulation time 520848346 ps
CPU time 0.64 seconds
Started Aug 16 04:35:46 PM PDT 24
Finished Aug 16 04:35:47 PM PDT 24
Peak memory 183680 kb
Host smart-671bb83c-7568-49af-abbe-9a54114ca3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365721057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1365721057
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.379471956
Short name T211
Test name
Test status
Simulation time 581710140 ps
CPU time 0.87 seconds
Started Aug 16 04:35:29 PM PDT 24
Finished Aug 16 04:35:30 PM PDT 24
Peak memory 196952 kb
Host smart-e0bb77ef-2024-412b-a539-69a37d0dbedc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379471956 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.379471956
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3681759941
Short name T67
Test name
Test status
Simulation time 332853155 ps
CPU time 0.7 seconds
Started Aug 16 04:35:40 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 193164 kb
Host smart-219f019b-296c-4c77-8d0c-ffb70748202d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681759941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3681759941
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2087906061
Short name T314
Test name
Test status
Simulation time 283634607 ps
CPU time 0.97 seconds
Started Aug 16 04:35:28 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 183656 kb
Host smart-6bf3e065-1089-4a7f-a99e-25bf504ddc6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087906061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2087906061
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1741239936
Short name T401
Test name
Test status
Simulation time 2231288733 ps
CPU time 3.14 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 194928 kb
Host smart-2f0623d0-5cc6-4ecb-9a1c-a98000d47a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741239936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1741239936
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3238859554
Short name T319
Test name
Test status
Simulation time 490778996 ps
CPU time 1.52 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 196728 kb
Host smart-040c9cc7-af96-43f2-a6e9-c6861330a1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238859554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3238859554
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2202316634
Short name T199
Test name
Test status
Simulation time 8758770131 ps
CPU time 4.28 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 198484 kb
Host smart-e54ace43-8d9d-458f-9076-b9ac7d327f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202316634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2202316634
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3482022569
Short name T381
Test name
Test status
Simulation time 433718208 ps
CPU time 1.29 seconds
Started Aug 16 04:35:48 PM PDT 24
Finished Aug 16 04:35:50 PM PDT 24
Peak memory 195884 kb
Host smart-b380aff7-f7fc-418f-a267-9c8683fda32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482022569 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3482022569
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.712843060
Short name T409
Test name
Test status
Simulation time 431031210 ps
CPU time 1.14 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 192960 kb
Host smart-1ecd4db9-5306-4076-b57c-20452f095003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712843060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.712843060
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3099392436
Short name T294
Test name
Test status
Simulation time 285494915 ps
CPU time 0.92 seconds
Started Aug 16 04:35:31 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 183680 kb
Host smart-05a6c6b8-842d-4024-b437-237e43f0acfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099392436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3099392436
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1115890808
Short name T72
Test name
Test status
Simulation time 2505347635 ps
CPU time 1.05 seconds
Started Aug 16 04:35:33 PM PDT 24
Finished Aug 16 04:35:34 PM PDT 24
Peak memory 195076 kb
Host smart-acd77e7f-c659-407a-8afa-9ca01832404b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115890808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1115890808
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4292732996
Short name T352
Test name
Test status
Simulation time 528706008 ps
CPU time 1.54 seconds
Started Aug 16 04:35:39 PM PDT 24
Finished Aug 16 04:35:40 PM PDT 24
Peak memory 198464 kb
Host smart-b9cccc11-1a71-4b6e-8f24-16ce00bea281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292732996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4292732996
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.57055038
Short name T420
Test name
Test status
Simulation time 8361790312 ps
CPU time 3.9 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 198384 kb
Host smart-b003236e-e7a9-473b-8f59-5e3eb1573827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57055038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_i
ntg_err.57055038
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4188770175
Short name T40
Test name
Test status
Simulation time 483984625 ps
CPU time 1.3 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 195992 kb
Host smart-29606cdb-0853-4051-af34-b207ce0e33b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188770175 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4188770175
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3352505685
Short name T347
Test name
Test status
Simulation time 403178995 ps
CPU time 0.86 seconds
Started Aug 16 04:35:19 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 192992 kb
Host smart-01612c76-5fed-41fc-9f7b-7b8158ab2fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352505685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3352505685
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2886020309
Short name T306
Test name
Test status
Simulation time 354301374 ps
CPU time 0.66 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 183644 kb
Host smart-f17b74f7-f674-444e-995d-ce16d9ea18a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886020309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2886020309
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.280119080
Short name T369
Test name
Test status
Simulation time 2068613316 ps
CPU time 1.66 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 193856 kb
Host smart-ea5a3375-08f4-45af-8be6-5007e6f1cb16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280119080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.280119080
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.56807825
Short name T320
Test name
Test status
Simulation time 419235486 ps
CPU time 1.35 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 198316 kb
Host smart-edccb1a1-2375-4696-8b67-84401cdfa76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56807825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.56807825
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3502092381
Short name T408
Test name
Test status
Simulation time 322258348 ps
CPU time 0.75 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 195260 kb
Host smart-f1b1d1b6-860c-4323-b94d-556a4d05a519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502092381 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3502092381
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1695751787
Short name T52
Test name
Test status
Simulation time 382385072 ps
CPU time 1.11 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 193972 kb
Host smart-2379d725-16c6-4028-ace9-95e3ca49e52b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695751787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1695751787
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.280790534
Short name T327
Test name
Test status
Simulation time 446325821 ps
CPU time 1.17 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183668 kb
Host smart-54c701c6-6c49-40a2-ac07-b2da51956a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280790534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.280790534
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1613346595
Short name T356
Test name
Test status
Simulation time 2974218899 ps
CPU time 2.66 seconds
Started Aug 16 04:35:30 PM PDT 24
Finished Aug 16 04:35:38 PM PDT 24
Peak memory 195544 kb
Host smart-bd392f76-f2d3-4fed-acc3-5e911dc7b8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613346595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1613346595
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2656947021
Short name T309
Test name
Test status
Simulation time 769802650 ps
CPU time 1.83 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 198600 kb
Host smart-96eced7d-79cd-471b-a841-0fc5b6d011f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656947021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2656947021
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4018572878
Short name T349
Test name
Test status
Simulation time 8080475005 ps
CPU time 2.94 seconds
Started Aug 16 04:35:38 PM PDT 24
Finished Aug 16 04:35:41 PM PDT 24
Peak memory 198276 kb
Host smart-a257a738-dac0-4f3a-9c2b-090c31d46f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018572878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4018572878
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4229634420
Short name T331
Test name
Test status
Simulation time 477094242 ps
CPU time 1.06 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 198308 kb
Host smart-1c900261-5fdb-4cdd-a1f9-bb7580597568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229634420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4229634420
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2810248702
Short name T423
Test name
Test status
Simulation time 496851819 ps
CPU time 0.64 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 191964 kb
Host smart-2d1316bd-3359-48c0-94b2-8f0855487e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810248702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2810248702
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.950503316
Short name T380
Test name
Test status
Simulation time 465343680 ps
CPU time 0.67 seconds
Started Aug 16 04:35:15 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 183656 kb
Host smart-3999cdf6-e9da-4b55-8abf-90f1b553e77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950503316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.950503316
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4113866083
Short name T348
Test name
Test status
Simulation time 1256498120 ps
CPU time 1.08 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:24 PM PDT 24
Peak memory 192868 kb
Host smart-e75a9aa1-9a35-4c04-b2a4-aadc8d8e6ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113866083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4113866083
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1437805293
Short name T338
Test name
Test status
Simulation time 511413811 ps
CPU time 2 seconds
Started Aug 16 04:35:34 PM PDT 24
Finished Aug 16 04:35:36 PM PDT 24
Peak memory 198564 kb
Host smart-ed66380f-6c00-4406-bf0b-004975ca0b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437805293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1437805293
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2578463189
Short name T360
Test name
Test status
Simulation time 8122910557 ps
CPU time 13.81 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:35:32 PM PDT 24
Peak memory 198128 kb
Host smart-b23699dc-ab33-4584-b2f1-d887b371c165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578463189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2578463189
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1747781537
Short name T245
Test name
Test status
Simulation time 12811395530 ps
CPU time 3.16 seconds
Started Aug 16 04:34:32 PM PDT 24
Finished Aug 16 04:34:36 PM PDT 24
Peak memory 192068 kb
Host smart-6e8d0355-9015-4002-bd0b-720eb464181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747781537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1747781537
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3558158236
Short name T250
Test name
Test status
Simulation time 449033286 ps
CPU time 1.23 seconds
Started Aug 16 04:34:37 PM PDT 24
Finished Aug 16 04:34:38 PM PDT 24
Peak memory 191992 kb
Host smart-00b6f348-072d-46e6-afb8-00ae3a4f0488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558158236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3558158236
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2782656290
Short name T19
Test name
Test status
Simulation time 35351140036 ps
CPU time 7.41 seconds
Started Aug 16 04:34:40 PM PDT 24
Finished Aug 16 04:34:47 PM PDT 24
Peak memory 197080 kb
Host smart-f9e5ee34-d85f-49c0-8969-8fedecfe7a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782656290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2782656290
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2801282008
Short name T14
Test name
Test status
Simulation time 9451622751 ps
CPU time 1.42 seconds
Started Aug 16 04:34:55 PM PDT 24
Finished Aug 16 04:34:57 PM PDT 24
Peak memory 216104 kb
Host smart-6be8b604-e180-443e-becf-47db77c6dfef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801282008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2801282008
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1324919743
Short name T285
Test name
Test status
Simulation time 443545864 ps
CPU time 1.29 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:34:55 PM PDT 24
Peak memory 191964 kb
Host smart-8ea8d0ed-a729-41ae-81d9-942fd7632483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324919743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1324919743
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.768204610
Short name T202
Test name
Test status
Simulation time 3211192355 ps
CPU time 14.93 seconds
Started Aug 16 04:34:33 PM PDT 24
Finished Aug 16 04:34:48 PM PDT 24
Peak memory 198628 kb
Host smart-000d01ca-a61d-482a-acb4-2e93978cafbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768204610 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.768204610
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3576255767
Short name T203
Test name
Test status
Simulation time 12758921519 ps
CPU time 7.88 seconds
Started Aug 16 04:35:01 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 197056 kb
Host smart-a2cb701e-7d25-478f-a25c-985fe5002c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576255767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3576255767
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1367978081
Short name T246
Test name
Test status
Simulation time 381641628 ps
CPU time 1.06 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:34:54 PM PDT 24
Peak memory 192016 kb
Host smart-d5f1fd38-9ef7-45e1-b752-484f6dadca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367978081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1367978081
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.109296104
Short name T270
Test name
Test status
Simulation time 2901309554 ps
CPU time 19.63 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 206896 kb
Host smart-03cd8aef-6867-4c15-a60f-d58214967c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109296104 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.109296104
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.772956045
Short name T190
Test name
Test status
Simulation time 635837794 ps
CPU time 0.72 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 196780 kb
Host smart-b8d74f66-80a5-4d05-bb1d-5d5ea83f1b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772956045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.772956045
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.7716330
Short name T241
Test name
Test status
Simulation time 32817514293 ps
CPU time 51.95 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:35:49 PM PDT 24
Peak memory 197056 kb
Host smart-ca0ebdc3-c821-4820-9e6a-584dbf45c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7716330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.7716330
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1366715407
Short name T257
Test name
Test status
Simulation time 553062534 ps
CPU time 1.51 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 192008 kb
Host smart-8cdc7c5c-2055-477f-b431-30c1ae4373df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366715407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1366715407
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.226103566
Short name T21
Test name
Test status
Simulation time 32342643277 ps
CPU time 3.15 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 192064 kb
Host smart-02e5dea6-0982-4a37-af9b-7868477c48c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226103566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.226103566
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2169509761
Short name T289
Test name
Test status
Simulation time 514199742 ps
CPU time 0.76 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:34:52 PM PDT 24
Peak memory 191972 kb
Host smart-2ee2a08a-6c6f-45eb-bb2d-bee1a77e79e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169509761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2169509761
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1315617760
Short name T264
Test name
Test status
Simulation time 27825206836 ps
CPU time 38.61 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 192060 kb
Host smart-fc05174c-d62a-4dee-b3d3-be07a5c5b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315617760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1315617760
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3120182494
Short name T213
Test name
Test status
Simulation time 604543051 ps
CPU time 1.05 seconds
Started Aug 16 04:34:48 PM PDT 24
Finished Aug 16 04:34:49 PM PDT 24
Peak memory 196804 kb
Host smart-4c825265-a63b-474c-a9e2-142b99164dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120182494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3120182494
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3336197167
Short name T230
Test name
Test status
Simulation time 40798908247 ps
CPU time 61.85 seconds
Started Aug 16 04:34:47 PM PDT 24
Finished Aug 16 04:35:49 PM PDT 24
Peak memory 192060 kb
Host smart-0f41df2a-efb3-4bb6-971b-9e081fab80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336197167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3336197167
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2775491113
Short name T276
Test name
Test status
Simulation time 448121967 ps
CPU time 1.21 seconds
Started Aug 16 04:34:54 PM PDT 24
Finished Aug 16 04:34:55 PM PDT 24
Peak memory 192016 kb
Host smart-7a19be63-a345-43d4-b7c1-bfddc59346a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775491113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2775491113
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2660786350
Short name T249
Test name
Test status
Simulation time 41522270553 ps
CPU time 59.51 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:35:56 PM PDT 24
Peak memory 192004 kb
Host smart-22a174a0-851d-40f3-8c20-423b48f8d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660786350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2660786350
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2688729973
Short name T242
Test name
Test status
Simulation time 612919091 ps
CPU time 1.52 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:34:53 PM PDT 24
Peak memory 196784 kb
Host smart-cfbcdeb1-8e47-4792-8174-6fe3d351b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688729973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2688729973
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1475266477
Short name T240
Test name
Test status
Simulation time 39795284902 ps
CPU time 60.83 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 197064 kb
Host smart-80232b93-2384-41c7-bed9-711978413869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475266477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1475266477
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3151415957
Short name T288
Test name
Test status
Simulation time 483777520 ps
CPU time 0.87 seconds
Started Aug 16 04:34:50 PM PDT 24
Finished Aug 16 04:34:51 PM PDT 24
Peak memory 196800 kb
Host smart-995549c2-28e7-4666-86ba-1ec2c217aaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151415957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3151415957
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3597798556
Short name T3
Test name
Test status
Simulation time 13841162630 ps
CPU time 4.48 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:34:50 PM PDT 24
Peak memory 197080 kb
Host smart-644bcc58-5606-4b42-a127-0a8cb9412c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597798556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3597798556
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1681308002
Short name T226
Test name
Test status
Simulation time 528039784 ps
CPU time 0.98 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:34:44 PM PDT 24
Peak memory 191996 kb
Host smart-76c3a037-8a38-495f-83ee-ff81a37a7109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681308002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1681308002
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4116732450
Short name T237
Test name
Test status
Simulation time 34311354153 ps
CPU time 12.52 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 196980 kb
Host smart-a255e1b2-16f0-451e-a43f-044dd54d122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116732450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4116732450
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.420403978
Short name T268
Test name
Test status
Simulation time 457866812 ps
CPU time 0.88 seconds
Started Aug 16 04:34:55 PM PDT 24
Finished Aug 16 04:34:56 PM PDT 24
Peak memory 191996 kb
Host smart-b5add4c3-4869-4dcb-b439-2793980a4b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420403978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.420403978
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1465811014
Short name T248
Test name
Test status
Simulation time 3058670031 ps
CPU time 1.53 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:06 PM PDT 24
Peak memory 192068 kb
Host smart-3b55f767-739a-49cc-a3d8-8577074a6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465811014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1465811014
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1351224565
Short name T284
Test name
Test status
Simulation time 469151940 ps
CPU time 0.66 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:00 PM PDT 24
Peak memory 191996 kb
Host smart-0ede337a-9e55-4e1a-b722-e89cdb391968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351224565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1351224565
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.759750399
Short name T208
Test name
Test status
Simulation time 36229048311 ps
CPU time 14.78 seconds
Started Aug 16 04:34:50 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 192068 kb
Host smart-f5871fac-bb8c-403f-bbeb-e41cb33d2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759750399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.759750399
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3603660246
Short name T15
Test name
Test status
Simulation time 4084562195 ps
CPU time 2.13 seconds
Started Aug 16 04:34:47 PM PDT 24
Finished Aug 16 04:34:49 PM PDT 24
Peak memory 215604 kb
Host smart-f82b588a-78c2-4388-b55d-80ea352bd5ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603660246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3603660246
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1606331861
Short name T219
Test name
Test status
Simulation time 493058523 ps
CPU time 0.71 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:34:54 PM PDT 24
Peak memory 196732 kb
Host smart-1c8d22db-6aa4-48b8-b488-4e14e2dec116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606331861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1606331861
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1120455096
Short name T193
Test name
Test status
Simulation time 123494468643 ps
CPU time 164.7 seconds
Started Aug 16 04:34:33 PM PDT 24
Finished Aug 16 04:37:17 PM PDT 24
Peak memory 191972 kb
Host smart-a6384e62-9650-44e8-bf0e-22e9fe48fbc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120455096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1120455096
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1148604169
Short name T22
Test name
Test status
Simulation time 21905623948 ps
CPU time 6.89 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:35:03 PM PDT 24
Peak memory 192140 kb
Host smart-ace38735-e8d0-4623-9dbb-1f2764a4733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148604169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1148604169
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1675019637
Short name T238
Test name
Test status
Simulation time 503529118 ps
CPU time 0.77 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:34:58 PM PDT 24
Peak memory 196756 kb
Host smart-ae5c928c-993a-4c0b-b958-9843cdf441ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675019637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1675019637
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2599641580
Short name T225
Test name
Test status
Simulation time 12266462323 ps
CPU time 16.2 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:37 PM PDT 24
Peak memory 197044 kb
Host smart-46e79f9e-57e2-4e65-bbb2-36b6ac798233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599641580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2599641580
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4127001438
Short name T222
Test name
Test status
Simulation time 504324591 ps
CPU time 0.75 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:34:58 PM PDT 24
Peak memory 191968 kb
Host smart-30be645b-28e5-49ea-bbc1-7eef268a1bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127001438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4127001438
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2732665522
Short name T50
Test name
Test status
Simulation time 20080532883 ps
CPU time 25.02 seconds
Started Aug 16 04:34:58 PM PDT 24
Finished Aug 16 04:35:23 PM PDT 24
Peak memory 192068 kb
Host smart-adb48f85-64cb-4775-865b-bfc08a682742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732665522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2732665522
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3562091083
Short name T6
Test name
Test status
Simulation time 409209141 ps
CPU time 0.88 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:34:57 PM PDT 24
Peak memory 196708 kb
Host smart-a03a0c1d-463f-4046-b896-b9dada8a857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562091083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3562091083
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.318136322
Short name T282
Test name
Test status
Simulation time 14199130902 ps
CPU time 2.43 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 197044 kb
Host smart-b1e94180-f0c0-46f4-a36c-08bb73edb700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318136322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.318136322
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.936304057
Short name T224
Test name
Test status
Simulation time 410263062 ps
CPU time 1.17 seconds
Started Aug 16 04:35:00 PM PDT 24
Finished Aug 16 04:35:02 PM PDT 24
Peak memory 191928 kb
Host smart-b98042d3-3f59-4561-98f7-81778f08f4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936304057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.936304057
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1733112342
Short name T235
Test name
Test status
Simulation time 61907541097 ps
CPU time 10.7 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 192056 kb
Host smart-b3e0fcfd-c9c3-437f-90cb-48b754fc57e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733112342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1733112342
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1966616098
Short name T272
Test name
Test status
Simulation time 380092676 ps
CPU time 1.1 seconds
Started Aug 16 04:34:52 PM PDT 24
Finished Aug 16 04:34:53 PM PDT 24
Peak memory 192044 kb
Host smart-53e3029e-df58-441e-ab30-67bd437fc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966616098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1966616098
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.817974368
Short name T251
Test name
Test status
Simulation time 2768769349 ps
CPU time 0.89 seconds
Started Aug 16 04:34:57 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 196840 kb
Host smart-63d91193-669a-4459-9b67-a43e52bcab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817974368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.817974368
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1178624280
Short name T266
Test name
Test status
Simulation time 576648813 ps
CPU time 0.62 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:06 PM PDT 24
Peak memory 196772 kb
Host smart-65940a02-a1c1-431a-8aa2-ee0665877297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178624280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1178624280
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4124270202
Short name T191
Test name
Test status
Simulation time 2455296232 ps
CPU time 15.07 seconds
Started Aug 16 04:34:49 PM PDT 24
Finished Aug 16 04:35:04 PM PDT 24
Peak memory 206848 kb
Host smart-4034a506-5d1d-4fdc-ac97-0c42dcd3c0a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124270202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4124270202
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2346675268
Short name T24
Test name
Test status
Simulation time 4973184812 ps
CPU time 2.48 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:34:59 PM PDT 24
Peak memory 192040 kb
Host smart-4f46c369-02f4-444d-ae39-eba8998b49c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346675268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2346675268
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3047381515
Short name T247
Test name
Test status
Simulation time 591046205 ps
CPU time 0.76 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 191976 kb
Host smart-b789044b-d6b7-40c9-8050-926659bdaeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047381515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3047381515
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2953966639
Short name T271
Test name
Test status
Simulation time 34700288317 ps
CPU time 25.94 seconds
Started Aug 16 04:35:16 PM PDT 24
Finished Aug 16 04:35:42 PM PDT 24
Peak memory 197104 kb
Host smart-f9acb43a-db26-48fc-a9e6-f91490094e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953966639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2953966639
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1371280706
Short name T155
Test name
Test status
Simulation time 675193416 ps
CPU time 0.65 seconds
Started Aug 16 04:35:04 PM PDT 24
Finished Aug 16 04:35:05 PM PDT 24
Peak memory 192080 kb
Host smart-3287fac5-467a-466f-92ab-72e0b88833d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371280706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1371280706
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3792222466
Short name T259
Test name
Test status
Simulation time 23993469648 ps
CPU time 36.77 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 192076 kb
Host smart-4d5c74c8-c121-48ba-8872-3d5a486bdeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792222466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3792222466
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3763616353
Short name T233
Test name
Test status
Simulation time 578689165 ps
CPU time 0.68 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 196824 kb
Host smart-9079abeb-341d-42f7-9b44-ef1382ea3cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763616353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3763616353
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.961729856
Short name T1
Test name
Test status
Simulation time 59586710307 ps
CPU time 20.97 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:31 PM PDT 24
Peak memory 197164 kb
Host smart-cf229bc2-37f8-4643-9a50-f94cc9a2e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961729856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.961729856
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3023925131
Short name T279
Test name
Test status
Simulation time 336048178 ps
CPU time 1.07 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 196808 kb
Host smart-de431960-f76f-433a-adc2-d59977cd999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023925131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3023925131
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2348432608
Short name T182
Test name
Test status
Simulation time 578981082 ps
CPU time 1.32 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:34:46 PM PDT 24
Peak memory 196876 kb
Host smart-69d5b222-e33b-4f1f-bf77-1c3662d663dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348432608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2348432608
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.4232583150
Short name T286
Test name
Test status
Simulation time 59657842591 ps
CPU time 55.64 seconds
Started Aug 16 04:34:49 PM PDT 24
Finished Aug 16 04:35:45 PM PDT 24
Peak memory 192072 kb
Host smart-082fe889-9daa-4df8-9fed-5d8f9d8cc484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232583150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4232583150
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3121085480
Short name T17
Test name
Test status
Simulation time 3887480727 ps
CPU time 6.83 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:35:03 PM PDT 24
Peak memory 215648 kb
Host smart-03e5e9b9-6f4b-4b4c-a485-44c2be2be2d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121085480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3121085480
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3985089197
Short name T215
Test name
Test status
Simulation time 541980013 ps
CPU time 0.83 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:34:46 PM PDT 24
Peak memory 191944 kb
Host smart-20205527-6a0e-46a2-9d69-d37da5f1fe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985089197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3985089197
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4025900021
Short name T206
Test name
Test status
Simulation time 43758795824 ps
CPU time 61.9 seconds
Started Aug 16 04:35:10 PM PDT 24
Finished Aug 16 04:36:22 PM PDT 24
Peak memory 192028 kb
Host smart-df490989-fd9f-4eef-9944-58c2fa2423da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025900021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4025900021
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.99307996
Short name T255
Test name
Test status
Simulation time 578111639 ps
CPU time 1.4 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:07 PM PDT 24
Peak memory 196776 kb
Host smart-94f0c62e-ca16-4103-9090-ec77715ad360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99307996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.99307996
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1609687009
Short name T201
Test name
Test status
Simulation time 3760133996 ps
CPU time 3.01 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 192068 kb
Host smart-4c2302e0-68d4-4de4-a2b2-2be921ad67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609687009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1609687009
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1743203375
Short name T280
Test name
Test status
Simulation time 398079521 ps
CPU time 1.13 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 192020 kb
Host smart-397a5998-a849-4ed6-8a49-b28cba08d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743203375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1743203375
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2686387814
Short name T278
Test name
Test status
Simulation time 53496692754 ps
CPU time 74.53 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:36:20 PM PDT 24
Peak memory 192064 kb
Host smart-6f9b068d-30ce-4a1d-9615-3d794a39be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686387814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2686387814
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.303752630
Short name T229
Test name
Test status
Simulation time 480263694 ps
CPU time 0.79 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 192028 kb
Host smart-59a11d5d-fd5a-43fa-be68-54bf0b79063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303752630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.303752630
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2532735712
Short name T262
Test name
Test status
Simulation time 42375105382 ps
CPU time 5.39 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 192160 kb
Host smart-d3d3503c-838c-4787-9aa8-90c03bf65bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532735712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2532735712
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3255941222
Short name T228
Test name
Test status
Simulation time 563346631 ps
CPU time 0.82 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:07 PM PDT 24
Peak memory 191996 kb
Host smart-74c40611-7a91-4aaf-ab77-4cce11c6b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255941222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3255941222
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.862661021
Short name T275
Test name
Test status
Simulation time 30114388131 ps
CPU time 47.35 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:55 PM PDT 24
Peak memory 197064 kb
Host smart-69a39793-60fa-40c3-8bfa-6efb8df81c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862661021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.862661021
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.964192307
Short name T23
Test name
Test status
Simulation time 585328144 ps
CPU time 0.77 seconds
Started Aug 16 04:35:03 PM PDT 24
Finished Aug 16 04:35:04 PM PDT 24
Peak memory 191952 kb
Host smart-4de7ddbe-098b-41d3-8712-d7fb351e89fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964192307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.964192307
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3076070087
Short name T205
Test name
Test status
Simulation time 27424185423 ps
CPU time 20.1 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 192068 kb
Host smart-ad7fdd73-ebf8-445a-a496-5075579c52bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076070087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3076070087
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3647342820
Short name T267
Test name
Test status
Simulation time 552240151 ps
CPU time 0.66 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 191968 kb
Host smart-b1786362-508e-45c5-bef5-d61b4e9e9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647342820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3647342820
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3977927016
Short name T253
Test name
Test status
Simulation time 2209731038 ps
CPU time 7.08 seconds
Started Aug 16 04:35:02 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 199128 kb
Host smart-923fd467-4f68-4164-b018-ee81a9be0ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977927016 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3977927016
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2059682294
Short name T274
Test name
Test status
Simulation time 19498201353 ps
CPU time 7.67 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:35:16 PM PDT 24
Peak memory 192064 kb
Host smart-81bedb12-47db-4dcc-9488-04ea49960b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059682294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2059682294
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1531057615
Short name T214
Test name
Test status
Simulation time 461429844 ps
CPU time 1.22 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 191996 kb
Host smart-5e7f4396-ece1-4084-92a8-e7f40323a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531057615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1531057615
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2203983211
Short name T261
Test name
Test status
Simulation time 34523298084 ps
CPU time 50.08 seconds
Started Aug 16 04:35:24 PM PDT 24
Finished Aug 16 04:36:14 PM PDT 24
Peak memory 192068 kb
Host smart-e666a48a-b74f-4687-b608-1ca957e81780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203983211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2203983211
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3241542862
Short name T200
Test name
Test status
Simulation time 531908332 ps
CPU time 0.84 seconds
Started Aug 16 04:35:05 PM PDT 24
Finished Aug 16 04:35:06 PM PDT 24
Peak memory 191976 kb
Host smart-ef7aee75-d78a-4609-8711-671932b5bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241542862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3241542862
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2757704192
Short name T74
Test name
Test status
Simulation time 3259627484 ps
CPU time 20.29 seconds
Started Aug 16 04:35:22 PM PDT 24
Finished Aug 16 04:35:43 PM PDT 24
Peak memory 206888 kb
Host smart-196af2cf-8960-4e38-b8c8-3f5fee2e2824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757704192 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2757704192
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1630777260
Short name T207
Test name
Test status
Simulation time 29369701798 ps
CPU time 42.44 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:36:01 PM PDT 24
Peak memory 192060 kb
Host smart-54dc997b-6ee0-4da5-ac4b-c7f0d8bd8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630777260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1630777260
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2631441212
Short name T212
Test name
Test status
Simulation time 431544871 ps
CPU time 1.26 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 192000 kb
Host smart-9d2004db-e606-4386-b63d-71e1ae71fa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631441212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2631441212
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2033578166
Short name T223
Test name
Test status
Simulation time 12084387293 ps
CPU time 15.33 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:28 PM PDT 24
Peak memory 191996 kb
Host smart-09d947e2-a2df-44e4-b299-c4ab57b39953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033578166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2033578166
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3649586232
Short name T217
Test name
Test status
Simulation time 628808742 ps
CPU time 0.81 seconds
Started Aug 16 04:35:07 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 196792 kb
Host smart-e4d1813d-341f-4388-a951-aa00d2e50e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649586232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3649586232
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4147339913
Short name T216
Test name
Test status
Simulation time 13966955742 ps
CPU time 8.17 seconds
Started Aug 16 04:34:59 PM PDT 24
Finished Aug 16 04:35:08 PM PDT 24
Peak memory 192072 kb
Host smart-4927bd17-afd1-4b2c-9d44-1ce147d4ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147339913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4147339913
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1511193700
Short name T16
Test name
Test status
Simulation time 3839935662 ps
CPU time 5.9 seconds
Started Aug 16 04:34:46 PM PDT 24
Finished Aug 16 04:34:52 PM PDT 24
Peak memory 215720 kb
Host smart-8066b5e4-5068-4f01-840a-e22719fa7b09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511193700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1511193700
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3615527989
Short name T48
Test name
Test status
Simulation time 435424239 ps
CPU time 0.94 seconds
Started Aug 16 04:34:56 PM PDT 24
Finished Aug 16 04:34:57 PM PDT 24
Peak memory 192012 kb
Host smart-6fab38f4-66e0-4854-aa3e-96385fedabae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615527989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3615527989
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.795326611
Short name T260
Test name
Test status
Simulation time 35424157900 ps
CPU time 22.77 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:34 PM PDT 24
Peak memory 191988 kb
Host smart-78ce8032-221c-4ff5-8707-b12fdbe4a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795326611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.795326611
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2102409513
Short name T252
Test name
Test status
Simulation time 425197323 ps
CPU time 0.6 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 196880 kb
Host smart-7248b592-693b-4386-a99c-135d68f60845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102409513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2102409513
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.757358408
Short name T181
Test name
Test status
Simulation time 435075101 ps
CPU time 0.83 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:11 PM PDT 24
Peak memory 196696 kb
Host smart-2c53d8bf-552f-474c-a7d8-1b33635cdd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757358408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.757358408
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3591514067
Short name T26
Test name
Test status
Simulation time 46734643500 ps
CPU time 4.16 seconds
Started Aug 16 04:35:04 PM PDT 24
Finished Aug 16 04:35:09 PM PDT 24
Peak memory 192068 kb
Host smart-7221368b-a1e3-4a51-b5b1-f88591895135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591514067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3591514067
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.193764728
Short name T277
Test name
Test status
Simulation time 484698924 ps
CPU time 0.77 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 191960 kb
Host smart-88895e49-a6f1-44ba-90b1-6115a2179ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193764728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.193764728
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3622744762
Short name T263
Test name
Test status
Simulation time 17103454618 ps
CPU time 20.08 seconds
Started Aug 16 04:35:06 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 192064 kb
Host smart-a135283b-a7e1-4500-b6c7-0fb0f40e8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622744762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3622744762
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.483774557
Short name T265
Test name
Test status
Simulation time 542160482 ps
CPU time 1.41 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:35:19 PM PDT 24
Peak memory 196844 kb
Host smart-8e8207dc-1d81-456d-876a-d2c5896bc8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483774557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.483774557
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4190497460
Short name T243
Test name
Test status
Simulation time 11185210936 ps
CPU time 8.68 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:22 PM PDT 24
Peak memory 197056 kb
Host smart-17bf1e54-999f-4223-ab4f-9dc6a8da8c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190497460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4190497460
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.367672902
Short name T244
Test name
Test status
Simulation time 552423995 ps
CPU time 0.96 seconds
Started Aug 16 04:35:13 PM PDT 24
Finished Aug 16 04:35:14 PM PDT 24
Peak memory 191916 kb
Host smart-8c835cdc-eb94-4b46-890f-83cdd110e6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367672902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.367672902
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.170459564
Short name T8
Test name
Test status
Simulation time 15890213535 ps
CPU time 7.09 seconds
Started Aug 16 04:35:20 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 192060 kb
Host smart-5835fd51-453c-487d-ac6d-e85f7f7a5a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170459564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.170459564
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2577655388
Short name T227
Test name
Test status
Simulation time 549461029 ps
CPU time 0.75 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:13 PM PDT 24
Peak memory 192056 kb
Host smart-90ac70ee-8912-4885-90e5-4084922ddc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577655388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2577655388
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2696704927
Short name T287
Test name
Test status
Simulation time 56646525346 ps
CPU time 79.03 seconds
Started Aug 16 04:35:08 PM PDT 24
Finished Aug 16 04:36:27 PM PDT 24
Peak memory 196980 kb
Host smart-2cabed5d-6e14-40a6-9445-68a0c98cc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696704927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2696704927
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4279293652
Short name T218
Test name
Test status
Simulation time 327932765 ps
CPU time 1.07 seconds
Started Aug 16 04:35:09 PM PDT 24
Finished Aug 16 04:35:10 PM PDT 24
Peak memory 192016 kb
Host smart-0c6879eb-d69b-4f0b-8249-1be4dd28b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279293652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4279293652
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.452917954
Short name T231
Test name
Test status
Simulation time 59924728936 ps
CPU time 25.07 seconds
Started Aug 16 04:35:21 PM PDT 24
Finished Aug 16 04:35:51 PM PDT 24
Peak memory 192040 kb
Host smart-ed26ad62-c025-4db4-b225-d388e984a329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452917954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.452917954
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2689230948
Short name T281
Test name
Test status
Simulation time 642719720 ps
CPU time 0.64 seconds
Started Aug 16 04:35:19 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 191936 kb
Host smart-2cc96574-3fa5-4f99-ba9c-25a88d690a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689230948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2689230948
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3840195140
Short name T204
Test name
Test status
Simulation time 10272871419 ps
CPU time 3.12 seconds
Started Aug 16 04:35:18 PM PDT 24
Finished Aug 16 04:35:21 PM PDT 24
Peak memory 192040 kb
Host smart-e90bdadd-13be-4773-a346-847f806ce29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840195140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3840195140
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1547550351
Short name T7
Test name
Test status
Simulation time 526514700 ps
CPU time 0.76 seconds
Started Aug 16 04:35:11 PM PDT 24
Finished Aug 16 04:35:12 PM PDT 24
Peak memory 192016 kb
Host smart-97da281a-6e31-47b2-8333-e1330901d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547550351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1547550351
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.835243146
Short name T234
Test name
Test status
Simulation time 2787926838 ps
CPU time 4.55 seconds
Started Aug 16 04:35:12 PM PDT 24
Finished Aug 16 04:35:17 PM PDT 24
Peak memory 196840 kb
Host smart-9021286f-94c5-4354-b038-15e622298c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835243146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.835243146
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3923084225
Short name T239
Test name
Test status
Simulation time 564069466 ps
CPU time 0.76 seconds
Started Aug 16 04:35:28 PM PDT 24
Finished Aug 16 04:35:29 PM PDT 24
Peak memory 191932 kb
Host smart-dfe084ed-2fd4-4a41-83c3-cd247647e972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923084225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3923084225
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1592664932
Short name T273
Test name
Test status
Simulation time 7963230592 ps
CPU time 6.13 seconds
Started Aug 16 04:35:14 PM PDT 24
Finished Aug 16 04:35:20 PM PDT 24
Peak memory 192068 kb
Host smart-2101b206-3dae-46b3-acdf-95b2620166f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592664932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1592664932
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.833987865
Short name T283
Test name
Test status
Simulation time 499863196 ps
CPU time 0.62 seconds
Started Aug 16 04:35:26 PM PDT 24
Finished Aug 16 04:35:27 PM PDT 24
Peak memory 191968 kb
Host smart-b84700db-aa0f-46a9-b920-2125e1d5be70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833987865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.833987865
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3506607343
Short name T232
Test name
Test status
Simulation time 41157466716 ps
CPU time 13.97 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:34:56 PM PDT 24
Peak memory 192064 kb
Host smart-38326df0-a566-47e3-863c-a79c7b9eb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506607343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3506607343
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2276869609
Short name T220
Test name
Test status
Simulation time 524046453 ps
CPU time 0.93 seconds
Started Aug 16 04:34:51 PM PDT 24
Finished Aug 16 04:34:53 PM PDT 24
Peak memory 196820 kb
Host smart-7ae01bfe-a6fb-44ed-81ff-56ea0fd02aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276869609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2276869609
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3193795762
Short name T41
Test name
Test status
Simulation time 41145143390 ps
CPU time 16.85 seconds
Started Aug 16 04:34:44 PM PDT 24
Finished Aug 16 04:35:01 PM PDT 24
Peak memory 197076 kb
Host smart-6a37f37b-a44d-4ed5-bd89-2a6bb8eb53ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193795762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3193795762
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2966318585
Short name T256
Test name
Test status
Simulation time 528855252 ps
CPU time 0.92 seconds
Started Aug 16 04:34:53 PM PDT 24
Finished Aug 16 04:34:54 PM PDT 24
Peak memory 191932 kb
Host smart-5329cf87-3565-4421-9ba9-6fb251e71bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966318585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2966318585
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2578815951
Short name T177
Test name
Test status
Simulation time 579369440 ps
CPU time 1.51 seconds
Started Aug 16 04:34:55 PM PDT 24
Finished Aug 16 04:34:57 PM PDT 24
Peak memory 196784 kb
Host smart-45d384ff-b18b-439f-b8d4-2eba610a77d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578815951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2578815951
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2361406721
Short name T236
Test name
Test status
Simulation time 47736824220 ps
CPU time 60.29 seconds
Started Aug 16 04:34:45 PM PDT 24
Finished Aug 16 04:35:46 PM PDT 24
Peak memory 192048 kb
Host smart-ea810278-1362-4be8-a804-bae6bb5c9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361406721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2361406721
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3158306488
Short name T254
Test name
Test status
Simulation time 381974150 ps
CPU time 1.07 seconds
Started Aug 16 04:34:46 PM PDT 24
Finished Aug 16 04:34:48 PM PDT 24
Peak memory 192008 kb
Host smart-cd8ae6ae-bb8e-4a46-8f32-e1e2576ad83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158306488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3158306488
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2486329261
Short name T49
Test name
Test status
Simulation time 46373287300 ps
CPU time 59.06 seconds
Started Aug 16 04:34:54 PM PDT 24
Finished Aug 16 04:35:53 PM PDT 24
Peak memory 197140 kb
Host smart-092fec96-a304-48d2-b8af-8643a180e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486329261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2486329261
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1396947042
Short name T269
Test name
Test status
Simulation time 495657239 ps
CPU time 0.73 seconds
Started Aug 16 04:34:32 PM PDT 24
Finished Aug 16 04:34:33 PM PDT 24
Peak memory 191916 kb
Host smart-d2c2a886-eaba-404b-a37c-a1d954b172cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396947042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1396947042
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2062725184
Short name T221
Test name
Test status
Simulation time 12448579526 ps
CPU time 17.55 seconds
Started Aug 16 04:34:33 PM PDT 24
Finished Aug 16 04:34:51 PM PDT 24
Peak memory 192068 kb
Host smart-7b6e0809-14c6-4a54-9069-5f4b0948c389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062725184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2062725184
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.923389708
Short name T258
Test name
Test status
Simulation time 444272569 ps
CPU time 0.92 seconds
Started Aug 16 04:34:42 PM PDT 24
Finished Aug 16 04:34:43 PM PDT 24
Peak memory 196812 kb
Host smart-5fbdac9f-a4af-409f-8c4d-040ddcfd266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923389708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.923389708
Directory /workspace/9.aon_timer_smoke/latest
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