Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18703	1			T1	217		T2	11		T4	12
bark[1]	532	1			T11	26		T83	38		T46	21
bark[2]	524	1			T35	21		T36	30		T88	14
bark[3]	160	1			T126	26		T158	66		T134	26
bark[4]	237	1			T10	30		T34	21		T35	26
bark[5]	250	1			T13	7		T34	14		T38	125
bark[6]	173	1			T46	35		T168	21		T141	21
bark[7]	342	1			T11	56		T14	21		T124	26
bark[8]	354	1			T3	14		T12	5		T17	26
bark[9]	297	1			T11	43		T32	14		T50	14
bark[10]	294	1			T14	7		T52	21		T24	21
bark[11]	390	1			T187	14		T132	21		T131	14
bark[12]	643	1			T38	21		T163	21		T79	240
bark[13]	275	1			T37	30		T88	26		T102	21
bark[14]	510	1			T7	14		T16	7		T37	14
bark[15]	155	1			T83	21		T122	14		T153	45
bark[16]	385	1			T10	14		T45	72		T124	21
bark[17]	183	1			T9	14		T31	14		T149	21
bark[18]	370	1			T37	21		T52	21		T102	21
bark[19]	560	1			T14	21		T132	30		T149	7
bark[20]	251	1			T28	14		T47	49		T168	43
bark[21]	288	1			T10	21		T126	5		T153	26
bark[22]	270	1			T83	26		T46	5		T31	21
bark[23]	122	1			T12	26		T168	21		T95	5
bark[24]	240	1			T17	21		T31	70		T142	21
bark[25]	906	1			T46	5		T47	5		T76	269
bark[26]	308	1			T1	21		T83	21		T24	30
bark[27]	531	1			T6	14		T83	60		T193	7
bark[28]	572	1			T45	42		T83	35		T168	38
bark[29]	479	1			T37	21		T181	14		T132	21
bark[30]	363	1			T38	5		T77	48		T164	122
bark[31]	550	1			T106	14		T27	14		T31	21
bark_0	4800	1			T1	21		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	18308	1			T1	216		T2	10		T4	11
bite[1]	131	1			T102	21		T82	26		T101	21
bite[2]	591	1			T11	43		T35	21		T27	13
bite[3]	237	1			T37	21		T83	56		T149	6
bite[4]	484	1			T1	21		T88	13		T132	21
bite[5]	190	1			T14	27		T132	38		T113	21
bite[6]	252	1			T14	21		T99	21		T101	26
bite[7]	238	1			T46	21		T31	70		T76	21
bite[8]	141	1			T34	21		T38	21		T166	13
bite[9]	459	1			T32	13		T17	21		T106	13
bite[10]	466	1			T45	6		T35	21		T38	4
bite[11]	204	1			T3	13		T88	26		T143	21
bite[12]	302	1			T50	13		T163	94		T78	13
bite[13]	591	1			T10	34		T37	30		T126	79
bite[14]	378	1			T47	48		T77	31		T144	13
bite[15]	266	1			T6	13		T123	21		T134	64
bite[16]	391	1			T124	26		T46	34		T24	21
bite[17]	753	1			T7	13		T46	4		T143	197
bite[18]	245	1			T83	21		T36	30		T102	21
bite[19]	230	1			T37	21		T52	21		T102	21
bite[20]	175	1			T12	4		T17	26		T37	21
bite[21]	467	1			T34	13		T126	21		T164	6
bite[22]	271	1			T45	21		T35	21		T24	13
bite[23]	753	1			T11	26		T12	25		T16	6
bite[24]	483	1			T47	67		T141	21		T77	233
bite[25]	558	1			T124	21		T83	121		T24	51
bite[26]	213	1			T122	13		T102	26		T79	46
bite[27]	381	1			T10	30		T37	13		T187	13
bite[28]	247	1			T83	26		T38	124		T31	21
bite[29]	163	1			T134	21		T151	13		T99	21
bite[30]	660	1			T11	55		T13	6		T45	71
bite[31]	482	1			T9	13		T181	13		T24	21
bite_0	5307	1			T1	22		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30620

1

T1

252

T2

11

T3

21

auto[1]

4397

1

T1

7

T2

7

T10

43

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	469	1			T17	45		T168	24		T193	2
prescale[1]	272	1			T1	36		T38	2		T88	19
prescale[2]	615	1			T10	19		T14	19		T45	47
prescale[3]	504	1			T17	19		T35	19		T38	51
prescale[4]	367	1			T45	2		T30	9		T168	19
prescale[5]	591	1			T11	19		T199	9		T23	9
prescale[6]	458	1			T13	2		T88	61		T76	40
prescale[7]	270	1			T14	28		T88	49		T200	9
prescale[8]	313	1			T11	19		T16	2		T17	18
prescale[9]	432	1			T1	19		T17	42		T38	19
prescale[10]	452	1			T10	36		T45	2		T35	23
prescale[11]	334	1			T10	19		T37	58		T141	24
prescale[12]	652	1			T1	19		T14	2		T24	40
prescale[13]	429	1			T52	36		T26	9		T47	21
prescale[14]	542	1			T12	4		T35	9		T52	92
prescale[15]	453	1			T11	24		T16	2		T31	23
prescale[16]	324	1			T14	2		T49	9		T24	23
prescale[17]	170	1			T16	2		T142	28		T120	36
prescale[18]	421	1			T47	2		T77	137		T130	24
prescale[19]	294	1			T1	47		T124	28		T201	9
prescale[20]	370	1			T8	9		T14	117		T132	19
prescale[21]	591	1			T35	24		T102	23		T126	52
prescale[22]	248	1			T35	19		T24	40		T76	97
prescale[23]	324	1			T14	2		T17	19		T35	28
prescale[24]	270	1			T17	19		T202	9		T38	19
prescale[25]	276	1			T14	2		T34	2		T24	42
prescale[26]	329	1			T76	2		T141	2		T77	2
prescale[27]	319	1			T124	26		T36	2		T76	19
prescale[28]	641	1			T36	2		T46	2		T76	182
prescale[29]	396	1			T45	155		T35	82		T78	2
prescale[30]	476	1			T4	9		T14	19		T168	19
prescale[31]	240	1			T12	2		T13	2		T52	19
prescale_0	22175	1			T1	138		T2	18		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23877

1

T1

127

T2

9

T3

21

auto[1]

11140

1

T1

132

T2

9

T8

10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

35017

1

T1

259

T2

18

T3

21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19315	1			T1	219		T2	13		T3	1
wkup[1]	76	1			T24	21		T153	26		T193	8
wkup[2]	213	1			T35	21		T52	21		T31	21
wkup[3]	233	1			T14	21		T45	35		T38	21
wkup[4]	114	1			T134	30		T96	21		T97	21
wkup[5]	123	1			T126	21		T146	21		T186	15
wkup[6]	142	1			T50	15		T126	21		T164	15
wkup[7]	218	1			T88	21		T163	30		T77	21
wkup[8]	254	1			T192	15		T110	15		T85	21
wkup[9]	187	1			T37	21		T76	26		T77	26
wkup[10]	275	1			T7	15		T141	30		T126	21
wkup[11]	232	1			T9	15		T11	21		T45	21
wkup[12]	172	1			T11	26		T37	21		T24	15
wkup[13]	212	1			T116	30		T164	6		T79	42
wkup[14]	36	1			T28	15		T125	15		T165	6
wkup[15]	253	1			T3	15		T83	47		T38	6
wkup[16]	143	1			T24	21		T31	15		T77	21
wkup[17]	120	1			T181	15		T76	21		T79	21
wkup[18]	115	1			T36	30		T129	26		T175	15
wkup[19]	145	1			T92	35		T153	21		T164	21
wkup[20]	167	1			T102	21		T92	39		T149	8
wkup[21]	228	1			T1	21		T47	21		T76	44
wkup[22]	182	1			T88	26		T46	6		T164	21
wkup[23]	277	1			T45	31		T38	26		T102	66
wkup[24]	109	1			T37	30		T77	8		T107	8
wkup[25]	180	1			T79	30		T121	21		T113	21
wkup[26]	173	1			T45	15		T31	21		T132	21
wkup[27]	171	1			T35	21		T83	21		T159	15
wkup[28]	192	1			T14	21		T76	26		T77	31
wkup[29]	136	1			T45	8		T46	21		T76	15
wkup[30]	225	1			T76	21		T141	21		T149	39
wkup[31]	247	1			T24	21		T126	26		T116	21
wkup[32]	162	1			T10	30		T14	21		T106	15
wkup[33]	161	1			T14	21		T121	29		T134	12
wkup[34]	139	1			T34	21		T88	15		T121	21
wkup[35]	188	1			T14	8		T38	15		T27	15
wkup[36]	182	1			T13	8		T46	21		T47	21
wkup[37]	192	1			T52	21		T83	35		T31	21
wkup[38]	178	1			T168	21		T126	21		T164	8
wkup[39]	313	1			T11	15		T38	21		T47	6
wkup[40]	159	1			T16	21		T24	30		T190	15
wkup[41]	356	1			T124	26		T132	21		T163	30
wkup[42]	247	1			T11	21		T76	21		T163	21
wkup[43]	139	1			T102	21		T163	15		T92	26
wkup[44]	257	1			T12	6		T37	21		T78	30
wkup[45]	89	1			T11	26		T92	21		T156	21
wkup[46]	165	1			T34	15		T37	15		T46	21
wkup[47]	159	1			T83	35		T77	26		T148	21
wkup[48]	171	1			T46	8		T193	21		T113	15
wkup[49]	200	1			T31	21		T149	21		T120	21
wkup[50]	240	1			T12	21		T76	21		T78	8
wkup[51]	267	1			T14	21		T36	21		T168	21
wkup[52]	183	1			T31	21		T76	30		T153	21
wkup[53]	250	1			T76	21		T121	21		T137	21
wkup[54]	224	1			T6	15		T35	21		T46	27
wkup[55]	210	1			T35	31		T52	21		T46	21
wkup[56]	149	1			T47	21		T132	21		T92	8
wkup[57]	251	1			T124	21		T83	39		T47	21
wkup[58]	237	1			T24	21		T132	30		T150	48
wkup[59]	126	1			T45	21		T164	21		T146	21
wkup[60]	178	1			T24	21		T79	26		T150	21
wkup[61]	214	1			T10	15		T35	26		T83	21
wkup[62]	150	1			T10	21		T32	15		T132	21
wkup[63]	266	1			T14	15		T17	47		T122	15
wkup_0	3750	1			T1	19		T2	5		T3	5