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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.50 99.33 95.61 100.00 98.40 99.51 44.15


Total test records in report: 427
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T169 /workspace/coverage/default/19.aon_timer_stress_all.1672625569 Aug 17 04:32:06 PM PDT 24 Aug 17 04:32:34 PM PDT 24 73940726497 ps
T22 /workspace/coverage/default/0.aon_timer_sec_cm.2614033221 Aug 17 04:31:34 PM PDT 24 Aug 17 04:31:40 PM PDT 24 4014539314 ps
T39 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.270815784 Aug 17 04:32:12 PM PDT 24 Aug 17 04:32:14 PM PDT 24 512089771 ps
T287 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.547209030 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:26 PM PDT 24 380842949 ps
T288 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3362713485 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:31 PM PDT 24 514881748 ps
T289 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1531812939 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 276859600 ps
T40 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.467561348 Aug 17 04:32:31 PM PDT 24 Aug 17 04:32:34 PM PDT 24 609486847 ps
T41 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2213556008 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:31 PM PDT 24 478447205 ps
T290 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2140183109 Aug 17 04:32:31 PM PDT 24 Aug 17 04:32:33 PM PDT 24 427742388 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1901097745 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:25 PM PDT 24 874179840 ps
T292 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2140107499 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:30 PM PDT 24 601517403 ps
T42 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1829989211 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:29 PM PDT 24 8243239480 ps
T66 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1037438473 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:32 PM PDT 24 1256720855 ps
T74 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1530184484 Aug 17 04:32:13 PM PDT 24 Aug 17 04:32:26 PM PDT 24 6949151558 ps
T43 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.906126162 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:40 PM PDT 24 8343019355 ps
T293 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3907025644 Aug 17 04:32:47 PM PDT 24 Aug 17 04:32:48 PM PDT 24 402219259 ps
T294 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3182951394 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:24 PM PDT 24 496787784 ps
T44 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2159493845 Aug 17 04:32:19 PM PDT 24 Aug 17 04:32:23 PM PDT 24 4433738915 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3803866259 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:38 PM PDT 24 480572487 ps
T295 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.573248703 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 415522312 ps
T296 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3543917462 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:31 PM PDT 24 638680275 ps
T297 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3501934734 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 423667453 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.825421832 Aug 17 04:32:36 PM PDT 24 Aug 17 04:32:38 PM PDT 24 2764087998 ps
T298 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1224741084 Aug 17 04:32:34 PM PDT 24 Aug 17 04:32:37 PM PDT 24 572650520 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2192392760 Aug 17 04:32:17 PM PDT 24 Aug 17 04:32:24 PM PDT 24 4451904384 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.402719874 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:32 PM PDT 24 3158659652 ps
T70 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2609024929 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:28 PM PDT 24 1516158358 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2317412125 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:29 PM PDT 24 1479919820 ps
T300 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2196620504 Aug 17 04:32:08 PM PDT 24 Aug 17 04:32:09 PM PDT 24 347792307 ps
T301 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1909648785 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:30 PM PDT 24 4711427835 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1908845596 Aug 17 04:32:15 PM PDT 24 Aug 17 04:32:19 PM PDT 24 8442936013 ps
T196 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1581658319 Aug 17 04:32:33 PM PDT 24 Aug 17 04:32:36 PM PDT 24 4644213270 ps
T303 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2788698247 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:31 PM PDT 24 469200001 ps
T71 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3723422939 Aug 17 04:32:34 PM PDT 24 Aug 17 04:32:36 PM PDT 24 2094367246 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2250258744 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:30 PM PDT 24 577854202 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4231666631 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:23 PM PDT 24 639170594 ps
T304 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4126168698 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:30 PM PDT 24 437604443 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2597276032 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 454922590 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1362775915 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 517126880 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2389964827 Aug 17 04:32:35 PM PDT 24 Aug 17 04:32:39 PM PDT 24 7332388197 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3953114829 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 287204343 ps
T308 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1075400688 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:22 PM PDT 24 339897031 ps
T309 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3231307730 Aug 17 04:32:45 PM PDT 24 Aug 17 04:32:50 PM PDT 24 8520325937 ps
T310 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1338720380 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:31 PM PDT 24 530587761 ps
T311 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3827978097 Aug 17 04:32:18 PM PDT 24 Aug 17 04:32:19 PM PDT 24 672975356 ps
T312 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1380048324 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:34 PM PDT 24 293102668 ps
T72 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1995319952 Aug 17 04:32:45 PM PDT 24 Aug 17 04:32:46 PM PDT 24 363324698 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.486411792 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 592829451 ps
T314 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3406643297 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:25 PM PDT 24 413831461 ps
T315 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3652732822 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 387387357 ps
T316 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1102745212 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:23 PM PDT 24 502754931 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2257925514 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:29 PM PDT 24 470655709 ps
T318 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3190674328 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 496303862 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3909204405 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 319105549 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4237925145 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 414041674 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2049515109 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:25 PM PDT 24 453564077 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2276443780 Aug 17 04:32:22 PM PDT 24 Aug 17 04:32:23 PM PDT 24 296618584 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.676657727 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 431012144 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1725232536 Aug 17 04:32:35 PM PDT 24 Aug 17 04:32:36 PM PDT 24 547427486 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.348415818 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 360431651 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3934322240 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:25 PM PDT 24 879922707 ps
T325 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2365034503 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 444859393 ps
T326 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.608605621 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:35 PM PDT 24 428789174 ps
T327 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2380505863 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 351572418 ps
T58 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3842272525 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:36 PM PDT 24 449255948 ps
T328 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3860674927 Aug 17 04:32:08 PM PDT 24 Aug 17 04:32:16 PM PDT 24 7277636025 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.557600668 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 600333427 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1032029054 Aug 17 04:32:19 PM PDT 24 Aug 17 04:32:21 PM PDT 24 390701565 ps
T331 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.263896357 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 387560549 ps
T332 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2421535983 Aug 17 04:32:55 PM PDT 24 Aug 17 04:32:56 PM PDT 24 329587799 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1343496648 Aug 17 04:32:22 PM PDT 24 Aug 17 04:32:24 PM PDT 24 515362342 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.426960163 Aug 17 04:32:13 PM PDT 24 Aug 17 04:32:14 PM PDT 24 569501109 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.225277593 Aug 17 04:32:31 PM PDT 24 Aug 17 04:32:34 PM PDT 24 4638785086 ps
T335 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.115320230 Aug 17 04:32:39 PM PDT 24 Aug 17 04:32:41 PM PDT 24 406300147 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2419072352 Aug 17 04:32:15 PM PDT 24 Aug 17 04:32:16 PM PDT 24 497724438 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.770852434 Aug 17 04:32:18 PM PDT 24 Aug 17 04:32:18 PM PDT 24 325115822 ps
T59 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1678166849 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 502241832 ps
T60 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4177322330 Aug 17 04:32:11 PM PDT 24 Aug 17 04:32:12 PM PDT 24 539160456 ps
T338 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4252128700 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 517293507 ps
T339 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3892023188 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:25 PM PDT 24 291210628 ps
T340 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.981584554 Aug 17 04:32:51 PM PDT 24 Aug 17 04:32:53 PM PDT 24 427501999 ps
T341 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4048201856 Aug 17 04:32:32 PM PDT 24 Aug 17 04:32:33 PM PDT 24 305120868 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.591616869 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 448331247 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1161606895 Aug 17 04:32:13 PM PDT 24 Aug 17 04:32:15 PM PDT 24 1602716260 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.94723399 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 406350205 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1441547036 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:30 PM PDT 24 1097640592 ps
T346 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1465851858 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:22 PM PDT 24 461928888 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3429725542 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:26 PM PDT 24 337834579 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2120439496 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:29 PM PDT 24 408440981 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4150405309 Aug 17 04:32:07 PM PDT 24 Aug 17 04:32:11 PM PDT 24 1916228471 ps
T350 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3876012187 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 496797353 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2774429831 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 469909836 ps
T352 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.746082988 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:27 PM PDT 24 2606303699 ps
T353 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4095573639 Aug 17 04:32:10 PM PDT 24 Aug 17 04:32:11 PM PDT 24 491521123 ps
T354 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3254949422 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 507446249 ps
T355 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2567417113 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:24 PM PDT 24 587144701 ps
T356 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1638156407 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:36 PM PDT 24 343744974 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2425585695 Aug 17 04:32:16 PM PDT 24 Aug 17 04:32:17 PM PDT 24 684788578 ps
T358 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2688113324 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 402787128 ps
T359 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3927015234 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:31 PM PDT 24 352403554 ps
T360 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.721799544 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 454965991 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3776592452 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 409012915 ps
T362 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.918516529 Aug 17 04:32:40 PM PDT 24 Aug 17 04:32:41 PM PDT 24 437430658 ps
T363 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2296223826 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:30 PM PDT 24 2660996131 ps
T364 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3760671599 Aug 17 04:32:09 PM PDT 24 Aug 17 04:32:11 PM PDT 24 4516841531 ps
T197 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2350042143 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:43 PM PDT 24 8433181062 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1678665566 Aug 17 04:32:21 PM PDT 24 Aug 17 04:32:27 PM PDT 24 352097674 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.951468401 Aug 17 04:32:17 PM PDT 24 Aug 17 04:32:20 PM PDT 24 1435893765 ps
T367 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4210411337 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 404023824 ps
T368 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1684283105 Aug 17 04:32:36 PM PDT 24 Aug 17 04:32:37 PM PDT 24 350201005 ps
T369 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1144850031 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:29 PM PDT 24 4520721918 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3925008380 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 378517232 ps
T194 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4025481199 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:38 PM PDT 24 7992510477 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2372697058 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:28 PM PDT 24 10951662073 ps
T62 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1038880512 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 325755866 ps
T371 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2434279826 Aug 17 04:32:30 PM PDT 24 Aug 17 04:32:31 PM PDT 24 536215455 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.466176497 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 539037446 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.824850582 Aug 17 04:32:11 PM PDT 24 Aug 17 04:32:14 PM PDT 24 484833611 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2995754535 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:25 PM PDT 24 358036937 ps
T375 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1769639658 Aug 17 04:32:58 PM PDT 24 Aug 17 04:32:59 PM PDT 24 514744809 ps
T376 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.388387723 Aug 17 04:32:10 PM PDT 24 Aug 17 04:32:12 PM PDT 24 387626104 ps
T377 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2136706917 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:24 PM PDT 24 309843629 ps
T378 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.644266259 Aug 17 04:32:33 PM PDT 24 Aug 17 04:32:39 PM PDT 24 476051823 ps
T379 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3064803131 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 459910927 ps
T380 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2898597700 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 336437205 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2851158005 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 333920663 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3255580826 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:25 PM PDT 24 2760205577 ps
T383 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2571861583 Aug 17 04:32:40 PM PDT 24 Aug 17 04:32:41 PM PDT 24 338091392 ps
T384 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3899410172 Aug 17 04:32:32 PM PDT 24 Aug 17 04:32:34 PM PDT 24 393993330 ps
T385 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1835753891 Aug 17 04:32:36 PM PDT 24 Aug 17 04:32:40 PM PDT 24 3964930474 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.816430131 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 289567186 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3789252196 Aug 17 04:32:18 PM PDT 24 Aug 17 04:32:20 PM PDT 24 440734280 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1478604955 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 400468542 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2708206606 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 459411001 ps
T390 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3821375094 Aug 17 04:32:22 PM PDT 24 Aug 17 04:32:23 PM PDT 24 465157376 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2867668910 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:31 PM PDT 24 9200774312 ps
T392 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1359523158 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:26 PM PDT 24 443349833 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1133207841 Aug 17 04:32:18 PM PDT 24 Aug 17 04:32:27 PM PDT 24 2262334092 ps
T394 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.175007421 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 392354547 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3383549756 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:29 PM PDT 24 2739072983 ps
T396 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2796121461 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:31 PM PDT 24 1659404465 ps
T397 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1192317913 Aug 17 04:32:32 PM PDT 24 Aug 17 04:32:33 PM PDT 24 511118265 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4188651438 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:25 PM PDT 24 467534808 ps
T399 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.232683272 Aug 17 04:32:33 PM PDT 24 Aug 17 04:32:34 PM PDT 24 379308013 ps
T198 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.687021411 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:34 PM PDT 24 8597643044 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.657236112 Aug 17 04:32:18 PM PDT 24 Aug 17 04:32:20 PM PDT 24 557127562 ps
T401 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3745020981 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 443244428 ps
T402 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1373094680 Aug 17 04:32:31 PM PDT 24 Aug 17 04:32:47 PM PDT 24 8521191702 ps
T403 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.104092313 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 305164834 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.321120715 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:21 PM PDT 24 1572195702 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.75891617 Aug 17 04:32:13 PM PDT 24 Aug 17 04:32:15 PM PDT 24 955982936 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.689537187 Aug 17 04:32:17 PM PDT 24 Aug 17 04:32:18 PM PDT 24 483754161 ps
T407 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.857138845 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 314533138 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.998800903 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 1457586059 ps
T63 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.271754669 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 324498236 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1445207811 Aug 17 04:32:39 PM PDT 24 Aug 17 04:32:42 PM PDT 24 4226273665 ps
T410 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1064635502 Aug 17 04:32:28 PM PDT 24 Aug 17 04:32:29 PM PDT 24 349023387 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2503237739 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:24 PM PDT 24 339769759 ps
T412 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2897988672 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:27 PM PDT 24 445952537 ps
T413 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1593404785 Aug 17 04:32:26 PM PDT 24 Aug 17 04:32:29 PM PDT 24 2194513563 ps
T195 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.856479341 Aug 17 04:32:34 PM PDT 24 Aug 17 04:32:47 PM PDT 24 7939193167 ps
T414 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3205332219 Aug 17 04:32:22 PM PDT 24 Aug 17 04:32:24 PM PDT 24 940992799 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3199595805 Aug 17 04:32:43 PM PDT 24 Aug 17 04:32:44 PM PDT 24 322470128 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3289877557 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 424981342 ps
T416 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2216904255 Aug 17 04:32:16 PM PDT 24 Aug 17 04:32:16 PM PDT 24 388248955 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2243590723 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:23 PM PDT 24 345498109 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.482643921 Aug 17 04:32:24 PM PDT 24 Aug 17 04:32:26 PM PDT 24 4031535505 ps
T419 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2279932457 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:31 PM PDT 24 2114055637 ps
T420 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.819668354 Aug 17 04:32:23 PM PDT 24 Aug 17 04:32:24 PM PDT 24 394810286 ps
T421 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.17453016 Aug 17 04:32:27 PM PDT 24 Aug 17 04:32:28 PM PDT 24 1040204924 ps
T422 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1521640318 Aug 17 04:32:25 PM PDT 24 Aug 17 04:32:26 PM PDT 24 361532893 ps
T423 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1501848930 Aug 17 04:32:20 PM PDT 24 Aug 17 04:32:22 PM PDT 24 2950213441 ps
T424 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2992998810 Aug 17 04:32:12 PM PDT 24 Aug 17 04:32:13 PM PDT 24 504710168 ps
T425 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3895127014 Aug 17 04:32:29 PM PDT 24 Aug 17 04:32:30 PM PDT 24 673759119 ps
T426 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1504048852 Aug 17 04:32:32 PM PDT 24 Aug 17 04:32:33 PM PDT 24 430973394 ps
T427 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2971316426 Aug 17 04:32:22 PM PDT 24 Aug 17 04:32:23 PM PDT 24 345023947 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3968073352 Aug 17 04:32:16 PM PDT 24 Aug 17 04:32:20 PM PDT 24 8781006576 ps

Test location /workspace/coverage/default/35.aon_timer_stress_all.3986076836
Short name T10
Test name
Test status
Simulation time 99461697026 ps
CPU time 74.68 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:33:18 PM PDT 24
Peak memory 198376 kb
Host smart-13028247-c1d1-4444-8287-2b22e413db24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986076836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3986076836
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1657892537
Short name T34
Test name
Test status
Simulation time 1500683739 ps
CPU time 7.48 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:41 PM PDT 24
Peak memory 214924 kb
Host smart-0b1f5b58-ac96-4a20-9f59-75eb1cadf73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657892537 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1657892537
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1829989211
Short name T42
Test name
Test status
Simulation time 8243239480 ps
CPU time 3.95 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 198268 kb
Host smart-3db5bfcd-322a-48c6-b2ac-abf9b0f27b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829989211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1829989211
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2250258744
Short name T53
Test name
Test status
Simulation time 577854202 ps
CPU time 1.36 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 192888 kb
Host smart-d0dac717-e18f-4a04-bbb8-7d21e96122a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250258744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2250258744
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2901535624
Short name T76
Test name
Test status
Simulation time 11663489647 ps
CPU time 22.6 seconds
Started Aug 17 04:31:52 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 198628 kb
Host smart-99a14a6a-3f65-4916-b558-dfb8ff64d6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901535624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2901535624
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1627700632
Short name T37
Test name
Test status
Simulation time 164864109967 ps
CPU time 54.9 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:33:16 PM PDT 24
Peak memory 198340 kb
Host smart-a75d27ed-9602-4cde-95b0-9097feeca55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627700632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1627700632
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.309814573
Short name T24
Test name
Test status
Simulation time 132510485372 ps
CPU time 122.05 seconds
Started Aug 17 04:31:59 PM PDT 24
Finished Aug 17 04:34:01 PM PDT 24
Peak memory 192604 kb
Host smart-9c8771c6-c861-4708-9f3d-3493a92e6bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309814573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.309814573
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2737959746
Short name T90
Test name
Test status
Simulation time 11879195909 ps
CPU time 31.53 seconds
Started Aug 17 04:31:43 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 206836 kb
Host smart-113804fc-31aa-4687-8c85-d926ded94388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737959746 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2737959746
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2240455198
Short name T93
Test name
Test status
Simulation time 243883185704 ps
CPU time 70.3 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:32:45 PM PDT 24
Peak memory 198396 kb
Host smart-27167ced-139a-49c1-bae6-5a7c9cc4fd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240455198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2240455198
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2614033221
Short name T22
Test name
Test status
Simulation time 4014539314 ps
CPU time 6.21 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:40 PM PDT 24
Peak memory 215640 kb
Host smart-b260ece6-d13d-4540-b50e-c549f29eb036
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614033221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2614033221
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1092273517
Short name T101
Test name
Test status
Simulation time 73995959316 ps
CPU time 117.05 seconds
Started Aug 17 04:32:14 PM PDT 24
Finished Aug 17 04:34:11 PM PDT 24
Peak memory 193092 kb
Host smart-56b6a7a2-c562-4172-8644-00d51cf0e605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092273517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1092273517
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.547517356
Short name T31
Test name
Test status
Simulation time 81559656482 ps
CPU time 120.25 seconds
Started Aug 17 04:31:38 PM PDT 24
Finished Aug 17 04:33:38 PM PDT 24
Peak memory 192632 kb
Host smart-45649085-886f-458b-821f-52d63c6cb1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547517356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.547517356
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.219570547
Short name T83
Test name
Test status
Simulation time 39160680705 ps
CPU time 58.19 seconds
Started Aug 17 04:31:58 PM PDT 24
Finished Aug 17 04:32:57 PM PDT 24
Peak memory 198408 kb
Host smart-713888fe-75cb-4e59-83de-5376a128474b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219570547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.219570547
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.377363394
Short name T85
Test name
Test status
Simulation time 72400998275 ps
CPU time 35.78 seconds
Started Aug 17 04:31:47 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 193156 kb
Host smart-fba99067-b402-4c55-b88d-ea4a798ad277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377363394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.377363394
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2287874673
Short name T96
Test name
Test status
Simulation time 123173510307 ps
CPU time 177.23 seconds
Started Aug 17 04:31:29 PM PDT 24
Finished Aug 17 04:34:26 PM PDT 24
Peak memory 198424 kb
Host smart-43483033-a51f-45da-b264-6850468b0f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287874673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2287874673
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2226812807
Short name T121
Test name
Test status
Simulation time 2920564747 ps
CPU time 5.76 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:13 PM PDT 24
Peak memory 184288 kb
Host smart-f166a9d2-517e-41c5-92f1-ae6ac7d18597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226812807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2226812807
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1197283025
Short name T107
Test name
Test status
Simulation time 4253099094 ps
CPU time 13.74 seconds
Started Aug 17 04:31:47 PM PDT 24
Finished Aug 17 04:32:01 PM PDT 24
Peak memory 198692 kb
Host smart-0ded3d7d-efd5-41e7-8f95-66ecc35c3e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197283025 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1197283025
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3772602547
Short name T130
Test name
Test status
Simulation time 225703034888 ps
CPU time 339.51 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:38:05 PM PDT 24
Peak memory 192148 kb
Host smart-2944235f-7a1b-4d0d-aca1-8312d02381e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772602547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3772602547
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1836893253
Short name T97
Test name
Test status
Simulation time 66506717311 ps
CPU time 54.26 seconds
Started Aug 17 04:31:43 PM PDT 24
Finished Aug 17 04:32:37 PM PDT 24
Peak memory 198408 kb
Host smart-88e329ab-603d-451b-8a33-682a0f6b850f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836893253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1836893253
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3515347276
Short name T79
Test name
Test status
Simulation time 21281979711 ps
CPU time 37.72 seconds
Started Aug 17 04:31:29 PM PDT 24
Finished Aug 17 04:32:07 PM PDT 24
Peak memory 198556 kb
Host smart-5a781333-a6dd-4780-8592-288ee4ccae17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515347276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3515347276
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2887438395
Short name T91
Test name
Test status
Simulation time 10181189754 ps
CPU time 45.99 seconds
Started Aug 17 04:31:43 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 198916 kb
Host smart-798dea73-dff2-4a0f-802e-799fa745e0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887438395 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2887438395
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1130984587
Short name T35
Test name
Test status
Simulation time 285945756894 ps
CPU time 105.8 seconds
Started Aug 17 04:31:38 PM PDT 24
Finished Aug 17 04:33:24 PM PDT 24
Peak memory 193092 kb
Host smart-9ecfb02c-604b-43aa-a23e-12d70291cb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130984587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1130984587
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2815211920
Short name T99
Test name
Test status
Simulation time 76846035916 ps
CPU time 114.46 seconds
Started Aug 17 04:32:01 PM PDT 24
Finished Aug 17 04:33:56 PM PDT 24
Peak memory 193340 kb
Host smart-72249a08-c0c7-460e-b9ff-e8a2ebe6c7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815211920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2815211920
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2980828958
Short name T120
Test name
Test status
Simulation time 5127497493 ps
CPU time 46.53 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 198712 kb
Host smart-ca785027-23f2-4fcd-8186-88e3baea09cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980828958 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2980828958
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2207253500
Short name T143
Test name
Test status
Simulation time 9517857099 ps
CPU time 21.76 seconds
Started Aug 17 04:32:19 PM PDT 24
Finished Aug 17 04:32:41 PM PDT 24
Peak memory 215076 kb
Host smart-914f7d3f-34d5-4dbe-b35a-b4469d911d12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207253500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2207253500
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2284542041
Short name T113
Test name
Test status
Simulation time 372496352698 ps
CPU time 31.92 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 198348 kb
Host smart-26a7118e-cfbe-4fa3-ac40-b10ca896a4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284542041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2284542041
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.253432833
Short name T132
Test name
Test status
Simulation time 128058104134 ps
CPU time 87.18 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:33:44 PM PDT 24
Peak memory 193116 kb
Host smart-3f9a90cc-3ad3-4ad0-a781-e3697f61e154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253432833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.253432833
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2390312409
Short name T116
Test name
Test status
Simulation time 136377759804 ps
CPU time 46.2 seconds
Started Aug 17 04:31:48 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 192764 kb
Host smart-6e3eefcc-1b20-49e1-8952-f07525818bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390312409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2390312409
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3202266284
Short name T86
Test name
Test status
Simulation time 4295656841 ps
CPU time 26.98 seconds
Started Aug 17 04:31:54 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 206928 kb
Host smart-06a34938-0aa6-45aa-8f71-e356ff9efab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202266284 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3202266284
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2061299302
Short name T115
Test name
Test status
Simulation time 50622844474 ps
CPU time 22.33 seconds
Started Aug 17 04:31:33 PM PDT 24
Finished Aug 17 04:31:56 PM PDT 24
Peak memory 192088 kb
Host smart-fe84f473-c811-414b-81e9-79670ca6329a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061299302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2061299302
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1054228840
Short name T102
Test name
Test status
Simulation time 171287327807 ps
CPU time 60.79 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:33:18 PM PDT 24
Peak memory 192092 kb
Host smart-2727391c-8d68-40df-84b5-cc775c8ff31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054228840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1054228840
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1664101129
Short name T148
Test name
Test status
Simulation time 20382388291 ps
CPU time 32.55 seconds
Started Aug 17 04:31:55 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 205800 kb
Host smart-491188ed-b785-43d2-a2d7-40773d41913c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664101129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1664101129
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3294024566
Short name T46
Test name
Test status
Simulation time 2372652079 ps
CPU time 14.86 seconds
Started Aug 17 04:31:46 PM PDT 24
Finished Aug 17 04:32:01 PM PDT 24
Peak memory 206920 kb
Host smart-6da7ab08-c083-44ff-aecf-5e803a1fd32c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294024566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3294024566
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3410068297
Short name T150
Test name
Test status
Simulation time 11205646880 ps
CPU time 18.95 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 198668 kb
Host smart-accdb10e-027f-4fde-9679-47cc56983b69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410068297 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3410068297
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1799047320
Short name T140
Test name
Test status
Simulation time 10474325263 ps
CPU time 16.35 seconds
Started Aug 17 04:31:40 PM PDT 24
Finished Aug 17 04:32:02 PM PDT 24
Peak memory 192004 kb
Host smart-c4765f79-48cc-43bd-9f3a-f777ad677935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799047320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1799047320
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.955764423
Short name T92
Test name
Test status
Simulation time 11415802181 ps
CPU time 21.44 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 206920 kb
Host smart-6284a217-16e4-43a9-bf8f-a76c062b4b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955764423 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.955764423
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2778636884
Short name T88
Test name
Test status
Simulation time 81797945227 ps
CPU time 109.32 seconds
Started Aug 17 04:31:56 PM PDT 24
Finished Aug 17 04:33:45 PM PDT 24
Peak memory 192164 kb
Host smart-27711a8b-c62b-4cbd-8629-313f4448a392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778636884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2778636884
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.4256025785
Short name T14
Test name
Test status
Simulation time 4051980144 ps
CPU time 23.7 seconds
Started Aug 17 04:31:59 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 198668 kb
Host smart-cc457552-a301-440e-9e04-8b6fb477b3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256025785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4256025785
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1789686272
Short name T160
Test name
Test status
Simulation time 4718507039 ps
CPU time 31.14 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:42 PM PDT 24
Peak memory 198696 kb
Host smart-3326bb15-6928-4c17-b802-0c7a1f6afac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789686272 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1789686272
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.661557794
Short name T81
Test name
Test status
Simulation time 14529231012 ps
CPU time 28.41 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:38 PM PDT 24
Peak memory 198692 kb
Host smart-abbde605-6b19-4316-9cd7-78137076f664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661557794 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.661557794
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1222547724
Short name T104
Test name
Test status
Simulation time 291152068947 ps
CPU time 102.52 seconds
Started Aug 17 04:31:47 PM PDT 24
Finished Aug 17 04:33:30 PM PDT 24
Peak memory 192052 kb
Host smart-38e6870f-92fa-4de4-8ed2-9a945196f81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222547724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1222547724
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3762090560
Short name T123
Test name
Test status
Simulation time 253169445738 ps
CPU time 366.68 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:37:43 PM PDT 24
Peak memory 192020 kb
Host smart-afe001dc-f7dd-4853-a39e-e9c6a0fd34d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762090560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3762090560
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.38822961
Short name T52
Test name
Test status
Simulation time 52477781691 ps
CPU time 36.46 seconds
Started Aug 17 04:31:57 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 193140 kb
Host smart-759b6f6d-4533-428c-86dd-b0101b590cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_al
l.38822961
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3391206406
Short name T98
Test name
Test status
Simulation time 104307177499 ps
CPU time 32.52 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:32:09 PM PDT 24
Peak memory 193200 kb
Host smart-599d51f6-9c0b-4145-99eb-4a825c8ec050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391206406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3391206406
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4112686363
Short name T135
Test name
Test status
Simulation time 44077637188 ps
CPU time 17.75 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 198316 kb
Host smart-fecc5014-96a3-462a-9822-4b8df6dbf763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112686363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4112686363
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4015840863
Short name T82
Test name
Test status
Simulation time 239847146851 ps
CPU time 388.4 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:38:42 PM PDT 24
Peak memory 198412 kb
Host smart-2fec2982-35f7-4256-b479-e874d6e91045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015840863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4015840863
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.598426681
Short name T134
Test name
Test status
Simulation time 8705578382 ps
CPU time 44.31 seconds
Started Aug 17 04:31:44 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 214808 kb
Host smart-dd8fe180-6f0e-48ed-af88-5160079eec1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598426681 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.598426681
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.51079311
Short name T163
Test name
Test status
Simulation time 210075456152 ps
CPU time 63.67 seconds
Started Aug 17 04:32:00 PM PDT 24
Finished Aug 17 04:33:04 PM PDT 24
Peak memory 193188 kb
Host smart-2295de08-8552-4a3b-8e1a-344c0c6e8229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51079311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_al
l.51079311
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2694609564
Short name T155
Test name
Test status
Simulation time 146816704645 ps
CPU time 104.15 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:33:52 PM PDT 24
Peak memory 193136 kb
Host smart-f896cd1a-5c4e-4352-a69e-88d3a97c28ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694609564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2694609564
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.114505175
Short name T146
Test name
Test status
Simulation time 3109555967 ps
CPU time 26.77 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 206824 kb
Host smart-cfd0a0be-a6e7-4b67-a626-b6e7f83ae025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114505175 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.114505175
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.185483851
Short name T139
Test name
Test status
Simulation time 3983407637 ps
CPU time 20.6 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:53 PM PDT 24
Peak memory 206888 kb
Host smart-9c13f109-48cd-42b4-b16c-64d48f6cccc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185483851 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.185483851
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3950966325
Short name T78
Test name
Test status
Simulation time 4568232177 ps
CPU time 29.95 seconds
Started Aug 17 04:31:49 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 206860 kb
Host smart-f5d06bc9-c067-49d0-855d-42cfc33d5e94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950966325 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3950966325
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3829469362
Short name T133
Test name
Test status
Simulation time 79817940393 ps
CPU time 16.85 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:43 PM PDT 24
Peak memory 198556 kb
Host smart-58b0417a-348d-4a7b-8963-c085b3862646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829469362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3829469362
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.626184303
Short name T11
Test name
Test status
Simulation time 48921622977 ps
CPU time 72.64 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:33:38 PM PDT 24
Peak memory 193104 kb
Host smart-596cd797-83a1-4f21-8f7d-7fce2b74fb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626184303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.626184303
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3803866259
Short name T67
Test name
Test status
Simulation time 480572487 ps
CPU time 1.3 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:38 PM PDT 24
Peak memory 193312 kb
Host smart-37a516ba-273c-43e0-894e-82a3ef67e5a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803866259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3803866259
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1475378745
Short name T129
Test name
Test status
Simulation time 444827185994 ps
CPU time 68.44 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:32:45 PM PDT 24
Peak memory 198428 kb
Host smart-1134ed7e-d65a-4c20-a842-981861a7c702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475378745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1475378745
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2559480464
Short name T128
Test name
Test status
Simulation time 145787103759 ps
CPU time 238.49 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:35:35 PM PDT 24
Peak memory 184704 kb
Host smart-a458ed92-f888-4a2a-91a9-5b300beeb657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559480464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2559480464
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.679804924
Short name T149
Test name
Test status
Simulation time 13422558838 ps
CPU time 22.41 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 214972 kb
Host smart-7cf11886-3614-4a4f-b7e0-5f29b8df5a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679804924 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.679804924
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3664766296
Short name T95
Test name
Test status
Simulation time 3808678357 ps
CPU time 27.4 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:40 PM PDT 24
Peak memory 206856 kb
Host smart-a7f48de3-94bf-40ee-8de3-d78104dab232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664766296 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3664766296
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3351146962
Short name T126
Test name
Test status
Simulation time 8056228147 ps
CPU time 29.36 seconds
Started Aug 17 04:32:01 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 198644 kb
Host smart-6a527db7-4f22-4123-bc45-e053cf6f7001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351146962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3351146962
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3118526328
Short name T136
Test name
Test status
Simulation time 51174208707 ps
CPU time 76.68 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:32:52 PM PDT 24
Peak memory 198416 kb
Host smart-3ab54f76-5268-41bf-854b-c51ddd895a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118526328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3118526328
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2615471996
Short name T142
Test name
Test status
Simulation time 9571163496 ps
CPU time 47.38 seconds
Started Aug 17 04:32:19 PM PDT 24
Finished Aug 17 04:33:06 PM PDT 24
Peak memory 206884 kb
Host smart-164bc6e5-d284-4adf-b119-becbd59debef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615471996 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2615471996
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.881498684
Short name T89
Test name
Test status
Simulation time 1589017880 ps
CPU time 7.65 seconds
Started Aug 17 04:31:58 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 198604 kb
Host smart-3865dde4-aa90-4316-a23c-19b92b6a24f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881498684 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.881498684
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2309060321
Short name T125
Test name
Test status
Simulation time 578033535 ps
CPU time 1.45 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196756 kb
Host smart-2d5be167-adca-4558-9df9-20e32cfccb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309060321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2309060321
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1142667910
Short name T105
Test name
Test status
Simulation time 2376679529 ps
CPU time 17.7 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 198668 kb
Host smart-3cb984a7-4f9d-4e91-932f-ba0c05beda7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142667910 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1142667910
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.692104333
Short name T111
Test name
Test status
Simulation time 224124833675 ps
CPU time 345.57 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:38:13 PM PDT 24
Peak memory 198428 kb
Host smart-af0bfd9f-d662-45db-984b-7221bc517ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692104333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.692104333
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2943449716
Short name T45
Test name
Test status
Simulation time 4060076263 ps
CPU time 13.63 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:48 PM PDT 24
Peak memory 198576 kb
Host smart-2054ba6a-6718-42f0-af6f-6ef8105d1d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943449716 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2943449716
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1726319159
Short name T32
Test name
Test status
Simulation time 558268669 ps
CPU time 1.08 seconds
Started Aug 17 04:31:40 PM PDT 24
Finished Aug 17 04:31:42 PM PDT 24
Peak memory 196840 kb
Host smart-9204b9d4-a90b-4637-9a6c-3035dc3f795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726319159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1726319159
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3783049593
Short name T108
Test name
Test status
Simulation time 2669070513 ps
CPU time 4.36 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 214852 kb
Host smart-dbb4b40b-7698-4505-a95a-22e75765b557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783049593 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3783049593
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1717721688
Short name T112
Test name
Test status
Simulation time 573854325 ps
CPU time 1.44 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:08 PM PDT 24
Peak memory 196796 kb
Host smart-5b539a21-ba64-4d56-b4c8-0f548b947b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717721688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1717721688
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2981893977
Short name T119
Test name
Test status
Simulation time 444304704 ps
CPU time 0.89 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:10 PM PDT 24
Peak memory 196772 kb
Host smart-83d80c74-d3b6-4d31-add1-ab3cbd781e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981893977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2981893977
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3505087654
Short name T94
Test name
Test status
Simulation time 98386861003 ps
CPU time 37.23 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:47 PM PDT 24
Peak memory 192364 kb
Host smart-951f49a6-b885-4a18-a701-0a63fdeb94bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505087654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3505087654
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2663251260
Short name T28
Test name
Test status
Simulation time 480460846 ps
CPU time 0.62 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:39 PM PDT 24
Peak memory 196740 kb
Host smart-b80e72cc-20b4-404f-8e5c-0d510ec5a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663251260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2663251260
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3529394882
Short name T152
Test name
Test status
Simulation time 579052414 ps
CPU time 1.02 seconds
Started Aug 17 04:31:57 PM PDT 24
Finished Aug 17 04:31:58 PM PDT 24
Peak memory 196880 kb
Host smart-a22d61a1-3332-49fb-8d80-a82d18602727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529394882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3529394882
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3905294186
Short name T137
Test name
Test status
Simulation time 143271313214 ps
CPU time 220.3 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:35:43 PM PDT 24
Peak memory 198436 kb
Host smart-3575c05c-2e59-4c88-a458-be6cc6e9ca5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905294186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3905294186
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2851148671
Short name T110
Test name
Test status
Simulation time 591052101 ps
CPU time 1.08 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 196904 kb
Host smart-7d62a2ad-b186-4f7a-9228-19b7451f685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851148671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2851148671
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1564477667
Short name T164
Test name
Test status
Simulation time 4759877140 ps
CPU time 16.1 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:38 PM PDT 24
Peak memory 206872 kb
Host smart-06058939-ac3f-4560-ac95-f3ab95c1bcea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564477667 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1564477667
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.141700416
Short name T122
Test name
Test status
Simulation time 553598841 ps
CPU time 1.41 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:13 PM PDT 24
Peak memory 196856 kb
Host smart-68688c48-60a1-4960-a647-5408b0f5ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141700416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.141700416
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.47326089
Short name T145
Test name
Test status
Simulation time 403303864 ps
CPU time 0.88 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196856 kb
Host smart-0506188d-1d20-42fa-b0a4-740c292b4e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47326089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.47326089
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1672625569
Short name T169
Test name
Test status
Simulation time 73940726497 ps
CPU time 28.26 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 192704 kb
Host smart-49594f85-575e-4013-9c79-e6aa22c23582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672625569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1672625569
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.41934915
Short name T154
Test name
Test status
Simulation time 367382354 ps
CPU time 1.16 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 196884 kb
Host smart-ea247a5f-566d-4ca2-a17f-1afdc8f65b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41934915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.41934915
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.520589510
Short name T47
Test name
Test status
Simulation time 1889869950 ps
CPU time 13.23 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 198604 kb
Host smart-8a887aee-1429-43e9-a4ef-67768e7a0002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520589510 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.520589510
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.432326942
Short name T38
Test name
Test status
Simulation time 2096263245 ps
CPU time 11.98 seconds
Started Aug 17 04:32:02 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 198716 kb
Host smart-4dcf898b-b830-4574-840a-0e08da52ce0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432326942 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.432326942
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.216390516
Short name T141
Test name
Test status
Simulation time 4136689513 ps
CPU time 17.75 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:50 PM PDT 24
Peak memory 214276 kb
Host smart-47368438-e8f0-4a9b-852b-557e44cc5d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216390516 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.216390516
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2966244333
Short name T36
Test name
Test status
Simulation time 7893329430 ps
CPU time 14.76 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:53 PM PDT 24
Peak memory 214228 kb
Host smart-6ec6ca83-6ff0-48c8-8e4c-e527d09c1f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966244333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2966244333
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3036559222
Short name T87
Test name
Test status
Simulation time 414933566 ps
CPU time 0.68 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196764 kb
Host smart-f17d7caa-ea8a-4e75-80cb-e33f468fb216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036559222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3036559222
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3378955267
Short name T100
Test name
Test status
Simulation time 1904841767 ps
CPU time 9.34 seconds
Started Aug 17 04:32:00 PM PDT 24
Finished Aug 17 04:32:09 PM PDT 24
Peak memory 198560 kb
Host smart-050f5cee-425e-48ad-a27d-a5faf8556b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378955267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3378955267
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1632308514
Short name T131
Test name
Test status
Simulation time 399477575 ps
CPU time 0.8 seconds
Started Aug 17 04:31:40 PM PDT 24
Finished Aug 17 04:31:41 PM PDT 24
Peak memory 196824 kb
Host smart-e96bab99-b31a-40b7-a391-b9fb7077b1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632308514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1632308514
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.970865589
Short name T158
Test name
Test status
Simulation time 169556328022 ps
CPU time 68.87 seconds
Started Aug 17 04:31:33 PM PDT 24
Finished Aug 17 04:32:42 PM PDT 24
Peak memory 198364 kb
Host smart-1fff3a1a-094b-4166-94a1-0c7dd727c31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970865589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.970865589
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1012954970
Short name T147
Test name
Test status
Simulation time 429814407 ps
CPU time 0.75 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:10 PM PDT 24
Peak memory 196824 kb
Host smart-525804ab-bd74-445a-b774-cdb8843ddea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012954970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1012954970
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1311404194
Short name T156
Test name
Test status
Simulation time 3096881314 ps
CPU time 9.21 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:18 PM PDT 24
Peak memory 206940 kb
Host smart-f2c1c5f1-1626-41c0-8ef4-d7fc2a2afca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311404194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1311404194
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1529715365
Short name T103
Test name
Test status
Simulation time 575229758 ps
CPU time 1.45 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 196812 kb
Host smart-400d0775-8854-4b41-8d94-c86360d0b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529715365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1529715365
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2067236432
Short name T118
Test name
Test status
Simulation time 469350295 ps
CPU time 0.73 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:08 PM PDT 24
Peak memory 196832 kb
Host smart-a97d7b3b-0137-4192-a45c-6bad37b971f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067236432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2067236432
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2863194079
Short name T127
Test name
Test status
Simulation time 543247770 ps
CPU time 0.89 seconds
Started Aug 17 04:32:34 PM PDT 24
Finished Aug 17 04:32:35 PM PDT 24
Peak memory 196724 kb
Host smart-56c0a110-c20e-48a6-951d-9cbfbb62e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863194079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2863194079
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3484033643
Short name T9
Test name
Test status
Simulation time 424094420 ps
CPU time 0.96 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 196808 kb
Host smart-f36111b2-9d59-4555-aaab-f6ca89bf4477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484033643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3484033643
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1877609933
Short name T114
Test name
Test status
Simulation time 455808327 ps
CPU time 0.93 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 196760 kb
Host smart-1b0575eb-8add-494b-b28b-88c6da5f5af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877609933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1877609933
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1831095982
Short name T176
Test name
Test status
Simulation time 7952296895 ps
CPU time 13.91 seconds
Started Aug 17 04:31:33 PM PDT 24
Finished Aug 17 04:31:47 PM PDT 24
Peak memory 206808 kb
Host smart-74e5350a-6a9d-44e3-ab6a-0e6930ca7db0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831095982 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1831095982
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.646223010
Short name T84
Test name
Test status
Simulation time 352100818 ps
CPU time 0.83 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 196812 kb
Host smart-ff464f32-7995-470d-84f5-08c45c2fe6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646223010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.646223010
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3559292964
Short name T170
Test name
Test status
Simulation time 179849152701 ps
CPU time 223.23 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:36:05 PM PDT 24
Peak memory 198408 kb
Host smart-daa28e3d-4537-4a4a-8141-8b2b4396bcb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559292964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3559292964
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3831635578
Short name T144
Test name
Test status
Simulation time 387759760 ps
CPU time 1.19 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 196864 kb
Host smart-6adfe9ed-93b8-4069-85d6-f9a733e89f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831635578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3831635578
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1757133098
Short name T153
Test name
Test status
Simulation time 71993539536 ps
CPU time 12.82 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 192068 kb
Host smart-69b604d4-ae2e-4a31-bbe2-b36cc44f99d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757133098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1757133098
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3740721831
Short name T109
Test name
Test status
Simulation time 488620744 ps
CPU time 1.37 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 196820 kb
Host smart-93efeec8-4f2b-441d-9f45-ced07549006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740721831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3740721831
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.479067816
Short name T138
Test name
Test status
Simulation time 427033228 ps
CPU time 0.78 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 196864 kb
Host smart-d24bdd6e-64de-424a-b90c-e426a242f01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479067816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.479067816
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1254091204
Short name T117
Test name
Test status
Simulation time 404386092 ps
CPU time 1.22 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:38 PM PDT 24
Peak memory 196872 kb
Host smart-2ba7d447-b573-4321-a802-cae1507b7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254091204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1254091204
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.254436056
Short name T178
Test name
Test status
Simulation time 282927956368 ps
CPU time 111.51 seconds
Started Aug 17 04:31:53 PM PDT 24
Finished Aug 17 04:33:44 PM PDT 24
Peak memory 198332 kb
Host smart-dcc9acc5-c65e-410b-8938-1276f89971df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254436056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.254436056
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2131064810
Short name T1
Test name
Test status
Simulation time 88530767674 ps
CPU time 114.57 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:34:05 PM PDT 24
Peak memory 198408 kb
Host smart-a93f2b40-02d0-46e8-b31c-eebd4ce6fee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131064810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2131064810
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.895159682
Short name T17
Test name
Test status
Simulation time 110366398754 ps
CPU time 148.44 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:34:49 PM PDT 24
Peak memory 192084 kb
Host smart-7b2f1b49-2dcf-41de-9d2a-955c583d50ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895159682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.895159682
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.665647534
Short name T167
Test name
Test status
Simulation time 161746786003 ps
CPU time 11.75 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:46 PM PDT 24
Peak memory 193088 kb
Host smart-f23f7291-c231-4599-9850-369fd1905b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665647534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.665647534
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2138843305
Short name T182
Test name
Test status
Simulation time 241711247925 ps
CPU time 25.03 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 192048 kb
Host smart-75f1ecf0-00a1-47b9-a017-bd4eba95392a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138843305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2138843305
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1225634706
Short name T193
Test name
Test status
Simulation time 14914611624 ps
CPU time 29.19 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:32 PM PDT 24
Peak memory 212248 kb
Host smart-862cde7d-bd48-4b2b-a1ff-cb993db4c867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225634706 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1225634706
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3372304854
Short name T165
Test name
Test status
Simulation time 4119609323 ps
CPU time 12.69 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 198688 kb
Host smart-52634e06-28f7-4ab8-827c-374b033039e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372304854 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3372304854
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1169947382
Short name T172
Test name
Test status
Simulation time 7921096367 ps
CPU time 14.47 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 206860 kb
Host smart-9560e00e-d66b-4613-a346-0aa20007678a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169947382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1169947382
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2923755080
Short name T157
Test name
Test status
Simulation time 399072883 ps
CPU time 1.12 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 196804 kb
Host smart-66b46394-7b19-4abc-a0cf-587eeaaed4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923755080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2923755080
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.337289307
Short name T174
Test name
Test status
Simulation time 508206643 ps
CPU time 0.88 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 196748 kb
Host smart-2c937c8d-c93d-43f6-9867-2b7fe45a68fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337289307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.337289307
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3462993029
Short name T12
Test name
Test status
Simulation time 1852565881 ps
CPU time 11.51 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 214124 kb
Host smart-58daf057-fe5a-4828-97bf-0765bbc3c4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462993029 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3462993029
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.377431586
Short name T181
Test name
Test status
Simulation time 467341427 ps
CPU time 1.22 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196892 kb
Host smart-6667ed61-5e85-4c37-9dc6-5bb5eefc5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377431586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.377431586
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4025442713
Short name T187
Test name
Test status
Simulation time 472890460 ps
CPU time 0.65 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 196780 kb
Host smart-30c113e7-50bc-4957-88f3-fff83a7373d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025442713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4025442713
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3902244672
Short name T7
Test name
Test status
Simulation time 495257512 ps
CPU time 1.25 seconds
Started Aug 17 04:31:43 PM PDT 24
Finished Aug 17 04:31:45 PM PDT 24
Peak memory 196744 kb
Host smart-93368d02-91c5-4e7c-96bd-5caaddb5526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902244672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3902244672
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2744160857
Short name T151
Test name
Test status
Simulation time 517262150 ps
CPU time 0.98 seconds
Started Aug 17 04:31:44 PM PDT 24
Finished Aug 17 04:31:50 PM PDT 24
Peak memory 196896 kb
Host smart-a32cc3b5-5b9f-4be2-a6bc-43b6dc61a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744160857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2744160857
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.814633097
Short name T171
Test name
Test status
Simulation time 371270829 ps
CPU time 0.71 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:35 PM PDT 24
Peak memory 196764 kb
Host smart-7db20c16-5fc1-4f89-a601-da5b86fb1768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814633097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.814633097
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2523218921
Short name T166
Test name
Test status
Simulation time 547422230 ps
CPU time 1.4 seconds
Started Aug 17 04:31:48 PM PDT 24
Finished Aug 17 04:31:50 PM PDT 24
Peak memory 196808 kb
Host smart-44a67cf7-7e5a-49f0-b2ae-4ee8cbc67d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523218921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2523218921
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2499060559
Short name T183
Test name
Test status
Simulation time 5706764706 ps
CPU time 10.16 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:46 PM PDT 24
Peak memory 207168 kb
Host smart-f988d85c-854c-430a-99d0-0921aa44705b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499060559 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2499060559
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.471424253
Short name T50
Test name
Test status
Simulation time 469564057 ps
CPU time 0.89 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:38 PM PDT 24
Peak memory 196784 kb
Host smart-11383e5f-a100-4b7b-9562-12ecff1696c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471424253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.471424253
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3008311762
Short name T180
Test name
Test status
Simulation time 15765081278 ps
CPU time 10.76 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:47 PM PDT 24
Peak memory 192396 kb
Host smart-f88b7955-020b-457c-b711-f973cf157a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008311762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3008311762
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1100839426
Short name T16
Test name
Test status
Simulation time 2092221118 ps
CPU time 13.68 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:37 PM PDT 24
Peak memory 198676 kb
Host smart-5b8953fe-6099-4d3e-a055-6b5670c5d93b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100839426 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1100839426
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2656714337
Short name T162
Test name
Test status
Simulation time 8433055785 ps
CPU time 23.12 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 215024 kb
Host smart-3bc74d1b-3f4e-4d6b-b6e5-979bb46b6475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656714337 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2656714337
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1861272187
Short name T6
Test name
Test status
Simulation time 587677160 ps
CPU time 1.18 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 196736 kb
Host smart-f4a95d04-c065-4936-9a05-4057d5949ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861272187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1861272187
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2266828929
Short name T77
Test name
Test status
Simulation time 12773477960 ps
CPU time 21.95 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:47 PM PDT 24
Peak memory 206852 kb
Host smart-2f7b8aa3-49e1-448c-a456-9243453ce0c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266828929 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2266828929
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1459256512
Short name T168
Test name
Test status
Simulation time 87560010016 ps
CPU time 62.12 seconds
Started Aug 17 04:31:40 PM PDT 24
Finished Aug 17 04:32:42 PM PDT 24
Peak memory 193184 kb
Host smart-c2d5cff2-904a-442f-97f6-ccfad4520567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459256512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1459256512
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.715688814
Short name T184
Test name
Test status
Simulation time 361647325 ps
CPU time 1.1 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:39 PM PDT 24
Peak memory 196792 kb
Host smart-5f06ec3f-27df-4e52-9660-1051efdffdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715688814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.715688814
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3935324904
Short name T185
Test name
Test status
Simulation time 407350236 ps
CPU time 0.71 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 196720 kb
Host smart-63c2ce48-462a-4160-9647-5889d009fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935324904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3935324904
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.414810897
Short name T192
Test name
Test status
Simulation time 387770409 ps
CPU time 1.12 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:31:35 PM PDT 24
Peak memory 196784 kb
Host smart-8d4e070e-ff24-43d5-b16a-213da2f453ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414810897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.414810897
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2775921632
Short name T177
Test name
Test status
Simulation time 374477172 ps
CPU time 1.1 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196752 kb
Host smart-455d5ee4-a0e1-4891-abc2-8574032af764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775921632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2775921632
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2350042143
Short name T197
Test name
Test status
Simulation time 8433181062 ps
CPU time 15.08 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:43 PM PDT 24
Peak memory 196764 kb
Host smart-2c4e5bce-3eb0-4e03-b286-59425dbf7968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350042143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2350042143
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.856479341
Short name T195
Test name
Test status
Simulation time 7939193167 ps
CPU time 12.58 seconds
Started Aug 17 04:32:34 PM PDT 24
Finished Aug 17 04:32:47 PM PDT 24
Peak memory 198380 kb
Host smart-67034523-b35c-4086-97f4-0e9148068554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856479341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.856479341
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2566806125
Short name T191
Test name
Test status
Simulation time 446575521 ps
CPU time 0.76 seconds
Started Aug 17 04:31:52 PM PDT 24
Finished Aug 17 04:31:53 PM PDT 24
Peak memory 196752 kb
Host smart-b4ebfb0d-a623-433b-9b94-04ec4b57829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566806125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2566806125
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2274928315
Short name T175
Test name
Test status
Simulation time 581147521 ps
CPU time 0.93 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196824 kb
Host smart-6e8e6cb3-865f-4dbc-97fe-ad731f80d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274928315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2274928315
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1375899703
Short name T106
Test name
Test status
Simulation time 378335455 ps
CPU time 0.85 seconds
Started Aug 17 04:31:41 PM PDT 24
Finished Aug 17 04:31:42 PM PDT 24
Peak memory 196732 kb
Host smart-5929335b-438b-42a1-8448-06e5619ef7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375899703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1375899703
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1252632156
Short name T161
Test name
Test status
Simulation time 581392460 ps
CPU time 0.81 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 196896 kb
Host smart-8d0d55f0-4a3f-47e5-8ea1-d60e6449cb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252632156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1252632156
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3643945862
Short name T190
Test name
Test status
Simulation time 471914390 ps
CPU time 0.79 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 196716 kb
Host smart-f7650f88-ab7a-48ed-931b-afad307e1d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643945862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3643945862
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2430887837
Short name T173
Test name
Test status
Simulation time 546486301 ps
CPU time 0.68 seconds
Started Aug 17 04:31:28 PM PDT 24
Finished Aug 17 04:31:29 PM PDT 24
Peak memory 196684 kb
Host smart-5f53e878-98f4-4191-9fab-bdbe297b06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430887837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2430887837
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3852774417
Short name T186
Test name
Test status
Simulation time 512919176 ps
CPU time 0.76 seconds
Started Aug 17 04:31:56 PM PDT 24
Finished Aug 17 04:31:57 PM PDT 24
Peak memory 196792 kb
Host smart-78e7fcd8-9480-4083-9687-98d0fd75d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852774417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3852774417
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.609813941
Short name T124
Test name
Test status
Simulation time 303279111339 ps
CPU time 69.75 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:33:20 PM PDT 24
Peak memory 192040 kb
Host smart-c0313ab0-a2fb-47ae-8235-e8d676f63e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609813941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.609813941
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1102251135
Short name T27
Test name
Test status
Simulation time 432283507 ps
CPU time 0.73 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 196760 kb
Host smart-d25413e4-bde2-499d-b9a0-fdc35e186706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102251135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1102251135
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2870867802
Short name T3
Test name
Test status
Simulation time 497439536 ps
CPU time 1.01 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 196704 kb
Host smart-7c9109fa-1a97-4240-bf2d-40216146126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870867802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2870867802
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1545459929
Short name T179
Test name
Test status
Simulation time 551180854 ps
CPU time 0.62 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 196736 kb
Host smart-1cd1945a-4cc4-431a-9297-17f13bcf8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545459929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1545459929
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2425585695
Short name T357
Test name
Test status
Simulation time 684788578 ps
CPU time 1.05 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 183812 kb
Host smart-f73f9912-5b9a-423f-8eb0-bc0c92acdaa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425585695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2425585695
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3968073352
Short name T65
Test name
Test status
Simulation time 8781006576 ps
CPU time 4.33 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 183964 kb
Host smart-e263f5b4-63fc-41a0-9582-7fd995ccc3d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968073352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3968073352
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.486411792
Short name T313
Test name
Test status
Simulation time 592829451 ps
CPU time 0.97 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 197608 kb
Host smart-f3a72d5c-5737-4dc0-aeaa-1a273d18235c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486411792 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.486411792
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2365034503
Short name T325
Test name
Test status
Simulation time 444859393 ps
CPU time 0.84 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 183688 kb
Host smart-6fbcb890-ec31-4e28-80d5-d7c69512f628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365034503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2365034503
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3501934734
Short name T297
Test name
Test status
Simulation time 423667453 ps
CPU time 0.86 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 183508 kb
Host smart-b725536f-d9d5-44d3-84b8-070a936eb503
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501934734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3501934734
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2992998810
Short name T424
Test name
Test status
Simulation time 504710168 ps
CPU time 0.56 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:13 PM PDT 24
Peak memory 183548 kb
Host smart-03f352c2-1790-47be-b66f-f495f6d23cba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992998810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2992998810
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.746082988
Short name T352
Test name
Test status
Simulation time 2606303699 ps
CPU time 1.46 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 194740 kb
Host smart-f6d9e987-9912-44d6-b9df-30cb2d9554df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746082988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.746082988
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1901097745
Short name T291
Test name
Test status
Simulation time 874179840 ps
CPU time 1.18 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 198508 kb
Host smart-e2f59cc7-041f-470d-b45d-f3d155a4883c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901097745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1901097745
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4231666631
Short name T54
Test name
Test status
Simulation time 639170594 ps
CPU time 1.62 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 194292 kb
Host smart-89741328-472f-42c4-9f51-870f598c2a50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231666631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4231666631
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1530184484
Short name T74
Test name
Test status
Simulation time 6949151558 ps
CPU time 13.27 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 192160 kb
Host smart-722d2c3d-1e80-40b4-a595-0176c2991967
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530184484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1530184484
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2317412125
Short name T75
Test name
Test status
Simulation time 1479919820 ps
CPU time 1.6 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 193308 kb
Host smart-70148458-dc68-4493-9cfb-5e8244601d7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317412125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2317412125
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.348415818
Short name T323
Test name
Test status
Simulation time 360431651 ps
CPU time 1.27 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 197044 kb
Host smart-3c3b7d0d-e9a3-4c32-a720-7d40d028d9d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348415818 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.348415818
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.591616869
Short name T342
Test name
Test status
Simulation time 448331247 ps
CPU time 0.84 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 192392 kb
Host smart-ba07718a-59f2-47f5-9cbd-b4f7a9ceedb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591616869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.591616869
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3429725542
Short name T347
Test name
Test status
Simulation time 337834579 ps
CPU time 0.78 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 192864 kb
Host smart-1c4cac74-3a33-44d8-a383-ea8b0d6b023c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429725542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3429725542
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2196620504
Short name T300
Test name
Test status
Simulation time 347792307 ps
CPU time 0.71 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:09 PM PDT 24
Peak memory 183556 kb
Host smart-d42fe616-629c-4c33-867f-0cc532950490
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196620504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2196620504
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4095573639
Short name T353
Test name
Test status
Simulation time 491521123 ps
CPU time 0.71 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 183600 kb
Host smart-11cf8303-cffc-4b75-b350-ff570aa984a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095573639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4095573639
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1161606895
Short name T343
Test name
Test status
Simulation time 1602716260 ps
CPU time 2.67 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 191896 kb
Host smart-445c97b6-6658-4043-a7f8-0884eaf18c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161606895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1161606895
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.657236112
Short name T400
Test name
Test status
Simulation time 557127562 ps
CPU time 2.5 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 198516 kb
Host smart-bff2ff2c-7917-46cd-aa15-8096653d069b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657236112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.657236112
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.482643921
Short name T418
Test name
Test status
Simulation time 4031535505 ps
CPU time 2.4 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 196424 kb
Host smart-c3856d37-b202-4a29-a1f5-88e22aaeaa49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482643921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.482643921
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3892023188
Short name T339
Test name
Test status
Simulation time 291210628 ps
CPU time 1.14 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 196040 kb
Host smart-55797072-b0f7-4780-b806-98bed706dc54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892023188 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3892023188
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1678166849
Short name T59
Test name
Test status
Simulation time 502241832 ps
CPU time 0.82 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 193944 kb
Host smart-b66c611a-95b6-4ce6-b94d-f9d6d252495a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678166849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1678166849
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2995754535
Short name T374
Test name
Test status
Simulation time 358036937 ps
CPU time 0.68 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 192924 kb
Host smart-f924faf4-37bc-43d9-b060-b95c69728bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995754535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2995754535
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1501848930
Short name T423
Test name
Test status
Simulation time 2950213441 ps
CPU time 1.73 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 195232 kb
Host smart-da886ade-a09a-42c9-89ea-ba0f773f1772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501848930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1501848930
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1638156407
Short name T356
Test name
Test status
Simulation time 343744974 ps
CPU time 1.36 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 198480 kb
Host smart-ac643201-563b-4203-a421-e4ebd38360c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638156407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1638156407
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2159493845
Short name T44
Test name
Test status
Simulation time 4433738915 ps
CPU time 4.18 seconds
Started Aug 17 04:32:19 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 196772 kb
Host smart-f5ed08eb-8d87-4bdf-bbec-ce232c1aa911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159493845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2159493845
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.819668354
Short name T420
Test name
Test status
Simulation time 394810286 ps
CPU time 1.08 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 195368 kb
Host smart-420626ab-bedd-4e5b-bdf8-b67cd15a612d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819668354 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.819668354
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3842272525
Short name T58
Test name
Test status
Simulation time 449255948 ps
CPU time 1.26 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 193384 kb
Host smart-c414dc96-aae3-4749-abce-d0f8403a0ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842272525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3842272525
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4048201856
Short name T341
Test name
Test status
Simulation time 305120868 ps
CPU time 0.62 seconds
Started Aug 17 04:32:32 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 192856 kb
Host smart-05281f43-0ae1-41fa-bbf4-f08025352422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048201856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4048201856
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1133207841
Short name T393
Test name
Test status
Simulation time 2262334092 ps
CPU time 8.63 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 195056 kb
Host smart-f789c027-1b75-4968-846f-c7268d8c6222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133207841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1133207841
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.557600668
Short name T329
Test name
Test status
Simulation time 600333427 ps
CPU time 1.43 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 198328 kb
Host smart-eb26d1dd-0bf5-44ec-aba0-7c74568bad1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557600668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.557600668
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1144850031
Short name T369
Test name
Test status
Simulation time 4520721918 ps
CPU time 2.3 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 197836 kb
Host smart-8cd3136f-12de-4f06-a256-e1950bdeff57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144850031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1144850031
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1521640318
Short name T422
Test name
Test status
Simulation time 361532893 ps
CPU time 0.92 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 196524 kb
Host smart-8e0bdc80-ffcc-4898-af13-50c1a876d4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521640318 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1521640318
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2688113324
Short name T358
Test name
Test status
Simulation time 402787128 ps
CPU time 0.88 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 192912 kb
Host smart-87768940-d55d-4796-9aa8-937d9692959b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688113324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2688113324
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3182951394
Short name T294
Test name
Test status
Simulation time 496787784 ps
CPU time 1.28 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 183760 kb
Host smart-b6e363b2-182a-4648-aa8b-5218d1a3c085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182951394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3182951394
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2609024929
Short name T70
Test name
Test status
Simulation time 1516158358 ps
CPU time 1.62 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 192924 kb
Host smart-be413f4c-18f5-46e2-ae3d-2fd28359602a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609024929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2609024929
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4126168698
Short name T304
Test name
Test status
Simulation time 437604443 ps
CPU time 1.75 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 198520 kb
Host smart-166a728a-590f-4c3d-b481-29d69cd93475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126168698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4126168698
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1835753891
Short name T385
Test name
Test status
Simulation time 3964930474 ps
CPU time 3.85 seconds
Started Aug 17 04:32:36 PM PDT 24
Finished Aug 17 04:32:40 PM PDT 24
Peak memory 197516 kb
Host smart-53627d10-79b5-4740-873f-7949e044b89c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835753891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1835753891
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.467561348
Short name T40
Test name
Test status
Simulation time 609486847 ps
CPU time 0.66 seconds
Started Aug 17 04:32:31 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 195616 kb
Host smart-f1c0339e-6537-43dc-87af-5c7a9440cc0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467561348 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.467561348
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2216904255
Short name T416
Test name
Test status
Simulation time 388248955 ps
CPU time 0.63 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 192028 kb
Host smart-f6f394ff-980f-4a52-91a4-aa9d02455b64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216904255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2216904255
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2380505863
Short name T327
Test name
Test status
Simulation time 351572418 ps
CPU time 0.98 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 183652 kb
Host smart-56d4b749-644c-4a94-ad7e-06cbbba01493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380505863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2380505863
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2279932457
Short name T419
Test name
Test status
Simulation time 2114055637 ps
CPU time 4.6 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 194044 kb
Host smart-64e64733-861f-4a09-8b96-7d8e8cc711f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279932457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2279932457
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.676657727
Short name T322
Test name
Test status
Simulation time 431012144 ps
CPU time 1.47 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 197188 kb
Host smart-907ba6f1-6666-4fd1-a014-92a622425ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676657727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.676657727
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1373094680
Short name T402
Test name
Test status
Simulation time 8521191702 ps
CPU time 15.12 seconds
Started Aug 17 04:32:31 PM PDT 24
Finished Aug 17 04:32:47 PM PDT 24
Peak memory 198332 kb
Host smart-a24d55b3-9a5a-4073-b7ee-b396790c225d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373094680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1373094680
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4237925145
Short name T319
Test name
Test status
Simulation time 414041674 ps
CPU time 0.87 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 197312 kb
Host smart-fda2b93b-b53a-4bf8-acb8-9b3b6382f6c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237925145 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4237925145
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1995319952
Short name T72
Test name
Test status
Simulation time 363324698 ps
CPU time 0.84 seconds
Started Aug 17 04:32:45 PM PDT 24
Finished Aug 17 04:32:46 PM PDT 24
Peak memory 192008 kb
Host smart-29e727b2-d332-449a-8deb-6989abf1d360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995319952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1995319952
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2120439496
Short name T348
Test name
Test status
Simulation time 408440981 ps
CPU time 0.74 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 183244 kb
Host smart-d22756c3-ec57-4830-8c0e-76d6e8806c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120439496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2120439496
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1593404785
Short name T413
Test name
Test status
Simulation time 2194513563 ps
CPU time 3.16 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 195000 kb
Host smart-e994ad91-314d-4be6-9305-e6ef18e80f46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593404785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1593404785
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2788698247
Short name T303
Test name
Test status
Simulation time 469200001 ps
CPU time 1.99 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 198592 kb
Host smart-8dc95cea-357d-44dd-aab3-b05a75631bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788698247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2788698247
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.225277593
Short name T334
Test name
Test status
Simulation time 4638785086 ps
CPU time 2.5 seconds
Started Aug 17 04:32:31 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 197928 kb
Host smart-8b861f3b-1910-493f-bfdc-ce7c1edffd54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225277593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.225277593
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1343496648
Short name T333
Test name
Test status
Simulation time 515362342 ps
CPU time 1.31 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 196172 kb
Host smart-cec70733-911b-464b-ac4b-b4a62e7734f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343496648 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1343496648
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3199595805
Short name T64
Test name
Test status
Simulation time 322470128 ps
CPU time 1.04 seconds
Started Aug 17 04:32:43 PM PDT 24
Finished Aug 17 04:32:44 PM PDT 24
Peak memory 192968 kb
Host smart-26d9d5bc-c2aa-4ec3-982b-046e9938be05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199595805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3199595805
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2597276032
Short name T305
Test name
Test status
Simulation time 454922590 ps
CPU time 0.69 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 183644 kb
Host smart-a60f9280-14c3-4d45-89ad-f073c40dee23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597276032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2597276032
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1037438473
Short name T66
Test name
Test status
Simulation time 1256720855 ps
CPU time 1.3 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:32 PM PDT 24
Peak memory 193428 kb
Host smart-d735cb87-d4c0-4c01-bcaf-cccaa94585bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037438473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1037438473
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3543917462
Short name T296
Test name
Test status
Simulation time 638680275 ps
CPU time 1.62 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 198496 kb
Host smart-42de6200-d886-4831-83cc-28e87cf99695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543917462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3543917462
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1338720380
Short name T310
Test name
Test status
Simulation time 530587761 ps
CPU time 1.07 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 198404 kb
Host smart-6ab59bc1-a12d-470e-bc3c-b4435229b121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338720380 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1338720380
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.271754669
Short name T63
Test name
Test status
Simulation time 324498236 ps
CPU time 0.8 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 193072 kb
Host smart-be8d2d2a-e738-48b4-945f-362d69250a13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271754669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.271754669
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2898597700
Short name T380
Test name
Test status
Simulation time 336437205 ps
CPU time 1.04 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 183636 kb
Host smart-9b678443-550c-4f93-a2e9-5f87f18a27ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898597700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2898597700
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.825421832
Short name T68
Test name
Test status
Simulation time 2764087998 ps
CPU time 2.07 seconds
Started Aug 17 04:32:36 PM PDT 24
Finished Aug 17 04:32:38 PM PDT 24
Peak memory 194136 kb
Host smart-a3d5865b-4cce-4b06-9a0b-7e12134a0587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825421832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.825421832
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3895127014
Short name T425
Test name
Test status
Simulation time 673759119 ps
CPU time 1.4 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 198536 kb
Host smart-68628ab7-9686-41f2-b3b5-1c2974bcd954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895127014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3895127014
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3231307730
Short name T309
Test name
Test status
Simulation time 8520325937 ps
CPU time 5.13 seconds
Started Aug 17 04:32:45 PM PDT 24
Finished Aug 17 04:32:50 PM PDT 24
Peak memory 198468 kb
Host smart-c5772e8c-9a16-49ec-b831-abb123bc000e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231307730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3231307730
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4210411337
Short name T367
Test name
Test status
Simulation time 404023824 ps
CPU time 1.23 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 195136 kb
Host smart-82ddf935-e8b4-44bf-a12b-a1c7e90c65bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210411337 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4210411337
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3821375094
Short name T390
Test name
Test status
Simulation time 465157376 ps
CPU time 0.8 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 192928 kb
Host smart-556d24bd-4f0d-49c8-8e9b-e9040f0c0136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821375094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3821375094
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.466176497
Short name T372
Test name
Test status
Simulation time 539037446 ps
CPU time 0.71 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 183716 kb
Host smart-1e304015-d862-4c65-b042-c6406afd583d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466176497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.466176497
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.17453016
Short name T421
Test name
Test status
Simulation time 1040204924 ps
CPU time 0.94 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 193324 kb
Host smart-0e9a965e-76d8-4a31-b6c9-bc72d926a3a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17453016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_
timer_same_csr_outstanding.17453016
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1224741084
Short name T298
Test name
Test status
Simulation time 572650520 ps
CPU time 2.92 seconds
Started Aug 17 04:32:34 PM PDT 24
Finished Aug 17 04:32:37 PM PDT 24
Peak memory 198536 kb
Host smart-11809b94-fb4f-4a56-a5db-15ba510e5ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224741084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1224741084
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.906126162
Short name T43
Test name
Test status
Simulation time 8343019355 ps
CPU time 12.44 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:40 PM PDT 24
Peak memory 198220 kb
Host smart-c79f9d14-4687-45e7-9d74-985d7c55f206
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906126162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.906126162
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.104092313
Short name T403
Test name
Test status
Simulation time 305164834 ps
CPU time 1.11 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 195180 kb
Host smart-a974cf24-23d2-46b4-b11c-272d849942e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104092313 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.104092313
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1725232536
Short name T57
Test name
Test status
Simulation time 547427486 ps
CPU time 0.75 seconds
Started Aug 17 04:32:35 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 192032 kb
Host smart-2c56ec64-d71e-487e-8203-7bc142bbbb40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725232536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1725232536
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1769639658
Short name T375
Test name
Test status
Simulation time 514744809 ps
CPU time 0.7 seconds
Started Aug 17 04:32:58 PM PDT 24
Finished Aug 17 04:32:59 PM PDT 24
Peak memory 192904 kb
Host smart-6c1ef8f4-35c1-48f4-b8af-03523623cd41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769639658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1769639658
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3383549756
Short name T395
Test name
Test status
Simulation time 2739072983 ps
CPU time 2.12 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 193824 kb
Host smart-cfa19237-bcce-4f1e-8c30-c95687549f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383549756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3383549756
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.115320230
Short name T335
Test name
Test status
Simulation time 406300147 ps
CPU time 1.97 seconds
Started Aug 17 04:32:39 PM PDT 24
Finished Aug 17 04:32:41 PM PDT 24
Peak memory 198588 kb
Host smart-fad14f79-0faf-40c7-bf20-fc100b9a9b33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115320230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.115320230
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2213556008
Short name T41
Test name
Test status
Simulation time 478447205 ps
CPU time 1.26 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 195984 kb
Host smart-f037adfa-24ae-46c8-a14e-9f31e6dfcf02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213556008 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2213556008
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.426960163
Short name T73
Test name
Test status
Simulation time 569501109 ps
CPU time 0.71 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 193920 kb
Host smart-b83c8a45-be48-4f94-8960-979503d24821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426960163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.426960163
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2897988672
Short name T412
Test name
Test status
Simulation time 445952537 ps
CPU time 0.84 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 192924 kb
Host smart-5a01b019-9e47-4fbf-89c6-59d7cc2a3b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897988672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2897988672
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3723422939
Short name T71
Test name
Test status
Simulation time 2094367246 ps
CPU time 1.4 seconds
Started Aug 17 04:32:34 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 193908 kb
Host smart-d1412286-dfe6-4d1a-b392-e6d0eb855f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723422939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3723422939
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3362713485
Short name T288
Test name
Test status
Simulation time 514881748 ps
CPU time 2.11 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 198548 kb
Host smart-30bcdeb5-169a-4ac0-88ab-d6c570c10495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362713485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3362713485
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2867668910
Short name T391
Test name
Test status
Simulation time 9200774312 ps
CPU time 1.86 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 198204 kb
Host smart-d5eac7a9-ff55-4216-894f-1ee125f4dab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867668910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2867668910
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1478604955
Short name T388
Test name
Test status
Simulation time 400468542 ps
CPU time 1.22 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 193956 kb
Host smart-379b9fb6-1d47-4555-9631-70684c92a4ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478604955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1478604955
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2389964827
Short name T55
Test name
Test status
Simulation time 7332388197 ps
CPU time 3.83 seconds
Started Aug 17 04:32:35 PM PDT 24
Finished Aug 17 04:32:39 PM PDT 24
Peak memory 192204 kb
Host smart-0bcf530a-ac65-44d7-8a89-d92114f97ee4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389964827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2389964827
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3205332219
Short name T414
Test name
Test status
Simulation time 940992799 ps
CPU time 1.99 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 194020 kb
Host smart-0d6cc698-78d8-40ed-8fa2-09c34213c61f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205332219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3205332219
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1032029054
Short name T330
Test name
Test status
Simulation time 390701565 ps
CPU time 1.17 seconds
Started Aug 17 04:32:19 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 197188 kb
Host smart-cb735c88-17fd-4d5f-aeae-606e46952518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032029054 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1032029054
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2851158005
Short name T381
Test name
Test status
Simulation time 333920663 ps
CPU time 0.87 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 192900 kb
Host smart-883a16ea-5687-4259-be6b-e002c4034c5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851158005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2851158005
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2049515109
Short name T320
Test name
Test status
Simulation time 453564077 ps
CPU time 1.14 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 183700 kb
Host smart-73ae2068-9ce3-4893-9e47-7460dc5efc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049515109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2049515109
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2276443780
Short name T321
Test name
Test status
Simulation time 296618584 ps
CPU time 0.86 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 183572 kb
Host smart-565791bb-05de-42ac-8b14-5cfe9b48c368
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276443780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2276443780
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3406643297
Short name T314
Test name
Test status
Simulation time 413831461 ps
CPU time 1.08 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 183624 kb
Host smart-1bc149a4-c339-4911-b7e8-8b4c7df90028
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406643297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3406643297
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.998800903
Short name T408
Test name
Test status
Simulation time 1457586059 ps
CPU time 1.07 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 193464 kb
Host smart-86e4726f-d0cb-48cf-82a6-aa6dcd98ab88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998800903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.998800903
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2774429831
Short name T351
Test name
Test status
Simulation time 469909836 ps
CPU time 1.56 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 198488 kb
Host smart-f1cbf814-832b-41a0-b16e-88179ec9efb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774429831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2774429831
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2192392760
Short name T299
Test name
Test status
Simulation time 4451904384 ps
CPU time 7.12 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 197728 kb
Host smart-ca4f0f6b-667e-4afc-9de0-01dffffc7fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192392760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2192392760
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3254949422
Short name T354
Test name
Test status
Simulation time 507446249 ps
CPU time 0.68 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 183640 kb
Host smart-17ecaae6-9d42-4dd7-9344-9502ce24c81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254949422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3254949422
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3652732822
Short name T315
Test name
Test status
Simulation time 387387357 ps
CPU time 0.82 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 183764 kb
Host smart-e1b4d1ac-7cf1-459b-80cf-3e159834f6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652732822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3652732822
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1064635502
Short name T410
Test name
Test status
Simulation time 349023387 ps
CPU time 0.84 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 192860 kb
Host smart-9546505c-8fa8-43fc-b0d3-6eb2e15eedd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064635502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1064635502
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.263896357
Short name T331
Test name
Test status
Simulation time 387560549 ps
CPU time 0.77 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 183688 kb
Host smart-4649649d-d9ff-4b01-8bc6-1bc8efdade5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263896357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.263896357
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1359523158
Short name T392
Test name
Test status
Simulation time 443349833 ps
CPU time 0.58 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 192916 kb
Host smart-10a350d4-1cb4-45fc-a1a3-1b527db24ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359523158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1359523158
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3907025644
Short name T293
Test name
Test status
Simulation time 402219259 ps
CPU time 0.67 seconds
Started Aug 17 04:32:47 PM PDT 24
Finished Aug 17 04:32:48 PM PDT 24
Peak memory 183688 kb
Host smart-adf9612d-440a-4e20-af55-a08cf4d22c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907025644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3907025644
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3927015234
Short name T359
Test name
Test status
Simulation time 352403554 ps
CPU time 1.07 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 192832 kb
Host smart-634b7c12-f200-4d3e-aecc-8f9699e15caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927015234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3927015234
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2136706917
Short name T377
Test name
Test status
Simulation time 309843629 ps
CPU time 0.76 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 183704 kb
Host smart-2fbe0dc7-2d71-4723-9e36-b92cf025ac53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136706917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2136706917
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.644266259
Short name T378
Test name
Test status
Simulation time 476051823 ps
CPU time 1.16 seconds
Started Aug 17 04:32:33 PM PDT 24
Finished Aug 17 04:32:39 PM PDT 24
Peak memory 192884 kb
Host smart-8fa2aea8-3804-4038-aef7-5af4eaebe7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644266259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.644266259
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1684283105
Short name T368
Test name
Test status
Simulation time 350201005 ps
CPU time 1.01 seconds
Started Aug 17 04:32:36 PM PDT 24
Finished Aug 17 04:32:37 PM PDT 24
Peak memory 192856 kb
Host smart-edd6a7a9-9367-41ba-95a4-7c0328899254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684283105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1684283105
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4188651438
Short name T398
Test name
Test status
Simulation time 467534808 ps
CPU time 1.18 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 193140 kb
Host smart-478a24ff-f1bf-4fef-b9bd-3072a08f5872
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188651438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4188651438
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2372697058
Short name T61
Test name
Test status
Simulation time 10951662073 ps
CPU time 3.5 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 196192 kb
Host smart-a27a3112-53b0-4972-bc8b-bc2d416c5cec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372697058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2372697058
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.951468401
Short name T366
Test name
Test status
Simulation time 1435893765 ps
CPU time 2.42 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 192976 kb
Host smart-4301bbe3-2814-4277-ba8a-d3f616d865b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951468401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.951468401
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1678665566
Short name T365
Test name
Test status
Simulation time 352097674 ps
CPU time 1.09 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 196524 kb
Host smart-94d18129-7dac-46b3-a129-d39369336d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678665566 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1678665566
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3909204405
Short name T56
Test name
Test status
Simulation time 319105549 ps
CPU time 0.98 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 193256 kb
Host smart-c7b5e492-b92c-46b8-9c7d-03a8dd243e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909204405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3909204405
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2419072352
Short name T336
Test name
Test status
Simulation time 497724438 ps
CPU time 0.69 seconds
Started Aug 17 04:32:15 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 183728 kb
Host smart-68de96e2-1348-4e9a-afba-93241495d2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419072352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2419072352
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3953114829
Short name T307
Test name
Test status
Simulation time 287204343 ps
CPU time 0.99 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 183552 kb
Host smart-c73ca0f6-4d86-4289-bc23-fb358ecca82e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953114829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3953114829
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2257925514
Short name T317
Test name
Test status
Simulation time 470655709 ps
CPU time 0.68 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 182164 kb
Host smart-b4276ca9-da6c-4426-9821-811dc25b44e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257925514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2257925514
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.402719874
Short name T69
Test name
Test status
Simulation time 3158659652 ps
CPU time 1.73 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:32 PM PDT 24
Peak memory 195464 kb
Host smart-05394719-717d-4469-80f5-41bfda01ba70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402719874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.402719874
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.824850582
Short name T373
Test name
Test status
Simulation time 484833611 ps
CPU time 2.68 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 198620 kb
Host smart-c2a1459e-a06f-4781-826a-7d1073b78a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824850582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.824850582
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.687021411
Short name T198
Test name
Test status
Simulation time 8597643044 ps
CPU time 8.11 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 198296 kb
Host smart-debe2b84-5522-410b-8765-bad8eaa1bc48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687021411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.687021411
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2571861583
Short name T383
Test name
Test status
Simulation time 338091392 ps
CPU time 1 seconds
Started Aug 17 04:32:40 PM PDT 24
Finished Aug 17 04:32:41 PM PDT 24
Peak memory 192856 kb
Host smart-d06fafe3-bc76-4f6c-83fe-3fb561592711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571861583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2571861583
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.608605621
Short name T326
Test name
Test status
Simulation time 428789174 ps
CPU time 0.65 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:35 PM PDT 24
Peak memory 183640 kb
Host smart-047df249-7f28-4ebf-86f9-a85b557c5bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608605621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.608605621
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2140183109
Short name T290
Test name
Test status
Simulation time 427742388 ps
CPU time 1.12 seconds
Started Aug 17 04:32:31 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 183696 kb
Host smart-7877f6cd-ca54-4bda-8541-0f32b3dff95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140183109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2140183109
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1380048324
Short name T312
Test name
Test status
Simulation time 293102668 ps
CPU time 0.94 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 192864 kb
Host smart-9b68f2e3-e313-4e84-8071-715685c69d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380048324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1380048324
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3899410172
Short name T384
Test name
Test status
Simulation time 393993330 ps
CPU time 0.62 seconds
Started Aug 17 04:32:32 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 183644 kb
Host smart-4eaeed66-f93b-49ca-95e7-b7471c7f713e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899410172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3899410172
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1531812939
Short name T289
Test name
Test status
Simulation time 276859600 ps
CPU time 0.68 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 192884 kb
Host smart-b539a76b-31f2-41b2-b6da-3c93a7031f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531812939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1531812939
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2421535983
Short name T332
Test name
Test status
Simulation time 329587799 ps
CPU time 1.07 seconds
Started Aug 17 04:32:55 PM PDT 24
Finished Aug 17 04:32:56 PM PDT 24
Peak memory 183628 kb
Host smart-b4d2c5a5-0f20-48f6-b795-5fad7c95aa41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421535983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2421535983
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1192317913
Short name T397
Test name
Test status
Simulation time 511118265 ps
CPU time 0.7 seconds
Started Aug 17 04:32:32 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 192912 kb
Host smart-7e2d2f55-91ed-43ea-bdb3-874c61c46308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192317913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1192317913
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1102745212
Short name T316
Test name
Test status
Simulation time 502754931 ps
CPU time 0.71 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 183680 kb
Host smart-a32d443c-f086-4c9d-a6fb-380bb8059856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102745212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1102745212
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.547209030
Short name T287
Test name
Test status
Simulation time 380842949 ps
CPU time 0.79 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 183640 kb
Host smart-a2d8debb-c57c-4335-ac4a-1909774d44df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547209030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.547209030
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4252128700
Short name T338
Test name
Test status
Simulation time 517293507 ps
CPU time 1.33 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 193200 kb
Host smart-305150ac-d8c0-4d86-b7c1-11372ef38815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252128700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4252128700
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3860674927
Short name T328
Test name
Test status
Simulation time 7277636025 ps
CPU time 2.44 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 195684 kb
Host smart-90f94988-3704-4dfa-a50d-d6e885e4f00b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860674927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3860674927
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3934322240
Short name T324
Test name
Test status
Simulation time 879922707 ps
CPU time 1.21 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 183764 kb
Host smart-16a65980-1cf2-4730-b940-a09190640ae2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934322240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3934322240
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.175007421
Short name T394
Test name
Test status
Simulation time 392354547 ps
CPU time 1.18 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 196452 kb
Host smart-280195c8-a269-4b59-9875-f4822f28f5fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175007421 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.175007421
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3776592452
Short name T361
Test name
Test status
Simulation time 409012915 ps
CPU time 0.61 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 192912 kb
Host smart-429fd8a2-2354-4d28-b8a6-f22e4d8c1c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776592452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3776592452
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3925008380
Short name T370
Test name
Test status
Simulation time 378517232 ps
CPU time 1.11 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 183676 kb
Host smart-b29976e4-4e99-45ed-af63-02197d23efa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925008380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3925008380
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.689537187
Short name T406
Test name
Test status
Simulation time 483754161 ps
CPU time 0.56 seconds
Started Aug 17 04:32:17 PM PDT 24
Finished Aug 17 04:32:18 PM PDT 24
Peak memory 183604 kb
Host smart-d0efd577-711c-4285-83ae-931b5cf3a2d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689537187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.689537187
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2708206606
Short name T389
Test name
Test status
Simulation time 459411001 ps
CPU time 1.13 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 183500 kb
Host smart-774b12fc-a4ba-4788-8bb1-664424e3b9f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708206606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2708206606
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3255580826
Short name T382
Test name
Test status
Simulation time 2760205577 ps
CPU time 1.71 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 193784 kb
Host smart-8c48742f-7837-4df5-9ffd-b2489eb205ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255580826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3255580826
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3789252196
Short name T387
Test name
Test status
Simulation time 440734280 ps
CPU time 1.93 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 198516 kb
Host smart-de167284-94c4-482a-83fe-50ce6094bda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789252196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3789252196
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1908845596
Short name T302
Test name
Test status
Simulation time 8442936013 ps
CPU time 3.44 seconds
Started Aug 17 04:32:15 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 198320 kb
Host smart-bdeac9b4-6f9e-4cdd-8e0d-a7354bf24cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908845596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1908845596
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3064803131
Short name T379
Test name
Test status
Simulation time 459910927 ps
CPU time 0.96 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 183716 kb
Host smart-baeabf6f-f746-460e-828e-cc2061608f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064803131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3064803131
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1075400688
Short name T308
Test name
Test status
Simulation time 339897031 ps
CPU time 1.09 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 183660 kb
Host smart-11cbd83b-5741-4b38-870a-38568abe5062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075400688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1075400688
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.573248703
Short name T295
Test name
Test status
Simulation time 415522312 ps
CPU time 0.68 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 183632 kb
Host smart-d382a619-baf4-49a2-9647-350500294edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573248703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.573248703
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2971316426
Short name T427
Test name
Test status
Simulation time 345023947 ps
CPU time 1.05 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 183684 kb
Host smart-88e2a39d-db46-4c7e-88d6-ab6c6d595fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971316426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2971316426
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.918516529
Short name T362
Test name
Test status
Simulation time 437430658 ps
CPU time 0.66 seconds
Started Aug 17 04:32:40 PM PDT 24
Finished Aug 17 04:32:41 PM PDT 24
Peak memory 183696 kb
Host smart-28776eb1-09fa-4b60-8f3f-f959c9a73d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918516529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.918516529
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3745020981
Short name T401
Test name
Test status
Simulation time 443244428 ps
CPU time 0.73 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 183676 kb
Host smart-61359289-6707-4664-a507-881dbbb67400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745020981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3745020981
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1504048852
Short name T426
Test name
Test status
Simulation time 430973394 ps
CPU time 0.94 seconds
Started Aug 17 04:32:32 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 183648 kb
Host smart-eb4e7338-785a-4cdb-9034-5393ecbf5aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504048852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1504048852
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3190674328
Short name T318
Test name
Test status
Simulation time 496303862 ps
CPU time 1.27 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 183256 kb
Host smart-a730a0a9-0dd1-4a80-b1d7-690edac72e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190674328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3190674328
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.981584554
Short name T340
Test name
Test status
Simulation time 427501999 ps
CPU time 1.19 seconds
Started Aug 17 04:32:51 PM PDT 24
Finished Aug 17 04:32:53 PM PDT 24
Peak memory 183700 kb
Host smart-1e1ba9c6-ea48-432c-adbc-1c9e7c5dad65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981584554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.981584554
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.721799544
Short name T360
Test name
Test status
Simulation time 454965991 ps
CPU time 0.8 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:29 PM PDT 24
Peak memory 192636 kb
Host smart-8f7ecbfc-29f8-4fac-b859-40a802b0dc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721799544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.721799544
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2567417113
Short name T355
Test name
Test status
Simulation time 587144701 ps
CPU time 0.99 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 198104 kb
Host smart-acb1719f-27d6-40c4-8e92-965763850e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567417113 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2567417113
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.270815784
Short name T39
Test name
Test status
Simulation time 512089771 ps
CPU time 1.21 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 194052 kb
Host smart-e2fad7b9-9861-4c71-be74-b3bd79021134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270815784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.270815784
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2243590723
Short name T417
Test name
Test status
Simulation time 345498109 ps
CPU time 0.66 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:23 PM PDT 24
Peak memory 192892 kb
Host smart-da4d3388-1910-41ec-8025-5a1a251b1b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243590723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2243590723
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4150405309
Short name T349
Test name
Test status
Simulation time 1916228471 ps
CPU time 3.14 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 193076 kb
Host smart-af4c7d73-c7d9-405b-a4c3-110f0e1ab630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150405309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4150405309
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.94723399
Short name T344
Test name
Test status
Simulation time 406350205 ps
CPU time 1.53 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 198476 kb
Host smart-99a619b6-bec7-4467-9bbf-b6d5f0a275bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94723399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.94723399
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1445207811
Short name T409
Test name
Test status
Simulation time 4226273665 ps
CPU time 2.4 seconds
Started Aug 17 04:32:39 PM PDT 24
Finished Aug 17 04:32:42 PM PDT 24
Peak memory 197852 kb
Host smart-e3af1adb-65fa-497c-839f-a911cb341f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445207811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1445207811
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3876012187
Short name T350
Test name
Test status
Simulation time 496797353 ps
CPU time 0.83 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:28 PM PDT 24
Peak memory 196152 kb
Host smart-019b0d42-56d7-484d-be30-da4559359469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876012187 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3876012187
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1038880512
Short name T62
Test name
Test status
Simulation time 325755866 ps
CPU time 0.83 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 193148 kb
Host smart-9de6c265-2af2-442f-9dfb-145019f63b55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038880512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1038880512
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1465851858
Short name T346
Test name
Test status
Simulation time 461928888 ps
CPU time 0.84 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 183680 kb
Host smart-0b086197-807b-469a-a749-4611b4275b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465851858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1465851858
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.321120715
Short name T404
Test name
Test status
Simulation time 1572195702 ps
CPU time 1.41 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 191948 kb
Host smart-82b539ee-c5ec-4ab4-b253-7507d273f1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321120715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.321120715
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.388387723
Short name T376
Test name
Test status
Simulation time 387626104 ps
CPU time 1.67 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 198540 kb
Host smart-9ac224d8-fbaa-47a6-922d-3bad01c00eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388387723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.388387723
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3760671599
Short name T364
Test name
Test status
Simulation time 4516841531 ps
CPU time 2.38 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 197852 kb
Host smart-84a5b71c-199a-4c24-9bb9-e18b31469aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760671599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3760671599
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2503237739
Short name T411
Test name
Test status
Simulation time 339769759 ps
CPU time 1.05 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 195940 kb
Host smart-96919671-c15b-4b6f-b3cc-4957fb2b887a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503237739 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2503237739
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.232683272
Short name T399
Test name
Test status
Simulation time 379308013 ps
CPU time 1.08 seconds
Started Aug 17 04:32:33 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 192032 kb
Host smart-4e738fcc-ab03-4750-a4a5-ace17c32d34e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232683272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.232683272
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.770852434
Short name T337
Test name
Test status
Simulation time 325115822 ps
CPU time 0.63 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:18 PM PDT 24
Peak memory 182756 kb
Host smart-0d2b2366-5900-46b8-b2d6-63447b92488a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770852434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.770852434
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2796121461
Short name T396
Test name
Test status
Simulation time 1659404465 ps
CPU time 1.97 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 193908 kb
Host smart-5aa4a055-61d1-43a9-8c63-78a27f3a4780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796121461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2796121461
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2140107499
Short name T292
Test name
Test status
Simulation time 601517403 ps
CPU time 2.61 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 198600 kb
Host smart-9b3e0af1-9abc-4d36-9821-4f80813bef95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140107499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2140107499
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4025481199
Short name T194
Test name
Test status
Simulation time 7992510477 ps
CPU time 12.21 seconds
Started Aug 17 04:32:25 PM PDT 24
Finished Aug 17 04:32:38 PM PDT 24
Peak memory 198140 kb
Host smart-226c5754-a8f7-492e-a21c-b31130b966ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025481199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.4025481199
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3289877557
Short name T415
Test name
Test status
Simulation time 424981342 ps
CPU time 0.84 seconds
Started Aug 17 04:32:29 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 196616 kb
Host smart-5d49913f-a225-4fc9-a894-b0c9d7568e17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289877557 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3289877557
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.4177322330
Short name T60
Test name
Test status
Simulation time 539160456 ps
CPU time 0.68 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 192976 kb
Host smart-fc13f3d9-5744-4cf0-8a43-23828cab452b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177322330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4177322330
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.816430131
Short name T386
Test name
Test status
Simulation time 289567186 ps
CPU time 0.9 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 183648 kb
Host smart-2bc16357-6c71-49f4-9a24-8ca37748b5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816430131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.816430131
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1441547036
Short name T345
Test name
Test status
Simulation time 1097640592 ps
CPU time 2.97 seconds
Started Aug 17 04:32:27 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 192940 kb
Host smart-5b72d9ff-1cb2-4917-90ba-a0e9783c2b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441547036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1441547036
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.75891617
Short name T405
Test name
Test status
Simulation time 955982936 ps
CPU time 1.84 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 198528 kb
Host smart-3cbaaa88-9963-423c-ad3b-8e0acae8fcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75891617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.75891617
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1909648785
Short name T301
Test name
Test status
Simulation time 4711427835 ps
CPU time 2.3 seconds
Started Aug 17 04:32:28 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 196840 kb
Host smart-1ccb2ae6-e3d1-4bf7-be43-9b5b2bd1cc77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909648785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1909648785
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3827978097
Short name T311
Test name
Test status
Simulation time 672975356 ps
CPU time 0.77 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 196824 kb
Host smart-77e5db24-54e0-4cae-ae62-ba54586991c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827978097 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3827978097
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2434279826
Short name T371
Test name
Test status
Simulation time 536215455 ps
CPU time 0.74 seconds
Started Aug 17 04:32:30 PM PDT 24
Finished Aug 17 04:32:31 PM PDT 24
Peak memory 193144 kb
Host smart-01027657-25b8-4521-8190-8855983f2711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434279826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2434279826
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.857138845
Short name T407
Test name
Test status
Simulation time 314533138 ps
CPU time 0.64 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:27 PM PDT 24
Peak memory 192908 kb
Host smart-2fabf760-7cff-4d0d-9341-ad3c06498f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857138845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.857138845
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2296223826
Short name T363
Test name
Test status
Simulation time 2660996131 ps
CPU time 3.46 seconds
Started Aug 17 04:32:26 PM PDT 24
Finished Aug 17 04:32:30 PM PDT 24
Peak memory 194072 kb
Host smart-3c53ca12-9cae-40f5-be28-f9505dc57fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296223826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2296223826
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1362775915
Short name T306
Test name
Test status
Simulation time 517126880 ps
CPU time 1.61 seconds
Started Aug 17 04:32:21 PM PDT 24
Finished Aug 17 04:32:22 PM PDT 24
Peak memory 198572 kb
Host smart-eda6f0c9-0ae7-4d53-9bda-04ee0d4e06c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362775915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1362775915
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1581658319
Short name T196
Test name
Test status
Simulation time 4644213270 ps
CPU time 2.66 seconds
Started Aug 17 04:32:33 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 197528 kb
Host smart-ec09c3fb-1fb5-4a2e-baaf-5e9dba791cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581658319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1581658319
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3779003209
Short name T256
Test name
Test status
Simulation time 20262845814 ps
CPU time 9.01 seconds
Started Aug 17 04:31:42 PM PDT 24
Finished Aug 17 04:31:51 PM PDT 24
Peak memory 192024 kb
Host smart-e242114b-1273-4f54-879f-c400d2e0f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779003209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3779003209
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3910803689
Short name T271
Test name
Test status
Simulation time 508730130 ps
CPU time 1.36 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 192024 kb
Host smart-ec466c5f-58de-4242-a62c-2da9b0ceb560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910803689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3910803689
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3016702673
Short name T13
Test name
Test status
Simulation time 1965343038 ps
CPU time 20.69 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:32:02 PM PDT 24
Peak memory 198600 kb
Host smart-fb8db739-72c5-44d0-a468-5c95df2a030e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016702673 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3016702673
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3404281714
Short name T188
Test name
Test status
Simulation time 594446509 ps
CPU time 1.02 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:38 PM PDT 24
Peak memory 196788 kb
Host smart-e4e6acbc-ef3c-4c1f-a49a-44631dfe249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404281714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3404281714
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3166628930
Short name T222
Test name
Test status
Simulation time 37949610028 ps
CPU time 14.62 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:47 PM PDT 24
Peak memory 191964 kb
Host smart-366b3e41-679b-4744-a71b-834ef18200ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166628930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3166628930
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2320539746
Short name T18
Test name
Test status
Simulation time 4442542266 ps
CPU time 7.2 seconds
Started Aug 17 04:31:30 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 215976 kb
Host smart-54403a7d-7a55-4048-8d6a-a8ca6e0369cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320539746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2320539746
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1892778300
Short name T284
Test name
Test status
Simulation time 509180541 ps
CPU time 1.28 seconds
Started Aug 17 04:31:31 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 192008 kb
Host smart-4cfcca8e-bf14-4e19-9905-99541c16faab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892778300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1892778300
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3554567215
Short name T30
Test name
Test status
Simulation time 9944241347 ps
CPU time 8.12 seconds
Started Aug 17 04:31:46 PM PDT 24
Finished Aug 17 04:31:54 PM PDT 24
Peak memory 192012 kb
Host smart-60ebd0d1-45e3-43d4-bfb9-b87361d27ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554567215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3554567215
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3326083303
Short name T268
Test name
Test status
Simulation time 523320179 ps
CPU time 0.73 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:40 PM PDT 24
Peak memory 191996 kb
Host smart-17cd2012-a441-4221-a4c3-411b2ec17305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326083303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3326083303
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4159375297
Short name T80
Test name
Test status
Simulation time 762703821 ps
CPU time 3.11 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:39 PM PDT 24
Peak memory 206800 kb
Host smart-e87806c9-b325-4b5c-ac99-f41632606692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159375297 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4159375297
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2632876407
Short name T49
Test name
Test status
Simulation time 31399604664 ps
CPU time 11.44 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:47 PM PDT 24
Peak memory 196968 kb
Host smart-af9a05a0-bdbd-43b7-ab84-3443c0743705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632876407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2632876407
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2532167816
Short name T276
Test name
Test status
Simulation time 598343273 ps
CPU time 0.8 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:46 PM PDT 24
Peak memory 196784 kb
Host smart-deebad56-33ac-43b3-a6da-42dda0931159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532167816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2532167816
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3676218341
Short name T262
Test name
Test status
Simulation time 37585303466 ps
CPU time 15.82 seconds
Started Aug 17 04:31:48 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 192040 kb
Host smart-b3bf92a1-4a31-4fbf-aaef-2428c92562eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676218341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3676218341
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3378026342
Short name T274
Test name
Test status
Simulation time 499966274 ps
CPU time 0.92 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 191948 kb
Host smart-50079113-3325-4653-a1a1-7571453738c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378026342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3378026342
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.437518015
Short name T277
Test name
Test status
Simulation time 46638620932 ps
CPU time 17.58 seconds
Started Aug 17 04:32:01 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 197036 kb
Host smart-f65f6611-5b8e-4eda-8b4c-aa5dc4cc45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437518015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.437518015
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.874240357
Short name T5
Test name
Test status
Simulation time 412845407 ps
CPU time 0.69 seconds
Started Aug 17 04:31:30 PM PDT 24
Finished Aug 17 04:31:30 PM PDT 24
Peak memory 191936 kb
Host smart-0ca850b6-53cb-4d1e-acb6-dd64ab46b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874240357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.874240357
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2162415944
Short name T285
Test name
Test status
Simulation time 53133452317 ps
CPU time 19.48 seconds
Started Aug 17 04:31:44 PM PDT 24
Finished Aug 17 04:32:04 PM PDT 24
Peak memory 192076 kb
Host smart-67d45aa7-ad7f-4b69-acf9-7d0e91975a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162415944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2162415944
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1091633742
Short name T225
Test name
Test status
Simulation time 508140296 ps
CPU time 0.83 seconds
Started Aug 17 04:31:50 PM PDT 24
Finished Aug 17 04:31:51 PM PDT 24
Peak memory 192036 kb
Host smart-780f7be0-366f-4899-b35a-740451d61051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091633742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1091633742
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1979214989
Short name T218
Test name
Test status
Simulation time 29956036582 ps
CPU time 36.32 seconds
Started Aug 17 04:31:44 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 192064 kb
Host smart-5af5b499-31b9-4641-8690-f1f16a722b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979214989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1979214989
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3642039683
Short name T252
Test name
Test status
Simulation time 631616714 ps
CPU time 0.67 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 191956 kb
Host smart-99036716-854b-4ef5-a98f-929cca95a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642039683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3642039683
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2093984184
Short name T230
Test name
Test status
Simulation time 26493413095 ps
CPU time 11.33 seconds
Started Aug 17 04:31:51 PM PDT 24
Finished Aug 17 04:32:02 PM PDT 24
Peak memory 192072 kb
Host smart-51af04be-e794-4bdb-9ea9-300de97378be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093984184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2093984184
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3331565092
Short name T269
Test name
Test status
Simulation time 410976052 ps
CPU time 0.66 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:38 PM PDT 24
Peak memory 196812 kb
Host smart-9ef0a9d7-7fec-443e-94ce-f23e9773ed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331565092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3331565092
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.754336675
Short name T286
Test name
Test status
Simulation time 9845329390 ps
CPU time 15.54 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:55 PM PDT 24
Peak memory 197044 kb
Host smart-7ba93bb7-936b-4e1e-ab93-6b1ed101904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754336675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.754336675
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1132032120
Short name T251
Test name
Test status
Simulation time 409232006 ps
CPU time 1.17 seconds
Started Aug 17 04:31:43 PM PDT 24
Finished Aug 17 04:31:44 PM PDT 24
Peak memory 196792 kb
Host smart-666b6bc1-97b9-4a15-84fd-9f03231358d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132032120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1132032120
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.345203241
Short name T261
Test name
Test status
Simulation time 4740858259 ps
CPU time 4.05 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:40 PM PDT 24
Peak memory 195956 kb
Host smart-67081dfa-69e5-458c-b315-e180fcd5cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345203241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.345203241
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3432742084
Short name T217
Test name
Test status
Simulation time 381702859 ps
CPU time 1.1 seconds
Started Aug 17 04:31:36 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 196788 kb
Host smart-5abffaf4-25f0-4bde-9ba2-4a13c71352c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432742084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3432742084
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.181499158
Short name T227
Test name
Test status
Simulation time 12119602913 ps
CPU time 10.45 seconds
Started Aug 17 04:31:52 PM PDT 24
Finished Aug 17 04:32:02 PM PDT 24
Peak memory 192020 kb
Host smart-e0aebe32-7e71-4611-b9fd-fe0e0a5605b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181499158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.181499158
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2548988573
Short name T283
Test name
Test status
Simulation time 445671294 ps
CPU time 1.22 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:36 PM PDT 24
Peak memory 191984 kb
Host smart-ae741889-a3a9-4575-ba45-40ce8c218cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548988573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2548988573
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1433790603
Short name T236
Test name
Test status
Simulation time 21141122655 ps
CPU time 32.96 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:32:07 PM PDT 24
Peak memory 197048 kb
Host smart-30b7b208-add8-4256-8f61-2341ae4e855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433790603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1433790603
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3885202226
Short name T21
Test name
Test status
Simulation time 8189177048 ps
CPU time 5.91 seconds
Started Aug 17 04:31:38 PM PDT 24
Finished Aug 17 04:31:44 PM PDT 24
Peak memory 216084 kb
Host smart-8dfc7cd3-0428-41f6-ab4f-be7b8ba47937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885202226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3885202226
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.356580293
Short name T250
Test name
Test status
Simulation time 396409742 ps
CPU time 0.82 seconds
Started Aug 17 04:31:30 PM PDT 24
Finished Aug 17 04:31:31 PM PDT 24
Peak memory 196660 kb
Host smart-50071a80-41cd-48a9-8f61-1786d7bc8a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356580293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.356580293
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3446049270
Short name T29
Test name
Test status
Simulation time 60429796073 ps
CPU time 78.9 seconds
Started Aug 17 04:31:58 PM PDT 24
Finished Aug 17 04:33:17 PM PDT 24
Peak memory 197008 kb
Host smart-26d260b8-42d8-4a3e-8b9d-43ceca3f4b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446049270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3446049270
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1369650697
Short name T2
Test name
Test status
Simulation time 604590487 ps
CPU time 1.06 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 192044 kb
Host smart-3cb4d7ba-38f3-4cd3-979d-08a0ca24be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369650697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1369650697
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3806261293
Short name T264
Test name
Test status
Simulation time 38116237547 ps
CPU time 10.21 seconds
Started Aug 17 04:32:01 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 192016 kb
Host smart-a3a765ef-41e4-45a8-b593-ff2ba62213ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806261293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3806261293
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1453849861
Short name T270
Test name
Test status
Simulation time 432788524 ps
CPU time 0.67 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:06 PM PDT 24
Peak memory 191972 kb
Host smart-6698acfd-863e-4cf6-ae6a-c23d99c506aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453849861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1453849861
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1078474472
Short name T282
Test name
Test status
Simulation time 2013864345 ps
CPU time 14.16 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 206788 kb
Host smart-4abbd386-173a-452b-81a5-20879559b386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078474472 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1078474472
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2606944267
Short name T51
Test name
Test status
Simulation time 20475908211 ps
CPU time 2.54 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:10 PM PDT 24
Peak memory 192032 kb
Host smart-61d24b2f-8c59-4b2b-b432-f7d50e9d12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606944267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2606944267
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3982774321
Short name T243
Test name
Test status
Simulation time 448009565 ps
CPU time 1.28 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:07 PM PDT 24
Peak memory 191956 kb
Host smart-85a4e4ce-2e7a-43a3-9a11-81d0c77879b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982774321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3982774321
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.114447112
Short name T202
Test name
Test status
Simulation time 32034244376 ps
CPU time 48.27 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:32:26 PM PDT 24
Peak memory 192060 kb
Host smart-4275a41a-27b5-4a17-adc3-e5a08067a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114447112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.114447112
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1053355051
Short name T228
Test name
Test status
Simulation time 497242039 ps
CPU time 1.25 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 192088 kb
Host smart-c2482717-0bd6-4bac-9749-685b6ec3fe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053355051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1053355051
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2749410220
Short name T233
Test name
Test status
Simulation time 29450658240 ps
CPU time 10.76 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 192364 kb
Host smart-f102791f-1562-4cf0-891b-4d593258cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749410220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2749410220
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4151853835
Short name T242
Test name
Test status
Simulation time 533701690 ps
CPU time 0.74 seconds
Started Aug 17 04:31:37 PM PDT 24
Finished Aug 17 04:31:38 PM PDT 24
Peak memory 192032 kb
Host smart-b95b9f23-7927-47bc-9b36-68ffe208176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151853835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4151853835
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2670549867
Short name T239
Test name
Test status
Simulation time 32990488279 ps
CPU time 25.12 seconds
Started Aug 17 04:32:10 PM PDT 24
Finished Aug 17 04:32:36 PM PDT 24
Peak memory 197032 kb
Host smart-c15012cc-1580-4a6a-843c-2f7fc0a005e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670549867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2670549867
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.666449777
Short name T238
Test name
Test status
Simulation time 526764576 ps
CPU time 1.34 seconds
Started Aug 17 04:31:50 PM PDT 24
Finished Aug 17 04:31:52 PM PDT 24
Peak memory 191940 kb
Host smart-9cb459a4-e0e3-4f34-a508-b7d4663ca3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666449777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.666449777
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.994927103
Short name T263
Test name
Test status
Simulation time 8425626324 ps
CPU time 13.72 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 196992 kb
Host smart-7bad54ac-425e-411e-a1f6-dc50d10258da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994927103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.994927103
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1369605570
Short name T48
Test name
Test status
Simulation time 441215625 ps
CPU time 1.19 seconds
Started Aug 17 04:31:52 PM PDT 24
Finished Aug 17 04:31:54 PM PDT 24
Peak memory 196792 kb
Host smart-8919e6a0-bc91-4ddd-87aa-8805b76d436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369605570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1369605570
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2000631311
Short name T211
Test name
Test status
Simulation time 45256390549 ps
CPU time 65.04 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:33:08 PM PDT 24
Peak memory 192068 kb
Host smart-ffd0718a-bdcd-465c-ab8f-7974d938ce5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000631311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2000631311
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4022442300
Short name T204
Test name
Test status
Simulation time 416592994 ps
CPU time 0.72 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 196748 kb
Host smart-f4a035ed-7af2-4056-8607-2e53e4a5c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022442300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4022442300
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2981353790
Short name T260
Test name
Test status
Simulation time 27031380860 ps
CPU time 36.69 seconds
Started Aug 17 04:31:58 PM PDT 24
Finished Aug 17 04:32:35 PM PDT 24
Peak memory 192092 kb
Host smart-1e9d3304-41b3-4c93-abf8-8ae2c45ca6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981353790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2981353790
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1156823770
Short name T231
Test name
Test status
Simulation time 427544113 ps
CPU time 0.73 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:06 PM PDT 24
Peak memory 196812 kb
Host smart-9972d34f-8de4-42bc-9efa-3f5dabe3b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156823770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1156823770
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.729052714
Short name T281
Test name
Test status
Simulation time 42022142901 ps
CPU time 67.88 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:33:12 PM PDT 24
Peak memory 192076 kb
Host smart-47d06309-d718-433a-945c-f71b4054ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729052714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.729052714
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1650419177
Short name T267
Test name
Test status
Simulation time 570379537 ps
CPU time 0.77 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:40 PM PDT 24
Peak memory 196756 kb
Host smart-d83eec11-f3a4-4298-aef3-a4e31f5df1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650419177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1650419177
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3732103167
Short name T253
Test name
Test status
Simulation time 5592789095 ps
CPU time 4.46 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 192084 kb
Host smart-b952714d-ebe2-4168-85bc-a5fefb23c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732103167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3732103167
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2618024348
Short name T19
Test name
Test status
Simulation time 4189152584 ps
CPU time 6.43 seconds
Started Aug 17 04:31:29 PM PDT 24
Finished Aug 17 04:31:35 PM PDT 24
Peak memory 215668 kb
Host smart-5c26c934-7b21-46fb-a7b9-b7cea7c8f82c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618024348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2618024348
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2151778311
Short name T25
Test name
Test status
Simulation time 600026207 ps
CPU time 1.47 seconds
Started Aug 17 04:31:28 PM PDT 24
Finished Aug 17 04:31:30 PM PDT 24
Peak memory 196808 kb
Host smart-9ef78069-901c-4c35-8bf1-90ac5076d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151778311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2151778311
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1090207874
Short name T215
Test name
Test status
Simulation time 14325757448 ps
CPU time 9.91 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 192080 kb
Host smart-8d0f5e7b-c221-4152-9f8f-6419a14205b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090207874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1090207874
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3150351584
Short name T209
Test name
Test status
Simulation time 390270768 ps
CPU time 1.1 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:08 PM PDT 24
Peak memory 196788 kb
Host smart-98346ded-dee3-4b2b-b5e4-5ef3fd745d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150351584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3150351584
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.289303861
Short name T189
Test name
Test status
Simulation time 439486933 ps
CPU time 0.76 seconds
Started Aug 17 04:32:24 PM PDT 24
Finished Aug 17 04:32:25 PM PDT 24
Peak memory 196752 kb
Host smart-4721a716-78ec-45bd-b516-85d0e6856018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289303861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.289303861
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3582319068
Short name T229
Test name
Test status
Simulation time 41598054126 ps
CPU time 14.51 seconds
Started Aug 17 04:32:04 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 197072 kb
Host smart-1a764aa1-bdec-48c8-b798-a1c38a7d488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582319068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3582319068
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3716889647
Short name T240
Test name
Test status
Simulation time 538812396 ps
CPU time 1.28 seconds
Started Aug 17 04:32:15 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 192088 kb
Host smart-bb2fd949-1c11-48fc-8447-0f8a7679d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716889647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3716889647
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2257268444
Short name T201
Test name
Test status
Simulation time 37436846991 ps
CPU time 51.16 seconds
Started Aug 17 04:31:52 PM PDT 24
Finished Aug 17 04:32:43 PM PDT 24
Peak memory 192088 kb
Host smart-5f2f9612-dd9e-40ff-87e5-799d24719312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257268444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2257268444
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.605370024
Short name T220
Test name
Test status
Simulation time 444303216 ps
CPU time 1.13 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:15 PM PDT 24
Peak memory 196776 kb
Host smart-49e7b4ea-3c23-48c0-acf3-0a4f3df8d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605370024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.605370024
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2606073042
Short name T273
Test name
Test status
Simulation time 24569049874 ps
CPU time 35.63 seconds
Started Aug 17 04:32:14 PM PDT 24
Finished Aug 17 04:32:50 PM PDT 24
Peak memory 192080 kb
Host smart-e7ad0746-d020-4fc0-b6f6-43883b0fea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606073042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2606073042
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4153725367
Short name T265
Test name
Test status
Simulation time 523989743 ps
CPU time 1.42 seconds
Started Aug 17 04:32:03 PM PDT 24
Finished Aug 17 04:32:05 PM PDT 24
Peak memory 192004 kb
Host smart-9a48cc06-0ecb-43e5-b50c-2aa1dbbda5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153725367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4153725367
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3146760327
Short name T248
Test name
Test status
Simulation time 37315521520 ps
CPU time 27.21 seconds
Started Aug 17 04:31:57 PM PDT 24
Finished Aug 17 04:32:24 PM PDT 24
Peak memory 192000 kb
Host smart-166f35ec-43bd-4aca-8a70-02107892fa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146760327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3146760327
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1275207994
Short name T249
Test name
Test status
Simulation time 592416524 ps
CPU time 0.86 seconds
Started Aug 17 04:32:00 PM PDT 24
Finished Aug 17 04:32:01 PM PDT 24
Peak memory 192048 kb
Host smart-7d2ba6ec-d83d-4102-a257-d5f81f925ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275207994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1275207994
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.671364465
Short name T234
Test name
Test status
Simulation time 31368016176 ps
CPU time 28.6 seconds
Started Aug 17 04:31:42 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 192092 kb
Host smart-eeff767f-3c4b-4ccb-a2da-5d3a14dc3394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671364465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.671364465
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2903043602
Short name T244
Test name
Test status
Simulation time 406624680 ps
CPU time 0.72 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:09 PM PDT 24
Peak memory 191948 kb
Host smart-0c67d266-d5b8-4289-8326-bbccd1205091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903043602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2903043602
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2166223236
Short name T23
Test name
Test status
Simulation time 7332166214 ps
CPU time 3.51 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:16 PM PDT 24
Peak memory 197072 kb
Host smart-3f300dbb-0085-40a4-8985-ce052f0479b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166223236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2166223236
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2667470564
Short name T232
Test name
Test status
Simulation time 518258234 ps
CPU time 0.77 seconds
Started Aug 17 04:31:50 PM PDT 24
Finished Aug 17 04:31:51 PM PDT 24
Peak memory 192012 kb
Host smart-6118783c-be5c-4ed1-8375-34e4db492255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667470564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2667470564
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2943629217
Short name T159
Test name
Test status
Simulation time 493570126 ps
CPU time 0.77 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:06 PM PDT 24
Peak memory 196752 kb
Host smart-f05b3d8e-f58a-432b-806d-66298975c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943629217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2943629217
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1567713475
Short name T208
Test name
Test status
Simulation time 1779910775 ps
CPU time 2.98 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:19 PM PDT 24
Peak memory 191996 kb
Host smart-8303ad9e-285f-4248-8ead-8da28048fb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567713475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1567713475
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.295775504
Short name T205
Test name
Test status
Simulation time 483606719 ps
CPU time 0.9 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:13 PM PDT 24
Peak memory 192068 kb
Host smart-130cb112-b3bc-46fc-b9c3-1cc0609b6e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295775504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.295775504
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1080289604
Short name T275
Test name
Test status
Simulation time 27580970509 ps
CPU time 42.18 seconds
Started Aug 17 04:32:19 PM PDT 24
Finished Aug 17 04:33:01 PM PDT 24
Peak memory 192020 kb
Host smart-5f00c63a-20b4-45d5-839a-a96f5948f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080289604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1080289604
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2861941423
Short name T33
Test name
Test status
Simulation time 546868710 ps
CPU time 0.76 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:07 PM PDT 24
Peak memory 191968 kb
Host smart-f772f17d-6f64-4849-9f91-b50fa0d40486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861941423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2861941423
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3106085542
Short name T245
Test name
Test status
Simulation time 5393813530 ps
CPU time 7.13 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:20 PM PDT 24
Peak memory 192056 kb
Host smart-462d7e37-7426-44f2-879e-d1a9fde8c3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106085542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3106085542
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3368840712
Short name T224
Test name
Test status
Simulation time 584415003 ps
CPU time 0.75 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:08 PM PDT 24
Peak memory 192004 kb
Host smart-872c234c-c996-4ac7-92fb-2912556303d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368840712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3368840712
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.414171212
Short name T199
Test name
Test status
Simulation time 10408230306 ps
CPU time 1.59 seconds
Started Aug 17 04:31:46 PM PDT 24
Finished Aug 17 04:31:48 PM PDT 24
Peak memory 192076 kb
Host smart-2a74f6d9-3f67-4643-b10c-16db4b112fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414171212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.414171212
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.75753726
Short name T20
Test name
Test status
Simulation time 7832968231 ps
CPU time 1.47 seconds
Started Aug 17 04:31:40 PM PDT 24
Finished Aug 17 04:31:42 PM PDT 24
Peak memory 216136 kb
Host smart-c3a7f873-c45a-425c-b373-c0dd2288bcb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75753726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.75753726
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.275089291
Short name T206
Test name
Test status
Simulation time 525376242 ps
CPU time 0.93 seconds
Started Aug 17 04:31:51 PM PDT 24
Finished Aug 17 04:31:52 PM PDT 24
Peak memory 192068 kb
Host smart-51481d1e-5a15-44f0-acff-fac46396a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275089291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.275089291
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.651192560
Short name T278
Test name
Test status
Simulation time 9743827130 ps
CPU time 13.81 seconds
Started Aug 17 04:32:07 PM PDT 24
Finished Aug 17 04:32:21 PM PDT 24
Peak memory 197068 kb
Host smart-c2078512-6b4e-4b4b-a72e-cca75f659dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651192560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.651192560
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.21153683
Short name T255
Test name
Test status
Simulation time 370580294 ps
CPU time 0.83 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 191988 kb
Host smart-770db408-7b2d-4464-9d50-cb59dc031c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21153683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.21153683
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.327424370
Short name T258
Test name
Test status
Simulation time 15372159808 ps
CPU time 9.8 seconds
Started Aug 17 04:32:08 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 191992 kb
Host smart-8cd6058a-26bd-49b5-8994-6402aa75dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327424370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.327424370
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1157970561
Short name T226
Test name
Test status
Simulation time 593120795 ps
CPU time 0.98 seconds
Started Aug 17 04:32:13 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 191988 kb
Host smart-eda686fd-415b-4f6f-ac4c-a846a56411c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157970561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1157970561
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2372976391
Short name T214
Test name
Test status
Simulation time 16032756473 ps
CPU time 26.08 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:35 PM PDT 24
Peak memory 192044 kb
Host smart-e27787a9-352c-4027-86f1-311ec9a104d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372976391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2372976391
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2136692220
Short name T247
Test name
Test status
Simulation time 427811827 ps
CPU time 0.83 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:06 PM PDT 24
Peak memory 196780 kb
Host smart-c87c06d8-8862-49de-be77-633a73e77c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136692220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2136692220
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3190114476
Short name T213
Test name
Test status
Simulation time 31184808239 ps
CPU time 23.47 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:35 PM PDT 24
Peak memory 192056 kb
Host smart-9ea35794-ee25-4ddc-9c27-82656ca05b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190114476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3190114476
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1840097097
Short name T15
Test name
Test status
Simulation time 546696975 ps
CPU time 1.25 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:10 PM PDT 24
Peak memory 191984 kb
Host smart-7d9460bd-00f7-4959-8f47-4e73c03a63e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840097097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1840097097
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1078705959
Short name T279
Test name
Test status
Simulation time 15438623315 ps
CPU time 20.82 seconds
Started Aug 17 04:32:22 PM PDT 24
Finished Aug 17 04:32:43 PM PDT 24
Peak memory 197092 kb
Host smart-a9093d86-98a3-4a9b-bf1e-535eaaa48ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078705959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1078705959
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3496994033
Short name T221
Test name
Test status
Simulation time 468987996 ps
CPU time 0.98 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 191992 kb
Host smart-87fe4739-286e-45cd-b77d-09307610d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496994033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3496994033
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2949118081
Short name T200
Test name
Test status
Simulation time 14910673886 ps
CPU time 5.62 seconds
Started Aug 17 04:32:06 PM PDT 24
Finished Aug 17 04:32:11 PM PDT 24
Peak memory 192132 kb
Host smart-ee5cab0c-e819-445a-af55-95245d5860f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949118081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2949118081
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3597675048
Short name T259
Test name
Test status
Simulation time 367077118 ps
CPU time 1.06 seconds
Started Aug 17 04:32:12 PM PDT 24
Finished Aug 17 04:32:14 PM PDT 24
Peak memory 192000 kb
Host smart-cfb9f0b1-cc69-4c39-b552-4ddad8b87815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597675048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3597675048
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.876209043
Short name T266
Test name
Test status
Simulation time 584445268 ps
CPU time 1.18 seconds
Started Aug 17 04:32:02 PM PDT 24
Finished Aug 17 04:32:03 PM PDT 24
Peak memory 197016 kb
Host smart-84c79360-2840-4366-a30f-1621c629b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876209043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.876209043
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.277655011
Short name T212
Test name
Test status
Simulation time 425950936 ps
CPU time 1.15 seconds
Started Aug 17 04:32:11 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 191944 kb
Host smart-b74e3cc2-8fec-4566-a369-01729af0cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277655011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.277655011
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.361129854
Short name T4
Test name
Test status
Simulation time 58777144704 ps
CPU time 18.98 seconds
Started Aug 17 04:32:18 PM PDT 24
Finished Aug 17 04:32:37 PM PDT 24
Peak memory 192044 kb
Host smart-20120940-84c2-4afb-85ca-24091191d3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361129854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.361129854
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4161448367
Short name T207
Test name
Test status
Simulation time 630297006 ps
CPU time 0.81 seconds
Started Aug 17 04:32:09 PM PDT 24
Finished Aug 17 04:32:10 PM PDT 24
Peak memory 196776 kb
Host smart-49485980-9396-44e7-b16c-e4c3e518d86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161448367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4161448367
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2013146943
Short name T219
Test name
Test status
Simulation time 18441846202 ps
CPU time 29.26 seconds
Started Aug 17 04:32:20 PM PDT 24
Finished Aug 17 04:32:49 PM PDT 24
Peak memory 197080 kb
Host smart-2dcb5a35-5a86-430f-95c9-919984b50151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013146943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2013146943
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3073800921
Short name T241
Test name
Test status
Simulation time 583595435 ps
CPU time 1.08 seconds
Started Aug 17 04:32:02 PM PDT 24
Finished Aug 17 04:32:03 PM PDT 24
Peak memory 196760 kb
Host smart-acfc0445-e31f-42e7-8452-debcd8122c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073800921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3073800921
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.189750720
Short name T257
Test name
Test status
Simulation time 1157537189 ps
CPU time 7.01 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:12 PM PDT 24
Peak memory 214012 kb
Host smart-d08b8e49-4389-4d24-8d94-a1f2e7bd8c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189750720 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.189750720
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1480316495
Short name T235
Test name
Test status
Simulation time 38542716364 ps
CPU time 11.57 seconds
Started Aug 17 04:32:23 PM PDT 24
Finished Aug 17 04:32:34 PM PDT 24
Peak memory 197060 kb
Host smart-8364b3e5-d8d9-4fa2-b7e6-b9dcb4c3e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480316495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1480316495
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1027857018
Short name T210
Test name
Test status
Simulation time 513752572 ps
CPU time 0.75 seconds
Started Aug 17 04:32:16 PM PDT 24
Finished Aug 17 04:32:17 PM PDT 24
Peak memory 191988 kb
Host smart-5925a328-e500-4fba-9798-4538be93e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027857018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1027857018
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.661030941
Short name T8
Test name
Test status
Simulation time 39139625542 ps
CPU time 54.56 seconds
Started Aug 17 04:31:44 PM PDT 24
Finished Aug 17 04:32:39 PM PDT 24
Peak memory 197064 kb
Host smart-f5be91fa-1357-48db-b673-b1ee850c01e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661030941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.661030941
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2851599279
Short name T216
Test name
Test status
Simulation time 456889196 ps
CPU time 0.79 seconds
Started Aug 17 04:31:42 PM PDT 24
Finished Aug 17 04:31:43 PM PDT 24
Peak memory 191968 kb
Host smart-0665fc1a-8d50-45f6-9558-b9dd4d2fbf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851599279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2851599279
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3732214489
Short name T272
Test name
Test status
Simulation time 56478632313 ps
CPU time 75.94 seconds
Started Aug 17 04:31:38 PM PDT 24
Finished Aug 17 04:32:54 PM PDT 24
Peak memory 191992 kb
Host smart-518e9b97-d712-4233-ba20-863a2a94cae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732214489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3732214489
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3520135727
Short name T223
Test name
Test status
Simulation time 384537070 ps
CPU time 1.07 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 191964 kb
Host smart-bd5d332e-f367-441e-a350-afb63a60971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520135727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3520135727
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3534093822
Short name T26
Test name
Test status
Simulation time 17835784056 ps
CPU time 12.16 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:45 PM PDT 24
Peak memory 192040 kb
Host smart-5563b462-af61-409f-9912-159199c02747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534093822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3534093822
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3348658630
Short name T246
Test name
Test status
Simulation time 426486852 ps
CPU time 0.83 seconds
Started Aug 17 04:31:32 PM PDT 24
Finished Aug 17 04:31:33 PM PDT 24
Peak memory 196732 kb
Host smart-755f7f86-4130-4cbf-b86e-437faf7e8fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348658630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3348658630
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.905956195
Short name T237
Test name
Test status
Simulation time 35768716416 ps
CPU time 58.61 seconds
Started Aug 17 04:31:34 PM PDT 24
Finished Aug 17 04:32:33 PM PDT 24
Peak memory 192088 kb
Host smart-04c879d1-bc48-4445-b88c-69ea402a928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905956195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.905956195
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.744193157
Short name T280
Test name
Test status
Simulation time 568302202 ps
CPU time 1.45 seconds
Started Aug 17 04:31:39 PM PDT 24
Finished Aug 17 04:31:41 PM PDT 24
Peak memory 191928 kb
Host smart-6133e106-7f93-457d-bf1f-a734df052f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744193157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.744193157
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1814965307
Short name T254
Test name
Test status
Simulation time 35266019390 ps
CPU time 48.35 seconds
Started Aug 17 04:32:05 PM PDT 24
Finished Aug 17 04:32:53 PM PDT 24
Peak memory 197008 kb
Host smart-66d84c9d-7897-4985-a947-9e4eb5114ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814965307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1814965307
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2245103097
Short name T203
Test name
Test status
Simulation time 371114383 ps
CPU time 1.09 seconds
Started Aug 17 04:31:35 PM PDT 24
Finished Aug 17 04:31:37 PM PDT 24
Peak memory 191980 kb
Host smart-00ecdd26-e6bf-4f5c-b977-2c6ff024f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245103097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2245103097
Directory /workspace/9.aon_timer_smoke/latest
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