Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18255	1			T1	12		T2	12		T3	12
bark[1]	239	1			T88	14		T96	21		T167	89
bark[2]	456	1			T13	14		T35	14		T96	26
bark[3]	343	1			T96	31		T103	21		T125	5
bark[4]	254	1			T86	21		T47	21		T32	14
bark[5]	402	1			T109	78		T190	14		T101	35
bark[6]	237	1			T16	14		T35	57		T162	14
bark[7]	433	1			T14	21		T87	21		T47	164
bark[8]	137	1			T114	88		T132	7		T180	21
bark[9]	305	1			T17	111		T110	14		T104	5
bark[10]	729	1			T6	21		T87	62		T49	114
bark[11]	313	1			T17	86		T87	21		T26	21
bark[12]	195	1			T14	21		T34	62		T50	21
bark[13]	230	1			T15	51		T49	5		T96	21
bark[14]	300	1			T34	21		T47	7		T52	21
bark[15]	191	1			T35	21		T186	14		T133	31
bark[16]	315	1			T35	21		T157	14		T131	14
bark[17]	206	1			T165	14		T114	31		T133	47
bark[18]	265	1			T11	14		T14	21		T50	21
bark[19]	815	1			T35	21		T18	21		T48	245
bark[20]	278	1			T87	21		T189	14		T125	134
bark[21]	279	1			T17	141		T179	14		T127	21
bark[22]	478	1			T123	26		T151	21		T114	196
bark[23]	279	1			T136	30		T101	21		T175	14
bark[24]	807	1			T10	14		T13	21		T86	98
bark[25]	420	1			T87	57		T50	115		T167	14
bark[26]	483	1			T35	21		T24	14		T178	14
bark[27]	165	1			T181	14		T177	14		T130	21
bark[28]	237	1			T17	5		T152	14		T50	21
bark[29]	461	1			T154	14		T109	69		T29	21
bark[30]	253	1			T4	14		T13	30		T117	21
bark[31]	515	1			T35	21		T158	14		T109	14
bark_0	4551	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17624	1			T1	11		T2	11		T3	11
bite[1]	494	1			T15	21		T34	13		T35	57
bite[2]	214	1			T14	21		T52	21		T192	13
bite[3]	143	1			T96	26		T136	21		T101	35
bite[4]	236	1			T34	21		T47	6		T114	31
bite[5]	474	1			T48	244		T136	55		T185	21
bite[6]	388	1			T10	13		T50	21		T144	198
bite[7]	226	1			T123	98		T117	21		T187	13
bite[8]	115	1			T86	21		T87	21		T108	21
bite[9]	599	1			T50	114		T109	34		T114	21
bite[10]	823	1			T48	21		T49	113		T50	21
bite[11]	172	1			T13	13		T136	13		T103	6
bite[12]	323	1			T47	21		T189	13		T201	4
bite[13]	316	1			T102	21		T125	21		T183	60
bite[14]	456	1			T47	163		T151	21		T127	21
bite[15]	253	1			T123	4		T131	13		T166	13
bite[16]	500	1			T6	21		T50	162		T96	21
bite[17]	152	1			T16	13		T13	30		T174	13
bite[18]	103	1			T81	61		T142	21		T97	21
bite[19]	200	1			T15	30		T179	13		T32	13
bite[20]	179	1			T17	21		T35	21		T152	13
bite[21]	638	1			T17	85		T35	13		T88	13
bite[22]	817	1			T35	21		T18	21		T109	69
bite[23]	393	1			T14	21		T87	77		T146	118
bite[24]	213	1			T50	21		T96	30		T146	21
bite[25]	615	1			T11	13		T87	21		T109	78
bite[26]	650	1			T17	140		T35	21		T26	21
bite[27]	338	1			T13	21		T34	48		T35	21
bite[28]	352	1			T17	114		T136	13		T83	46
bite[29]	196	1			T49	4		T167	51		T136	21
bite[30]	163	1			T96	21		T157	13		T102	21
bite[31]	406	1			T14	21		T35	21		T86	98
bite_0	5055	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29786

1

T1

19

T2

19

T3

19

auto[1]

4040

1

T6

66

T14

34

T15

18

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	318	1			T12	2		T48	9		T26	49
prescale[1]	293	1			T15	40		T50	57		T127	28
prescale[2]	295	1			T6	19		T17	2		T47	88
prescale[3]	547	1			T96	24		T136	2		T114	2
prescale[4]	229	1			T17	62		T47	54		T49	2
prescale[5]	258	1			T54	9		T17	2		T86	72
prescale[6]	643	1			T1	9		T6	23		T47	19
prescale[7]	329	1			T3	9		T6	24		T12	2
prescale[8]	542	1			T13	19		T87	68		T48	2
prescale[9]	221	1			T15	9		T18	68		T29	19
prescale[10]	372	1			T86	19		T46	2		T26	47
prescale[11]	555	1			T15	32		T17	53		T49	21
prescale[12]	762	1			T2	9		T34	28		T35	57
prescale[13]	327	1			T202	9		T51	2		T96	45
prescale[14]	406	1			T13	32		T35	23		T89	9
prescale[15]	539	1			T34	23		T17	60		T87	19
prescale[16]	398	1			T34	40		T17	2		T30	9
prescale[17]	359	1			T5	9		T14	9		T17	67
prescale[18]	490	1			T48	147		T29	19		T203	9
prescale[19]	174	1			T17	2		T87	9		T204	2
prescale[20]	285	1			T47	43		T205	9		T206	9
prescale[21]	454	1			T45	9		T86	23		T50	9
prescale[22]	888	1			T6	19		T7	9		T9	9
prescale[23]	128	1			T14	32		T55	9		T51	2
prescale[24]	451	1			T17	62		T50	19		T127	135
prescale[25]	447	1			T117	19		T114	2		T207	9
prescale[26]	292	1			T35	19		T109	44		T29	19
prescale[27]	269	1			T6	19		T17	53		T51	2
prescale[28]	441	1			T109	32		T133	165		T125	2
prescale[29]	638	1			T13	58		T14	79		T17	9
prescale[30]	504	1			T34	24		T50	108		T52	2
prescale[31]	348	1			T34	19		T50	70		T109	19
prescale_0	20624	1			T1	10		T2	10		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22807

1

T1

19

T2

19

T3

9

auto[1]

11019

1

T3

10

T4

12

T5

10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

33826

1

T1

19

T2

19

T3

19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19053	1			T1	14		T2	14		T3	14
wkup[1]	98	1			T189	15		T185	21		T159	41
wkup[2]	208	1			T50	21		T186	15		T146	21
wkup[3]	176	1			T34	15		T167	21		T101	56
wkup[4]	150	1			T17	6		T48	45		T125	21
wkup[5]	289	1			T14	21		T15	21		T165	15
wkup[6]	103	1			T86	26		T167	21		T183	26
wkup[7]	137	1			T17	15		T47	44		T51	6
wkup[8]	267	1			T17	15		T26	45		T123	21
wkup[9]	233	1			T35	21		T87	26		T88	15
wkup[10]	137	1			T87	26		T48	21		T117	21
wkup[11]	207	1			T47	15		T50	21		T127	15
wkup[12]	223	1			T114	30		T133	21		T125	21
wkup[13]	111	1			T17	21		T32	15		T104	6
wkup[14]	141	1			T34	21		T123	6		T146	21
wkup[15]	206	1			T13	15		T136	30		T81	21
wkup[16]	147	1			T50	48		T167	15		T110	15
wkup[17]	187	1			T108	51		T141	21		T164	21
wkup[18]	182	1			T50	21		T29	21		T96	21
wkup[19]	93	1			T109	15		T101	21		T127	21
wkup[20]	119	1			T103	26		T176	21		T107	21
wkup[21]	194	1			T13	21		T48	21		T81	31
wkup[22]	187	1			T14	21		T47	21		T109	21
wkup[23]	156	1			T136	42		T114	31		T131	15
wkup[24]	164	1			T17	30		T35	21		T47	21
wkup[25]	159	1			T17	42		T96	21		T114	26
wkup[26]	198	1			T17	42		T154	15		T136	15
wkup[27]	128	1			T103	21		T144	21		T85	8
wkup[28]	289	1			T15	30		T18	21		T48	21
wkup[29]	199	1			T35	15		T146	8		T114	35
wkup[30]	92	1			T127	35		T80	21		T134	21
wkup[31]	123	1			T50	39		T117	21		T161	42
wkup[32]	126	1			T51	21		T114	21		T125	21
wkup[33]	147	1			T17	30		T166	15		T125	30
wkup[34]	165	1			T17	21		T103	8		T183	21
wkup[35]	120	1			T175	15		T159	21		T108	21
wkup[36]	247	1			T34	48		T50	35		T153	15
wkup[37]	287	1			T13	30		T17	42		T35	21
wkup[38]	182	1			T6	21		T16	15		T176	26
wkup[39]	95	1			T14	21		T87	21		T50	21
wkup[40]	57	1			T117	21		T103	15		T171	21
wkup[41]	187	1			T174	15		T123	21		T146	21
wkup[42]	274	1			T114	21		T103	35		T125	21
wkup[43]	231	1			T15	30		T86	21		T26	35
wkup[44]	167	1			T35	21		T52	21		T172	15
wkup[45]	95	1			T47	8		T93	15		T201	6
wkup[46]	255	1			T24	15		T127	21		T80	48
wkup[47]	217	1			T48	30		T109	21		T183	21
wkup[48]	147	1			T50	21		T96	21		T114	21
wkup[49]	120	1			T4	15		T14	21		T151	21
wkup[50]	93	1			T158	15		T102	21		T160	21
wkup[51]	175	1			T151	21		T80	35		T144	21
wkup[52]	297	1			T10	15		T152	15		T47	21
wkup[53]	244	1			T17	21		T87	21		T48	21
wkup[54]	159	1			T35	21		T50	21		T109	21
wkup[55]	198	1			T49	6		T167	30		T102	21
wkup[56]	173	1			T50	21		T96	21		T101	21
wkup[57]	233	1			T48	21		T96	21		T117	21
wkup[58]	84	1			T119	21		T107	21		T115	21
wkup[59]	214	1			T179	15		T29	21		T52	21
wkup[60]	230	1			T49	40		T50	8		T109	21
wkup[61]	362	1			T15	21		T109	21		T181	15
wkup[62]	190	1			T11	15		T87	21		T160	21
wkup[63]	140	1			T17	21		T35	21		T146	15
wkup_0	3559	1			T1	5		T2	5		T3	5