Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.35 99.33 95.61 100.00 98.40 99.51 43.27


Total test records in report: 420
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T288 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3065646228 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:25 PM PDT 24 400907763 ps
T43 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3518925592 Aug 18 04:22:03 PM PDT 24 Aug 18 04:22:04 PM PDT 24 384328248 ps
T38 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4005170298 Aug 18 04:19:36 PM PDT 24 Aug 18 04:19:37 PM PDT 24 608661059 ps
T289 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2796183370 Aug 18 04:23:06 PM PDT 24 Aug 18 04:23:07 PM PDT 24 410462750 ps
T44 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1735934966 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:32 PM PDT 24 1326715434 ps
T290 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1197235026 Aug 18 04:22:56 PM PDT 24 Aug 18 04:22:58 PM PDT 24 702029971 ps
T39 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.292659024 Aug 18 04:21:45 PM PDT 24 Aug 18 04:21:50 PM PDT 24 4320086878 ps
T291 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4152975945 Aug 18 04:21:45 PM PDT 24 Aug 18 04:21:47 PM PDT 24 709109551 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.650058799 Aug 18 04:22:02 PM PDT 24 Aug 18 04:22:05 PM PDT 24 1866213476 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2047999967 Aug 18 04:19:36 PM PDT 24 Aug 18 04:19:40 PM PDT 24 1824564599 ps
T73 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2143850982 Aug 18 04:18:18 PM PDT 24 Aug 18 04:18:19 PM PDT 24 2504196130 ps
T79 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4549440 Aug 18 04:18:55 PM PDT 24 Aug 18 04:18:57 PM PDT 24 495765603 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2710616914 Aug 18 04:21:52 PM PDT 24 Aug 18 04:21:53 PM PDT 24 301815753 ps
T293 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1642668327 Aug 18 04:23:02 PM PDT 24 Aug 18 04:23:03 PM PDT 24 439291531 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2255140871 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:55 PM PDT 24 1092664125 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1170157738 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:24 PM PDT 24 296171533 ps
T75 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2263352376 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:31 PM PDT 24 1229581431 ps
T295 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3970178164 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 325516069 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.191144615 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:30 PM PDT 24 309336921 ps
T297 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4147888884 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 443097370 ps
T76 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1679321841 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:28 PM PDT 24 2504358318 ps
T56 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2479223204 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:53 PM PDT 24 437565918 ps
T298 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.72189488 Aug 18 04:22:56 PM PDT 24 Aug 18 04:22:57 PM PDT 24 318928652 ps
T299 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2187634213 Aug 18 04:22:31 PM PDT 24 Aug 18 04:22:32 PM PDT 24 514729537 ps
T208 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4039173309 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:31 PM PDT 24 705063088 ps
T77 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3600986443 Aug 18 04:20:14 PM PDT 24 Aug 18 04:20:21 PM PDT 24 2854547785 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2599713727 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:20 PM PDT 24 1007296500 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1349297028 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:24 PM PDT 24 304357016 ps
T301 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1825095665 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:55 PM PDT 24 475548823 ps
T302 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4169758485 Aug 18 04:21:38 PM PDT 24 Aug 18 04:21:41 PM PDT 24 453645835 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1453943966 Aug 18 04:22:59 PM PDT 24 Aug 18 04:23:00 PM PDT 24 433326199 ps
T304 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2948767309 Aug 18 04:22:44 PM PDT 24 Aug 18 04:22:45 PM PDT 24 431039064 ps
T305 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.909103166 Aug 18 04:23:03 PM PDT 24 Aug 18 04:23:05 PM PDT 24 421630113 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3387015484 Aug 18 04:21:43 PM PDT 24 Aug 18 04:21:45 PM PDT 24 848616708 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2929336202 Aug 18 04:22:56 PM PDT 24 Aug 18 04:23:01 PM PDT 24 5089201605 ps
T78 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3454068283 Aug 18 04:22:43 PM PDT 24 Aug 18 04:22:46 PM PDT 24 1477213043 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1200385683 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:25 PM PDT 24 702067142 ps
T308 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1351789983 Aug 18 04:23:13 PM PDT 24 Aug 18 04:23:14 PM PDT 24 491739483 ps
T309 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2904088770 Aug 18 04:22:31 PM PDT 24 Aug 18 04:22:32 PM PDT 24 367866005 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2535731491 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:54 PM PDT 24 395708404 ps
T311 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3026005628 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:53 PM PDT 24 498948050 ps
T40 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3867620986 Aug 18 04:19:09 PM PDT 24 Aug 18 04:19:11 PM PDT 24 4486038255 ps
T41 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2456607277 Aug 18 04:23:01 PM PDT 24 Aug 18 04:23:05 PM PDT 24 8673462453 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2671675837 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:53 PM PDT 24 541911190 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3888406391 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:31 PM PDT 24 461264126 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1391085700 Aug 18 04:17:35 PM PDT 24 Aug 18 04:17:36 PM PDT 24 458301857 ps
T313 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.709476546 Aug 18 04:22:59 PM PDT 24 Aug 18 04:23:01 PM PDT 24 426583330 ps
T314 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1697357368 Aug 18 04:23:00 PM PDT 24 Aug 18 04:23:01 PM PDT 24 353535895 ps
T315 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3037909997 Aug 18 04:23:02 PM PDT 24 Aug 18 04:23:03 PM PDT 24 456601590 ps
T316 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3405046744 Aug 18 04:23:01 PM PDT 24 Aug 18 04:23:02 PM PDT 24 284054470 ps
T317 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.696244728 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 413854160 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2433205953 Aug 18 04:18:32 PM PDT 24 Aug 18 04:18:35 PM PDT 24 576806033 ps
T198 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.739676923 Aug 18 04:22:28 PM PDT 24 Aug 18 04:22:36 PM PDT 24 4289335088 ps
T319 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3249888077 Aug 18 04:19:13 PM PDT 24 Aug 18 04:19:14 PM PDT 24 341128560 ps
T320 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.177584617 Aug 18 04:19:50 PM PDT 24 Aug 18 04:19:52 PM PDT 24 623150924 ps
T321 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3760570814 Aug 18 04:18:42 PM PDT 24 Aug 18 04:18:44 PM PDT 24 365006131 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2459276803 Aug 18 04:22:21 PM PDT 24 Aug 18 04:22:23 PM PDT 24 460255305 ps
T195 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.521626756 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:58 PM PDT 24 4138995135 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.141974364 Aug 18 04:22:28 PM PDT 24 Aug 18 04:22:30 PM PDT 24 679858887 ps
T324 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4253602704 Aug 18 04:23:04 PM PDT 24 Aug 18 04:23:05 PM PDT 24 609621095 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1838182148 Aug 18 04:22:13 PM PDT 24 Aug 18 04:22:14 PM PDT 24 1981206762 ps
T326 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3835302787 Aug 18 04:22:50 PM PDT 24 Aug 18 04:22:51 PM PDT 24 443686015 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2365624550 Aug 18 04:22:02 PM PDT 24 Aug 18 04:22:03 PM PDT 24 443512089 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3560130747 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:55 PM PDT 24 357735345 ps
T329 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.729627017 Aug 18 04:21:44 PM PDT 24 Aug 18 04:21:46 PM PDT 24 416791871 ps
T330 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1804794061 Aug 18 04:22:25 PM PDT 24 Aug 18 04:22:27 PM PDT 24 945108558 ps
T331 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.376207189 Aug 18 04:21:48 PM PDT 24 Aug 18 04:21:50 PM PDT 24 279671137 ps
T332 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2939246660 Aug 18 04:22:58 PM PDT 24 Aug 18 04:22:59 PM PDT 24 540591930 ps
T333 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3187696064 Aug 18 04:22:49 PM PDT 24 Aug 18 04:22:53 PM PDT 24 8174266019 ps
T334 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.543270668 Aug 18 04:23:01 PM PDT 24 Aug 18 04:23:02 PM PDT 24 293868432 ps
T335 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.892015521 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:02 PM PDT 24 1440269886 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3565656777 Aug 18 04:22:31 PM PDT 24 Aug 18 04:22:32 PM PDT 24 519312109 ps
T61 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.794458198 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:24 PM PDT 24 383726163 ps
T337 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3792609319 Aug 18 04:18:00 PM PDT 24 Aug 18 04:18:02 PM PDT 24 406887459 ps
T338 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2778373369 Aug 18 04:23:00 PM PDT 24 Aug 18 04:23:01 PM PDT 24 418184228 ps
T199 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3513719864 Aug 18 04:22:58 PM PDT 24 Aug 18 04:23:08 PM PDT 24 8133238549 ps
T339 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4108283952 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 300231641 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2051956724 Aug 18 04:23:00 PM PDT 24 Aug 18 04:23:01 PM PDT 24 425707853 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.143165206 Aug 18 04:21:52 PM PDT 24 Aug 18 04:21:54 PM PDT 24 530888543 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3852882505 Aug 18 04:22:17 PM PDT 24 Aug 18 04:22:18 PM PDT 24 478753091 ps
T342 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3230727039 Aug 18 04:23:06 PM PDT 24 Aug 18 04:23:07 PM PDT 24 533544479 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3015148839 Aug 18 04:19:39 PM PDT 24 Aug 18 04:19:40 PM PDT 24 495681927 ps
T343 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1545731972 Aug 18 04:22:47 PM PDT 24 Aug 18 04:22:51 PM PDT 24 9006317924 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1434728692 Aug 18 04:22:56 PM PDT 24 Aug 18 04:23:00 PM PDT 24 1440991136 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1075238745 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:53 PM PDT 24 478638142 ps
T64 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2560660295 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:25 PM PDT 24 8668127588 ps
T346 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.677193981 Aug 18 04:22:58 PM PDT 24 Aug 18 04:22:59 PM PDT 24 327398754 ps
T347 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.874766944 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:30 PM PDT 24 477559429 ps
T348 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3559134002 Aug 18 04:21:48 PM PDT 24 Aug 18 04:21:50 PM PDT 24 382124709 ps
T349 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3239244319 Aug 18 04:22:56 PM PDT 24 Aug 18 04:22:57 PM PDT 24 419783655 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.258104312 Aug 18 04:19:37 PM PDT 24 Aug 18 04:19:37 PM PDT 24 434574480 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2127011143 Aug 18 04:21:53 PM PDT 24 Aug 18 04:21:55 PM PDT 24 511786053 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3360991503 Aug 18 04:22:54 PM PDT 24 Aug 18 04:22:56 PM PDT 24 371562041 ps
T352 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.700901756 Aug 18 04:22:32 PM PDT 24 Aug 18 04:22:33 PM PDT 24 507600659 ps
T353 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3435815461 Aug 18 04:18:22 PM PDT 24 Aug 18 04:18:23 PM PDT 24 567567836 ps
T354 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3276076723 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 465859540 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2551370452 Aug 18 04:22:04 PM PDT 24 Aug 18 04:22:04 PM PDT 24 325710017 ps
T200 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1468685335 Aug 18 04:22:52 PM PDT 24 Aug 18 04:23:05 PM PDT 24 8722713349 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3652015083 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:30 PM PDT 24 470588192 ps
T357 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2782513171 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:02 PM PDT 24 453167216 ps
T358 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3886287764 Aug 18 04:18:58 PM PDT 24 Aug 18 04:19:01 PM PDT 24 1372839661 ps
T359 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1681455829 Aug 18 04:21:45 PM PDT 24 Aug 18 04:21:46 PM PDT 24 465766530 ps
T360 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2657727183 Aug 18 04:22:27 PM PDT 24 Aug 18 04:22:29 PM PDT 24 992685718 ps
T361 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.79342618 Aug 18 04:17:55 PM PDT 24 Aug 18 04:18:15 PM PDT 24 7138080483 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.860204332 Aug 18 04:22:04 PM PDT 24 Aug 18 04:22:06 PM PDT 24 425473022 ps
T363 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.893518755 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:19 PM PDT 24 308401302 ps
T364 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.131557387 Aug 18 04:23:01 PM PDT 24 Aug 18 04:23:02 PM PDT 24 400379528 ps
T365 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1969069255 Aug 18 04:22:22 PM PDT 24 Aug 18 04:22:24 PM PDT 24 505301666 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.344967940 Aug 18 04:18:46 PM PDT 24 Aug 18 04:18:47 PM PDT 24 310503679 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2796634158 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:03 PM PDT 24 509319365 ps
T196 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1678168141 Aug 18 04:21:44 PM PDT 24 Aug 18 04:21:47 PM PDT 24 4124145387 ps
T368 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3308953993 Aug 18 04:22:50 PM PDT 24 Aug 18 04:22:52 PM PDT 24 464714154 ps
T369 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3440254594 Aug 18 04:22:58 PM PDT 24 Aug 18 04:23:00 PM PDT 24 396495867 ps
T370 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3682449841 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:53 PM PDT 24 387596815 ps
T371 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3942306394 Aug 18 04:20:41 PM PDT 24 Aug 18 04:20:43 PM PDT 24 394652680 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1092612111 Aug 18 04:19:14 PM PDT 24 Aug 18 04:19:21 PM PDT 24 6164960897 ps
T372 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3910183995 Aug 18 04:23:06 PM PDT 24 Aug 18 04:23:07 PM PDT 24 425172504 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2760388671 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:02 PM PDT 24 1317463901 ps
T374 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1774296228 Aug 18 04:22:02 PM PDT 24 Aug 18 04:22:04 PM PDT 24 8556256599 ps
T375 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.198614020 Aug 18 04:20:43 PM PDT 24 Aug 18 04:20:45 PM PDT 24 1752192817 ps
T376 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1102983812 Aug 18 04:22:56 PM PDT 24 Aug 18 04:22:57 PM PDT 24 438498580 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.887289603 Aug 18 04:21:39 PM PDT 24 Aug 18 04:21:40 PM PDT 24 840109135 ps
T377 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3350650983 Aug 18 04:22:02 PM PDT 24 Aug 18 04:22:03 PM PDT 24 436685088 ps
T378 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3730205389 Aug 18 04:22:34 PM PDT 24 Aug 18 04:22:35 PM PDT 24 343984835 ps
T379 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.19400465 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:54 PM PDT 24 291330042 ps
T380 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4157655189 Aug 18 04:22:53 PM PDT 24 Aug 18 04:23:01 PM PDT 24 4326809922 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3599625939 Aug 18 04:18:06 PM PDT 24 Aug 18 04:18:07 PM PDT 24 289635467 ps
T68 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2330137510 Aug 18 04:22:31 PM PDT 24 Aug 18 04:22:32 PM PDT 24 489555735 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3177222541 Aug 18 04:21:44 PM PDT 24 Aug 18 04:21:51 PM PDT 24 4447187335 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4189210354 Aug 18 04:22:08 PM PDT 24 Aug 18 04:22:10 PM PDT 24 501184248 ps
T69 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2540820864 Aug 18 04:19:29 PM PDT 24 Aug 18 04:19:30 PM PDT 24 392820342 ps
T384 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3866238568 Aug 18 04:22:58 PM PDT 24 Aug 18 04:23:02 PM PDT 24 1423131150 ps
T385 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1234593528 Aug 18 04:22:58 PM PDT 24 Aug 18 04:22:59 PM PDT 24 609776707 ps
T70 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2483101468 Aug 18 04:22:58 PM PDT 24 Aug 18 04:23:00 PM PDT 24 367103950 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3785094723 Aug 18 04:22:02 PM PDT 24 Aug 18 04:22:03 PM PDT 24 443680483 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4160437529 Aug 18 04:17:13 PM PDT 24 Aug 18 04:17:14 PM PDT 24 482815408 ps
T388 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3542975205 Aug 18 04:22:22 PM PDT 24 Aug 18 04:22:24 PM PDT 24 2778714653 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.707916121 Aug 18 04:22:28 PM PDT 24 Aug 18 04:22:30 PM PDT 24 4299667568 ps
T390 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.179572459 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 318757592 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1148896489 Aug 18 04:22:01 PM PDT 24 Aug 18 04:22:03 PM PDT 24 2894060301 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.431107998 Aug 18 04:22:27 PM PDT 24 Aug 18 04:22:29 PM PDT 24 695927008 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3559077109 Aug 18 04:20:52 PM PDT 24 Aug 18 04:20:53 PM PDT 24 479949440 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3527146395 Aug 18 04:23:03 PM PDT 24 Aug 18 04:23:09 PM PDT 24 2459655420 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1200377645 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:30 PM PDT 24 7863598249 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.995532588 Aug 18 04:22:29 PM PDT 24 Aug 18 04:22:32 PM PDT 24 4457375629 ps
T397 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3887715337 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:20 PM PDT 24 526762553 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.252003544 Aug 18 04:19:09 PM PDT 24 Aug 18 04:19:10 PM PDT 24 270407090 ps
T399 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1986911455 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:56 PM PDT 24 587910187 ps
T400 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.122873038 Aug 18 04:18:22 PM PDT 24 Aug 18 04:18:23 PM PDT 24 503164526 ps
T401 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.470509794 Aug 18 04:22:55 PM PDT 24 Aug 18 04:22:57 PM PDT 24 425884092 ps
T402 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3015274135 Aug 18 04:22:33 PM PDT 24 Aug 18 04:22:39 PM PDT 24 8248105342 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2646093870 Aug 18 04:17:13 PM PDT 24 Aug 18 04:17:14 PM PDT 24 504982912 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3112632969 Aug 18 04:22:53 PM PDT 24 Aug 18 04:22:54 PM PDT 24 431673122 ps
T405 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2486377593 Aug 18 04:22:59 PM PDT 24 Aug 18 04:23:00 PM PDT 24 1350413912 ps
T406 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1670858881 Aug 18 04:22:52 PM PDT 24 Aug 18 04:22:53 PM PDT 24 352403404 ps
T407 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1450540194 Aug 18 04:21:53 PM PDT 24 Aug 18 04:21:54 PM PDT 24 546392388 ps
T197 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3812318889 Aug 18 04:22:18 PM PDT 24 Aug 18 04:22:25 PM PDT 24 8765360628 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1494139824 Aug 18 04:21:38 PM PDT 24 Aug 18 04:21:40 PM PDT 24 534687096 ps
T409 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3992466896 Aug 18 04:20:30 PM PDT 24 Aug 18 04:20:30 PM PDT 24 457713888 ps
T410 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3108625314 Aug 18 04:23:06 PM PDT 24 Aug 18 04:23:07 PM PDT 24 413557773 ps
T411 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.42883552 Aug 18 04:22:35 PM PDT 24 Aug 18 04:22:38 PM PDT 24 539362002 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1830461660 Aug 18 04:22:49 PM PDT 24 Aug 18 04:22:50 PM PDT 24 515789031 ps
T413 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2502568927 Aug 18 04:19:59 PM PDT 24 Aug 18 04:20:02 PM PDT 24 4325421032 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4166966261 Aug 18 04:22:44 PM PDT 24 Aug 18 04:22:46 PM PDT 24 433003931 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.91755397 Aug 18 04:22:23 PM PDT 24 Aug 18 04:22:24 PM PDT 24 392265769 ps
T416 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1490123288 Aug 18 04:22:56 PM PDT 24 Aug 18 04:22:57 PM PDT 24 362534157 ps
T417 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4273175006 Aug 18 04:17:19 PM PDT 24 Aug 18 04:17:20 PM PDT 24 482806781 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2573036694 Aug 18 04:22:51 PM PDT 24 Aug 18 04:22:53 PM PDT 24 367348807 ps
T419 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.774885047 Aug 18 04:21:43 PM PDT 24 Aug 18 04:21:46 PM PDT 24 4481397962 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.55967286 Aug 18 04:18:16 PM PDT 24 Aug 18 04:18:17 PM PDT 24 890661190 ps

Test location /workspace/coverage/default/49.aon_timer_smoke.3502053830
Short name T8
Test name
Test status
Simulation time 390037190 ps
CPU time 1.15 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:19 PM PDT 24
Peak memory 196912 kb
Host smart-819331a5-46f7-4af0-a756-34e270c1370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502053830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3502053830
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2009447292
Short name T17
Test name
Test status
Simulation time 17827647672 ps
CPU time 34.97 seconds
Started Aug 18 04:27:10 PM PDT 24
Finished Aug 18 04:27:45 PM PDT 24
Peak memory 206788 kb
Host smart-9a968da3-b91f-4421-9937-8e0d26d19bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009447292 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2009447292
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2577494651
Short name T6
Test name
Test status
Simulation time 82747712336 ps
CPU time 37.8 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:52 PM PDT 24
Peak memory 192108 kb
Host smart-fe2f512c-4ee6-46ca-afea-c1b11769d1cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577494651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2577494651
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1187706728
Short name T51
Test name
Test status
Simulation time 3682992724 ps
CPU time 23.55 seconds
Started Aug 18 04:26:41 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 206860 kb
Host smart-eb9429dc-fe43-4cef-9038-a54f0ea7fc9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187706728 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1187706728
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.292659024
Short name T39
Test name
Test status
Simulation time 4320086878 ps
CPU time 4.25 seconds
Started Aug 18 04:21:45 PM PDT 24
Finished Aug 18 04:21:50 PM PDT 24
Peak memory 196960 kb
Host smart-ad82ac7f-b9f5-463a-b45e-b71e79ef8a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292659024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.292659024
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4050540206
Short name T35
Test name
Test status
Simulation time 22814673858 ps
CPU time 35.3 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 192004 kb
Host smart-f365c3a1-9808-4fd1-a67d-c93add145786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050540206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4050540206
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1024934129
Short name T136
Test name
Test status
Simulation time 3967960998 ps
CPU time 20.15 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 206800 kb
Host smart-9db3b6f5-6ccd-4778-bbe9-0ac8b03a89ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024934129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1024934129
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3518925592
Short name T43
Test name
Test status
Simulation time 384328248 ps
CPU time 0.71 seconds
Started Aug 18 04:22:03 PM PDT 24
Finished Aug 18 04:22:04 PM PDT 24
Peak memory 191936 kb
Host smart-f7edef8a-2dd1-45cb-80be-03b719c20be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518925592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3518925592
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1745677897
Short name T84
Test name
Test status
Simulation time 11370789067 ps
CPU time 31.49 seconds
Started Aug 18 04:26:44 PM PDT 24
Finished Aug 18 04:27:15 PM PDT 24
Peak memory 199184 kb
Host smart-ca9072e9-6619-4a54-a84e-dc8a767c00e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745677897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1745677897
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2473702867
Short name T92
Test name
Test status
Simulation time 19298108289 ps
CPU time 40.77 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 198916 kb
Host smart-de05f807-85ca-4772-8841-96867e1c2cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473702867 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2473702867
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1631915277
Short name T21
Test name
Test status
Simulation time 4492685029 ps
CPU time 7.56 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:06 PM PDT 24
Peak memory 216040 kb
Host smart-3a1132cb-fbc0-49b9-8791-fb194d4dba43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631915277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1631915277
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1179029478
Short name T108
Test name
Test status
Simulation time 2855952587 ps
CPU time 22.66 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 206792 kb
Host smart-105f460e-963a-4e68-9c3c-c90b358dd4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179029478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1179029478
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4221975692
Short name T50
Test name
Test status
Simulation time 10469416648 ps
CPU time 35.85 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 198656 kb
Host smart-33ab1aa0-dfa0-435a-ab80-1c130bd6c67f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221975692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4221975692
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.534448102
Short name T97
Test name
Test status
Simulation time 71002127413 ps
CPU time 110.74 seconds
Started Aug 18 04:26:54 PM PDT 24
Finished Aug 18 04:28:45 PM PDT 24
Peak memory 193096 kb
Host smart-3f456e80-cf00-4563-82d9-8abe8ae61690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534448102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.534448102
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1284263334
Short name T127
Test name
Test status
Simulation time 37499053308 ps
CPU time 55.09 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 193020 kb
Host smart-3c4c0224-4a2e-46b0-98b4-b79194159796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284263334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1284263334
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2012500388
Short name T96
Test name
Test status
Simulation time 47583899227 ps
CPU time 19.67 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:58 PM PDT 24
Peak memory 191992 kb
Host smart-164b13ec-ab29-4bad-a375-fd1f4d20e9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012500388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2012500388
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1807150140
Short name T103
Test name
Test status
Simulation time 8715147877 ps
CPU time 19.04 seconds
Started Aug 18 04:26:57 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 198596 kb
Host smart-2a05e960-6348-47b2-94fc-ea8b22341baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807150140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1807150140
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1022611753
Short name T102
Test name
Test status
Simulation time 103477401253 ps
CPU time 141.59 seconds
Started Aug 18 04:26:54 PM PDT 24
Finished Aug 18 04:29:15 PM PDT 24
Peak memory 192592 kb
Host smart-531a9d0f-0013-4c71-afef-5123d7ed931a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022611753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1022611753
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.806888648
Short name T112
Test name
Test status
Simulation time 194073771128 ps
CPU time 300.63 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:32:16 PM PDT 24
Peak memory 198320 kb
Host smart-eac4591f-5d4a-4399-aee5-868da1f788bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806888648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.806888648
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1273254710
Short name T105
Test name
Test status
Simulation time 398236781159 ps
CPU time 53.5 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 198336 kb
Host smart-565486a5-3212-439c-b02d-762ac699fe75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273254710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1273254710
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1733514266
Short name T150
Test name
Test status
Simulation time 114725235848 ps
CPU time 186.16 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:29:49 PM PDT 24
Peak memory 193116 kb
Host smart-8bc3cf0a-ace5-45d5-bbcc-e3f9f7395772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733514266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1733514266
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.920261251
Short name T140
Test name
Test status
Simulation time 599654458351 ps
CPU time 848.88 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:41:26 PM PDT 24
Peak memory 193096 kb
Host smart-152f208d-733b-4831-a208-32c676e8dce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920261251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.920261251
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3676199738
Short name T142
Test name
Test status
Simulation time 114501829137 ps
CPU time 74.93 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:28:23 PM PDT 24
Peak memory 193036 kb
Host smart-ae424a1c-3077-4d68-bda8-4bebbb6af660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676199738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3676199738
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1543424397
Short name T114
Test name
Test status
Simulation time 18567498970 ps
CPU time 39.42 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 214996 kb
Host smart-f4944661-e2df-4843-a7b9-5ad66213876e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543424397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1543424397
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2412558035
Short name T132
Test name
Test status
Simulation time 12870931112 ps
CPU time 27.93 seconds
Started Aug 18 04:26:45 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 206928 kb
Host smart-334cfe6b-271b-4de1-ae41-2d98a04918e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412558035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2412558035
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3475253851
Short name T125
Test name
Test status
Simulation time 11115488237 ps
CPU time 30.37 seconds
Started Aug 18 04:26:51 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 198660 kb
Host smart-120cac87-b2a8-4174-8077-629705e605a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475253851 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3475253851
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.4244988833
Short name T101
Test name
Test status
Simulation time 71917201774 ps
CPU time 114.42 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:29:09 PM PDT 24
Peak memory 192996 kb
Host smart-79aed4ab-cb2b-4a5d-8fbf-56f4679a7fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244988833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.4244988833
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1229679595
Short name T126
Test name
Test status
Simulation time 101605806365 ps
CPU time 140.33 seconds
Started Aug 18 04:26:35 PM PDT 24
Finished Aug 18 04:28:56 PM PDT 24
Peak memory 198344 kb
Host smart-6ae0b8e8-2374-461a-9a9a-543f8bc08f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229679595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1229679595
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2359172553
Short name T94
Test name
Test status
Simulation time 79494452941 ps
CPU time 29.24 seconds
Started Aug 18 04:26:40 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 198316 kb
Host smart-980efeaa-4ece-4b10-a603-9c42f01c025b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359172553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2359172553
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3613598366
Short name T109
Test name
Test status
Simulation time 184801490850 ps
CPU time 27.54 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:27:32 PM PDT 24
Peak memory 192584 kb
Host smart-aa62265d-e16c-4c71-9137-b88eaf30a8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613598366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3613598366
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2820864504
Short name T115
Test name
Test status
Simulation time 195489387460 ps
CPU time 135.58 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:28:52 PM PDT 24
Peak memory 192064 kb
Host smart-87a32546-dde2-485d-be7a-02fd0319ef68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820864504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2820864504
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4023943350
Short name T120
Test name
Test status
Simulation time 115305326987 ps
CPU time 34.03 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 192020 kb
Host smart-ebd72574-dab5-4706-85cc-26ef7d8d285e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023943350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4023943350
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4071089558
Short name T100
Test name
Test status
Simulation time 250028543600 ps
CPU time 339.62 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:32:46 PM PDT 24
Peak memory 192644 kb
Host smart-49f75b4c-f7cf-4757-8d90-214ba0f143f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071089558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4071089558
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4016297126
Short name T81
Test name
Test status
Simulation time 2559462310 ps
CPU time 15.61 seconds
Started Aug 18 04:26:40 PM PDT 24
Finished Aug 18 04:26:55 PM PDT 24
Peak memory 199140 kb
Host smart-b722a66f-fd0d-49c9-9cdf-c3ff5edb5e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016297126 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4016297126
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.749240936
Short name T13
Test name
Test status
Simulation time 377731342759 ps
CPU time 124.31 seconds
Started Aug 18 04:27:02 PM PDT 24
Finished Aug 18 04:29:06 PM PDT 24
Peak memory 198328 kb
Host smart-fe7b052f-e01c-48ef-b173-e4d8e4b296f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749240936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.749240936
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4282400938
Short name T113
Test name
Test status
Simulation time 69660823041 ps
CPU time 37.92 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:27:55 PM PDT 24
Peak memory 198384 kb
Host smart-a0f11e68-b4b0-4660-a827-675dbbe60ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282400938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4282400938
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.487875124
Short name T149
Test name
Test status
Simulation time 11416152151 ps
CPU time 27.72 seconds
Started Aug 18 04:27:00 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 207140 kb
Host smart-a15c2e06-37e6-4564-a30f-f2a1ab70ca46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487875124 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.487875124
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.914080400
Short name T117
Test name
Test status
Simulation time 139645909584 ps
CPU time 199.48 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:30:31 PM PDT 24
Peak memory 192012 kb
Host smart-116ca45d-32bc-46bf-8c93-b1e26dde2ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914080400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.914080400
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3355623767
Short name T141
Test name
Test status
Simulation time 424313953528 ps
CPU time 155.94 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:29:34 PM PDT 24
Peak memory 191988 kb
Host smart-374c3539-a935-493c-a0f1-8e354924a30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355623767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3355623767
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2577839478
Short name T139
Test name
Test status
Simulation time 209152366480 ps
CPU time 34.75 seconds
Started Aug 18 04:26:51 PM PDT 24
Finished Aug 18 04:27:25 PM PDT 24
Peak memory 192628 kb
Host smart-595d5f4c-fe2b-40cc-9262-35fab66465f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577839478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2577839478
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1250609661
Short name T128
Test name
Test status
Simulation time 12838470521 ps
CPU time 26.34 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:35 PM PDT 24
Peak memory 207104 kb
Host smart-7f01154a-c347-49d6-aeb3-8d679b2e5b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250609661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1250609661
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1319692979
Short name T148
Test name
Test status
Simulation time 109214775298 ps
CPU time 147.52 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:29:42 PM PDT 24
Peak memory 198344 kb
Host smart-c7ac0601-c2bd-4a06-adf6-c973e90faca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319692979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1319692979
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.841629750
Short name T14
Test name
Test status
Simulation time 615208826165 ps
CPU time 225.1 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:30:25 PM PDT 24
Peak memory 198300 kb
Host smart-fdaa7856-ecd4-4277-9d4c-7a5e2f9acadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841629750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.841629750
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2097167640
Short name T87
Test name
Test status
Simulation time 151344621604 ps
CPU time 223.7 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:30:42 PM PDT 24
Peak memory 191992 kb
Host smart-87b7969e-f5c0-4175-b2e9-29e761779cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097167640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2097167640
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3855459224
Short name T160
Test name
Test status
Simulation time 351890893081 ps
CPU time 112.7 seconds
Started Aug 18 04:27:24 PM PDT 24
Finished Aug 18 04:29:16 PM PDT 24
Peak memory 198384 kb
Host smart-01aac133-28d3-41d7-97d4-40d45b9c1d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855459224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3855459224
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4131025256
Short name T47
Test name
Test status
Simulation time 4587006904 ps
CPU time 23.62 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 206840 kb
Host smart-f05c7ca4-376f-4514-a11a-ef4e46905fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131025256 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4131025256
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.116161290
Short name T122
Test name
Test status
Simulation time 295850613096 ps
CPU time 225.93 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:30:59 PM PDT 24
Peak memory 198348 kb
Host smart-8865798a-f40a-4b68-a2eb-e372cec833fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116161290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.116161290
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1287401329
Short name T138
Test name
Test status
Simulation time 356824734118 ps
CPU time 516.78 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:35:20 PM PDT 24
Peak memory 193096 kb
Host smart-076f984f-e674-40ce-8821-c495879d634e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287401329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1287401329
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1731508833
Short name T34
Test name
Test status
Simulation time 152661995916 ps
CPU time 118.61 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:29:10 PM PDT 24
Peak memory 192620 kb
Host smart-4fbfc397-37dd-46db-8994-5860a8197e38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731508833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1731508833
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2216296739
Short name T146
Test name
Test status
Simulation time 1939427892 ps
CPU time 10.12 seconds
Started Aug 18 04:26:54 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 198660 kb
Host smart-377087a5-785d-48aa-bd70-724db0b9f068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216296739 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2216296739
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4280130571
Short name T145
Test name
Test status
Simulation time 488027762796 ps
CPU time 639.61 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:37:56 PM PDT 24
Peak memory 192036 kb
Host smart-7839ddea-c606-41fa-b0ea-e1773e8919bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280130571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4280130571
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3488260150
Short name T52
Test name
Test status
Simulation time 1870691287 ps
CPU time 14.45 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 198580 kb
Host smart-5bbd85a0-f276-415e-9ea3-716a667c599f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488260150 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3488260150
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2600682977
Short name T161
Test name
Test status
Simulation time 253457681740 ps
CPU time 84.41 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:28:38 PM PDT 24
Peak memory 192500 kb
Host smart-dcbeae06-74e0-4892-8a0f-e2dee6c28a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600682977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2600682977
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3393367013
Short name T123
Test name
Test status
Simulation time 3388154055 ps
CPU time 24.6 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:27:22 PM PDT 24
Peak memory 215020 kb
Host smart-d57da1a9-7109-4b97-9990-0c0c34dcb8d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393367013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3393367013
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.143165206
Short name T62
Test name
Test status
Simulation time 530888543 ps
CPU time 1.51 seconds
Started Aug 18 04:21:52 PM PDT 24
Finished Aug 18 04:21:54 PM PDT 24
Peak memory 193104 kb
Host smart-746c8f35-5a88-4f01-8057-c6718f854a79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143165206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.143165206
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.650058799
Short name T71
Test name
Test status
Simulation time 1866213476 ps
CPU time 2.85 seconds
Started Aug 18 04:22:02 PM PDT 24
Finished Aug 18 04:22:05 PM PDT 24
Peak memory 193836 kb
Host smart-3687b04b-370b-4ceb-9b98-4c243f6049ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650058799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.650058799
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.712462617
Short name T80
Test name
Test status
Simulation time 4306983893 ps
CPU time 9.25 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:47 PM PDT 24
Peak memory 214328 kb
Host smart-57a509b5-225c-4df7-9f26-6ff53c65e671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712462617 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.712462617
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4112231622
Short name T137
Test name
Test status
Simulation time 2525829217 ps
CPU time 16.54 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:19 PM PDT 24
Peak memory 199120 kb
Host smart-970c7740-d74b-4f90-a147-697d14dee1be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112231622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4112231622
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3389577904
Short name T85
Test name
Test status
Simulation time 18524462967 ps
CPU time 34.6 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:27:40 PM PDT 24
Peak memory 198888 kb
Host smart-adce6401-e02c-4080-a3ff-9d56ebcfa7d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389577904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3389577904
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2242071800
Short name T143
Test name
Test status
Simulation time 273205206017 ps
CPU time 338.22 seconds
Started Aug 18 04:27:00 PM PDT 24
Finished Aug 18 04:32:39 PM PDT 24
Peak memory 192008 kb
Host smart-610c28eb-f8c7-45b4-861b-b666b722379e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242071800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2242071800
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3059103900
Short name T144
Test name
Test status
Simulation time 11390101879 ps
CPU time 26.35 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:52 PM PDT 24
Peak memory 214996 kb
Host smart-b56a4113-64bd-4b74-9302-9ff632100cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059103900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3059103900
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3852816774
Short name T29
Test name
Test status
Simulation time 284255103666 ps
CPU time 200.21 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:30:26 PM PDT 24
Peak memory 193128 kb
Host smart-df8c224e-74b1-447e-be5d-5d9752ca8cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852816774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3852816774
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3087101628
Short name T119
Test name
Test status
Simulation time 102802949653 ps
CPU time 168.53 seconds
Started Aug 18 04:26:41 PM PDT 24
Finished Aug 18 04:29:30 PM PDT 24
Peak memory 198360 kb
Host smart-d5462049-0615-4c5e-94f8-c5f1c968804a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087101628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3087101628
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3230090520
Short name T134
Test name
Test status
Simulation time 109178703668 ps
CPU time 154.14 seconds
Started Aug 18 04:26:49 PM PDT 24
Finished Aug 18 04:29:23 PM PDT 24
Peak memory 191992 kb
Host smart-5e6f103a-b541-441f-9560-e859d3fbf90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230090520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3230090520
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2718365095
Short name T164
Test name
Test status
Simulation time 3686057628 ps
CPU time 34.64 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 199136 kb
Host smart-ad141a2a-ac86-4edd-8d23-07c9a07d7b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718365095 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2718365095
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3535848453
Short name T107
Test name
Test status
Simulation time 4894659538 ps
CPU time 26.64 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 206780 kb
Host smart-ed10f06e-e3e8-4c82-b872-c54d50d56b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535848453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3535848453
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.701756898
Short name T124
Test name
Test status
Simulation time 523979503 ps
CPU time 0.66 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 196756 kb
Host smart-682d2bb7-05b7-4047-b809-5648116110a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701756898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.701756898
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.433559547
Short name T129
Test name
Test status
Simulation time 544880195 ps
CPU time 1.21 seconds
Started Aug 18 04:27:25 PM PDT 24
Finished Aug 18 04:27:26 PM PDT 24
Peak memory 196868 kb
Host smart-ed91f756-5d79-48f7-ae85-69a497979392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433559547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.433559547
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2561994685
Short name T154
Test name
Test status
Simulation time 352852757 ps
CPU time 0.83 seconds
Started Aug 18 04:26:50 PM PDT 24
Finished Aug 18 04:26:51 PM PDT 24
Peak memory 196716 kb
Host smart-6f0ea623-46cd-4c43-89db-132007a10521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561994685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2561994685
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2320818722
Short name T133
Test name
Test status
Simulation time 13089890371 ps
CPU time 26.98 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 198616 kb
Host smart-c7bf215c-58ac-40dd-92aa-66ac1af97e82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320818722 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2320818722
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2425871869
Short name T4
Test name
Test status
Simulation time 558286341 ps
CPU time 0.79 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:40 PM PDT 24
Peak memory 197088 kb
Host smart-d6963de3-5bdc-46ea-854d-346838f21e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425871869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2425871869
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3589266237
Short name T98
Test name
Test status
Simulation time 535107885 ps
CPU time 0.77 seconds
Started Aug 18 04:26:28 PM PDT 24
Finished Aug 18 04:26:29 PM PDT 24
Peak memory 196724 kb
Host smart-bf1c163c-d6cb-4ea8-af27-00d372560f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589266237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3589266237
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1001462493
Short name T116
Test name
Test status
Simulation time 526656581 ps
CPU time 1.42 seconds
Started Aug 18 04:27:18 PM PDT 24
Finished Aug 18 04:27:20 PM PDT 24
Peak memory 196672 kb
Host smart-a48899ee-3590-4d8f-aca7-b3726fa77b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001462493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1001462493
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2332113669
Short name T147
Test name
Test status
Simulation time 540198551 ps
CPU time 0.63 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:27:06 PM PDT 24
Peak memory 196700 kb
Host smart-f0707896-0dff-4ef0-9737-e0b176e6fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332113669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2332113669
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3809878629
Short name T86
Test name
Test status
Simulation time 99580785947 ps
CPU time 38.74 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:28:01 PM PDT 24
Peak memory 198276 kb
Host smart-92ee8531-3a9f-48d2-b60c-e88515a2aa91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809878629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3809878629
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1605965338
Short name T157
Test name
Test status
Simulation time 472109290 ps
CPU time 1.29 seconds
Started Aug 18 04:26:42 PM PDT 24
Finished Aug 18 04:26:43 PM PDT 24
Peak memory 196812 kb
Host smart-d1524f26-2fca-4738-869d-ba6dccb618f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605965338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1605965338
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.566643663
Short name T88
Test name
Test status
Simulation time 549482225 ps
CPU time 1.28 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:26:59 PM PDT 24
Peak memory 196856 kb
Host smart-514bf849-3d73-403d-aab0-a3c599459af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566643663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.566643663
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1204125961
Short name T158
Test name
Test status
Simulation time 507301217 ps
CPU time 0.75 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 196728 kb
Host smart-a446b07c-4cf9-4db7-89f6-aea453ec0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204125961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1204125961
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2303413800
Short name T130
Test name
Test status
Simulation time 4670832230 ps
CPU time 19.94 seconds
Started Aug 18 04:26:54 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 198572 kb
Host smart-44eb0f47-7646-4c69-9309-8165730c4f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303413800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2303413800
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.592806744
Short name T99
Test name
Test status
Simulation time 352838116 ps
CPU time 0.8 seconds
Started Aug 18 04:26:28 PM PDT 24
Finished Aug 18 04:26:29 PM PDT 24
Peak memory 196756 kb
Host smart-cf828eca-3315-4ee9-a299-9655c651568b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592806744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.592806744
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.694109319
Short name T151
Test name
Test status
Simulation time 3928138821 ps
CPU time 2.28 seconds
Started Aug 18 04:26:49 PM PDT 24
Finished Aug 18 04:26:51 PM PDT 24
Peak memory 191972 kb
Host smart-c5a28082-645f-40f2-84e1-a7b3634efad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694109319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.694109319
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3503001973
Short name T32
Test name
Test status
Simulation time 390810975 ps
CPU time 0.79 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:38 PM PDT 24
Peak memory 196648 kb
Host smart-ec16089e-2435-4169-a059-d21b3be68086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503001973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3503001973
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1634858063
Short name T152
Test name
Test status
Simulation time 512087721 ps
CPU time 0.81 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 196720 kb
Host smart-ed4a1497-8cbd-4ed5-bf2e-ac126276abec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634858063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1634858063
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2858214788
Short name T93
Test name
Test status
Simulation time 520054801 ps
CPU time 1.21 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 196788 kb
Host smart-ee5e0f20-84f1-40bb-a6c3-f2d18c3ba46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858214788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2858214788
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3022930251
Short name T170
Test name
Test status
Simulation time 210087237413 ps
CPU time 308.55 seconds
Started Aug 18 04:27:20 PM PDT 24
Finished Aug 18 04:32:29 PM PDT 24
Peak memory 191248 kb
Host smart-fa3a585b-6ffc-42fe-a3f5-943b17205430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022930251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3022930251
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.4147027910
Short name T15
Test name
Test status
Simulation time 46245507693 ps
CPU time 17.2 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 193096 kb
Host smart-49e17cb7-6b71-46f1-b44b-160a5c16bc07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147027910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.4147027910
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2190325922
Short name T111
Test name
Test status
Simulation time 3927378449 ps
CPU time 33.18 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 206640 kb
Host smart-14f0a509-623b-4fe5-8464-ec75d5919eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190325922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2190325922
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.989286553
Short name T48
Test name
Test status
Simulation time 7727783090 ps
CPU time 35.12 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:27:31 PM PDT 24
Peak memory 215012 kb
Host smart-2bc7c6a7-8d7b-4911-8b4f-8ad3fdd3c200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989286553 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.989286553
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4124517382
Short name T156
Test name
Test status
Simulation time 172434349464 ps
CPU time 236.74 seconds
Started Aug 18 04:26:57 PM PDT 24
Finished Aug 18 04:30:54 PM PDT 24
Peak memory 198320 kb
Host smart-7f7a2265-6b64-46d8-9bbc-3765a2a57cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124517382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4124517382
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.39327510
Short name T135
Test name
Test status
Simulation time 600993152 ps
CPU time 0.84 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 196756 kb
Host smart-f1462179-36de-4387-941e-eca1b743e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39327510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.39327510
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3048653075
Short name T185
Test name
Test status
Simulation time 92359973568 ps
CPU time 61.28 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:28:05 PM PDT 24
Peak memory 191992 kb
Host smart-636a02a4-1794-4411-8379-5a23216206dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048653075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3048653075
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3297902260
Short name T118
Test name
Test status
Simulation time 374875581 ps
CPU time 0.7 seconds
Started Aug 18 04:27:10 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 196752 kb
Host smart-891ada50-b1bf-4d0f-a9a6-825576765aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297902260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3297902260
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3911847424
Short name T131
Test name
Test status
Simulation time 381654099 ps
CPU time 1.16 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:20 PM PDT 24
Peak memory 196712 kb
Host smart-1d1013f1-a62e-488f-b03c-199c6fdef378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911847424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3911847424
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.710924604
Short name T26
Test name
Test status
Simulation time 73975120413 ps
CPU time 96.59 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:28:16 PM PDT 24
Peak memory 191984 kb
Host smart-643791c9-1ba5-452f-833d-79b66b842aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710924604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.710924604
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.529518017
Short name T16
Test name
Test status
Simulation time 590582654 ps
CPU time 1.34 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:39 PM PDT 24
Peak memory 196736 kb
Host smart-ea135a9f-ca99-4e90-9e21-f9a9b0537eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529518017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.529518017
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3196909202
Short name T155
Test name
Test status
Simulation time 480534378 ps
CPU time 1.27 seconds
Started Aug 18 04:26:52 PM PDT 24
Finished Aug 18 04:26:53 PM PDT 24
Peak memory 196716 kb
Host smart-0e0e3a3e-70f5-48d2-9b48-15b13005a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196909202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3196909202
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4150186987
Short name T95
Test name
Test status
Simulation time 631640861 ps
CPU time 0.69 seconds
Started Aug 18 04:26:41 PM PDT 24
Finished Aug 18 04:26:42 PM PDT 24
Peak memory 196724 kb
Host smart-5d52e993-b11b-4a41-a213-72a63de7275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150186987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4150186987
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3391005491
Short name T168
Test name
Test status
Simulation time 2517763333 ps
CPU time 20.28 seconds
Started Aug 18 04:26:45 PM PDT 24
Finished Aug 18 04:27:05 PM PDT 24
Peak memory 206872 kb
Host smart-20e202d8-ac2c-431d-b92c-91fca3a753ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391005491 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3391005491
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3489028980
Short name T153
Test name
Test status
Simulation time 527805105 ps
CPU time 1.21 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 196776 kb
Host smart-0ef1197f-139b-49ba-855f-5dfcf2648abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489028980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3489028980
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3590413399
Short name T176
Test name
Test status
Simulation time 164074222382 ps
CPU time 239.58 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:31:11 PM PDT 24
Peak memory 198324 kb
Host smart-b6ae8c42-d544-4731-bd7f-4345f8400a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590413399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3590413399
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.728272589
Short name T183
Test name
Test status
Simulation time 34025592531 ps
CPU time 30.26 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:50 PM PDT 24
Peak memory 206760 kb
Host smart-c197ffe9-35ee-49c9-a0d1-8101860c7326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728272589 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.728272589
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1493656230
Short name T91
Test name
Test status
Simulation time 407285790 ps
CPU time 1.11 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 196828 kb
Host smart-d9f5161b-7e71-4049-962b-9feec903fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493656230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1493656230
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.393491029
Short name T110
Test name
Test status
Simulation time 617792296 ps
CPU time 1.45 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:15 PM PDT 24
Peak memory 196796 kb
Host smart-caab9952-c308-437c-a8c1-a185e04fd99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393491029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.393491029
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1212272528
Short name T180
Test name
Test status
Simulation time 17064599131 ps
CPU time 46.15 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:27:44 PM PDT 24
Peak memory 214400 kb
Host smart-d2d80a3d-29dd-43e5-ac2a-b21ee89e6094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212272528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1212272528
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.12380908
Short name T175
Test name
Test status
Simulation time 557551505 ps
CPU time 0.96 seconds
Started Aug 18 04:26:41 PM PDT 24
Finished Aug 18 04:26:42 PM PDT 24
Peak memory 196752 kb
Host smart-b7a1a309-fbc6-4dbf-a36d-31c9099ba942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12380908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.12380908
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3979028964
Short name T104
Test name
Test status
Simulation time 2331816417 ps
CPU time 20.24 seconds
Started Aug 18 04:26:42 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 206840 kb
Host smart-9d845cc3-1fa2-4ffd-b755-830757354d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979028964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3979028964
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4167363932
Short name T162
Test name
Test status
Simulation time 513431044 ps
CPU time 0.79 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:08 PM PDT 24
Peak memory 196724 kb
Host smart-f9cb6087-4188-4ede-a03e-f861455568b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167363932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4167363932
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3842469019
Short name T189
Test name
Test status
Simulation time 416475511 ps
CPU time 0.88 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 196700 kb
Host smart-ae50511e-af42-438b-87bf-719e9b6a17c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842469019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3842469019
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3105578673
Short name T177
Test name
Test status
Simulation time 480001569 ps
CPU time 0.95 seconds
Started Aug 18 04:27:01 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 196716 kb
Host smart-f3d8cbdf-066f-4af8-9c2f-11277ebb3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105578673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3105578673
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1343112023
Short name T190
Test name
Test status
Simulation time 398044719 ps
CPU time 1.26 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:05 PM PDT 24
Peak memory 196840 kb
Host smart-82a3f79d-ab65-46bd-a27e-fff278e30e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343112023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1343112023
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2785647066
Short name T167
Test name
Test status
Simulation time 390593790060 ps
CPU time 291.57 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:31:54 PM PDT 24
Peak memory 191964 kb
Host smart-4551c210-c2ef-404f-8910-fd981b7c8df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785647066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2785647066
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2810814337
Short name T188
Test name
Test status
Simulation time 506805787 ps
CPU time 1.29 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 196696 kb
Host smart-b9a381e4-a8c1-4331-8a4d-27088d9bfa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810814337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2810814337
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3175265687
Short name T24
Test name
Test status
Simulation time 481612986 ps
CPU time 0.68 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:27:12 PM PDT 24
Peak memory 196720 kb
Host smart-f998ab09-577b-4ef7-bdfa-51cf06dfd960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175265687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3175265687
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3191012179
Short name T169
Test name
Test status
Simulation time 564874964 ps
CPU time 0.93 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:26:57 PM PDT 24
Peak memory 196808 kb
Host smart-6914d5fa-2294-4367-98a5-331d30f8a559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191012179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3191012179
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2206285951
Short name T171
Test name
Test status
Simulation time 4786021302 ps
CPU time 21.19 seconds
Started Aug 18 04:26:55 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 206844 kb
Host smart-5d2971b0-d6dc-4264-b758-4acc91af6b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206285951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2206285951
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3812318889
Short name T197
Test name
Test status
Simulation time 8765360628 ps
CPU time 6.71 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 198048 kb
Host smart-327a5e10-11af-4052-9f56-ac2b10b1db6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812318889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3812318889
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3191419986
Short name T163
Test name
Test status
Simulation time 504252797 ps
CPU time 0.67 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 196836 kb
Host smart-5a0c850e-ca9a-49f0-8845-00679c7173a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191419986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3191419986
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3556740165
Short name T10
Test name
Test status
Simulation time 461271347 ps
CPU time 0.98 seconds
Started Aug 18 04:27:10 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 196776 kb
Host smart-c09f0f4d-7020-439b-8026-1a7a144de4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556740165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3556740165
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1839127277
Short name T187
Test name
Test status
Simulation time 481644116 ps
CPU time 0.65 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 196736 kb
Host smart-d905204c-84ef-48f9-a196-2b19fae05cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839127277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1839127277
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4059045843
Short name T121
Test name
Test status
Simulation time 475466128 ps
CPU time 1.33 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:27:00 PM PDT 24
Peak memory 196660 kb
Host smart-36bba5de-73dd-4135-aa26-37bbf2e72847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059045843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4059045843
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2840389413
Short name T165
Test name
Test status
Simulation time 393825609 ps
CPU time 0.69 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:07 PM PDT 24
Peak memory 196644 kb
Host smart-e9ac3872-94e7-4eea-91e2-1d6bb540ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840389413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2840389413
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1321007395
Short name T173
Test name
Test status
Simulation time 153916187677 ps
CPU time 61.1 seconds
Started Aug 18 04:27:00 PM PDT 24
Finished Aug 18 04:28:01 PM PDT 24
Peak memory 184260 kb
Host smart-5782147d-df40-481b-b834-da949cf6129c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321007395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1321007395
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2797260574
Short name T166
Test name
Test status
Simulation time 552441164 ps
CPU time 0.63 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 196736 kb
Host smart-3eb233d7-e472-40ce-ae1a-c36e4b9e26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797260574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2797260574
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2512943437
Short name T184
Test name
Test status
Simulation time 547893232 ps
CPU time 0.75 seconds
Started Aug 18 04:26:35 PM PDT 24
Finished Aug 18 04:26:36 PM PDT 24
Peak memory 196716 kb
Host smart-c1b2225a-0848-4a1a-ad4f-f947f058ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512943437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2512943437
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1361170073
Short name T11
Test name
Test status
Simulation time 624190412 ps
CPU time 0.74 seconds
Started Aug 18 04:26:57 PM PDT 24
Finished Aug 18 04:26:58 PM PDT 24
Peak memory 196672 kb
Host smart-d732df1e-2874-4208-a385-6ee472c8f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361170073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1361170073
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1373398971
Short name T191
Test name
Test status
Simulation time 4419565753 ps
CPU time 27.95 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 206812 kb
Host smart-443299be-85f6-4ffd-be53-08166731c2e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373398971 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1373398971
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4022855949
Short name T172
Test name
Test status
Simulation time 429810050 ps
CPU time 1.15 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 196792 kb
Host smart-19916cbd-46d0-4845-9f6e-883b3c5ff166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022855949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4022855949
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2445953167
Short name T106
Test name
Test status
Simulation time 355637371 ps
CPU time 0.82 seconds
Started Aug 18 04:26:27 PM PDT 24
Finished Aug 18 04:26:28 PM PDT 24
Peak memory 196740 kb
Host smart-c2386daf-3e07-4a4d-ac67-0e22ac26456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445953167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2445953167
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2671774782
Short name T178
Test name
Test status
Simulation time 347960449 ps
CPU time 0.88 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:26:43 PM PDT 24
Peak memory 196692 kb
Host smart-ec377684-4a1f-4e3f-94b6-c58c2495fb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671774782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2671774782
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.7894208
Short name T159
Test name
Test status
Simulation time 9523445371 ps
CPU time 47.37 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 214988 kb
Host smart-0af96839-cca0-46f7-a959-59fffa1080e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7894208 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.7894208
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.967192758
Short name T179
Test name
Test status
Simulation time 632175502 ps
CPU time 1.41 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:08 PM PDT 24
Peak memory 196740 kb
Host smart-a4c1de2d-ef26-4b67-9bfb-8c5ba29644a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967192758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.967192758
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2587214706
Short name T186
Test name
Test status
Simulation time 450265163 ps
CPU time 1.22 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:07 PM PDT 24
Peak memory 196704 kb
Host smart-0944d873-b037-4cd5-9828-224a5fed85cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587214706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2587214706
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.508452869
Short name T182
Test name
Test status
Simulation time 548064237 ps
CPU time 0.89 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:27:05 PM PDT 24
Peak memory 196832 kb
Host smart-ede06af6-3bc6-413c-ada3-6a125a12e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508452869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.508452869
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1182160647
Short name T192
Test name
Test status
Simulation time 533521212 ps
CPU time 0.63 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:39 PM PDT 24
Peak memory 196712 kb
Host smart-e6901aee-8ad8-42c0-a898-f62e53dc60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182160647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1182160647
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2599713727
Short name T57
Test name
Test status
Simulation time 1007296500 ps
CPU time 1.63 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:20 PM PDT 24
Peak memory 183840 kb
Host smart-4abfd215-b088-4cf8-a74b-b8d25eeeeb84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599713727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2599713727
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.55967286
Short name T420
Test name
Test status
Simulation time 890661190 ps
CPU time 0.71 seconds
Started Aug 18 04:18:16 PM PDT 24
Finished Aug 18 04:18:17 PM PDT 24
Peak memory 183592 kb
Host smart-344bca49-a50b-42f3-b145-dff4f9ea4393
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55967286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_
reset.55967286
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3066874354
Short name T37
Test name
Test status
Simulation time 389523885 ps
CPU time 1.2 seconds
Started Aug 18 04:22:08 PM PDT 24
Finished Aug 18 04:22:09 PM PDT 24
Peak memory 195816 kb
Host smart-cc9d37e5-5efb-43eb-8b7d-f53054f41591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066874354 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3066874354
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.860204332
Short name T362
Test name
Test status
Simulation time 425473022 ps
CPU time 0.98 seconds
Started Aug 18 04:22:04 PM PDT 24
Finished Aug 18 04:22:06 PM PDT 24
Peak memory 183584 kb
Host smart-1f1dfb3c-7b30-4481-b02e-40abc03005b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860204332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.860204332
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.893518755
Short name T363
Test name
Test status
Simulation time 308401302 ps
CPU time 1.02 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:19 PM PDT 24
Peak memory 182788 kb
Host smart-d474c93a-952e-4405-939c-3298b158d757
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893518755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.893518755
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2551370452
Short name T355
Test name
Test status
Simulation time 325710017 ps
CPU time 0.67 seconds
Started Aug 18 04:22:04 PM PDT 24
Finished Aug 18 04:22:04 PM PDT 24
Peak memory 183488 kb
Host smart-a073eb8d-1157-4886-93a4-d84ff309c713
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551370452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2551370452
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.177584617
Short name T320
Test name
Test status
Simulation time 623150924 ps
CPU time 2.59 seconds
Started Aug 18 04:19:50 PM PDT 24
Finished Aug 18 04:19:52 PM PDT 24
Peak memory 198392 kb
Host smart-80366906-4521-4466-9314-ac462a88e9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177584617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.177584617
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3177222541
Short name T382
Test name
Test status
Simulation time 4447187335 ps
CPU time 6.67 seconds
Started Aug 18 04:21:44 PM PDT 24
Finished Aug 18 04:21:51 PM PDT 24
Peak memory 197504 kb
Host smart-d8407a51-8267-4f75-8f41-62e20af513cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177222541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3177222541
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3888406391
Short name T60
Test name
Test status
Simulation time 461264126 ps
CPU time 1.38 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:31 PM PDT 24
Peak memory 194048 kb
Host smart-fc9bfd31-23d1-43ea-8163-839c68f13b08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888406391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3888406391
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2560660295
Short name T64
Test name
Test status
Simulation time 8668127588 ps
CPU time 6.41 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 192100 kb
Host smart-19334f56-86ef-4f62-93c8-583bca020279
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560660295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2560660295
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.887289603
Short name T67
Test name
Test status
Simulation time 840109135 ps
CPU time 0.85 seconds
Started Aug 18 04:21:39 PM PDT 24
Finished Aug 18 04:21:40 PM PDT 24
Peak memory 192480 kb
Host smart-24b5502c-cdf7-42cd-a1aa-16ae7e3eb0de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887289603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.887289603
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3652015083
Short name T356
Test name
Test status
Simulation time 470588192 ps
CPU time 0.8 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:30 PM PDT 24
Peak memory 195620 kb
Host smart-17b3e7a7-2577-4c48-8af3-d08301084903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652015083 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3652015083
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1494139824
Short name T408
Test name
Test status
Simulation time 534687096 ps
CPU time 0.95 seconds
Started Aug 18 04:21:38 PM PDT 24
Finished Aug 18 04:21:40 PM PDT 24
Peak memory 190840 kb
Host smart-85596ff9-efb7-4d06-8e93-35a98209405b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494139824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1494139824
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1391085700
Short name T312
Test name
Test status
Simulation time 458301857 ps
CPU time 0.65 seconds
Started Aug 18 04:17:35 PM PDT 24
Finished Aug 18 04:17:36 PM PDT 24
Peak memory 183988 kb
Host smart-cd17a3d7-ef56-4408-a463-285ab86581b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391085700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1391085700
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2710616914
Short name T292
Test name
Test status
Simulation time 301815753 ps
CPU time 0.67 seconds
Started Aug 18 04:21:52 PM PDT 24
Finished Aug 18 04:21:53 PM PDT 24
Peak memory 183464 kb
Host smart-07d3438d-8e2c-4f1f-85ab-a285a1bb68b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710616914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2710616914
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3852882505
Short name T341
Test name
Test status
Simulation time 478753091 ps
CPU time 0.66 seconds
Started Aug 18 04:22:17 PM PDT 24
Finished Aug 18 04:22:18 PM PDT 24
Peak memory 183488 kb
Host smart-1bffe818-140e-485b-8ad1-3053d7efe69e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852882505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3852882505
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1838182148
Short name T325
Test name
Test status
Simulation time 1981206762 ps
CPU time 1.03 seconds
Started Aug 18 04:22:13 PM PDT 24
Finished Aug 18 04:22:14 PM PDT 24
Peak memory 192024 kb
Host smart-0331d0c8-7d52-4d48-bae3-16a1bcb956db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838182148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1838182148
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3627558603
Short name T286
Test name
Test status
Simulation time 516619118 ps
CPU time 1.28 seconds
Started Aug 18 04:18:42 PM PDT 24
Finished Aug 18 04:18:44 PM PDT 24
Peak memory 198360 kb
Host smart-68357fa5-b63e-4561-9f25-98ec8aa6406a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627558603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3627558603
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1200377645
Short name T395
Test name
Test status
Simulation time 7863598249 ps
CPU time 12.05 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:30 PM PDT 24
Peak memory 198308 kb
Host smart-bae5d6dd-928f-4323-81fc-e8c6f427cfbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200377645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1200377645
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2782513171
Short name T357
Test name
Test status
Simulation time 453167216 ps
CPU time 0.89 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:02 PM PDT 24
Peak memory 198208 kb
Host smart-140b3ba8-5f43-4d0f-9c42-a62b2f37bd40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782513171 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2782513171
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3026005628
Short name T311
Test name
Test status
Simulation time 498948050 ps
CPU time 1.24 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 191692 kb
Host smart-728264f1-538d-4410-b17f-99f92d075a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026005628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3026005628
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.729627017
Short name T329
Test name
Test status
Simulation time 416791871 ps
CPU time 1.22 seconds
Started Aug 18 04:21:44 PM PDT 24
Finished Aug 18 04:21:46 PM PDT 24
Peak memory 182848 kb
Host smart-b6b51067-9d8a-4949-8079-d449b1fa825e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729627017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.729627017
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.892015521
Short name T335
Test name
Test status
Simulation time 1440269886 ps
CPU time 1 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:02 PM PDT 24
Peak memory 183676 kb
Host smart-1262c581-a242-4669-846e-092f726c13f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892015521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.892015521
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3760570814
Short name T321
Test name
Test status
Simulation time 365006131 ps
CPU time 2.32 seconds
Started Aug 18 04:18:42 PM PDT 24
Finished Aug 18 04:18:44 PM PDT 24
Peak memory 198468 kb
Host smart-fa94cebb-7d1e-4ffd-9015-9360d92666b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760570814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3760570814
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3867620986
Short name T40
Test name
Test status
Simulation time 4486038255 ps
CPU time 2.56 seconds
Started Aug 18 04:19:09 PM PDT 24
Finished Aug 18 04:19:11 PM PDT 24
Peak memory 197080 kb
Host smart-6341946e-d48c-49bf-8817-a941009aac91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867620986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3867620986
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4005170298
Short name T38
Test name
Test status
Simulation time 608661059 ps
CPU time 0.94 seconds
Started Aug 18 04:19:36 PM PDT 24
Finished Aug 18 04:19:37 PM PDT 24
Peak memory 196424 kb
Host smart-a2fe4a90-8b2a-41d3-85ce-54671fdef5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005170298 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4005170298
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.326192507
Short name T42
Test name
Test status
Simulation time 490671862 ps
CPU time 0.93 seconds
Started Aug 18 04:22:27 PM PDT 24
Finished Aug 18 04:22:28 PM PDT 24
Peak memory 192864 kb
Host smart-1e3b3dff-049a-461f-92a7-39ce5a5b082b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326192507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.326192507
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2187634213
Short name T299
Test name
Test status
Simulation time 514729537 ps
CPU time 0.71 seconds
Started Aug 18 04:22:31 PM PDT 24
Finished Aug 18 04:22:32 PM PDT 24
Peak memory 183292 kb
Host smart-b9b8bdfc-e855-4e00-a950-c61be56e2fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187634213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2187634213
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1148896489
Short name T391
Test name
Test status
Simulation time 2894060301 ps
CPU time 1.53 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 191936 kb
Host smart-f4ae4bb0-7e8e-4474-98b4-d1be1e813a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148896489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1148896489
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4152975945
Short name T291
Test name
Test status
Simulation time 709109551 ps
CPU time 1.45 seconds
Started Aug 18 04:21:45 PM PDT 24
Finished Aug 18 04:21:47 PM PDT 24
Peak memory 197704 kb
Host smart-d37e43ee-1011-4abe-8c7c-a7d49b321761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152975945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4152975945
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1774296228
Short name T374
Test name
Test status
Simulation time 8556256599 ps
CPU time 2.23 seconds
Started Aug 18 04:22:02 PM PDT 24
Finished Aug 18 04:22:04 PM PDT 24
Peak memory 198324 kb
Host smart-45013a1e-c741-426a-ad65-c4990cc6951b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774296228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1774296228
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1681455829
Short name T359
Test name
Test status
Simulation time 465766530 ps
CPU time 1.15 seconds
Started Aug 18 04:21:45 PM PDT 24
Finished Aug 18 04:21:46 PM PDT 24
Peak memory 198112 kb
Host smart-e412de1b-02f4-465b-8524-f6e463f9b71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681455829 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1681455829
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3249888077
Short name T319
Test name
Test status
Simulation time 341128560 ps
CPU time 1.12 seconds
Started Aug 18 04:19:13 PM PDT 24
Finished Aug 18 04:19:14 PM PDT 24
Peak memory 192860 kb
Host smart-6f2d86cf-a0b1-454c-afeb-282dadb4fce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249888077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3249888077
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3992466896
Short name T409
Test name
Test status
Simulation time 457713888 ps
CPU time 0.7 seconds
Started Aug 18 04:20:30 PM PDT 24
Finished Aug 18 04:20:30 PM PDT 24
Peak memory 183552 kb
Host smart-fdcd4a8d-5e2d-4234-983b-4c18e3839385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992466896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3992466896
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2047999967
Short name T72
Test name
Test status
Simulation time 1824564599 ps
CPU time 4.76 seconds
Started Aug 18 04:19:36 PM PDT 24
Finished Aug 18 04:19:40 PM PDT 24
Peak memory 193948 kb
Host smart-d5f3a9fc-7791-4c33-b918-3421a4132ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047999967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2047999967
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4169758485
Short name T302
Test name
Test status
Simulation time 453645835 ps
CPU time 2.16 seconds
Started Aug 18 04:21:38 PM PDT 24
Finished Aug 18 04:21:41 PM PDT 24
Peak memory 198060 kb
Host smart-17583ad8-4de2-4f87-9e44-7b9f5c99b4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169758485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4169758485
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.739676923
Short name T198
Test name
Test status
Simulation time 4289335088 ps
CPU time 7.62 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:22:36 PM PDT 24
Peak memory 196316 kb
Host smart-487d23c0-85fe-4ace-adc3-7da99f5422b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739676923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.739676923
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3435815461
Short name T353
Test name
Test status
Simulation time 567567836 ps
CPU time 1.1 seconds
Started Aug 18 04:18:22 PM PDT 24
Finished Aug 18 04:18:23 PM PDT 24
Peak memory 196500 kb
Host smart-7cc1387e-784e-4f2e-a8c4-35ed127ada4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435815461 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3435815461
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.122873038
Short name T400
Test name
Test status
Simulation time 503164526 ps
CPU time 0.68 seconds
Started Aug 18 04:18:22 PM PDT 24
Finished Aug 18 04:18:23 PM PDT 24
Peak memory 193036 kb
Host smart-1985ccd6-87cd-4a88-a73a-53ce6ce411ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122873038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.122873038
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2948767309
Short name T304
Test name
Test status
Simulation time 431039064 ps
CPU time 0.82 seconds
Started Aug 18 04:22:44 PM PDT 24
Finished Aug 18 04:22:45 PM PDT 24
Peak memory 183572 kb
Host smart-4a119c25-aae1-40c4-a9e1-55ecdab75366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948767309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2948767309
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1679321841
Short name T76
Test name
Test status
Simulation time 2504358318 ps
CPU time 4.47 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:28 PM PDT 24
Peak memory 195056 kb
Host smart-542defc3-6a8c-4690-85b9-cb129b990779
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679321841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1679321841
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3559134002
Short name T348
Test name
Test status
Simulation time 382124709 ps
CPU time 1.23 seconds
Started Aug 18 04:21:48 PM PDT 24
Finished Aug 18 04:21:50 PM PDT 24
Peak memory 198008 kb
Host smart-e35d7213-bb90-45f3-a16c-20571b24fb37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559134002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3559134002
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.707916121
Short name T389
Test name
Test status
Simulation time 4299667568 ps
CPU time 2.51 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:22:30 PM PDT 24
Peak memory 197788 kb
Host smart-4e43db79-2b8f-40cd-875b-c1a35a7abc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707916121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.707916121
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1969069255
Short name T365
Test name
Test status
Simulation time 505301666 ps
CPU time 1.35 seconds
Started Aug 18 04:22:22 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 196236 kb
Host smart-b33535f8-0963-48da-80dd-adc9acbe636f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969069255 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1969069255
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.794458198
Short name T61
Test name
Test status
Simulation time 383726163 ps
CPU time 0.66 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 193036 kb
Host smart-b6a0bd29-3d71-415f-8abe-201afae5c742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794458198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.794458198
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4273175006
Short name T417
Test name
Test status
Simulation time 482806781 ps
CPU time 0.64 seconds
Started Aug 18 04:17:19 PM PDT 24
Finished Aug 18 04:17:20 PM PDT 24
Peak memory 183984 kb
Host smart-6fae4330-258a-416f-a5f4-f2c9b99e4439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273175006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4273175006
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2263352376
Short name T75
Test name
Test status
Simulation time 1229581431 ps
CPU time 1.39 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:31 PM PDT 24
Peak memory 193896 kb
Host smart-9f41b690-4216-4931-aa44-9d69238d09d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263352376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2263352376
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3792609319
Short name T337
Test name
Test status
Simulation time 406887459 ps
CPU time 2.59 seconds
Started Aug 18 04:18:00 PM PDT 24
Finished Aug 18 04:18:02 PM PDT 24
Peak memory 198428 kb
Host smart-a8345096-dfea-4844-bc19-e2ae0528807f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792609319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3792609319
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.774885047
Short name T419
Test name
Test status
Simulation time 4481397962 ps
CPU time 2.19 seconds
Started Aug 18 04:21:43 PM PDT 24
Finished Aug 18 04:21:46 PM PDT 24
Peak memory 196820 kb
Host smart-ca2f2d9f-7195-48bb-967b-6e7e21b13dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774885047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.774885047
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1830461660
Short name T412
Test name
Test status
Simulation time 515789031 ps
CPU time 0.91 seconds
Started Aug 18 04:22:49 PM PDT 24
Finished Aug 18 04:22:50 PM PDT 24
Peak memory 196820 kb
Host smart-9b697280-ccc4-4084-94c1-ab734bbab94c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830461660 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1830461660
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2330137510
Short name T68
Test name
Test status
Simulation time 489555735 ps
CPU time 0.75 seconds
Started Aug 18 04:22:31 PM PDT 24
Finished Aug 18 04:22:32 PM PDT 24
Peak memory 193852 kb
Host smart-598e5015-52ba-4937-8568-def3a04ddbce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330137510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2330137510
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1170157738
Short name T294
Test name
Test status
Simulation time 296171533 ps
CPU time 0.65 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 183596 kb
Host smart-e45196f2-aa5d-4e9d-ab76-766694c05609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170157738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1170157738
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2143850982
Short name T73
Test name
Test status
Simulation time 2504196130 ps
CPU time 1.44 seconds
Started Aug 18 04:18:18 PM PDT 24
Finished Aug 18 04:18:19 PM PDT 24
Peak memory 194296 kb
Host smart-8e8f23a3-a1ac-4e0c-99fc-9322871fa0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143850982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2143850982
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3887715337
Short name T397
Test name
Test status
Simulation time 526762553 ps
CPU time 1.52 seconds
Started Aug 18 04:22:18 PM PDT 24
Finished Aug 18 04:22:20 PM PDT 24
Peak memory 198112 kb
Host smart-251e6b58-c9a7-4a2d-a117-501e2888e223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887715337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3887715337
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.709476546
Short name T313
Test name
Test status
Simulation time 426583330 ps
CPU time 1.26 seconds
Started Aug 18 04:22:59 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 195484 kb
Host smart-c522488f-611b-4b72-8a90-092b6e40a4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709476546 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.709476546
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3560130747
Short name T328
Test name
Test status
Simulation time 357735345 ps
CPU time 1.09 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:55 PM PDT 24
Peak memory 193036 kb
Host smart-4e348286-1a13-4e82-932e-5aeac4639a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560130747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3560130747
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2051956724
Short name T340
Test name
Test status
Simulation time 425707853 ps
CPU time 0.82 seconds
Started Aug 18 04:23:00 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 192764 kb
Host smart-25f770f9-fda1-4983-9aa2-23a9ac201165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051956724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2051956724
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3866238568
Short name T384
Test name
Test status
Simulation time 1423131150 ps
CPU time 3.85 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:23:02 PM PDT 24
Peak memory 193472 kb
Host smart-0c3d6c4a-c444-4c3e-85d1-28f6065fc29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866238568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3866238568
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3308953993
Short name T368
Test name
Test status
Simulation time 464714154 ps
CPU time 1.59 seconds
Started Aug 18 04:22:50 PM PDT 24
Finished Aug 18 04:22:52 PM PDT 24
Peak memory 198452 kb
Host smart-f84fe88e-f59b-4777-a43d-3e44f9e85c20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308953993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3308953993
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4157655189
Short name T380
Test name
Test status
Simulation time 4326809922 ps
CPU time 7.46 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 197904 kb
Host smart-6a0c345a-5698-407a-99a0-7b86e7d66794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157655189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4157655189
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3835302787
Short name T326
Test name
Test status
Simulation time 443686015 ps
CPU time 0.8 seconds
Started Aug 18 04:22:50 PM PDT 24
Finished Aug 18 04:22:51 PM PDT 24
Peak memory 195428 kb
Host smart-881be193-b7ee-4369-8fdb-74bed85e931d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835302787 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3835302787
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3276076723
Short name T354
Test name
Test status
Simulation time 465859540 ps
CPU time 0.67 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 193092 kb
Host smart-243847af-eabb-4781-87cf-77b34c2e44dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276076723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3276076723
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3970178164
Short name T295
Test name
Test status
Simulation time 325516069 ps
CPU time 0.98 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 192804 kb
Host smart-7540515b-9fa3-4bbe-9f5d-fbba07f03736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970178164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3970178164
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3527146395
Short name T394
Test name
Test status
Simulation time 2459655420 ps
CPU time 5.72 seconds
Started Aug 18 04:23:03 PM PDT 24
Finished Aug 18 04:23:09 PM PDT 24
Peak memory 194808 kb
Host smart-5820b14b-e09f-4d7a-af8a-316598cbf35a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527146395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3527146395
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1197235026
Short name T290
Test name
Test status
Simulation time 702029971 ps
CPU time 1.9 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:22:58 PM PDT 24
Peak memory 198420 kb
Host smart-49c5ed8d-b574-462e-aef7-3ee836bcddfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197235026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1197235026
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3513719864
Short name T199
Test name
Test status
Simulation time 8133238549 ps
CPU time 9.91 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:23:08 PM PDT 24
Peak memory 197916 kb
Host smart-878bf14c-33ef-4e59-aeb7-948514281dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513719864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3513719864
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1453943966
Short name T303
Test name
Test status
Simulation time 433326199 ps
CPU time 0.83 seconds
Started Aug 18 04:22:59 PM PDT 24
Finished Aug 18 04:23:00 PM PDT 24
Peak memory 196564 kb
Host smart-b01a730d-88dc-4cdc-95b4-e7839f0043ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453943966 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1453943966
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1986911455
Short name T399
Test name
Test status
Simulation time 587910187 ps
CPU time 0.7 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 193200 kb
Host smart-57027f84-ac93-4797-8c78-32b06875a986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986911455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1986911455
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4253602704
Short name T324
Test name
Test status
Simulation time 609621095 ps
CPU time 0.65 seconds
Started Aug 18 04:23:04 PM PDT 24
Finished Aug 18 04:23:05 PM PDT 24
Peak memory 183592 kb
Host smart-29db366b-f5a4-451b-b26a-a3932ae44cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253602704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4253602704
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1434728692
Short name T344
Test name
Test status
Simulation time 1440991136 ps
CPU time 3.56 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:23:00 PM PDT 24
Peak memory 192740 kb
Host smart-9df3c9e2-11ba-4779-881c-1f8a24cad6b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434728692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1434728692
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3360991503
Short name T351
Test name
Test status
Simulation time 371562041 ps
CPU time 2.03 seconds
Started Aug 18 04:22:54 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 198444 kb
Host smart-84346cc3-f225-4441-9dac-7484525a8455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360991503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3360991503
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3187696064
Short name T333
Test name
Test status
Simulation time 8174266019 ps
CPU time 4.04 seconds
Started Aug 18 04:22:49 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 198188 kb
Host smart-7ad62229-35ee-4b80-8e62-7bbf537eee96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187696064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3187696064
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3037909997
Short name T315
Test name
Test status
Simulation time 456601590 ps
CPU time 0.94 seconds
Started Aug 18 04:23:02 PM PDT 24
Finished Aug 18 04:23:03 PM PDT 24
Peak memory 195928 kb
Host smart-fc8bfbe3-41f4-4d55-8b9b-760c1fe12690
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037909997 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3037909997
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2483101468
Short name T70
Test name
Test status
Simulation time 367103950 ps
CPU time 1.05 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:23:00 PM PDT 24
Peak memory 193184 kb
Host smart-b99cd3d6-43bb-42da-8a55-1fe582889731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483101468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2483101468
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2535731491
Short name T310
Test name
Test status
Simulation time 395708404 ps
CPU time 1.11 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:54 PM PDT 24
Peak memory 192836 kb
Host smart-ce614e01-1e59-49c0-859c-5ba720c301fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535731491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2535731491
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2486377593
Short name T405
Test name
Test status
Simulation time 1350413912 ps
CPU time 0.88 seconds
Started Aug 18 04:22:59 PM PDT 24
Finished Aug 18 04:23:00 PM PDT 24
Peak memory 193668 kb
Host smart-8b4d707d-088a-4cfe-8a21-11f3de4a8e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486377593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2486377593
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3440254594
Short name T369
Test name
Test status
Simulation time 396495867 ps
CPU time 1.59 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:23:00 PM PDT 24
Peak memory 198436 kb
Host smart-816eb428-8778-48ce-a927-563c1c569b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440254594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3440254594
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2456607277
Short name T41
Test name
Test status
Simulation time 8673462453 ps
CPU time 4.17 seconds
Started Aug 18 04:23:01 PM PDT 24
Finished Aug 18 04:23:05 PM PDT 24
Peak memory 198188 kb
Host smart-76e9d8dd-4353-404d-a824-2ebb5c236242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456607277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2456607277
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4039173309
Short name T208
Test name
Test status
Simulation time 705063088 ps
CPU time 1.83 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:31 PM PDT 24
Peak memory 191464 kb
Host smart-35d21f7f-8192-42cf-8f62-0cfc16408697
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039173309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4039173309
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2929336202
Short name T58
Test name
Test status
Simulation time 5089201605 ps
CPU time 4.83 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 191824 kb
Host smart-10fcda02-249e-4b8a-a30f-5e936550c8ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929336202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2929336202
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3387015484
Short name T306
Test name
Test status
Simulation time 848616708 ps
CPU time 1.55 seconds
Started Aug 18 04:21:43 PM PDT 24
Finished Aug 18 04:21:45 PM PDT 24
Peak memory 182592 kb
Host smart-e7980af1-7c63-466a-80fa-c1cf31937527
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387015484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3387015484
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2904088770
Short name T309
Test name
Test status
Simulation time 367866005 ps
CPU time 1.17 seconds
Started Aug 18 04:22:31 PM PDT 24
Finished Aug 18 04:22:32 PM PDT 24
Peak memory 196148 kb
Host smart-07047461-6e06-43cc-bfd4-c2bd57668f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904088770 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2904088770
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2127011143
Short name T65
Test name
Test status
Simulation time 511786053 ps
CPU time 1.3 seconds
Started Aug 18 04:21:53 PM PDT 24
Finished Aug 18 04:21:55 PM PDT 24
Peak memory 192808 kb
Host smart-792f6995-01d1-4ea6-8bc8-5099b7d384cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127011143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2127011143
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2646093870
Short name T403
Test name
Test status
Simulation time 504982912 ps
CPU time 0.94 seconds
Started Aug 18 04:17:13 PM PDT 24
Finished Aug 18 04:17:14 PM PDT 24
Peak memory 192796 kb
Host smart-df3d225f-e702-48d0-a2e1-ac57317e282a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646093870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2646093870
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1450540194
Short name T407
Test name
Test status
Simulation time 546392388 ps
CPU time 0.61 seconds
Started Aug 18 04:21:53 PM PDT 24
Finished Aug 18 04:21:54 PM PDT 24
Peak memory 183448 kb
Host smart-cd60cd86-e365-4e06-b87a-68c13a2e318d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450540194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1450540194
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.191144615
Short name T296
Test name
Test status
Simulation time 309336921 ps
CPU time 0.97 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:30 PM PDT 24
Peak memory 183356 kb
Host smart-ef2fa8f2-c555-426d-bc8b-0e4e3fdc51c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191144615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.191144615
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1735934966
Short name T44
Test name
Test status
Simulation time 1326715434 ps
CPU time 2.63 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:32 PM PDT 24
Peak memory 192288 kb
Host smart-2e8f8612-86e2-464b-b970-ca42712937fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735934966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1735934966
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4160437529
Short name T387
Test name
Test status
Simulation time 482815408 ps
CPU time 1.35 seconds
Started Aug 18 04:17:13 PM PDT 24
Finished Aug 18 04:17:14 PM PDT 24
Peak memory 198412 kb
Host smart-34b7810a-4ec5-4292-86aa-f5c881753b44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160437529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4160437529
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.995532588
Short name T396
Test name
Test status
Simulation time 4457375629 ps
CPU time 1.99 seconds
Started Aug 18 04:22:29 PM PDT 24
Finished Aug 18 04:22:32 PM PDT 24
Peak memory 197508 kb
Host smart-76ceb2f1-9662-4807-8dd0-2f9d9aaf2bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995532588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.995532588
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2939246660
Short name T332
Test name
Test status
Simulation time 540591930 ps
CPU time 0.56 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:22:59 PM PDT 24
Peak memory 182352 kb
Host smart-fb39e404-ab9f-43c2-8e7d-15ecf1c1f751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939246660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2939246660
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1825095665
Short name T301
Test name
Test status
Simulation time 475548823 ps
CPU time 1.27 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:55 PM PDT 24
Peak memory 192692 kb
Host smart-761ea35b-a28b-4649-aba1-efc03464de41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825095665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1825095665
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1234593528
Short name T385
Test name
Test status
Simulation time 609776707 ps
CPU time 0.59 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:22:59 PM PDT 24
Peak memory 182808 kb
Host smart-92dfcf9a-1981-492e-a475-5769c057d957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234593528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1234593528
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.677193981
Short name T346
Test name
Test status
Simulation time 327398754 ps
CPU time 0.63 seconds
Started Aug 18 04:22:58 PM PDT 24
Finished Aug 18 04:22:59 PM PDT 24
Peak memory 182448 kb
Host smart-0e1c539b-1d23-4001-8e15-3a8a1e0a7380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677193981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.677193981
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.470509794
Short name T401
Test name
Test status
Simulation time 425884092 ps
CPU time 0.84 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:57 PM PDT 24
Peak memory 183600 kb
Host smart-9b926bfa-9779-49bb-b001-04962482a78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470509794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.470509794
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.131557387
Short name T364
Test name
Test status
Simulation time 400379528 ps
CPU time 0.55 seconds
Started Aug 18 04:23:01 PM PDT 24
Finished Aug 18 04:23:02 PM PDT 24
Peak memory 183600 kb
Host smart-d8c3c3cb-d4c9-46c9-b568-050554af79c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131557387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.131557387
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3682449841
Short name T370
Test name
Test status
Simulation time 387596815 ps
CPU time 0.65 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 182892 kb
Host smart-b639cf82-05b2-451f-a431-d8c8513f67a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682449841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3682449841
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4108283952
Short name T339
Test name
Test status
Simulation time 300231641 ps
CPU time 0.65 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 183572 kb
Host smart-e817666b-8367-4934-b8a8-3911e29e1ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108283952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4108283952
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1670858881
Short name T406
Test name
Test status
Simulation time 352403404 ps
CPU time 0.71 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 192836 kb
Host smart-f6e43e61-1cd7-4a16-a266-0172bb3ede81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670858881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1670858881
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2796183370
Short name T289
Test name
Test status
Simulation time 410462750 ps
CPU time 1.1 seconds
Started Aug 18 04:23:06 PM PDT 24
Finished Aug 18 04:23:07 PM PDT 24
Peak memory 183564 kb
Host smart-4709050e-978d-462f-a870-88fe15aad40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796183370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2796183370
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3785094723
Short name T386
Test name
Test status
Simulation time 443680483 ps
CPU time 0.72 seconds
Started Aug 18 04:22:02 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 183676 kb
Host smart-ea5bf65a-d6ef-4840-90a4-73a7acc2b1a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785094723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3785094723
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.79342618
Short name T361
Test name
Test status
Simulation time 7138080483 ps
CPU time 20.1 seconds
Started Aug 18 04:17:55 PM PDT 24
Finished Aug 18 04:18:15 PM PDT 24
Peak memory 196276 kb
Host smart-7cc056aa-ae95-45da-8f99-9de189aaa9f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79342618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit
_bash.79342618
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2760388671
Short name T373
Test name
Test status
Simulation time 1317463901 ps
CPU time 1.03 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:02 PM PDT 24
Peak memory 183820 kb
Host smart-9029d0da-cf1b-42ca-b683-617fd774ab29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760388671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2760388671
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3350650983
Short name T377
Test name
Test status
Simulation time 436685088 ps
CPU time 0.93 seconds
Started Aug 18 04:22:02 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 196992 kb
Host smart-325adac6-2b53-4bba-ba4e-1f2e3041f3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350650983 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3350650983
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2671675837
Short name T59
Test name
Test status
Simulation time 541911190 ps
CPU time 0.89 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 192864 kb
Host smart-0fda6c31-e1e6-4b41-b5f8-5f2f87734eed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671675837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2671675837
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3599625939
Short name T381
Test name
Test status
Simulation time 289635467 ps
CPU time 0.7 seconds
Started Aug 18 04:18:06 PM PDT 24
Finished Aug 18 04:18:07 PM PDT 24
Peak memory 183596 kb
Host smart-3cf3ec4b-6e4e-4e86-85c5-968edf6e3eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599625939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3599625939
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2573036694
Short name T418
Test name
Test status
Simulation time 367348807 ps
CPU time 0.98 seconds
Started Aug 18 04:22:51 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 183220 kb
Host smart-a4f6d4d0-4262-456c-9f34-7b83971df708
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573036694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2573036694
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.252003544
Short name T398
Test name
Test status
Simulation time 270407090 ps
CPU time 0.68 seconds
Started Aug 18 04:19:09 PM PDT 24
Finished Aug 18 04:19:10 PM PDT 24
Peak memory 183492 kb
Host smart-0f71983c-a7e2-4df3-a5e5-05078b1ac021
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252003544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.252003544
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3600986443
Short name T77
Test name
Test status
Simulation time 2854547785 ps
CPU time 6.25 seconds
Started Aug 18 04:20:14 PM PDT 24
Finished Aug 18 04:20:21 PM PDT 24
Peak memory 194404 kb
Host smart-edb89454-02d3-46ee-8695-ba3c28b2f902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600986443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3600986443
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1200385683
Short name T307
Test name
Test status
Simulation time 702067142 ps
CPU time 1.98 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 198408 kb
Host smart-d117f9b2-b9e4-440b-a29a-2e1e48aabacc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200385683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1200385683
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1468685335
Short name T200
Test name
Test status
Simulation time 8722713349 ps
CPU time 13.59 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:23:05 PM PDT 24
Peak memory 197992 kb
Host smart-87b7a8cd-c32f-4b7e-94e5-0b5c0aee8ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468685335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1468685335
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1102983812
Short name T376
Test name
Test status
Simulation time 438498580 ps
CPU time 1.17 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:22:57 PM PDT 24
Peak memory 192808 kb
Host smart-3b481eb4-914f-4b6c-84c0-58982805f554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102983812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1102983812
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.909103166
Short name T305
Test name
Test status
Simulation time 421630113 ps
CPU time 1.22 seconds
Started Aug 18 04:23:03 PM PDT 24
Finished Aug 18 04:23:05 PM PDT 24
Peak memory 192792 kb
Host smart-5e161169-0c4e-4140-9291-d1f6d288cf0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909103166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.909103166
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1697357368
Short name T314
Test name
Test status
Simulation time 353535895 ps
CPU time 0.72 seconds
Started Aug 18 04:23:00 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 192804 kb
Host smart-76f18605-49e1-4d93-9ccb-dc8f9ff4a7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697357368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1697357368
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1642668327
Short name T293
Test name
Test status
Simulation time 439291531 ps
CPU time 1.2 seconds
Started Aug 18 04:23:02 PM PDT 24
Finished Aug 18 04:23:03 PM PDT 24
Peak memory 183608 kb
Host smart-7604f32a-45b6-4cc8-ac0f-dabb12eb8e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642668327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1642668327
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.543270668
Short name T334
Test name
Test status
Simulation time 293868432 ps
CPU time 0.75 seconds
Started Aug 18 04:23:01 PM PDT 24
Finished Aug 18 04:23:02 PM PDT 24
Peak memory 192824 kb
Host smart-2c2d34f1-a7c0-4cb5-958f-5d4c17ebd444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543270668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.543270668
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1351789983
Short name T308
Test name
Test status
Simulation time 491739483 ps
CPU time 0.59 seconds
Started Aug 18 04:23:13 PM PDT 24
Finished Aug 18 04:23:14 PM PDT 24
Peak memory 192816 kb
Host smart-db8aa43a-bb1f-475e-9f28-31f47ca73d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351789983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1351789983
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.72189488
Short name T298
Test name
Test status
Simulation time 318928652 ps
CPU time 0.68 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:22:57 PM PDT 24
Peak memory 192820 kb
Host smart-d673b0d0-7de2-4cd8-a308-efafb3cbe74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72189488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.72189488
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3405046744
Short name T316
Test name
Test status
Simulation time 284054470 ps
CPU time 0.66 seconds
Started Aug 18 04:23:01 PM PDT 24
Finished Aug 18 04:23:02 PM PDT 24
Peak memory 183608 kb
Host smart-d0881207-8105-47ef-90df-212c646c016f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405046744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3405046744
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4147888884
Short name T297
Test name
Test status
Simulation time 443097370 ps
CPU time 1.08 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 183592 kb
Host smart-a5919115-c2fb-4cf1-a3c9-5c66dda94e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147888884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4147888884
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1490123288
Short name T416
Test name
Test status
Simulation time 362534157 ps
CPU time 0.67 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:22:57 PM PDT 24
Peak memory 183592 kb
Host smart-0e73c7d2-677b-4d64-9f93-ef12fd3c0860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490123288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1490123288
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3015148839
Short name T63
Test name
Test status
Simulation time 495681927 ps
CPU time 0.98 seconds
Started Aug 18 04:19:39 PM PDT 24
Finished Aug 18 04:19:40 PM PDT 24
Peak memory 193760 kb
Host smart-676f89f4-7813-4300-8e02-a6a368529394
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015148839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3015148839
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1092612111
Short name T66
Test name
Test status
Simulation time 6164960897 ps
CPU time 7.47 seconds
Started Aug 18 04:19:14 PM PDT 24
Finished Aug 18 04:19:21 PM PDT 24
Peak memory 196260 kb
Host smart-e85fa504-8e36-414d-bd16-e28ca4e1ba49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092612111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1092612111
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.431107998
Short name T392
Test name
Test status
Simulation time 695927008 ps
CPU time 1.56 seconds
Started Aug 18 04:22:27 PM PDT 24
Finished Aug 18 04:22:29 PM PDT 24
Peak memory 183644 kb
Host smart-412c7945-430d-4eaa-b930-b875b1b393c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431107998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.431107998
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4166966261
Short name T414
Test name
Test status
Simulation time 433003931 ps
CPU time 1.31 seconds
Started Aug 18 04:22:44 PM PDT 24
Finished Aug 18 04:22:46 PM PDT 24
Peak memory 196872 kb
Host smart-e85e3860-d3c4-4422-a610-4c0cadaa8635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166966261 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4166966261
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.91755397
Short name T415
Test name
Test status
Simulation time 392265769 ps
CPU time 0.82 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 192684 kb
Host smart-9c993868-fd37-4e71-9fed-394d4f764df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91755397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.91755397
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1349297028
Short name T300
Test name
Test status
Simulation time 304357016 ps
CPU time 0.62 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 192660 kb
Host smart-08c981b0-35be-416d-825b-067856aa630a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349297028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1349297028
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.258104312
Short name T350
Test name
Test status
Simulation time 434574480 ps
CPU time 0.61 seconds
Started Aug 18 04:19:37 PM PDT 24
Finished Aug 18 04:19:37 PM PDT 24
Peak memory 183428 kb
Host smart-883c7969-dd27-4198-a95c-3cf82558935f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258104312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.258104312
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2365624550
Short name T327
Test name
Test status
Simulation time 443512089 ps
CPU time 0.69 seconds
Started Aug 18 04:22:02 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 183508 kb
Host smart-ae4f8d3f-a0c8-4ba9-8f0d-3777359a7134
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365624550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2365624550
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3454068283
Short name T78
Test name
Test status
Simulation time 1477213043 ps
CPU time 2.65 seconds
Started Aug 18 04:22:43 PM PDT 24
Finished Aug 18 04:22:46 PM PDT 24
Peak memory 193948 kb
Host smart-33196828-bd21-40cf-b19a-4956fb4c5f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454068283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3454068283
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2433205953
Short name T318
Test name
Test status
Simulation time 576806033 ps
CPU time 2.85 seconds
Started Aug 18 04:18:32 PM PDT 24
Finished Aug 18 04:18:35 PM PDT 24
Peak memory 198420 kb
Host smart-16fece65-26e2-45e5-9e2c-4d105b8c6c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433205953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2433205953
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3239244319
Short name T349
Test name
Test status
Simulation time 419783655 ps
CPU time 1.13 seconds
Started Aug 18 04:22:56 PM PDT 24
Finished Aug 18 04:22:57 PM PDT 24
Peak memory 192812 kb
Host smart-2e4304a0-8785-45d6-8f6e-650152e39520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239244319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3239244319
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.19400465
Short name T379
Test name
Test status
Simulation time 291330042 ps
CPU time 0.96 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:54 PM PDT 24
Peak memory 192692 kb
Host smart-2b8a52d8-6497-49e3-8f19-1f5e498bba84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.19400465
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.179572459
Short name T390
Test name
Test status
Simulation time 318757592 ps
CPU time 0.84 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 192776 kb
Host smart-14f53013-3338-4b78-a595-00cd42a377f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179572459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.179572459
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.696244728
Short name T317
Test name
Test status
Simulation time 413854160 ps
CPU time 0.83 seconds
Started Aug 18 04:22:55 PM PDT 24
Finished Aug 18 04:22:56 PM PDT 24
Peak memory 183504 kb
Host smart-adb539d5-7c8c-420f-b035-376b8f9d6c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696244728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.696244728
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3910183995
Short name T372
Test name
Test status
Simulation time 425172504 ps
CPU time 0.84 seconds
Started Aug 18 04:23:06 PM PDT 24
Finished Aug 18 04:23:07 PM PDT 24
Peak memory 183540 kb
Host smart-250a9473-a9dd-44c3-8a3f-691ec772b01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910183995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3910183995
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3108625314
Short name T410
Test name
Test status
Simulation time 413557773 ps
CPU time 1.25 seconds
Started Aug 18 04:23:06 PM PDT 24
Finished Aug 18 04:23:07 PM PDT 24
Peak memory 192784 kb
Host smart-f0eda65b-5138-4c88-8253-1d19b907765a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108625314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3108625314
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3230727039
Short name T342
Test name
Test status
Simulation time 533544479 ps
CPU time 0.76 seconds
Started Aug 18 04:23:06 PM PDT 24
Finished Aug 18 04:23:07 PM PDT 24
Peak memory 183560 kb
Host smart-20960c89-fc93-4176-89e6-43ab3e1dffe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230727039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3230727039
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2784832158
Short name T287
Test name
Test status
Simulation time 577354376 ps
CPU time 0.63 seconds
Started Aug 18 04:23:07 PM PDT 24
Finished Aug 18 04:23:08 PM PDT 24
Peak memory 183564 kb
Host smart-69348bef-dd08-4303-85d6-a2cae886f3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784832158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2784832158
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2778373369
Short name T338
Test name
Test status
Simulation time 418184228 ps
CPU time 0.83 seconds
Started Aug 18 04:23:00 PM PDT 24
Finished Aug 18 04:23:01 PM PDT 24
Peak memory 192792 kb
Host smart-da9bc001-0fd5-44d8-8666-40cbcfefa3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778373369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2778373369
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4199079757
Short name T285
Test name
Test status
Simulation time 359271148 ps
CPU time 0.66 seconds
Started Aug 18 04:23:04 PM PDT 24
Finished Aug 18 04:23:05 PM PDT 24
Peak memory 183592 kb
Host smart-9667eeee-da80-408f-abea-7ea80af9d8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199079757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4199079757
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.700901756
Short name T352
Test name
Test status
Simulation time 507600659 ps
CPU time 1.09 seconds
Started Aug 18 04:22:32 PM PDT 24
Finished Aug 18 04:22:33 PM PDT 24
Peak memory 196116 kb
Host smart-eb19a459-96e5-4a5f-a280-2bde294c72fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700901756 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.700901756
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4549440
Short name T79
Test name
Test status
Simulation time 495765603 ps
CPU time 1.31 seconds
Started Aug 18 04:18:55 PM PDT 24
Finished Aug 18 04:18:57 PM PDT 24
Peak memory 192808 kb
Host smart-9c38cabe-e09d-4cfe-8264-e6b50bfc4099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4549440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4549440
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.376207189
Short name T331
Test name
Test status
Simulation time 279671137 ps
CPU time 0.94 seconds
Started Aug 18 04:21:48 PM PDT 24
Finished Aug 18 04:21:50 PM PDT 24
Peak memory 183192 kb
Host smart-38f7286c-48e3-4b99-8243-8194fe1cf27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376207189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.376207189
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.198614020
Short name T375
Test name
Test status
Simulation time 1752192817 ps
CPU time 1.69 seconds
Started Aug 18 04:20:43 PM PDT 24
Finished Aug 18 04:20:45 PM PDT 24
Peak memory 192784 kb
Host smart-c5511a9f-6bd7-496a-abb9-f0ec3b0db09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198614020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.198614020
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2657727183
Short name T360
Test name
Test status
Simulation time 992685718 ps
CPU time 1.91 seconds
Started Aug 18 04:22:27 PM PDT 24
Finished Aug 18 04:22:29 PM PDT 24
Peak memory 197640 kb
Host smart-9abd4d64-ad91-44cd-a96c-6852ef0646fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657727183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2657727183
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1678168141
Short name T196
Test name
Test status
Simulation time 4124145387 ps
CPU time 2.68 seconds
Started Aug 18 04:21:44 PM PDT 24
Finished Aug 18 04:21:47 PM PDT 24
Peak memory 197660 kb
Host smart-30e613b2-8f5a-481f-9054-95b00ede4cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678168141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1678168141
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2459276803
Short name T322
Test name
Test status
Simulation time 460255305 ps
CPU time 1.53 seconds
Started Aug 18 04:22:21 PM PDT 24
Finished Aug 18 04:22:23 PM PDT 24
Peak memory 196824 kb
Host smart-62f078ad-edc2-4b16-b8a0-e7ffddfa6230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459276803 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2459276803
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.344967940
Short name T366
Test name
Test status
Simulation time 310503679 ps
CPU time 0.7 seconds
Started Aug 18 04:18:46 PM PDT 24
Finished Aug 18 04:18:47 PM PDT 24
Peak memory 192160 kb
Host smart-662d1758-ccad-47db-a586-3c5890f497ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344967940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.344967940
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3559077109
Short name T393
Test name
Test status
Simulation time 479949440 ps
CPU time 0.62 seconds
Started Aug 18 04:20:52 PM PDT 24
Finished Aug 18 04:20:53 PM PDT 24
Peak memory 183588 kb
Host smart-6536fd3b-5ac7-4a42-96aa-bbed2afba635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559077109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3559077109
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3886287764
Short name T358
Test name
Test status
Simulation time 1372839661 ps
CPU time 2.55 seconds
Started Aug 18 04:18:58 PM PDT 24
Finished Aug 18 04:19:01 PM PDT 24
Peak memory 193272 kb
Host smart-bd982b4d-6a95-4a64-9608-0e78e3a78655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886287764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3886287764
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.141974364
Short name T323
Test name
Test status
Simulation time 679858887 ps
CPU time 2.07 seconds
Started Aug 18 04:22:28 PM PDT 24
Finished Aug 18 04:22:30 PM PDT 24
Peak memory 198448 kb
Host smart-fea385ab-fcdb-4df6-8ece-370e3f3c5c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141974364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.141974364
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3015274135
Short name T402
Test name
Test status
Simulation time 8248105342 ps
CPU time 6.64 seconds
Started Aug 18 04:22:33 PM PDT 24
Finished Aug 18 04:22:39 PM PDT 24
Peak memory 198052 kb
Host smart-e910f686-d7ce-4b60-a440-6dfb4656b655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015274135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3015274135
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3565656777
Short name T336
Test name
Test status
Simulation time 519312109 ps
CPU time 0.8 seconds
Started Aug 18 04:22:31 PM PDT 24
Finished Aug 18 04:22:32 PM PDT 24
Peak memory 195496 kb
Host smart-2492e96b-19ee-49e8-a244-b2a88fc6424b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565656777 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3565656777
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3942306394
Short name T371
Test name
Test status
Simulation time 394652680 ps
CPU time 0.99 seconds
Started Aug 18 04:20:41 PM PDT 24
Finished Aug 18 04:20:43 PM PDT 24
Peak memory 193020 kb
Host smart-0e33d492-730a-4fd2-912e-df912949b67e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942306394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3942306394
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3730205389
Short name T378
Test name
Test status
Simulation time 343984835 ps
CPU time 0.65 seconds
Started Aug 18 04:22:34 PM PDT 24
Finished Aug 18 04:22:35 PM PDT 24
Peak memory 183592 kb
Host smart-2f5e8fce-940a-4067-9c80-58147c0f162e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730205389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3730205389
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3542975205
Short name T388
Test name
Test status
Simulation time 2778714653 ps
CPU time 2.06 seconds
Started Aug 18 04:22:22 PM PDT 24
Finished Aug 18 04:22:24 PM PDT 24
Peak memory 194088 kb
Host smart-217226f5-77ab-4053-afbb-3044dac50fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542975205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3542975205
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3065646228
Short name T288
Test name
Test status
Simulation time 400907763 ps
CPU time 1.63 seconds
Started Aug 18 04:22:23 PM PDT 24
Finished Aug 18 04:22:25 PM PDT 24
Peak memory 198452 kb
Host smart-76cc65b5-bdc1-48dc-8403-f91b22abe397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065646228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3065646228
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2502568927
Short name T413
Test name
Test status
Simulation time 4325421032 ps
CPU time 2.13 seconds
Started Aug 18 04:19:59 PM PDT 24
Finished Aug 18 04:20:02 PM PDT 24
Peak memory 196772 kb
Host smart-7d5fb0f1-3f35-4e40-a183-953f8c6843c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502568927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2502568927
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1075238745
Short name T345
Test name
Test status
Simulation time 478638142 ps
CPU time 0.8 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 195472 kb
Host smart-aea0c660-1b78-4c0f-bdaf-c01063ca23d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075238745 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1075238745
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2540820864
Short name T69
Test name
Test status
Simulation time 392820342 ps
CPU time 0.73 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:30 PM PDT 24
Peak memory 191528 kb
Host smart-f02c2217-31e2-47fb-b01f-781b58ef908b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540820864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2540820864
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3112632969
Short name T404
Test name
Test status
Simulation time 431673122 ps
CPU time 0.82 seconds
Started Aug 18 04:22:53 PM PDT 24
Finished Aug 18 04:22:54 PM PDT 24
Peak memory 183600 kb
Host smart-328669bb-6d38-41a2-b57c-1485e4107749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112632969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3112632969
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2255140871
Short name T74
Test name
Test status
Simulation time 1092664125 ps
CPU time 2.12 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:55 PM PDT 24
Peak memory 193932 kb
Host smart-8e8e2467-4c8f-4dca-a3bf-65502afb1146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255140871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2255140871
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.42883552
Short name T411
Test name
Test status
Simulation time 539362002 ps
CPU time 1.89 seconds
Started Aug 18 04:22:35 PM PDT 24
Finished Aug 18 04:22:38 PM PDT 24
Peak memory 197676 kb
Host smart-e725052b-dce1-412d-aed1-2a2c3f06d841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.42883552
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1545731972
Short name T343
Test name
Test status
Simulation time 9006317924 ps
CPU time 3.15 seconds
Started Aug 18 04:22:47 PM PDT 24
Finished Aug 18 04:22:51 PM PDT 24
Peak memory 198068 kb
Host smart-5330b089-ee16-46c2-960b-8f3f96ea6d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545731972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1545731972
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2796634158
Short name T367
Test name
Test status
Simulation time 509319365 ps
CPU time 1.32 seconds
Started Aug 18 04:22:01 PM PDT 24
Finished Aug 18 04:22:03 PM PDT 24
Peak memory 196044 kb
Host smart-0b1441d4-f7ec-4fa9-900c-e81de7334b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796634158 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2796634158
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2479223204
Short name T56
Test name
Test status
Simulation time 437565918 ps
CPU time 1.01 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:53 PM PDT 24
Peak memory 191696 kb
Host smart-fdb3bfd8-5c48-4e69-a147-3fb2bf4d19d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479223204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2479223204
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.874766944
Short name T347
Test name
Test status
Simulation time 477559429 ps
CPU time 0.86 seconds
Started Aug 18 04:19:29 PM PDT 24
Finished Aug 18 04:19:30 PM PDT 24
Peak memory 182700 kb
Host smart-032c321a-fc25-48ad-b96d-24ab28d794bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874766944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.874766944
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1804794061
Short name T330
Test name
Test status
Simulation time 945108558 ps
CPU time 1.34 seconds
Started Aug 18 04:22:25 PM PDT 24
Finished Aug 18 04:22:27 PM PDT 24
Peak memory 193856 kb
Host smart-9b87295d-fea2-44dd-bc11-c605885ae034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804794061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1804794061
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4189210354
Short name T383
Test name
Test status
Simulation time 501184248 ps
CPU time 1.72 seconds
Started Aug 18 04:22:08 PM PDT 24
Finished Aug 18 04:22:10 PM PDT 24
Peak memory 197284 kb
Host smart-b5d4e4f6-0bd4-49ea-abe9-ba1fdca06617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189210354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4189210354
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.521626756
Short name T195
Test name
Test status
Simulation time 4138995135 ps
CPU time 6.25 seconds
Started Aug 18 04:22:52 PM PDT 24
Finished Aug 18 04:22:58 PM PDT 24
Peak memory 197772 kb
Host smart-60036672-0865-4b4d-92cf-c8df21bf73f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521626756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.521626756
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3162239599
Short name T1
Test name
Test status
Simulation time 12389431567 ps
CPU time 17.44 seconds
Started Aug 18 04:26:28 PM PDT 24
Finished Aug 18 04:26:45 PM PDT 24
Peak memory 192008 kb
Host smart-61489cf1-e202-4bd6-9239-ce0d4c577ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162239599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3162239599
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1513769663
Short name T282
Test name
Test status
Simulation time 474357034 ps
CPU time 1.25 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:26:38 PM PDT 24
Peak memory 196728 kb
Host smart-da55d90c-a098-4d5f-9f4e-1262f7490523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513769663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1513769663
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1893630573
Short name T25
Test name
Test status
Simulation time 27634745282 ps
CPU time 37.91 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:27:43 PM PDT 24
Peak memory 192096 kb
Host smart-2a0c5778-04fd-4906-8a56-1dd731020cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893630573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1893630573
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1574902499
Short name T22
Test name
Test status
Simulation time 7867543482 ps
CPU time 3.62 seconds
Started Aug 18 04:26:28 PM PDT 24
Finished Aug 18 04:26:32 PM PDT 24
Peak memory 215312 kb
Host smart-314a9e81-7129-46c5-b3c7-8574da502c53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574902499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1574902499
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2488427530
Short name T226
Test name
Test status
Simulation time 595622935 ps
CPU time 0.74 seconds
Started Aug 18 04:26:22 PM PDT 24
Finished Aug 18 04:26:22 PM PDT 24
Peak memory 191932 kb
Host smart-05d8112c-d5a8-41ea-9d03-694732d219f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488427530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2488427530
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.923086567
Short name T193
Test name
Test status
Simulation time 510823691 ps
CPU time 1.11 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:41 PM PDT 24
Peak memory 196724 kb
Host smart-550cb12b-c1fb-4cb0-b88e-66c53d975660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923086567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.923086567
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2220879655
Short name T259
Test name
Test status
Simulation time 26355447579 ps
CPU time 9.71 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:48 PM PDT 24
Peak memory 196988 kb
Host smart-13af9c26-d8a1-4233-b3a9-0384d16170e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220879655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2220879655
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1667292078
Short name T271
Test name
Test status
Simulation time 347642757 ps
CPU time 0.86 seconds
Started Aug 18 04:26:40 PM PDT 24
Finished Aug 18 04:26:41 PM PDT 24
Peak memory 191900 kb
Host smart-a0e50965-7b77-4497-b14c-d191979f3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667292078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1667292078
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3664901360
Short name T18
Test name
Test status
Simulation time 2382558448 ps
CPU time 4.05 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:48 PM PDT 24
Peak memory 206888 kb
Host smart-c0bd8662-1405-4479-bc5d-7facc024339c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664901360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3664901360
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2734821924
Short name T260
Test name
Test status
Simulation time 18412874635 ps
CPU time 7.5 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:46 PM PDT 24
Peak memory 191988 kb
Host smart-b4dc2286-d0de-41c6-ba84-f35e034e8459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734821924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2734821924
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2031824037
Short name T28
Test name
Test status
Simulation time 391579011 ps
CPU time 1.14 seconds
Started Aug 18 04:26:40 PM PDT 24
Finished Aug 18 04:26:42 PM PDT 24
Peak memory 191892 kb
Host smart-a41b9a9c-1872-4eed-b366-e3798a05b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031824037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2031824037
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3944409878
Short name T213
Test name
Test status
Simulation time 21501717273 ps
CPU time 31.82 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 197024 kb
Host smart-e39eccfe-c0e0-4a73-8f73-bd64ef32b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944409878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3944409878
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2500124351
Short name T272
Test name
Test status
Simulation time 547942418 ps
CPU time 1.24 seconds
Started Aug 18 04:26:48 PM PDT 24
Finished Aug 18 04:26:50 PM PDT 24
Peak memory 191908 kb
Host smart-73d0191c-73e2-4061-a51d-f6a76b8f70d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500124351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2500124351
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2165719062
Short name T220
Test name
Test status
Simulation time 28503954064 ps
CPU time 10.49 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:50 PM PDT 24
Peak memory 191992 kb
Host smart-ecca5216-2c35-4f45-9689-44668a14bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165719062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2165719062
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1438053610
Short name T234
Test name
Test status
Simulation time 512465622 ps
CPU time 0.61 seconds
Started Aug 18 04:26:55 PM PDT 24
Finished Aug 18 04:26:55 PM PDT 24
Peak memory 196728 kb
Host smart-dbbedbcb-0b4a-4263-b9c3-859a8f1be2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438053610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1438053610
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2026630579
Short name T248
Test name
Test status
Simulation time 24235080255 ps
CPU time 16.18 seconds
Started Aug 18 04:26:45 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 192020 kb
Host smart-929c3243-175b-4bad-9508-7bdbe36f1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026630579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2026630579
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2741500490
Short name T266
Test name
Test status
Simulation time 426217963 ps
CPU time 0.87 seconds
Started Aug 18 04:26:25 PM PDT 24
Finished Aug 18 04:26:25 PM PDT 24
Peak memory 196764 kb
Host smart-aa7a9e68-ce9a-4521-9eef-b7b94eb88688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741500490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2741500490
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.201279775
Short name T207
Test name
Test status
Simulation time 32475889322 ps
CPU time 13.16 seconds
Started Aug 18 04:26:50 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 192004 kb
Host smart-f8fb61b2-84b5-4866-ba5a-9bc9d0babd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201279775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.201279775
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.797179694
Short name T217
Test name
Test status
Simulation time 373456868 ps
CPU time 0.84 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:15 PM PDT 24
Peak memory 196740 kb
Host smart-49a85222-de50-4348-ad79-03d4b5280e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797179694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.797179694
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3955404670
Short name T201
Test name
Test status
Simulation time 1008609638 ps
CPU time 7.48 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:51 PM PDT 24
Peak memory 198592 kb
Host smart-f7c369b4-660b-41f3-8a0d-3dce721cbeee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955404670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3955404670
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2125395523
Short name T54
Test name
Test status
Simulation time 7712040993 ps
CPU time 11.23 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:50 PM PDT 24
Peak memory 197024 kb
Host smart-932cb08c-2c94-4c62-9c0b-18b9259819d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125395523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2125395523
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.201686054
Short name T33
Test name
Test status
Simulation time 534677882 ps
CPU time 0.78 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:26:44 PM PDT 24
Peak memory 191876 kb
Host smart-74c4aa14-19c0-4386-bdc8-e3f2c502215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201686054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.201686054
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1633776889
Short name T277
Test name
Test status
Simulation time 30148493549 ps
CPU time 10.89 seconds
Started Aug 18 04:26:45 PM PDT 24
Finished Aug 18 04:27:01 PM PDT 24
Peak memory 192000 kb
Host smart-cc63df33-2488-4202-9130-e62bd1dbd87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633776889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1633776889
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1998183422
Short name T228
Test name
Test status
Simulation time 590966151 ps
CPU time 0.78 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 196772 kb
Host smart-70f1d9e3-a4cd-4d52-8932-9fe8a8d9a0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998183422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1998183422
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3360868339
Short name T210
Test name
Test status
Simulation time 18660264247 ps
CPU time 2 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:27:06 PM PDT 24
Peak memory 191932 kb
Host smart-01bd7e80-9a5e-4fdd-bde0-7500ee1643cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360868339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3360868339
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4227486066
Short name T222
Test name
Test status
Simulation time 401738297 ps
CPU time 0.71 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 191940 kb
Host smart-8700b6b1-8d18-4d64-ac8e-d5313e64af3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227486066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4227486066
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1140708099
Short name T45
Test name
Test status
Simulation time 41834380949 ps
CPU time 56.92 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:28:11 PM PDT 24
Peak memory 196996 kb
Host smart-9939df96-3ca9-42c4-a443-50bc0fb7d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140708099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1140708099
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3503997651
Short name T255
Test name
Test status
Simulation time 507429265 ps
CPU time 1.28 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:40 PM PDT 24
Peak memory 191948 kb
Host smart-ea833359-2b61-48fe-af48-4378ecabcf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503997651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3503997651
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.758747595
Short name T202
Test name
Test status
Simulation time 26701623910 ps
CPU time 10.21 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:49 PM PDT 24
Peak memory 191836 kb
Host smart-c2120a18-6472-498f-9a8c-be08b374cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758747595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.758747595
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3158033424
Short name T23
Test name
Test status
Simulation time 4150746450 ps
CPU time 6.98 seconds
Started Aug 18 04:26:48 PM PDT 24
Finished Aug 18 04:26:55 PM PDT 24
Peak memory 215720 kb
Host smart-c82984a0-57ba-45dc-824f-44a940c9345e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158033424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3158033424
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1901811956
Short name T253
Test name
Test status
Simulation time 522490679 ps
CPU time 0.72 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:44 PM PDT 24
Peak memory 191748 kb
Host smart-7aa9efbc-d1c5-43ca-a99c-04bf53c958b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901811956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1901811956
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3179190951
Short name T9
Test name
Test status
Simulation time 29608943183 ps
CPU time 12.88 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:29 PM PDT 24
Peak memory 192024 kb
Host smart-12192bab-be3a-4663-8df2-1d5de5e8736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179190951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3179190951
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2262831542
Short name T238
Test name
Test status
Simulation time 548973858 ps
CPU time 1.28 seconds
Started Aug 18 04:27:26 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 196752 kb
Host smart-9ad0c68b-2c3e-43a4-b194-31bb01d7e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262831542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2262831542
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.66409402
Short name T236
Test name
Test status
Simulation time 29865221879 ps
CPU time 48.41 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:57 PM PDT 24
Peak memory 197028 kb
Host smart-7e19d8ba-f87b-4793-9a1d-fc9ed8cb4f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66409402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.66409402
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2730123946
Short name T221
Test name
Test status
Simulation time 399861327 ps
CPU time 0.72 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 196712 kb
Host smart-ab4ce0bb-9e95-499f-bc2e-21794765e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730123946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2730123946
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.834381129
Short name T265
Test name
Test status
Simulation time 34058512358 ps
CPU time 8.11 seconds
Started Aug 18 04:26:42 PM PDT 24
Finished Aug 18 04:26:51 PM PDT 24
Peak memory 192024 kb
Host smart-033e7fc1-c4c1-4350-8752-6f7d119c846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834381129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.834381129
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3953753216
Short name T245
Test name
Test status
Simulation time 465806560 ps
CPU time 0.76 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:26:59 PM PDT 24
Peak memory 191924 kb
Host smart-4971d2c2-bd8c-40bd-928e-4198d85da566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953753216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3953753216
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4099522266
Short name T219
Test name
Test status
Simulation time 1052264737 ps
CPU time 0.88 seconds
Started Aug 18 04:26:57 PM PDT 24
Finished Aug 18 04:26:58 PM PDT 24
Peak memory 196676 kb
Host smart-5e8489b7-018f-41f3-a6b0-35c24f83ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099522266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4099522266
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.443825191
Short name T270
Test name
Test status
Simulation time 566015558 ps
CPU time 1.38 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:05 PM PDT 24
Peak memory 191872 kb
Host smart-3d9eab60-59c3-45fd-b6a9-9ccaa165783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443825191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.443825191
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2794624712
Short name T194
Test name
Test status
Simulation time 456520187 ps
CPU time 0.88 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:13 PM PDT 24
Peak memory 196776 kb
Host smart-2e518be8-78e3-4830-8dcf-8a3faaf8d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794624712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2794624712
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.297474168
Short name T244
Test name
Test status
Simulation time 39602319078 ps
CPU time 54.77 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:28:07 PM PDT 24
Peak memory 192020 kb
Host smart-f3840d22-83fa-4c3c-923c-dd52402e5d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297474168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.297474168
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1589371911
Short name T242
Test name
Test status
Simulation time 459914659 ps
CPU time 1.25 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:26:44 PM PDT 24
Peak memory 191880 kb
Host smart-97b6a6ad-80f9-450a-bfe4-5f8936d59411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589371911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1589371911
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.481848161
Short name T5
Test name
Test status
Simulation time 22995555223 ps
CPU time 30.65 seconds
Started Aug 18 04:27:23 PM PDT 24
Finished Aug 18 04:27:54 PM PDT 24
Peak memory 192036 kb
Host smart-1331abb1-c5f0-41ee-b564-76572f0fb97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481848161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.481848161
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2570190657
Short name T214
Test name
Test status
Simulation time 595547428 ps
CPU time 1 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:26:59 PM PDT 24
Peak memory 191900 kb
Host smart-6c0876bc-92c8-4a31-ada3-08ae0f695682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570190657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2570190657
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2779101440
Short name T243
Test name
Test status
Simulation time 18007399604 ps
CPU time 13.8 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 191976 kb
Host smart-f1624699-69f4-4de2-a96f-36e2b19fc717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779101440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2779101440
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2492288233
Short name T280
Test name
Test status
Simulation time 399983991 ps
CPU time 0.75 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:26:44 PM PDT 24
Peak memory 196744 kb
Host smart-d422e6e3-6852-420d-8640-8eafd8d206cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492288233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2492288233
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.913837593
Short name T83
Test name
Test status
Simulation time 2721605673 ps
CPU time 17.32 seconds
Started Aug 18 04:26:55 PM PDT 24
Finished Aug 18 04:27:12 PM PDT 24
Peak memory 213396 kb
Host smart-3011c8f6-adb3-416d-bd23-045ba80d8948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913837593 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.913837593
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2502158998
Short name T251
Test name
Test status
Simulation time 56716571386 ps
CPU time 74.45 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:28:27 PM PDT 24
Peak memory 197008 kb
Host smart-afac5907-20b8-46a8-9fb8-c55b1d671c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502158998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2502158998
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1477469023
Short name T267
Test name
Test status
Simulation time 567641188 ps
CPU time 0.73 seconds
Started Aug 18 04:27:04 PM PDT 24
Finished Aug 18 04:27:05 PM PDT 24
Peak memory 191936 kb
Host smart-fb412d75-a0ad-4bc4-9ccd-7dc1588fa1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477469023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1477469023
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.731117719
Short name T82
Test name
Test status
Simulation time 2295620530 ps
CPU time 15.6 seconds
Started Aug 18 04:27:05 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 198628 kb
Host smart-bad2d7f0-f284-4b85-af6a-ff2b9aa51b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731117719 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.731117719
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1036117587
Short name T258
Test name
Test status
Simulation time 5356711115 ps
CPU time 2.37 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:26:59 PM PDT 24
Peak memory 191984 kb
Host smart-3bebf4a1-5b1d-4e7e-950a-850df810567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036117587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1036117587
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.359881380
Short name T279
Test name
Test status
Simulation time 446328769 ps
CPU time 1.18 seconds
Started Aug 18 04:27:25 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 191904 kb
Host smart-414c789a-3b51-4b06-9cf0-d308750046d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359881380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.359881380
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2702648031
Short name T256
Test name
Test status
Simulation time 4737149690 ps
CPU time 4.01 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 191956 kb
Host smart-5fbf7420-4a52-4cad-99fc-8cdd9d930132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702648031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2702648031
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2728103017
Short name T284
Test name
Test status
Simulation time 575461084 ps
CPU time 0.78 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 191908 kb
Host smart-fbc58801-db30-4ab0-a28b-91a9e44e2ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728103017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2728103017
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3348545369
Short name T224
Test name
Test status
Simulation time 25480748095 ps
CPU time 35.92 seconds
Started Aug 18 04:26:26 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 192004 kb
Host smart-e485553b-eb03-4929-a034-bd85759d0f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348545369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3348545369
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1127487586
Short name T19
Test name
Test status
Simulation time 8679840028 ps
CPU time 2.81 seconds
Started Aug 18 04:26:42 PM PDT 24
Finished Aug 18 04:26:45 PM PDT 24
Peak memory 216076 kb
Host smart-ce8ebd15-f354-4361-b29b-e2651bc26fc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127487586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1127487586
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2098589175
Short name T53
Test name
Test status
Simulation time 487116906 ps
CPU time 0.97 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 191932 kb
Host smart-8156e689-0d13-4e12-8788-a31dd5001790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098589175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2098589175
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.729983044
Short name T205
Test name
Test status
Simulation time 38995482048 ps
CPU time 12.52 seconds
Started Aug 18 04:26:58 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 192016 kb
Host smart-ee345bc5-5c8f-4d84-b256-c08dfec462ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729983044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.729983044
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.415502338
Short name T215
Test name
Test status
Simulation time 576138759 ps
CPU time 0.72 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 196712 kb
Host smart-8a06f4bb-5c89-48c2-a824-4a49ec193d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415502338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.415502338
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3719878275
Short name T232
Test name
Test status
Simulation time 9919171864 ps
CPU time 4.07 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 197012 kb
Host smart-93194810-b407-433a-b7c6-e13f42b61558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719878275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3719878275
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3831583784
Short name T216
Test name
Test status
Simulation time 431873025 ps
CPU time 1.16 seconds
Started Aug 18 04:27:10 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 191964 kb
Host smart-b8c5b623-5dc0-43d7-8a2e-5fd5212566f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831583784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3831583784
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2950210845
Short name T7
Test name
Test status
Simulation time 43614073323 ps
CPU time 6.48 seconds
Started Aug 18 04:27:12 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 191992 kb
Host smart-22535d34-1b82-4551-843a-24e310665046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950210845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2950210845
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.167328566
Short name T211
Test name
Test status
Simulation time 387301461 ps
CPU time 0.7 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:27:28 PM PDT 24
Peak memory 191948 kb
Host smart-6129ac84-3909-46f2-ad00-adf61576ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167328566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.167328566
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.481673500
Short name T250
Test name
Test status
Simulation time 53977814590 ps
CPU time 84.3 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:28:41 PM PDT 24
Peak memory 197032 kb
Host smart-dc109dd2-97d5-448b-b832-28146c79ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481673500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.481673500
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.433994050
Short name T36
Test name
Test status
Simulation time 545099067 ps
CPU time 0.77 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:08 PM PDT 24
Peak memory 191936 kb
Host smart-1dbff5cc-2f9f-4a53-8067-bbb0e70d2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433994050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.433994050
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1805224079
Short name T89
Test name
Test status
Simulation time 19589272098 ps
CPU time 29.88 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:27:48 PM PDT 24
Peak memory 191960 kb
Host smart-2f857b85-9f9f-4774-a788-63b7e395f900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805224079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1805224079
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1559642465
Short name T231
Test name
Test status
Simulation time 595964557 ps
CPU time 1.44 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:00 PM PDT 24
Peak memory 191960 kb
Host smart-56cfb5d8-3fa4-4292-875a-1925c32ec202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559642465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1559642465
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3712319810
Short name T181
Test name
Test status
Simulation time 552496244 ps
CPU time 1.28 seconds
Started Aug 18 04:27:10 PM PDT 24
Finished Aug 18 04:27:11 PM PDT 24
Peak memory 196704 kb
Host smart-31ae9f75-1eba-4542-a52e-f8270b1d5773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712319810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3712319810
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3312620620
Short name T206
Test name
Test status
Simulation time 38681964718 ps
CPU time 13.33 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 196992 kb
Host smart-f89b7a60-2aae-4900-8d59-b7c55ba346b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312620620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3312620620
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1059676198
Short name T275
Test name
Test status
Simulation time 393136287 ps
CPU time 0.75 seconds
Started Aug 18 04:27:09 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 192028 kb
Host smart-95cf9e7a-9259-470d-8492-05ad6d944024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059676198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1059676198
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3637982593
Short name T204
Test name
Test status
Simulation time 3774762779 ps
CPU time 12.65 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:27 PM PDT 24
Peak memory 198592 kb
Host smart-ff9f03a3-af99-4380-b12e-4fbf8231d984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637982593 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3637982593
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1165188988
Short name T246
Test name
Test status
Simulation time 8488468681 ps
CPU time 1.34 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 192020 kb
Host smart-3439448c-a7be-432b-9f53-2f1099405eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165188988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1165188988
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2864013281
Short name T209
Test name
Test status
Simulation time 486572294 ps
CPU time 0.94 seconds
Started Aug 18 04:27:19 PM PDT 24
Finished Aug 18 04:27:20 PM PDT 24
Peak memory 196752 kb
Host smart-2c80cca1-f43c-4166-b418-615f7771aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864013281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2864013281
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3164900203
Short name T274
Test name
Test status
Simulation time 3065049871 ps
CPU time 20.75 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:26 PM PDT 24
Peak memory 206824 kb
Host smart-35b5b032-acd2-4807-a9a3-8f037634dcac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164900203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3164900203
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2982936981
Short name T257
Test name
Test status
Simulation time 52605577586 ps
CPU time 21.16 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:27:38 PM PDT 24
Peak memory 192028 kb
Host smart-abc71b4a-f627-4cd7-a4bb-95b3c4fca2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982936981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2982936981
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1334330705
Short name T223
Test name
Test status
Simulation time 521291259 ps
CPU time 0.74 seconds
Started Aug 18 04:27:24 PM PDT 24
Finished Aug 18 04:27:25 PM PDT 24
Peak memory 196772 kb
Host smart-c8ee23fa-7755-493d-a66e-0d80ec36dbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334330705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1334330705
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2516462765
Short name T264
Test name
Test status
Simulation time 21594459447 ps
CPU time 14.12 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:21 PM PDT 24
Peak memory 192004 kb
Host smart-8e814245-708f-42dc-aaf7-a7bc3a9cd358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516462765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2516462765
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.946854212
Short name T237
Test name
Test status
Simulation time 418739967 ps
CPU time 1.11 seconds
Started Aug 18 04:27:16 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 191956 kb
Host smart-e6281125-a278-4576-810e-5502ffa3677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946854212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.946854212
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2253207277
Short name T203
Test name
Test status
Simulation time 24045216750 ps
CPU time 10.02 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 192004 kb
Host smart-c727a091-fd67-4147-b206-88f7d1ab1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253207277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2253207277
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.322182430
Short name T261
Test name
Test status
Simulation time 493684118 ps
CPU time 0.79 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:07 PM PDT 24
Peak memory 191908 kb
Host smart-50caf3cd-e885-4bdb-902d-6bd14f5a8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322182430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.322182430
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2195013015
Short name T230
Test name
Test status
Simulation time 26847306948 ps
CPU time 14.46 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:54 PM PDT 24
Peak memory 192012 kb
Host smart-d1047748-1d1c-4df1-ae4a-19b5080fb97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195013015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2195013015
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.287130753
Short name T20
Test name
Test status
Simulation time 7871753137 ps
CPU time 3.64 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 216088 kb
Host smart-0e447cb9-5460-4b6a-b679-30d5d2f016ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287130753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.287130753
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.155076231
Short name T283
Test name
Test status
Simulation time 594203067 ps
CPU time 1.29 seconds
Started Aug 18 04:26:36 PM PDT 24
Finished Aug 18 04:26:37 PM PDT 24
Peak memory 196772 kb
Host smart-671bf5a5-5116-48dc-b611-7f73a94e106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155076231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.155076231
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.622284552
Short name T49
Test name
Test status
Simulation time 1994407961 ps
CPU time 12.32 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:50 PM PDT 24
Peak memory 214380 kb
Host smart-2221bd94-5c0d-4788-843e-214fa1a551aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622284552 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.622284552
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2668177898
Short name T262
Test name
Test status
Simulation time 38888596734 ps
CPU time 19.91 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 192000 kb
Host smart-ab0fe7a6-0db7-40e0-a78a-7db743d9647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668177898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2668177898
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3798837123
Short name T31
Test name
Test status
Simulation time 484897207 ps
CPU time 0.7 seconds
Started Aug 18 04:27:17 PM PDT 24
Finished Aug 18 04:27:18 PM PDT 24
Peak memory 191904 kb
Host smart-40a06b7b-702a-4544-9f26-151df740f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798837123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3798837123
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1052519374
Short name T12
Test name
Test status
Simulation time 3977462683 ps
CPU time 11.11 seconds
Started Aug 18 04:27:22 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 206832 kb
Host smart-74e14899-2fae-4bc4-9cc8-b39573171cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052519374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1052519374
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2525896019
Short name T30
Test name
Test status
Simulation time 21935070917 ps
CPU time 8.98 seconds
Started Aug 18 04:27:07 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 192004 kb
Host smart-4eef7116-dd42-401c-a86c-4ed85312bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525896019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2525896019
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3456571594
Short name T27
Test name
Test status
Simulation time 426783168 ps
CPU time 0.72 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:26:57 PM PDT 24
Peak memory 191932 kb
Host smart-1c890438-825e-4184-879b-8e3f3f599ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456571594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3456571594
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1442437655
Short name T46
Test name
Test status
Simulation time 987597380 ps
CPU time 3.59 seconds
Started Aug 18 04:27:06 PM PDT 24
Finished Aug 18 04:27:10 PM PDT 24
Peak memory 214196 kb
Host smart-e927c3e1-8963-4af7-baf6-399d15e0a039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442437655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1442437655
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3161688860
Short name T273
Test name
Test status
Simulation time 16223078270 ps
CPU time 10.71 seconds
Started Aug 18 04:27:11 PM PDT 24
Finished Aug 18 04:27:22 PM PDT 24
Peak memory 192004 kb
Host smart-3bd36746-973e-47fd-95c2-ae1fb071d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161688860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3161688860
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3266904313
Short name T247
Test name
Test status
Simulation time 398154014 ps
CPU time 1.19 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:00 PM PDT 24
Peak memory 191936 kb
Host smart-5e3cba0f-16c6-4aba-b234-a852319741ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266904313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3266904313
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4131795527
Short name T281
Test name
Test status
Simulation time 8984981637 ps
CPU time 12.43 seconds
Started Aug 18 04:27:03 PM PDT 24
Finished Aug 18 04:27:16 PM PDT 24
Peak memory 196996 kb
Host smart-54cf19e1-00e9-4f63-993e-d51d3840590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131795527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4131795527
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4024452899
Short name T239
Test name
Test status
Simulation time 462308154 ps
CPU time 0.77 seconds
Started Aug 18 04:27:01 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 191936 kb
Host smart-57808179-3043-4443-af65-a5fd2d067e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024452899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4024452899
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3161185184
Short name T240
Test name
Test status
Simulation time 26643466112 ps
CPU time 18.34 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:33 PM PDT 24
Peak memory 191912 kb
Host smart-e946b484-3335-43a7-963c-1e534f7bece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161185184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3161185184
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.967325020
Short name T218
Test name
Test status
Simulation time 389618077 ps
CPU time 0.67 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 191908 kb
Host smart-d24dc4c3-478c-457e-a6f6-c5b9e3a2e2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967325020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.967325020
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2206475497
Short name T254
Test name
Test status
Simulation time 981407625 ps
CPU time 0.87 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:14 PM PDT 24
Peak memory 191940 kb
Host smart-6c702abc-c0d4-40ef-afbd-50b717198474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206475497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2206475497
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3238886547
Short name T252
Test name
Test status
Simulation time 602294590 ps
CPU time 0.74 seconds
Started Aug 18 04:27:02 PM PDT 24
Finished Aug 18 04:27:02 PM PDT 24
Peak memory 191960 kb
Host smart-3d92a0e3-bbec-44c7-b419-475e553ba1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238886547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3238886547
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2259164231
Short name T2
Test name
Test status
Simulation time 25172699024 ps
CPU time 3.34 seconds
Started Aug 18 04:27:13 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 192008 kb
Host smart-c34d7880-e34a-4f07-b435-d505945d8481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259164231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2259164231
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2963423555
Short name T233
Test name
Test status
Simulation time 432321949 ps
CPU time 0.83 seconds
Started Aug 18 04:27:08 PM PDT 24
Finished Aug 18 04:27:09 PM PDT 24
Peak memory 191936 kb
Host smart-e00d6e7c-cc98-403b-abf0-609554d6f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963423555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2963423555
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2632080066
Short name T90
Test name
Test status
Simulation time 29043956608 ps
CPU time 16.97 seconds
Started Aug 18 04:27:27 PM PDT 24
Finished Aug 18 04:27:44 PM PDT 24
Peak memory 192008 kb
Host smart-8e70fcf5-1559-4d67-894b-c463eccc8ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632080066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2632080066
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3680675754
Short name T235
Test name
Test status
Simulation time 563352258 ps
CPU time 1.05 seconds
Started Aug 18 04:27:21 PM PDT 24
Finished Aug 18 04:27:23 PM PDT 24
Peak memory 191932 kb
Host smart-863ec650-7953-477d-addb-07dece3b387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680675754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3680675754
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4011431332
Short name T55
Test name
Test status
Simulation time 30254785104 ps
CPU time 12.32 seconds
Started Aug 18 04:27:14 PM PDT 24
Finished Aug 18 04:27:26 PM PDT 24
Peak memory 197004 kb
Host smart-02158ea4-329d-4bce-b636-cf73b17cb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011431332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4011431332
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1633296315
Short name T241
Test name
Test status
Simulation time 533683306 ps
CPU time 1.41 seconds
Started Aug 18 04:27:15 PM PDT 24
Finished Aug 18 04:27:17 PM PDT 24
Peak memory 196704 kb
Host smart-7ded8b39-4c96-410f-a2fc-83e50fc4ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633296315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1633296315
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2239252634
Short name T3
Test name
Test status
Simulation time 9391297858 ps
CPU time 12.75 seconds
Started Aug 18 04:27:23 PM PDT 24
Finished Aug 18 04:27:36 PM PDT 24
Peak memory 191972 kb
Host smart-5f010a50-8aef-46e3-a679-bc2bd4690779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239252634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2239252634
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3658962162
Short name T269
Test name
Test status
Simulation time 21007217365 ps
CPU time 8.19 seconds
Started Aug 18 04:26:55 PM PDT 24
Finished Aug 18 04:27:04 PM PDT 24
Peak memory 197000 kb
Host smart-68dd4db0-c2f0-4c91-84a3-93b79410885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658962162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3658962162
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.947342938
Short name T227
Test name
Test status
Simulation time 452449499 ps
CPU time 0.7 seconds
Started Aug 18 04:26:52 PM PDT 24
Finished Aug 18 04:26:53 PM PDT 24
Peak memory 196700 kb
Host smart-6ca232ab-e40e-43de-b54a-f2d49ac30bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947342938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.947342938
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3948227535
Short name T212
Test name
Test status
Simulation time 50886521771 ps
CPU time 68.08 seconds
Started Aug 18 04:26:56 PM PDT 24
Finished Aug 18 04:28:04 PM PDT 24
Peak memory 191976 kb
Host smart-b223b2a2-7e42-4a76-a43a-b7c068c4bc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948227535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3948227535
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4084289499
Short name T263
Test name
Test status
Simulation time 587307535 ps
CPU time 0.77 seconds
Started Aug 18 04:26:38 PM PDT 24
Finished Aug 18 04:26:39 PM PDT 24
Peak memory 191932 kb
Host smart-5c87c5af-4b89-45af-99be-d3c2053c645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084289499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4084289499
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3533540548
Short name T249
Test name
Test status
Simulation time 10550606462 ps
CPU time 3.29 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:42 PM PDT 24
Peak memory 192324 kb
Host smart-d0c410c5-3c73-4036-bf41-ba003387e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533540548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3533540548
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.4283974463
Short name T225
Test name
Test status
Simulation time 599216933 ps
CPU time 0.72 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:40 PM PDT 24
Peak memory 196632 kb
Host smart-751c4c12-4dd5-418d-a1b3-56935aca257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283974463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4283974463
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1618335089
Short name T174
Test name
Test status
Simulation time 509667105 ps
CPU time 1.38 seconds
Started Aug 18 04:26:43 PM PDT 24
Finished Aug 18 04:26:44 PM PDT 24
Peak memory 196800 kb
Host smart-d16cb0af-0d55-43ea-a528-76125283f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618335089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1618335089
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.904256586
Short name T229
Test name
Test status
Simulation time 14010180380 ps
CPU time 2.03 seconds
Started Aug 18 04:26:59 PM PDT 24
Finished Aug 18 04:27:01 PM PDT 24
Peak memory 196984 kb
Host smart-52ad83e5-ae48-44b3-8521-081b7e4b7995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904256586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.904256586
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.258085403
Short name T268
Test name
Test status
Simulation time 491576354 ps
CPU time 0.85 seconds
Started Aug 18 04:26:28 PM PDT 24
Finished Aug 18 04:26:29 PM PDT 24
Peak memory 196728 kb
Host smart-2426f2c4-9a67-4d22-88d8-583ec976a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258085403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.258085403
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4131637673
Short name T276
Test name
Test status
Simulation time 28361132450 ps
CPU time 9.58 seconds
Started Aug 18 04:26:39 PM PDT 24
Finished Aug 18 04:26:49 PM PDT 24
Peak memory 191988 kb
Host smart-9e1d30b9-b4e8-4ec6-93c9-e22ea3068e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131637673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4131637673
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2249060488
Short name T278
Test name
Test status
Simulation time 509137550 ps
CPU time 0.74 seconds
Started Aug 18 04:26:37 PM PDT 24
Finished Aug 18 04:26:38 PM PDT 24
Peak memory 196780 kb
Host smart-6e3894da-57e4-432a-84e5-fd443157cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249060488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2249060488
Directory /workspace/9.aon_timer_smoke/latest
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