Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18078	1			T1	12		T2	12		T3	191
bark[1]	773	1			T6	47		T10	14		T16	14
bark[2]	296	1			T17	14		T101	21		T40	26
bark[3]	131	1			T11	14		T19	7		T182	14
bark[4]	341	1			T14	14		T92	21		T66	26
bark[5]	185	1			T29	14		T101	30		T70	40
bark[6]	457	1			T101	21		T43	35		T174	71
bark[7]	684	1			T135	26		T40	155		T42	21
bark[8]	335	1			T17	21		T92	21		T40	47
bark[9]	127	1			T160	47		T93	38		T129	21
bark[10]	434	1			T6	68		T87	49		T116	57
bark[11]	346	1			T3	21		T9	21		T30	14
bark[12]	136	1			T156	14		T144	57		T82	30
bark[13]	311	1			T6	21		T14	5		T101	21
bark[14]	243	1			T70	21		T103	14		T118	35
bark[15]	481	1			T14	21		T19	21		T135	26
bark[16]	184	1			T92	21		T106	21		T132	14
bark[17]	219	1			T89	21		T143	14		T97	72
bark[18]	564	1			T17	21		T28	214		T39	43
bark[19]	333	1			T6	38		T19	82		T86	14
bark[20]	392	1			T105	26		T167	14		T109	26
bark[21]	193	1			T13	21		T160	26		T76	21
bark[22]	353	1			T27	26		T42	164		T139	36
bark[23]	285	1			T14	21		T27	45		T92	64
bark[24]	426	1			T6	26		T13	26		T14	7
bark[25]	364	1			T14	5		T19	114		T40	26
bark[26]	386	1			T6	26		T89	124		T174	93
bark[27]	161	1			T25	14		T92	65		T177	49
bark[28]	406	1			T3	91		T4	14		T66	7
bark[29]	406	1			T18	153		T27	21		T19	21
bark[30]	308	1			T159	14		T176	14		T67	47
bark[31]	56	1			T14	21		T31	14		T135	21
bark_0	4445	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17509	1			T1	11		T2	11		T3	190
bite[1]	298	1			T10	13		T27	21		T87	49
bite[2]	331	1			T6	26		T27	26		T92	21
bite[3]	225	1			T67	26		T70	46		T105	21
bite[4]	58	1			T43	6		T105	26		T154	13
bite[5]	223	1			T67	40		T174	18		T79	21
bite[6]	483	1			T6	21		T25	13		T19	81
bite[7]	136	1			T30	13		T92	36		T101	21
bite[8]	446	1			T14	4		T18	152		T65	13
bite[9]	315	1			T66	6		T76	21		T174	71
bite[10]	132	1			T16	13		T86	13		T92	21
bite[11]	548	1			T3	91		T18	21		T19	113
bite[12]	482	1			T6	46		T29	13		T159	13
bite[13]	264	1			T17	21		T116	30		T139	36
bite[14]	163	1			T4	13		T6	21		T135	21
bite[15]	316	1			T40	25		T67	21		T70	71
bite[16]	378	1			T17	21		T40	154		T97	47
bite[17]	290	1			T19	6		T92	21		T42	163
bite[18]	255	1			T89	21		T146	21		T121	21
bite[19]	436	1			T11	13		T135	26		T41	21
bite[20]	135	1			T3	21		T13	26		T19	21
bite[21]	328	1			T14	21		T39	42		T101	21
bite[22]	339	1			T14	13		T19	21		T32	13
bite[23]	480	1			T66	304		T70	21		T167	13
bite[24]	774	1			T6	26		T13	21		T28	213
bite[25]	398	1			T14	6		T101	21		T67	47
bite[26]	585	1			T14	46		T31	13		T135	26
bite[27]	652	1			T6	38		T17	13		T27	45
bite[28]	173	1			T161	13		T105	21		T139	30
bite[29]	207	1			T9	21		T181	44		T106	21
bite[30]	177	1			T6	21		T106	38		T155	42
bite[31]	383	1			T87	21		T89	123		T160	26
bite_0	4920	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29554

1

T1

19

T2

19

T3

310

auto[1]

3285

1

T13

50

T17

66

T27

74

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	534	1			T28	2		T87	91		T40	2
prescale[1]	254	1			T13	38		T17	23		T38	60
prescale[2]	324	1			T7	9		T18	36		T19	2
prescale[3]	225	1			T40	2		T143	28		T42	36
prescale[4]	473	1			T9	19		T13	33		T17	19
prescale[5]	417	1			T38	2		T39	2		T40	2
prescale[6]	557	1			T9	28		T44	9		T70	166
prescale[7]	296	1			T3	53		T189	9		T67	19
prescale[8]	389	1			T9	36		T14	26		T190	9
prescale[9]	374	1			T6	128		T13	19		T73	19
prescale[10]	242	1			T14	21		T191	9		T41	2
prescale[11]	373	1			T135	23		T40	2		T42	19
prescale[12]	250	1			T17	19		T92	44		T78	4
prescale[13]	178	1			T13	19		T18	2		T27	36
prescale[14]	466	1			T2	9		T135	57		T87	39
prescale[15]	483	1			T9	19		T17	28		T87	19
prescale[16]	390	1			T3	88		T105	45		T139	40
prescale[17]	405	1			T9	9		T19	2		T39	4
prescale[18]	333	1			T13	19		T18	2		T28	2
prescale[19]	300	1			T3	53		T9	19		T19	2
prescale[20]	258	1			T3	38		T14	2		T17	33
prescale[21]	299	1			T97	33		T119	30		T79	89
prescale[22]	357	1			T9	19		T135	19		T77	25
prescale[23]	462	1			T9	37		T18	2		T19	55
prescale[24]	176	1			T77	2		T178	57		T96	30
prescale[25]	284	1			T39	2		T40	2		T143	23
prescale[26]	288	1			T13	9		T19	9		T40	2
prescale[27]	272	1			T14	26		T84	9		T101	19
prescale[28]	240	1			T1	9		T13	19		T90	9
prescale[29]	239	1			T87	23		T92	23		T116	19
prescale[30]	502	1			T17	19		T27	28		T39	19
prescale[31]	341	1			T8	9		T9	19		T89	56
prescale_0	21858	1			T1	10		T2	10		T3	78

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21491

1

T1

9

T2

19

T3

189

auto[1]

11348

1

T1

10

T3

121

T5

9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

32839

1

T1

19

T2

19

T3

310

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	18246	1			T1	14		T2	14		T3	263
wkup[1]	149	1			T14	26		T159	15		T147	15
wkup[2]	42	1			T14	21		T134	21		-	-
wkup[3]	175	1			T14	21		T41	21		T66	21
wkup[4]	272	1			T6	26		T14	15		T18	21
wkup[5]	157	1			T40	21		T160	26		T95	21
wkup[6]	204	1			T3	21		T17	15		T87	26
wkup[7]	261	1			T14	21		T18	21		T19	35
wkup[8]	206	1			T18	30		T19	21		T92	21
wkup[9]	250	1			T6	26		T38	30		T135	21
wkup[10]	119	1			T116	21		T185	15		T122	26
wkup[11]	169	1			T18	21		T101	21		T73	26
wkup[12]	144	1			T11	15		T139	21		T112	21
wkup[13]	182	1			T16	15		T25	15		T119	21
wkup[14]	153	1			T117	21		T122	21		T129	21
wkup[15]	283	1			T19	51		T143	15		T70	21
wkup[16]	249	1			T101	21		T43	8		T119	21
wkup[17]	187	1			T14	21		T177	21		T170	15
wkup[18]	63	1			T174	21		T95	21		T145	21
wkup[19]	71	1			T19	8		T79	21		T117	21
wkup[20]	134	1			T3	21		T182	15		T97	21
wkup[21]	177	1			T28	42		T143	21		T79	21
wkup[22]	161	1			T14	21		T101	21		T106	21
wkup[23]	230	1			T18	21		T135	26		T87	21
wkup[24]	202	1			T28	21		T40	26		T42	21
wkup[25]	239	1			T6	26		T18	21		T135	21
wkup[26]	214	1			T87	21		T92	21		T139	21
wkup[27]	65	1			T14	15		T111	15		T134	35
wkup[28]	223	1			T92	21		T40	21		T70	35
wkup[29]	293	1			T6	21		T27	21		T19	36
wkup[30]	134	1			T4	15		T27	21		T32	15
wkup[31]	177	1			T6	21		T92	21		T79	21
wkup[32]	183	1			T41	21		T160	21		T109	21
wkup[33]	158	1			T31	15		T28	26		T176	15
wkup[34]	149	1			T160	21		T168	15		T139	36
wkup[35]	229	1			T87	47		T41	21		T66	26
wkup[36]	189	1			T40	21		T43	30		T65	15
wkup[37]	115	1			T86	15		T100	15		T70	35
wkup[38]	197	1			T39	21		T87	21		T40	21
wkup[39]	269	1			T13	47		T135	26		T116	35
wkup[40]	126	1			T6	21		T28	26		T118	35
wkup[41]	191	1			T9	21		T29	15		T87	24
wkup[42]	251	1			T18	21		T27	21		T174	35
wkup[43]	214	1			T92	36		T116	21		T66	21
wkup[44]	89	1			T18	21		T67	21		T104	26
wkup[45]	167	1			T19	21		T70	21		T119	21
wkup[46]	201	1			T6	21		T14	6		T66	15
wkup[47]	161	1			T18	21		T101	21		T43	13
wkup[48]	172	1			T18	21		T19	21		T41	21
wkup[49]	227	1			T17	21		T40	42		T67	21
wkup[50]	183	1			T40	42		T105	21		T119	21
wkup[51]	57	1			T10	15		T105	21		T77	21
wkup[52]	73	1			T14	6		T101	26		T172	15
wkup[53]	241	1			T40	21		T97	42		T95	30
wkup[54]	275	1			T89	42		T40	30		T105	21
wkup[55]	262	1			T89	21		T42	15		T70	21
wkup[56]	187	1			T40	21		T42	35		T66	21
wkup[57]	153	1			T17	21		T92	24		T95	51
wkup[58]	107	1			T92	21		T112	21		T96	15
wkup[59]	42	1			T14	6		T103	36		-	-
wkup[60]	255	1			T14	21		T38	15		T92	21
wkup[61]	149	1			T78	21		T156	15		T129	8
wkup[62]	122	1			T6	21		T27	26		T40	8
wkup[63]	132	1			T14	8		T18	21		T101	26
wkup_0	3482	1			T1	5		T2	5		T3	5