Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.72 99.33 95.61 100.00 98.40 99.51 45.48


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T278 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.522367438 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:23 PM PDT 24 443074641 ps
T279 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3627335935 Aug 19 04:26:36 PM PDT 24 Aug 19 04:26:37 PM PDT 24 341456779 ps
T37 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.462080517 Aug 19 04:26:03 PM PDT 24 Aug 19 04:26:04 PM PDT 24 507043378 ps
T280 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.121116627 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:16 PM PDT 24 345424848 ps
T34 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.198950691 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:29 PM PDT 24 8543590215 ps
T35 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1366327819 Aug 19 04:26:36 PM PDT 24 Aug 19 04:26:36 PM PDT 24 1458394412 ps
T281 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1553635650 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 460299670 ps
T36 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.855732768 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:27 PM PDT 24 8128510763 ps
T282 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2500048082 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:15 PM PDT 24 364769481 ps
T283 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.314897045 Aug 19 04:26:07 PM PDT 24 Aug 19 04:26:08 PM PDT 24 522989441 ps
T284 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4183566875 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:15 PM PDT 24 350626694 ps
T45 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3492768665 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:11 PM PDT 24 518369489 ps
T285 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.475989838 Aug 19 04:26:04 PM PDT 24 Aug 19 04:26:06 PM PDT 24 451157390 ps
T286 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3250998677 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:19 PM PDT 24 499263578 ps
T188 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2527915728 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:18 PM PDT 24 8545140078 ps
T287 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1842077015 Aug 19 04:26:26 PM PDT 24 Aug 19 04:26:27 PM PDT 24 437775267 ps
T288 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3906783261 Aug 19 04:26:16 PM PDT 24 Aug 19 04:26:17 PM PDT 24 360111790 ps
T289 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3854778293 Aug 19 04:26:29 PM PDT 24 Aug 19 04:26:36 PM PDT 24 4298610858 ps
T290 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2527522931 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:24 PM PDT 24 279199577 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2332034003 Aug 19 04:26:24 PM PDT 24 Aug 19 04:26:27 PM PDT 24 459847509 ps
T74 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3631597976 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:11 PM PDT 24 508222434 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.980584942 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 497790885 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4072337105 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:18 PM PDT 24 327708223 ps
T294 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1478576829 Aug 19 04:26:02 PM PDT 24 Aug 19 04:26:04 PM PDT 24 409864598 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3641033710 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 369271118 ps
T296 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1650208996 Aug 19 04:26:27 PM PDT 24 Aug 19 04:26:27 PM PDT 24 335214650 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2385469164 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:20 PM PDT 24 418328949 ps
T298 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2499797750 Aug 19 04:26:22 PM PDT 24 Aug 19 04:26:28 PM PDT 24 364403730 ps
T46 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3176753329 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:14 PM PDT 24 468609417 ps
T299 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1114854728 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:24 PM PDT 24 446376447 ps
T300 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.548607503 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:21 PM PDT 24 540586424 ps
T301 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3720497602 Aug 19 04:26:38 PM PDT 24 Aug 19 04:26:39 PM PDT 24 359640981 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2790276200 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:16 PM PDT 24 397750016 ps
T59 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1273003419 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 1459445908 ps
T302 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3134711699 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:23 PM PDT 24 537709530 ps
T303 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1977904710 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:33 PM PDT 24 8342000592 ps
T304 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1461290946 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:14 PM PDT 24 376159464 ps
T305 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4233400001 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 506422327 ps
T47 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2329011981 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 448463022 ps
T306 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3699697724 Aug 19 04:26:07 PM PDT 24 Aug 19 04:26:08 PM PDT 24 306578668 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2239897117 Aug 19 04:26:08 PM PDT 24 Aug 19 04:26:09 PM PDT 24 801353091 ps
T308 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.808185725 Aug 19 04:26:25 PM PDT 24 Aug 19 04:26:27 PM PDT 24 429588424 ps
T309 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1447011125 Aug 19 04:26:09 PM PDT 24 Aug 19 04:26:10 PM PDT 24 503480975 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3972478319 Aug 19 04:26:35 PM PDT 24 Aug 19 04:26:36 PM PDT 24 402373028 ps
T310 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2682509205 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:24 PM PDT 24 391393046 ps
T61 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3122085276 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:12 PM PDT 24 941067665 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1262262682 Aug 19 04:26:16 PM PDT 24 Aug 19 04:26:17 PM PDT 24 1617736307 ps
T311 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3637740237 Aug 19 04:26:11 PM PDT 24 Aug 19 04:26:18 PM PDT 24 4229123327 ps
T312 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.513206213 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:25 PM PDT 24 509740770 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.746019510 Aug 19 04:26:16 PM PDT 24 Aug 19 04:26:16 PM PDT 24 569458175 ps
T314 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.256368154 Aug 19 04:26:16 PM PDT 24 Aug 19 04:26:17 PM PDT 24 470310003 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1886058838 Aug 19 04:26:06 PM PDT 24 Aug 19 04:26:06 PM PDT 24 343908857 ps
T316 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4004552412 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:22 PM PDT 24 4229976438 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2492643979 Aug 19 04:26:07 PM PDT 24 Aug 19 04:26:10 PM PDT 24 455608549 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2146594903 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:15 PM PDT 24 498833718 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.328212797 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 508884580 ps
T48 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3046261659 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:24 PM PDT 24 9675215424 ps
T320 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2676590577 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 468759772 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3663084452 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:22 PM PDT 24 4902631150 ps
T322 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3790769931 Aug 19 04:26:24 PM PDT 24 Aug 19 04:26:25 PM PDT 24 318733007 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2716678474 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:21 PM PDT 24 345813947 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2353498192 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 352039780 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.232400941 Aug 19 04:25:56 PM PDT 24 Aug 19 04:25:57 PM PDT 24 1356949256 ps
T64 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.143072347 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:25 PM PDT 24 2393673614 ps
T325 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1338598669 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:19 PM PDT 24 411584297 ps
T326 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2901774317 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:30 PM PDT 24 318125737 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1961297754 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 460039386 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.387924335 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:23 PM PDT 24 871542753 ps
T329 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1267647454 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:19 PM PDT 24 561967740 ps
T49 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.95329348 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 396315781 ps
T330 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3478802365 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 271772913 ps
T331 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.223855355 Aug 19 04:26:27 PM PDT 24 Aug 19 04:26:28 PM PDT 24 321792300 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2045521718 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:25 PM PDT 24 2570908508 ps
T50 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3235942349 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:10 PM PDT 24 406063877 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2457048523 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 4216420084 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4024773233 Aug 19 04:26:25 PM PDT 24 Aug 19 04:26:26 PM PDT 24 1002903800 ps
T334 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2594068812 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:22 PM PDT 24 7843509877 ps
T335 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3588807561 Aug 19 04:26:03 PM PDT 24 Aug 19 04:26:06 PM PDT 24 383518263 ps
T336 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2901181730 Aug 19 04:26:36 PM PDT 24 Aug 19 04:26:38 PM PDT 24 621502622 ps
T337 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.508088372 Aug 19 04:26:42 PM PDT 24 Aug 19 04:26:43 PM PDT 24 550721709 ps
T338 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.106407997 Aug 19 04:26:44 PM PDT 24 Aug 19 04:26:47 PM PDT 24 2113977155 ps
T52 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3793072241 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 631570125 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4025735580 Aug 19 04:26:08 PM PDT 24 Aug 19 04:26:09 PM PDT 24 461289867 ps
T340 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3346281802 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:24 PM PDT 24 4146406144 ps
T341 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.391516104 Aug 19 04:26:25 PM PDT 24 Aug 19 04:26:26 PM PDT 24 436075053 ps
T342 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.269509228 Aug 19 04:26:03 PM PDT 24 Aug 19 04:26:06 PM PDT 24 571257386 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3117053135 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:16 PM PDT 24 527598680 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2322948204 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:15 PM PDT 24 447634639 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.89365309 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:27 PM PDT 24 4610068178 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.950703507 Aug 19 04:26:33 PM PDT 24 Aug 19 04:26:37 PM PDT 24 2161512569 ps
T347 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4202191279 Aug 19 04:26:52 PM PDT 24 Aug 19 04:26:53 PM PDT 24 443038766 ps
T348 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.890654151 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:18 PM PDT 24 365180096 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1298071631 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:22 PM PDT 24 1151827401 ps
T350 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.289955245 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:22 PM PDT 24 9026683230 ps
T351 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1609265493 Aug 19 04:26:25 PM PDT 24 Aug 19 04:26:31 PM PDT 24 431976932 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4090354466 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:23 PM PDT 24 14354582143 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1767227567 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 314053034 ps
T353 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2931978586 Aug 19 04:26:04 PM PDT 24 Aug 19 04:26:07 PM PDT 24 510398758 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1059121914 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:23 PM PDT 24 321360926 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2012682784 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:16 PM PDT 24 1228959476 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3515446531 Aug 19 04:26:01 PM PDT 24 Aug 19 04:26:01 PM PDT 24 370759421 ps
T357 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1747880721 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 423736475 ps
T358 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.115553078 Aug 19 04:26:09 PM PDT 24 Aug 19 04:26:11 PM PDT 24 644817997 ps
T359 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.890041914 Aug 19 04:26:37 PM PDT 24 Aug 19 04:26:38 PM PDT 24 483315504 ps
T360 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3358509727 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:12 PM PDT 24 435126823 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2638217239 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:27 PM PDT 24 4193329195 ps
T362 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4276700027 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:20 PM PDT 24 7441441136 ps
T363 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1897356886 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:21 PM PDT 24 482698813 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1236597960 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 427319123 ps
T365 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3206039924 Aug 19 04:26:52 PM PDT 24 Aug 19 04:26:53 PM PDT 24 333855041 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2800116448 Aug 19 04:26:00 PM PDT 24 Aug 19 04:26:01 PM PDT 24 471938408 ps
T367 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2143578070 Aug 19 04:26:29 PM PDT 24 Aug 19 04:26:30 PM PDT 24 306974689 ps
T368 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3148999393 Aug 19 04:26:27 PM PDT 24 Aug 19 04:26:30 PM PDT 24 1377142847 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2917535281 Aug 19 04:26:15 PM PDT 24 Aug 19 04:26:16 PM PDT 24 483019396 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3170385106 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 558210416 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3696054029 Aug 19 04:26:02 PM PDT 24 Aug 19 04:26:05 PM PDT 24 1537120613 ps
T371 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2452693395 Aug 19 04:26:09 PM PDT 24 Aug 19 04:26:10 PM PDT 24 430683386 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1391160460 Aug 19 04:26:02 PM PDT 24 Aug 19 04:26:09 PM PDT 24 573296117 ps
T373 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3687358626 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:14 PM PDT 24 1519155659 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.990729585 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:18 PM PDT 24 485389130 ps
T374 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2605175470 Aug 19 04:26:22 PM PDT 24 Aug 19 04:26:23 PM PDT 24 275968664 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.560630916 Aug 19 04:26:01 PM PDT 24 Aug 19 04:26:05 PM PDT 24 7065117910 ps
T376 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4234418372 Aug 19 04:26:07 PM PDT 24 Aug 19 04:26:10 PM PDT 24 367094211 ps
T377 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4123790101 Aug 19 04:26:55 PM PDT 24 Aug 19 04:26:56 PM PDT 24 454138084 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3759049262 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 452485463 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2791928967 Aug 19 04:26:22 PM PDT 24 Aug 19 04:26:23 PM PDT 24 494821189 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3263611308 Aug 19 04:25:58 PM PDT 24 Aug 19 04:25:59 PM PDT 24 532810900 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1937279759 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:31 PM PDT 24 2333114150 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2453855381 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:19 PM PDT 24 380606863 ps
T382 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.438563994 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:21 PM PDT 24 395397555 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.269012889 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:26 PM PDT 24 4338407367 ps
T57 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1596281525 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:21 PM PDT 24 354095474 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2905830449 Aug 19 04:26:22 PM PDT 24 Aug 19 04:26:23 PM PDT 24 1311384518 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2445702844 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:20 PM PDT 24 455535141 ps
T386 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2107870263 Aug 19 04:26:30 PM PDT 24 Aug 19 04:26:30 PM PDT 24 282263897 ps
T387 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.368077715 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:24 PM PDT 24 453953095 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1426912826 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 269970364 ps
T389 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3459344684 Aug 19 04:26:28 PM PDT 24 Aug 19 04:26:29 PM PDT 24 306648086 ps
T390 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1354425951 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:15 PM PDT 24 549520830 ps
T391 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2946557133 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:17 PM PDT 24 496927476 ps
T392 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1466731548 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:14 PM PDT 24 1508342003 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.618592392 Aug 19 04:26:27 PM PDT 24 Aug 19 04:26:29 PM PDT 24 897424159 ps
T394 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.536511153 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:13 PM PDT 24 527986642 ps
T395 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1768067048 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:22 PM PDT 24 332899399 ps
T396 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.854072928 Aug 19 04:26:14 PM PDT 24 Aug 19 04:26:15 PM PDT 24 310219042 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3613256544 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 599309261 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.330479734 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:22 PM PDT 24 1459451415 ps
T399 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2638715148 Aug 19 04:26:23 PM PDT 24 Aug 19 04:26:23 PM PDT 24 519023176 ps
T400 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.459426373 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:27 PM PDT 24 4326475520 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1917870681 Aug 19 04:26:26 PM PDT 24 Aug 19 04:26:31 PM PDT 24 8783244341 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3399544421 Aug 19 04:26:09 PM PDT 24 Aug 19 04:26:10 PM PDT 24 513710826 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1767735948 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:19 PM PDT 24 725073862 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1763488157 Aug 19 04:26:16 PM PDT 24 Aug 19 04:26:17 PM PDT 24 288149945 ps
T405 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3119558685 Aug 19 04:26:48 PM PDT 24 Aug 19 04:26:48 PM PDT 24 351749885 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.408315207 Aug 19 04:26:21 PM PDT 24 Aug 19 04:26:23 PM PDT 24 441128114 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1856078990 Aug 19 04:26:22 PM PDT 24 Aug 19 04:26:24 PM PDT 24 1196868973 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3929179606 Aug 19 04:26:02 PM PDT 24 Aug 19 04:26:03 PM PDT 24 793249316 ps
T408 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3460566557 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:28 PM PDT 24 4371707667 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.574908407 Aug 19 04:26:20 PM PDT 24 Aug 19 04:26:21 PM PDT 24 1339382955 ps
T410 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4164366336 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:11 PM PDT 24 434248301 ps
T411 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3943331634 Aug 19 04:25:58 PM PDT 24 Aug 19 04:25:58 PM PDT 24 324307648 ps
T412 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1469861507 Aug 19 04:26:03 PM PDT 24 Aug 19 04:26:04 PM PDT 24 2620331340 ps
T413 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.123652480 Aug 19 04:26:13 PM PDT 24 Aug 19 04:26:15 PM PDT 24 511438153 ps
T414 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4232951664 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:23 PM PDT 24 1532821357 ps
T415 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3000882081 Aug 19 04:26:29 PM PDT 24 Aug 19 04:26:30 PM PDT 24 413442801 ps
T416 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3495809983 Aug 19 04:26:17 PM PDT 24 Aug 19 04:26:21 PM PDT 24 355054693 ps
T417 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3655749067 Aug 19 04:26:10 PM PDT 24 Aug 19 04:26:17 PM PDT 24 14076442731 ps
T418 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1255582778 Aug 19 04:26:19 PM PDT 24 Aug 19 04:26:20 PM PDT 24 454327335 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3299056099 Aug 19 04:26:09 PM PDT 24 Aug 19 04:26:10 PM PDT 24 2600770673 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2477880077 Aug 19 04:26:12 PM PDT 24 Aug 19 04:26:14 PM PDT 24 300433980 ps
T421 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4184468984 Aug 19 04:26:29 PM PDT 24 Aug 19 04:26:30 PM PDT 24 365068082 ps
T422 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2476171980 Aug 19 04:26:18 PM PDT 24 Aug 19 04:26:22 PM PDT 24 8502330636 ps
T423 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2706354257 Aug 19 04:26:05 PM PDT 24 Aug 19 04:26:11 PM PDT 24 417415768 ps

Test location /workspace/coverage/default/34.aon_timer_stress_all.3150119100
Short name T3
Test name
Test status
Simulation time 367592845634 ps
CPU time 544.89 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:37:13 PM PDT 24
Peak memory 198476 kb
Host smart-39426896-39f1-4aa9-917b-4eb5dd5452ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150119100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3150119100
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.828022520
Short name T19
Test name
Test status
Simulation time 2015886410 ps
CPU time 13.24 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 198648 kb
Host smart-714190da-172b-4cb5-9228-2215d724da74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828022520 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.828022520
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.855732768
Short name T36
Test name
Test status
Simulation time 8128510763 ps
CPU time 3.94 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 198088 kb
Host smart-96bf38b3-466c-4400-96d8-f06c20100ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855732768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.855732768
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.940273424
Short name T80
Test name
Test status
Simulation time 48727245661 ps
CPU time 26.75 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 214480 kb
Host smart-62282af5-94b0-40ee-a8dc-82525bbade51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940273424 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.940273424
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3492768665
Short name T45
Test name
Test status
Simulation time 518369489 ps
CPU time 0.75 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:11 PM PDT 24
Peak memory 193264 kb
Host smart-049eab04-fbbc-44fa-bbd7-3c62ee36ce54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492768665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3492768665
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.483264914
Short name T6
Test name
Test status
Simulation time 147222549968 ps
CPU time 90.86 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:29:24 PM PDT 24
Peak memory 193272 kb
Host smart-f5fbd1ee-6afb-4ea9-aac5-7fbe309ccf27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483264914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.483264914
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.95057102
Short name T95
Test name
Test status
Simulation time 5212296990 ps
CPU time 45.63 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 207016 kb
Host smart-e6a85e8c-7498-4008-9a91-815de92346be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95057102 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.95057102
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2178260122
Short name T105
Test name
Test status
Simulation time 235131676884 ps
CPU time 300.81 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:32:51 PM PDT 24
Peak memory 198716 kb
Host smart-d488a28b-2198-40d0-a8fd-17f2d60722d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178260122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2178260122
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.327613509
Short name T14
Test name
Test status
Simulation time 2750760521 ps
CPU time 15.86 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 206988 kb
Host smart-d8fd1a4b-2511-4e0e-afd3-5779d65f8229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327613509 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.327613509
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.89628013
Short name T92
Test name
Test status
Simulation time 11021445415 ps
CPU time 2.67 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 192728 kb
Host smart-ea336bc7-1966-48a0-8feb-906b20055951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89628013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.89628013
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2364529927
Short name T23
Test name
Test status
Simulation time 4486651145 ps
CPU time 7.51 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:47 PM PDT 24
Peak memory 216208 kb
Host smart-6884903c-65bb-40c4-899a-0334126743de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364529927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2364529927
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4264679703
Short name T40
Test name
Test status
Simulation time 10081877030 ps
CPU time 40.36 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 198700 kb
Host smart-3a2fb6fe-b1de-404f-914e-29c6e638c2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264679703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4264679703
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2556146629
Short name T131
Test name
Test status
Simulation time 113187639869 ps
CPU time 158.72 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 198684 kb
Host smart-0d351c0e-37e2-4833-9ded-d81fb50cfa70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556146629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2556146629
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2872588441
Short name T102
Test name
Test status
Simulation time 87076271520 ps
CPU time 29.21 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 198448 kb
Host smart-f1a28f76-55db-45fd-bb41-08366f290418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872588441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2872588441
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1538595044
Short name T18
Test name
Test status
Simulation time 35770179377 ps
CPU time 19.05 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 214704 kb
Host smart-09b91a66-7caf-4e60-a547-f94326a8730f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538595044 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1538595044
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3526128962
Short name T112
Test name
Test status
Simulation time 2730674744 ps
CPU time 15.82 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 199392 kb
Host smart-a95ccda3-f7e8-4eb4-a172-a89cb28557de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526128962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3526128962
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.632346257
Short name T101
Test name
Test status
Simulation time 192268195638 ps
CPU time 133.42 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 193172 kb
Host smart-252c0dba-7f23-4c64-a38a-0c6780130d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632346257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.632346257
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2947643701
Short name T99
Test name
Test status
Simulation time 104812272485 ps
CPU time 41.46 seconds
Started Aug 19 04:27:22 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 184460 kb
Host smart-9059c096-8ff3-484c-8523-b0797b9a1a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947643701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2947643701
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2770833133
Short name T138
Test name
Test status
Simulation time 8409861646 ps
CPU time 45.44 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 206984 kb
Host smart-7528a69e-ab08-4197-9782-57251098fb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770833133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2770833133
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1173143436
Short name T98
Test name
Test status
Simulation time 61807991879 ps
CPU time 44.49 seconds
Started Aug 19 04:27:28 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 192180 kb
Host smart-18ebdb82-721c-4979-8d33-22958925746d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173143436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1173143436
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3945263848
Short name T67
Test name
Test status
Simulation time 26292282134 ps
CPU time 39.33 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 192160 kb
Host smart-a144c6aa-7398-44df-856f-292adc4943df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945263848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3945263848
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3174016390
Short name T129
Test name
Test status
Simulation time 8479723222 ps
CPU time 15.66 seconds
Started Aug 19 04:27:41 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 198760 kb
Host smart-da887aa0-2aac-4289-8784-356bfdd37a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174016390 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3174016390
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4258068164
Short name T103
Test name
Test status
Simulation time 110117337110 ps
CPU time 148.75 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 198468 kb
Host smart-4f86983f-d910-4a1e-b149-2558492c51f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258068164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4258068164
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2871464962
Short name T122
Test name
Test status
Simulation time 107117495752 ps
CPU time 40.58 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:29:15 PM PDT 24
Peak memory 193132 kb
Host smart-364fc7a3-8589-4bb4-b517-911183741db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871464962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2871464962
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2963844284
Short name T107
Test name
Test status
Simulation time 98865392381 ps
CPU time 23.02 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 198536 kb
Host smart-a91e7a10-1bd2-4790-97ea-7f8a8871cbf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963844284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2963844284
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1074410119
Short name T70
Test name
Test status
Simulation time 16990672541 ps
CPU time 33.87 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 206956 kb
Host smart-684c760e-477a-4300-ba0e-44debbed6ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074410119 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1074410119
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1501732609
Short name T117
Test name
Test status
Simulation time 164139118595 ps
CPU time 127.41 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 198512 kb
Host smart-7c0a708b-90ee-480d-8099-b0260e932f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501732609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1501732609
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1408043888
Short name T115
Test name
Test status
Simulation time 67516287295 ps
CPU time 99.01 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:29:35 PM PDT 24
Peak memory 193208 kb
Host smart-bb83fe07-6289-438c-a6a5-ff769def99b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408043888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1408043888
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4086802989
Short name T145
Test name
Test status
Simulation time 41920955102 ps
CPU time 15.32 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 193188 kb
Host smart-098c2d24-2283-4050-87d2-042cdf915ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086802989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4086802989
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4239283785
Short name T132
Test name
Test status
Simulation time 4140572102 ps
CPU time 29.51 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 198800 kb
Host smart-c3b02ff2-caaf-41f2-aa0c-68b8a6e7f193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239283785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4239283785
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1854749200
Short name T93
Test name
Test status
Simulation time 106520899709 ps
CPU time 73.15 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 198416 kb
Host smart-528ed0d2-4c3e-408f-a478-6397e040c0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854749200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1854749200
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2173771577
Short name T27
Test name
Test status
Simulation time 219202956995 ps
CPU time 31.59 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 192184 kb
Host smart-fb69b0bf-fb06-4c1c-9a73-801b3d8c8654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173771577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2173771577
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1954199013
Short name T136
Test name
Test status
Simulation time 84669501187 ps
CPU time 66.63 seconds
Started Aug 19 04:27:41 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 192180 kb
Host smart-4d11e1d7-3d5c-4982-8927-e186d13851ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954199013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1954199013
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3365403012
Short name T82
Test name
Test status
Simulation time 3518267160 ps
CPU time 11.46 seconds
Started Aug 19 04:27:52 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 198820 kb
Host smart-49baf21c-bcc2-4b9f-8337-3e859b3d2237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365403012 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3365403012
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1161674300
Short name T111
Test name
Test status
Simulation time 10726003755 ps
CPU time 42.54 seconds
Started Aug 19 04:27:59 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 214632 kb
Host smart-95a2b902-4d5a-443a-8980-723654f3caab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161674300 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1161674300
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1395770480
Short name T32
Test name
Test status
Simulation time 373046374 ps
CPU time 1.16 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:41 PM PDT 24
Peak memory 196916 kb
Host smart-a8826a7e-0e85-40e9-89c5-09dd1ae92337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395770480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1395770480
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.859781515
Short name T139
Test name
Test status
Simulation time 2388536228 ps
CPU time 9.43 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 198728 kb
Host smart-9b7ce0f7-1ecd-41bb-ba3d-faf23a29b95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859781515 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.859781515
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3014308412
Short name T121
Test name
Test status
Simulation time 4268805143 ps
CPU time 37.53 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:46 PM PDT 24
Peak memory 214276 kb
Host smart-9e0cc435-3c95-47a3-8d5e-189bd8132e89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014308412 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3014308412
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1285749029
Short name T87
Test name
Test status
Simulation time 163031938848 ps
CPU time 67.06 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 193196 kb
Host smart-bd083a9a-72a6-4bb1-b826-40c428f95db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285749029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1285749029
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.4140635363
Short name T109
Test name
Test status
Simulation time 426742280373 ps
CPU time 123.9 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 192104 kb
Host smart-0536dfda-4ada-4570-abe8-d2c7e17eb1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140635363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.4140635363
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2917269943
Short name T66
Test name
Test status
Simulation time 3001013327 ps
CPU time 12.9 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 214816 kb
Host smart-5715fd9b-f681-47e5-9bd1-55e8ebb40839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917269943 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2917269943
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2427639395
Short name T17
Test name
Test status
Simulation time 94015525237 ps
CPU time 134.94 seconds
Started Aug 19 04:27:24 PM PDT 24
Finished Aug 19 04:29:39 PM PDT 24
Peak memory 198440 kb
Host smart-1c63a95b-2265-4672-8dc1-3a56f71310aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427639395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2427639395
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1439415866
Short name T144
Test name
Test status
Simulation time 206701297821 ps
CPU time 138.29 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:30:31 PM PDT 24
Peak memory 193272 kb
Host smart-eff73b9f-2c4c-4d90-9196-4db6f23719a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439415866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1439415866
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3848071679
Short name T89
Test name
Test status
Simulation time 288403759896 ps
CPU time 114.72 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 192104 kb
Host smart-3a2d2b5f-1122-49ad-86c9-1187fb4ee6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848071679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3848071679
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3810761842
Short name T125
Test name
Test status
Simulation time 465798380044 ps
CPU time 76.05 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 192100 kb
Host smart-485a8827-87f3-455e-9be0-1083d57de454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810761842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3810761842
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1274925158
Short name T104
Test name
Test status
Simulation time 11710693826 ps
CPU time 45.46 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 214552 kb
Host smart-2ef2fa42-3945-4ae0-9f66-13251d7e65e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274925158 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1274925158
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2315868916
Short name T106
Test name
Test status
Simulation time 110956978400 ps
CPU time 36.16 seconds
Started Aug 19 04:27:28 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 184368 kb
Host smart-0254b46d-a17a-4323-b75e-1f6f6a193c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315868916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2315868916
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3623902986
Short name T135
Test name
Test status
Simulation time 152095550270 ps
CPU time 16.94 seconds
Started Aug 19 04:27:14 PM PDT 24
Finished Aug 19 04:27:31 PM PDT 24
Peak memory 192112 kb
Host smart-d96f4804-ba3c-433e-851e-3ba9a263888d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623902986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3623902986
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3988035673
Short name T114
Test name
Test status
Simulation time 364450296306 ps
CPU time 130.91 seconds
Started Aug 19 04:28:43 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 193484 kb
Host smart-486d020c-b45e-4aa4-b002-2813daa8d41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988035673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3988035673
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.773659922
Short name T42
Test name
Test status
Simulation time 1896863141 ps
CPU time 11.23 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 198772 kb
Host smart-4cc981ea-f489-4774-925b-d905ca08af41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773659922 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.773659922
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.990976399
Short name T130
Test name
Test status
Simulation time 17778377912 ps
CPU time 34.42 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 214788 kb
Host smart-56ed4356-88fb-414c-a7e0-f04b0284f617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990976399 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.990976399
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3612874893
Short name T166
Test name
Test status
Simulation time 79197239618 ps
CPU time 14.47 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 198464 kb
Host smart-049f0405-4d52-44db-a996-434ce30da8de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612874893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3612874893
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3081917654
Short name T140
Test name
Test status
Simulation time 6207774239 ps
CPU time 12.77 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 206992 kb
Host smart-a97b8480-5400-440f-b46f-441ea8bba741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081917654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3081917654
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2311832687
Short name T116
Test name
Test status
Simulation time 257903213686 ps
CPU time 61.91 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 193280 kb
Host smart-a535e6d2-00c9-4848-8ac8-a8aeca9bc3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311832687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2311832687
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4293239531
Short name T160
Test name
Test status
Simulation time 68468420452 ps
CPU time 21.44 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 192172 kb
Host smart-e4801c9e-4329-4b9d-aa87-c1133fe35a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293239531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4293239531
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4168029896
Short name T83
Test name
Test status
Simulation time 5060199602 ps
CPU time 32.38 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:28:03 PM PDT 24
Peak memory 198784 kb
Host smart-bda35a95-a19f-45a3-91cb-e63db00d53e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168029896 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4168029896
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2253822309
Short name T79
Test name
Test status
Simulation time 46185532618 ps
CPU time 27.34 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 206900 kb
Host smart-3552df86-d7f5-44ab-8b00-13e6bebfa85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253822309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2253822309
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2814369523
Short name T134
Test name
Test status
Simulation time 5024077722 ps
CPU time 9.55 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 198804 kb
Host smart-a0742ce2-1d5b-44fd-973b-798e2e8ab049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814369523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2814369523
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3524847024
Short name T146
Test name
Test status
Simulation time 285492846476 ps
CPU time 372.85 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 193128 kb
Host smart-f121e02d-67ce-4e3b-a544-a8b63423729b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524847024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3524847024
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.364974970
Short name T76
Test name
Test status
Simulation time 2177215887 ps
CPU time 7.08 seconds
Started Aug 19 04:27:19 PM PDT 24
Finished Aug 19 04:27:26 PM PDT 24
Peak memory 198808 kb
Host smart-6d5615f6-ab50-4e74-86a1-a18c00acd87d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364974970 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.364974970
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2035413116
Short name T77
Test name
Test status
Simulation time 9528352445 ps
CPU time 33.94 seconds
Started Aug 19 04:27:25 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 206972 kb
Host smart-8fb5a506-d5cc-4868-b0db-4241c24b7749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035413116 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2035413116
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3047226073
Short name T137
Test name
Test status
Simulation time 3022548401 ps
CPU time 11.79 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:33 PM PDT 24
Peak memory 214356 kb
Host smart-58047598-d70a-4d85-b50f-4ecdbe178f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047226073 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3047226073
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4206729184
Short name T28
Test name
Test status
Simulation time 4588327760 ps
CPU time 9.69 seconds
Started Aug 19 04:27:59 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 215156 kb
Host smart-e02ee160-7514-4176-83b9-82ec664d31a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206729184 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4206729184
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1345331645
Short name T156
Test name
Test status
Simulation time 373255263 ps
CPU time 1.14 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:47 PM PDT 24
Peak memory 196868 kb
Host smart-f0ab62f4-c13a-42be-b92d-745e939a0ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345331645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1345331645
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1496054492
Short name T147
Test name
Test status
Simulation time 628115184 ps
CPU time 0.64 seconds
Started Aug 19 04:27:46 PM PDT 24
Finished Aug 19 04:27:47 PM PDT 24
Peak memory 196992 kb
Host smart-47c29465-466b-42cd-993a-c6a236fd5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496054492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1496054492
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.716944800
Short name T41
Test name
Test status
Simulation time 7579410781 ps
CPU time 13.26 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 198652 kb
Host smart-b097c255-b56f-4faa-87a4-869ec83d0fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716944800 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.716944800
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1314111281
Short name T97
Test name
Test status
Simulation time 365157952358 ps
CPU time 517.1 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:36:31 PM PDT 24
Peak memory 192848 kb
Host smart-54871590-c61e-4547-b08f-de76f9dfefb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314111281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1314111281
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2728111889
Short name T154
Test name
Test status
Simulation time 552996636 ps
CPU time 1.37 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:06 PM PDT 24
Peak memory 196800 kb
Host smart-03128b65-2317-426d-bd9f-9158472a201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728111889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2728111889
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3669234943
Short name T143
Test name
Test status
Simulation time 55679410261 ps
CPU time 12.9 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 192176 kb
Host smart-adcd78d4-95fa-4606-98ce-6d5e9edc2052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669234943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3669234943
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4137919771
Short name T128
Test name
Test status
Simulation time 3694734800 ps
CPU time 27.85 seconds
Started Aug 19 04:28:05 PM PDT 24
Finished Aug 19 04:28:33 PM PDT 24
Peak memory 214368 kb
Host smart-e36b0015-21ed-4ee0-ac4c-d7da73c287c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137919771 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4137919771
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1101159478
Short name T110
Test name
Test status
Simulation time 207070697476 ps
CPU time 17.15 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 198544 kb
Host smart-e1af75c5-c438-497a-9a6a-2db0b7295c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101159478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1101159478
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1290008275
Short name T181
Test name
Test status
Simulation time 108727998616 ps
CPU time 148.4 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:29:49 PM PDT 24
Peak memory 192096 kb
Host smart-4d18361f-a896-49ea-95c8-09e6cf4bc1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290008275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1290008275
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4019270159
Short name T127
Test name
Test status
Simulation time 44728766119 ps
CPU time 33.07 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 192096 kb
Host smart-85d2f18d-be99-470b-993d-e8d3ff29f5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019270159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4019270159
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3471574440
Short name T65
Test name
Test status
Simulation time 550778910 ps
CPU time 0.89 seconds
Started Aug 19 04:27:59 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 197136 kb
Host smart-8ebb188c-7acb-43e0-9c25-dfcc3a4375b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471574440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3471574440
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3729811885
Short name T126
Test name
Test status
Simulation time 538765705 ps
CPU time 0.81 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 196932 kb
Host smart-77cb2c10-be22-49f5-bd26-2691e1043b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729811885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3729811885
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4150035913
Short name T148
Test name
Test status
Simulation time 487512190 ps
CPU time 1.3 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 196844 kb
Host smart-3c8bbdf3-f9f8-44d7-923c-ab060f949c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150035913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4150035913
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.4073131371
Short name T141
Test name
Test status
Simulation time 601564067 ps
CPU time 0.8 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:27:55 PM PDT 24
Peak memory 196896 kb
Host smart-d7a4ec60-d1d4-40a2-8d3d-31c11c1eea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073131371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.4073131371
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1760761214
Short name T174
Test name
Test status
Simulation time 361101743508 ps
CPU time 514.26 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:37:16 PM PDT 24
Peak memory 193228 kb
Host smart-4a9cb8a7-4999-473b-a8cf-5425d835c1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760761214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1760761214
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2046226855
Short name T10
Test name
Test status
Simulation time 575605128 ps
CPU time 1.49 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 197016 kb
Host smart-dc68fab1-2f1e-4171-a596-49b61d92dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046226855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2046226855
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3930604228
Short name T124
Test name
Test status
Simulation time 514868567 ps
CPU time 0.79 seconds
Started Aug 19 04:28:01 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 195844 kb
Host smart-7b6d2fdc-7fb4-436e-b08c-df4cc9e719c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930604228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3930604228
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3984291341
Short name T119
Test name
Test status
Simulation time 2041122938 ps
CPU time 4.65 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 198404 kb
Host smart-70b4eb9b-5b38-4881-bacd-0e550c4d7029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984291341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3984291341
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2279017830
Short name T16
Test name
Test status
Simulation time 563819338 ps
CPU time 0.76 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 196924 kb
Host smart-397db757-d9d2-4b71-a52f-9982e4094928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279017830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2279017830
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4231779583
Short name T123
Test name
Test status
Simulation time 3108449296 ps
CPU time 20.95 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 215176 kb
Host smart-dc8f0f39-8fb2-4729-ba73-313aeac195f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231779583 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4231779583
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3117742033
Short name T178
Test name
Test status
Simulation time 451487366935 ps
CPU time 105.28 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:29:26 PM PDT 24
Peak memory 192096 kb
Host smart-f7fbef68-aa1c-4839-9df5-19de0fd8d4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117742033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3117742033
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2715396437
Short name T142
Test name
Test status
Simulation time 8231957587 ps
CPU time 22.04 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 198780 kb
Host smart-69256e41-9b33-4bb2-8a89-1383fe87b031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715396437 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2715396437
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3411980453
Short name T118
Test name
Test status
Simulation time 335391515339 ps
CPU time 456.56 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 198440 kb
Host smart-ed239217-64ad-47fa-a188-94b974ba510c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411980453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3411980453
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1014068669
Short name T152
Test name
Test status
Simulation time 504313653 ps
CPU time 1.26 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 196924 kb
Host smart-244aa98b-c29f-46cd-839c-40906254eda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014068669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1014068669
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.4094567839
Short name T155
Test name
Test status
Simulation time 168673646845 ps
CPU time 86.64 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 192188 kb
Host smart-9b0e1412-39c5-4ad3-80c8-c21292166c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094567839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.4094567839
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.722747816
Short name T113
Test name
Test status
Simulation time 581288133 ps
CPU time 1.38 seconds
Started Aug 19 04:27:27 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 196892 kb
Host smart-d00ba033-4c02-405e-a6f2-0bc6da4dc457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722747816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.722747816
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3100831885
Short name T150
Test name
Test status
Simulation time 463583175 ps
CPU time 0.96 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:01 PM PDT 24
Peak memory 196896 kb
Host smart-992c152e-13c4-40f5-a750-3a4377dddee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100831885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3100831885
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.403086584
Short name T73
Test name
Test status
Simulation time 483201185844 ps
CPU time 511.48 seconds
Started Aug 19 04:28:45 PM PDT 24
Finished Aug 19 04:37:17 PM PDT 24
Peak memory 198480 kb
Host smart-6e4bb623-5818-4197-a07a-3c490a017f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403086584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.403086584
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3614061664
Short name T151
Test name
Test status
Simulation time 375563639 ps
CPU time 0.69 seconds
Started Aug 19 04:27:29 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 196832 kb
Host smart-000cd4c2-1238-476c-8241-c88983c34474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614061664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3614061664
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4050821912
Short name T100
Test name
Test status
Simulation time 442756061 ps
CPU time 0.68 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 196832 kb
Host smart-f78ee09d-6ba4-4db9-b454-5de9f1a03df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050821912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4050821912
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2644948470
Short name T162
Test name
Test status
Simulation time 7389237256 ps
CPU time 15.28 seconds
Started Aug 19 04:27:34 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 206888 kb
Host smart-06217011-3a40-4648-886d-3ffcb6fe4261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644948470 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2644948470
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.160581213
Short name T9
Test name
Test status
Simulation time 277288369613 ps
CPU time 383.42 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 184400 kb
Host smart-715b8322-5ed5-4c29-9dec-b51ecfec318a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160581213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.160581213
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3404642564
Short name T94
Test name
Test status
Simulation time 602375102 ps
CPU time 0.85 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 196872 kb
Host smart-ae873291-9135-4ff1-afb9-95c6f7b9c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404642564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3404642564
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1756160012
Short name T96
Test name
Test status
Simulation time 159973474245 ps
CPU time 231.07 seconds
Started Aug 19 04:27:23 PM PDT 24
Finished Aug 19 04:31:14 PM PDT 24
Peak memory 198452 kb
Host smart-28212c0b-1149-4e79-b968-aa11f1d0ee35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756160012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1756160012
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1010262827
Short name T177
Test name
Test status
Simulation time 111762271322 ps
CPU time 155.69 seconds
Started Aug 19 04:28:20 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 192172 kb
Host smart-dd45b9c4-6e18-4e65-8970-d86064a0e6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010262827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1010262827
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3713196700
Short name T149
Test name
Test status
Simulation time 444902720 ps
CPU time 0.66 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:27:27 PM PDT 24
Peak memory 196940 kb
Host smart-1c134128-e2d4-44fe-b4f0-4066cfbee74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713196700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3713196700
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2855661717
Short name T182
Test name
Test status
Simulation time 418604815 ps
CPU time 0.83 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:44 PM PDT 24
Peak memory 196880 kb
Host smart-f79ead83-def7-418a-82cd-f340ddad3fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855661717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2855661717
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2849859290
Short name T13
Test name
Test status
Simulation time 168833865151 ps
CPU time 237.96 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:31:28 PM PDT 24
Peak memory 198536 kb
Host smart-8ae7838d-2a3e-499f-89e9-d8a0253bc947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849859290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2849859290
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.509080002
Short name T25
Test name
Test status
Simulation time 474549820 ps
CPU time 1.45 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:35 PM PDT 24
Peak memory 196896 kb
Host smart-0fa70da7-c15b-4244-ad3d-0114505ee4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509080002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.509080002
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3905894727
Short name T120
Test name
Test status
Simulation time 536098428 ps
CPU time 1.26 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:27:56 PM PDT 24
Peak memory 196936 kb
Host smart-c53d2007-4611-47fd-b764-637c0df4fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905894727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3905894727
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.44519100
Short name T39
Test name
Test status
Simulation time 2944597386 ps
CPU time 18.62 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 214968 kb
Host smart-63ff9bb5-11e0-439d-ba1c-346530657209
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44519100 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.44519100
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.991874433
Short name T168
Test name
Test status
Simulation time 462693467 ps
CPU time 0.94 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 196728 kb
Host smart-ad37b0f4-f47a-4bec-8dbb-d091935df637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991874433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.991874433
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2192937155
Short name T30
Test name
Test status
Simulation time 431279178 ps
CPU time 0.91 seconds
Started Aug 19 04:27:54 PM PDT 24
Finished Aug 19 04:27:55 PM PDT 24
Peak memory 196844 kb
Host smart-3a0a169b-69c4-4852-8dd2-a777bdcd469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192937155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2192937155
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2366814400
Short name T108
Test name
Test status
Simulation time 368550490 ps
CPU time 1.02 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:40 PM PDT 24
Peak memory 196872 kb
Host smart-3fa1e339-a1e8-4f3f-b221-cd08804d225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366814400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2366814400
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1658016596
Short name T175
Test name
Test status
Simulation time 574433580 ps
CPU time 1.53 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:42 PM PDT 24
Peak memory 196896 kb
Host smart-6218b19b-a3e4-43d7-82ea-9be5807ac17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658016596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1658016596
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2808043106
Short name T31
Test name
Test status
Simulation time 375877177 ps
CPU time 0.74 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 196904 kb
Host smart-c35d97e5-b9e9-4380-84a2-7296cff97588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808043106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2808043106
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1957186508
Short name T153
Test name
Test status
Simulation time 355562303 ps
CPU time 1.13 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 196868 kb
Host smart-915103a1-be7e-40ed-8c2e-2c283104c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957186508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1957186508
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1606158801
Short name T179
Test name
Test status
Simulation time 536803084 ps
CPU time 0.76 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 196976 kb
Host smart-fd2929f3-6543-468d-9013-2984d9fe552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606158801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1606158801
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2815685427
Short name T159
Test name
Test status
Simulation time 425999681 ps
CPU time 1.1 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 196888 kb
Host smart-cc7b5c63-9354-4d8f-b262-bb6fd7f66e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815685427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2815685427
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.128383295
Short name T187
Test name
Test status
Simulation time 404682972 ps
CPU time 0.74 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:48 PM PDT 24
Peak memory 196772 kb
Host smart-45228848-3a0c-4e80-9d65-2b880fdad569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128383295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.128383295
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3988044371
Short name T78
Test name
Test status
Simulation time 28529779285 ps
CPU time 17.01 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 198788 kb
Host smart-ae269e20-f61f-45b2-add1-819e9a054648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988044371 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3988044371
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1796897716
Short name T173
Test name
Test status
Simulation time 491241001 ps
CPU time 0.71 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 196824 kb
Host smart-0a8218e9-5a16-4ea4-9a38-7d0ba1974914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796897716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1796897716
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.474968888
Short name T180
Test name
Test status
Simulation time 563324433 ps
CPU time 0.99 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 196860 kb
Host smart-e80871a1-a1d3-40c3-b013-6872e3bd5ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474968888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.474968888
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2953934901
Short name T172
Test name
Test status
Simulation time 398101516 ps
CPU time 0.98 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 196872 kb
Host smart-bfd73654-7fc4-4ce5-b7a3-fbe3231a3ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953934901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2953934901
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1500511151
Short name T29
Test name
Test status
Simulation time 494489591 ps
CPU time 0.66 seconds
Started Aug 19 04:27:18 PM PDT 24
Finished Aug 19 04:27:19 PM PDT 24
Peak memory 196880 kb
Host smart-d796ae77-89b8-43b3-9775-4923ac2fe817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500511151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1500511151
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2594068812
Short name T334
Test name
Test status
Simulation time 7843509877 ps
CPU time 7.29 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 198300 kb
Host smart-959696ce-7e83-4f4a-9713-8aacfe7d8d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594068812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2594068812
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.aon_timer_jump.85245065
Short name T4
Test name
Test status
Simulation time 595380335 ps
CPU time 0.79 seconds
Started Aug 19 04:27:15 PM PDT 24
Finished Aug 19 04:27:16 PM PDT 24
Peak memory 196720 kb
Host smart-af7f1ada-11f7-4add-bd45-5c57041cf5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85245065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.85245065
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3558721283
Short name T163
Test name
Test status
Simulation time 525655767 ps
CPU time 0.82 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 197000 kb
Host smart-62c55c3a-4271-4e5b-b14c-b66f3c905297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558721283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3558721283
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.566682086
Short name T164
Test name
Test status
Simulation time 4480167024 ps
CPU time 9.38 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 206896 kb
Host smart-5a1c1193-4ae6-4893-9d1a-87de1bb2c881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566682086 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.566682086
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1057549912
Short name T186
Test name
Test status
Simulation time 630494033 ps
CPU time 0.97 seconds
Started Aug 19 04:27:46 PM PDT 24
Finished Aug 19 04:27:47 PM PDT 24
Peak memory 196884 kb
Host smart-357df1ec-eb31-4cfb-be6a-bd6378b194f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057549912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1057549912
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2634630984
Short name T133
Test name
Test status
Simulation time 346557804 ps
CPU time 1.1 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:03 PM PDT 24
Peak memory 196868 kb
Host smart-3aff9d2b-d4fd-46d5-b262-724c0da46ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634630984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2634630984
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.406204822
Short name T38
Test name
Test status
Simulation time 2440731866 ps
CPU time 15.94 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 206916 kb
Host smart-36c7bce4-2a2f-4dba-a2bd-4ec999954c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406204822 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.406204822
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2953363023
Short name T11
Test name
Test status
Simulation time 466779707 ps
CPU time 1.29 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:44 PM PDT 24
Peak memory 196876 kb
Host smart-4d772e41-782e-43a0-b6f2-62ccfc452abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953363023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2953363023
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2239525221
Short name T170
Test name
Test status
Simulation time 445945675 ps
CPU time 0.72 seconds
Started Aug 19 04:28:29 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 196904 kb
Host smart-d6dc6cda-8e5f-4d4b-bfdd-bcb0a219ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239525221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2239525221
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2568528688
Short name T185
Test name
Test status
Simulation time 501463308 ps
CPU time 0.7 seconds
Started Aug 19 04:28:46 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 196904 kb
Host smart-b2310320-099f-4aa6-ac5f-0b07d7e86cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568528688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2568528688
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3765272665
Short name T183
Test name
Test status
Simulation time 576523774 ps
CPU time 0.95 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 196968 kb
Host smart-f719c05f-de6f-458f-87ff-e5e29248a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765272665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3765272665
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1565447432
Short name T43
Test name
Test status
Simulation time 5700536737 ps
CPU time 18.83 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 206956 kb
Host smart-497e989f-5f62-45b6-b73e-25e2734b95d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565447432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1565447432
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3551878783
Short name T161
Test name
Test status
Simulation time 622488524 ps
CPU time 0.61 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 196972 kb
Host smart-c49f74a6-40ae-4ec0-974e-1c9607780f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551878783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3551878783
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2917535281
Short name T54
Test name
Test status
Simulation time 483019396 ps
CPU time 0.93 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 194552 kb
Host smart-1de9e741-952b-4ac3-967d-b0ad6525fbfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917535281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2917535281
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3655749067
Short name T417
Test name
Test status
Simulation time 14076442731 ps
CPU time 6.22 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 192192 kb
Host smart-894b8577-9f39-4d4c-ba5d-f92ffac173bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655749067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3655749067
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1298071631
Short name T349
Test name
Test status
Simulation time 1151827401 ps
CPU time 2.32 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 193356 kb
Host smart-44e8ddf8-b462-417a-8f58-ab2015c8d9a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298071631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1298071631
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4025735580
Short name T339
Test name
Test status
Simulation time 461289867 ps
CPU time 1.02 seconds
Started Aug 19 04:26:08 PM PDT 24
Finished Aug 19 04:26:09 PM PDT 24
Peak memory 196108 kb
Host smart-8d538186-1ec8-4596-80e7-06e3d225385e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025735580 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4025735580
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2790276200
Short name T75
Test name
Test status
Simulation time 397750016 ps
CPU time 1.19 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 192952 kb
Host smart-8f8c197a-5fa6-4f68-acaf-ae7ef9bc78bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790276200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2790276200
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3641033710
Short name T295
Test name
Test status
Simulation time 369271118 ps
CPU time 0.99 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183676 kb
Host smart-3d1cdf86-48fd-41ad-a46d-d8c0d7332b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641033710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3641033710
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.536511153
Short name T394
Test name
Test status
Simulation time 527986642 ps
CPU time 0.66 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:13 PM PDT 24
Peak memory 183596 kb
Host smart-e9f4b5cf-bfb7-4a14-bcaf-e0fb7031915b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536511153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.536511153
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3399544421
Short name T402
Test name
Test status
Simulation time 513710826 ps
CPU time 0.91 seconds
Started Aug 19 04:26:09 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 183604 kb
Host smart-b8b4563a-8648-4d60-b40c-3f71bd2688ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399544421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3399544421
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.232400941
Short name T63
Test name
Test status
Simulation time 1356949256 ps
CPU time 0.91 seconds
Started Aug 19 04:25:56 PM PDT 24
Finished Aug 19 04:25:57 PM PDT 24
Peak memory 192944 kb
Host smart-3f3cc9a0-331e-4e99-bece-f1dc1f663c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232400941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.232400941
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.115553078
Short name T358
Test name
Test status
Simulation time 644817997 ps
CPU time 2.21 seconds
Started Aug 19 04:26:09 PM PDT 24
Finished Aug 19 04:26:11 PM PDT 24
Peak memory 198536 kb
Host smart-565223d0-7860-486a-871c-17f98d4d5784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115553078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.115553078
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.990729585
Short name T55
Test name
Test status
Simulation time 485389130 ps
CPU time 1.29 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:18 PM PDT 24
Peak memory 183744 kb
Host smart-b8b4cb82-558e-424c-8bee-b71134606e46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990729585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.990729585
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3046261659
Short name T48
Test name
Test status
Simulation time 9675215424 ps
CPU time 5.42 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 184020 kb
Host smart-5cbc3743-8adc-4cc1-94b5-030ee9a68dd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046261659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3046261659
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1856078990
Short name T407
Test name
Test status
Simulation time 1196868973 ps
CPU time 2.4 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 193244 kb
Host smart-39948410-f400-44bd-baec-c4009d8ed038
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856078990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1856078990
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1391160460
Short name T372
Test name
Test status
Simulation time 573296117 ps
CPU time 1.14 seconds
Started Aug 19 04:26:02 PM PDT 24
Finished Aug 19 04:26:09 PM PDT 24
Peak memory 198292 kb
Host smart-7d17e808-c7bd-4191-a387-bcd7389471b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391160460 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1391160460
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3972478319
Short name T60
Test name
Test status
Simulation time 402373028 ps
CPU time 0.94 seconds
Started Aug 19 04:26:35 PM PDT 24
Finished Aug 19 04:26:36 PM PDT 24
Peak memory 193240 kb
Host smart-e25b281b-b8b3-41a3-a242-2b3e46469190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972478319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3972478319
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1961297754
Short name T327
Test name
Test status
Simulation time 460039386 ps
CPU time 1.27 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192900 kb
Host smart-7232a3bd-11e4-4c8a-b890-4ac77bf20b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961297754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1961297754
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2146594903
Short name T318
Test name
Test status
Simulation time 498833718 ps
CPU time 1.2 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 183572 kb
Host smart-f136e67a-bac8-4d8a-9ca7-723fb196ed0e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146594903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2146594903
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2385469164
Short name T297
Test name
Test status
Simulation time 418328949 ps
CPU time 1.07 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 183572 kb
Host smart-2f7c3690-4c06-40ac-99a4-ec1601d62f4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385469164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2385469164
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3696054029
Short name T370
Test name
Test status
Simulation time 1537120613 ps
CPU time 2.18 seconds
Started Aug 19 04:26:02 PM PDT 24
Finished Aug 19 04:26:05 PM PDT 24
Peak memory 193400 kb
Host smart-0c2dde16-0eb5-49ba-801b-435da6484587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696054029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3696054029
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2246381242
Short name T277
Test name
Test status
Simulation time 541457878 ps
CPU time 2.03 seconds
Started Aug 19 04:26:02 PM PDT 24
Finished Aug 19 04:26:04 PM PDT 24
Peak memory 198592 kb
Host smart-ee7da979-1f37-45e7-8c7d-1bcdd1379055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246381242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2246381242
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.766377921
Short name T33
Test name
Test status
Simulation time 8045323258 ps
CPU time 11.36 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:32 PM PDT 24
Peak memory 198260 kb
Host smart-b5fcaecb-0cdf-4533-a5c0-ec9dc13a2c61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766377921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.766377921
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3117053135
Short name T343
Test name
Test status
Simulation time 527598680 ps
CPU time 0.92 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 197332 kb
Host smart-ba3c41ab-1b86-4974-a5b5-40e2e5b518e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117053135 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3117053135
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.95329348
Short name T49
Test name
Test status
Simulation time 396315781 ps
CPU time 0.67 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 191976 kb
Host smart-db863967-ec72-4ce3-95f1-ee8303512d28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95329348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.95329348
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3495809983
Short name T416
Test name
Test status
Simulation time 355054693 ps
CPU time 1.04 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183648 kb
Host smart-e77da8ee-9823-4337-a493-bea98e6f164c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495809983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3495809983
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1469861507
Short name T412
Test name
Test status
Simulation time 2620331340 ps
CPU time 0.98 seconds
Started Aug 19 04:26:03 PM PDT 24
Finished Aug 19 04:26:04 PM PDT 24
Peak memory 193924 kb
Host smart-fd84567c-36a4-48f0-bc56-746c8a7d39af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469861507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1469861507
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.269509228
Short name T342
Test name
Test status
Simulation time 571257386 ps
CPU time 2.32 seconds
Started Aug 19 04:26:03 PM PDT 24
Finished Aug 19 04:26:06 PM PDT 24
Peak memory 198492 kb
Host smart-31fe0350-498f-4eca-b897-c09ec5b4c2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269509228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.269509228
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3460566557
Short name T408
Test name
Test status
Simulation time 4371707667 ps
CPU time 7.64 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:28 PM PDT 24
Peak memory 197672 kb
Host smart-13a738f1-9383-4dce-af64-d69f0f246eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460566557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3460566557
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1842077015
Short name T287
Test name
Test status
Simulation time 437775267 ps
CPU time 1.03 seconds
Started Aug 19 04:26:26 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 198356 kb
Host smart-f848ad44-a645-4674-98a5-744db718a303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842077015 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1842077015
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.462080517
Short name T37
Test name
Test status
Simulation time 507043378 ps
CPU time 1.31 seconds
Started Aug 19 04:26:03 PM PDT 24
Finished Aug 19 04:26:04 PM PDT 24
Peak memory 192880 kb
Host smart-3864f376-857c-464a-8e36-013137ad817e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462080517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.462080517
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1747880721
Short name T357
Test name
Test status
Simulation time 423736475 ps
CPU time 1.05 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 181840 kb
Host smart-4da23ad8-1976-42fb-8946-96288efec0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747880721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1747880721
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.143072347
Short name T64
Test name
Test status
Simulation time 2393673614 ps
CPU time 5.1 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 192288 kb
Host smart-1da5aac0-6cf5-4eb2-a0f1-ee9628ba73ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143072347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.143072347
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3588807561
Short name T335
Test name
Test status
Simulation time 383518263 ps
CPU time 2.93 seconds
Started Aug 19 04:26:03 PM PDT 24
Finished Aug 19 04:26:06 PM PDT 24
Peak memory 198496 kb
Host smart-d1b960c2-55d6-47de-97af-65b63658bd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588807561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3588807561
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.289955245
Short name T350
Test name
Test status
Simulation time 9026683230 ps
CPU time 8.57 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 198284 kb
Host smart-bff9d2ca-af46-4c5a-9514-1cdc1268ef7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289955245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.289955245
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.980584942
Short name T292
Test name
Test status
Simulation time 497790885 ps
CPU time 0.79 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 196596 kb
Host smart-d2d13020-3106-4abf-b6b9-ef826d8499ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980584942 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.980584942
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3759049262
Short name T378
Test name
Test status
Simulation time 452485463 ps
CPU time 0.73 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 192028 kb
Host smart-21a96364-abb4-4daf-8d6e-742ca3d58dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759049262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3759049262
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.121116627
Short name T280
Test name
Test status
Simulation time 345424848 ps
CPU time 1.01 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 192892 kb
Host smart-428f43aa-51a3-45ae-a9e8-cbae3bff40a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121116627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.121116627
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1366327819
Short name T35
Test name
Test status
Simulation time 1458394412 ps
CPU time 0.9 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:36 PM PDT 24
Peak memory 193748 kb
Host smart-487e175d-c67a-4183-b1c4-b85d90f5a951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366327819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1366327819
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2492643979
Short name T317
Test name
Test status
Simulation time 455608549 ps
CPU time 2.49 seconds
Started Aug 19 04:26:07 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 198528 kb
Host smart-42372f58-5fb9-4221-8417-041d58478979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492643979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2492643979
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.269012889
Short name T383
Test name
Test status
Simulation time 4338407367 ps
CPU time 6.38 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:26 PM PDT 24
Peak memory 197604 kb
Host smart-fc8d3057-03e6-48a8-9c4f-730a89e59b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269012889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.269012889
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.508088372
Short name T337
Test name
Test status
Simulation time 550721709 ps
CPU time 0.98 seconds
Started Aug 19 04:26:42 PM PDT 24
Finished Aug 19 04:26:43 PM PDT 24
Peak memory 197684 kb
Host smart-f1bf7326-7201-4d0c-8e35-ac688ada5fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508088372 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.508088372
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4164366336
Short name T410
Test name
Test status
Simulation time 434248301 ps
CPU time 0.61 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:11 PM PDT 24
Peak memory 192952 kb
Host smart-2d0aac2e-e085-428c-b68f-b2fb0db2c160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164366336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4164366336
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.123652480
Short name T413
Test name
Test status
Simulation time 511438153 ps
CPU time 1.2 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 183680 kb
Host smart-cd78abea-6e95-422d-b958-71c6789da3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123652480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.123652480
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.330479734
Short name T398
Test name
Test status
Simulation time 1459451415 ps
CPU time 2.32 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 193660 kb
Host smart-847c011e-9570-47f7-a2dc-8c7c6efe9e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330479734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.330479734
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.513206213
Short name T312
Test name
Test status
Simulation time 509740770 ps
CPU time 2.66 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 198540 kb
Host smart-bdfb300c-4a74-4f42-893f-bebe702d3e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513206213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.513206213
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2476171980
Short name T422
Test name
Test status
Simulation time 8502330636 ps
CPU time 3.88 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 198272 kb
Host smart-a634e523-67f5-4b23-96a9-459d4f4e4f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476171980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2476171980
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2353498192
Short name T324
Test name
Test status
Simulation time 352039780 ps
CPU time 0.86 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 195512 kb
Host smart-cdf20386-a735-44f8-8704-a1aa4d95d367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353498192 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2353498192
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1767227567
Short name T352
Test name
Test status
Simulation time 314053034 ps
CPU time 0.97 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 193528 kb
Host smart-b8f781ab-7bbe-44cd-a35c-1565b591fcc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767227567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1767227567
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2452693395
Short name T371
Test name
Test status
Simulation time 430683386 ps
CPU time 0.64 seconds
Started Aug 19 04:26:09 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 183652 kb
Host smart-a3acf922-6959-4468-9e28-5ef7cb000f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452693395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2452693395
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3122085276
Short name T61
Test name
Test status
Simulation time 941067665 ps
CPU time 1.47 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:12 PM PDT 24
Peak memory 183924 kb
Host smart-c8f3b963-744a-48a2-9d05-e4c3aa26b29d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122085276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3122085276
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2332034003
Short name T291
Test name
Test status
Simulation time 459847509 ps
CPU time 2.89 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 198492 kb
Host smart-45bf2430-5e64-4cab-a81c-7c42687659ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332034003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2332034003
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.854072928
Short name T396
Test name
Test status
Simulation time 310219042 ps
CPU time 0.85 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 196096 kb
Host smart-1c5b6334-4d2a-4fc9-8f0d-e3ee381e2efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854072928 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.854072928
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2453855381
Short name T381
Test name
Test status
Simulation time 380606863 ps
CPU time 0.85 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 192956 kb
Host smart-ce7f767e-5a39-4e8d-9905-3b1e6f513b1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453855381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2453855381
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2901774317
Short name T326
Test name
Test status
Simulation time 318125737 ps
CPU time 0.62 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 183684 kb
Host smart-fdb5c854-1948-42dc-9f38-c14d08cee0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901774317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2901774317
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.106407997
Short name T338
Test name
Test status
Simulation time 2113977155 ps
CPU time 2.87 seconds
Started Aug 19 04:26:44 PM PDT 24
Finished Aug 19 04:26:47 PM PDT 24
Peak memory 193948 kb
Host smart-a392c1e7-7f22-462f-8d19-95837f477813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106407997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.106407997
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3250998677
Short name T286
Test name
Test status
Simulation time 499263578 ps
CPU time 2.15 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 198484 kb
Host smart-4a766285-d3f8-42df-842b-c23a0be591c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250998677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3250998677
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2457048523
Short name T333
Test name
Test status
Simulation time 4216420084 ps
CPU time 1.86 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 197836 kb
Host smart-506d132f-b32c-4f94-9479-3353b6e5f2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457048523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2457048523
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.890654151
Short name T348
Test name
Test status
Simulation time 365180096 ps
CPU time 0.87 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:18 PM PDT 24
Peak memory 195608 kb
Host smart-d05659a2-e7d7-4e3c-b96f-70f269be4231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890654151 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.890654151
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2500048082
Short name T282
Test name
Test status
Simulation time 364769481 ps
CPU time 0.97 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 183660 kb
Host smart-58ae2cbf-4cbf-4378-8a3b-31940f7aff47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500048082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2500048082
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2012682784
Short name T355
Test name
Test status
Simulation time 1228959476 ps
CPU time 1.02 seconds
Started Aug 19 04:26:15 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 193624 kb
Host smart-b959b6e4-8e0d-46a1-8570-e029c676a0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012682784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2012682784
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2901181730
Short name T336
Test name
Test status
Simulation time 621502622 ps
CPU time 1.31 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:38 PM PDT 24
Peak memory 198340 kb
Host smart-80b1ee74-2b29-4e3c-b3a3-89380a93f83a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901181730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2901181730
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1977904710
Short name T303
Test name
Test status
Simulation time 8342000592 ps
CPU time 12.8 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:33 PM PDT 24
Peak memory 198200 kb
Host smart-e15329af-39a8-4d6a-a615-6c01322d50b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977904710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1977904710
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3906783261
Short name T288
Test name
Test status
Simulation time 360111790 ps
CPU time 0.77 seconds
Started Aug 19 04:26:16 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 196308 kb
Host smart-a9e8d31c-aaf6-49bf-b8a0-d2bc967765a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906783261 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3906783261
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.368077715
Short name T387
Test name
Test status
Simulation time 453953095 ps
CPU time 0.92 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 193140 kb
Host smart-75f6e64b-4d5a-4b6d-811f-3f94c7f044a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368077715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.368077715
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2499797750
Short name T298
Test name
Test status
Simulation time 364403730 ps
CPU time 0.59 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:28 PM PDT 24
Peak memory 192904 kb
Host smart-6413ee17-cfcc-4fcf-86f1-9a0e27c2ce96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499797750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2499797750
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1273003419
Short name T59
Test name
Test status
Simulation time 1459445908 ps
CPU time 1.09 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 183748 kb
Host smart-f57b58fd-be7b-4823-9c0c-bf926653ec2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273003419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1273003419
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.522367438
Short name T278
Test name
Test status
Simulation time 443074641 ps
CPU time 2.61 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 198532 kb
Host smart-84af7945-e939-48ed-a693-ccb8662c6eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522367438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.522367438
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3854778293
Short name T289
Test name
Test status
Simulation time 4298610858 ps
CPU time 7.02 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:36 PM PDT 24
Peak memory 196492 kb
Host smart-988c3bd7-9c45-4bbc-ada8-1df593435457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854778293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3854778293
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3170385106
Short name T369
Test name
Test status
Simulation time 558210416 ps
CPU time 1.46 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 196476 kb
Host smart-8374251e-a6ab-45c5-b89e-6b22564d3165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170385106 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3170385106
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3176753329
Short name T46
Test name
Test status
Simulation time 468609417 ps
CPU time 0.84 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 193984 kb
Host smart-4d12fd9e-45cf-46ee-aa12-f0beaa058800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176753329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3176753329
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.408315207
Short name T406
Test name
Test status
Simulation time 441128114 ps
CPU time 1.17 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 183684 kb
Host smart-d527b8e9-5804-4ac9-a0bd-2f1e04a4b6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408315207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.408315207
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.950703507
Short name T346
Test name
Test status
Simulation time 2161512569 ps
CPU time 3.64 seconds
Started Aug 19 04:26:33 PM PDT 24
Finished Aug 19 04:26:37 PM PDT 24
Peak memory 193068 kb
Host smart-bbb1d09f-03ab-4dc1-bab9-69cd9d397a7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950703507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.950703507
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3134711699
Short name T302
Test name
Test status
Simulation time 537709530 ps
CPU time 3.29 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 198532 kb
Host smart-d096f3d0-b25b-46e7-97e8-1c40ba2ceb17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134711699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3134711699
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3637740237
Short name T311
Test name
Test status
Simulation time 4229123327 ps
CPU time 1.73 seconds
Started Aug 19 04:26:11 PM PDT 24
Finished Aug 19 04:26:18 PM PDT 24
Peak memory 197780 kb
Host smart-8059a189-b3fd-4a1b-97da-01851860c316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637740237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3637740237
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2143578070
Short name T367
Test name
Test status
Simulation time 306974689 ps
CPU time 1.02 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 195968 kb
Host smart-12d333e8-c90b-4be5-b876-322885d8c4f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143578070 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2143578070
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3613256544
Short name T397
Test name
Test status
Simulation time 599309261 ps
CPU time 0.63 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192968 kb
Host smart-c49c03d4-8274-46e3-b72c-c24f8c0c6ea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613256544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3613256544
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3119558685
Short name T405
Test name
Test status
Simulation time 351749885 ps
CPU time 0.68 seconds
Started Aug 19 04:26:48 PM PDT 24
Finished Aug 19 04:26:48 PM PDT 24
Peak memory 192916 kb
Host smart-6d359215-69f1-4f28-afc8-7240cc38d73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119558685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3119558685
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3148999393
Short name T368
Test name
Test status
Simulation time 1377142847 ps
CPU time 2.38 seconds
Started Aug 19 04:26:27 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 194088 kb
Host smart-2a7e0dda-3705-481f-b12a-563467f0b546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148999393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3148999393
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.618592392
Short name T393
Test name
Test status
Simulation time 897424159 ps
CPU time 2.12 seconds
Started Aug 19 04:26:27 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 198540 kb
Host smart-3d3c00a3-dfff-4e65-9853-42f235d35b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618592392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.618592392
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2638217239
Short name T361
Test name
Test status
Simulation time 4193329195 ps
CPU time 7.08 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 197884 kb
Host smart-8f59358f-0c36-4a15-8b21-1a6f6ff4fac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638217239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2638217239
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2791928967
Short name T379
Test name
Test status
Simulation time 494821189 ps
CPU time 1.02 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 193184 kb
Host smart-4c1af5b8-e37c-4859-8056-006f3b594c71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791928967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2791928967
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4276700027
Short name T362
Test name
Test status
Simulation time 7441441136 ps
CPU time 2.79 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 192200 kb
Host smart-bc530721-1e71-440e-8c4b-48951ff77b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276700027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4276700027
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.574908407
Short name T409
Test name
Test status
Simulation time 1339382955 ps
CPU time 0.75 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 193240 kb
Host smart-c367562c-5f30-4f9c-b47b-3af01f267969
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574908407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.574908407
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2239897117
Short name T307
Test name
Test status
Simulation time 801353091 ps
CPU time 0.69 seconds
Started Aug 19 04:26:08 PM PDT 24
Finished Aug 19 04:26:09 PM PDT 24
Peak memory 195996 kb
Host smart-7086e960-0543-466e-aca9-4ec77bf40f85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239897117 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2239897117
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3235942349
Short name T50
Test name
Test status
Simulation time 406063877 ps
CPU time 0.72 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 193112 kb
Host smart-553e054a-9403-4bac-95e6-914024605e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235942349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3235942349
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2706354257
Short name T423
Test name
Test status
Simulation time 417415768 ps
CPU time 1.17 seconds
Started Aug 19 04:26:05 PM PDT 24
Finished Aug 19 04:26:11 PM PDT 24
Peak memory 183676 kb
Host smart-0aab84a3-2d22-4043-af88-339b89640570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706354257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2706354257
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.256368154
Short name T314
Test name
Test status
Simulation time 470310003 ps
CPU time 0.66 seconds
Started Aug 19 04:26:16 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 183600 kb
Host smart-9be701a2-72f8-4697-8828-91095be8c4ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256368154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.256368154
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1426912826
Short name T388
Test name
Test status
Simulation time 269970364 ps
CPU time 0.91 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183604 kb
Host smart-fc51963c-faee-4fed-a9f8-c3a2cff5897d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426912826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1426912826
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1262262682
Short name T62
Test name
Test status
Simulation time 1617736307 ps
CPU time 1.52 seconds
Started Aug 19 04:26:16 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 183744 kb
Host smart-2f6b2dfc-e2c6-4b85-a480-5944b190be00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262262682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1262262682
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1478576829
Short name T294
Test name
Test status
Simulation time 409864598 ps
CPU time 1.64 seconds
Started Aug 19 04:26:02 PM PDT 24
Finished Aug 19 04:26:04 PM PDT 24
Peak memory 198480 kb
Host smart-4539fa13-48ad-40fc-bfa1-e48f56e2414b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478576829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1478576829
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.198950691
Short name T34
Test name
Test status
Simulation time 8543590215 ps
CPU time 14.22 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 198320 kb
Host smart-54d848b6-5d5f-4cfb-8b42-5b94e63f864b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198950691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.198950691
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.438563994
Short name T382
Test name
Test status
Simulation time 395397555 ps
CPU time 1.12 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192884 kb
Host smart-0e1587e0-e69e-4d09-afd4-eb8c152b4ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438563994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.438563994
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2107870263
Short name T386
Test name
Test status
Simulation time 282263897 ps
CPU time 0.67 seconds
Started Aug 19 04:26:30 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 183652 kb
Host smart-0eb9aec6-1506-4687-81c3-703733c4bdb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107870263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2107870263
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1447011125
Short name T309
Test name
Test status
Simulation time 503480975 ps
CPU time 1.3 seconds
Started Aug 19 04:26:09 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 192904 kb
Host smart-03b23c11-e284-43b0-9690-a48007344568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447011125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1447011125
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3720497602
Short name T301
Test name
Test status
Simulation time 359640981 ps
CPU time 1.04 seconds
Started Aug 19 04:26:38 PM PDT 24
Finished Aug 19 04:26:39 PM PDT 24
Peak memory 192892 kb
Host smart-d5cdf437-3cf6-4de7-acfa-2327a10dab10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720497602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3720497602
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3627335935
Short name T279
Test name
Test status
Simulation time 341456779 ps
CPU time 0.63 seconds
Started Aug 19 04:26:36 PM PDT 24
Finished Aug 19 04:26:37 PM PDT 24
Peak memory 183672 kb
Host smart-3836b8c7-dadd-42d4-a130-865243aafd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627335935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3627335935
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1897356886
Short name T363
Test name
Test status
Simulation time 482698813 ps
CPU time 0.69 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183672 kb
Host smart-a0779311-69b4-440c-a20f-e9a6d258e2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897356886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1897356886
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3206039924
Short name T365
Test name
Test status
Simulation time 333855041 ps
CPU time 0.68 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:26:53 PM PDT 24
Peak memory 183688 kb
Host smart-7804c418-1eb2-446b-b0b1-04880c835c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206039924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3206039924
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3790769931
Short name T322
Test name
Test status
Simulation time 318733007 ps
CPU time 0.94 seconds
Started Aug 19 04:26:24 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 183668 kb
Host smart-faf8db21-5ca5-439e-b040-fde7d2618c88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790769931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3790769931
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1609265493
Short name T351
Test name
Test status
Simulation time 431976932 ps
CPU time 1.12 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:31 PM PDT 24
Peak memory 183688 kb
Host smart-b81974d6-f6e5-47cc-bb4b-04bbe7506df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609265493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1609265493
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3478802365
Short name T330
Test name
Test status
Simulation time 271772913 ps
CPU time 0.88 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183684 kb
Host smart-74d970e6-86ef-4f75-b4ad-890581992497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478802365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3478802365
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3263611308
Short name T56
Test name
Test status
Simulation time 532810900 ps
CPU time 1.45 seconds
Started Aug 19 04:25:58 PM PDT 24
Finished Aug 19 04:25:59 PM PDT 24
Peak memory 183740 kb
Host smart-52ab850b-4ac4-4554-8dc8-9c3054e965aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263611308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3263611308
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.560630916
Short name T375
Test name
Test status
Simulation time 7065117910 ps
CPU time 4.34 seconds
Started Aug 19 04:26:01 PM PDT 24
Finished Aug 19 04:26:05 PM PDT 24
Peak memory 192244 kb
Host smart-1c82515e-42a5-412b-b60d-f07008bcccb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560630916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.560630916
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3929179606
Short name T58
Test name
Test status
Simulation time 793249316 ps
CPU time 0.86 seconds
Started Aug 19 04:26:02 PM PDT 24
Finished Aug 19 04:26:03 PM PDT 24
Peak memory 183808 kb
Host smart-0c69f491-25a4-40bd-a84f-603403be4060
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929179606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3929179606
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4072337105
Short name T293
Test name
Test status
Simulation time 327708223 ps
CPU time 0.88 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:18 PM PDT 24
Peak memory 195600 kb
Host smart-07df82bb-cff4-4726-a825-4d2be628c536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072337105 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4072337105
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2329011981
Short name T47
Test name
Test status
Simulation time 448463022 ps
CPU time 1.23 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192024 kb
Host smart-875a89e4-06cb-4f53-b9c6-4f27cac2fb13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329011981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2329011981
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1886058838
Short name T315
Test name
Test status
Simulation time 343908857 ps
CPU time 0.58 seconds
Started Aug 19 04:26:06 PM PDT 24
Finished Aug 19 04:26:06 PM PDT 24
Peak memory 183672 kb
Host smart-85177ae0-8d05-43b9-9fdd-891be7604dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886058838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1886058838
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1763488157
Short name T404
Test name
Test status
Simulation time 288149945 ps
CPU time 0.61 seconds
Started Aug 19 04:26:16 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 183592 kb
Host smart-96fdc864-e3a7-4040-aeb7-eaa5be4a6e84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763488157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1763488157
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2322948204
Short name T344
Test name
Test status
Simulation time 447634639 ps
CPU time 0.67 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 183592 kb
Host smart-ebd67682-c6de-425b-87d9-b60119aadfe3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322948204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2322948204
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1937279759
Short name T380
Test name
Test status
Simulation time 2333114150 ps
CPU time 2.04 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:31 PM PDT 24
Peak memory 195336 kb
Host smart-ae773ff2-bf11-4d26-8afd-27062dc6990f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937279759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1937279759
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.475989838
Short name T285
Test name
Test status
Simulation time 451157390 ps
CPU time 2.19 seconds
Started Aug 19 04:26:04 PM PDT 24
Finished Aug 19 04:26:06 PM PDT 24
Peak memory 198560 kb
Host smart-1f5b0f1c-dce6-4c06-aa9f-3b5214f1efe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475989838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.475989838
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1917870681
Short name T401
Test name
Test status
Simulation time 8783244341 ps
CPU time 5.11 seconds
Started Aug 19 04:26:26 PM PDT 24
Finished Aug 19 04:26:31 PM PDT 24
Peak memory 198300 kb
Host smart-05285b99-4bd0-47e5-b4eb-b2000670c76d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917870681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1917870681
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.391516104
Short name T341
Test name
Test status
Simulation time 436075053 ps
CPU time 0.69 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:26 PM PDT 24
Peak memory 183688 kb
Host smart-55682e61-6cae-4eff-9ab0-4e8f979896d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391516104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.391516104
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4202191279
Short name T347
Test name
Test status
Simulation time 443038766 ps
CPU time 0.73 seconds
Started Aug 19 04:26:52 PM PDT 24
Finished Aug 19 04:26:53 PM PDT 24
Peak memory 183672 kb
Host smart-a74562f3-c826-46c1-80d9-9e1a267b5ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202191279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4202191279
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4183566875
Short name T284
Test name
Test status
Simulation time 350626694 ps
CPU time 0.55 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 183676 kb
Host smart-891a4728-f9f0-418b-89ca-f04a4725f52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183566875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4183566875
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4233400001
Short name T305
Test name
Test status
Simulation time 506422327 ps
CPU time 1.3 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192908 kb
Host smart-6254cebb-bf86-4a37-be94-8844f0a2f956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233400001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.4233400001
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4184468984
Short name T421
Test name
Test status
Simulation time 365068082 ps
CPU time 0.63 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 183696 kb
Host smart-debf01d1-56c4-422e-b116-86b31a2faa7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184468984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4184468984
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1255582778
Short name T418
Test name
Test status
Simulation time 454327335 ps
CPU time 0.9 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 183696 kb
Host smart-8c32baa2-0b4c-4595-ae00-c4244e639805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255582778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1255582778
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.808185725
Short name T308
Test name
Test status
Simulation time 429588424 ps
CPU time 1.11 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 183672 kb
Host smart-dfb9bb31-ae39-4219-adb5-75725324c19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808185725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.808185725
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3459344684
Short name T389
Test name
Test status
Simulation time 306648086 ps
CPU time 0.97 seconds
Started Aug 19 04:26:28 PM PDT 24
Finished Aug 19 04:26:29 PM PDT 24
Peak memory 192896 kb
Host smart-fabbf33d-d33c-480a-b98b-a4e1cefcc028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459344684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3459344684
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2676590577
Short name T320
Test name
Test status
Simulation time 468759772 ps
CPU time 0.83 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183644 kb
Host smart-d3472d59-16f3-458c-bac2-0156b519079f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676590577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2676590577
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1461290946
Short name T304
Test name
Test status
Simulation time 376159464 ps
CPU time 0.79 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 183676 kb
Host smart-237e69ad-43ce-437e-a466-6d4395b352bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461290946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1461290946
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3793072241
Short name T52
Test name
Test status
Simulation time 631570125 ps
CPU time 0.83 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183732 kb
Host smart-48213537-c9f8-4a2e-9373-b12fe098e7fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793072241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3793072241
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4090354466
Short name T53
Test name
Test status
Simulation time 14354582143 ps
CPU time 10.69 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 196224 kb
Host smart-61fc9af4-27c5-417d-a214-a477fc5bfde2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090354466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4090354466
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4024773233
Short name T51
Test name
Test status
Simulation time 1002903800 ps
CPU time 1.43 seconds
Started Aug 19 04:26:25 PM PDT 24
Finished Aug 19 04:26:26 PM PDT 24
Peak memory 193364 kb
Host smart-c2d63268-1927-472c-92d3-1fc645910c2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024773233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4024773233
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1767735948
Short name T403
Test name
Test status
Simulation time 725073862 ps
CPU time 0.84 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 197080 kb
Host smart-42b98c27-cf15-4982-bece-847e5c12a251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767735948 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1767735948
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3943331634
Short name T411
Test name
Test status
Simulation time 324307648 ps
CPU time 0.62 seconds
Started Aug 19 04:25:58 PM PDT 24
Finished Aug 19 04:25:58 PM PDT 24
Peak memory 192960 kb
Host smart-3c8f8166-5869-4193-8896-4ac6281b79fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943331634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3943331634
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2946557133
Short name T391
Test name
Test status
Simulation time 496927476 ps
CPU time 0.71 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:17 PM PDT 24
Peak memory 183672 kb
Host smart-148e3fc1-d90e-450e-9171-6ed8a2fd4134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946557133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2946557133
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.223855355
Short name T331
Test name
Test status
Simulation time 321792300 ps
CPU time 0.66 seconds
Started Aug 19 04:26:27 PM PDT 24
Finished Aug 19 04:26:28 PM PDT 24
Peak memory 183592 kb
Host smart-bd365211-abd4-458d-8c00-8f5b1affa6f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223855355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.223855355
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2800116448
Short name T366
Test name
Test status
Simulation time 471938408 ps
CPU time 0.62 seconds
Started Aug 19 04:26:00 PM PDT 24
Finished Aug 19 04:26:01 PM PDT 24
Peak memory 183588 kb
Host smart-151409cb-d8f2-40c9-89f5-94bc9044de4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800116448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2800116448
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2045521718
Short name T332
Test name
Test status
Simulation time 2570908508 ps
CPU time 3.58 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:25 PM PDT 24
Peak memory 195080 kb
Host smart-6b0631d3-554e-4737-b8a5-2bb9d87ebf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045521718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2045521718
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2477880077
Short name T420
Test name
Test status
Simulation time 300433980 ps
CPU time 1.11 seconds
Started Aug 19 04:26:12 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 198320 kb
Host smart-77fdd8fd-3630-426e-9e09-580bc5bd09a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477880077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2477880077
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2527915728
Short name T188
Test name
Test status
Simulation time 8545140078 ps
CPU time 4.38 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:18 PM PDT 24
Peak memory 198260 kb
Host smart-f5f24383-c5eb-437f-a3b0-25be9bdcecf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527915728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2527915728
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.890041914
Short name T359
Test name
Test status
Simulation time 483315504 ps
CPU time 0.54 seconds
Started Aug 19 04:26:37 PM PDT 24
Finished Aug 19 04:26:38 PM PDT 24
Peak memory 183636 kb
Host smart-640d214d-dc10-417a-80e2-f6813bfb85ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890041914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.890041914
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1768067048
Short name T395
Test name
Test status
Simulation time 332899399 ps
CPU time 0.61 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 183688 kb
Host smart-9e42b48e-04c6-41c2-b5ec-8f4968a7335f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768067048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1768067048
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4123790101
Short name T377
Test name
Test status
Simulation time 454138084 ps
CPU time 0.86 seconds
Started Aug 19 04:26:55 PM PDT 24
Finished Aug 19 04:26:56 PM PDT 24
Peak memory 183696 kb
Host smart-1a8cefe6-83b6-4c84-9d98-d679bd00a5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123790101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4123790101
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2605175470
Short name T374
Test name
Test status
Simulation time 275968664 ps
CPU time 0.94 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 192908 kb
Host smart-2944de9a-14d4-4be6-9104-3afb7bb25986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605175470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2605175470
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2638715148
Short name T399
Test name
Test status
Simulation time 519023176 ps
CPU time 0.59 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 183684 kb
Host smart-9c34b5a9-4d54-4488-aac6-c547ebc9874e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638715148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2638715148
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1650208996
Short name T296
Test name
Test status
Simulation time 335214650 ps
CPU time 0.65 seconds
Started Aug 19 04:26:27 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 183684 kb
Host smart-c78bcb39-a304-4b5e-baf7-f1a15b068409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650208996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1650208996
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1553635650
Short name T281
Test name
Test status
Simulation time 460299670 ps
CPU time 1.11 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 193008 kb
Host smart-f9b591d5-d426-404a-b95b-585c26daa8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553635650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1553635650
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3000882081
Short name T415
Test name
Test status
Simulation time 413442801 ps
CPU time 1.06 seconds
Started Aug 19 04:26:29 PM PDT 24
Finished Aug 19 04:26:30 PM PDT 24
Peak memory 193000 kb
Host smart-4dfb2510-f5c1-49d1-8ced-6d95f69b12c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000882081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3000882081
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2682509205
Short name T310
Test name
Test status
Simulation time 391393046 ps
CPU time 0.61 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 183788 kb
Host smart-b8e0ca3f-915a-4b19-b7de-254961e3fcb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682509205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2682509205
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1114854728
Short name T299
Test name
Test status
Simulation time 446376447 ps
CPU time 0.87 seconds
Started Aug 19 04:26:23 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 192868 kb
Host smart-9f277fef-6378-491c-8d9e-16b952478b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114854728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1114854728
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1267647454
Short name T329
Test name
Test status
Simulation time 561967740 ps
CPU time 1.43 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 196556 kb
Host smart-c7ebd5c6-5de5-42d0-80bc-a1cec7474e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267647454 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1267647454
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3515446531
Short name T356
Test name
Test status
Simulation time 370759421 ps
CPU time 0.71 seconds
Started Aug 19 04:26:01 PM PDT 24
Finished Aug 19 04:26:01 PM PDT 24
Peak memory 192952 kb
Host smart-9d5d9d57-f0a5-4102-9bf9-9dd1549e977b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515446531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3515446531
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2527522931
Short name T290
Test name
Test status
Simulation time 279199577 ps
CPU time 0.79 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 183676 kb
Host smart-a283ae42-24ce-4140-b1d5-281c8449ad2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527522931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2527522931
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2905830449
Short name T384
Test name
Test status
Simulation time 1311384518 ps
CPU time 1.02 seconds
Started Aug 19 04:26:22 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 193412 kb
Host smart-9b101839-132a-4001-aed2-cbf0697c13bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905830449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2905830449
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.387924335
Short name T328
Test name
Test status
Simulation time 871542753 ps
CPU time 2.12 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 198536 kb
Host smart-f6644c6f-9089-4268-acb0-d4cd45e7e7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387924335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.387924335
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.459426373
Short name T400
Test name
Test status
Simulation time 4326475520 ps
CPU time 7.07 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 197820 kb
Host smart-999faaab-43a0-430c-baa3-6abf936a3af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459426373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.459426373
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.328212797
Short name T319
Test name
Test status
Simulation time 508884580 ps
CPU time 1.02 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 196004 kb
Host smart-e699107f-09b5-4f1a-ba5e-a217e662934e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328212797 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.328212797
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1596281525
Short name T57
Test name
Test status
Simulation time 354095474 ps
CPU time 0.68 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 192032 kb
Host smart-b85ae959-c298-4726-adab-5e2d4bade2b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596281525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1596281525
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2716678474
Short name T323
Test name
Test status
Simulation time 345813947 ps
CPU time 1.04 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 183672 kb
Host smart-bbf9474e-f68e-4786-bcc2-07afae2356d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716678474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2716678474
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4232951664
Short name T414
Test name
Test status
Simulation time 1532821357 ps
CPU time 3.6 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 192964 kb
Host smart-6a9ef883-4e2b-4414-995a-b394819b6844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232951664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4232951664
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2931978586
Short name T353
Test name
Test status
Simulation time 510398758 ps
CPU time 2.16 seconds
Started Aug 19 04:26:04 PM PDT 24
Finished Aug 19 04:26:07 PM PDT 24
Peak memory 198540 kb
Host smart-a888d3fc-a5e3-4e61-9e2a-62035f4ae170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931978586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2931978586
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4004552412
Short name T316
Test name
Test status
Simulation time 4229976438 ps
CPU time 5.37 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 197556 kb
Host smart-23a913bb-537b-4dce-b4b5-78f60ae92635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004552412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4004552412
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1354425951
Short name T390
Test name
Test status
Simulation time 549520830 ps
CPU time 1.02 seconds
Started Aug 19 04:26:14 PM PDT 24
Finished Aug 19 04:26:15 PM PDT 24
Peak memory 198372 kb
Host smart-00835b03-5a52-4529-8d59-cf60e9618bb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354425951 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1354425951
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1236597960
Short name T364
Test name
Test status
Simulation time 427319123 ps
CPU time 1.16 seconds
Started Aug 19 04:26:21 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 192016 kb
Host smart-08586a19-b442-4a3d-bbd9-67d56b1397a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236597960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1236597960
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1059121914
Short name T354
Test name
Test status
Simulation time 321360926 ps
CPU time 0.66 seconds
Started Aug 19 04:26:17 PM PDT 24
Finished Aug 19 04:26:23 PM PDT 24
Peak memory 183564 kb
Host smart-944772e7-09de-4a98-ad05-cd27def059ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059121914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1059121914
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1466731548
Short name T392
Test name
Test status
Simulation time 1508342003 ps
CPU time 1.54 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 193584 kb
Host smart-0d1e4417-681c-4bdf-8c87-52a18b6668f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466731548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1466731548
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.548607503
Short name T300
Test name
Test status
Simulation time 540586424 ps
CPU time 1.23 seconds
Started Aug 19 04:26:18 PM PDT 24
Finished Aug 19 04:26:21 PM PDT 24
Peak memory 198684 kb
Host smart-5d51551b-ceda-4675-858b-faed3c7be453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548607503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.548607503
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3346281802
Short name T340
Test name
Test status
Simulation time 4146406144 ps
CPU time 4.15 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:24 PM PDT 24
Peak memory 197568 kb
Host smart-333b3106-6295-4819-9291-802f92bfb626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346281802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3346281802
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3699697724
Short name T306
Test name
Test status
Simulation time 306578668 ps
CPU time 0.82 seconds
Started Aug 19 04:26:07 PM PDT 24
Finished Aug 19 04:26:08 PM PDT 24
Peak memory 195964 kb
Host smart-e285c2ac-5192-444c-b8ee-7462a3616212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699697724 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3699697724
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2445702844
Short name T385
Test name
Test status
Simulation time 455535141 ps
CPU time 0.75 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:20 PM PDT 24
Peak memory 192912 kb
Host smart-b7e0ed83-de78-4465-9af7-571c51d10696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445702844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2445702844
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1338598669
Short name T325
Test name
Test status
Simulation time 411584297 ps
CPU time 1.1 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:19 PM PDT 24
Peak memory 192896 kb
Host smart-f9d1321e-4908-4c31-9daa-eea5af99f81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338598669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1338598669
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3687358626
Short name T373
Test name
Test status
Simulation time 1519155659 ps
CPU time 1 seconds
Started Aug 19 04:26:13 PM PDT 24
Finished Aug 19 04:26:14 PM PDT 24
Peak memory 193768 kb
Host smart-ea9f8c7f-2424-4adf-8710-a1fbd256dd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687358626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3687358626
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3358509727
Short name T360
Test name
Test status
Simulation time 435126823 ps
CPU time 1.27 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:12 PM PDT 24
Peak memory 198316 kb
Host smart-f4841f6b-fe3b-4fe0-a75d-ca2ebc606409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358509727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3358509727
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.89365309
Short name T345
Test name
Test status
Simulation time 4610068178 ps
CPU time 6.96 seconds
Started Aug 19 04:26:19 PM PDT 24
Finished Aug 19 04:26:27 PM PDT 24
Peak memory 197856 kb
Host smart-def2aa98-bb1e-4cfd-a1ff-0a4444729b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89365309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_i
ntg_err.89365309
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.746019510
Short name T313
Test name
Test status
Simulation time 569458175 ps
CPU time 0.84 seconds
Started Aug 19 04:26:16 PM PDT 24
Finished Aug 19 04:26:16 PM PDT 24
Peak memory 197308 kb
Host smart-78181e3a-8c35-41bf-846f-f9553f77d5fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746019510 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.746019510
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3631597976
Short name T74
Test name
Test status
Simulation time 508222434 ps
CPU time 0.76 seconds
Started Aug 19 04:26:10 PM PDT 24
Finished Aug 19 04:26:11 PM PDT 24
Peak memory 193936 kb
Host smart-ac19960f-5f8b-49e5-9a23-06e50c812d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631597976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3631597976
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.314897045
Short name T283
Test name
Test status
Simulation time 522989441 ps
CPU time 0.92 seconds
Started Aug 19 04:26:07 PM PDT 24
Finished Aug 19 04:26:08 PM PDT 24
Peak memory 183632 kb
Host smart-6ff54799-3315-438a-bc46-a52ffc59f4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314897045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.314897045
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3299056099
Short name T419
Test name
Test status
Simulation time 2600770673 ps
CPU time 1.06 seconds
Started Aug 19 04:26:09 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 195136 kb
Host smart-ee9dfd66-d2f8-4953-a4d5-6918b89d9560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299056099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3299056099
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4234418372
Short name T376
Test name
Test status
Simulation time 367094211 ps
CPU time 2.57 seconds
Started Aug 19 04:26:07 PM PDT 24
Finished Aug 19 04:26:10 PM PDT 24
Peak memory 198496 kb
Host smart-ebf0a2d0-3a5d-484b-b2d2-2b09fa028f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234418372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4234418372
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3663084452
Short name T321
Test name
Test status
Simulation time 4902631150 ps
CPU time 2.52 seconds
Started Aug 19 04:26:20 PM PDT 24
Finished Aug 19 04:26:22 PM PDT 24
Peak memory 197796 kb
Host smart-13703d47-1b1a-44c5-9e9d-de99012f2214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663084452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3663084452
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2370165619
Short name T229
Test name
Test status
Simulation time 36153231210 ps
CPU time 51.12 seconds
Started Aug 19 04:27:35 PM PDT 24
Finished Aug 19 04:28:26 PM PDT 24
Peak memory 192176 kb
Host smart-7707d3bd-a673-4797-9b75-802c55140358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370165619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2370165619
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.532359393
Short name T217
Test name
Test status
Simulation time 443716871 ps
CPU time 1.35 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:34 PM PDT 24
Peak memory 192120 kb
Host smart-6e0258dc-1816-4ea5-9530-fc097e46cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532359393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.532359393
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2802421000
Short name T267
Test name
Test status
Simulation time 38575485349 ps
CPU time 45.52 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:28:34 PM PDT 24
Peak memory 192100 kb
Host smart-33bd058f-8adc-4a1a-bd61-7c43b3bb7de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802421000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2802421000
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1054209533
Short name T22
Test name
Test status
Simulation time 7579309564 ps
CPU time 3.57 seconds
Started Aug 19 04:27:32 PM PDT 24
Finished Aug 19 04:27:36 PM PDT 24
Peak memory 216228 kb
Host smart-53fcc06e-9e2a-4de2-9048-7d606e50f598
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054209533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1054209533
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.192484999
Short name T250
Test name
Test status
Simulation time 581781314 ps
CPU time 0.82 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:48 PM PDT 24
Peak memory 192120 kb
Host smart-bf041afb-7b39-4b65-83f3-a33b20073ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192484999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.192484999
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1344465153
Short name T275
Test name
Test status
Simulation time 16239462560 ps
CPU time 12.59 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:56 PM PDT 24
Peak memory 192100 kb
Host smart-7dcefa9d-8df9-4085-a74e-ea03aa05eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344465153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1344465153
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2858778523
Short name T237
Test name
Test status
Simulation time 395475334 ps
CPU time 0.83 seconds
Started Aug 19 04:27:28 PM PDT 24
Finished Aug 19 04:27:29 PM PDT 24
Peak memory 192024 kb
Host smart-df6284b8-c7d8-430b-8958-a0410dc12594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858778523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2858778523
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1611404753
Short name T7
Test name
Test status
Simulation time 3417814790 ps
CPU time 5.84 seconds
Started Aug 19 04:27:33 PM PDT 24
Finished Aug 19 04:27:39 PM PDT 24
Peak memory 196908 kb
Host smart-b3546283-4b48-42c6-94d9-9baa4cab3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611404753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1611404753
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3675590014
Short name T197
Test name
Test status
Simulation time 465504844 ps
CPU time 0.71 seconds
Started Aug 19 04:27:21 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 196872 kb
Host smart-3f095b46-4766-4774-ba82-553a6a2b106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675590014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3675590014
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2825805895
Short name T84
Test name
Test status
Simulation time 35279002224 ps
CPU time 22.11 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 192120 kb
Host smart-2ed19444-5ed1-4d82-9db9-515cd6f7b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825805895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2825805895
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3509947240
Short name T72
Test name
Test status
Simulation time 453145398 ps
CPU time 0.82 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 196964 kb
Host smart-02d9b788-bbec-4e1f-95a2-a200c557d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509947240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3509947240
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3531558710
Short name T202
Test name
Test status
Simulation time 26004180264 ps
CPU time 17.73 seconds
Started Aug 19 04:27:41 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 197096 kb
Host smart-0e74b638-b097-40b7-bd7d-717bab035916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531558710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3531558710
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.456107737
Short name T259
Test name
Test status
Simulation time 666780854 ps
CPU time 0.67 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:27:42 PM PDT 24
Peak memory 192116 kb
Host smart-34e0ef56-a9c0-4df7-96d3-c0e110db647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456107737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.456107737
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3401068651
Short name T230
Test name
Test status
Simulation time 25859133362 ps
CPU time 42.45 seconds
Started Aug 19 04:27:27 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 192108 kb
Host smart-500e5c31-6cc5-45bf-a9f0-4ae07eff3eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401068651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3401068651
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3497248972
Short name T15
Test name
Test status
Simulation time 588753169 ps
CPU time 1.29 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 192044 kb
Host smart-76a19347-a82e-4c95-a705-3c8c23203259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497248972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3497248972
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3971534165
Short name T211
Test name
Test status
Simulation time 25521695938 ps
CPU time 38.83 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:28:23 PM PDT 24
Peak memory 197156 kb
Host smart-3917ba85-cfbc-4c96-9932-d5d19bf99333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971534165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3971534165
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3001606191
Short name T201
Test name
Test status
Simulation time 591393771 ps
CPU time 0.75 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 191984 kb
Host smart-f7930951-4de0-47ca-82dd-997d2ba70758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001606191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3001606191
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2088257781
Short name T262
Test name
Test status
Simulation time 46656645157 ps
CPU time 3.64 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:43 PM PDT 24
Peak memory 197088 kb
Host smart-59723d17-e928-4f9e-ab36-b8fc9e9c3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088257781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2088257781
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.684294956
Short name T85
Test name
Test status
Simulation time 545148224 ps
CPU time 0.93 seconds
Started Aug 19 04:27:52 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 192124 kb
Host smart-1a9eb8c0-9950-442f-90bd-25d10c54bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684294956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.684294956
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2309475252
Short name T176
Test name
Test status
Simulation time 453757970 ps
CPU time 1.17 seconds
Started Aug 19 04:27:34 PM PDT 24
Finished Aug 19 04:27:35 PM PDT 24
Peak memory 196796 kb
Host smart-ee26c6fe-92a0-408e-abea-159700193afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309475252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2309475252
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.215239484
Short name T239
Test name
Test status
Simulation time 3559779811 ps
CPU time 5.64 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 196976 kb
Host smart-b1d1162e-9c34-493d-ba91-8b35712560d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215239484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.215239484
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.414150531
Short name T68
Test name
Test status
Simulation time 522408800 ps
CPU time 0.91 seconds
Started Aug 19 04:27:40 PM PDT 24
Finished Aug 19 04:27:41 PM PDT 24
Peak memory 192028 kb
Host smart-8e0eeb1e-3763-46f3-a804-7ae947e08e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414150531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.414150531
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3114813354
Short name T44
Test name
Test status
Simulation time 12795523939 ps
CPU time 8.54 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 192104 kb
Host smart-5cbf0c22-3be6-4237-b646-a0b1224028eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114813354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3114813354
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1256531374
Short name T204
Test name
Test status
Simulation time 492547125 ps
CPU time 0.73 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 192036 kb
Host smart-c2556414-95b5-48f3-9142-2ff23f2fe062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256531374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1256531374
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4160793526
Short name T266
Test name
Test status
Simulation time 10327541812 ps
CPU time 4.46 seconds
Started Aug 19 04:27:41 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 197092 kb
Host smart-85c598ed-9b2f-416b-b3ac-4cca8e86f28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160793526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4160793526
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.105915502
Short name T256
Test name
Test status
Simulation time 478030252 ps
CPU time 1.16 seconds
Started Aug 19 04:27:34 PM PDT 24
Finished Aug 19 04:27:35 PM PDT 24
Peak memory 192032 kb
Host smart-b7c4f1b5-9478-47f9-b7c2-f9e246720b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105915502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.105915502
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1210998420
Short name T232
Test name
Test status
Simulation time 1966772001 ps
CPU time 3.13 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 192088 kb
Host smart-8269be74-791e-450c-8070-4636246683c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210998420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1210998420
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4123493404
Short name T24
Test name
Test status
Simulation time 8464849555 ps
CPU time 6.78 seconds
Started Aug 19 04:27:27 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 216180 kb
Host smart-d93dbad0-e24b-46a6-93e0-936b464b11bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123493404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4123493404
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1067872378
Short name T224
Test name
Test status
Simulation time 323261191 ps
CPU time 1 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:38 PM PDT 24
Peak memory 196968 kb
Host smart-a901c1d6-7ec5-49f6-b4e0-df5fc353588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067872378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1067872378
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2154402097
Short name T171
Test name
Test status
Simulation time 11352050345 ps
CPU time 38.63 seconds
Started Aug 19 04:27:26 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 206908 kb
Host smart-3be95690-4d01-4777-bfc0-240958fcc497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154402097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2154402097
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1852347939
Short name T158
Test name
Test status
Simulation time 531901963 ps
CPU time 0.95 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:27:43 PM PDT 24
Peak memory 196960 kb
Host smart-63d11ef9-48b7-47ed-b565-a0c7adb7dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852347939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1852347939
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3600351787
Short name T219
Test name
Test status
Simulation time 34803527089 ps
CPU time 14.29 seconds
Started Aug 19 04:27:38 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 192100 kb
Host smart-04e859fd-4bed-4fac-bd5b-ced908f2c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600351787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3600351787
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.745708085
Short name T12
Test name
Test status
Simulation time 464018048 ps
CPU time 1.27 seconds
Started Aug 19 04:27:28 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 196860 kb
Host smart-6f0581eb-ed91-4c2f-aafd-75300e23d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745708085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.745708085
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2548301136
Short name T271
Test name
Test status
Simulation time 36390969436 ps
CPU time 25.35 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 192096 kb
Host smart-0b80438e-7352-4653-abcf-fb1bc2729098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548301136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2548301136
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1641323821
Short name T276
Test name
Test status
Simulation time 487559034 ps
CPU time 0.95 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 192084 kb
Host smart-73f46224-645c-48f2-aa10-13fffbc405ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641323821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1641323821
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1397018262
Short name T268
Test name
Test status
Simulation time 59194546959 ps
CPU time 88.85 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:29:32 PM PDT 24
Peak memory 192112 kb
Host smart-61901fdf-b300-4618-981a-788454c489b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397018262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1397018262
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4037178386
Short name T196
Test name
Test status
Simulation time 498233074 ps
CPU time 0.92 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:27:43 PM PDT 24
Peak memory 192036 kb
Host smart-7db1de55-de2f-4836-a72e-c458b745d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037178386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4037178386
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1765908401
Short name T212
Test name
Test status
Simulation time 8463437018 ps
CPU time 6.28 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:53 PM PDT 24
Peak memory 192096 kb
Host smart-71aa486f-9b5a-4de6-af27-75dc43e06d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765908401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1765908401
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1540705818
Short name T247
Test name
Test status
Simulation time 708826851 ps
CPU time 0.67 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 196872 kb
Host smart-1ee32e55-3ac4-4346-a00b-944fc91dea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540705818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1540705818
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.267835476
Short name T213
Test name
Test status
Simulation time 11876322997 ps
CPU time 8.94 seconds
Started Aug 19 04:27:39 PM PDT 24
Finished Aug 19 04:27:48 PM PDT 24
Peak memory 197156 kb
Host smart-06faef3b-ee48-4116-a50a-b4587239cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267835476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.267835476
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1737688960
Short name T214
Test name
Test status
Simulation time 445241953 ps
CPU time 1.26 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 192124 kb
Host smart-7fbc8ba2-350e-4cff-bedb-72e0a70106f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737688960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1737688960
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1728373698
Short name T215
Test name
Test status
Simulation time 32782382719 ps
CPU time 22.73 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:28:06 PM PDT 24
Peak memory 197080 kb
Host smart-5957bf63-05a9-4af5-9e1d-e3a78283f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728373698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1728373698
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.851093841
Short name T274
Test name
Test status
Simulation time 481126682 ps
CPU time 1.34 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 196844 kb
Host smart-7fa95011-5454-44d7-ad5b-683ba666bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851093841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.851093841
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1021867527
Short name T191
Test name
Test status
Simulation time 20463885227 ps
CPU time 26.03 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:26 PM PDT 24
Peak memory 192100 kb
Host smart-56d4ebbf-f722-4079-9cdd-39d14e100869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021867527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1021867527
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2966820693
Short name T273
Test name
Test status
Simulation time 407593275 ps
CPU time 0.76 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 196924 kb
Host smart-b26417c2-8c64-437a-a55b-17bb0474912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966820693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2966820693
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4053679444
Short name T223
Test name
Test status
Simulation time 22630366003 ps
CPU time 9.14 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 192104 kb
Host smart-76ba441d-e17b-4f6d-8ad2-32ab0170a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053679444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4053679444
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1418808982
Short name T192
Test name
Test status
Simulation time 600246001 ps
CPU time 1.3 seconds
Started Aug 19 04:27:43 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 196940 kb
Host smart-ee993ade-642b-4a7c-a2cc-32d4138a69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418808982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1418808982
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.440956734
Short name T225
Test name
Test status
Simulation time 2305747207 ps
CPU time 11.15 seconds
Started Aug 19 04:27:51 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 214704 kb
Host smart-cb465a6c-e20e-4f8e-9eb2-ba76c95c55ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440956734 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.440956734
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.423731111
Short name T167
Test name
Test status
Simulation time 590188739 ps
CPU time 1.54 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 196836 kb
Host smart-a0a3de1a-e515-4b33-9de6-492247f6a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423731111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.423731111
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1568238167
Short name T254
Test name
Test status
Simulation time 38321302850 ps
CPU time 11.85 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 192112 kb
Host smart-8ac9b5e4-8cf7-4228-a5fc-afda1c6a6471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568238167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1568238167
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2863230986
Short name T5
Test name
Test status
Simulation time 529497118 ps
CPU time 1.28 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 192124 kb
Host smart-d5a6f694-ae1b-4ac5-a85b-349d6724834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863230986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2863230986
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2411665982
Short name T207
Test name
Test status
Simulation time 5441332191 ps
CPU time 7.89 seconds
Started Aug 19 04:27:47 PM PDT 24
Finished Aug 19 04:27:55 PM PDT 24
Peak memory 197092 kb
Host smart-0802bb36-9963-468f-ae6a-31d50053c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411665982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2411665982
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2227787595
Short name T200
Test name
Test status
Simulation time 582889021 ps
CPU time 1.33 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 196800 kb
Host smart-7aa605d6-852b-464d-8c94-a5dce1f3565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227787595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2227787595
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1517929832
Short name T226
Test name
Test status
Simulation time 46528203434 ps
CPU time 14.56 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:59 PM PDT 24
Peak memory 183904 kb
Host smart-682dff3a-5b7f-4c26-84a1-66d3ad0543ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517929832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1517929832
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.559991700
Short name T205
Test name
Test status
Simulation time 27482754128 ps
CPU time 18.75 seconds
Started Aug 19 04:27:19 PM PDT 24
Finished Aug 19 04:27:38 PM PDT 24
Peak memory 197096 kb
Host smart-321f1cbd-0539-45b3-aac2-1bcbb1a4e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559991700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.559991700
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1036423373
Short name T20
Test name
Test status
Simulation time 7735103583 ps
CPU time 13.32 seconds
Started Aug 19 04:27:36 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 216152 kb
Host smart-c233d7c9-fcff-4b9a-b447-503bf7246e69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036423373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1036423373
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3122459462
Short name T241
Test name
Test status
Simulation time 547240915 ps
CPU time 0.86 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:27:51 PM PDT 24
Peak memory 196868 kb
Host smart-eab20fd8-6d37-433d-b1e5-a3a811ef6aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122459462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3122459462
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1671130272
Short name T221
Test name
Test status
Simulation time 6108213294 ps
CPU time 17.46 seconds
Started Aug 19 04:27:13 PM PDT 24
Finished Aug 19 04:27:30 PM PDT 24
Peak memory 214220 kb
Host smart-cf33d47b-6523-4661-a2f5-a4bacc7dcc8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671130272 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1671130272
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1713299138
Short name T253
Test name
Test status
Simulation time 28822733913 ps
CPU time 20.44 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 192092 kb
Host smart-bd0b881b-696b-4ff2-a377-0c79047db820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713299138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1713299138
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2746356315
Short name T246
Test name
Test status
Simulation time 394034908 ps
CPU time 0.75 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 192024 kb
Host smart-9cee3e01-64d5-41a1-8c03-b314c12c3dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746356315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2746356315
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3192945129
Short name T184
Test name
Test status
Simulation time 515581085 ps
CPU time 0.72 seconds
Started Aug 19 04:27:45 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 196856 kb
Host smart-9bde69db-f6ce-45e3-a236-b3b65657fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192945129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3192945129
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3933445018
Short name T195
Test name
Test status
Simulation time 26854291328 ps
CPU time 44.57 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 192192 kb
Host smart-6a469ca7-7796-47e0-b7c9-a6e890b449c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933445018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3933445018
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2471517171
Short name T88
Test name
Test status
Simulation time 363383425 ps
CPU time 1.02 seconds
Started Aug 19 04:27:51 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 192120 kb
Host smart-54cfe491-1014-4467-a7ef-56228134e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471517171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2471517171
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1164495405
Short name T236
Test name
Test status
Simulation time 18442905549 ps
CPU time 7.77 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 197116 kb
Host smart-0d9d13b2-87f4-47f5-95fa-93d96257a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164495405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1164495405
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2696100974
Short name T251
Test name
Test status
Simulation time 389641816 ps
CPU time 0.77 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:01 PM PDT 24
Peak memory 192088 kb
Host smart-f089c592-c69c-48d5-981c-0b90160a0ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696100974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2696100974
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2268246119
Short name T235
Test name
Test status
Simulation time 49119574657 ps
CPU time 73.73 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:29:21 PM PDT 24
Peak memory 197100 kb
Host smart-f44e935d-981d-4f5d-80ee-8ec52a14153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268246119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2268246119
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.642409456
Short name T257
Test name
Test status
Simulation time 570990534 ps
CPU time 1.56 seconds
Started Aug 19 04:27:52 PM PDT 24
Finished Aug 19 04:27:54 PM PDT 24
Peak memory 196868 kb
Host smart-9479e6cc-b0be-4768-b871-47f58cfaf291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642409456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.642409456
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.596916897
Short name T231
Test name
Test status
Simulation time 259064951106 ps
CPU time 97.56 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:29:48 PM PDT 24
Peak memory 192192 kb
Host smart-80d2b180-cbfa-49c8-b1ee-ab68d21cc0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596916897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.596916897
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2716598582
Short name T244
Test name
Test status
Simulation time 56897607460 ps
CPU time 71.37 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 197068 kb
Host smart-868f86ef-fa33-4aa1-afcd-b53887dd34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716598582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2716598582
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3839175289
Short name T91
Test name
Test status
Simulation time 479772787 ps
CPU time 1.32 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:03 PM PDT 24
Peak memory 192120 kb
Host smart-0e02bd65-2ceb-4cd7-b141-e55ddd7ef1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839175289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3839175289
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1816416288
Short name T228
Test name
Test status
Simulation time 26357208107 ps
CPU time 10.64 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 197184 kb
Host smart-402caf9b-6808-4cff-8b5e-2cbd93aa3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816416288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1816416288
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.357631324
Short name T206
Test name
Test status
Simulation time 484630212 ps
CPU time 0.73 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 192120 kb
Host smart-37844813-215c-4d47-aaff-ea0dea85966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357631324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.357631324
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2468233514
Short name T189
Test name
Test status
Simulation time 10000058969 ps
CPU time 3.92 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 197120 kb
Host smart-8cc037bc-6636-439b-b653-28f4bc6d0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468233514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2468233514
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1568812539
Short name T218
Test name
Test status
Simulation time 468340441 ps
CPU time 0.87 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:49 PM PDT 24
Peak memory 192120 kb
Host smart-299cdf04-3bb0-423a-b055-a909d83dbc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568812539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1568812539
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1716043799
Short name T249
Test name
Test status
Simulation time 52666042479 ps
CPU time 20.96 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 192192 kb
Host smart-24751248-1a46-4a99-8e24-09087e4d62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716043799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1716043799
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3179309384
Short name T220
Test name
Test status
Simulation time 538438591 ps
CPU time 0.67 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:27:45 PM PDT 24
Peak memory 192120 kb
Host smart-59c9dcd5-152c-491c-86de-1705ee2a470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179309384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3179309384
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.169935296
Short name T227
Test name
Test status
Simulation time 15835546758 ps
CPU time 5.48 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:06 PM PDT 24
Peak memory 197148 kb
Host smart-4cf6110d-1d0d-40df-aa2a-21f913f17d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169935296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.169935296
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.291914457
Short name T203
Test name
Test status
Simulation time 465167767 ps
CPU time 0.68 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 192124 kb
Host smart-fbfdc119-ce25-467f-8fb9-e41ea510aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291914457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.291914457
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3470957485
Short name T272
Test name
Test status
Simulation time 7312641539 ps
CPU time 14.97 seconds
Started Aug 19 04:27:50 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 206980 kb
Host smart-266055c1-a04b-4cd6-a11a-2a592c8db8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470957485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3470957485
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2436045791
Short name T209
Test name
Test status
Simulation time 31290729118 ps
CPU time 44.98 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 192096 kb
Host smart-04cfef8c-d41f-4655-ab8d-55bffcf73f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436045791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2436045791
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1871288473
Short name T198
Test name
Test status
Simulation time 359025422 ps
CPU time 0.74 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 192124 kb
Host smart-b01d5b36-e971-4f2f-8199-fdd7bf6d094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871288473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1871288473
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4072553312
Short name T260
Test name
Test status
Simulation time 15307803976 ps
CPU time 13.14 seconds
Started Aug 19 04:27:32 PM PDT 24
Finished Aug 19 04:27:46 PM PDT 24
Peak memory 192096 kb
Host smart-6f090a53-4748-41c0-a143-420ea3ce45fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072553312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4072553312
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1659068807
Short name T21
Test name
Test status
Simulation time 4494608941 ps
CPU time 7.9 seconds
Started Aug 19 04:27:42 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 216220 kb
Host smart-852d84e8-6f01-4ff7-97b8-dede7cea2116
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659068807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1659068807
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2415831796
Short name T26
Test name
Test status
Simulation time 500162886 ps
CPU time 0.88 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 192040 kb
Host smart-95275d7a-5e84-4567-8057-5cac59917f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415831796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2415831796
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1484265799
Short name T81
Test name
Test status
Simulation time 2889742282 ps
CPU time 15.56 seconds
Started Aug 19 04:27:36 PM PDT 24
Finished Aug 19 04:27:52 PM PDT 24
Peak memory 206980 kb
Host smart-593b47d1-37bf-41ff-a0b1-78fba80ec03c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484265799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1484265799
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2365946028
Short name T1
Test name
Test status
Simulation time 54464085780 ps
CPU time 35.38 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 192096 kb
Host smart-ce312100-1c55-4607-9365-a91fe747bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365946028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2365946028
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2047788309
Short name T199
Test name
Test status
Simulation time 569926958 ps
CPU time 0.96 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 192088 kb
Host smart-e719b86d-e481-46d5-bd47-9100d5b6cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047788309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2047788309
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2413466046
Short name T240
Test name
Test status
Simulation time 8421893816 ps
CPU time 13.11 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:12 PM PDT 24
Peak memory 192104 kb
Host smart-93466cfe-6e67-4ae4-9844-0e171a6e41ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413466046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2413466046
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.192376624
Short name T208
Test name
Test status
Simulation time 489311306 ps
CPU time 1.29 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 192024 kb
Host smart-6af71ff5-30b6-429a-b63e-8e96608c19b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192376624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.192376624
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2132206035
Short name T8
Test name
Test status
Simulation time 61752994403 ps
CPU time 28.22 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 192196 kb
Host smart-8bd5ece6-41a2-4e9e-94ba-80e75e7dc66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132206035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2132206035
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2063922990
Short name T238
Test name
Test status
Simulation time 363574132 ps
CPU time 0.7 seconds
Started Aug 19 04:27:53 PM PDT 24
Finished Aug 19 04:27:54 PM PDT 24
Peak memory 192108 kb
Host smart-caad9194-9028-4ab6-84fe-9aeecff49cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063922990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2063922990
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.150281435
Short name T86
Test name
Test status
Simulation time 562808572 ps
CPU time 0.76 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 196908 kb
Host smart-2c69951d-1499-4e22-8ce3-eb44d9177a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150281435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.150281435
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3686727284
Short name T233
Test name
Test status
Simulation time 20359624589 ps
CPU time 7.82 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 197104 kb
Host smart-ad54f353-c732-4e71-85d4-f3c736209cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686727284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3686727284
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.278481740
Short name T157
Test name
Test status
Simulation time 391240450 ps
CPU time 1.12 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 196932 kb
Host smart-47e7b111-3858-459e-8ae3-adedf36a87cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278481740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.278481740
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.968437204
Short name T169
Test name
Test status
Simulation time 449330619 ps
CPU time 0.73 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 196828 kb
Host smart-6060df75-b74b-4a42-a216-f8ca1703b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968437204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.968437204
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1879663043
Short name T255
Test name
Test status
Simulation time 20221525588 ps
CPU time 29.63 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:25 PM PDT 24
Peak memory 192064 kb
Host smart-00b0d37b-b7ba-437c-9a62-233cd6c1c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879663043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1879663043
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3794009860
Short name T242
Test name
Test status
Simulation time 538046712 ps
CPU time 0.63 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:27:58 PM PDT 24
Peak memory 192048 kb
Host smart-86f4f1e7-bac3-4fcd-a400-bd7ed7acd386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794009860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3794009860
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.608878962
Short name T263
Test name
Test status
Simulation time 2005117836 ps
CPU time 15.91 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 206772 kb
Host smart-7342f5be-993c-4b3d-9277-ec0dda8e433f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608878962 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.608878962
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2629729243
Short name T234
Test name
Test status
Simulation time 11130290489 ps
CPU time 8.38 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:22 PM PDT 24
Peak memory 192200 kb
Host smart-28ccb42f-8b7d-4544-87b9-083aedba7823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629729243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2629729243
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1778040693
Short name T243
Test name
Test status
Simulation time 598502581 ps
CPU time 0.73 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 196908 kb
Host smart-46d55068-92a7-4df8-a318-2496fd28a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778040693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1778040693
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.522314710
Short name T265
Test name
Test status
Simulation time 1401775856 ps
CPU time 8.82 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 214188 kb
Host smart-c7e33867-e3ee-40d8-9096-7221c3ecd8c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522314710 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.522314710
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3762815880
Short name T165
Test name
Test status
Simulation time 591733625 ps
CPU time 0.8 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 196912 kb
Host smart-f4518e06-4ebe-4c6f-a0ab-7c35bab736c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762815880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3762815880
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2262467337
Short name T216
Test name
Test status
Simulation time 52880805640 ps
CPU time 17.42 seconds
Started Aug 19 04:28:44 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 197192 kb
Host smart-cec0b23d-e65c-4eed-a192-9aebdb6fecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262467337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2262467337
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1800120030
Short name T69
Test name
Test status
Simulation time 467417973 ps
CPU time 1.24 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 196956 kb
Host smart-b4155f99-54c5-4362-92f6-88c710581da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800120030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1800120030
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1277376331
Short name T258
Test name
Test status
Simulation time 41564097136 ps
CPU time 16.58 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 192100 kb
Host smart-338df6e8-c920-425c-b050-4c98e28e737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277376331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1277376331
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3794342523
Short name T193
Test name
Test status
Simulation time 350591055 ps
CPU time 1.05 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 192008 kb
Host smart-3135daf4-48ec-4743-a955-5abe805625f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794342523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3794342523
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1698096007
Short name T245
Test name
Test status
Simulation time 16813484608 ps
CPU time 12.84 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 197176 kb
Host smart-e8223698-5cc6-4d5d-b9ad-626ff8a679da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698096007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1698096007
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3483796484
Short name T210
Test name
Test status
Simulation time 471757430 ps
CPU time 1.28 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 192124 kb
Host smart-aac084f8-c460-4dcd-9ae3-452c042fff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483796484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3483796484
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3446143050
Short name T264
Test name
Test status
Simulation time 4608417402 ps
CPU time 2.26 seconds
Started Aug 19 04:28:02 PM PDT 24
Finished Aug 19 04:28:04 PM PDT 24
Peak memory 192064 kb
Host smart-b02a238a-7dfa-4d17-a81c-f051db914e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446143050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3446143050
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2777923383
Short name T194
Test name
Test status
Simulation time 512475597 ps
CPU time 0.71 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 192124 kb
Host smart-53b2a654-859e-4b8b-afb5-f5772a0795be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777923383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2777923383
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2341573202
Short name T248
Test name
Test status
Simulation time 27560222132 ps
CPU time 9.43 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 192116 kb
Host smart-bc02a9f4-cce0-49bb-b85a-a2d56573f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341573202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2341573202
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2543183060
Short name T261
Test name
Test status
Simulation time 657621237 ps
CPU time 0.68 seconds
Started Aug 19 04:27:49 PM PDT 24
Finished Aug 19 04:27:50 PM PDT 24
Peak memory 196944 kb
Host smart-e7ee056c-1c79-4c27-a327-f157ca7f7c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543183060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2543183060
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3685553009
Short name T270
Test name
Test status
Simulation time 36329337101 ps
CPU time 53.78 seconds
Started Aug 19 04:27:16 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 197176 kb
Host smart-a1d7bd37-f8ec-4e0e-8390-bae885058c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685553009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3685553009
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3668569732
Short name T71
Test name
Test status
Simulation time 604857561 ps
CPU time 1.07 seconds
Started Aug 19 04:27:32 PM PDT 24
Finished Aug 19 04:27:34 PM PDT 24
Peak memory 192040 kb
Host smart-1a2a2c71-d0e5-4b83-8c6c-158540ab46ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668569732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3668569732
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2041367080
Short name T190
Test name
Test status
Simulation time 17262738628 ps
CPU time 7.15 seconds
Started Aug 19 04:27:48 PM PDT 24
Finished Aug 19 04:27:55 PM PDT 24
Peak memory 197188 kb
Host smart-7ee546f3-ca1f-4050-b7f0-28c59937df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041367080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2041367080
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.5702868
Short name T252
Test name
Test status
Simulation time 590162682 ps
CPU time 1.44 seconds
Started Aug 19 04:27:20 PM PDT 24
Finished Aug 19 04:27:22 PM PDT 24
Peak memory 192056 kb
Host smart-3c900540-723f-4200-b3a2-f6f9c06e8f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5702868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.5702868
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2778207784
Short name T2
Test name
Test status
Simulation time 19246885462 ps
CPU time 26.48 seconds
Started Aug 19 04:27:44 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 197176 kb
Host smart-de986dcb-f72d-4daa-8265-73a1d4c1afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778207784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2778207784
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4004933015
Short name T269
Test name
Test status
Simulation time 427988058 ps
CPU time 0.71 seconds
Started Aug 19 04:27:37 PM PDT 24
Finished Aug 19 04:27:37 PM PDT 24
Peak memory 192024 kb
Host smart-64b2121c-e090-4bc4-9060-0f857edfbc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004933015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4004933015
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2687033836
Short name T90
Test name
Test status
Simulation time 54197538834 ps
CPU time 34.68 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:46 PM PDT 24
Peak memory 192108 kb
Host smart-a843962f-1428-4ade-a7ea-1a4b56aa3127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687033836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2687033836
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3271287925
Short name T222
Test name
Test status
Simulation time 413987357 ps
CPU time 1.19 seconds
Started Aug 19 04:27:30 PM PDT 24
Finished Aug 19 04:27:32 PM PDT 24
Peak memory 192112 kb
Host smart-3490174d-ec6c-4f1e-bf0b-59dfddd8cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271287925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3271287925
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%