Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 19592 1 T1 10 T3 11 T5 11
bark[1] 619 1 T2 14 T86 21 T130 23
bark[2] 343 1 T12 7 T16 21 T20 21
bark[3] 306 1 T121 63 T139 21 T126 21
bark[4] 467 1 T18 21 T86 21 T156 71
bark[5] 549 1 T38 81 T171 14 T86 21
bark[6] 204 1 T6 14 T105 21 T108 21
bark[7] 448 1 T16 127 T43 7 T188 14
bark[8] 268 1 T18 7 T39 5 T43 7
bark[9] 215 1 T18 21 T144 14 T92 21
bark[10] 294 1 T92 26 T172 21 T135 7
bark[11] 306 1 T51 14 T41 14 T131 30
bark[12] 467 1 T4 14 T8 14 T129 5
bark[13] 375 1 T13 21 T48 14 T21 31
bark[14] 589 1 T12 7 T25 14 T42 26
bark[15] 535 1 T136 14 T199 68 T86 21
bark[16] 164 1 T129 21 T145 21 T137 14
bark[17] 157 1 T38 21 T168 14 T41 21
bark[18] 186 1 T13 21 T38 64 T199 21
bark[19] 459 1 T39 21 T41 7 T29 151
bark[20] 149 1 T26 14 T146 7 T81 45
bark[21] 636 1 T39 74 T41 132 T177 14
bark[22] 215 1 T18 26 T88 21 T110 39
bark[23] 296 1 T13 21 T134 14 T90 21
bark[24] 200 1 T39 5 T41 7 T21 21
bark[25] 281 1 T38 7 T40 7 T129 113
bark[26] 156 1 T16 49 T41 21 T152 21
bark[27] 84 1 T46 14 T149 14 T100 21
bark[28] 475 1 T14 14 T151 14 T110 106
bark[29] 723 1 T42 21 T29 21 T146 21
bark[30] 336 1 T42 7 T80 14 T164 82
bark[31] 489 1 T12 7 T125 14 T156 42
bark_0 4468 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 18923 1 T1 9 T3 10 T5 10
bite[1] 251 1 T39 4 T21 21 T167 13
bite[2] 622 1 T29 150 T171 13 T146 21
bite[3] 50 1 T29 21 T129 4 T117 4
bite[4] 407 1 T6 13 T156 21 T100 47
bite[5] 124 1 T12 6 T156 39 T139 35
bite[6] 326 1 T13 21 T25 13 T41 21
bite[7] 237 1 T16 21 T132 13 T81 51
bite[8] 564 1 T130 42 T137 13 T108 39
bite[9] 449 1 T16 48 T38 21 T85 13
bite[10] 300 1 T86 21 T130 22 T156 21
bite[11] 582 1 T41 144 T188 13 T199 21
bite[12] 382 1 T168 13 T40 6 T41 6
bite[13] 674 1 T125 13 T128 13 T129 21
bite[14] 454 1 T18 26 T134 13 T146 42
bite[15] 136 1 T12 6 T42 25 T103 21
bite[16] 546 1 T18 21 T130 4 T156 157
bite[17] 191 1 T4 13 T48 13 T39 4
bite[18] 632 1 T16 25 T51 13 T21 21
bite[19] 329 1 T8 13 T18 6 T38 80
bite[20] 305 1 T12 6 T38 6 T28 25
bite[21] 420 1 T2 13 T14 13 T38 63
bite[22] 381 1 T13 21 T151 13 T86 42
bite[23] 316 1 T26 13 T144 13 T42 21
bite[24] 277 1 T13 21 T41 6 T177 13
bite[25] 191 1 T175 13 T86 21 T156 42
bite[26] 459 1 T39 21 T43 6 T158 13
bite[27] 394 1 T18 21 T43 6 T130 21
bite[28] 219 1 T46 13 T136 13 T199 67
bite[29] 202 1 T156 70 T105 43 T133 21
bite[30] 251 1 T156 55 T149 13 T103 21
bite[31] 507 1 T16 100 T39 73 T41 6
bite_0 4950 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30384 1 T1 17 T2 21 T3 18
auto[1] 4667 1 T5 7 T16 115 T78 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 565 1 T28 9 T39 78 T42 19
prescale[1] 348 1 T28 2 T200 9 T156 2
prescale[2] 370 1 T18 33 T28 19 T201 9
prescale[3] 182 1 T52 9 T28 2 T199 2
prescale[4] 545 1 T38 2 T41 114 T42 2
prescale[5] 718 1 T38 135 T28 98 T40 12
prescale[6] 168 1 T42 2 T20 28 T202 9
prescale[7] 538 1 T28 2 T40 58 T29 2
prescale[8] 300 1 T39 9 T118 19 T146 38
prescale[9] 455 1 T18 19 T38 67 T203 9
prescale[10] 377 1 T9 9 T16 9 T40 2
prescale[11] 498 1 T28 129 T40 2 T199 2
prescale[12] 285 1 T42 2 T20 32 T92 2
prescale[13] 327 1 T41 47 T42 61 T29 2
prescale[14] 409 1 T16 19 T204 9 T205 9
prescale[15] 341 1 T18 2 T38 2 T40 2
prescale[16] 332 1 T13 40 T199 98 T130 2
prescale[17] 315 1 T38 2 T40 2 T42 32
prescale[18] 817 1 T12 87 T16 26 T38 2
prescale[19] 381 1 T13 37 T16 40 T18 135
prescale[20] 360 1 T12 2 T16 19 T18 2
prescale[21] 182 1 T118 23 T146 2 T206 19
prescale[22] 585 1 T13 28 T50 9 T42 45
prescale[23] 359 1 T12 2 T28 2 T39 2
prescale[24] 275 1 T28 19 T20 19 T207 9
prescale[25] 753 1 T12 2 T13 19 T16 2
prescale[26] 427 1 T208 9 T47 9 T42 44
prescale[27] 373 1 T41 4 T42 2 T156 2
prescale[28] 288 1 T13 49 T49 9 T38 2
prescale[29] 608 1 T10 9 T16 181 T41 30
prescale[30] 287 1 T29 2 T199 9 T156 2
prescale[31] 456 1 T12 86 T18 64 T209 9
prescale_0 21827 1 T1 17 T2 21 T3 18


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23623 1 T1 17 T2 21 T3 9
auto[1] 11428 1 T3 9 T4 12 T5 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 35051 1 T1 17 T2 21 T3 18


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 19483 1 T1 12 T2 1 T3 13
wkup[1] 78 1 T83 21 T155 15 T166 21
wkup[2] 135 1 T16 21 T131 30 T92 21
wkup[3] 207 1 T39 6 T188 15 T111 21
wkup[4] 156 1 T38 21 T152 21 T190 15
wkup[5] 136 1 T21 21 T129 21 T88 26
wkup[6] 266 1 T12 21 T28 30 T134 15
wkup[7] 260 1 T39 21 T40 30 T86 21
wkup[8] 289 1 T8 15 T12 8 T18 21
wkup[9] 193 1 T42 21 T118 26 T179 21
wkup[10] 194 1 T86 21 T118 21 T146 47
wkup[11] 154 1 T29 21 T85 15 T146 21
wkup[12] 152 1 T16 21 T20 21 T90 21
wkup[13] 261 1 T38 21 T156 30 T179 21
wkup[14] 193 1 T14 15 T38 21 T28 21
wkup[15] 126 1 T130 24 T100 21 T82 30
wkup[16] 242 1 T16 30 T41 8 T92 21
wkup[17] 209 1 T18 26 T20 21 T191 15
wkup[18] 84 1 T199 6 T156 21 T92 21
wkup[19] 259 1 T12 21 T16 35 T38 8
wkup[20] 128 1 T136 15 T29 21 T100 26
wkup[21] 81 1 T46 15 T29 21 T170 15
wkup[22] 173 1 T12 35 T39 21 T42 21
wkup[23] 264 1 T18 21 T156 21 T129 21
wkup[24] 307 1 T41 21 T132 15 T167 26
wkup[25] 156 1 T4 15 T13 21 T41 21
wkup[26] 154 1 T13 21 T26 15 T29 15
wkup[27] 161 1 T28 21 T40 21 T29 21
wkup[28] 129 1 T129 15 T92 21 T103 21
wkup[29] 200 1 T6 15 T18 8 T42 15
wkup[30] 312 1 T38 21 T42 21 T43 21
wkup[31] 230 1 T146 15 T131 30 T84 21
wkup[32] 243 1 T28 21 T199 21 T156 21
wkup[33] 111 1 T28 30 T199 21 T21 21
wkup[34] 167 1 T48 15 T156 21 T100 21
wkup[35] 114 1 T39 6 T29 21 T177 15
wkup[36] 153 1 T41 14 T199 35 T94 15
wkup[37] 173 1 T38 26 T130 21 T146 21
wkup[38] 113 1 T12 21 T42 21 T146 8
wkup[39] 162 1 T41 42 T21 15 T92 21
wkup[40] 118 1 T38 21 T105 21 T133 21
wkup[41] 71 1 T40 8 T199 21 T96 21
wkup[42] 240 1 T2 15 T18 21 T41 21
wkup[43] 78 1 T18 21 T193 15 T96 21
wkup[44] 154 1 T16 21 T41 29 T29 26
wkup[45] 294 1 T16 26 T42 8 T129 6
wkup[46] 161 1 T16 21 T168 15 T21 21
wkup[47] 268 1 T12 8 T51 15 T29 21
wkup[48] 309 1 T12 26 T18 26 T39 21
wkup[49] 253 1 T16 15 T156 61 T145 21
wkup[50] 184 1 T12 21 T41 15 T43 8
wkup[51] 249 1 T38 15 T199 21 T156 21
wkup[52] 188 1 T99 21 T103 21 T147 21
wkup[53] 265 1 T125 15 T29 21 T187 15
wkup[54] 259 1 T43 8 T20 21 T171 15
wkup[55] 134 1 T16 21 T41 15 T29 21
wkup[56] 223 1 T12 8 T13 21 T99 21
wkup[57] 210 1 T18 15 T151 15 T41 21
wkup[58] 229 1 T13 21 T25 15 T42 21
wkup[59] 144 1 T144 15 T38 21 T40 15
wkup[60] 162 1 T137 15 T108 60 T142 21
wkup[61] 235 1 T12 42 T130 21 T156 21
wkup[62] 222 1 T39 21 T21 31 T86 35
wkup[63] 327 1 T175 15 T86 30 T128 15
wkup_0 3466 1 T1 5 T2 5 T3 5

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