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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.67 99.33 95.61 100.00 98.40 99.51 45.15


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T290 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.456414190 Aug 21 05:19:24 PM UTC 24 Aug 21 05:19:28 PM UTC 24 311935463 ps
T291 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.301786726 Aug 21 05:19:27 PM UTC 24 Aug 21 05:19:30 PM UTC 24 477784213 ps
T36 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2406748255 Aug 21 05:19:28 PM UTC 24 Aug 21 05:19:31 PM UTC 24 429756616 ps
T37 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1832849462 Aug 21 05:19:30 PM UTC 24 Aug 21 05:19:32 PM UTC 24 563804798 ps
T30 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4265103181 Aug 21 05:19:29 PM UTC 24 Aug 21 05:19:32 PM UTC 24 537413326 ps
T31 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2041687069 Aug 21 05:19:28 PM UTC 24 Aug 21 05:19:32 PM UTC 24 1059127347 ps
T292 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2165554396 Aug 21 05:19:30 PM UTC 24 Aug 21 05:19:34 PM UTC 24 848044005 ps
T32 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2758689337 Aug 21 05:19:29 PM UTC 24 Aug 21 05:19:34 PM UTC 24 1431475589 ps
T33 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1794086430 Aug 21 05:19:31 PM UTC 24 Aug 21 05:19:34 PM UTC 24 5077017478 ps
T293 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3112477773 Aug 21 05:19:32 PM UTC 24 Aug 21 05:19:34 PM UTC 24 519404468 ps
T34 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3992044741 Aug 21 05:19:24 PM UTC 24 Aug 21 05:19:34 PM UTC 24 4713865372 ps
T294 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1157147937 Aug 21 05:19:33 PM UTC 24 Aug 21 05:19:35 PM UTC 24 315335144 ps
T295 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1369992393 Aug 21 05:19:33 PM UTC 24 Aug 21 05:19:36 PM UTC 24 453118392 ps
T75 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1462164779 Aug 21 05:19:33 PM UTC 24 Aug 21 05:19:36 PM UTC 24 1319428970 ps
T69 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3753736804 Aug 21 05:19:35 PM UTC 24 Aug 21 05:19:37 PM UTC 24 475746956 ps
T76 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.724861098 Aug 21 05:19:35 PM UTC 24 Aug 21 05:19:37 PM UTC 24 443477676 ps
T77 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1972128759 Aug 21 05:19:29 PM UTC 24 Aug 21 05:19:38 PM UTC 24 13842755720 ps
T70 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2276986202 Aug 21 05:19:35 PM UTC 24 Aug 21 05:19:38 PM UTC 24 2528778050 ps
T296 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2025081243 Aug 21 05:19:36 PM UTC 24 Aug 21 05:19:38 PM UTC 24 349234850 ps
T297 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2757674764 Aug 21 05:19:36 PM UTC 24 Aug 21 05:19:38 PM UTC 24 388204712 ps
T298 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1703455488 Aug 21 05:19:36 PM UTC 24 Aug 21 05:19:38 PM UTC 24 489693455 ps
T299 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3376761376 Aug 21 05:19:36 PM UTC 24 Aug 21 05:19:38 PM UTC 24 424688274 ps
T53 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.112511475 Aug 21 05:19:35 PM UTC 24 Aug 21 05:19:39 PM UTC 24 732248017 ps
T300 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1204527232 Aug 21 05:19:37 PM UTC 24 Aug 21 05:19:39 PM UTC 24 746666944 ps
T301 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.201848527 Aug 21 05:19:37 PM UTC 24 Aug 21 05:19:40 PM UTC 24 397335036 ps
T302 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.344902978 Aug 21 05:19:37 PM UTC 24 Aug 21 05:19:40 PM UTC 24 384675370 ps
T303 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1088963324 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:51 PM UTC 24 549687106 ps
T304 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.36964770 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:40 PM UTC 24 399786592 ps
T305 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2686291350 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:41 PM UTC 24 392890729 ps
T306 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3428571522 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:41 PM UTC 24 709760624 ps
T210 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.235927277 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:41 PM UTC 24 674269378 ps
T307 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2761262866 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:41 PM UTC 24 341795142 ps
T308 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.568712107 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:48 PM UTC 24 375400032 ps
T309 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1268256347 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:48 PM UTC 24 428283537 ps
T71 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4169222694 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:41 PM UTC 24 1210143696 ps
T35 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1097526521 Aug 21 05:19:36 PM UTC 24 Aug 21 05:19:42 PM UTC 24 8425922788 ps
T310 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2054552244 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:42 PM UTC 24 690254056 ps
T54 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2289128371 Aug 21 05:19:40 PM UTC 24 Aug 21 05:19:42 PM UTC 24 479604413 ps
T72 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3584693196 Aug 21 05:19:41 PM UTC 24 Aug 21 05:19:43 PM UTC 24 1568108206 ps
T311 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2217877670 Aug 21 05:19:41 PM UTC 24 Aug 21 05:19:43 PM UTC 24 463772947 ps
T312 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.970677867 Aug 21 05:19:40 PM UTC 24 Aug 21 05:19:43 PM UTC 24 1109178115 ps
T194 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3090447719 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:44 PM UTC 24 3929267313 ps
T313 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4003703444 Aug 21 05:19:41 PM UTC 24 Aug 21 05:19:44 PM UTC 24 360666868 ps
T55 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2041800401 Aug 21 05:19:41 PM UTC 24 Aug 21 05:19:44 PM UTC 24 462295302 ps
T56 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3605423443 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:45 PM UTC 24 361262202 ps
T314 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2171797024 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:45 PM UTC 24 461698976 ps
T315 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2683086112 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:45 PM UTC 24 267035211 ps
T316 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2848028559 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:45 PM UTC 24 384045614 ps
T317 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.766080743 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:45 PM UTC 24 431854662 ps
T57 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.667569041 Aug 21 05:19:38 PM UTC 24 Aug 21 05:19:45 PM UTC 24 3733130247 ps
T195 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1325883665 Aug 21 05:19:41 PM UTC 24 Aug 21 05:19:46 PM UTC 24 8486207490 ps
T58 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.882098792 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:46 PM UTC 24 1211543775 ps
T318 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2435728014 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:46 PM UTC 24 355225283 ps
T59 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.538678024 Aug 21 05:19:40 PM UTC 24 Aug 21 05:19:46 PM UTC 24 6782053463 ps
T319 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.4127135191 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:47 PM UTC 24 406309727 ps
T320 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.2107267246 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:47 PM UTC 24 296010142 ps
T73 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.336107051 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:47 PM UTC 24 1136644662 ps
T321 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2784949570 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:47 PM UTC 24 435395574 ps
T322 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.113436252 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:47 PM UTC 24 381472460 ps
T60 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1234720746 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:47 PM UTC 24 382114540 ps
T323 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.776170358 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:48 PM UTC 24 309159904 ps
T324 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.216655779 Aug 21 05:19:43 PM UTC 24 Aug 21 05:19:48 PM UTC 24 7503508694 ps
T325 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.2405311789 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:48 PM UTC 24 291182205 ps
T326 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3216935068 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:48 PM UTC 24 369217740 ps
T64 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4085645316 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:48 PM UTC 24 515885921 ps
T327 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.162777405 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:49 PM UTC 24 568579589 ps
T74 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.974423453 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:49 PM UTC 24 2860974956 ps
T328 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1722125711 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:49 PM UTC 24 852053546 ps
T329 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.25489629 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:50 PM UTC 24 365619903 ps
T196 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3191297808 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:50 PM UTC 24 8729799687 ps
T330 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3679235887 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:50 PM UTC 24 493284458 ps
T331 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3801038083 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:50 PM UTC 24 4658507524 ps
T332 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.346772232 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:50 PM UTC 24 519946422 ps
T333 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1406683198 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:50 PM UTC 24 353502957 ps
T334 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2508537974 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:50 PM UTC 24 503823812 ps
T335 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2174820438 Aug 21 05:19:46 PM UTC 24 Aug 21 05:19:51 PM UTC 24 1290518637 ps
T336 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3532927105 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:51 PM UTC 24 2819153496 ps
T337 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1226872079 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 2659310699 ps
T338 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.935225515 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 380968994 ps
T339 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2538649676 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 407499871 ps
T340 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2266884625 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 445171035 ps
T65 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.947937976 Aug 21 05:19:50 PM UTC 24 Aug 21 05:19:52 PM UTC 24 299864573 ps
T66 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3389073609 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 495436893 ps
T341 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3133927523 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 339805269 ps
T342 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.473450386 Aug 21 05:19:50 PM UTC 24 Aug 21 05:19:52 PM UTC 24 411214731 ps
T343 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1875104511 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:52 PM UTC 24 2103903244 ps
T344 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2058011247 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:52 PM UTC 24 401764679 ps
T345 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2939405769 Aug 21 05:19:50 PM UTC 24 Aug 21 05:19:53 PM UTC 24 2476425163 ps
T346 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2975323580 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:53 PM UTC 24 2647093313 ps
T347 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.698106010 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:53 PM UTC 24 366433186 ps
T348 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2342915762 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:53 PM UTC 24 471184260 ps
T349 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2673045489 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:53 PM UTC 24 445846171 ps
T350 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2632023956 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:53 PM UTC 24 642899036 ps
T351 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4262552704 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:53 PM UTC 24 587965570 ps
T197 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3959449110 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:54 PM UTC 24 8704632493 ps
T352 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2625041380 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:54 PM UTC 24 540202995 ps
T353 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4213182575 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 1181667496 ps
T61 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1591361563 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 618006437 ps
T354 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1507793421 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 475698822 ps
T355 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.2663653105 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 324053656 ps
T356 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3282867979 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:54 PM UTC 24 1512389041 ps
T357 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.3282268856 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 320719674 ps
T358 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2717755035 Aug 21 05:19:45 PM UTC 24 Aug 21 05:19:54 PM UTC 24 8144264850 ps
T359 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1503009868 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:54 PM UTC 24 327402510 ps
T360 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.698589916 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 338196691 ps
T361 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.1267388077 Aug 21 05:19:59 PM UTC 24 Aug 21 05:20:02 PM UTC 24 481854237 ps
T362 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.531098404 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:55 PM UTC 24 482540505 ps
T363 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2560291940 Aug 21 05:19:48 PM UTC 24 Aug 21 05:19:56 PM UTC 24 4085605190 ps
T62 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1205524993 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 345593254 ps
T364 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4143922966 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 470456639 ps
T365 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.4045491507 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 385380144 ps
T366 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3653758642 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 397964063 ps
T367 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.128175460 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 307705143 ps
T368 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.112973093 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:56 PM UTC 24 391246850 ps
T369 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1152459206 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:57 PM UTC 24 949976164 ps
T370 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1629479286 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:57 PM UTC 24 2531001247 ps
T371 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.656822793 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:57 PM UTC 24 467833179 ps
T372 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4274987176 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:57 PM UTC 24 4776904695 ps
T373 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3109541912 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:57 PM UTC 24 4452342536 ps
T67 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3190550555 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 430520639 ps
T374 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2702547985 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 1094514100 ps
T375 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.376152894 Aug 21 05:19:54 PM UTC 24 Aug 21 05:19:58 PM UTC 24 557194694 ps
T376 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2925448303 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 499572392 ps
T377 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3125769510 Aug 21 05:19:56 PM UTC 24 Aug 21 05:19:58 PM UTC 24 364816078 ps
T68 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2590276943 Aug 21 05:19:56 PM UTC 24 Aug 21 05:19:58 PM UTC 24 417097333 ps
T378 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2414443497 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 341048884 ps
T379 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1300996460 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 476195917 ps
T380 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.2249398646 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:58 PM UTC 24 519339035 ps
T381 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.528170114 Aug 21 05:19:51 PM UTC 24 Aug 21 05:19:59 PM UTC 24 4176732707 ps
T382 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2630676747 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:59 PM UTC 24 418916786 ps
T383 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2956272280 Aug 21 05:19:57 PM UTC 24 Aug 21 05:19:59 PM UTC 24 605085203 ps
T384 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.1251769106 Aug 21 05:19:57 PM UTC 24 Aug 21 05:19:59 PM UTC 24 418524777 ps
T385 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2628806026 Aug 21 05:19:57 PM UTC 24 Aug 21 05:19:59 PM UTC 24 503835176 ps
T63 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.909512603 Aug 21 05:19:57 PM UTC 24 Aug 21 05:19:59 PM UTC 24 296710424 ps
T386 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2039463736 Aug 21 05:19:56 PM UTC 24 Aug 21 05:19:59 PM UTC 24 2435688312 ps
T387 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.4110458279 Aug 21 05:19:55 PM UTC 24 Aug 21 05:19:59 PM UTC 24 497504944 ps
T198 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2689277836 Aug 21 05:19:52 PM UTC 24 Aug 21 05:19:59 PM UTC 24 8289318798 ps
T388 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3782911396 Aug 21 05:19:57 PM UTC 24 Aug 21 05:19:59 PM UTC 24 313194701 ps
T389 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3930419654 Aug 21 05:19:49 PM UTC 24 Aug 21 05:19:59 PM UTC 24 4546845462 ps
T390 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3246737594 Aug 21 05:19:57 PM UTC 24 Aug 21 05:20:00 PM UTC 24 483276912 ps
T391 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3649561254 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 424704898 ps
T392 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2176210491 Aug 21 05:19:57 PM UTC 24 Aug 21 05:20:00 PM UTC 24 2770100167 ps
T393 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2793625755 Aug 21 05:19:55 PM UTC 24 Aug 21 05:20:00 PM UTC 24 8736755003 ps
T394 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2495332255 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 350021539 ps
T395 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2663520727 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 495997153 ps
T396 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3080868365 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 518740038 ps
T397 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.946271406 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 491660960 ps
T398 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2290116350 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 358397874 ps
T399 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1706980520 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 398728897 ps
T400 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2096174073 Aug 21 05:19:58 PM UTC 24 Aug 21 05:20:00 PM UTC 24 299487112 ps
T401 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1163218012 Aug 21 05:19:55 PM UTC 24 Aug 21 05:20:00 PM UTC 24 4447755581 ps
T402 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1683135996 Aug 21 05:19:59 PM UTC 24 Aug 21 05:20:01 PM UTC 24 499748994 ps
T403 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.1272881611 Aug 21 05:19:59 PM UTC 24 Aug 21 05:20:02 PM UTC 24 542319617 ps
T404 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2675536559 Aug 21 05:19:59 PM UTC 24 Aug 21 05:20:02 PM UTC 24 503074537 ps
T405 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1635717049 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 336052553 ps
T406 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.378823366 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 406956841 ps
T407 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.1494557497 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 458606779 ps
T408 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2737067483 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 325161105 ps
T409 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2850917307 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 487524276 ps
T410 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.4279571208 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 505785090 ps
T411 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.3744101319 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 453087049 ps
T412 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.1907619906 Aug 21 05:20:00 PM UTC 24 Aug 21 05:20:02 PM UTC 24 490838436 ps
T413 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1358717788 Aug 21 05:19:57 PM UTC 24 Aug 21 05:20:03 PM UTC 24 9091378339 ps
T414 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.3559330350 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 356271486 ps
T415 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3706494111 Aug 21 05:19:55 PM UTC 24 Aug 21 05:20:03 PM UTC 24 2198453222 ps
T416 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3578439484 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 536231471 ps
T417 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2179704582 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 515621805 ps
T418 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.642617943 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 508483297 ps
T419 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1341267774 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 377736551 ps
T420 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.4012867222 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 379837086 ps
T421 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1535755256 Aug 21 05:20:01 PM UTC 24 Aug 21 05:20:03 PM UTC 24 493373556 ps
T422 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.874489456 Aug 21 05:19:52 PM UTC 24 Aug 21 05:20:04 PM UTC 24 8163131851 ps
T423 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.905885403 Aug 21 05:19:54 PM UTC 24 Aug 21 05:20:06 PM UTC 24 8180936635 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.4146915669
Short name T6
Test name
Test status
Simulation time 374246634 ps
CPU time 1.46 seconds
Started Aug 21 05:16:23 PM UTC 24
Finished Aug 21 05:16:25 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4146915669 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4146915669
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.2440558788
Short name T12
Test name
Test status
Simulation time 3271662435 ps
CPU time 10.94 seconds
Started Aug 21 05:17:24 PM UTC 24
Finished Aug 21 05:17:37 PM UTC 24
Peak memory 219516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2440558788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2440558788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.366755396
Short name T13
Test name
Test status
Simulation time 145263889440 ps
CPU time 24.63 seconds
Started Aug 21 05:16:09 PM UTC 24
Finished Aug 21 05:16:35 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366755396
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer
_stress_all.366755396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1794086430
Short name T33
Test name
Test status
Simulation time 5077017478 ps
CPU time 2.07 seconds
Started Aug 21 05:19:31 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 205628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=179408
6430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ao
n_timer_tl_intg_err.1794086430
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.73228248
Short name T156
Test name
Test status
Simulation time 18612718601 ps
CPU time 49.31 seconds
Started Aug 21 05:17:04 PM UTC 24
Finished Aug 21 05:17:55 PM UTC 24
Peak memory 218052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73228248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.73228248
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.112511475
Short name T53
Test name
Test status
Simulation time 732248017 ps
CPU time 2.96 seconds
Started Aug 21 05:19:35 PM UTC 24
Finished Aug 21 05:19:39 PM UTC 24
Peak memory 205592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112511475
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_csr_bit_bash.112511475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.4160572733
Short name T146
Test name
Test status
Simulation time 7854498013 ps
CPU time 30.57 seconds
Started Aug 21 05:17:38 PM UTC 24
Finished Aug 21 05:18:10 PM UTC 24
Peak memory 206472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4160572733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4160572733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.3986437958
Short name T112
Test name
Test status
Simulation time 19469339946 ps
CPU time 41.27 seconds
Started Aug 21 05:19:02 PM UTC 24
Finished Aug 21 05:19:44 PM UTC 24
Peak memory 206580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3986437958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3986437958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.855459675
Short name T86
Test name
Test status
Simulation time 135865855306 ps
CPU time 60.83 seconds
Started Aug 21 05:16:42 PM UTC 24
Finished Aug 21 05:17:44 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=855459675
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer
_stress_all.855459675
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3899128587
Short name T91
Test name
Test status
Simulation time 119888374698 ps
CPU time 77.83 seconds
Started Aug 21 05:19:15 PM UTC 24
Finished Aug 21 05:20:34 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899128587
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_tim
er_stress_all.3899128587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.3895747894
Short name T17
Test name
Test status
Simulation time 8261278823 ps
CPU time 19.12 seconds
Started Aug 21 05:16:14 PM UTC 24
Finished Aug 21 05:16:34 PM UTC 24
Peak memory 231220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3895747894 -as
sert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3895747894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1713531925
Short name T107
Test name
Test status
Simulation time 260989676245 ps
CPU time 534.61 seconds
Started Aug 21 05:16:52 PM UTC 24
Finished Aug 21 05:25:53 PM UTC 24
Peak memory 204072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713531925
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_time
r_stress_all.1713531925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.2852670361
Short name T103
Test name
Test status
Simulation time 72114223158 ps
CPU time 123.76 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:18:42 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2852670361
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_time
r_stress_all.2852670361
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3605932502
Short name T102
Test name
Test status
Simulation time 9626725029 ps
CPU time 49.18 seconds
Started Aug 21 05:19:13 PM UTC 24
Finished Aug 21 05:20:04 PM UTC 24
Peak memory 206632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3605932502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3605932502
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.4041607110
Short name T140
Test name
Test status
Simulation time 11148838293 ps
CPU time 26.1 seconds
Started Aug 21 05:18:57 PM UTC 24
Finished Aug 21 05:19:24 PM UTC 24
Peak memory 206644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4041607110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4041607110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2063726981
Short name T92
Test name
Test status
Simulation time 14050760309 ps
CPU time 36.1 seconds
Started Aug 21 05:17:49 PM UTC 24
Finished Aug 21 05:18:26 PM UTC 24
Peak memory 206668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2063726981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2063726981
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.2404929336
Short name T84
Test name
Test status
Simulation time 22929252683 ps
CPU time 51.64 seconds
Started Aug 21 05:18:16 PM UTC 24
Finished Aug 21 05:19:09 PM UTC 24
Peak memory 215376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2404929336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2404929336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.1084341550
Short name T18
Test name
Test status
Simulation time 15259891971 ps
CPU time 28.59 seconds
Started Aug 21 05:16:19 PM UTC 24
Finished Aug 21 05:16:49 PM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084341550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1084341550
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.4177275435
Short name T97
Test name
Test status
Simulation time 13420319455 ps
CPU time 22.4 seconds
Started Aug 21 05:19:11 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4177275435
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_tim
er_stress_all.4177275435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.3029601453
Short name T95
Test name
Test status
Simulation time 371117517718 ps
CPU time 503.11 seconds
Started Aug 21 05:16:59 PM UTC 24
Finished Aug 21 05:25:27 PM UTC 24
Peak memory 204076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3029601453
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_tim
er_stress_all.3029601453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.557361906
Short name T110
Test name
Test status
Simulation time 134099615159 ps
CPU time 35.99 seconds
Started Aug 21 05:18:17 PM UTC 24
Finished Aug 21 05:18:54 PM UTC 24
Peak memory 200712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557361906
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_time
r_stress_all.557361906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.1012637682
Short name T121
Test name
Test status
Simulation time 5328451442 ps
CPU time 11.75 seconds
Started Aug 21 05:18:56 PM UTC 24
Finished Aug 21 05:19:08 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1012637682
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_tim
er_stress_all.1012637682
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.553060377
Short name T123
Test name
Test status
Simulation time 200768829280 ps
CPU time 364.87 seconds
Started Aug 21 05:18:58 PM UTC 24
Finished Aug 21 05:25:07 PM UTC 24
Peak memory 200556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=553060377
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_time
r_stress_all.553060377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.4264124725
Short name T20
Test name
Test status
Simulation time 104788319484 ps
CPU time 38.32 seconds
Started Aug 21 05:16:47 PM UTC 24
Finished Aug 21 05:17:26 PM UTC 24
Peak memory 200432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4264124725
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_time
r_stress_all.4264124725
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.2821913719
Short name T108
Test name
Test status
Simulation time 262637608775 ps
CPU time 100.48 seconds
Started Aug 21 05:17:05 PM UTC 24
Finished Aug 21 05:18:47 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821913719
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_tim
er_stress_all.2821913719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.700530339
Short name T99
Test name
Test status
Simulation time 139475305851 ps
CPU time 115.49 seconds
Started Aug 21 05:16:32 PM UTC 24
Finished Aug 21 05:18:29 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=700530339
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer
_stress_all.700530339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.514589683
Short name T153
Test name
Test status
Simulation time 146153072023 ps
CPU time 254.85 seconds
Started Aug 21 05:17:18 PM UTC 24
Finished Aug 21 05:21:36 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=514589683
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_time
r_stress_all.514589683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1006608576
Short name T41
Test name
Test status
Simulation time 8188409915 ps
CPU time 22.76 seconds
Started Aug 21 05:16:59 PM UTC 24
Finished Aug 21 05:17:23 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1006608576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1006608576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.3538030371
Short name T21
Test name
Test status
Simulation time 20957629167 ps
CPU time 4.43 seconds
Started Aug 21 05:17:35 PM UTC 24
Finished Aug 21 05:17:40 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3538030371
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_tim
er_stress_all.3538030371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.399857978
Short name T113
Test name
Test status
Simulation time 199532489062 ps
CPU time 55.47 seconds
Started Aug 21 05:19:18 PM UTC 24
Finished Aug 21 05:20:15 PM UTC 24
Peak memory 200840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399857978
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_time
r_stress_all.399857978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.4198749880
Short name T29
Test name
Test status
Simulation time 9102381169 ps
CPU time 45.76 seconds
Started Aug 21 05:16:38 PM UTC 24
Finished Aug 21 05:17:26 PM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198749880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.4198749880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2840185394
Short name T4
Test name
Test status
Simulation time 544274402 ps
CPU time 2.76 seconds
Started Aug 21 05:16:19 PM UTC 24
Finished Aug 21 05:16:22 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2840185394 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2840185394
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.1287630327
Short name T16
Test name
Test status
Simulation time 4206042581 ps
CPU time 28.36 seconds
Started Aug 21 05:16:08 PM UTC 24
Finished Aug 21 05:16:38 PM UTC 24
Peak memory 206548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287630327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1287630327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.2113058273
Short name T93
Test name
Test status
Simulation time 529686407287 ps
CPU time 1030.88 seconds
Started Aug 21 05:16:56 PM UTC 24
Finished Aug 21 05:34:18 PM UTC 24
Peak memory 204148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2113058273
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_time
r_stress_all.2113058273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.323713354
Short name T106
Test name
Test status
Simulation time 167203134669 ps
CPU time 20.24 seconds
Started Aug 21 05:19:19 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 200904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=323713354
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_time
r_stress_all.323713354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.2232984692
Short name T127
Test name
Test status
Simulation time 54762297156 ps
CPU time 99.45 seconds
Started Aug 21 05:18:11 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2232984692
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_tim
er_stress_all.2232984692
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.312628915
Short name T101
Test name
Test status
Simulation time 13011732629 ps
CPU time 76.38 seconds
Started Aug 21 05:17:22 PM UTC 24
Finished Aug 21 05:18:40 PM UTC 24
Peak memory 218060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=312628915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.312628915
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.1669022746
Short name T141
Test name
Test status
Simulation time 171436700941 ps
CPU time 129.75 seconds
Started Aug 21 05:18:52 PM UTC 24
Finished Aug 21 05:21:04 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1669022746
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_tim
er_stress_all.1669022746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.1132333117
Short name T100
Test name
Test status
Simulation time 2199427992 ps
CPU time 14.23 seconds
Started Aug 21 05:17:55 PM UTC 24
Finished Aug 21 05:18:10 PM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132333117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1132333117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.1949757157
Short name T83
Test name
Test status
Simulation time 7615166998 ps
CPU time 13.99 seconds
Started Aug 21 05:18:51 PM UTC 24
Finished Aug 21 05:19:06 PM UTC 24
Peak memory 206644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949757157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1949757157
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1795000575
Short name T109
Test name
Test status
Simulation time 22157463880 ps
CPU time 35.16 seconds
Started Aug 21 05:19:11 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1795000575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1795000575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.3397222935
Short name T118
Test name
Test status
Simulation time 77260821108 ps
CPU time 38.62 seconds
Started Aug 21 05:18:15 PM UTC 24
Finished Aug 21 05:18:55 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397222935
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_tim
er_stress_all.3397222935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.1127679336
Short name T178
Test name
Test status
Simulation time 75648744851 ps
CPU time 37.32 seconds
Started Aug 21 05:19:08 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1127679336
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_tim
er_stress_all.1127679336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.556480273
Short name T42
Test name
Test status
Simulation time 25448455023 ps
CPU time 34.49 seconds
Started Aug 21 05:16:47 PM UTC 24
Finished Aug 21 05:17:23 PM UTC 24
Peak memory 219340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556480273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.556480273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.2974051601
Short name T38
Test name
Test status
Simulation time 25010515713 ps
CPU time 34.77 seconds
Started Aug 21 05:16:24 PM UTC 24
Finished Aug 21 05:17:01 PM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974051601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2974051601
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1384805942
Short name T126
Test name
Test status
Simulation time 73720273090 ps
CPU time 81.57 seconds
Started Aug 21 05:17:55 PM UTC 24
Finished Aug 21 05:19:18 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1384805942
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_tim
er_stress_all.1384805942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.1563054338
Short name T120
Test name
Test status
Simulation time 102205562110 ps
CPU time 163.49 seconds
Started Aug 21 05:18:32 PM UTC 24
Finished Aug 21 05:21:19 PM UTC 24
Peak memory 200612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1563054338
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_tim
er_stress_all.1563054338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.1011372794
Short name T96
Test name
Test status
Simulation time 91833803154 ps
CPU time 46.12 seconds
Started Aug 21 05:18:35 PM UTC 24
Finished Aug 21 05:19:23 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011372794
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_tim
er_stress_all.1011372794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.3043632137
Short name T89
Test name
Test status
Simulation time 128855218479 ps
CPU time 241.24 seconds
Started Aug 21 05:16:24 PM UTC 24
Finished Aug 21 05:20:29 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3043632137
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_time
r_stress_all.3043632137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.3497559224
Short name T154
Test name
Test status
Simulation time 54296091518 ps
CPU time 46.57 seconds
Started Aug 21 05:18:22 PM UTC 24
Finished Aug 21 05:19:10 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497559224
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_tim
er_stress_all.3497559224
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.656205032
Short name T82
Test name
Test status
Simulation time 12989161619 ps
CPU time 37.87 seconds
Started Aug 21 05:18:21 PM UTC 24
Finished Aug 21 05:19:01 PM UTC 24
Peak memory 218020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656205032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.656205032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3753736804
Short name T69
Test name
Test status
Simulation time 475746956 ps
CPU time 1.46 seconds
Started Aug 21 05:19:35 PM UTC 24
Finished Aug 21 05:19:37 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753736804 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_c
sr_rw.3753736804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.2685806541
Short name T105
Test name
Test status
Simulation time 59489215860 ps
CPU time 81.6 seconds
Started Aug 21 05:17:12 PM UTC 24
Finished Aug 21 05:18:35 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685806541
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_tim
er_stress_all.2685806541
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.3406620693
Short name T164
Test name
Test status
Simulation time 139686999230 ps
CPU time 105.17 seconds
Started Aug 21 05:17:31 PM UTC 24
Finished Aug 21 05:19:19 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3406620693
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_tim
er_stress_all.3406620693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.3026397091
Short name T114
Test name
Test status
Simulation time 184215036697 ps
CPU time 317.25 seconds
Started Aug 21 05:18:12 PM UTC 24
Finished Aug 21 05:23:34 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3026397091
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_tim
er_stress_all.3026397091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.871449776
Short name T139
Test name
Test status
Simulation time 58279324834 ps
CPU time 22.35 seconds
Started Aug 21 05:18:48 PM UTC 24
Finished Aug 21 05:19:12 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871449776
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_time
r_stress_all.871449776
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.1000657987
Short name T135
Test name
Test status
Simulation time 6398134103 ps
CPU time 15.17 seconds
Started Aug 21 05:19:07 PM UTC 24
Finished Aug 21 05:19:24 PM UTC 24
Peak memory 214832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000657987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1000657987
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2913970534
Short name T124
Test name
Test status
Simulation time 71568392779 ps
CPU time 22.09 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913970534
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_tim
er_stress_all.2913970534
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.947937976
Short name T65
Test name
Test status
Simulation time 299864573 ps
CPU time 1.13 seconds
Started Aug 21 05:19:50 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947937976 -asse
rt nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_c
sr_rw.947937976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2347249083
Short name T133
Test name
Test status
Simulation time 139613297922 ps
CPU time 48.94 seconds
Started Aug 21 05:18:05 PM UTC 24
Finished Aug 21 05:18:55 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347249083
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_tim
er_stress_all.2347249083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.2572053094
Short name T81
Test name
Test status
Simulation time 12389439245 ps
CPU time 34.67 seconds
Started Aug 21 05:18:14 PM UTC 24
Finished Aug 21 05:18:50 PM UTC 24
Peak memory 215568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572053094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2572053094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.224306554
Short name T104
Test name
Test status
Simulation time 92575128902 ps
CPU time 164.78 seconds
Started Aug 21 05:18:42 PM UTC 24
Finished Aug 21 05:21:29 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=224306554
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_time
r_stress_all.224306554
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3410043908
Short name T166
Test name
Test status
Simulation time 3602716620 ps
CPU time 32.96 seconds
Started Aug 21 05:19:05 PM UTC 24
Finished Aug 21 05:19:39 PM UTC 24
Peak memory 214476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410043908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3410043908
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.3857420875
Short name T130
Test name
Test status
Simulation time 4609361758 ps
CPU time 28.85 seconds
Started Aug 21 05:17:18 PM UTC 24
Finished Aug 21 05:17:48 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3857420875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3857420875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.1290909827
Short name T167
Test name
Test status
Simulation time 11865176634 ps
CPU time 38.67 seconds
Started Aug 21 05:17:35 PM UTC 24
Finished Aug 21 05:18:15 PM UTC 24
Peak memory 220200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1290909827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1290909827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.3975129902
Short name T122
Test name
Test status
Simulation time 93886026364 ps
CPU time 39.84 seconds
Started Aug 21 05:19:02 PM UTC 24
Finished Aug 21 05:19:43 PM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975129902
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_tim
er_stress_all.3975129902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.3316327453
Short name T98
Test name
Test status
Simulation time 254231663316 ps
CPU time 360.26 seconds
Started Aug 21 05:19:03 PM UTC 24
Finished Aug 21 05:25:08 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316327453
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_tim
er_stress_all.3316327453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.4092722781
Short name T179
Test name
Test status
Simulation time 67355683403 ps
CPU time 27.04 seconds
Started Aug 21 05:17:43 PM UTC 24
Finished Aug 21 05:18:11 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4092722781
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_tim
er_stress_all.4092722781
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.1793978274
Short name T174
Test name
Test status
Simulation time 446209318205 ps
CPU time 77.79 seconds
Started Aug 21 05:18:46 PM UTC 24
Finished Aug 21 05:20:06 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793978274
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_tim
er_stress_all.1793978274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3410060616
Short name T163
Test name
Test status
Simulation time 3579565968 ps
CPU time 18.86 seconds
Started Aug 21 05:19:03 PM UTC 24
Finished Aug 21 05:19:23 PM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410060616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3410060616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.920094568
Short name T26
Test name
Test status
Simulation time 423334008 ps
CPU time 1.22 seconds
Started Aug 21 05:16:37 PM UTC 24
Finished Aug 21 05:16:40 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=920094568 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.920094568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.4171906313
Short name T48
Test name
Test status
Simulation time 455560943 ps
CPU time 1.06 seconds
Started Aug 21 05:16:53 PM UTC 24
Finished Aug 21 05:16:56 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4171906313 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4171906313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.1351525064
Short name T136
Test name
Test status
Simulation time 560432013 ps
CPU time 1.51 seconds
Started Aug 21 05:17:20 PM UTC 24
Finished Aug 21 05:17:23 PM UTC 24
Peak memory 199628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1351525064 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1351525064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2624656929
Short name T85
Test name
Test status
Simulation time 571081067 ps
CPU time 2.4 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:17:31 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2624656929 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2624656929
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.2531825029
Short name T90
Test name
Test status
Simulation time 88258060501 ps
CPU time 50.06 seconds
Started Aug 21 05:17:38 PM UTC 24
Finished Aug 21 05:18:30 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2531825029
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_tim
er_stress_all.2531825029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.2334554241
Short name T149
Test name
Test status
Simulation time 593654743 ps
CPU time 1.27 seconds
Started Aug 21 05:18:00 PM UTC 24
Finished Aug 21 05:18:02 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2334554241 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2334554241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2202808070
Short name T150
Test name
Test status
Simulation time 101876173304 ps
CPU time 15.7 seconds
Started Aug 21 05:18:29 PM UTC 24
Finished Aug 21 05:18:46 PM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202808070
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_tim
er_stress_all.2202808070
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.588593777
Short name T80
Test name
Test status
Simulation time 1593612264 ps
CPU time 11.13 seconds
Started Aug 21 05:18:31 PM UTC 24
Finished Aug 21 05:18:44 PM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588593777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.588593777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.158613993
Short name T88
Test name
Test status
Simulation time 2448322136 ps
CPU time 8.25 seconds
Started Aug 21 05:18:37 PM UTC 24
Finished Aug 21 05:18:47 PM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=158613993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.158613993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.4145895059
Short name T142
Test name
Test status
Simulation time 1810802687 ps
CPU time 15.61 seconds
Started Aug 21 05:18:44 PM UTC 24
Finished Aug 21 05:19:01 PM UTC 24
Peak memory 217140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4145895059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4145895059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.3846400574
Short name T143
Test name
Test status
Simulation time 465525820 ps
CPU time 1.06 seconds
Started Aug 21 05:19:00 PM UTC 24
Finished Aug 21 05:19:02 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3846400574 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3846400574
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1287401428
Short name T148
Test name
Test status
Simulation time 38040401548 ps
CPU time 17.74 seconds
Started Aug 21 05:19:06 PM UTC 24
Finished Aug 21 05:19:25 PM UTC 24
Peak memory 200580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287401428
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_tim
er_stress_all.1287401428
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.193847558
Short name T25
Test name
Test status
Simulation time 567443236 ps
CPU time 1.69 seconds
Started Aug 21 05:16:40 PM UTC 24
Finished Aug 21 05:16:42 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=193847558 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.193847558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.2688824298
Short name T151
Test name
Test status
Simulation time 480093168 ps
CPU time 2.1 seconds
Started Aug 21 05:16:52 PM UTC 24
Finished Aug 21 05:16:55 PM UTC 24
Peak memory 200528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2688824298 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2688824298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.3272093608
Short name T39
Test name
Test status
Simulation time 2046218547 ps
CPU time 17.99 seconds
Started Aug 21 05:16:55 PM UTC 24
Finished Aug 21 05:17:14 PM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3272093608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3272093608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.1632395114
Short name T144
Test name
Test status
Simulation time 585632684 ps
CPU time 1.09 seconds
Started Aug 21 05:16:58 PM UTC 24
Finished Aug 21 05:17:00 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1632395114 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1632395114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2202677334
Short name T145
Test name
Test status
Simulation time 137677214809 ps
CPU time 65.41 seconds
Started Aug 21 05:17:23 PM UTC 24
Finished Aug 21 05:18:30 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202677334
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_tim
er_stress_all.2202677334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3237405824
Short name T137
Test name
Test status
Simulation time 430185819 ps
CPU time 2.36 seconds
Started Aug 21 05:18:30 PM UTC 24
Finished Aug 21 05:18:34 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3237405824 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3237405824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.71563010
Short name T14
Test name
Test status
Simulation time 469404329 ps
CPU time 1.17 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:16:38 PM UTC 24
Peak memory 199628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71563010 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.71563010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.2477757281
Short name T147
Test name
Test status
Simulation time 76768761315 ps
CPU time 81.88 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:18:51 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2477757281
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_tim
er_stress_all.2477757281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.384994039
Short name T128
Test name
Test status
Simulation time 387508396 ps
CPU time 0.99 seconds
Started Aug 21 05:17:47 PM UTC 24
Finished Aug 21 05:17:49 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=384994039 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.384994039
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.1564036232
Short name T119
Test name
Test status
Simulation time 83290939676 ps
CPU time 106.8 seconds
Started Aug 21 05:17:50 PM UTC 24
Finished Aug 21 05:19:39 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564036232
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_tim
er_stress_all.1564036232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.2013787562
Short name T158
Test name
Test status
Simulation time 446027932 ps
CPU time 1.94 seconds
Started Aug 21 05:18:05 PM UTC 24
Finished Aug 21 05:18:08 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2013787562 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2013787562
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.3626404995
Short name T115
Test name
Test status
Simulation time 502473910 ps
CPU time 2.54 seconds
Started Aug 21 05:18:44 PM UTC 24
Finished Aug 21 05:18:47 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3626404995 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3626404995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.392734739
Short name T138
Test name
Test status
Simulation time 583733392 ps
CPU time 1.7 seconds
Started Aug 21 05:19:07 PM UTC 24
Finished Aug 21 05:19:10 PM UTC 24
Peak memory 198760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392734739 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.392734739
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.1229714094
Short name T87
Test name
Test status
Simulation time 395087235 ps
CPU time 1.33 seconds
Started Aug 21 05:19:19 PM UTC 24
Finished Aug 21 05:19:22 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229714094 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1229714094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.4155052193
Short name T117
Test name
Test status
Simulation time 3442538207 ps
CPU time 27.66 seconds
Started Aug 21 05:19:19 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155052193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4155052193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.672971238
Short name T162
Test name
Test status
Simulation time 4533232878 ps
CPU time 20.42 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:19:46 PM UTC 24
Peak memory 216140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=672971238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.672971238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.830681072
Short name T28
Test name
Test status
Simulation time 4715961164 ps
CPU time 29.41 seconds
Started Aug 21 05:16:41 PM UTC 24
Finished Aug 21 05:17:12 PM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830681072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.830681072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.1229036587
Short name T51
Test name
Test status
Simulation time 559660240 ps
CPU time 2.39 seconds
Started Aug 21 05:17:01 PM UTC 24
Finished Aug 21 05:17:04 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229036587 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1229036587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.1229936200
Short name T125
Test name
Test status
Simulation time 415391721 ps
CPU time 2.02 seconds
Started Aug 21 05:17:16 PM UTC 24
Finished Aug 21 05:17:19 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1229936200 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1229936200
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.2093097530
Short name T131
Test name
Test status
Simulation time 2107048879 ps
CPU time 15.53 seconds
Started Aug 21 05:18:00 PM UTC 24
Finished Aug 21 05:18:17 PM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2093097530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2093097530
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.1697199281
Short name T116
Test name
Test status
Simulation time 523220573 ps
CPU time 1.23 seconds
Started Aug 21 05:19:02 PM UTC 24
Finished Aug 21 05:19:04 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697199281 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1697199281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.1066088356
Short name T152
Test name
Test status
Simulation time 86519895888 ps
CPU time 107.41 seconds
Started Aug 21 05:16:39 PM UTC 24
Finished Aug 21 05:18:28 PM UTC 24
Peak memory 200712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1066088356
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_time
r_stress_all.1066088356
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3231644466
Short name T168
Test name
Test status
Simulation time 425953882 ps
CPU time 0.88 seconds
Started Aug 21 05:17:10 PM UTC 24
Finished Aug 21 05:17:12 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3231644466 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3231644466
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.34541203
Short name T129
Test name
Test status
Simulation time 3384324877 ps
CPU time 31.86 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:18:00 PM UTC 24
Peak memory 213936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34541203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.34541203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.1401932541
Short name T165
Test name
Test status
Simulation time 477932450 ps
CPU time 2.51 seconds
Started Aug 21 05:18:12 PM UTC 24
Finished Aug 21 05:18:16 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401932541 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1401932541
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.1273143
Short name T111
Test name
Test status
Simulation time 9245187891 ps
CPU time 25.32 seconds
Started Aug 21 05:18:12 PM UTC 24
Finished Aug 21 05:18:39 PM UTC 24
Peak memory 214680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1273143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1273143
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2979424745
Short name T157
Test name
Test status
Simulation time 554242801 ps
CPU time 0.95 seconds
Started Aug 21 05:18:13 PM UTC 24
Finished Aug 21 05:18:15 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979424745 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2979424745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.593159730
Short name T94
Test name
Test status
Simulation time 362654912 ps
CPU time 1.27 seconds
Started Aug 21 05:18:16 PM UTC 24
Finished Aug 21 05:18:18 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=593159730 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.593159730
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.2178193529
Short name T169
Test name
Test status
Simulation time 209857096529 ps
CPU time 69.59 seconds
Started Aug 21 05:18:25 PM UTC 24
Finished Aug 21 05:19:36 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2178193529
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_tim
er_stress_all.2178193529
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2788219473
Short name T181
Test name
Test status
Simulation time 5762058375 ps
CPU time 30.98 seconds
Started Aug 21 05:18:34 PM UTC 24
Finished Aug 21 05:19:06 PM UTC 24
Peak memory 218316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2788219473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2788219473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.302642465
Short name T190
Test name
Test status
Simulation time 577579024 ps
CPU time 2.09 seconds
Started Aug 21 05:18:50 PM UTC 24
Finished Aug 21 05:18:54 PM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=302642465 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.302642465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.4162179780
Short name T183
Test name
Test status
Simulation time 5221276967 ps
CPU time 16.06 seconds
Started Aug 21 05:18:56 PM UTC 24
Finished Aug 21 05:19:13 PM UTC 24
Peak memory 219492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162179780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4162179780
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.1430767378
Short name T192
Test name
Test status
Simulation time 445758811 ps
CPU time 1.53 seconds
Started Aug 21 05:19:11 PM UTC 24
Finished Aug 21 05:19:13 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430767378 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1430767378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.1332442831
Short name T185
Test name
Test status
Simulation time 418642925 ps
CPU time 1.49 seconds
Started Aug 21 05:19:13 PM UTC 24
Finished Aug 21 05:19:16 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332442831 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1332442831
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.3405845349
Short name T155
Test name
Test status
Simulation time 421599490 ps
CPU time 1.37 seconds
Started Aug 21 05:19:15 PM UTC 24
Finished Aug 21 05:19:17 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3405845349 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3405845349
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.495710948
Short name T46
Test name
Test status
Simulation time 411209927 ps
CPU time 1.8 seconds
Started Aug 21 05:16:47 PM UTC 24
Finished Aug 21 05:16:50 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=495710948 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.495710948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3191297808
Short name T196
Test name
Test status
Simulation time 8729799687 ps
CPU time 3.62 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 207068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319129
7808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ao
n_timer_tl_intg_err.3191297808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.1307597509
Short name T177
Test name
Test status
Simulation time 547397532 ps
CPU time 2.24 seconds
Started Aug 21 05:17:30 PM UTC 24
Finished Aug 21 05:17:34 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307597509 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1307597509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.1919757264
Short name T132
Test name
Test status
Simulation time 501083883 ps
CPU time 1.26 seconds
Started Aug 21 05:17:32 PM UTC 24
Finished Aug 21 05:17:35 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1919757264 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1919757264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.2076258499
Short name T180
Test name
Test status
Simulation time 547434446 ps
CPU time 1.19 seconds
Started Aug 21 05:18:21 PM UTC 24
Finished Aug 21 05:18:24 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076258499 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2076258499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.3749577295
Short name T191
Test name
Test status
Simulation time 359022351 ps
CPU time 1.73 seconds
Started Aug 21 05:18:24 PM UTC 24
Finished Aug 21 05:18:26 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3749577295 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3749577295
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2051502253
Short name T170
Test name
Test status
Simulation time 500221698 ps
CPU time 1.21 seconds
Started Aug 21 05:18:27 PM UTC 24
Finished Aug 21 05:18:29 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2051502253 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2051502253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1613130624
Short name T173
Test name
Test status
Simulation time 360777732 ps
CPU time 1.11 seconds
Started Aug 21 05:18:36 PM UTC 24
Finished Aug 21 05:18:38 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613130624 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1613130624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.1832533272
Short name T160
Test name
Test status
Simulation time 572727133 ps
CPU time 1.28 seconds
Started Aug 21 05:18:41 PM UTC 24
Finished Aug 21 05:18:43 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832533272 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1832533272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2154994436
Short name T184
Test name
Test status
Simulation time 516271880 ps
CPU time 1.79 seconds
Started Aug 21 05:18:56 PM UTC 24
Finished Aug 21 05:18:58 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154994436 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2154994436
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.3298836783
Short name T186
Test name
Test status
Simulation time 442311103 ps
CPU time 0.87 seconds
Started Aug 21 05:19:05 PM UTC 24
Finished Aug 21 05:19:07 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3298836783 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3298836783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.2900812488
Short name T176
Test name
Test status
Simulation time 504768723 ps
CPU time 1.42 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:19:27 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900812488 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2900812488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.1464982560
Short name T188
Test name
Test status
Simulation time 417943494 ps
CPU time 1.94 seconds
Started Aug 21 05:17:23 PM UTC 24
Finished Aug 21 05:17:26 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1464982560 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1464982560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.1311945205
Short name T171
Test name
Test status
Simulation time 400594202 ps
CPU time 1.22 seconds
Started Aug 21 05:17:37 PM UTC 24
Finished Aug 21 05:17:39 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1311945205 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1311945205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.3714505205
Short name T175
Test name
Test status
Simulation time 469158720 ps
CPU time 1.67 seconds
Started Aug 21 05:17:40 PM UTC 24
Finished Aug 21 05:17:43 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714505205 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3714505205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1711112559
Short name T182
Test name
Test status
Simulation time 604375727 ps
CPU time 1.77 seconds
Started Aug 21 05:18:08 PM UTC 24
Finished Aug 21 05:18:11 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711112559 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1711112559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.1051518223
Short name T8
Test name
Test status
Simulation time 619290143 ps
CPU time 0.94 seconds
Started Aug 21 05:16:30 PM UTC 24
Finished Aug 21 05:16:32 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051518223 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1051518223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.4031398809
Short name T193
Test name
Test status
Simulation time 632352427 ps
CPU time 2 seconds
Started Aug 21 05:18:34 PM UTC 24
Finished Aug 21 05:18:36 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4031398809 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4031398809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.2041941729
Short name T172
Test name
Test status
Simulation time 73243711808 ps
CPU time 38.55 seconds
Started Aug 21 05:18:38 PM UTC 24
Finished Aug 21 05:19:18 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2041941729
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_tim
er_stress_all.2041941729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.575796153
Short name T161
Test name
Test status
Simulation time 446901321 ps
CPU time 1.26 seconds
Started Aug 21 05:18:47 PM UTC 24
Finished Aug 21 05:18:49 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575796153 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.575796153
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.3048848655
Short name T189
Test name
Test status
Simulation time 1678236020 ps
CPU time 10.44 seconds
Started Aug 21 05:18:48 PM UTC 24
Finished Aug 21 05:19:00 PM UTC 24
Peak memory 215316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048848655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3048848655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3980315671
Short name T134
Test name
Test status
Simulation time 580791884 ps
CPU time 1.26 seconds
Started Aug 21 05:18:54 PM UTC 24
Finished Aug 21 05:18:57 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3980315671 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3980315671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4265103181
Short name T30
Test name
Test status
Simulation time 537413326 ps
CPU time 2.19 seconds
Started Aug 21 05:19:29 PM UTC 24
Finished Aug 21 05:19:32 PM UTC 24
Peak memory 203320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426510318
1 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_csr_aliasing.4265103181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1972128759
Short name T77
Test name
Test status
Simulation time 13842755720 ps
CPU time 7.7 seconds
Started Aug 21 05:19:29 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 205640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=197212875
9 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_csr_bit_bash.1972128759
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2041687069
Short name T31
Test name
Test status
Simulation time 1059127347 ps
CPU time 3.55 seconds
Started Aug 21 05:19:28 PM UTC 24
Finished Aug 21 05:19:32 PM UTC 24
Peak memory 203248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204168706
9 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_csr_hw_reset.2041687069
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1832849462
Short name T37
Test name
Test status
Simulation time 563804798 ps
CPU time 1.1 seconds
Started Aug 21 05:19:30 PM UTC 24
Finished Aug 21 05:19:32 PM UTC 24
Peak memory 203984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=1832849462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1832849462
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2406748255
Short name T36
Test name
Test status
Simulation time 429756616 ps
CPU time 2.28 seconds
Started Aug 21 05:19:28 PM UTC 24
Finished Aug 21 05:19:31 PM UTC 24
Peak memory 201596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2406748255 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_c
sr_rw.2406748255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.1564578385
Short name T289
Test name
Test status
Simulation time 500143360 ps
CPU time 1.22 seconds
Started Aug 21 05:19:26 PM UTC 24
Finished Aug 21 05:19:28 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564578385 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr
_test.1564578385
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.301786726
Short name T291
Test name
Test status
Simulation time 477784213 ps
CPU time 2.31 seconds
Started Aug 21 05:19:27 PM UTC 24
Finished Aug 21 05:19:30 PM UTC 24
Peak memory 201144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed
=301786726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.aon_timer_mem_partial_access.301786726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.3470534504
Short name T288
Test name
Test status
Simulation time 291278719 ps
CPU time 0.9 seconds
Started Aug 21 05:19:26 PM UTC 24
Finished Aug 21 05:19:28 PM UTC 24
Peak memory 200544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=347053450
4 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_walk.3470534504
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2758689337
Short name T32
Test name
Test status
Simulation time 1431475589 ps
CPU time 4.21 seconds
Started Aug 21 05:19:29 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 203704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2758689337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.aon_timer_same_csr_outstanding.2758689337
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.456414190
Short name T290
Test name
Test status
Simulation time 311935463 ps
CPU time 2.31 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:19:28 PM UTC 24
Peak memory 206816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456414190 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_er
rors.456414190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3992044741
Short name T34
Test name
Test status
Simulation time 4713865372 ps
CPU time 8.69 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 206916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399204
4741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ao
n_timer_tl_intg_err.3992044741
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.724861098
Short name T76
Test name
Test status
Simulation time 443477676 ps
CPU time 1.57 seconds
Started Aug 21 05:19:35 PM UTC 24
Finished Aug 21 05:19:37 PM UTC 24
Peak memory 202176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=724861098
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_csr_aliasing.724861098
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1462164779
Short name T75
Test name
Test status
Simulation time 1319428970 ps
CPU time 1.94 seconds
Started Aug 21 05:19:33 PM UTC 24
Finished Aug 21 05:19:36 PM UTC 24
Peak memory 202172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146216477
9 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_csr_hw_reset.1462164779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2757674764
Short name T297
Test name
Test status
Simulation time 388204712 ps
CPU time 1.09 seconds
Started Aug 21 05:19:36 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2757674764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2757674764
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3112477773
Short name T293
Test name
Test status
Simulation time 519404468 ps
CPU time 1.14 seconds
Started Aug 21 05:19:32 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3112477773 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr
_test.3112477773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1369992393
Short name T295
Test name
Test status
Simulation time 453118392 ps
CPU time 1.45 seconds
Started Aug 21 05:19:33 PM UTC 24
Finished Aug 21 05:19:36 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed
=1369992393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.aon_timer_mem_partial_access.1369992393
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1157147937
Short name T294
Test name
Test status
Simulation time 315335144 ps
CPU time 0.84 seconds
Started Aug 21 05:19:33 PM UTC 24
Finished Aug 21 05:19:35 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=115714793
7 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_walk.1157147937
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2276986202
Short name T70
Test name
Test status
Simulation time 2528778050 ps
CPU time 2.03 seconds
Started Aug 21 05:19:35 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2276986202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.aon_timer_same_csr_outstanding.2276986202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2165554396
Short name T292
Test name
Test status
Simulation time 848044005 ps
CPU time 2.96 seconds
Started Aug 21 05:19:30 PM UTC 24
Finished Aug 21 05:19:34 PM UTC 24
Peak memory 206832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165554396 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_e
rrors.2165554396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2266884625
Short name T340
Test name
Test status
Simulation time 445171035 ps
CPU time 0.99 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 206092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2266884625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2266884625
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3389073609
Short name T66
Test name
Test status
Simulation time 495436893 ps
CPU time 1.29 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 202172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3389073609 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_
csr_rw.3389073609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2538649676
Short name T339
Test name
Test status
Simulation time 407499871 ps
CPU time 1.13 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 202136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538649676 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_int
r_test.2538649676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2975323580
Short name T346
Test name
Test status
Simulation time 2647093313 ps
CPU time 2.17 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2975323580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.aon_timer_same_csr_outstanding.2975323580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2058011247
Short name T344
Test name
Test status
Simulation time 401764679 ps
CPU time 1.92 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2058011247 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_
errors.2058011247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3930419654
Short name T389
Test name
Test status
Simulation time 4546845462 ps
CPU time 8.78 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 206684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=393041
9654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.a
on_timer_tl_intg_err.3930419654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.473450386
Short name T342
Test name
Test status
Simulation time 411214731 ps
CPU time 1.21 seconds
Started Aug 21 05:19:50 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=473450386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.473450386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3133927523
Short name T341
Test name
Test status
Simulation time 339805269 ps
CPU time 1.38 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3133927523 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_int
r_test.3133927523
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2939405769
Short name T345
Test name
Test status
Simulation time 2476425163 ps
CPU time 2.11 seconds
Started Aug 21 05:19:50 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2939405769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.aon_timer_same_csr_outstanding.2939405769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2632023956
Short name T350
Test name
Test status
Simulation time 642899036 ps
CPU time 2.39 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2632023956 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_
errors.2632023956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3109541912
Short name T373
Test name
Test status
Simulation time 4452342536 ps
CPU time 6.69 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:57 PM UTC 24
Peak memory 206328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310954
1912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.a
on_timer_tl_intg_err.3109541912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4262552704
Short name T351
Test name
Test status
Simulation time 587965570 ps
CPU time 1.27 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 204188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=4262552704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4262552704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.698106010
Short name T347
Test name
Test status
Simulation time 366433186 ps
CPU time 0.92 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 200100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=698106010 -asse
rt nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_c
sr_rw.698106010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2673045489
Short name T349
Test name
Test status
Simulation time 445846171 ps
CPU time 1.31 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673045489 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_int
r_test.2673045489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3282867979
Short name T356
Test name
Test status
Simulation time 1512389041 ps
CPU time 2.19 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 203512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=3282867979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.aon_timer_same_csr_outstanding.3282867979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2342915762
Short name T348
Test name
Test status
Simulation time 471184260 ps
CPU time 1.32 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:53 PM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342915762 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_
errors.2342915762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.528170114
Short name T381
Test name
Test status
Simulation time 4176732707 ps
CPU time 6.73 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 207116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=528170
114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_tl_intg_err.528170114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1507793421
Short name T354
Test name
Test status
Simulation time 475698822 ps
CPU time 0.94 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 205820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=1507793421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1507793421
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1591361563
Short name T61
Test name
Test status
Simulation time 618006437 ps
CPU time 0.81 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 202172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591361563 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_
csr_rw.1591361563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.2663653105
Short name T355
Test name
Test status
Simulation time 324053656 ps
CPU time 1.07 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2663653105 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_int
r_test.2663653105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4213182575
Short name T353
Test name
Test status
Simulation time 1181667496 ps
CPU time 0.74 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=4213182575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.aon_timer_same_csr_outstanding.4213182575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2625041380
Short name T352
Test name
Test status
Simulation time 540202995 ps
CPU time 1.54 seconds
Started Aug 21 05:19:51 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2625041380 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_
errors.2625041380
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2689277836
Short name T198
Test name
Test status
Simulation time 8289318798 ps
CPU time 6.29 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 207032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=268927
7836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.a
on_timer_tl_intg_err.2689277836
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4143922966
Short name T364
Test name
Test status
Simulation time 470456639 ps
CPU time 1.16 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 204152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=4143922966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4143922966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.3282268856
Short name T357
Test name
Test status
Simulation time 320719674 ps
CPU time 0.94 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 202172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282268856 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_
csr_rw.3282268856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1503009868
Short name T359
Test name
Test status
Simulation time 327402510 ps
CPU time 1.05 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1503009868 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_int
r_test.1503009868
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1629479286
Short name T370
Test name
Test status
Simulation time 2531001247 ps
CPU time 2.27 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:57 PM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=1629479286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.aon_timer_same_csr_outstanding.1629479286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.531098404
Short name T362
Test name
Test status
Simulation time 482540505 ps
CPU time 2.17 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:19:55 PM UTC 24
Peak memory 206996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531098404 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_e
rrors.531098404
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.874489456
Short name T422
Test name
Test status
Simulation time 8163131851 ps
CPU time 10.51 seconds
Started Aug 21 05:19:52 PM UTC 24
Finished Aug 21 05:20:04 PM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=874489
456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_tl_intg_err.874489456
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.128175460
Short name T367
Test name
Test status
Simulation time 307705143 ps
CPU time 1.16 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=128175460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.128175460
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1205524993
Short name T62
Test name
Test status
Simulation time 345593254 ps
CPU time 0.77 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1205524993 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_
csr_rw.1205524993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.112973093
Short name T368
Test name
Test status
Simulation time 391246850 ps
CPU time 1.41 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112973093 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr
_test.112973093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1152459206
Short name T369
Test name
Test status
Simulation time 949976164 ps
CPU time 1.89 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:57 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=1152459206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.aon_timer_same_csr_outstanding.1152459206
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.376152894
Short name T375
Test name
Test status
Simulation time 557194694 ps
CPU time 2.83 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=376152894 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_e
rrors.376152894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.905885403
Short name T423
Test name
Test status
Simulation time 8180936635 ps
CPU time 11.42 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:20:06 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905885
403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_tl_intg_err.905885403
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2925448303
Short name T376
Test name
Test status
Simulation time 499572392 ps
CPU time 1.51 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 203972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2925448303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2925448303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.4045491507
Short name T365
Test name
Test status
Simulation time 385380144 ps
CPU time 0.95 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4045491507 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_
csr_rw.4045491507
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3653758642
Short name T366
Test name
Test status
Simulation time 397964063 ps
CPU time 1.11 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653758642 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_int
r_test.3653758642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3706494111
Short name T415
Test name
Test status
Simulation time 2198453222 ps
CPU time 6.47 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 205456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=3706494111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.aon_timer_same_csr_outstanding.3706494111
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.656822793
Short name T371
Test name
Test status
Simulation time 467833179 ps
CPU time 2.08 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:57 PM UTC 24
Peak memory 206968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656822793 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_e
rrors.656822793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4274987176
Short name T372
Test name
Test status
Simulation time 4776904695 ps
CPU time 2.03 seconds
Started Aug 21 05:19:54 PM UTC 24
Finished Aug 21 05:19:57 PM UTC 24
Peak memory 205208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=427498
7176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.a
on_timer_tl_intg_err.4274987176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2630676747
Short name T382
Test name
Test status
Simulation time 418916786 ps
CPU time 2.1 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 205624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2630676747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2630676747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3190550555
Short name T67
Test name
Test status
Simulation time 430520639 ps
CPU time 1.11 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3190550555 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_
csr_rw.3190550555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2414443497
Short name T378
Test name
Test status
Simulation time 341048884 ps
CPU time 1.67 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414443497 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_int
r_test.2414443497
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2702547985
Short name T374
Test name
Test status
Simulation time 1094514100 ps
CPU time 1.14 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2702547985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.aon_timer_same_csr_outstanding.2702547985
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.4110458279
Short name T387
Test name
Test status
Simulation time 497504944 ps
CPU time 2.77 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110458279 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_
errors.4110458279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2793625755
Short name T393
Test name
Test status
Simulation time 8736755003 ps
CPU time 3.72 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279362
5755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.a
on_timer_tl_intg_err.2793625755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3125769510
Short name T377
Test name
Test status
Simulation time 364816078 ps
CPU time 1.25 seconds
Started Aug 21 05:19:56 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=3125769510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3125769510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2590276943
Short name T68
Test name
Test status
Simulation time 417097333 ps
CPU time 1.3 seconds
Started Aug 21 05:19:56 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 202172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590276943 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_
csr_rw.2590276943
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.2249398646
Short name T380
Test name
Test status
Simulation time 519339035 ps
CPU time 1.6 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249398646 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_int
r_test.2249398646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2039463736
Short name T386
Test name
Test status
Simulation time 2435688312 ps
CPU time 2.24 seconds
Started Aug 21 05:19:56 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2039463736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.aon_timer_same_csr_outstanding.2039463736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1300996460
Short name T379
Test name
Test status
Simulation time 476195917 ps
CPU time 1.66 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:19:58 PM UTC 24
Peak memory 206056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1300996460 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_
errors.1300996460
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1163218012
Short name T401
Test name
Test status
Simulation time 4447755581 ps
CPU time 3.89 seconds
Started Aug 21 05:19:55 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 206044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=116321
8012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.a
on_timer_tl_intg_err.1163218012
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2956272280
Short name T383
Test name
Test status
Simulation time 605085203 ps
CPU time 0.93 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 205352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2956272280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2956272280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.909512603
Short name T63
Test name
Test status
Simulation time 296710424 ps
CPU time 1.16 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 200052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=909512603 -asse
rt nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_c
sr_rw.909512603
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2628806026
Short name T385
Test name
Test status
Simulation time 503835176 ps
CPU time 1.09 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2628806026 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_int
r_test.2628806026
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2176210491
Short name T392
Test name
Test status
Simulation time 2770100167 ps
CPU time 2.09 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 205420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2176210491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.aon_timer_same_csr_outstanding.2176210491
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3782911396
Short name T388
Test name
Test status
Simulation time 313194701 ps
CPU time 1.64 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3782911396 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_
errors.3782911396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1358717788
Short name T413
Test name
Test status
Simulation time 9091378339 ps
CPU time 4.69 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 206924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=135871
7788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.a
on_timer_tl_intg_err.1358717788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3428571522
Short name T306
Test name
Test status
Simulation time 709760624 ps
CPU time 0.97 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 201980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342857152
2 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_csr_aliasing.3428571522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.667569041
Short name T57
Test name
Test status
Simulation time 3733130247 ps
CPU time 5.53 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 205584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667569041
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_csr_bit_bash.667569041
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1204527232
Short name T300
Test name
Test status
Simulation time 746666944 ps
CPU time 1.18 seconds
Started Aug 21 05:19:37 PM UTC 24
Finished Aug 21 05:19:39 PM UTC 24
Peak memory 200080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=120452723
2 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_csr_hw_reset.1204527232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.235927277
Short name T210
Test name
Test status
Simulation time 674269378 ps
CPU time 1.35 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 206112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=235927277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.235927277
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.344902978
Short name T302
Test name
Test status
Simulation time 384675370 ps
CPU time 1.72 seconds
Started Aug 21 05:19:37 PM UTC 24
Finished Aug 21 05:19:40 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344902978 -asse
rt nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_cs
r_rw.344902978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2025081243
Short name T296
Test name
Test status
Simulation time 349234850 ps
CPU time 0.78 seconds
Started Aug 21 05:19:36 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025081243 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr
_test.2025081243
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.201848527
Short name T301
Test name
Test status
Simulation time 397335036 ps
CPU time 1.36 seconds
Started Aug 21 05:19:37 PM UTC 24
Finished Aug 21 05:19:40 PM UTC 24
Peak memory 200020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed
=201848527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.aon_timer_mem_partial_access.201848527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1703455488
Short name T298
Test name
Test status
Simulation time 489693455 ps
CPU time 0.97 seconds
Started Aug 21 05:19:36 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=170345548
8 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_walk.1703455488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4169222694
Short name T71
Test name
Test status
Simulation time 1210143696 ps
CPU time 1.55 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=4169222694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.aon_timer_same_csr_outstanding.4169222694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3376761376
Short name T299
Test name
Test status
Simulation time 424688274 ps
CPU time 1.42 seconds
Started Aug 21 05:19:36 PM UTC 24
Finished Aug 21 05:19:38 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376761376 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_e
rrors.3376761376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1097526521
Short name T35
Test name
Test status
Simulation time 8425922788 ps
CPU time 4.7 seconds
Started Aug 21 05:19:36 PM UTC 24
Finished Aug 21 05:19:42 PM UTC 24
Peak memory 206864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109752
6521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ao
n_timer_tl_intg_err.1097526521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.1251769106
Short name T384
Test name
Test status
Simulation time 418524777 ps
CPU time 0.82 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:19:59 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1251769106 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_int
r_test.1251769106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3246737594
Short name T390
Test name
Test status
Simulation time 483276912 ps
CPU time 1.37 seconds
Started Aug 21 05:19:57 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246737594 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_int
r_test.3246737594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3649561254
Short name T391
Test name
Test status
Simulation time 424704898 ps
CPU time 0.71 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 199820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3649561254 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_int
r_test.3649561254
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2495332255
Short name T394
Test name
Test status
Simulation time 350021539 ps
CPU time 0.89 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495332255 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_int
r_test.2495332255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.946271406
Short name T397
Test name
Test status
Simulation time 491660960 ps
CPU time 0.96 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 199932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=946271406 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr
_test.946271406
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2290116350
Short name T398
Test name
Test status
Simulation time 358397874 ps
CPU time 1.06 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 202156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2290116350 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_int
r_test.2290116350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1706980520
Short name T399
Test name
Test status
Simulation time 398728897 ps
CPU time 0.94 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706980520 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_int
r_test.1706980520
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2096174073
Short name T400
Test name
Test status
Simulation time 299487112 ps
CPU time 1.02 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096174073 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_int
r_test.2096174073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2663520727
Short name T395
Test name
Test status
Simulation time 495997153 ps
CPU time 0.8 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2663520727 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_int
r_test.2663520727
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3080868365
Short name T396
Test name
Test status
Simulation time 518740038 ps
CPU time 0.78 seconds
Started Aug 21 05:19:58 PM UTC 24
Finished Aug 21 05:20:00 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080868365 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_int
r_test.3080868365
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2041800401
Short name T55
Test name
Test status
Simulation time 462295302 ps
CPU time 2.16 seconds
Started Aug 21 05:19:41 PM UTC 24
Finished Aug 21 05:19:44 PM UTC 24
Peak memory 203320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204180040
1 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_csr_aliasing.2041800401
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.538678024
Short name T59
Test name
Test status
Simulation time 6782053463 ps
CPU time 5.39 seconds
Started Aug 21 05:19:40 PM UTC 24
Finished Aug 21 05:19:46 PM UTC 24
Peak memory 205660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=538678024
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_csr_bit_bash.538678024
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.970677867
Short name T312
Test name
Test status
Simulation time 1109178115 ps
CPU time 2.6 seconds
Started Aug 21 05:19:40 PM UTC 24
Finished Aug 21 05:19:43 PM UTC 24
Peak memory 203520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=970677867
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_csr_hw_reset.970677867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2217877670
Short name T311
Test name
Test status
Simulation time 463772947 ps
CPU time 1.43 seconds
Started Aug 21 05:19:41 PM UTC 24
Finished Aug 21 05:19:43 PM UTC 24
Peak memory 205088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2217877670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2217877670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2289128371
Short name T54
Test name
Test status
Simulation time 479604413 ps
CPU time 1.49 seconds
Started Aug 21 05:19:40 PM UTC 24
Finished Aug 21 05:19:42 PM UTC 24
Peak memory 202108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289128371 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_c
sr_rw.2289128371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2686291350
Short name T305
Test name
Test status
Simulation time 392890729 ps
CPU time 1.15 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686291350 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr
_test.2686291350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2761262866
Short name T307
Test name
Test status
Simulation time 341795142 ps
CPU time 1.12 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:41 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed
=2761262866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.aon_timer_mem_partial_access.2761262866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.36964770
Short name T304
Test name
Test status
Simulation time 399786592 ps
CPU time 1.07 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:40 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36964770
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_mem_walk.36964770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3584693196
Short name T72
Test name
Test status
Simulation time 1568108206 ps
CPU time 1.29 seconds
Started Aug 21 05:19:41 PM UTC 24
Finished Aug 21 05:19:43 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=3584693196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.aon_timer_same_csr_outstanding.3584693196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2054552244
Short name T310
Test name
Test status
Simulation time 690254056 ps
CPU time 2.33 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:42 PM UTC 24
Peak memory 206984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054552244 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_e
rrors.2054552244
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3090447719
Short name T194
Test name
Test status
Simulation time 3929267313 ps
CPU time 3.73 seconds
Started Aug 21 05:19:38 PM UTC 24
Finished Aug 21 05:19:44 PM UTC 24
Peak memory 205460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309044
7719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ao
n_timer_tl_intg_err.3090447719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.1267388077
Short name T361
Test name
Test status
Simulation time 481854237 ps
CPU time 1.2 seconds
Started Aug 21 05:19:59 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1267388077 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_int
r_test.1267388077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1683135996
Short name T402
Test name
Test status
Simulation time 499748994 ps
CPU time 0.79 seconds
Started Aug 21 05:19:59 PM UTC 24
Finished Aug 21 05:20:01 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683135996 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_int
r_test.1683135996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.1272881611
Short name T403
Test name
Test status
Simulation time 542319617 ps
CPU time 0.96 seconds
Started Aug 21 05:19:59 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272881611 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_int
r_test.1272881611
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2675536559
Short name T404
Test name
Test status
Simulation time 503074537 ps
CPU time 0.88 seconds
Started Aug 21 05:19:59 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2675536559 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_int
r_test.2675536559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2850917307
Short name T409
Test name
Test status
Simulation time 487524276 ps
CPU time 1.31 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850917307 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_int
r_test.2850917307
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.698589916
Short name T360
Test name
Test status
Simulation time 338196691 ps
CPU time 0.78 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=698589916 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr
_test.698589916
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.1907619906
Short name T412
Test name
Test status
Simulation time 490838436 ps
CPU time 1.41 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1907619906 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_int
r_test.1907619906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.4279571208
Short name T410
Test name
Test status
Simulation time 505785090 ps
CPU time 1.34 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4279571208 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_int
r_test.4279571208
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.1494557497
Short name T407
Test name
Test status
Simulation time 458606779 ps
CPU time 0.99 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1494557497 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_int
r_test.1494557497
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2737067483
Short name T408
Test name
Test status
Simulation time 325161105 ps
CPU time 1.08 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 199840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737067483 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_int
r_test.2737067483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.766080743
Short name T317
Test name
Test status
Simulation time 431854662 ps
CPU time 1.3 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 202176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=766080743
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_csr_aliasing.766080743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.216655779
Short name T324
Test name
Test status
Simulation time 7503508694 ps
CPU time 3.78 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 205720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=216655779
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_csr_bit_bash.216655779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.882098792
Short name T58
Test name
Test status
Simulation time 1211543775 ps
CPU time 2.01 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:46 PM UTC 24
Peak memory 202156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=882098792
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_csr_hw_reset.882098792
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2435728014
Short name T318
Test name
Test status
Simulation time 355225283 ps
CPU time 1.63 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:46 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2435728014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2435728014
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3605423443
Short name T56
Test name
Test status
Simulation time 361262202 ps
CPU time 0.89 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 202168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3605423443 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_c
sr_rw.3605423443
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2683086112
Short name T315
Test name
Test status
Simulation time 267035211 ps
CPU time 1.14 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683086112 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr
_test.2683086112
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2171797024
Short name T314
Test name
Test status
Simulation time 461698976 ps
CPU time 0.92 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed
=2171797024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.aon_timer_mem_partial_access.2171797024
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2848028559
Short name T316
Test name
Test status
Simulation time 384045614 ps
CPU time 1.37 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:45 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=284802855
9 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_walk.2848028559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.336107051
Short name T73
Test name
Test status
Simulation time 1136644662 ps
CPU time 2.88 seconds
Started Aug 21 05:19:43 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 203512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=336107051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.aon_timer_same_csr_outstanding.336107051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4003703444
Short name T313
Test name
Test status
Simulation time 360666868 ps
CPU time 1.84 seconds
Started Aug 21 05:19:41 PM UTC 24
Finished Aug 21 05:19:44 PM UTC 24
Peak memory 207140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003703444 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_e
rrors.4003703444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1325883665
Short name T195
Test name
Test status
Simulation time 8486207490 ps
CPU time 3.81 seconds
Started Aug 21 05:19:41 PM UTC 24
Finished Aug 21 05:19:46 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=132588
3665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ao
n_timer_tl_intg_err.1325883665
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.378823366
Short name T406
Test name
Test status
Simulation time 406956841 ps
CPU time 0.78 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=378823366 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr
_test.378823366
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.3744101319
Short name T411
Test name
Test status
Simulation time 453087049 ps
CPU time 1.22 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744101319 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_int
r_test.3744101319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1635717049
Short name T405
Test name
Test status
Simulation time 336052553 ps
CPU time 0.7 seconds
Started Aug 21 05:20:00 PM UTC 24
Finished Aug 21 05:20:02 PM UTC 24
Peak memory 200004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1635717049 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_int
r_test.1635717049
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.3559330350
Short name T414
Test name
Test status
Simulation time 356271486 ps
CPU time 0.69 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 199832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559330350 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_int
r_test.3559330350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1535755256
Short name T421
Test name
Test status
Simulation time 493373556 ps
CPU time 1.26 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 200032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1535755256 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_int
r_test.1535755256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.642617943
Short name T418
Test name
Test status
Simulation time 508483297 ps
CPU time 0.73 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=642617943 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr
_test.642617943
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1341267774
Short name T419
Test name
Test status
Simulation time 377736551 ps
CPU time 0.97 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1341267774 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_int
r_test.1341267774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.4012867222
Short name T420
Test name
Test status
Simulation time 379837086 ps
CPU time 1.1 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 202164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012867222 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_int
r_test.4012867222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3578439484
Short name T416
Test name
Test status
Simulation time 536231471 ps
CPU time 0.57 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578439484 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_int
r_test.3578439484
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2179704582
Short name T417
Test name
Test status
Simulation time 515621805 ps
CPU time 0.65 seconds
Started Aug 21 05:20:01 PM UTC 24
Finished Aug 21 05:20:03 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2179704582 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_int
r_test.2179704582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2784949570
Short name T321
Test name
Test status
Simulation time 435395574 ps
CPU time 0.98 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 204208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2784949570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2784949570
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.4127135191
Short name T319
Test name
Test status
Simulation time 406309727 ps
CPU time 0.75 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4127135191 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_c
sr_rw.4127135191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.2107267246
Short name T320
Test name
Test status
Simulation time 296010142 ps
CPU time 1.06 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107267246 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr
_test.2107267246
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3532927105
Short name T336
Test name
Test status
Simulation time 2819153496 ps
CPU time 4.82 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:51 PM UTC 24
Peak memory 205492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=3532927105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.aon_timer_same_csr_outstanding.3532927105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.776170358
Short name T323
Test name
Test status
Simulation time 309159904 ps
CPU time 1.88 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=776170358 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_er
rors.776170358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2717755035
Short name T358
Test name
Test status
Simulation time 8144264850 ps
CPU time 8.08 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271775
5035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ao
n_timer_tl_intg_err.2717755035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1268256347
Short name T309
Test name
Test status
Simulation time 428283537 ps
CPU time 1.21 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=1268256347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1268256347
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1234720746
Short name T60
Test name
Test status
Simulation time 382114540 ps
CPU time 1.03 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 202108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1234720746 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_c
sr_rw.1234720746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.113436252
Short name T322
Test name
Test status
Simulation time 381472460 ps
CPU time 1.05 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:47 PM UTC 24
Peak memory 200056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113436252 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_
test.113436252
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.974423453
Short name T74
Test name
Test status
Simulation time 2860974956 ps
CPU time 1.68 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:49 PM UTC 24
Peak memory 204216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=974423453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.aon_timer_same_csr_outstanding.974423453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.2405311789
Short name T325
Test name
Test status
Simulation time 291182205 ps
CPU time 1.86 seconds
Started Aug 21 05:19:45 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2405311789 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_e
rrors.2405311789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3216935068
Short name T326
Test name
Test status
Simulation time 369217740 ps
CPU time 0.86 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 206052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=3216935068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3216935068
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4085645316
Short name T64
Test name
Test status
Simulation time 515885921 ps
CPU time 0.89 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 202108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085645316 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_c
sr_rw.4085645316
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.568712107
Short name T308
Test name
Test status
Simulation time 375400032 ps
CPU time 0.79 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:48 PM UTC 24
Peak memory 199940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=568712107 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_
test.568712107
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2174820438
Short name T335
Test name
Test status
Simulation time 1290518637 ps
CPU time 3.05 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:51 PM UTC 24
Peak memory 203384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2174820438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.aon_timer_same_csr_outstanding.2174820438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.162777405
Short name T327
Test name
Test status
Simulation time 568579589 ps
CPU time 1.35 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:49 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162777405 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_er
rors.162777405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3801038083
Short name T331
Test name
Test status
Simulation time 4658507524 ps
CPU time 2.65 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 206080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=380103
8083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ao
n_timer_tl_intg_err.3801038083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2508537974
Short name T334
Test name
Test status
Simulation time 503823812 ps
CPU time 1.18 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 204212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=2508537974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2508537974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.25489629
Short name T329
Test name
Test status
Simulation time 365619903 ps
CPU time 0.89 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 200068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25489629 -asser
t nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.25489629
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3679235887
Short name T330
Test name
Test status
Simulation time 493284458 ps
CPU time 0.94 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679235887 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr
_test.3679235887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1875104511
Short name T343
Test name
Test status
Simulation time 2103903244 ps
CPU time 2.96 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 203308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=1875104511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.aon_timer_same_csr_outstanding.1875104511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1722125711
Short name T328
Test name
Test status
Simulation time 852053546 ps
CPU time 1.43 seconds
Started Aug 21 05:19:46 PM UTC 24
Finished Aug 21 05:19:49 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722125711 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_e
rrors.1722125711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3959449110
Short name T197
Test name
Test status
Simulation time 8704632493 ps
CPU time 4.64 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 206992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=395944
9110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ao
n_timer_tl_intg_err.3959449110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.935225515
Short name T338
Test name
Test status
Simulation time 380968994 ps
CPU time 1.21 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 204824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout
_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan
/hw/dv/tools/sim.tcl +ntb_random_seed=935225515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.935225515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.346772232
Short name T332
Test name
Test status
Simulation time 519946422 ps
CPU time 0.98 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 200124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=346772232 -asse
rt nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_cs
r_rw.346772232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1406683198
Short name T333
Test name
Test status
Simulation time 353502957 ps
CPU time 1.07 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:50 PM UTC 24
Peak memory 200060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406683198 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr
_test.1406683198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1226872079
Short name T337
Test name
Test status
Simulation time 2659310699 ps
CPU time 1.14 seconds
Started Aug 21 05:19:49 PM UTC 24
Finished Aug 21 05:19:52 PM UTC 24
Peak memory 204216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=1226872079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.aon_timer_same_csr_outstanding.1226872079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1088963324
Short name T303
Test name
Test status
Simulation time 549687106 ps
CPU time 1.99 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:51 PM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088963324 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_e
rrors.1088963324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2560291940
Short name T363
Test name
Test status
Simulation time 4085605190 ps
CPU time 6.39 seconds
Started Aug 21 05:19:48 PM UTC 24
Finished Aug 21 05:19:56 PM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256029
1940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ao
n_timer_tl_intg_err.2560291940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.2406046032
Short name T2
Test name
Test status
Simulation time 499554221 ps
CPU time 1.2 seconds
Started Aug 21 05:16:06 PM UTC 24
Finished Aug 21 05:16:08 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2406046032 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2406046032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.191337015
Short name T10
Test name
Test status
Simulation time 38567319887 ps
CPU time 29.09 seconds
Started Aug 21 05:16:04 PM UTC 24
Finished Aug 21 05:16:35 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=191337015 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.191337015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1221338487
Short name T1
Test name
Test status
Simulation time 575866923 ps
CPU time 2.43 seconds
Started Aug 21 05:16:04 PM UTC 24
Finished Aug 21 05:16:08 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221338487 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1221338487
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.1360028156
Short name T44
Test name
Test status
Simulation time 49048572201 ps
CPU time 21.05 seconds
Started Aug 21 05:16:17 PM UTC 24
Finished Aug 21 05:16:39 PM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1360028156 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1360028156
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.448267966
Short name T19
Test name
Test status
Simulation time 3762629037 ps
CPU time 13.22 seconds
Started Aug 21 05:16:21 PM UTC 24
Finished Aug 21 05:16:35 PM UTC 24
Peak memory 230856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448267966 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.448267966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.764156330
Short name T3
Test name
Test status
Simulation time 615817953 ps
CPU time 1.15 seconds
Started Aug 21 05:16:16 PM UTC 24
Finished Aug 21 05:16:18 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764156330 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.764156330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.2059824934
Short name T206
Test name
Test status
Simulation time 180887085503 ps
CPU time 120.59 seconds
Started Aug 21 05:16:19 PM UTC 24
Finished Aug 21 05:18:22 PM UTC 24
Peak memory 200904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2059824934
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_time
r_stress_all.2059824934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.3561219519
Short name T52
Test name
Test status
Simulation time 5558941956 ps
CPU time 8.06 seconds
Started Aug 21 05:16:57 PM UTC 24
Finished Aug 21 05:17:06 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561219519 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3561219519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.4263918505
Short name T159
Test name
Test status
Simulation time 401712404 ps
CPU time 2.08 seconds
Started Aug 21 05:16:57 PM UTC 24
Finished Aug 21 05:17:00 PM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4263918505 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4263918505
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.3840285089
Short name T217
Test name
Test status
Simulation time 30010814426 ps
CPU time 23.57 seconds
Started Aug 21 05:17:01 PM UTC 24
Finished Aug 21 05:17:26 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3840285089 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3840285089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.3707340990
Short name T212
Test name
Test status
Simulation time 559306947 ps
CPU time 0.96 seconds
Started Aug 21 05:17:01 PM UTC 24
Finished Aug 21 05:17:03 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3707340990 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3707340990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2445143808
Short name T205
Test name
Test status
Simulation time 28023196423 ps
CPU time 14.77 seconds
Started Aug 21 05:17:07 PM UTC 24
Finished Aug 21 05:17:23 PM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445143808 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2445143808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.3162834126
Short name T213
Test name
Test status
Simulation time 632347115 ps
CPU time 1.35 seconds
Started Aug 21 05:17:07 PM UTC 24
Finished Aug 21 05:17:09 PM UTC 24
Peak memory 199620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162834126 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3162834126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2778720255
Short name T43
Test name
Test status
Simulation time 3792121577 ps
CPU time 11.54 seconds
Started Aug 21 05:17:11 PM UTC 24
Finished Aug 21 05:17:23 PM UTC 24
Peak memory 217608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778720255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2778720255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.1762912345
Short name T255
Test name
Test status
Simulation time 55097068413 ps
CPU time 88.92 seconds
Started Aug 21 05:17:15 PM UTC 24
Finished Aug 21 05:18:46 PM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1762912345 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1762912345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.3382082950
Short name T214
Test name
Test status
Simulation time 403342907 ps
CPU time 1.87 seconds
Started Aug 21 05:17:13 PM UTC 24
Finished Aug 21 05:17:16 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3382082950 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3382082950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.1104733975
Short name T201
Test name
Test status
Simulation time 4514691001 ps
CPU time 10.92 seconds
Started Aug 21 05:17:20 PM UTC 24
Finished Aug 21 05:17:32 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1104733975 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1104733975
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2157558217
Short name T215
Test name
Test status
Simulation time 378131737 ps
CPU time 2.1 seconds
Started Aug 21 05:17:18 PM UTC 24
Finished Aug 21 05:17:21 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2157558217 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2157558217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2868073094
Short name T230
Test name
Test status
Simulation time 33275007263 ps
CPU time 40.9 seconds
Started Aug 21 05:17:23 PM UTC 24
Finished Aug 21 05:18:06 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868073094 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2868073094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.428245113
Short name T216
Test name
Test status
Simulation time 535142115 ps
CPU time 1.19 seconds
Started Aug 21 05:17:23 PM UTC 24
Finished Aug 21 05:17:25 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=428245113 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.428245113
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3193345516
Short name T200
Test name
Test status
Simulation time 3629299757 ps
CPU time 6.66 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:17:35 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193345516 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3193345516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.462430920
Short name T220
Test name
Test status
Simulation time 503882368 ps
CPU time 2.38 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:17:30 PM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=462430920 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.462430920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.1272870622
Short name T207
Test name
Test status
Simulation time 31748234139 ps
CPU time 9.19 seconds
Started Aug 21 05:17:30 PM UTC 24
Finished Aug 21 05:17:41 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272870622 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1272870622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.822323245
Short name T219
Test name
Test status
Simulation time 425656746 ps
CPU time 1.17 seconds
Started Aug 21 05:17:27 PM UTC 24
Finished Aug 21 05:17:29 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822323245 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.822323245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.4164695767
Short name T233
Test name
Test status
Simulation time 52465029683 ps
CPU time 36.58 seconds
Started Aug 21 05:17:31 PM UTC 24
Finished Aug 21 05:18:10 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4164695767 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4164695767
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.1647767783
Short name T221
Test name
Test status
Simulation time 478389223 ps
CPU time 0.95 seconds
Started Aug 21 05:17:31 PM UTC 24
Finished Aug 21 05:17:34 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647767783 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1647767783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.2076794179
Short name T234
Test name
Test status
Simulation time 27910932503 ps
CPU time 32.97 seconds
Started Aug 21 05:17:36 PM UTC 24
Finished Aug 21 05:18:10 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076794179 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2076794179
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.569036950
Short name T222
Test name
Test status
Simulation time 473243283 ps
CPU time 0.99 seconds
Started Aug 21 05:17:36 PM UTC 24
Finished Aug 21 05:17:38 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569036950 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.569036950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.2216590231
Short name T208
Test name
Test status
Simulation time 50639856787 ps
CPU time 24.11 seconds
Started Aug 21 05:16:23 PM UTC 24
Finished Aug 21 05:16:48 PM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216590231 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2216590231
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1811031030
Short name T11
Test name
Test status
Simulation time 8428486895 ps
CPU time 7.52 seconds
Started Aug 21 05:16:24 PM UTC 24
Finished Aug 21 05:16:33 PM UTC 24
Peak memory 231120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1811031030 -as
sert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1811031030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.918183055
Short name T5
Test name
Test status
Simulation time 408685682 ps
CPU time 2.01 seconds
Started Aug 21 05:16:21 PM UTC 24
Finished Aug 21 05:16:24 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=918183055 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.918183055
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.2561111062
Short name T202
Test name
Test status
Simulation time 8831963476 ps
CPU time 9.67 seconds
Started Aug 21 05:17:39 PM UTC 24
Finished Aug 21 05:17:50 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2561111062 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2561111062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.620445564
Short name T223
Test name
Test status
Simulation time 550775987 ps
CPU time 1.26 seconds
Started Aug 21 05:17:39 PM UTC 24
Finished Aug 21 05:17:42 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=620445564 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.620445564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.3252792191
Short name T239
Test name
Test status
Simulation time 60048012491 ps
CPU time 31.88 seconds
Started Aug 21 05:17:45 PM UTC 24
Finished Aug 21 05:18:18 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252792191 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3252792191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.898475325
Short name T224
Test name
Test status
Simulation time 492504306 ps
CPU time 1.63 seconds
Started Aug 21 05:17:44 PM UTC 24
Finished Aug 21 05:17:46 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898475325 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.898475325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1706302546
Short name T187
Test name
Test status
Simulation time 447773799 ps
CPU time 1.43 seconds
Started Aug 21 05:17:54 PM UTC 24
Finished Aug 21 05:17:56 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706302546 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1706302546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.809792578
Short name T226
Test name
Test status
Simulation time 9633404249 ps
CPU time 6.83 seconds
Started Aug 21 05:17:51 PM UTC 24
Finished Aug 21 05:17:59 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=809792578 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.809792578
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.1205523273
Short name T225
Test name
Test status
Simulation time 566731490 ps
CPU time 1.72 seconds
Started Aug 21 05:17:51 PM UTC 24
Finished Aug 21 05:17:54 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1205523273 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1205523273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1743183904
Short name T229
Test name
Test status
Simulation time 8670327229 ps
CPU time 5.86 seconds
Started Aug 21 05:17:57 PM UTC 24
Finished Aug 21 05:18:04 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743183904 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1743183904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.787347509
Short name T227
Test name
Test status
Simulation time 521800694 ps
CPU time 2.6 seconds
Started Aug 21 05:17:56 PM UTC 24
Finished Aug 21 05:18:00 PM UTC 24
Peak memory 200496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787347509 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.787347509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1031504867
Short name T236
Test name
Test status
Simulation time 8042609892 ps
CPU time 7.76 seconds
Started Aug 21 05:18:05 PM UTC 24
Finished Aug 21 05:18:14 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1031504867 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1031504867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2388656282
Short name T231
Test name
Test status
Simulation time 483368158 ps
CPU time 1.37 seconds
Started Aug 21 05:18:03 PM UTC 24
Finished Aug 21 05:18:06 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2388656282 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2388656282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3322014494
Short name T246
Test name
Test status
Simulation time 50930909950 ps
CPU time 24.39 seconds
Started Aug 21 05:18:06 PM UTC 24
Finished Aug 21 05:18:32 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3322014494 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3322014494
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.1432808440
Short name T232
Test name
Test status
Simulation time 541471726 ps
CPU time 2.54 seconds
Started Aug 21 05:18:06 PM UTC 24
Finished Aug 21 05:18:10 PM UTC 24
Peak memory 200436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1432808440 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1432808440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1716190789
Short name T247
Test name
Test status
Simulation time 4775758020 ps
CPU time 23.18 seconds
Started Aug 21 05:18:08 PM UTC 24
Finished Aug 21 05:18:33 PM UTC 24
Peak memory 200980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1716190789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1716190789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.3817912647
Short name T238
Test name
Test status
Simulation time 2716047409 ps
CPU time 5.96 seconds
Started Aug 21 05:18:11 PM UTC 24
Finished Aug 21 05:18:18 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3817912647 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3817912647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.316969417
Short name T235
Test name
Test status
Simulation time 478472089 ps
CPU time 0.89 seconds
Started Aug 21 05:18:11 PM UTC 24
Finished Aug 21 05:18:13 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316969417 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.316969417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.749602272
Short name T243
Test name
Test status
Simulation time 17538156091 ps
CPU time 11.4 seconds
Started Aug 21 05:18:13 PM UTC 24
Finished Aug 21 05:18:25 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749602272 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.749602272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.3055751372
Short name T237
Test name
Test status
Simulation time 588914381 ps
CPU time 1.55 seconds
Started Aug 21 05:18:13 PM UTC 24
Finished Aug 21 05:18:15 PM UTC 24
Peak memory 199540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055751372 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3055751372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.4083467948
Short name T263
Test name
Test status
Simulation time 54160474764 ps
CPU time 44.77 seconds
Started Aug 21 05:18:16 PM UTC 24
Finished Aug 21 05:19:02 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083467948 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4083467948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.421974479
Short name T240
Test name
Test status
Simulation time 569246588 ps
CPU time 2.46 seconds
Started Aug 21 05:18:15 PM UTC 24
Finished Aug 21 05:18:18 PM UTC 24
Peak memory 200560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=421974479 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.421974479
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.605465399
Short name T252
Test name
Test status
Simulation time 35663083003 ps
CPU time 18.76 seconds
Started Aug 21 05:18:20 PM UTC 24
Finished Aug 21 05:18:40 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605465399 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.605465399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1363673969
Short name T241
Test name
Test status
Simulation time 557064279 ps
CPU time 1.51 seconds
Started Aug 21 05:18:20 PM UTC 24
Finished Aug 21 05:18:23 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363673969 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1363673969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3807339944
Short name T9
Test name
Test status
Simulation time 14421501858 ps
CPU time 2.96 seconds
Started Aug 21 05:16:29 PM UTC 24
Finished Aug 21 05:16:33 PM UTC 24
Peak memory 200620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3807339944 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3807339944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.2077352377
Short name T22
Test name
Test status
Simulation time 4061319118 ps
CPU time 9.57 seconds
Started Aug 21 05:16:33 PM UTC 24
Finished Aug 21 05:16:43 PM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077352377 -as
sert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2077352377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.3657507053
Short name T7
Test name
Test status
Simulation time 532652505 ps
CPU time 0.99 seconds
Started Aug 21 05:16:26 PM UTC 24
Finished Aug 21 05:16:29 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3657507053 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3657507053
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.2993090278
Short name T245
Test name
Test status
Simulation time 47440895156 ps
CPU time 7.36 seconds
Started Aug 21 05:18:23 PM UTC 24
Finished Aug 21 05:18:31 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2993090278 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2993090278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.2748551964
Short name T242
Test name
Test status
Simulation time 557675550 ps
CPU time 1.67 seconds
Started Aug 21 05:18:22 PM UTC 24
Finished Aug 21 05:18:24 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748551964 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2748551964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.1293011941
Short name T79
Test name
Test status
Simulation time 3018250654 ps
CPU time 14.68 seconds
Started Aug 21 05:18:25 PM UTC 24
Finished Aug 21 05:18:41 PM UTC 24
Peak memory 206624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293011941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1293011941
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.867679497
Short name T256
Test name
Test status
Simulation time 34877094964 ps
CPU time 20.49 seconds
Started Aug 21 05:18:27 PM UTC 24
Finished Aug 21 05:18:49 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867679497 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.867679497
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.4290538267
Short name T244
Test name
Test status
Simulation time 570511098 ps
CPU time 1.84 seconds
Started Aug 21 05:18:26 PM UTC 24
Finished Aug 21 05:18:29 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4290538267 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4290538267
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.231064540
Short name T249
Test name
Test status
Simulation time 5478134495 ps
CPU time 1.77 seconds
Started Aug 21 05:18:30 PM UTC 24
Finished Aug 21 05:18:33 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231064540 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.231064540
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1478195185
Short name T248
Test name
Test status
Simulation time 460937975 ps
CPU time 1.6 seconds
Started Aug 21 05:18:30 PM UTC 24
Finished Aug 21 05:18:33 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478195185 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1478195185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.4255118646
Short name T273
Test name
Test status
Simulation time 17730657098 ps
CPU time 41.83 seconds
Started Aug 21 05:18:33 PM UTC 24
Finished Aug 21 05:19:17 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4255118646 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4255118646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.2866821298
Short name T250
Test name
Test status
Simulation time 386288615 ps
CPU time 1.17 seconds
Started Aug 21 05:18:32 PM UTC 24
Finished Aug 21 05:18:35 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866821298 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2866821298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.1334951912
Short name T203
Test name
Test status
Simulation time 13085925385 ps
CPU time 21.76 seconds
Started Aug 21 05:18:36 PM UTC 24
Finished Aug 21 05:18:59 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1334951912 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1334951912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3201736869
Short name T251
Test name
Test status
Simulation time 366815315 ps
CPU time 1.18 seconds
Started Aug 21 05:18:35 PM UTC 24
Finished Aug 21 05:18:37 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3201736869 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3201736869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.908172743
Short name T262
Test name
Test status
Simulation time 10024268940 ps
CPU time 20.55 seconds
Started Aug 21 05:18:40 PM UTC 24
Finished Aug 21 05:19:01 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=908172743 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.908172743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.2834860631
Short name T253
Test name
Test status
Simulation time 362512062 ps
CPU time 1.45 seconds
Started Aug 21 05:18:40 PM UTC 24
Finished Aug 21 05:18:42 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834860631 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2834860631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.1198593148
Short name T259
Test name
Test status
Simulation time 1079361015 ps
CPU time 10.85 seconds
Started Aug 21 05:18:42 PM UTC 24
Finished Aug 21 05:18:54 PM UTC 24
Peak memory 215248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1198593148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1198593148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.1661970917
Short name T269
Test name
Test status
Simulation time 29623996378 ps
CPU time 24.91 seconds
Started Aug 21 05:18:43 PM UTC 24
Finished Aug 21 05:19:09 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661970917 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1661970917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.2281702274
Short name T254
Test name
Test status
Simulation time 481624040 ps
CPU time 1.85 seconds
Started Aug 21 05:18:43 PM UTC 24
Finished Aug 21 05:18:46 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2281702274 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2281702274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2846419315
Short name T265
Test name
Test status
Simulation time 6111886756 ps
CPU time 16.36 seconds
Started Aug 21 05:18:47 PM UTC 24
Finished Aug 21 05:19:05 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846419315 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2846419315
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.688571079
Short name T257
Test name
Test status
Simulation time 520195890 ps
CPU time 1.97 seconds
Started Aug 21 05:18:46 PM UTC 24
Finished Aug 21 05:18:49 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688571079 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.688571079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.1970562994
Short name T277
Test name
Test status
Simulation time 14466534063 ps
CPU time 35.44 seconds
Started Aug 21 05:18:49 PM UTC 24
Finished Aug 21 05:19:26 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970562994 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1970562994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.636237838
Short name T258
Test name
Test status
Simulation time 354242938 ps
CPU time 1.69 seconds
Started Aug 21 05:18:49 PM UTC 24
Finished Aug 21 05:18:52 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636237838 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.636237838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1953199145
Short name T281
Test name
Test status
Simulation time 46466353870 ps
CPU time 39.2 seconds
Started Aug 21 05:18:53 PM UTC 24
Finished Aug 21 05:19:33 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953199145 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1953199145
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.2851285148
Short name T260
Test name
Test status
Simulation time 423062869 ps
CPU time 1.36 seconds
Started Aug 21 05:18:52 PM UTC 24
Finished Aug 21 05:18:54 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2851285148 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2851285148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.1977120600
Short name T218
Test name
Test status
Simulation time 34503384136 ps
CPU time 50.73 seconds
Started Aug 21 05:16:34 PM UTC 24
Finished Aug 21 05:17:26 PM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1977120600 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1977120600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.1446824131
Short name T23
Test name
Test status
Simulation time 8571460690 ps
CPU time 18.53 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:16:56 PM UTC 24
Peak memory 231380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1446824131 -as
sert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1446824131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2141809649
Short name T24
Test name
Test status
Simulation time 583235308 ps
CPU time 2.77 seconds
Started Aug 21 05:16:34 PM UTC 24
Finished Aug 21 05:16:38 PM UTC 24
Peak memory 200572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2141809649 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2141809649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.2650293369
Short name T40
Test name
Test status
Simulation time 39700046178 ps
CPU time 40.28 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:17:18 PM UTC 24
Peak memory 214712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2650293369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2650293369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.3110568372
Short name T270
Test name
Test status
Simulation time 5089158704 ps
CPU time 13.63 seconds
Started Aug 21 05:18:56 PM UTC 24
Finished Aug 21 05:19:10 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3110568372 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3110568372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.527776240
Short name T228
Test name
Test status
Simulation time 594531874 ps
CPU time 0.96 seconds
Started Aug 21 05:18:56 PM UTC 24
Finished Aug 21 05:18:58 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=527776240 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.527776240
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.2376596768
Short name T267
Test name
Test status
Simulation time 1797878361 ps
CPU time 6.17 seconds
Started Aug 21 05:18:59 PM UTC 24
Finished Aug 21 05:19:06 PM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376596768 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2376596768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.1802618049
Short name T261
Test name
Test status
Simulation time 397359487 ps
CPU time 1.02 seconds
Started Aug 21 05:18:58 PM UTC 24
Finished Aug 21 05:19:00 PM UTC 24
Peak memory 199628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1802618049 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1802618049
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.617320275
Short name T279
Test name
Test status
Simulation time 18270044075 ps
CPU time 25.95 seconds
Started Aug 21 05:19:02 PM UTC 24
Finished Aug 21 05:19:29 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617320275 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.617320275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.973286290
Short name T264
Test name
Test status
Simulation time 546331205 ps
CPU time 0.9 seconds
Started Aug 21 05:19:02 PM UTC 24
Finished Aug 21 05:19:04 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=973286290 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.973286290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3065934326
Short name T275
Test name
Test status
Simulation time 8465587186 ps
CPU time 15.55 seconds
Started Aug 21 05:19:04 PM UTC 24
Finished Aug 21 05:19:21 PM UTC 24
Peak memory 200896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3065934326 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3065934326
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1687218193
Short name T266
Test name
Test status
Simulation time 605767429 ps
CPU time 1.31 seconds
Started Aug 21 05:19:03 PM UTC 24
Finished Aug 21 05:19:05 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1687218193 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1687218193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.854209692
Short name T285
Test name
Test status
Simulation time 43944797974 ps
CPU time 35.62 seconds
Started Aug 21 05:19:06 PM UTC 24
Finished Aug 21 05:19:43 PM UTC 24
Peak memory 200728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=854209692 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.854209692
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.885010195
Short name T268
Test name
Test status
Simulation time 480246647 ps
CPU time 0.96 seconds
Started Aug 21 05:19:06 PM UTC 24
Finished Aug 21 05:19:08 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=885010195 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.885010195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.1972662532
Short name T282
Test name
Test status
Simulation time 51522062426 ps
CPU time 26.34 seconds
Started Aug 21 05:19:10 PM UTC 24
Finished Aug 21 05:19:37 PM UTC 24
Peak memory 200896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1972662532 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1972662532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.1698547668
Short name T271
Test name
Test status
Simulation time 611973313 ps
CPU time 1.27 seconds
Started Aug 21 05:19:09 PM UTC 24
Finished Aug 21 05:19:12 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1698547668 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1698547668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2277009549
Short name T286
Test name
Test status
Simulation time 34117530954 ps
CPU time 39.65 seconds
Started Aug 21 05:19:13 PM UTC 24
Finished Aug 21 05:19:54 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2277009549 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2277009549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.53919697
Short name T272
Test name
Test status
Simulation time 582324773 ps
CPU time 1.18 seconds
Started Aug 21 05:19:12 PM UTC 24
Finished Aug 21 05:19:14 PM UTC 24
Peak memory 199636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53919697 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.53919697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.2243476114
Short name T280
Test name
Test status
Simulation time 8555669245 ps
CPU time 13.35 seconds
Started Aug 21 05:19:15 PM UTC 24
Finished Aug 21 05:19:29 PM UTC 24
Peak memory 200588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243476114 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2243476114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.217045657
Short name T274
Test name
Test status
Simulation time 413826413 ps
CPU time 1.14 seconds
Started Aug 21 05:19:15 PM UTC 24
Finished Aug 21 05:19:17 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217045657 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.217045657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.3444115544
Short name T283
Test name
Test status
Simulation time 8397888273 ps
CPU time 20.16 seconds
Started Aug 21 05:19:16 PM UTC 24
Finished Aug 21 05:19:37 PM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3444115544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3444115544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.2018192872
Short name T284
Test name
Test status
Simulation time 11697414519 ps
CPU time 20.39 seconds
Started Aug 21 05:19:18 PM UTC 24
Finished Aug 21 05:19:40 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2018192872 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2018192872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.640476279
Short name T276
Test name
Test status
Simulation time 328699017 ps
CPU time 1.62 seconds
Started Aug 21 05:19:18 PM UTC 24
Finished Aug 21 05:19:21 PM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=640476279 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.640476279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.1222704094
Short name T287
Test name
Test status
Simulation time 37745986579 ps
CPU time 62 seconds
Started Aug 21 05:19:24 PM UTC 24
Finished Aug 21 05:20:28 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1222704094 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1222704094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.367772104
Short name T278
Test name
Test status
Simulation time 580089075 ps
CPU time 2.53 seconds
Started Aug 21 05:19:23 PM UTC 24
Finished Aug 21 05:19:27 PM UTC 24
Peak memory 200560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=367772104 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.367772104
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.1659020311
Short name T49
Test name
Test status
Simulation time 36797218980 ps
CPU time 20.35 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:16:58 PM UTC 24
Peak memory 200824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659020311 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1659020311
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.4241766732
Short name T15
Test name
Test status
Simulation time 535582196 ps
CPU time 1.13 seconds
Started Aug 21 05:16:36 PM UTC 24
Finished Aug 21 05:16:38 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241766732 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4241766732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3058918564
Short name T204
Test name
Test status
Simulation time 27567756980 ps
CPU time 39.24 seconds
Started Aug 21 05:16:39 PM UTC 24
Finished Aug 21 05:17:19 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3058918564 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3058918564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.4049487951
Short name T45
Test name
Test status
Simulation time 601290030 ps
CPU time 1.29 seconds
Started Aug 21 05:16:39 PM UTC 24
Finished Aug 21 05:16:41 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4049487951 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4049487951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.2319538748
Short name T47
Test name
Test status
Simulation time 34465170696 ps
CPU time 7.96 seconds
Started Aug 21 05:16:43 PM UTC 24
Finished Aug 21 05:16:52 PM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2319538748 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2319538748
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.4025853607
Short name T211
Test name
Test status
Simulation time 396844890 ps
CPU time 1.63 seconds
Started Aug 21 05:16:43 PM UTC 24
Finished Aug 21 05:16:46 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025853607 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4025853607
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.1850305113
Short name T50
Test name
Test status
Simulation time 28605227761 ps
CPU time 8.26 seconds
Started Aug 21 05:16:49 PM UTC 24
Finished Aug 21 05:16:58 PM UTC 24
Peak memory 200824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1850305113 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1850305113
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.2210926428
Short name T27
Test name
Test status
Simulation time 590607926 ps
CPU time 1.4 seconds
Started Aug 21 05:16:47 PM UTC 24
Finished Aug 21 05:16:49 PM UTC 24
Peak memory 199632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2210926428 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2210926428
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.3164636844
Short name T199
Test name
Test status
Simulation time 14155371010 ps
CPU time 42.25 seconds
Started Aug 21 05:16:52 PM UTC 24
Finished Aug 21 05:17:36 PM UTC 24
Peak memory 206456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
aces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3164636844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_time
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3164636844
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.1351072834
Short name T209
Test name
Test status
Simulation time 41427242678 ps
CPU time 15.23 seconds
Started Aug 21 05:16:53 PM UTC 24
Finished Aug 21 05:17:10 PM UTC 24
Peak memory 200620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1351072834 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1351072834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.931852240
Short name T78
Test name
Test status
Simulation time 505785606 ps
CPU time 0.87 seconds
Started Aug 21 05:16:52 PM UTC 24
Finished Aug 21 05:16:54 PM UTC 24
Peak memory 199364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=931852240 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.931852240
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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