Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	18326	1			T1	11		T4	10		T5	12
bark[1]	642	1			T37	244		T140	14		T136	14
bark[2]	602	1			T31	21		T95	14		T174	14
bark[3]	439	1			T45	237		T190	14		T132	21
bark[4]	241	1			T16	21		T131	7		T124	71
bark[5]	140	1			T194	14		T111	14		T116	21
bark[6]	279	1			T22	21		T81	14		T101	30
bark[7]	230	1			T28	14		T101	40		T118	21
bark[8]	196	1			T52	14		T131	21		T142	21
bark[9]	345	1			T27	14		T46	52		T140	21
bark[10]	363	1			T15	21		T21	90		T127	66
bark[11]	760	1			T44	5		T37	237		T80	7
bark[12]	212	1			T18	21		T131	109		T184	14
bark[13]	308	1			T16	26		T45	47		T164	5
bark[14]	194	1			T15	21		T89	42		T81	21
bark[15]	355	1			T26	14		T21	21		T36	14
bark[16]	148	1			T161	21		T183	52		T118	21
bark[17]	338	1			T45	21		T121	99		T82	79
bark[18]	467	1			T18	90		T140	21		T81	21
bark[19]	578	1			T13	90		T44	35		T147	14
bark[20]	225	1			T46	21		T143	14		T118	35
bark[21]	154	1			T18	5		T31	7		T127	21
bark[22]	312	1			T131	103		T157	14		T101	26
bark[23]	215	1			T7	14		T165	14		T22	67
bark[24]	364	1			T15	21		T32	14		T17	21
bark[25]	277	1			T15	91		T140	21		T175	14
bark[26]	502	1			T18	31		T21	19		T140	35
bark[27]	447	1			T3	14		T51	14		T127	7
bark[28]	188	1			T2	14		T15	42		T46	5
bark[29]	153	1			T159	38		T169	54		T125	61
bark[30]	395	1			T25	14		T37	7		T191	14
bark[31]	508	1			T21	21		T31	107		T46	5
bark_0	4714	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	18081	1			T1	10		T4	9		T5	11
bite[1]	576	1			T15	42		T18	21		T22	21
bite[2]	348	1			T3	13		T121	21		T137	76
bite[3]	456	1			T51	13		T37	236		T135	51
bite[4]	222	1			T25	13		T45	21		T46	59
bite[5]	242	1			T18	4		T124	63		T93	6
bite[6]	463	1			T124	6		T93	4		T111	13
bite[7]	304	1			T17	21		T140	21		T168	52
bite[8]	244	1			T21	69		T22	52		T121	21
bite[9]	328	1			T31	21		T124	127		T168	35
bite[10]	161	1			T21	18		T140	21		T89	21
bite[11]	232	1			T118	13		T141	26		T126	21
bite[12]	581	1			T27	13		T127	6		T22	66
bite[13]	330	1			T52	13		T46	4		T140	21
bite[14]	439	1			T89	21		T81	21		T135	21
bite[15]	124	1			T127	35		T162	30		T94	59
bite[16]	313	1			T7	13		T15	21		T18	38
bite[17]	275	1			T31	26		T95	13		T140	21
bite[18]	229	1			T13	6		T31	6		T140	26
bite[19]	311	1			T146	13		T121	99		T129	30
bite[20]	260	1			T13	82		T174	13		T22	21
bite[21]	233	1			T36	13		T150	13		T203	4
bite[22]	365	1			T28	13		T45	21		T190	13
bite[23]	303	1			T46	81		T127	21		T161	21
bite[24]	522	1			T2	13		T15	91		T46	4
bite[25]	338	1			T16	46		T21	21		T45	25
bite[26]	270	1			T45	236		T158	13		T99	21
bite[27]	341	1			T32	13		T18	89		T46	43
bite[28]	339	1			T15	42		T127	30		T194	13
bite[29]	157	1			T101	13		T118	21		T116	6
bite[30]	674	1			T26	13		T21	21		T31	199
bite[31]	386	1			T165	13		T164	21		T101	21
bite_0	5170	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30118

1

T1

11

T2

21

T3

21

auto[1]

3499

1

T1

7

T17

237

T29

7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	496	1			T14	9		T37	81		T127	9
prescale[1]	416	1			T21	19		T31	2		T44	26
prescale[2]	673	1			T9	9		T15	53		T16	2
prescale[3]	279	1			T5	9		T19	2		T50	9
prescale[4]	291	1			T19	19		T31	43		T37	19
prescale[5]	561	1			T17	19		T18	9		T142	51
prescale[6]	583	1			T17	57		T18	2		T37	2
prescale[7]	703	1			T13	2		T15	60		T37	2
prescale[8]	319	1			T13	2		T45	2		T89	23
prescale[9]	390	1			T45	19		T46	24		T121	23
prescale[10]	188	1			T16	2		T204	9		T46	2
prescale[11]	362	1			T18	2		T19	2		T45	2
prescale[12]	497	1			T21	19		T37	79		T140	11
prescale[13]	263	1			T16	2		T17	2		T44	2
prescale[14]	454	1			T17	9		T37	104		T140	46
prescale[15]	340	1			T45	2		T131	42		T81	19
prescale[16]	255	1			T127	2		T131	2		T144	36
prescale[17]	256	1			T45	28		T144	40		T135	2
prescale[18]	263	1			T35	9		T37	2		T127	2
prescale[19]	870	1			T16	2		T45	19		T127	9
prescale[20]	385	1			T44	57		T46	2		T127	2
prescale[21]	238	1			T8	9		T87	9		T80	2
prescale[22]	297	1			T31	47		T205	9		T131	2
prescale[23]	634	1			T13	4		T18	2		T44	2
prescale[24]	411	1			T17	63		T18	2		T206	9
prescale[25]	375	1			T37	2		T124	2		T144	66
prescale[26]	345	1			T19	9		T81	31		T142	2
prescale[27]	378	1			T19	2		T49	9		T44	2
prescale[28]	379	1			T37	19		T45	4		T46	40
prescale[29]	364	1			T17	19		T31	36		T207	9
prescale[30]	560	1			T17	36		T31	40		T22	61
prescale[31]	342	1			T18	2		T46	9		T127	36
prescale_0	20450	1			T1	18		T2	21		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22033

1

T1

9

T2

21

T3

21

auto[1]

11584

1

T1

9

T9

10

T13

47

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

33617

1

T1

18

T2

21

T3

21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	18839	1			T1	13		T2	1		T3	1
wkup[1]	120	1			T13	26		T46	21		T140	21
wkup[2]	286	1			T16	21		T21	21		T31	26
wkup[3]	72	1			T123	21		T139	21		T102	30
wkup[4]	66	1			T37	30		T110	21		T119	15
wkup[5]	104	1			T116	42		T179	26		T99	6
wkup[6]	209	1			T15	21		T22	21		T131	30
wkup[7]	228	1			T161	21		T93	21		T98	15
wkup[8]	336	1			T31	21		T127	21		T151	15
wkup[9]	292	1			T18	26		T89	21		T131	21
wkup[10]	299	1			T3	15		T21	21		T150	15
wkup[11]	204	1			T27	15		T21	48		T45	21
wkup[12]	130	1			T37	21		T22	21		T194	15
wkup[13]	156	1			T45	21		T144	21		T159	30
wkup[14]	123	1			T15	21		T127	21		T146	15
wkup[15]	131	1			T81	21		T135	26		T85	21
wkup[16]	135	1			T22	21		T124	42		T121	21
wkup[17]	182	1			T21	20		T52	15		T46	21
wkup[18]	132	1			T46	21		T121	21		T126	21
wkup[19]	193	1			T45	21		T82	30		T135	26
wkup[20]	86	1			T19	21		T135	8		T149	21
wkup[21]	179	1			T13	8		T15	21		T89	21
wkup[22]	211	1			T15	21		T82	42		T115	21
wkup[23]	93	1			T36	15		T31	21		T140	15
wkup[24]	168	1			T15	21		T45	21		T46	21
wkup[25]	344	1			T13	35		T16	21		T32	15
wkup[26]	144	1			T124	21		T111	15		T167	15
wkup[27]	145	1			T45	15		T161	21		T116	21
wkup[28]	180	1			T26	15		T45	21		T132	21
wkup[29]	71	1			T37	8		T120	21		T112	21
wkup[30]	146	1			T18	6		T21	21		T131	8
wkup[31]	150	1			T46	45		T93	6		T116	21
wkup[32]	163	1			T51	15		T31	47		T46	6
wkup[33]	277	1			T19	39		T45	21		T131	35
wkup[34]	223	1			T17	21		T31	21		T81	26
wkup[35]	98	1			T46	14		T129	21		T123	21
wkup[36]	201	1			T45	15		T131	21		T121	21
wkup[37]	148	1			T136	15		T160	35		T163	35
wkup[38]	203	1			T21	21		T140	36		T174	15
wkup[39]	211	1			T15	21		T140	15		T22	26
wkup[40]	232	1			T19	21		T45	21		T80	8
wkup[41]	60	1			T44	21		T95	15		T152	24
wkup[42]	158	1			T31	8		T93	21		T116	21
wkup[43]	324	1			T31	21		T46	35		T127	21
wkup[44]	261	1			T45	21		T46	21		T89	21
wkup[45]	183	1			T15	21		T37	21		T140	21
wkup[46]	112	1			T37	26		T127	8		T81	21
wkup[47]	177	1			T46	40		T127	21		T80	21
wkup[48]	131	1			T18	21		T37	26		T131	21
wkup[49]	169	1			T17	35		T44	6		T121	21
wkup[50]	154	1			T132	21		T121	21		T93	15
wkup[51]	261	1			T89	21		T181	49		T103	15
wkup[52]	92	1			T25	15		T116	26		T105	21
wkup[53]	179	1			T28	15		T45	42		T203	8
wkup[54]	124	1			T118	36		T116	30		T113	31
wkup[55]	92	1			T144	21		T101	42		T90	8
wkup[56]	123	1			T2	15		T127	30		T81	21
wkup[57]	188	1			T18	21		T37	21		T168	26
wkup[58]	156	1			T37	21		T190	15		T192	21
wkup[59]	198	1			T7	15		T19	21		T121	21
wkup[60]	206	1			T15	21		T18	21		T140	21
wkup[61]	230	1			T18	21		T44	15		T127	21
wkup[62]	235	1			T127	35		T80	21		T131	21
wkup[63]	193	1			T37	21		T124	21		T81	21
wkup_0	3701	1			T1	5		T2	5		T3	5