| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.61 | 99.33 | 95.61 | 100.00 | 98.40 | 99.51 | 44.84 |
| T291 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1789717610 | Aug 23 09:18:26 PM UTC 24 | Aug 23 09:18:28 PM UTC 24 | 393057891 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.219032633 | Aug 23 09:18:26 PM UTC 24 | Aug 23 09:18:28 PM UTC 24 | 1258506660 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.857534102 | Aug 23 09:18:27 PM UTC 24 | Aug 23 09:18:29 PM UTC 24 | 460125994 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1581417665 | Aug 23 09:18:27 PM UTC 24 | Aug 23 09:18:29 PM UTC 24 | 411893953 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2584335667 | Aug 23 09:18:29 PM UTC 24 | Aug 23 09:18:31 PM UTC 24 | 346068128 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2193984110 | Aug 23 09:18:29 PM UTC 24 | Aug 23 09:18:31 PM UTC 24 | 533429272 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1659644070 | Aug 23 09:18:29 PM UTC 24 | Aug 23 09:18:31 PM UTC 24 | 495174265 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3278790309 | Aug 23 09:18:28 PM UTC 24 | Aug 23 09:18:32 PM UTC 24 | 1551692246 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2797198273 | Aug 23 09:18:30 PM UTC 24 | Aug 23 09:18:32 PM UTC 24 | 286223761 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2098824600 | Aug 23 09:18:29 PM UTC 24 | Aug 23 09:18:32 PM UTC 24 | 792219244 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3789404963 | Aug 23 09:18:29 PM UTC 24 | Aug 23 09:18:32 PM UTC 24 | 9322945561 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.776319611 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:34 PM UTC 24 | 332566412 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1268943212 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:34 PM UTC 24 | 576555406 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2725517333 | Aug 23 09:18:31 PM UTC 24 | Aug 23 09:18:34 PM UTC 24 | 1132774241 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2252064517 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:35 PM UTC 24 | 519947972 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.609383931 | Aug 23 09:18:33 PM UTC 24 | Aug 23 09:18:35 PM UTC 24 | 334518636 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3859144723 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:35 PM UTC 24 | 532349604 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3593407434 | Aug 23 09:18:34 PM UTC 24 | Aug 23 09:18:36 PM UTC 24 | 491544045 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1221129050 | Aug 23 09:18:34 PM UTC 24 | Aug 23 09:18:36 PM UTC 24 | 478052424 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3042767867 | Aug 23 09:18:27 PM UTC 24 | Aug 23 09:18:37 PM UTC 24 | 7024225363 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.969433101 | Aug 23 09:18:36 PM UTC 24 | Aug 23 09:18:37 PM UTC 24 | 1029438346 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2753225342 | Aug 23 09:18:36 PM UTC 24 | Aug 23 09:18:38 PM UTC 24 | 587977961 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2175128567 | Aug 23 09:18:36 PM UTC 24 | Aug 23 09:18:38 PM UTC 24 | 452908112 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3872567224 | Aug 23 09:18:33 PM UTC 24 | Aug 23 09:18:38 PM UTC 24 | 8940496369 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.947317445 | Aug 23 09:18:37 PM UTC 24 | Aug 23 09:18:39 PM UTC 24 | 379680118 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3571332159 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:39 PM UTC 24 | 2543897863 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1651536773 | Aug 23 09:18:37 PM UTC 24 | Aug 23 09:18:40 PM UTC 24 | 705481783 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2146718121 | Aug 23 09:18:38 PM UTC 24 | Aug 23 09:18:40 PM UTC 24 | 343507170 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.4109430488 | Aug 23 09:18:38 PM UTC 24 | Aug 23 09:18:40 PM UTC 24 | 384303362 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2094895806 | Aug 23 09:18:39 PM UTC 24 | Aug 23 09:18:41 PM UTC 24 | 280934544 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.539191030 | Aug 23 09:18:39 PM UTC 24 | Aug 23 09:18:41 PM UTC 24 | 1070497133 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4163986039 | Aug 23 09:18:39 PM UTC 24 | Aug 23 09:18:41 PM UTC 24 | 498688435 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3480870211 | Aug 23 09:18:36 PM UTC 24 | Aug 23 09:18:42 PM UTC 24 | 6203983430 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2945647305 | Aug 23 09:18:37 PM UTC 24 | Aug 23 09:18:42 PM UTC 24 | 2712932427 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2941078543 | Aug 23 09:18:38 PM UTC 24 | Aug 23 09:18:42 PM UTC 24 | 4490182544 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2760266981 | Aug 23 09:18:40 PM UTC 24 | Aug 23 09:18:42 PM UTC 24 | 557779617 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.690422036 | Aug 23 09:18:32 PM UTC 24 | Aug 23 09:18:43 PM UTC 24 | 6908462582 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2581420960 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:43 PM UTC 24 | 487371446 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.3807616147 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:43 PM UTC 24 | 478976932 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.763532974 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:43 PM UTC 24 | 324751307 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1250910785 | Aug 23 09:18:42 PM UTC 24 | Aug 23 09:18:44 PM UTC 24 | 304848379 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2533925374 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:44 PM UTC 24 | 652958042 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4142963491 | Aug 23 09:18:42 PM UTC 24 | Aug 23 09:18:44 PM UTC 24 | 516620566 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3863727399 | Aug 23 09:18:42 PM UTC 24 | Aug 23 09:18:45 PM UTC 24 | 679960193 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3094580112 | Aug 23 09:18:40 PM UTC 24 | Aug 23 09:18:45 PM UTC 24 | 7514458183 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1426267512 | Aug 23 09:18:44 PM UTC 24 | Aug 23 09:18:45 PM UTC 24 | 441158462 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1007206398 | Aug 23 09:18:44 PM UTC 24 | Aug 23 09:18:45 PM UTC 24 | 566680593 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1666969348 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:45 PM UTC 24 | 2557213814 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2788216036 | Aug 23 09:18:44 PM UTC 24 | Aug 23 09:18:46 PM UTC 24 | 1365596330 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1747476658 | Aug 23 09:18:44 PM UTC 24 | Aug 23 09:18:46 PM UTC 24 | 516413416 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4185532185 | Aug 23 09:18:45 PM UTC 24 | Aug 23 09:18:46 PM UTC 24 | 477330652 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2333564642 | Aug 23 09:18:45 PM UTC 24 | Aug 23 09:18:47 PM UTC 24 | 413594891 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.257823567 | Aug 23 09:18:45 PM UTC 24 | Aug 23 09:18:47 PM UTC 24 | 473782343 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.131295744 | Aug 23 09:18:45 PM UTC 24 | Aug 23 09:18:47 PM UTC 24 | 1910317078 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1965487993 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:48 PM UTC 24 | 399518834 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.171169758 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:48 PM UTC 24 | 339932270 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2569403786 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:48 PM UTC 24 | 502697129 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2545537495 | Aug 23 09:18:47 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 4532812260 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3721622731 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:48 PM UTC 24 | 1158080421 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1161976330 | Aug 23 09:18:42 PM UTC 24 | Aug 23 09:18:48 PM UTC 24 | 4830439429 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.997908119 | Aug 23 09:18:47 PM UTC 24 | Aug 23 09:18:49 PM UTC 24 | 465054409 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1486438063 | Aug 23 09:18:41 PM UTC 24 | Aug 23 09:18:49 PM UTC 24 | 4508822510 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1107982227 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 2914349738 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1957852931 | Aug 23 09:18:48 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 301152453 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1618839974 | Aug 23 09:18:46 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 7577917529 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.405055751 | Aug 23 09:18:47 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 688796121 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3480054640 | Aug 23 09:18:48 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 455428868 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4243112705 | Aug 23 09:18:48 PM UTC 24 | Aug 23 09:18:50 PM UTC 24 | 518992036 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.797213983 | Aug 23 09:18:49 PM UTC 24 | Aug 23 09:18:51 PM UTC 24 | 300793549 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.823325020 | Aug 23 09:18:49 PM UTC 24 | Aug 23 09:18:51 PM UTC 24 | 428330752 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3528590847 | Aug 23 09:18:48 PM UTC 24 | Aug 23 09:18:51 PM UTC 24 | 2298282296 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.754656253 | Aug 23 09:18:49 PM UTC 24 | Aug 23 09:18:51 PM UTC 24 | 357499426 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.72400743 | Aug 23 09:18:49 PM UTC 24 | Aug 23 09:18:52 PM UTC 24 | 1579972343 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3831482366 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:52 PM UTC 24 | 340680690 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3336034771 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:52 PM UTC 24 | 502820119 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4150133100 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:53 PM UTC 24 | 472074637 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.386496578 | Aug 23 09:18:49 PM UTC 24 | Aug 23 09:18:53 PM UTC 24 | 4504783445 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1110273071 | Aug 23 09:18:51 PM UTC 24 | Aug 23 09:18:53 PM UTC 24 | 415948134 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.2191067200 | Aug 23 09:18:52 PM UTC 24 | Aug 23 09:18:53 PM UTC 24 | 348667154 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3986957850 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:53 PM UTC 24 | 678240502 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.403339980 | Aug 23 09:18:52 PM UTC 24 | Aug 23 09:18:54 PM UTC 24 | 626867304 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2195447565 | Aug 23 09:18:52 PM UTC 24 | Aug 23 09:18:54 PM UTC 24 | 471583830 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3625190922 | Aug 23 09:18:52 PM UTC 24 | Aug 23 09:18:54 PM UTC 24 | 791728262 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2460592735 | Aug 23 09:18:53 PM UTC 24 | Aug 23 09:18:55 PM UTC 24 | 322359607 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3058222549 | Aug 23 09:18:53 PM UTC 24 | Aug 23 09:18:55 PM UTC 24 | 427748469 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2805638315 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:55 PM UTC 24 | 8589849588 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3090568099 | Aug 23 09:18:50 PM UTC 24 | Aug 23 09:18:55 PM UTC 24 | 1457047472 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3203263661 | Aug 23 09:18:53 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 2778053679 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3412433718 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 325473383 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2837791889 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 364440341 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3160254443 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 1534490128 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1851300992 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 306484027 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3018129774 | Aug 23 09:18:44 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 8982979489 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.89013878 | Aug 23 09:18:53 PM UTC 24 | Aug 23 09:18:56 PM UTC 24 | 4600792336 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1220334510 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:57 PM UTC 24 | 512745273 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1554352083 | Aug 23 09:18:51 PM UTC 24 | Aug 23 09:18:57 PM UTC 24 | 4841344653 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3548647617 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:57 PM UTC 24 | 479647767 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.4158910837 | Aug 23 09:18:55 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 480000989 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3530990333 | Aug 23 09:18:55 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 429598786 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2459576102 | Aug 23 09:18:56 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 444047521 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1071985070 | Aug 23 09:18:56 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 337455916 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2995349782 | Aug 23 09:18:57 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 414939234 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2139773480 | Aug 23 09:18:52 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 2400450501 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.4078670697 | Aug 23 09:18:57 PM UTC 24 | Aug 23 09:18:58 PM UTC 24 | 360096049 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.568996368 | Aug 23 09:18:57 PM UTC 24 | Aug 23 09:18:59 PM UTC 24 | 351765679 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2049402146 | Aug 23 09:18:54 PM UTC 24 | Aug 23 09:18:59 PM UTC 24 | 3998867110 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.816459164 | Aug 23 09:18:58 PM UTC 24 | Aug 23 09:18:59 PM UTC 24 | 555497452 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.807430027 | Aug 23 09:18:56 PM UTC 24 | Aug 23 09:18:59 PM UTC 24 | 2360595574 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3931393968 | Aug 23 09:18:58 PM UTC 24 | Aug 23 09:19:00 PM UTC 24 | 385181122 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.730116186 | Aug 23 09:18:57 PM UTC 24 | Aug 23 09:19:00 PM UTC 24 | 8067134137 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3767367985 | Aug 23 09:18:58 PM UTC 24 | Aug 23 09:19:00 PM UTC 24 | 429968866 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.2488462101 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 400914913 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1484978371 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 383665836 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1891058045 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 408723869 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2023638635 | Aug 23 09:18:58 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 4447794054 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3448343483 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 1269716515 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3565002395 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 505203225 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.1324813444 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 549058560 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2477232559 | Aug 23 09:18:59 PM UTC 24 | Aug 23 09:19:01 PM UTC 24 | 4244805051 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1720080098 | Aug 23 09:19:00 PM UTC 24 | Aug 23 09:19:02 PM UTC 24 | 366566572 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.301837839 | Aug 23 09:19:00 PM UTC 24 | Aug 23 09:19:02 PM UTC 24 | 364052636 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2948536484 | Aug 23 09:18:58 PM UTC 24 | Aug 23 09:19:03 PM UTC 24 | 1474445118 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2494236614 | Aug 23 09:19:00 PM UTC 24 | Aug 23 09:19:03 PM UTC 24 | 520443630 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.542269387 | Aug 23 09:19:01 PM UTC 24 | Aug 23 09:19:03 PM UTC 24 | 548363295 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3769905525 | Aug 23 09:19:01 PM UTC 24 | Aug 23 09:19:03 PM UTC 24 | 390861963 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3308426357 | Aug 23 09:19:01 PM UTC 24 | Aug 23 09:19:04 PM UTC 24 | 1563111398 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.150428501 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:04 PM UTC 24 | 488348831 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1214216636 | Aug 23 09:19:01 PM UTC 24 | Aug 23 09:19:04 PM UTC 24 | 392778095 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3776762502 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:04 PM UTC 24 | 490071749 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3841242043 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:04 PM UTC 24 | 497829254 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1726528356 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:05 PM UTC 24 | 523307731 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.233498023 | Aug 23 09:19:03 PM UTC 24 | Aug 23 09:19:05 PM UTC 24 | 325458360 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2706081018 | Aug 23 09:19:04 PM UTC 24 | Aug 23 09:19:05 PM UTC 24 | 412732248 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.881654055 | Aug 23 09:19:04 PM UTC 24 | Aug 23 09:19:05 PM UTC 24 | 400655960 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3441327299 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 1305137586 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3740949601 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 645658806 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1197953005 | Aug 23 09:19:04 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 430494992 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1073013228 | Aug 23 09:19:00 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 2346356999 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.1893561820 | Aug 23 09:19:05 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 407885687 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2932101458 | Aug 23 09:19:05 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 323144413 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.330672297 | Aug 23 09:19:04 PM UTC 24 | Aug 23 09:19:06 PM UTC 24 | 2135393620 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3876205088 | Aug 23 09:19:05 PM UTC 24 | Aug 23 09:19:07 PM UTC 24 | 412350014 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.963366777 | Aug 23 09:19:01 PM UTC 24 | Aug 23 09:19:07 PM UTC 24 | 8329620366 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4006569878 | Aug 23 09:19:05 PM UTC 24 | Aug 23 09:19:07 PM UTC 24 | 472846445 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.745473611 | Aug 23 09:19:05 PM UTC 24 | Aug 23 09:19:07 PM UTC 24 | 471130768 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1132783827 | Aug 23 09:19:02 PM UTC 24 | Aug 23 09:19:07 PM UTC 24 | 7914334165 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.2799249377 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 483479290 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3326897739 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 426857978 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2345046859 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 370716102 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.1617757972 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 329345221 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.4201382366 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 357358556 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2568648584 | Aug 23 09:19:06 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 380231980 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3945976768 | Aug 23 09:18:55 PM UTC 24 | Aug 23 09:19:08 PM UTC 24 | 8149391457 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3610211001 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 339544159 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2485201513 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 523285158 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3545157825 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 413576899 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.600125006 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 375005488 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3438221944 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 468375477 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2789627962 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 480573440 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.4012516559 | Aug 23 09:19:07 PM UTC 24 | Aug 23 09:19:09 PM UTC 24 | 492833203 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.3570153774 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:10 PM UTC 24 | 465518070 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3572020986 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:10 PM UTC 24 | 554661781 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2782513559 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:10 PM UTC 24 | 410153327 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2631419652 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:10 PM UTC 24 | 321308232 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3578695359 | Aug 23 09:19:09 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 391402103 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.4099425941 | Aug 23 09:19:09 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 307362192 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.3862456381 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 332576609 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2677716523 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 437833223 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4102134562 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 408378806 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.935764560 | Aug 23 09:19:08 PM UTC 24 | Aug 23 09:19:11 PM UTC 24 | 409229180 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1936532198 | Aug 23 09:19:00 PM UTC 24 | Aug 23 09:19:14 PM UTC 24 | 8963603938 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.812589379 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7899380660 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:21 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812589379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.812589379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2749377988 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4300980106 ps |
| CPU time | 27.5 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:45 PM UTC 24 |
| Peak memory | 215352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2749377988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.2749377988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.3120215926 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 43430556397 ps |
| CPU time | 15.32 seconds |
| Started | Aug 23 09:14:20 PM UTC 24 |
| Finished | Aug 23 09:14:37 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120215926 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.3120215926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3426853183 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4489972948 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 09:18:23 PM UTC 24 |
| Finished | Aug 23 09:18:26 PM UTC 24 |
| Peak memory | 205508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426853183 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.3426853183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.3950620775 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3216614915 ps |
| CPU time | 5.67 seconds |
| Started | Aug 23 09:14:21 PM UTC 24 |
| Finished | Aug 23 09:14:28 PM UTC 24 |
| Peak memory | 206116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3950620775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.aon_timer_stress_all_with_rand_reset.3950620775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.1453879072 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4808746039 ps |
| CPU time | 34.32 seconds |
| Started | Aug 23 09:16:42 PM UTC 24 |
| Finished | Aug 23 09:17:18 PM UTC 24 |
| Peak memory | 203084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1453879072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.aon_timer_stress_all_with_rand_reset.1453879072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2252064517 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 519947972 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:35 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252064517 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2252064517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.1924661138 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 13434004903 ps |
| CPU time | 29.37 seconds |
| Started | Aug 23 09:16:53 PM UTC 24 |
| Finished | Aug 23 09:17:24 PM UTC 24 |
| Peak memory | 206624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1924661138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.aon_timer_stress_all_with_rand_reset.1924661138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1443564726 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5014148764 ps |
| CPU time | 35.15 seconds |
| Started | Aug 23 09:17:01 PM UTC 24 |
| Finished | Aug 23 09:17:38 PM UTC 24 |
| Peak memory | 214980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1443564726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 31.aon_timer_stress_all_with_rand_reset.1443564726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.3075127128 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 69650869889 ps |
| CPU time | 39.89 seconds |
| Started | Aug 23 09:15:53 PM UTC 24 |
| Finished | Aug 23 09:16:34 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075127128 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.3075127128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.1586125968 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 63747942132 ps |
| CPU time | 21.37 seconds |
| Started | Aug 23 09:15:40 PM UTC 24 |
| Finished | Aug 23 09:16:03 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586125968 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.1586125968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.2201386489 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4396718669 ps |
| CPU time | 2.15 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:20 PM UTC 24 |
| Peak memory | 231336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201386489 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2201386489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2773820278 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 84374747887 ps |
| CPU time | 13.65 seconds |
| Started | Aug 23 09:16:38 PM UTC 24 |
| Finished | Aug 23 09:16:53 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773820278 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2773820278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1822021334 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 141657672597 ps |
| CPU time | 49.26 seconds |
| Started | Aug 23 09:16:48 PM UTC 24 |
| Finished | Aug 23 09:17:39 PM UTC 24 |
| Peak memory | 200908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822021334 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1822021334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.4240865170 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 63644145605 ps |
| CPU time | 41.79 seconds |
| Started | Aug 23 09:15:03 PM UTC 24 |
| Finished | Aug 23 09:15:47 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240865170 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.4240865170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.4262310766 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 6358697067 ps |
| CPU time | 27.2 seconds |
| Started | Aug 23 09:17:50 PM UTC 24 |
| Finished | Aug 23 09:18:19 PM UTC 24 |
| Peak memory | 201032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4262310766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.aon_timer_stress_all_with_rand_reset.4262310766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.880024860 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3787972890 ps |
| CPU time | 19.76 seconds |
| Started | Aug 23 09:17:41 PM UTC 24 |
| Finished | Aug 23 09:18:02 PM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=880024860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.aon_timer_stress_all_with_rand_reset.880024860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.2311061524 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 70011908434 ps |
| CPU time | 102.75 seconds |
| Started | Aug 23 09:17:45 PM UTC 24 |
| Finished | Aug 23 09:19:30 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311061524 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.2311061524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.327330664 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 19435732120 ps |
| CPU time | 12.76 seconds |
| Started | Aug 23 09:17:54 PM UTC 24 |
| Finished | Aug 23 09:18:08 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327330664 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.327330664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.782671059 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3599541408 ps |
| CPU time | 5.17 seconds |
| Started | Aug 23 09:14:48 PM UTC 24 |
| Finished | Aug 23 09:14:54 PM UTC 24 |
| Peak memory | 200696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782671059 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.782671059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.4266369340 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 81860931842 ps |
| CPU time | 28.13 seconds |
| Started | Aug 23 09:15:32 PM UTC 24 |
| Finished | Aug 23 09:16:02 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266369340 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.4266369340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.2463602987 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 95846670905 ps |
| CPU time | 124.32 seconds |
| Started | Aug 23 09:16:06 PM UTC 24 |
| Finished | Aug 23 09:18:13 PM UTC 24 |
| Peak memory | 200940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463602987 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.2463602987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.3362837513 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2765311752 ps |
| CPU time | 12.4 seconds |
| Started | Aug 23 09:14:49 PM UTC 24 |
| Finished | Aug 23 09:15:02 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3362837513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.aon_timer_stress_all_with_rand_reset.3362837513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1886874545 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 137125868608 ps |
| CPU time | 86.26 seconds |
| Started | Aug 23 09:18:16 PM UTC 24 |
| Finished | Aug 23 09:19:44 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886874545 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1886874545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.2312293506 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 9666476465 ps |
| CPU time | 23.88 seconds |
| Started | Aug 23 09:15:03 PM UTC 24 |
| Finished | Aug 23 09:15:29 PM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2312293506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.2312293506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2080532569 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7930234585 ps |
| CPU time | 24.01 seconds |
| Started | Aug 23 09:17:24 PM UTC 24 |
| Finished | Aug 23 09:17:50 PM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2080532569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.aon_timer_stress_all_with_rand_reset.2080532569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.3143792453 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 156135236182 ps |
| CPU time | 226.3 seconds |
| Started | Aug 23 09:14:26 PM UTC 24 |
| Finished | Aug 23 09:18:16 PM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143792453 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.3143792453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.1108413944 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2653795509 ps |
| CPU time | 17.79 seconds |
| Started | Aug 23 09:15:30 PM UTC 24 |
| Finished | Aug 23 09:15:49 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1108413944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 13.aon_timer_stress_all_with_rand_reset.1108413944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.959268935 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 10827522869 ps |
| CPU time | 32.58 seconds |
| Started | Aug 23 09:17:53 PM UTC 24 |
| Finished | Aug 23 09:18:27 PM UTC 24 |
| Peak memory | 206496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=959268935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.aon_timer_stress_all_with_rand_reset.959268935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.955976775 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 367780931834 ps |
| CPU time | 91.08 seconds |
| Started | Aug 23 09:17:14 PM UTC 24 |
| Finished | Aug 23 09:18:47 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955976775 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.955976775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.510383861 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 59313171295 ps |
| CPU time | 83.78 seconds |
| Started | Aug 23 09:18:13 PM UTC 24 |
| Finished | Aug 23 09:19:39 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510383861 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.510383861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.1950799156 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 69571413062 ps |
| CPU time | 24.63 seconds |
| Started | Aug 23 09:17:17 PM UTC 24 |
| Finished | Aug 23 09:17:43 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950799156 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.1950799156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.2020903195 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 232994632002 ps |
| CPU time | 159.99 seconds |
| Started | Aug 23 09:17:36 PM UTC 24 |
| Finished | Aug 23 09:20:18 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020903195 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.2020903195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.2504203589 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 297873468097 ps |
| CPU time | 86.92 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:15:45 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504203589 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.2504203589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.528000953 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 325247804493 ps |
| CPU time | 162.97 seconds |
| Started | Aug 23 09:17:30 PM UTC 24 |
| Finished | Aug 23 09:20:15 PM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528000953 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.528000953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.519040163 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6348089020 ps |
| CPU time | 19.1 seconds |
| Started | Aug 23 09:17:09 PM UTC 24 |
| Finished | Aug 23 09:17:30 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=519040163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.aon_timer_stress_all_with_rand_reset.519040163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.4130868828 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 79889247333 ps |
| CPU time | 27.18 seconds |
| Started | Aug 23 09:17:50 PM UTC 24 |
| Finished | Aug 23 09:18:19 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130868828 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.4130868828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.2636124024 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 194973259642 ps |
| CPU time | 227.12 seconds |
| Started | Aug 23 09:16:08 PM UTC 24 |
| Finished | Aug 23 09:19:58 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636124024 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.2636124024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.157803698 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 132745501210 ps |
| CPU time | 48.39 seconds |
| Started | Aug 23 09:16:11 PM UTC 24 |
| Finished | Aug 23 09:17:00 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157803698 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.157803698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.3442348312 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 164097426546 ps |
| CPU time | 104.9 seconds |
| Started | Aug 23 09:15:21 PM UTC 24 |
| Finished | Aug 23 09:17:08 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442348312 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.3442348312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.563731330 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3498700153 ps |
| CPU time | 14.71 seconds |
| Started | Aug 23 09:15:35 PM UTC 24 |
| Finished | Aug 23 09:15:52 PM UTC 24 |
| Peak memory | 206612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=563731330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.aon_timer_stress_all_with_rand_reset.563731330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.3014126744 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2222087594 ps |
| CPU time | 11.04 seconds |
| Started | Aug 23 09:15:56 PM UTC 24 |
| Finished | Aug 23 09:16:08 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3014126744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.aon_timer_stress_all_with_rand_reset.3014126744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.2198175000 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 6095752461 ps |
| CPU time | 19.24 seconds |
| Started | Aug 23 09:16:37 PM UTC 24 |
| Finished | Aug 23 09:16:57 PM UTC 24 |
| Peak memory | 206548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2198175000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.aon_timer_stress_all_with_rand_reset.2198175000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.176911509 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 432934479254 ps |
| CPU time | 174.32 seconds |
| Started | Aug 23 09:18:20 PM UTC 24 |
| Finished | Aug 23 09:21:17 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176911509 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.176911509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.605180736 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 29196706149 ps |
| CPU time | 34.13 seconds |
| Started | Aug 23 09:14:41 PM UTC 24 |
| Finished | Aug 23 09:15:17 PM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=605180736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.aon_timer_stress_all_with_rand_reset.605180736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.1929952504 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4025390495 ps |
| CPU time | 18.23 seconds |
| Started | Aug 23 09:15:13 PM UTC 24 |
| Finished | Aug 23 09:15:32 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1929952504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.aon_timer_stress_all_with_rand_reset.1929952504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.4087397703 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4284549993 ps |
| CPU time | 28.19 seconds |
| Started | Aug 23 09:14:55 PM UTC 24 |
| Finished | Aug 23 09:15:25 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4087397703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.4087397703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.2109447050 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 290514082162 ps |
| CPU time | 92.73 seconds |
| Started | Aug 23 09:16:34 PM UTC 24 |
| Finished | Aug 23 09:18:09 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109447050 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.2109447050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.4271128959 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 136194400579 ps |
| CPU time | 163.31 seconds |
| Started | Aug 23 09:16:43 PM UTC 24 |
| Finished | Aug 23 09:19:29 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271128959 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.4271128959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.1096731173 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 21988344639 ps |
| CPU time | 14.02 seconds |
| Started | Aug 23 09:17:35 PM UTC 24 |
| Finished | Aug 23 09:17:50 PM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1096731173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.1096731173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2231887821 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 11984644488 ps |
| CPU time | 15.74 seconds |
| Started | Aug 23 09:15:48 PM UTC 24 |
| Finished | Aug 23 09:16:05 PM UTC 24 |
| Peak memory | 206644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2231887821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.aon_timer_stress_all_with_rand_reset.2231887821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.1127140254 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4553635413 ps |
| CPU time | 37.21 seconds |
| Started | Aug 23 09:15:50 PM UTC 24 |
| Finished | Aug 23 09:16:29 PM UTC 24 |
| Peak memory | 206648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1127140254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.1127140254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.1766287959 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4033438545 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 09:18:05 PM UTC 24 |
| Finished | Aug 23 09:18:10 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766287959 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.1766287959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.857534102 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 460125994 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:18:27 PM UTC 24 |
| Finished | Aug 23 09:18:29 PM UTC 24 |
| Peak memory | 201316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857534102 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.857534102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.3193062097 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 45371401824 ps |
| CPU time | 27.7 seconds |
| Started | Aug 23 09:17:14 PM UTC 24 |
| Finished | Aug 23 09:17:43 PM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3193062097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.3193062097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.84921076 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2542120557 ps |
| CPU time | 11.87 seconds |
| Started | Aug 23 09:17:16 PM UTC 24 |
| Finished | Aug 23 09:17:29 PM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=84921076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 34.aon_timer_stress_all_with_rand_reset.84921076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.656903965 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 138539561507 ps |
| CPU time | 50.99 seconds |
| Started | Aug 23 09:17:26 PM UTC 24 |
| Finished | Aug 23 09:18:19 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656903965 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.656903965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.2006595597 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 472964738252 ps |
| CPU time | 133.18 seconds |
| Started | Aug 23 09:14:55 PM UTC 24 |
| Finished | Aug 23 09:17:11 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006595597 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.2006595597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.4290241855 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3240167865 ps |
| CPU time | 17.14 seconds |
| Started | Aug 23 09:14:19 PM UTC 24 |
| Finished | Aug 23 09:14:37 PM UTC 24 |
| Peak memory | 218500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4290241855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.aon_timer_stress_all_with_rand_reset.4290241855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2397470700 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 108992513504 ps |
| CPU time | 129.1 seconds |
| Started | Aug 23 09:16:18 PM UTC 24 |
| Finished | Aug 23 09:18:29 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397470700 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.2397470700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.1672966192 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5951085311 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 09:17:01 PM UTC 24 |
| Finished | Aug 23 09:17:05 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672966192 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.1672966192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.4158529546 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 650706348889 ps |
| CPU time | 433.16 seconds |
| Started | Aug 23 09:14:41 PM UTC 24 |
| Finished | Aug 23 09:22:00 PM UTC 24 |
| Peak memory | 204136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158529546 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.4158529546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3299843570 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 529369070 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:15:18 PM UTC 24 |
| Finished | Aug 23 09:15:20 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299843570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3299843570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.1087248846 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 50778576614 ps |
| CPU time | 15.94 seconds |
| Started | Aug 23 09:15:50 PM UTC 24 |
| Finished | Aug 23 09:16:08 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087248846 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.1087248846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.2713366270 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 170595649844 ps |
| CPU time | 25.71 seconds |
| Started | Aug 23 09:16:13 PM UTC 24 |
| Finished | Aug 23 09:16:40 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713366270 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.2713366270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.1292585806 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 442839874 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:17:24 PM UTC 24 |
| Finished | Aug 23 09:17:26 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292585806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1292585806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.3313684992 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 386155175960 ps |
| CPU time | 583.51 seconds |
| Started | Aug 23 09:14:50 PM UTC 24 |
| Finished | Aug 23 09:24:39 PM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313684992 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.3313684992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.1556631422 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 482499451625 ps |
| CPU time | 632.1 seconds |
| Started | Aug 23 09:15:16 PM UTC 24 |
| Finished | Aug 23 09:25:54 PM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556631422 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.1556631422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.1860917427 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 461683986 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 09:15:40 PM UTC 24 |
| Finished | Aug 23 09:15:42 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860917427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1860917427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.2286809492 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 630133411 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:16:16 PM UTC 24 |
| Finished | Aug 23 09:16:18 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286809492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2286809492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.1379256144 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 570714573 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 09:17:18 PM UTC 24 |
| Finished | Aug 23 09:17:20 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379256144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1379256144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.4229831670 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3315270568 ps |
| CPU time | 6.07 seconds |
| Started | Aug 23 09:17:20 PM UTC 24 |
| Finished | Aug 23 09:17:27 PM UTC 24 |
| Peak memory | 219264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4229831670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 35.aon_timer_stress_all_with_rand_reset.4229831670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.3615596396 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 350986612 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 09:17:30 PM UTC 24 |
| Finished | Aug 23 09:17:32 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615596396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3615596396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.575107734 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 467747603 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 09:17:48 PM UTC 24 |
| Finished | Aug 23 09:17:51 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575107734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.575107734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.1888368869 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3861096872 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 09:15:52 PM UTC 24 |
| Finished | Aug 23 09:16:07 PM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1888368869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.aon_timer_stress_all_with_rand_reset.1888368869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.1665115640 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 32879831876 ps |
| CPU time | 10.8 seconds |
| Started | Aug 23 09:15:56 PM UTC 24 |
| Finished | Aug 23 09:16:08 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665115640 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.1665115640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.2993344613 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 529529687 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 09:16:08 PM UTC 24 |
| Finished | Aug 23 09:16:10 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993344613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2993344613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.839254804 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 589357806 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 09:17:08 PM UTC 24 |
| Finished | Aug 23 09:17:11 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839254804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.839254804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.2931572969 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 26253771123 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 09:17:09 PM UTC 24 |
| Finished | Aug 23 09:17:14 PM UTC 24 |
| Peak memory | 200280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931572969 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.2931572969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.1285179875 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 340976509 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 09:17:58 PM UTC 24 |
| Finished | Aug 23 09:18:00 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285179875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1285179875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.2940311459 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2441472272 ps |
| CPU time | 16.66 seconds |
| Started | Aug 23 09:18:00 PM UTC 24 |
| Finished | Aug 23 09:18:18 PM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2940311459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.aon_timer_stress_all_with_rand_reset.2940311459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.1887256562 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 248951312113 ps |
| CPU time | 318.81 seconds |
| Started | Aug 23 09:14:39 PM UTC 24 |
| Finished | Aug 23 09:20:02 PM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887256562 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.1887256562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.3879824043 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 585811929 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 09:14:47 PM UTC 24 |
| Finished | Aug 23 09:14:49 PM UTC 24 |
| Peak memory | 199248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879824043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3879824043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.3805001578 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 154025175465 ps |
| CPU time | 97.86 seconds |
| Started | Aug 23 09:15:36 PM UTC 24 |
| Finished | Aug 23 09:17:16 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805001578 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.3805001578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.4161825217 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 70949036781 ps |
| CPU time | 47.19 seconds |
| Started | Aug 23 09:14:26 PM UTC 24 |
| Finished | Aug 23 09:15:15 PM UTC 24 |
| Peak memory | 214324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4161825217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.aon_timer_stress_all_with_rand_reset.4161825217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.1964146340 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 440147881 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:15:10 PM UTC 24 |
| Finished | Aug 23 09:15:12 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964146340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1964146340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.2687169897 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 141427020453 ps |
| CPU time | 159.72 seconds |
| Started | Aug 23 09:14:24 PM UTC 24 |
| Finished | Aug 23 09:17:07 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687169897 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.2687169897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.153271986 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 488071591 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 09:16:11 PM UTC 24 |
| Finished | Aug 23 09:16:13 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153271986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.153271986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.2698252005 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 521555461 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:16:26 PM UTC 24 |
| Finished | Aug 23 09:16:28 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698252005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2698252005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.2946352396 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 13299425589 ps |
| CPU time | 32.75 seconds |
| Started | Aug 23 09:16:47 PM UTC 24 |
| Finished | Aug 23 09:17:21 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2946352396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.aon_timer_stress_all_with_rand_reset.2946352396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3353980247 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 403330570 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 09:17:40 PM UTC 24 |
| Finished | Aug 23 09:17:42 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353980247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3353980247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.1051896272 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 538742037 ps |
| CPU time | 0.9 seconds |
| Started | Aug 23 09:17:53 PM UTC 24 |
| Finished | Aug 23 09:17:55 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051896272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1051896272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.210679433 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3604418812 ps |
| CPU time | 20.33 seconds |
| Started | Aug 23 09:14:47 PM UTC 24 |
| Finished | Aug 23 09:15:08 PM UTC 24 |
| Peak memory | 219376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=210679433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.aon_timer_stress_all_with_rand_reset.210679433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.3893938478 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 532006438 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:15:00 PM UTC 24 |
| Finished | Aug 23 09:15:02 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893938478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3893938478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.1384369519 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2222471582 ps |
| CPU time | 11.83 seconds |
| Started | Aug 23 09:15:19 PM UTC 24 |
| Finished | Aug 23 09:15:32 PM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1384369519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.1384369519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.2234480709 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 13421699404 ps |
| CPU time | 25.66 seconds |
| Started | Aug 23 09:15:40 PM UTC 24 |
| Finished | Aug 23 09:16:07 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2234480709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 15.aon_timer_stress_all_with_rand_reset.2234480709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2813063247 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 545418545 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 09:15:47 PM UTC 24 |
| Finished | Aug 23 09:15:49 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813063247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2813063247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.2815126003 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 467777185 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:15:52 PM UTC 24 |
| Finished | Aug 23 09:15:53 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815126003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2815126003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.630711734 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 480090530 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:16:41 PM UTC 24 |
| Finished | Aug 23 09:16:43 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630711734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.630711734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.2596776421 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 513567902 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 09:16:52 PM UTC 24 |
| Finished | Aug 23 09:16:54 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596776421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2596776421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.3894444988 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7775623462 ps |
| CPU time | 7.89 seconds |
| Started | Aug 23 09:14:31 PM UTC 24 |
| Finished | Aug 23 09:14:40 PM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3894444988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.aon_timer_stress_all_with_rand_reset.3894444988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1165549553 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2530782610 ps |
| CPU time | 7.51 seconds |
| Started | Aug 23 09:17:45 PM UTC 24 |
| Finished | Aug 23 09:17:54 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1165549553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.aon_timer_stress_all_with_rand_reset.1165549553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.1380724335 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 22053170232 ps |
| CPU time | 11.92 seconds |
| Started | Aug 23 09:18:22 PM UTC 24 |
| Finished | Aug 23 09:18:35 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380724335 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.1380724335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.1567066218 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 364266702 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:18 PM UTC 24 |
| Peak memory | 199248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567066218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1567066218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.2776587572 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 569991776 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 09:15:29 PM UTC 24 |
| Finished | Aug 23 09:15:32 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776587572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2776587572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.2694057855 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 576710717 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 09:15:55 PM UTC 24 |
| Finished | Aug 23 09:15:57 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694057855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2694057855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.34865630 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 402977751 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 09:16:03 PM UTC 24 |
| Finished | Aug 23 09:16:05 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34865630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.34865630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.1622989511 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4028650150 ps |
| CPU time | 32.7 seconds |
| Started | Aug 23 09:16:08 PM UTC 24 |
| Finished | Aug 23 09:16:42 PM UTC 24 |
| Peak memory | 212036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1622989511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 21.aon_timer_stress_all_with_rand_reset.1622989511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1565429161 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 534149020 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 09:16:09 PM UTC 24 |
| Finished | Aug 23 09:16:12 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565429161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1565429161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2650708432 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 441275001 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:17:16 PM UTC 24 |
| Finished | Aug 23 09:17:18 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650708432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2650708432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.3833518334 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2342250674 ps |
| CPU time | 12.63 seconds |
| Started | Aug 23 09:17:30 PM UTC 24 |
| Finished | Aug 23 09:17:43 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3833518334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 37.aon_timer_stress_all_with_rand_reset.3833518334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.106847612 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 512841088 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:18:03 PM UTC 24 |
| Finished | Aug 23 09:18:05 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106847612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.106847612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.1146980680 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 556185738 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:18:18 PM UTC 24 |
| Finished | Aug 23 09:18:20 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146980680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1146980680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2289728757 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 560722958 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:14:41 PM UTC 24 |
| Finished | Aug 23 09:14:43 PM UTC 24 |
| Peak memory | 198956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289728757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2289728757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.798008266 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 549896827 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:14:53 PM UTC 24 |
| Finished | Aug 23 09:14:55 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798008266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.798008266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2477232559 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4244805051 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 206556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477232559 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.2477232559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2153595498 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 453752778 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:19 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153595498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2153595498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.2946101693 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 414275091 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 09:15:49 PM UTC 24 |
| Finished | Aug 23 09:15:51 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946101693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2946101693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.4134410077 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1423762748 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 09:16:03 PM UTC 24 |
| Finished | Aug 23 09:16:10 PM UTC 24 |
| Peak memory | 217432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4134410077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.aon_timer_stress_all_with_rand_reset.4134410077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1658430117 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3355277328 ps |
| CPU time | 19.5 seconds |
| Started | Aug 23 09:16:27 PM UTC 24 |
| Finished | Aug 23 09:16:48 PM UTC 24 |
| Peak memory | 219240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1658430117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.1658430117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3110480818 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 567360209 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:16:46 PM UTC 24 |
| Finished | Aug 23 09:16:48 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110480818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3110480818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3436040602 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 560147179 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:17:13 PM UTC 24 |
| Finished | Aug 23 09:17:14 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436040602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3436040602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.3595352410 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 36177613768 ps |
| CPU time | 22.55 seconds |
| Started | Aug 23 09:17:20 PM UTC 24 |
| Finished | Aug 23 09:17:44 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595352410 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.3595352410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.1913869514 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 379825321 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 09:14:29 PM UTC 24 |
| Finished | Aug 23 09:14:31 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913869514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1913869514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.1981211183 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 204278171491 ps |
| CPU time | 266.84 seconds |
| Started | Aug 23 09:14:31 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 204136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981211183 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.1981211183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.2784769726 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2214320854 ps |
| CPU time | 14.23 seconds |
| Started | Aug 23 09:18:04 PM UTC 24 |
| Finished | Aug 23 09:18:19 PM UTC 24 |
| Peak memory | 214760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2784769726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 44.aon_timer_stress_all_with_rand_reset.2784769726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.3945635003 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 467389742 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 09:18:11 PM UTC 24 |
| Finished | Aug 23 09:18:13 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945635003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3945635003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.4269532569 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 357942455 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:18:14 PM UTC 24 |
| Finished | Aug 23 09:18:16 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269532569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4269532569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.481836921 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 5218735499 ps |
| CPU time | 9.43 seconds |
| Started | Aug 23 09:18:21 PM UTC 24 |
| Finished | Aug 23 09:18:31 PM UTC 24 |
| Peak memory | 203084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=481836921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 49.aon_timer_stress_all_with_rand_reset.481836921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.825087664 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1846395941 ps |
| CPU time | 7.94 seconds |
| Started | Aug 23 09:14:37 PM UTC 24 |
| Finished | Aug 23 09:14:46 PM UTC 24 |
| Peak memory | 206492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=825087664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.aon_timer_stress_all_with_rand_reset.825087664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.690422036 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6908462582 ps |
| CPU time | 9.34 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:43 PM UTC 24 |
| Peak memory | 205168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690422036 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.690422036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.3807890809 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 619378567 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 09:15:33 PM UTC 24 |
| Finished | Aug 23 09:15:36 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807890809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3807890809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.3841555151 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 386616197 ps |
| CPU time | 1 seconds |
| Started | Aug 23 09:14:21 PM UTC 24 |
| Finished | Aug 23 09:14:23 PM UTC 24 |
| Peak memory | 199248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841555151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3841555151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.148389406 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 42577398624 ps |
| CPU time | 15.08 seconds |
| Started | Aug 23 09:16:28 PM UTC 24 |
| Finished | Aug 23 09:16:45 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148389406 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.148389406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.4196932187 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 633405689 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 09:16:31 PM UTC 24 |
| Finished | Aug 23 09:16:33 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196932187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4196932187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.3916809505 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 374130145 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 09:14:26 PM UTC 24 |
| Finished | Aug 23 09:14:28 PM UTC 24 |
| Peak memory | 198736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916809505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3916809505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.1736214531 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 578183412 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 09:16:58 PM UTC 24 |
| Finished | Aug 23 09:17:01 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736214531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1736214531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.4147467725 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 604027878 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:17:34 PM UTC 24 |
| Finished | Aug 23 09:17:35 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147467725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4147467725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2368366764 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 435946082 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:17:44 PM UTC 24 |
| Finished | Aug 23 09:17:46 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368366764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2368366764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.3636616867 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1394897289 ps |
| CPU time | 6.9 seconds |
| Started | Aug 23 09:18:20 PM UTC 24 |
| Finished | Aug 23 09:18:28 PM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3636616867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.aon_timer_stress_all_with_rand_reset.3636616867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.3831035735 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 419811903 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 09:18:21 PM UTC 24 |
| Finished | Aug 23 09:18:23 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831035735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3831035735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.360335077 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 622391421 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 09:14:37 PM UTC 24 |
| Finished | Aug 23 09:14:39 PM UTC 24 |
| Peak memory | 198392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360335077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.360335077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.1076183147 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 484979707 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 09:14:49 PM UTC 24 |
| Finished | Aug 23 09:14:51 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076183147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1076183147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1581417665 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 411893953 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:18:27 PM UTC 24 |
| Finished | Aug 23 09:18:29 PM UTC 24 |
| Peak memory | 201304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581417665 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1581417665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3042767867 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 7024225363 ps |
| CPU time | 8.8 seconds |
| Started | Aug 23 09:18:27 PM UTC 24 |
| Finished | Aug 23 09:18:37 PM UTC 24 |
| Peak memory | 205592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042767867 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3042767867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.219032633 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1258506660 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 09:18:26 PM UTC 24 |
| Finished | Aug 23 09:18:28 PM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219032633 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.219032633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2193984110 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 533429272 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 09:18:29 PM UTC 24 |
| Finished | Aug 23 09:18:31 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2193984110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.2193984110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.1767145180 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 427631318 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:18:23 PM UTC 24 |
| Finished | Aug 23 09:18:25 PM UTC 24 |
| Peak memory | 202652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767145180 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1767145180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1789717610 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 393057891 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:18:26 PM UTC 24 |
| Finished | Aug 23 09:18:28 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789717610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.1789717610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.3941377292 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 405731502 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 09:18:24 PM UTC 24 |
| Finished | Aug 23 09:18:26 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941377292 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.3941377292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3278790309 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1551692246 ps |
| CPU time | 2.22 seconds |
| Started | Aug 23 09:18:28 PM UTC 24 |
| Finished | Aug 23 09:18:32 PM UTC 24 |
| Peak memory | 203640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278790309 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3278790309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3199811756 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 502975284 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 09:18:23 PM UTC 24 |
| Finished | Aug 23 09:18:25 PM UTC 24 |
| Peak memory | 207024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199811756 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3199811756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2725517333 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1132774241 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 09:18:31 PM UTC 24 |
| Finished | Aug 23 09:18:34 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725517333 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.2725517333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1268943212 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 576555406 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:34 PM UTC 24 |
| Peak memory | 205596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1268943212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim er_csr_mem_rw_with_rand_reset.1268943212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.776319611 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 332566412 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:34 PM UTC 24 |
| Peak memory | 201312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776319611 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.776319611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2584335667 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 346068128 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:18:29 PM UTC 24 |
| Finished | Aug 23 09:18:31 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584335667 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2584335667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2797198273 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 286223761 ps |
| CPU time | 0.51 seconds |
| Started | Aug 23 09:18:30 PM UTC 24 |
| Finished | Aug 23 09:18:32 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797198273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2797198273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1659644070 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 495174265 ps |
| CPU time | 1 seconds |
| Started | Aug 23 09:18:29 PM UTC 24 |
| Finished | Aug 23 09:18:31 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659644070 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.1659644070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3571332159 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2543897863 ps |
| CPU time | 5.78 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:39 PM UTC 24 |
| Peak memory | 205416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571332159 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.3571332159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2098824600 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 792219244 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 09:18:29 PM UTC 24 |
| Finished | Aug 23 09:18:32 PM UTC 24 |
| Peak memory | 207004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098824600 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2098824600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3789404963 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9322945561 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 09:18:29 PM UTC 24 |
| Finished | Aug 23 09:18:32 PM UTC 24 |
| Peak memory | 206352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789404963 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.3789404963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.403339980 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 626867304 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 09:18:52 PM UTC 24 |
| Finished | Aug 23 09:18:54 PM UTC 24 |
| Peak memory | 205008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=403339980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_tim er_csr_mem_rw_with_rand_reset.403339980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.2191067200 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 348667154 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 09:18:52 PM UTC 24 |
| Finished | Aug 23 09:18:53 PM UTC 24 |
| Peak memory | 201728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191067200 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2191067200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2195447565 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 471583830 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 09:18:52 PM UTC 24 |
| Finished | Aug 23 09:18:54 PM UTC 24 |
| Peak memory | 199552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195447565 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2195447565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2139773480 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2400450501 ps |
| CPU time | 5.48 seconds |
| Started | Aug 23 09:18:52 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 205420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139773480 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.2139773480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1110273071 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 415948134 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 09:18:51 PM UTC 24 |
| Finished | Aug 23 09:18:53 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110273071 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1110273071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1554352083 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4841344653 ps |
| CPU time | 4.84 seconds |
| Started | Aug 23 09:18:51 PM UTC 24 |
| Finished | Aug 23 09:18:57 PM UTC 24 |
| Peak memory | 206560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554352083 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.1554352083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3412433718 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 325473383 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 205480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3412433718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti mer_csr_mem_rw_with_rand_reset.3412433718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2460592735 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 322359607 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:18:53 PM UTC 24 |
| Finished | Aug 23 09:18:55 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460592735 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2460592735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3058222549 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 427748469 ps |
| CPU time | 1 seconds |
| Started | Aug 23 09:18:53 PM UTC 24 |
| Finished | Aug 23 09:18:55 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058222549 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3058222549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3203263661 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2778053679 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 09:18:53 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203263661 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3203263661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3625190922 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 791728262 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 09:18:52 PM UTC 24 |
| Finished | Aug 23 09:18:54 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625190922 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3625190922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.89013878 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4600792336 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 09:18:53 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 205836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89013878 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.89013878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1220334510 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 512745273 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:57 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1220334510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti mer_csr_mem_rw_with_rand_reset.1220334510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2837791889 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 364440341 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837791889 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2837791889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1851300992 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 306484027 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851300992 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1851300992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3160254443 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1534490128 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160254443 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.3160254443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3548647617 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 479647767 ps |
| CPU time | 2.16 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:57 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548647617 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3548647617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2049402146 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3998867110 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 09:18:54 PM UTC 24 |
| Finished | Aug 23 09:18:59 PM UTC 24 |
| Peak memory | 207196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049402146 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2049402146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1071985070 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 337455916 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:18:56 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1071985070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti mer_csr_mem_rw_with_rand_reset.1071985070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2459576102 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 444047521 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:18:56 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459576102 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2459576102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.4158910837 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 480000989 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 09:18:55 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158910837 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4158910837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.807430027 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2360595574 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 09:18:56 PM UTC 24 |
| Finished | Aug 23 09:18:59 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807430027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.807430027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3530990333 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 429598786 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 09:18:55 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530990333 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3530990333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3945976768 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 8149391457 ps |
| CPU time | 11.31 seconds |
| Started | Aug 23 09:18:55 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 206796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945976768 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3945976768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.816459164 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 555497452 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:18:58 PM UTC 24 |
| Finished | Aug 23 09:18:59 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=816459164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_tim er_csr_mem_rw_with_rand_reset.816459164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2995349782 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 414939234 ps |
| CPU time | 0.51 seconds |
| Started | Aug 23 09:18:57 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995349782 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2995349782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.4078670697 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 360096049 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 09:18:57 PM UTC 24 |
| Finished | Aug 23 09:18:58 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078670697 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4078670697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2948536484 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1474445118 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 09:18:58 PM UTC 24 |
| Finished | Aug 23 09:19:03 PM UTC 24 |
| Peak memory | 203308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948536484 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.2948536484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.568996368 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 351765679 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 09:18:57 PM UTC 24 |
| Finished | Aug 23 09:18:59 PM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568996368 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.568996368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.730116186 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 8067134137 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 09:18:57 PM UTC 24 |
| Finished | Aug 23 09:19:00 PM UTC 24 |
| Peak memory | 206788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730116186 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.730116186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1891058045 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 408723869 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 202872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1891058045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti mer_csr_mem_rw_with_rand_reset.1891058045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.2488462101 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 400914913 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 199384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488462101 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2488462101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3931393968 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 385181122 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 09:18:58 PM UTC 24 |
| Finished | Aug 23 09:19:00 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931393968 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3931393968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3448343483 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1269716515 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448343483 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3448343483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3767367985 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 429968866 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 09:18:58 PM UTC 24 |
| Finished | Aug 23 09:19:00 PM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767367985 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3767367985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2023638635 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4447794054 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 09:18:58 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 206352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023638635 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.2023638635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1720080098 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 366566572 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:19:00 PM UTC 24 |
| Finished | Aug 23 09:19:02 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1720080098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti mer_csr_mem_rw_with_rand_reset.1720080098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1484978371 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 383665836 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484978371 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1484978371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3565002395 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 505203225 ps |
| CPU time | 1.13 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565002395 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3565002395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1073013228 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2346356999 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 09:19:00 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 205816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073013228 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1073013228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.1324813444 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 549058560 ps |
| CPU time | 1.41 seconds |
| Started | Aug 23 09:18:59 PM UTC 24 |
| Finished | Aug 23 09:19:01 PM UTC 24 |
| Peak memory | 206228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324813444 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1324813444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3769905525 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 390861963 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 09:19:01 PM UTC 24 |
| Finished | Aug 23 09:19:03 PM UTC 24 |
| Peak memory | 205448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3769905525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.3769905525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.542269387 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 548363295 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 09:19:01 PM UTC 24 |
| Finished | Aug 23 09:19:03 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542269387 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.542269387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.301837839 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 364052636 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 09:19:00 PM UTC 24 |
| Finished | Aug 23 09:19:02 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301837839 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.301837839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3308426357 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1563111398 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 09:19:01 PM UTC 24 |
| Finished | Aug 23 09:19:04 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308426357 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.3308426357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2494236614 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 520443630 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 09:19:00 PM UTC 24 |
| Finished | Aug 23 09:19:03 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494236614 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2494236614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1936532198 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8963603938 ps |
| CPU time | 12.44 seconds |
| Started | Aug 23 09:19:00 PM UTC 24 |
| Finished | Aug 23 09:19:14 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936532198 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.1936532198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1726528356 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 523307731 ps |
| CPU time | 1.13 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:05 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1726528356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti mer_csr_mem_rw_with_rand_reset.1726528356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.150428501 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 488348831 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:04 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150428501 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.150428501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3841242043 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 497829254 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:04 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841242043 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3841242043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3441327299 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1305137586 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 203448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441327299 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.3441327299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1214216636 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 392778095 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 09:19:01 PM UTC 24 |
| Finished | Aug 23 09:19:04 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214216636 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1214216636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.963366777 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8329620366 ps |
| CPU time | 4.25 seconds |
| Started | Aug 23 09:19:01 PM UTC 24 |
| Finished | Aug 23 09:19:07 PM UTC 24 |
| Peak memory | 207324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963366777 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.963366777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.881654055 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 400655960 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 09:19:04 PM UTC 24 |
| Finished | Aug 23 09:19:05 PM UTC 24 |
| Peak memory | 205716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=881654055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_tim er_csr_mem_rw_with_rand_reset.881654055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.233498023 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 325458360 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 09:19:03 PM UTC 24 |
| Finished | Aug 23 09:19:05 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233498023 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.233498023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3776762502 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 490071749 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:04 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776762502 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3776762502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.330672297 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2135393620 ps |
| CPU time | 1.8 seconds |
| Started | Aug 23 09:19:04 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330672297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.330672297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3740949601 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 645658806 ps |
| CPU time | 2 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740949601 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3740949601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1132783827 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 7914334165 ps |
| CPU time | 3.42 seconds |
| Started | Aug 23 09:19:02 PM UTC 24 |
| Finished | Aug 23 09:19:07 PM UTC 24 |
| Peak memory | 207076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132783827 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.1132783827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2753225342 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 587977961 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 09:18:36 PM UTC 24 |
| Finished | Aug 23 09:18:38 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753225342 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.2753225342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3480870211 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 6203983430 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 09:18:36 PM UTC 24 |
| Finished | Aug 23 09:18:42 PM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480870211 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3480870211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.969433101 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1029438346 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 09:18:36 PM UTC 24 |
| Finished | Aug 23 09:18:37 PM UTC 24 |
| Peak memory | 200728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969433101 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.969433101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.947317445 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 379680118 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 09:18:37 PM UTC 24 |
| Finished | Aug 23 09:18:39 PM UTC 24 |
| Peak memory | 205332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=947317445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_time r_csr_mem_rw_with_rand_reset.947317445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2175128567 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 452908112 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 09:18:36 PM UTC 24 |
| Finished | Aug 23 09:18:38 PM UTC 24 |
| Peak memory | 200588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175128567 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2175128567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.609383931 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 334518636 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 09:18:33 PM UTC 24 |
| Finished | Aug 23 09:18:35 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609383931 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.609383931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1221129050 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 478052424 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 09:18:34 PM UTC 24 |
| Finished | Aug 23 09:18:36 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221129050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.1221129050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3593407434 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 491544045 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:18:34 PM UTC 24 |
| Finished | Aug 23 09:18:36 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593407434 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.3593407434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2945647305 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2712932427 ps |
| CPU time | 3.88 seconds |
| Started | Aug 23 09:18:37 PM UTC 24 |
| Finished | Aug 23 09:18:42 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945647305 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.2945647305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3859144723 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 532349604 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 09:18:32 PM UTC 24 |
| Finished | Aug 23 09:18:35 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859144723 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3859144723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3872567224 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8940496369 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 09:18:33 PM UTC 24 |
| Finished | Aug 23 09:18:38 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872567224 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3872567224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2706081018 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 412732248 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 09:19:04 PM UTC 24 |
| Finished | Aug 23 09:19:05 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706081018 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2706081018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1197953005 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 430494992 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 09:19:04 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197953005 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1197953005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.1893561820 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 407885687 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 09:19:05 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893561820 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1893561820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2932101458 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 323144413 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 09:19:05 PM UTC 24 |
| Finished | Aug 23 09:19:06 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932101458 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2932101458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4006569878 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 472846445 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 09:19:05 PM UTC 24 |
| Finished | Aug 23 09:19:07 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006569878 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4006569878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3876205088 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 412350014 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 09:19:05 PM UTC 24 |
| Finished | Aug 23 09:19:07 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876205088 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3876205088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.745473611 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 471130768 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 09:19:05 PM UTC 24 |
| Finished | Aug 23 09:19:07 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745473611 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.745473611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3326897739 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 426857978 ps |
| CPU time | 0.5 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326897739 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3326897739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2345046859 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 370716102 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345046859 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2345046859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.4201382366 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 357358556 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201382366 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4201382366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2760266981 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 557779617 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 09:18:40 PM UTC 24 |
| Finished | Aug 23 09:18:42 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760266981 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2760266981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3094580112 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 7514458183 ps |
| CPU time | 3.93 seconds |
| Started | Aug 23 09:18:40 PM UTC 24 |
| Finished | Aug 23 09:18:45 PM UTC 24 |
| Peak memory | 205652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094580112 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.3094580112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.539191030 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1070497133 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 09:18:39 PM UTC 24 |
| Finished | Aug 23 09:18:41 PM UTC 24 |
| Peak memory | 201780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539191030 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.539191030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2581420960 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 487371446 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:43 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2581420960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim er_csr_mem_rw_with_rand_reset.2581420960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4163986039 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 498688435 ps |
| CPU time | 1.16 seconds |
| Started | Aug 23 09:18:39 PM UTC 24 |
| Finished | Aug 23 09:18:41 PM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163986039 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4163986039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.4109430488 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 384303362 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 09:18:38 PM UTC 24 |
| Finished | Aug 23 09:18:40 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109430488 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4109430488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2094895806 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 280934544 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 09:18:39 PM UTC 24 |
| Finished | Aug 23 09:18:41 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094895806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2094895806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2146718121 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 343507170 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 09:18:38 PM UTC 24 |
| Finished | Aug 23 09:18:40 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146718121 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.2146718121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1666969348 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2557213814 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:45 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666969348 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.1666969348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1651536773 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 705481783 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 09:18:37 PM UTC 24 |
| Finished | Aug 23 09:18:40 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651536773 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1651536773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2941078543 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4490182544 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 09:18:38 PM UTC 24 |
| Finished | Aug 23 09:18:42 PM UTC 24 |
| Peak memory | 206456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941078543 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.2941078543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.2799249377 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 483479290 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799249377 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2799249377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2568648584 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 380231980 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568648584 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2568648584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.1617757972 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 329345221 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 09:19:06 PM UTC 24 |
| Finished | Aug 23 09:19:08 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617757972 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1617757972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2485201513 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 523285158 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485201513 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2485201513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2789627962 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 480573440 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789627962 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2789627962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3545157825 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 413576899 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545157825 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3545157825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3610211001 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 339544159 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610211001 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3610211001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3438221944 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 468375477 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438221944 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3438221944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.600125006 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 375005488 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600125006 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.600125006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.4012516559 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 492833203 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 09:19:07 PM UTC 24 |
| Finished | Aug 23 09:19:09 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012516559 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4012516559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1426267512 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 441158462 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:18:44 PM UTC 24 |
| Finished | Aug 23 09:18:45 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426267512 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.1426267512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1161976330 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4830439429 ps |
| CPU time | 4.79 seconds |
| Started | Aug 23 09:18:42 PM UTC 24 |
| Finished | Aug 23 09:18:48 PM UTC 24 |
| Peak memory | 205980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161976330 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.1161976330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3863727399 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 679960193 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 09:18:42 PM UTC 24 |
| Finished | Aug 23 09:18:45 PM UTC 24 |
| Peak memory | 199736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863727399 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.3863727399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1007206398 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 566680593 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 09:18:44 PM UTC 24 |
| Finished | Aug 23 09:18:45 PM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1007206398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim er_csr_mem_rw_with_rand_reset.1007206398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4142963491 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 516620566 ps |
| CPU time | 0.52 seconds |
| Started | Aug 23 09:18:42 PM UTC 24 |
| Finished | Aug 23 09:18:44 PM UTC 24 |
| Peak memory | 199420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142963491 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4142963491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.763532974 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 324751307 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:43 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763532974 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.763532974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1250910785 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 304848379 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 09:18:42 PM UTC 24 |
| Finished | Aug 23 09:18:44 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250910785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.1250910785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.3807616147 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 478976932 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:43 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807616147 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.3807616147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2788216036 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1365596330 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 09:18:44 PM UTC 24 |
| Finished | Aug 23 09:18:46 PM UTC 24 |
| Peak memory | 201728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788216036 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.2788216036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2533925374 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 652958042 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:44 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533925374 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2533925374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1486438063 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4508822510 ps |
| CPU time | 6.84 seconds |
| Started | Aug 23 09:18:41 PM UTC 24 |
| Finished | Aug 23 09:18:49 PM UTC 24 |
| Peak memory | 206624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486438063 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.1486438063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3572020986 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 554661781 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:10 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572020986 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3572020986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.3570153774 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 465518070 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:10 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570153774 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3570153774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2782513559 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 410153327 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:10 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782513559 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2782513559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2677716523 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 437833223 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677716523 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2677716523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4102134562 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 408378806 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102134562 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4102134562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.3862456381 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 332576609 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862456381 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3862456381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2631419652 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 321308232 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:10 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631419652 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2631419652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.935764560 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 409229180 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 09:19:08 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935764560 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.935764560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3578695359 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 391402103 ps |
| CPU time | 0.5 seconds |
| Started | Aug 23 09:19:09 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578695359 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3578695359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.4099425941 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 307362192 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 09:19:09 PM UTC 24 |
| Finished | Aug 23 09:19:11 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099425941 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4099425941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.257823567 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 473782343 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 09:18:45 PM UTC 24 |
| Finished | Aug 23 09:18:47 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=257823567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_time r_csr_mem_rw_with_rand_reset.257823567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2333564642 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 413594891 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 09:18:45 PM UTC 24 |
| Finished | Aug 23 09:18:47 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333564642 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2333564642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4185532185 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 477330652 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 09:18:45 PM UTC 24 |
| Finished | Aug 23 09:18:46 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185532185 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4185532185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.131295744 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1910317078 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 09:18:45 PM UTC 24 |
| Finished | Aug 23 09:18:47 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131295744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.131295744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1747476658 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 516413416 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 09:18:44 PM UTC 24 |
| Finished | Aug 23 09:18:46 PM UTC 24 |
| Peak memory | 207068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747476658 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1747476658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3018129774 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8982979489 ps |
| CPU time | 11.48 seconds |
| Started | Aug 23 09:18:44 PM UTC 24 |
| Finished | Aug 23 09:18:56 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018129774 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3018129774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.171169758 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 339932270 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:48 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=171169758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_time r_csr_mem_rw_with_rand_reset.171169758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1965487993 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 399518834 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:48 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965487993 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1965487993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2569403786 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 502697129 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:48 PM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569403786 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2569403786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1107982227 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2914349738 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 205416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107982227 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.1107982227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3721622731 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1158080421 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:48 PM UTC 24 |
| Peak memory | 204760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721622731 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3721622731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1618839974 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7577917529 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 09:18:46 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618839974 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1618839974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3480054640 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 455428868 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 09:18:48 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 205704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3480054640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim er_csr_mem_rw_with_rand_reset.3480054640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1957852931 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 301152453 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:18:48 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957852931 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1957852931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.997908119 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 465054409 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 09:18:47 PM UTC 24 |
| Finished | Aug 23 09:18:49 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997908119 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.997908119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3528590847 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2298282296 ps |
| CPU time | 1.94 seconds |
| Started | Aug 23 09:18:48 PM UTC 24 |
| Finished | Aug 23 09:18:51 PM UTC 24 |
| Peak memory | 203852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528590847 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3528590847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.405055751 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 688796121 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 09:18:47 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 207260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405055751 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.405055751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2545537495 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4532812260 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 09:18:47 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 206300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545537495 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.2545537495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.754656253 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 357499426 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 09:18:49 PM UTC 24 |
| Finished | Aug 23 09:18:51 PM UTC 24 |
| Peak memory | 205888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=754656253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_time r_csr_mem_rw_with_rand_reset.754656253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.797213983 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 300793549 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:18:49 PM UTC 24 |
| Finished | Aug 23 09:18:51 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797213983 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.797213983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.823325020 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 428330752 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 09:18:49 PM UTC 24 |
| Finished | Aug 23 09:18:51 PM UTC 24 |
| Peak memory | 200076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823325020 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.823325020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.72400743 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1579972343 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 09:18:49 PM UTC 24 |
| Finished | Aug 23 09:18:52 PM UTC 24 |
| Peak memory | 202024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72400743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.72400743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4243112705 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 518992036 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 09:18:48 PM UTC 24 |
| Finished | Aug 23 09:18:50 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243112705 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4243112705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.386496578 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4504783445 ps |
| CPU time | 2.28 seconds |
| Started | Aug 23 09:18:49 PM UTC 24 |
| Finished | Aug 23 09:18:53 PM UTC 24 |
| Peak memory | 205380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386496578 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.386496578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3831482366 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 340680690 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:52 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3831482366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim er_csr_mem_rw_with_rand_reset.3831482366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4150133100 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 472074637 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:53 PM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150133100 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4150133100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3336034771 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 502820119 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:52 PM UTC 24 |
| Peak memory | 199736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336034771 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3336034771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3090568099 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1457047472 ps |
| CPU time | 3.75 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:55 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090568099 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.3090568099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3986957850 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 678240502 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:53 PM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986957850 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3986957850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2805638315 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 8589849588 ps |
| CPU time | 3.52 seconds |
| Started | Aug 23 09:18:50 PM UTC 24 |
| Finished | Aug 23 09:18:55 PM UTC 24 |
| Peak memory | 206892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805638315 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.2805638315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.1868124872 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4960708229 ps |
| CPU time | 7.58 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:25 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868124872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1868124872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1960046132 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 407816003 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:18 PM UTC 24 |
| Peak memory | 199984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960046132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1960046132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.3042853895 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8114896603 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 09:14:20 PM UTC 24 |
| Finished | Aug 23 09:14:24 PM UTC 24 |
| Peak memory | 231376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042853895 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3042853895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.1533755293 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 424600704 ps |
| CPU time | 1.16 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:19 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533755293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1533755293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.1473118971 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 37882105604 ps |
| CPU time | 13.49 seconds |
| Started | Aug 23 09:15:00 PM UTC 24 |
| Finished | Aug 23 09:15:15 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473118971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1473118971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.3963277918 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 544518779 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 09:14:57 PM UTC 24 |
| Finished | Aug 23 09:14:59 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963277918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3963277918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1990185057 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 58389842934 ps |
| CPU time | 72.43 seconds |
| Started | Aug 23 09:15:08 PM UTC 24 |
| Finished | Aug 23 09:16:22 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990185057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1990185057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.3308059245 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 575464463 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 09:15:05 PM UTC 24 |
| Finished | Aug 23 09:15:06 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308059245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3308059245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2551108519 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 42397656757 ps |
| CPU time | 15.63 seconds |
| Started | Aug 23 09:15:16 PM UTC 24 |
| Finished | Aug 23 09:15:33 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551108519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2551108519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.833685031 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 442685488 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:15:16 PM UTC 24 |
| Finished | Aug 23 09:15:18 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833685031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.833685031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.891888582 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 12107539403 ps |
| CPU time | 16.14 seconds |
| Started | Aug 23 09:15:28 PM UTC 24 |
| Finished | Aug 23 09:15:46 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891888582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.891888582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.3791898900 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 413935310 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:15:25 PM UTC 24 |
| Finished | Aug 23 09:15:27 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791898900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3791898900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.1859252325 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 32219988548 ps |
| CPU time | 36.65 seconds |
| Started | Aug 23 09:15:33 PM UTC 24 |
| Finished | Aug 23 09:16:11 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859252325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1859252325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.4195518782 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 556881505 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 09:15:32 PM UTC 24 |
| Finished | Aug 23 09:15:35 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195518782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4195518782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.3690258270 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 24461752140 ps |
| CPU time | 13.38 seconds |
| Started | Aug 23 09:15:40 PM UTC 24 |
| Finished | Aug 23 09:15:54 PM UTC 24 |
| Peak memory | 200208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690258270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3690258270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.3371089287 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 547823314 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 09:15:40 PM UTC 24 |
| Finished | Aug 23 09:15:42 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371089287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3371089287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.1736020825 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 8618664870 ps |
| CPU time | 6.2 seconds |
| Started | Aug 23 09:15:44 PM UTC 24 |
| Finished | Aug 23 09:15:51 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736020825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1736020825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.590229109 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 495484656 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 09:15:44 PM UTC 24 |
| Finished | Aug 23 09:15:46 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590229109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.590229109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.656640451 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 11345493027 ps |
| CPU time | 4.43 seconds |
| Started | Aug 23 09:15:49 PM UTC 24 |
| Finished | Aug 23 09:15:55 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656640451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.656640451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.3056867739 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 582554749 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:15:48 PM UTC 24 |
| Finished | Aug 23 09:15:50 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056867739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3056867739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.4008681664 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 35500101165 ps |
| CPU time | 13.2 seconds |
| Started | Aug 23 09:15:52 PM UTC 24 |
| Finished | Aug 23 09:16:06 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008681664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4008681664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.4128601253 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 477402262 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 09:15:52 PM UTC 24 |
| Finished | Aug 23 09:15:54 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128601253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4128601253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.3789858941 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 55418670716 ps |
| CPU time | 37.29 seconds |
| Started | Aug 23 09:15:55 PM UTC 24 |
| Finished | Aug 23 09:16:33 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789858941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3789858941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.3945584095 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 590883537 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 09:15:54 PM UTC 24 |
| Finished | Aug 23 09:15:55 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945584095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3945584095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.343295859 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 41445046898 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 09:14:20 PM UTC 24 |
| Finished | Aug 23 09:14:25 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343295859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.343295859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.2551825453 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3968529222 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 09:14:24 PM UTC 24 |
| Finished | Aug 23 09:14:27 PM UTC 24 |
| Peak memory | 231056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551825453 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2551825453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.1339061661 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 408981841 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:14:20 PM UTC 24 |
| Finished | Aug 23 09:14:22 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339061661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1339061661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.417012628 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7349826266 ps |
| CPU time | 8.15 seconds |
| Started | Aug 23 09:15:59 PM UTC 24 |
| Finished | Aug 23 09:16:08 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417012628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.417012628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.1992643914 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 586520460 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 09:15:57 PM UTC 24 |
| Finished | Aug 23 09:15:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992643914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1992643914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.2304868520 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 31536034451 ps |
| CPU time | 41.97 seconds |
| Started | Aug 23 09:16:07 PM UTC 24 |
| Finished | Aug 23 09:16:50 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304868520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2304868520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.210530286 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 470584246 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:16:06 PM UTC 24 |
| Finished | Aug 23 09:16:08 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210530286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.210530286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.1843886059 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 18831143694 ps |
| CPU time | 7.5 seconds |
| Started | Aug 23 09:16:08 PM UTC 24 |
| Finished | Aug 23 09:16:17 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843886059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1843886059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.243395901 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 438979077 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:16:08 PM UTC 24 |
| Finished | Aug 23 09:16:10 PM UTC 24 |
| Peak memory | 199164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243395901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.243395901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.1381741171 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3471711896 ps |
| CPU time | 27.53 seconds |
| Started | Aug 23 09:16:09 PM UTC 24 |
| Finished | Aug 23 09:16:38 PM UTC 24 |
| Peak memory | 214152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1381741171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 22.aon_timer_stress_all_with_rand_reset.1381741171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.61138762 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 48504109265 ps |
| CPU time | 60.78 seconds |
| Started | Aug 23 09:16:11 PM UTC 24 |
| Finished | Aug 23 09:17:13 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61138762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.61138762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.3054457478 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 508603919 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 09:16:11 PM UTC 24 |
| Finished | Aug 23 09:16:13 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054457478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3054457478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.2700726745 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2436697972 ps |
| CPU time | 17.82 seconds |
| Started | Aug 23 09:16:12 PM UTC 24 |
| Finished | Aug 23 09:16:31 PM UTC 24 |
| Peak memory | 219288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2700726745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.aon_timer_stress_all_with_rand_reset.2700726745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1978646817 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7451972327 ps |
| CPU time | 12.11 seconds |
| Started | Aug 23 09:16:14 PM UTC 24 |
| Finished | Aug 23 09:16:27 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978646817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1978646817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.897386326 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 426607487 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:16:14 PM UTC 24 |
| Finished | Aug 23 09:16:15 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897386326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.897386326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3986762850 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13293511665 ps |
| CPU time | 2.18 seconds |
| Started | Aug 23 09:16:25 PM UTC 24 |
| Finished | Aug 23 09:16:28 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986762850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3986762850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.870422036 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 422926886 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 09:16:23 PM UTC 24 |
| Finished | Aug 23 09:16:25 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870422036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.870422036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.4240680838 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 61114621398 ps |
| CPU time | 75.76 seconds |
| Started | Aug 23 09:16:29 PM UTC 24 |
| Finished | Aug 23 09:17:47 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240680838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4240680838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.3692591372 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 510565465 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:16:29 PM UTC 24 |
| Finished | Aug 23 09:16:31 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692591372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3692591372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.2304704285 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 748132176 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 09:16:32 PM UTC 24 |
| Finished | Aug 23 09:16:36 PM UTC 24 |
| Peak memory | 206392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2304704285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 26.aon_timer_stress_all_with_rand_reset.2304704285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2124868346 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 561325865 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 09:16:36 PM UTC 24 |
| Finished | Aug 23 09:16:38 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124868346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2124868346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.321618305 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 29307990619 ps |
| CPU time | 10.32 seconds |
| Started | Aug 23 09:16:35 PM UTC 24 |
| Finished | Aug 23 09:16:46 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321618305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.321618305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.2022641938 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 603557256 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:16:34 PM UTC 24 |
| Finished | Aug 23 09:16:37 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022641938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2022641938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.652185148 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 25842110207 ps |
| CPU time | 14.81 seconds |
| Started | Aug 23 09:16:39 PM UTC 24 |
| Finished | Aug 23 09:16:55 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652185148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.652185148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.3792563604 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 577040100 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 09:16:39 PM UTC 24 |
| Finished | Aug 23 09:16:41 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792563604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3792563604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.2647858176 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 31666163694 ps |
| CPU time | 24.95 seconds |
| Started | Aug 23 09:16:46 PM UTC 24 |
| Finished | Aug 23 09:17:12 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647858176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2647858176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.406270039 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 381801051 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:16:44 PM UTC 24 |
| Finished | Aug 23 09:16:46 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406270039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.406270039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.1873810128 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 522229260 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 09:14:26 PM UTC 24 |
| Finished | Aug 23 09:14:29 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873810128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1873810128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.682067334 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4268616078 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 09:14:26 PM UTC 24 |
| Finished | Aug 23 09:14:29 PM UTC 24 |
| Peak memory | 230924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682067334 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.682067334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.2829640529 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 605683289 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 09:14:24 PM UTC 24 |
| Finished | Aug 23 09:14:26 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829640529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2829640529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.3300477958 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 11385341348 ps |
| CPU time | 16.66 seconds |
| Started | Aug 23 09:16:51 PM UTC 24 |
| Finished | Aug 23 09:17:09 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300477958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3300477958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.1027736249 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 371363103 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 09:16:49 PM UTC 24 |
| Finished | Aug 23 09:16:51 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027736249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1027736249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.3745202474 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 27694543093 ps |
| CPU time | 38.63 seconds |
| Started | Aug 23 09:16:58 PM UTC 24 |
| Finished | Aug 23 09:17:38 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745202474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3745202474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.2743771019 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 519630343 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 09:16:55 PM UTC 24 |
| Finished | Aug 23 09:16:57 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743771019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2743771019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.2102419785 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 40285270788 ps |
| CPU time | 16.82 seconds |
| Started | Aug 23 09:17:07 PM UTC 24 |
| Finished | Aug 23 09:17:25 PM UTC 24 |
| Peak memory | 200900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102419785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2102419785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1751941321 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 568078037 ps |
| CPU time | 1.15 seconds |
| Started | Aug 23 09:17:06 PM UTC 24 |
| Finished | Aug 23 09:17:09 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751941321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1751941321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.1539426110 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 7415622930 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 09:17:12 PM UTC 24 |
| Finished | Aug 23 09:17:15 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539426110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1539426110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.3137153588 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 411957305 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 09:17:12 PM UTC 24 |
| Finished | Aug 23 09:17:13 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137153588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3137153588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.4112287459 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 13204611776 ps |
| CPU time | 18.12 seconds |
| Started | Aug 23 09:17:15 PM UTC 24 |
| Finished | Aug 23 09:17:34 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112287459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4112287459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3306211345 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 586398110 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 09:17:15 PM UTC 24 |
| Finished | Aug 23 09:17:16 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306211345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3306211345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.3558707378 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 35925493891 ps |
| CPU time | 9.28 seconds |
| Started | Aug 23 09:17:18 PM UTC 24 |
| Finished | Aug 23 09:17:28 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558707378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3558707378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.1904496216 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 491411159 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 09:17:17 PM UTC 24 |
| Finished | Aug 23 09:17:19 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904496216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1904496216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.2830263281 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 40353721161 ps |
| CPU time | 49.3 seconds |
| Started | Aug 23 09:17:22 PM UTC 24 |
| Finished | Aug 23 09:18:13 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830263281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2830263281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.1267233906 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 467751121 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 09:17:21 PM UTC 24 |
| Finished | Aug 23 09:17:23 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267233906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1267233906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.3165273927 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 31776915932 ps |
| CPU time | 24.2 seconds |
| Started | Aug 23 09:17:28 PM UTC 24 |
| Finished | Aug 23 09:17:54 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165273927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3165273927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.477741066 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 564554230 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 09:17:26 PM UTC 24 |
| Finished | Aug 23 09:17:29 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477741066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.477741066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2761394289 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 20348004830 ps |
| CPU time | 29.72 seconds |
| Started | Aug 23 09:17:33 PM UTC 24 |
| Finished | Aug 23 09:18:04 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761394289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2761394289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.230224627 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 475389157 ps |
| CPU time | 1.15 seconds |
| Started | Aug 23 09:17:31 PM UTC 24 |
| Finished | Aug 23 09:17:33 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230224627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.230224627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1077464430 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 26114328665 ps |
| CPU time | 12.84 seconds |
| Started | Aug 23 09:17:39 PM UTC 24 |
| Finished | Aug 23 09:17:53 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077464430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1077464430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.2929785145 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 341365183 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 09:17:39 PM UTC 24 |
| Finished | Aug 23 09:17:41 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929785145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2929785145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.2553342615 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 23860000248 ps |
| CPU time | 17.05 seconds |
| Started | Aug 23 09:14:29 PM UTC 24 |
| Finished | Aug 23 09:14:47 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553342615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2553342615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.3752670968 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8770463191 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 09:14:33 PM UTC 24 |
| Finished | Aug 23 09:14:35 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752670968 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3752670968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.3626762887 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 545131336 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 09:14:29 PM UTC 24 |
| Finished | Aug 23 09:14:31 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626762887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3626762887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.1827418974 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 23886348283 ps |
| CPU time | 16.87 seconds |
| Started | Aug 23 09:17:44 PM UTC 24 |
| Finished | Aug 23 09:18:02 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827418974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1827418974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.1577731736 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 407570325 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 09:17:43 PM UTC 24 |
| Finished | Aug 23 09:17:45 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577731736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1577731736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.4251183594 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3677027841 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 09:17:48 PM UTC 24 |
| Finished | Aug 23 09:17:52 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251183594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4251183594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.1529051243 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 572092010 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:17:46 PM UTC 24 |
| Finished | Aug 23 09:17:48 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529051243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1529051243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.1679786807 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 25330079853 ps |
| CPU time | 16 seconds |
| Started | Aug 23 09:17:52 PM UTC 24 |
| Finished | Aug 23 09:18:10 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679786807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1679786807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.1810689318 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 452387654 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 09:17:51 PM UTC 24 |
| Finished | Aug 23 09:17:53 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810689318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1810689318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.143329686 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2224885845 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 09:17:56 PM UTC 24 |
| Finished | Aug 23 09:17:59 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143329686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.143329686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3368072620 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 569213675 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 09:17:54 PM UTC 24 |
| Finished | Aug 23 09:17:56 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368072620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3368072620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.4006327457 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 33973678232 ps |
| CPU time | 44.78 seconds |
| Started | Aug 23 09:18:03 PM UTC 24 |
| Finished | Aug 23 09:18:49 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006327457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4006327457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.312085623 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 464800621 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 09:18:03 PM UTC 24 |
| Finished | Aug 23 09:18:04 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312085623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.312085623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.2993773182 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 558666928 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 09:18:07 PM UTC 24 |
| Finished | Aug 23 09:18:09 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993773182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2993773182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.3973358869 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 45544655860 ps |
| CPU time | 8.56 seconds |
| Started | Aug 23 09:18:05 PM UTC 24 |
| Finished | Aug 23 09:18:15 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973358869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3973358869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.2801870088 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 425312484 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:18:05 PM UTC 24 |
| Finished | Aug 23 09:18:06 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801870088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2801870088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.795259072 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6833102634 ps |
| CPU time | 9.83 seconds |
| Started | Aug 23 09:18:11 PM UTC 24 |
| Finished | Aug 23 09:18:22 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795259072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.795259072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.4258475762 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 530450221 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 09:18:10 PM UTC 24 |
| Finished | Aug 23 09:18:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258475762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4258475762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.2156084578 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 15858680771 ps |
| CPU time | 5.64 seconds |
| Started | Aug 23 09:18:14 PM UTC 24 |
| Finished | Aug 23 09:18:21 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156084578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2156084578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.4208845607 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 490980040 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 09:18:14 PM UTC 24 |
| Finished | Aug 23 09:18:16 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208845607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4208845607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.98316757 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 9552613267 ps |
| CPU time | 3.21 seconds |
| Started | Aug 23 09:18:17 PM UTC 24 |
| Finished | Aug 23 09:18:22 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98316757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.98316757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.2172122408 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 482904246 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 09:18:17 PM UTC 24 |
| Finished | Aug 23 09:18:20 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172122408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2172122408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.1933290883 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 18467261942 ps |
| CPU time | 13.47 seconds |
| Started | Aug 23 09:18:20 PM UTC 24 |
| Finished | Aug 23 09:18:34 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933290883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1933290883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.1832766909 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 567572463 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 09:18:20 PM UTC 24 |
| Finished | Aug 23 09:18:22 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832766909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1832766909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.423602024 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 27402495065 ps |
| CPU time | 9.86 seconds |
| Started | Aug 23 09:14:37 PM UTC 24 |
| Finished | Aug 23 09:14:48 PM UTC 24 |
| Peak memory | 200588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423602024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.423602024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.549030046 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 610300567 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 09:14:33 PM UTC 24 |
| Finished | Aug 23 09:14:35 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549030046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.549030046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.4168013601 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 35349979851 ps |
| CPU time | 5.1 seconds |
| Started | Aug 23 09:14:41 PM UTC 24 |
| Finished | Aug 23 09:14:48 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168013601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4168013601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.3381075190 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 442079543 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 09:14:39 PM UTC 24 |
| Finished | Aug 23 09:14:41 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381075190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3381075190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.269762629 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4786483698 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 09:14:47 PM UTC 24 |
| Finished | Aug 23 09:14:49 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269762629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.269762629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.1970020372 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 478661072 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 09:14:43 PM UTC 24 |
| Finished | Aug 23 09:14:45 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970020372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1970020372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2207602924 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 32096301999 ps |
| CPU time | 10.27 seconds |
| Started | Aug 23 09:14:48 PM UTC 24 |
| Finished | Aug 23 09:14:59 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207602924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2207602924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.4232198077 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 630580266 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 09:14:48 PM UTC 24 |
| Finished | Aug 23 09:14:49 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232198077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4232198077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.1514007721 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 20411152714 ps |
| CPU time | 3.7 seconds |
| Started | Aug 23 09:14:52 PM UTC 24 |
| Finished | Aug 23 09:14:57 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514007721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1514007721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.3345300902 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 468647297 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 09:14:50 PM UTC 24 |
| Finished | Aug 23 09:14:52 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345300902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3345300902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
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