Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	21026	1			T1	10		T3	11		T5	10
bark[1]	251	1			T192	14		T143	14		T149	40
bark[2]	749	1			T48	14		T132	14		T21	21
bark[3]	666	1			T11	21		T185	14		T117	21
bark[4]	376	1			T41	82		T22	26		T153	5
bark[5]	856	1			T44	282		T47	35		T182	14
bark[6]	620	1			T27	14		T14	5		T42	7
bark[7]	198	1			T28	14		T166	14		T43	7
bark[8]	424	1			T31	14		T164	59		T195	14
bark[9]	338	1			T21	94		T165	146		T103	14
bark[10]	155	1			T83	14		T93	26		T121	21
bark[11]	247	1			T124	21		T96	21		T102	21
bark[12]	406	1			T4	14		T15	21		T126	14
bark[13]	308	1			T86	14		T47	21		T131	21
bark[14]	643	1			T42	47		T117	181		T137	26
bark[15]	336	1			T2	14		T22	38		T137	21
bark[16]	598	1			T7	14		T20	52		T47	26
bark[17]	197	1			T15	7		T21	21		T149	26
bark[18]	189	1			T41	21		T21	42		T144	30
bark[19]	280	1			T26	14		T197	14		T146	14
bark[20]	310	1			T191	14		T147	14		T148	14
bark[21]	221	1			T21	23		T47	5		T111	14
bark[22]	305	1			T32	14		T137	7		T74	5
bark[23]	348	1			T11	109		T33	14		T73	26
bark[24]	506	1			T91	128		T173	5		T149	52
bark[25]	133	1			T91	21		T77	21		T110	21
bark[26]	216	1			T10	14		T14	7		T125	30
bark[27]	422	1			T14	26		T15	61		T137	35
bark[28]	722	1			T47	47		T171	250		T165	267
bark[29]	344	1			T22	14		T156	21		T149	5
bark[30]	346	1			T46	5		T117	21		T130	173
bark[31]	179	1			T125	21		T95	64		T123	7
bark_0	4833	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	20481	1			T1	9		T3	10		T5	9
bite[1]	517	1			T33	13		T21	21		T193	13
bite[2]	440	1			T117	203		T173	4		T101	21
bite[3]	438	1			T26	13		T170	13		T14	6
bite[4]	370	1			T28	13		T22	21		T129	178
bite[5]	581	1			T42	46		T111	13		T171	91
bite[6]	190	1			T83	13		T195	13		T144	66
bite[7]	647	1			T15	6		T117	21		T137	35
bite[8]	848	1			T21	21		T44	281		T117	180
bite[9]	325	1			T4	13		T185	13		T146	13
bite[10]	313	1			T32	13		T47	4		T91	127
bite[11]	223	1			T166	13		T122	13		T125	21
bite[12]	272	1			T47	25		T188	13		T174	65
bite[13]	340	1			T132	13		T91	27		T175	21
bite[14]	230	1			T186	13		T123	25		T94	21
bite[15]	351	1			T14	111		T41	81		T22	13
bite[16]	187	1			T41	21		T43	6		T91	21
bite[17]	252	1			T11	21		T14	4		T197	13
bite[18]	333	1			T2	13		T15	60		T41	88
bite[19]	969	1			T20	51		T117	21		T22	26
bite[20]	219	1			T10	13		T164	61		T137	6
bite[21]	277	1			T27	13		T81	13		T192	13
bite[22]	263	1			T11	21		T21	22		T125	30
bite[23]	252	1			T167	13		T129	21		T153	21
bite[24]	447	1			T48	13		T14	25		T130	172
bite[25]	750	1			T11	108		T46	4		T117	123
bite[26]	158	1			T191	13		T108	13		T129	21
bite[27]	187	1			T182	13		T137	30		T149	21
bite[28]	253	1			T135	43		T123	6		T183	111
bite[29]	482	1			T7	13		T86	13		T91	237
bite[30]	488	1			T31	13		T21	94		T47	46
bite[31]	295	1			T21	42		T131	30		T101	21
bite_0	5370	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34089

1

T1

17

T2

21

T3

11

auto[1]

3659

1

T3

7

T9

7

T12

7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	463	1			T44	19		T175	28		T206	9
prescale[1]	367	1			T6	9		T207	9		T47	61
prescale[2]	208	1			T44	2		T175	2		T164	19
prescale[3]	293	1			T15	9		T208	9		T43	19
prescale[4]	457	1			T20	32		T44	2		T47	14
prescale[5]	556	1			T47	2		T117	89		T91	70
prescale[6]	346	1			T41	2		T44	54		T47	68
prescale[7]	270	1			T47	2		T117	28		T175	2
prescale[8]	677	1			T85	9		T117	85		T91	118
prescale[9]	473	1			T22	36		T124	9		T171	2
prescale[10]	310	1			T11	9		T209	9		T93	2
prescale[11]	551	1			T45	2		T46	47		T73	2
prescale[12]	565	1			T42	23		T73	2		T22	46
prescale[13]	454	1			T43	19		T91	77		T149	2
prescale[14]	282	1			T15	2		T43	66		T117	2
prescale[15]	453	1			T210	9		T21	40		T43	47
prescale[16]	441	1			T91	21		T153	134		T74	9
prescale[17]	332	1			T41	2		T45	2		T47	19
prescale[18]	342	1			T14	26		T211	9		T15	42
prescale[19]	609	1			T117	74		T212	9		T156	69
prescale[20]	213	1			T43	2		T91	28		T173	2
prescale[21]	480	1			T46	26		T47	21		T156	2
prescale[22]	552	1			T11	40		T43	21		T91	106
prescale[23]	472	1			T41	21		T44	73		T45	2
prescale[24]	441	1			T15	19		T213	9		T47	57
prescale[25]	300	1			T91	9		T73	2		T156	71
prescale[26]	640	1			T11	9		T49	9		T15	37
prescale[27]	493	1			T47	2		T175	204		T164	23
prescale[28]	729	1			T11	36		T44	2		T47	66
prescale[29]	585	1			T44	70		T117	45		T214	9
prescale[30]	722	1			T41	98		T91	9		T171	61
prescale[31]	256	1			T42	2		T44	2		T215	9
prescale_0	23416	1			T1	17		T2	21		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25997

1

T1

17

T2

9

T3

9

auto[1]

11751

1

T2

12

T3

9

T4

12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

37748

1

T1

17

T2

21

T3

18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	20822	1			T1	12		T2	1		T3	13
wkup[1]	92	1			T117	21		T131	8		T92	21
wkup[2]	207	1			T32	15		T20	21		T171	21
wkup[3]	230	1			T15	21		T47	21		T164	21
wkup[4]	192	1			T41	30		T91	42		T124	21
wkup[5]	181	1			T41	15		T46	6		T47	21
wkup[6]	259	1			T41	21		T47	15		T180	15
wkup[7]	316	1			T14	6		T81	15		T83	15
wkup[8]	206	1			T14	21		T44	21		T22	21
wkup[9]	304	1			T20	30		T21	21		T124	21
wkup[10]	292	1			T27	15		T33	15		T15	21
wkup[11]	219	1			T44	21		T45	31		T101	21
wkup[12]	364	1			T91	44		T137	27		T95	39
wkup[13]	177	1			T11	21		T48	15		T192	15
wkup[14]	233	1			T47	21		T180	21		T131	21
wkup[15]	223	1			T170	15		T15	8		T42	8
wkup[16]	69	1			T75	21		T158	27		T120	21
wkup[17]	126	1			T125	21		T194	15		T92	42
wkup[18]	65	1			T15	8		T91	21		T198	15
wkup[19]	140	1			T11	21		T20	21		T131	21
wkup[20]	219	1			T117	42		T91	30		T149	21
wkup[21]	123	1			T31	15		T108	15		T22	15
wkup[22]	168	1			T47	21		T117	21		T165	21
wkup[23]	189	1			T47	15		T153	21		T139	15
wkup[24]	201	1			T11	21		T28	15		T22	21
wkup[25]	222	1			T14	21		T185	15		T130	21
wkup[26]	156	1			T4	15		T156	21		T171	21
wkup[27]	171	1			T132	15		T182	15		T95	46
wkup[28]	261	1			T44	51		T117	21		T22	26
wkup[29]	361	1			T11	21		T47	21		T156	47
wkup[30]	300	1			T14	8		T45	21		T117	42
wkup[31]	184	1			T15	21		T44	21		T117	21
wkup[32]	300	1			T14	30		T91	26		T130	15
wkup[33]	219	1			T41	21		T126	15		T117	21
wkup[34]	168	1			T140	15		T102	40		T151	8
wkup[35]	306	1			T91	26		T164	21		T129	30
wkup[36]	263	1			T41	21		T42	8		T47	27
wkup[37]	203	1			T117	21		T149	21		T174	21
wkup[38]	197	1			T129	26		T101	21		T127	24
wkup[39]	176	1			T7	15		T44	35		T130	21
wkup[40]	163	1			T91	42		T186	15		T149	8
wkup[41]	275	1			T91	39		T173	21		T129	21
wkup[42]	282	1			T117	21		T91	42		T131	21
wkup[43]	197	1			T47	21		T149	21		T178	15
wkup[44]	128	1			T47	21		T124	30		T115	15
wkup[45]	194	1			T21	21		T44	21		T175	42
wkup[46]	156	1			T15	21		T21	21		T91	21
wkup[47]	233	1			T21	21		T173	6		T129	40
wkup[48]	236	1			T42	21		T46	21		T47	21
wkup[49]	92	1			T41	21		T129	8		T77	21
wkup[50]	189	1			T156	21		T149	6		T95	21
wkup[51]	197	1			T41	21		T44	21		T153	21
wkup[52]	194	1			T43	8		T119	26		T165	42
wkup[53]	186	1			T166	15		T43	21		T137	21
wkup[54]	86	1			T2	15		T195	15		T135	21
wkup[55]	183	1			T191	15		T165	42		T110	21
wkup[56]	165	1			T197	15		T86	15		T156	21
wkup[57]	228	1			T26	15		T21	21		T124	21
wkup[58]	276	1			T21	21		T117	21		T175	21
wkup[59]	256	1			T10	15		T43	15		T117	26
wkup[60]	251	1			T143	15		T124	30		T171	21
wkup[61]	237	1			T44	15		T91	21		T129	21
wkup[62]	285	1			T146	15		T21	21		T137	21
wkup[63]	177	1			T41	21		T47	21		T171	21
wkup_0	3778	1			T1	5		T2	5		T3	5